1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef EVERGREEND_H 25 #define EVERGREEND_H 26 27 #define EVERGREEN_MAX_SH_GPRS 256 28 #define EVERGREEN_MAX_TEMP_GPRS 16 29 #define EVERGREEN_MAX_SH_THREADS 256 30 #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 31 #define EVERGREEN_MAX_FRC_EOV_CNT 16384 32 #define EVERGREEN_MAX_BACKENDS 8 33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF 34 #define EVERGREEN_MAX_SIMDS 16 35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF 36 #define EVERGREEN_MAX_PIPES 8 37 #define EVERGREEN_MAX_PIPES_MASK 0xFF 38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF 39 40 #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003 41 #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003 42 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 43 #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002 44 #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002 45 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 46 #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 47 #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 48 49 /* Registers */ 50 51 #define RCU_IND_INDEX 0x100 52 #define RCU_IND_DATA 0x104 53 54 #define GRBM_GFX_INDEX 0x802C 55 #define INSTANCE_INDEX(x) ((x) << 0) 56 #define SE_INDEX(x) ((x) << 16) 57 #define INSTANCE_BROADCAST_WRITES (1 << 30) 58 #define SE_BROADCAST_WRITES (1 << 31) 59 #define RLC_GFX_INDEX 0x3fC4 60 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 61 #define WRITE_DIS (1 << 0) 62 #define CC_RB_BACKEND_DISABLE 0x98F4 63 #define BACKEND_DISABLE(x) ((x) << 16) 64 #define GB_ADDR_CONFIG 0x98F8 65 #define NUM_PIPES(x) ((x) << 0) 66 #define NUM_PIPES_MASK 0x0000000f 67 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 68 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 69 #define NUM_SHADER_ENGINES(x) ((x) << 12) 70 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 71 #define NUM_GPUS(x) ((x) << 20) 72 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 73 #define ROW_SIZE(x) ((x) << 28) 74 #define GB_BACKEND_MAP 0x98FC 75 #define DMIF_ADDR_CONFIG 0xBD4 76 #define HDP_ADDR_CONFIG 0x2F48 77 #define HDP_MISC_CNTL 0x2F4C 78 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 79 80 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 81 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 82 83 #define CGTS_SYS_TCC_DISABLE 0x3F90 84 #define CGTS_TCC_DISABLE 0x9148 85 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 86 #define CGTS_USER_TCC_DISABLE 0x914C 87 88 #define CONFIG_MEMSIZE 0x5428 89 90 #define BIF_FB_EN 0x5490 91 #define FB_READ_EN (1 << 0) 92 #define FB_WRITE_EN (1 << 1) 93 94 #define CP_COHER_BASE 0x85F8 95 #define CP_STALLED_STAT1 0x8674 96 #define CP_STALLED_STAT2 0x8678 97 #define CP_BUSY_STAT 0x867C 98 #define CP_STAT 0x8680 99 #define CP_ME_CNTL 0x86D8 100 #define CP_ME_HALT (1 << 28) 101 #define CP_PFP_HALT (1 << 26) 102 #define CP_ME_RAM_DATA 0xC160 103 #define CP_ME_RAM_RADDR 0xC158 104 #define CP_ME_RAM_WADDR 0xC15C 105 #define CP_MEQ_THRESHOLDS 0x8764 106 #define STQ_SPLIT(x) ((x) << 0) 107 #define CP_PERFMON_CNTL 0x87FC 108 #define CP_PFP_UCODE_ADDR 0xC150 109 #define CP_PFP_UCODE_DATA 0xC154 110 #define CP_QUEUE_THRESHOLDS 0x8760 111 #define ROQ_IB1_START(x) ((x) << 0) 112 #define ROQ_IB2_START(x) ((x) << 8) 113 #define CP_RB_BASE 0xC100 114 #define CP_RB_CNTL 0xC104 115 #define RB_BUFSZ(x) ((x) << 0) 116 #define RB_BLKSZ(x) ((x) << 8) 117 #define RB_NO_UPDATE (1 << 27) 118 #define RB_RPTR_WR_ENA (1 << 31) 119 #define BUF_SWAP_32BIT (2 << 16) 120 #define CP_RB_RPTR 0x8700 121 #define CP_RB_RPTR_ADDR 0xC10C 122 #define RB_RPTR_SWAP(x) ((x) << 0) 123 #define CP_RB_RPTR_ADDR_HI 0xC110 124 #define CP_RB_RPTR_WR 0xC108 125 #define CP_RB_WPTR 0xC114 126 #define CP_RB_WPTR_ADDR 0xC118 127 #define CP_RB_WPTR_ADDR_HI 0xC11C 128 #define CP_RB_WPTR_DELAY 0x8704 129 #define CP_SEM_WAIT_TIMER 0x85BC 130 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 131 #define CP_DEBUG 0xC1FC 132 133 /* Audio clocks */ 134 #define DCCG_AUDIO_DTO_SOURCE 0x05ac 135 # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ 136 # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */ 137 138 #define DCCG_AUDIO_DTO0_PHASE 0x05b0 139 #define DCCG_AUDIO_DTO0_MODULE 0x05b4 140 #define DCCG_AUDIO_DTO0_LOAD 0x05b8 141 #define DCCG_AUDIO_DTO0_CNTL 0x05bc 142 143 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 144 #define DCCG_AUDIO_DTO1_MODULE 0x05c4 145 #define DCCG_AUDIO_DTO1_LOAD 0x05c8 146 #define DCCG_AUDIO_DTO1_CNTL 0x05cc 147 148 /* DCE 4.0 AFMT */ 149 #define HDMI_CONTROL 0x7030 150 # define HDMI_KEEPOUT_MODE (1 << 0) 151 # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ 152 # define HDMI_ERROR_ACK (1 << 8) 153 # define HDMI_ERROR_MASK (1 << 9) 154 # define HDMI_DEEP_COLOR_ENABLE (1 << 24) 155 # define HDMI_DEEP_COLOR_DEPTH (((x) & 3) << 28) 156 # define HDMI_24BIT_DEEP_COLOR 0 157 # define HDMI_30BIT_DEEP_COLOR 1 158 # define HDMI_36BIT_DEEP_COLOR 2 159 #define HDMI_STATUS 0x7034 160 # define HDMI_ACTIVE_AVMUTE (1 << 0) 161 # define HDMI_AUDIO_PACKET_ERROR (1 << 16) 162 # define HDMI_VBI_PACKET_ERROR (1 << 20) 163 #define HDMI_AUDIO_PACKET_CONTROL 0x7038 164 # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 165 # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 166 #define HDMI_ACR_PACKET_CONTROL 0x703c 167 # define HDMI_ACR_SEND (1 << 0) 168 # define HDMI_ACR_CONT (1 << 1) 169 # define HDMI_ACR_SELECT(x) (((x) & 3) << 4) 170 # define HDMI_ACR_HW 0 171 # define HDMI_ACR_32 1 172 # define HDMI_ACR_44 2 173 # define HDMI_ACR_48 3 174 # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 175 # define HDMI_ACR_AUTO_SEND (1 << 12) 176 # define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16) 177 # define HDMI_ACR_X1 1 178 # define HDMI_ACR_X2 2 179 # define HDMI_ACR_X4 4 180 # define HDMI_ACR_AUDIO_PRIORITY (1 << 31) 181 #define HDMI_VBI_PACKET_CONTROL 0x7040 182 # define HDMI_NULL_SEND (1 << 0) 183 # define HDMI_GC_SEND (1 << 4) 184 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 185 #define HDMI_INFOFRAME_CONTROL0 0x7044 186 # define HDMI_AVI_INFO_SEND (1 << 0) 187 # define HDMI_AVI_INFO_CONT (1 << 1) 188 # define HDMI_AUDIO_INFO_SEND (1 << 4) 189 # define HDMI_AUDIO_INFO_CONT (1 << 5) 190 # define HDMI_MPEG_INFO_SEND (1 << 8) 191 # define HDMI_MPEG_INFO_CONT (1 << 9) 192 #define HDMI_INFOFRAME_CONTROL1 0x7048 193 # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 194 # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 195 # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 196 #define HDMI_GENERIC_PACKET_CONTROL 0x704c 197 # define HDMI_GENERIC0_SEND (1 << 0) 198 # define HDMI_GENERIC0_CONT (1 << 1) 199 # define HDMI_GENERIC1_SEND (1 << 4) 200 # define HDMI_GENERIC1_CONT (1 << 5) 201 # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 202 # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 203 #define HDMI_GC 0x7058 204 # define HDMI_GC_AVMUTE (1 << 0) 205 # define HDMI_GC_AVMUTE_CONT (1 << 2) 206 #define AFMT_AUDIO_PACKET_CONTROL2 0x705c 207 # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) 208 # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) 209 # define AFMT_60958_CS_SOURCE (1 << 4) 210 # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) 211 # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) 212 #define AFMT_AVI_INFO0 0x7084 213 # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 214 # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) 215 # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) 216 # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) 217 # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) 218 # define AFMT_AVI_INFO_Y_RGB 0 219 # define AFMT_AVI_INFO_Y_YCBCR422 1 220 # define AFMT_AVI_INFO_Y_YCBCR444 2 221 # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 222 # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) 223 # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) 224 # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) 225 # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 226 # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) 227 # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) 228 # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) 229 # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) 230 # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 231 #define AFMT_AVI_INFO1 0x7088 232 # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 233 # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 234 # define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12) 235 # define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14) 236 # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 237 #define AFMT_AVI_INFO2 0x708c 238 # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 239 # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 240 #define AFMT_AVI_INFO3 0x7090 241 # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 242 # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) 243 #define AFMT_MPEG_INFO0 0x7094 244 # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 245 # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 246 # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 247 # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 248 #define AFMT_MPEG_INFO1 0x7098 249 # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 250 # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) 251 # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) 252 #define AFMT_GENERIC0_HDR 0x709c 253 #define AFMT_GENERIC0_0 0x70a0 254 #define AFMT_GENERIC0_1 0x70a4 255 #define AFMT_GENERIC0_2 0x70a8 256 #define AFMT_GENERIC0_3 0x70ac 257 #define AFMT_GENERIC0_4 0x70b0 258 #define AFMT_GENERIC0_5 0x70b4 259 #define AFMT_GENERIC0_6 0x70b8 260 #define AFMT_GENERIC1_HDR 0x70bc 261 #define AFMT_GENERIC1_0 0x70c0 262 #define AFMT_GENERIC1_1 0x70c4 263 #define AFMT_GENERIC1_2 0x70c8 264 #define AFMT_GENERIC1_3 0x70cc 265 #define AFMT_GENERIC1_4 0x70d0 266 #define AFMT_GENERIC1_5 0x70d4 267 #define AFMT_GENERIC1_6 0x70d8 268 #define HDMI_ACR_32_0 0x70dc 269 # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 270 #define HDMI_ACR_32_1 0x70e0 271 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) 272 #define HDMI_ACR_44_0 0x70e4 273 # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 274 #define HDMI_ACR_44_1 0x70e8 275 # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) 276 #define HDMI_ACR_48_0 0x70ec 277 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 278 #define HDMI_ACR_48_1 0x70f0 279 # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) 280 #define HDMI_ACR_STATUS_0 0x70f4 281 #define HDMI_ACR_STATUS_1 0x70f8 282 #define AFMT_AUDIO_INFO0 0x70fc 283 # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 284 # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) 285 # define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11) 286 # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) 287 # define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24) 288 #define AFMT_AUDIO_INFO1 0x7100 289 # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 290 # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 291 # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 292 # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 293 # define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16) 294 #define AFMT_60958_0 0x7104 295 # define AFMT_60958_CS_A(x) (((x) & 1) << 0) 296 # define AFMT_60958_CS_B(x) (((x) & 1) << 1) 297 # define AFMT_60958_CS_C(x) (((x) & 1) << 2) 298 # define AFMT_60958_CS_D(x) (((x) & 3) << 3) 299 # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) 300 # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 301 # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 302 # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 303 # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 304 # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 305 #define AFMT_60958_1 0x7108 306 # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 307 # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 308 # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) 309 # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) 310 # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 311 #define AFMT_AUDIO_CRC_CONTROL 0x710c 312 # define AFMT_AUDIO_CRC_EN (1 << 0) 313 #define AFMT_RAMP_CONTROL0 0x7110 314 # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 315 # define AFMT_RAMP_DATA_SIGN (1 << 31) 316 #define AFMT_RAMP_CONTROL1 0x7114 317 # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 318 # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) 319 #define AFMT_RAMP_CONTROL2 0x7118 320 # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 321 #define AFMT_RAMP_CONTROL3 0x711c 322 # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 323 #define AFMT_60958_2 0x7120 324 # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 325 # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 326 # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 327 # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 328 # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 329 # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 330 #define AFMT_STATUS 0x7128 331 # define AFMT_AUDIO_ENABLE (1 << 4) 332 # define AFMT_AUDIO_HBR_ENABLE (1 << 8) 333 # define AFMT_AZ_FORMAT_WTRIG (1 << 28) 334 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 335 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 336 #define AFMT_AUDIO_PACKET_CONTROL 0x712c 337 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 338 # define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */ 339 # define AFMT_AUDIO_TEST_EN (1 << 12) 340 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 341 # define AFMT_60958_CS_UPDATE (1 << 26) 342 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 343 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 344 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 345 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 346 #define AFMT_VBI_PACKET_CONTROL 0x7130 347 # define AFMT_GENERIC0_UPDATE (1 << 2) 348 #define AFMT_INFOFRAME_CONTROL0 0x7134 349 # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */ 350 # define AFMT_AUDIO_INFO_UPDATE (1 << 7) 351 # define AFMT_MPEG_INFO_UPDATE (1 << 10) 352 #define AFMT_GENERIC0_7 0x7138 353 354 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 355 #define INACTIVE_QD_PIPES(x) ((x) << 8) 356 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 357 #define INACTIVE_SIMDS(x) ((x) << 16) 358 #define INACTIVE_SIMDS_MASK 0x00FF0000 359 360 #define GRBM_CNTL 0x8000 361 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 362 #define GRBM_SOFT_RESET 0x8020 363 #define SOFT_RESET_CP (1 << 0) 364 #define SOFT_RESET_CB (1 << 1) 365 #define SOFT_RESET_DB (1 << 3) 366 #define SOFT_RESET_PA (1 << 5) 367 #define SOFT_RESET_SC (1 << 6) 368 #define SOFT_RESET_SPI (1 << 8) 369 #define SOFT_RESET_SH (1 << 9) 370 #define SOFT_RESET_SX (1 << 10) 371 #define SOFT_RESET_TC (1 << 11) 372 #define SOFT_RESET_TA (1 << 12) 373 #define SOFT_RESET_VC (1 << 13) 374 #define SOFT_RESET_VGT (1 << 14) 375 376 #define GRBM_STATUS 0x8010 377 #define CMDFIFO_AVAIL_MASK 0x0000000F 378 #define SRBM_RQ_PENDING (1 << 5) 379 #define CF_RQ_PENDING (1 << 7) 380 #define PF_RQ_PENDING (1 << 8) 381 #define GRBM_EE_BUSY (1 << 10) 382 #define SX_CLEAN (1 << 11) 383 #define DB_CLEAN (1 << 12) 384 #define CB_CLEAN (1 << 13) 385 #define TA_BUSY (1 << 14) 386 #define VGT_BUSY_NO_DMA (1 << 16) 387 #define VGT_BUSY (1 << 17) 388 #define SX_BUSY (1 << 20) 389 #define SH_BUSY (1 << 21) 390 #define SPI_BUSY (1 << 22) 391 #define SC_BUSY (1 << 24) 392 #define PA_BUSY (1 << 25) 393 #define DB_BUSY (1 << 26) 394 #define CP_COHERENCY_BUSY (1 << 28) 395 #define CP_BUSY (1 << 29) 396 #define CB_BUSY (1 << 30) 397 #define GUI_ACTIVE (1 << 31) 398 #define GRBM_STATUS_SE0 0x8014 399 #define GRBM_STATUS_SE1 0x8018 400 #define SE_SX_CLEAN (1 << 0) 401 #define SE_DB_CLEAN (1 << 1) 402 #define SE_CB_CLEAN (1 << 2) 403 #define SE_TA_BUSY (1 << 25) 404 #define SE_SX_BUSY (1 << 26) 405 #define SE_SPI_BUSY (1 << 27) 406 #define SE_SH_BUSY (1 << 28) 407 #define SE_SC_BUSY (1 << 29) 408 #define SE_DB_BUSY (1 << 30) 409 #define SE_CB_BUSY (1 << 31) 410 /* evergreen */ 411 #define CG_THERMAL_CTRL 0x72c 412 #define TOFFSET_MASK 0x00003FE0 413 #define TOFFSET_SHIFT 5 414 #define CG_MULT_THERMAL_STATUS 0x740 415 #define ASIC_T(x) ((x) << 16) 416 #define ASIC_T_MASK 0x07FF0000 417 #define ASIC_T_SHIFT 16 418 #define CG_TS0_STATUS 0x760 419 #define TS0_ADC_DOUT_MASK 0x000003FF 420 #define TS0_ADC_DOUT_SHIFT 0 421 /* APU */ 422 #define CG_THERMAL_STATUS 0x678 423 424 #define HDP_HOST_PATH_CNTL 0x2C00 425 #define HDP_NONSURFACE_BASE 0x2C04 426 #define HDP_NONSURFACE_INFO 0x2C08 427 #define HDP_NONSURFACE_SIZE 0x2C0C 428 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 429 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 430 #define HDP_TILING_CONFIG 0x2F3C 431 432 #define MC_SHARED_CHMAP 0x2004 433 #define NOOFCHAN_SHIFT 12 434 #define NOOFCHAN_MASK 0x00003000 435 #define MC_SHARED_CHREMAP 0x2008 436 437 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 438 #define BLACKOUT_MODE_MASK 0x00000007 439 440 #define MC_ARB_RAMCFG 0x2760 441 #define NOOFBANK_SHIFT 0 442 #define NOOFBANK_MASK 0x00000003 443 #define NOOFRANK_SHIFT 2 444 #define NOOFRANK_MASK 0x00000004 445 #define NOOFROWS_SHIFT 3 446 #define NOOFROWS_MASK 0x00000038 447 #define NOOFCOLS_SHIFT 6 448 #define NOOFCOLS_MASK 0x000000C0 449 #define CHANSIZE_SHIFT 8 450 #define CHANSIZE_MASK 0x00000100 451 #define BURSTLENGTH_SHIFT 9 452 #define BURSTLENGTH_MASK 0x00000200 453 #define CHANSIZE_OVERRIDE (1 << 11) 454 #define FUS_MC_ARB_RAMCFG 0x2768 455 #define MC_VM_AGP_TOP 0x2028 456 #define MC_VM_AGP_BOT 0x202C 457 #define MC_VM_AGP_BASE 0x2030 458 #define MC_VM_FB_LOCATION 0x2024 459 #define MC_FUS_VM_FB_OFFSET 0x2898 460 #define MC_VM_MB_L1_TLB0_CNTL 0x2234 461 #define MC_VM_MB_L1_TLB1_CNTL 0x2238 462 #define MC_VM_MB_L1_TLB2_CNTL 0x223C 463 #define MC_VM_MB_L1_TLB3_CNTL 0x2240 464 #define ENABLE_L1_TLB (1 << 0) 465 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 466 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 467 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 468 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 469 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 470 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 471 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 472 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 473 #define MC_VM_MD_L1_TLB0_CNTL 0x2654 474 #define MC_VM_MD_L1_TLB1_CNTL 0x2658 475 #define MC_VM_MD_L1_TLB2_CNTL 0x265C 476 #define MC_VM_MD_L1_TLB3_CNTL 0x2698 477 478 #define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C 479 #define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660 480 #define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664 481 482 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 483 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 484 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 485 486 #define PA_CL_ENHANCE 0x8A14 487 #define CLIP_VTX_REORDER_ENA (1 << 0) 488 #define NUM_CLIP_SEQ(x) ((x) << 1) 489 #define PA_SC_ENHANCE 0x8BF0 490 #define PA_SC_AA_CONFIG 0x28C04 491 #define MSAA_NUM_SAMPLES_SHIFT 0 492 #define MSAA_NUM_SAMPLES_MASK 0x3 493 #define PA_SC_CLIPRECT_RULE 0x2820C 494 #define PA_SC_EDGERULE 0x28230 495 #define PA_SC_FIFO_SIZE 0x8BCC 496 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 497 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 498 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 499 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 500 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 501 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 502 #define PA_SC_LINE_STIPPLE 0x28A0C 503 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 504 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 505 506 #define SCRATCH_REG0 0x8500 507 #define SCRATCH_REG1 0x8504 508 #define SCRATCH_REG2 0x8508 509 #define SCRATCH_REG3 0x850C 510 #define SCRATCH_REG4 0x8510 511 #define SCRATCH_REG5 0x8514 512 #define SCRATCH_REG6 0x8518 513 #define SCRATCH_REG7 0x851C 514 #define SCRATCH_UMSK 0x8540 515 #define SCRATCH_ADDR 0x8544 516 517 #define SMX_SAR_CTL0 0xA008 518 #define SMX_DC_CTL0 0xA020 519 #define USE_HASH_FUNCTION (1 << 0) 520 #define NUMBER_OF_SETS(x) ((x) << 1) 521 #define FLUSH_ALL_ON_EVENT (1 << 10) 522 #define STALL_ON_EVENT (1 << 11) 523 #define SMX_EVENT_CTL 0xA02C 524 #define ES_FLUSH_CTL(x) ((x) << 0) 525 #define GS_FLUSH_CTL(x) ((x) << 3) 526 #define ACK_FLUSH_CTL(x) ((x) << 6) 527 #define SYNC_FLUSH_CTL (1 << 8) 528 529 #define SPI_CONFIG_CNTL 0x9100 530 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 531 #define SPI_CONFIG_CNTL_1 0x913C 532 #define VTX_DONE_DELAY(x) ((x) << 0) 533 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 534 #define SPI_INPUT_Z 0x286D8 535 #define SPI_PS_IN_CONTROL_0 0x286CC 536 #define NUM_INTERP(x) ((x)<<0) 537 #define POSITION_ENA (1<<8) 538 #define POSITION_CENTROID (1<<9) 539 #define POSITION_ADDR(x) ((x)<<10) 540 #define PARAM_GEN(x) ((x)<<15) 541 #define PARAM_GEN_ADDR(x) ((x)<<19) 542 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 543 #define PERSP_GRADIENT_ENA (1<<28) 544 #define LINEAR_GRADIENT_ENA (1<<29) 545 #define POSITION_SAMPLE (1<<30) 546 #define BARYC_AT_SAMPLE_ENA (1<<31) 547 548 #define SQ_CONFIG 0x8C00 549 #define VC_ENABLE (1 << 0) 550 #define EXPORT_SRC_C (1 << 1) 551 #define CS_PRIO(x) ((x) << 18) 552 #define LS_PRIO(x) ((x) << 20) 553 #define HS_PRIO(x) ((x) << 22) 554 #define PS_PRIO(x) ((x) << 24) 555 #define VS_PRIO(x) ((x) << 26) 556 #define GS_PRIO(x) ((x) << 28) 557 #define ES_PRIO(x) ((x) << 30) 558 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 559 #define NUM_PS_GPRS(x) ((x) << 0) 560 #define NUM_VS_GPRS(x) ((x) << 16) 561 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 562 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 563 #define NUM_GS_GPRS(x) ((x) << 0) 564 #define NUM_ES_GPRS(x) ((x) << 16) 565 #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C 566 #define NUM_HS_GPRS(x) ((x) << 0) 567 #define NUM_LS_GPRS(x) ((x) << 16) 568 #define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10 569 #define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14 570 #define SQ_THREAD_RESOURCE_MGMT 0x8C18 571 #define NUM_PS_THREADS(x) ((x) << 0) 572 #define NUM_VS_THREADS(x) ((x) << 8) 573 #define NUM_GS_THREADS(x) ((x) << 16) 574 #define NUM_ES_THREADS(x) ((x) << 24) 575 #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C 576 #define NUM_HS_THREADS(x) ((x) << 0) 577 #define NUM_LS_THREADS(x) ((x) << 8) 578 #define SQ_STACK_RESOURCE_MGMT_1 0x8C20 579 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 580 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 581 #define SQ_STACK_RESOURCE_MGMT_2 0x8C24 582 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 583 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 584 #define SQ_STACK_RESOURCE_MGMT_3 0x8C28 585 #define NUM_HS_STACK_ENTRIES(x) ((x) << 0) 586 #define NUM_LS_STACK_ENTRIES(x) ((x) << 16) 587 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 588 #define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94 589 #define SQ_STATIC_THREAD_MGMT_1 0x8E20 590 #define SQ_STATIC_THREAD_MGMT_2 0x8E24 591 #define SQ_STATIC_THREAD_MGMT_3 0x8E28 592 #define SQ_LDS_RESOURCE_MGMT 0x8E2C 593 594 #define SQ_MS_FIFO_SIZES 0x8CF0 595 #define CACHE_FIFO_SIZE(x) ((x) << 0) 596 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 597 #define DONE_FIFO_HIWATER(x) ((x) << 16) 598 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 599 600 #define SX_DEBUG_1 0x9058 601 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 602 #define SX_EXPORT_BUFFER_SIZES 0x900C 603 #define COLOR_BUFFER_SIZE(x) ((x) << 0) 604 #define POSITION_BUFFER_SIZE(x) ((x) << 8) 605 #define SMX_BUFFER_SIZE(x) ((x) << 16) 606 #define SX_MEMORY_EXPORT_BASE 0x9010 607 #define SX_MISC 0x28350 608 609 #define CB_PERF_CTR0_SEL_0 0x9A20 610 #define CB_PERF_CTR0_SEL_1 0x9A24 611 #define CB_PERF_CTR1_SEL_0 0x9A28 612 #define CB_PERF_CTR1_SEL_1 0x9A2C 613 #define CB_PERF_CTR2_SEL_0 0x9A30 614 #define CB_PERF_CTR2_SEL_1 0x9A34 615 #define CB_PERF_CTR3_SEL_0 0x9A38 616 #define CB_PERF_CTR3_SEL_1 0x9A3C 617 618 #define TA_CNTL_AUX 0x9508 619 #define DISABLE_CUBE_WRAP (1 << 0) 620 #define DISABLE_CUBE_ANISO (1 << 1) 621 #define SYNC_GRADIENT (1 << 24) 622 #define SYNC_WALKER (1 << 25) 623 #define SYNC_ALIGNER (1 << 26) 624 625 #define TCP_CHAN_STEER_LO 0x960c 626 #define TCP_CHAN_STEER_HI 0x9610 627 628 #define VGT_CACHE_INVALIDATION 0x88C4 629 #define CACHE_INVALIDATION(x) ((x) << 0) 630 #define VC_ONLY 0 631 #define TC_ONLY 1 632 #define VC_AND_TC 2 633 #define AUTO_INVLD_EN(x) ((x) << 6) 634 #define NO_AUTO 0 635 #define ES_AUTO 1 636 #define GS_AUTO 2 637 #define ES_AND_GS_AUTO 3 638 #define VGT_GS_VERTEX_REUSE 0x88D4 639 #define VGT_NUM_INSTANCES 0x8974 640 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 641 #define DEALLOC_DIST_MASK 0x0000007F 642 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 643 #define VTX_REUSE_DEPTH_MASK 0x000000FF 644 645 #define VM_CONTEXT0_CNTL 0x1410 646 #define ENABLE_CONTEXT (1 << 0) 647 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 648 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 649 #define VM_CONTEXT1_CNTL 0x1414 650 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 651 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 652 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 653 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 654 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 655 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 656 #define RESPONSE_TYPE_MASK 0x000000F0 657 #define RESPONSE_TYPE_SHIFT 4 658 #define VM_L2_CNTL 0x1400 659 #define ENABLE_L2_CACHE (1 << 0) 660 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 661 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 662 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 663 #define VM_L2_CNTL2 0x1404 664 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 665 #define INVALIDATE_L2_CACHE (1 << 1) 666 #define VM_L2_CNTL3 0x1408 667 #define BANK_SELECT(x) ((x) << 0) 668 #define CACHE_UPDATE_MODE(x) ((x) << 6) 669 #define VM_L2_STATUS 0x140C 670 #define L2_BUSY (1 << 0) 671 672 #define WAIT_UNTIL 0x8040 673 674 #define SRBM_STATUS 0x0E50 675 #define SRBM_SOFT_RESET 0x0E60 676 #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 677 #define SOFT_RESET_BIF (1 << 1) 678 #define SOFT_RESET_CG (1 << 2) 679 #define SOFT_RESET_DC (1 << 5) 680 #define SOFT_RESET_GRBM (1 << 8) 681 #define SOFT_RESET_HDP (1 << 9) 682 #define SOFT_RESET_IH (1 << 10) 683 #define SOFT_RESET_MC (1 << 11) 684 #define SOFT_RESET_RLC (1 << 13) 685 #define SOFT_RESET_ROM (1 << 14) 686 #define SOFT_RESET_SEM (1 << 15) 687 #define SOFT_RESET_VMC (1 << 17) 688 #define SOFT_RESET_TST (1 << 21) 689 #define SOFT_RESET_REGBB (1 << 22) 690 #define SOFT_RESET_ORB (1 << 23) 691 692 /* display watermarks */ 693 #define DC_LB_MEMORY_SPLIT 0x6b0c 694 #define PRIORITY_A_CNT 0x6b18 695 #define PRIORITY_MARK_MASK 0x7fff 696 #define PRIORITY_OFF (1 << 16) 697 #define PRIORITY_ALWAYS_ON (1 << 20) 698 #define PRIORITY_B_CNT 0x6b1c 699 #define PIPE0_ARBITRATION_CONTROL3 0x0bf0 700 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 701 #define PIPE0_LATENCY_CONTROL 0x0bf4 702 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 703 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 704 705 #define IH_RB_CNTL 0x3e00 706 # define IH_RB_ENABLE (1 << 0) 707 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 708 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 709 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 710 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 711 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 712 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 713 #define IH_RB_BASE 0x3e04 714 #define IH_RB_RPTR 0x3e08 715 #define IH_RB_WPTR 0x3e0c 716 # define RB_OVERFLOW (1 << 0) 717 # define WPTR_OFFSET_MASK 0x3fffc 718 #define IH_RB_WPTR_ADDR_HI 0x3e10 719 #define IH_RB_WPTR_ADDR_LO 0x3e14 720 #define IH_CNTL 0x3e18 721 # define ENABLE_INTR (1 << 0) 722 # define IH_MC_SWAP(x) ((x) << 1) 723 # define IH_MC_SWAP_NONE 0 724 # define IH_MC_SWAP_16BIT 1 725 # define IH_MC_SWAP_32BIT 2 726 # define IH_MC_SWAP_64BIT 3 727 # define RPTR_REARM (1 << 4) 728 # define MC_WRREQ_CREDIT(x) ((x) << 15) 729 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 730 731 #define CP_INT_CNTL 0xc124 732 # define CNTX_BUSY_INT_ENABLE (1 << 19) 733 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 734 # define SCRATCH_INT_ENABLE (1 << 25) 735 # define TIME_STAMP_INT_ENABLE (1 << 26) 736 # define IB2_INT_ENABLE (1 << 29) 737 # define IB1_INT_ENABLE (1 << 30) 738 # define RB_INT_ENABLE (1 << 31) 739 #define CP_INT_STATUS 0xc128 740 # define SCRATCH_INT_STAT (1 << 25) 741 # define TIME_STAMP_INT_STAT (1 << 26) 742 # define IB2_INT_STAT (1 << 29) 743 # define IB1_INT_STAT (1 << 30) 744 # define RB_INT_STAT (1 << 31) 745 746 #define GRBM_INT_CNTL 0x8060 747 # define RDERR_INT_ENABLE (1 << 0) 748 # define GUI_IDLE_INT_ENABLE (1 << 19) 749 750 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 751 #define CRTC_STATUS_FRAME_COUNT 0x6e98 752 753 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 754 #define VLINE_STATUS 0x6bb8 755 # define VLINE_OCCURRED (1 << 0) 756 # define VLINE_ACK (1 << 4) 757 # define VLINE_STAT (1 << 12) 758 # define VLINE_INTERRUPT (1 << 16) 759 # define VLINE_INTERRUPT_TYPE (1 << 17) 760 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 761 #define VBLANK_STATUS 0x6bbc 762 # define VBLANK_OCCURRED (1 << 0) 763 # define VBLANK_ACK (1 << 4) 764 # define VBLANK_STAT (1 << 12) 765 # define VBLANK_INTERRUPT (1 << 16) 766 # define VBLANK_INTERRUPT_TYPE (1 << 17) 767 768 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 769 #define INT_MASK 0x6b40 770 # define VBLANK_INT_MASK (1 << 0) 771 # define VLINE_INT_MASK (1 << 4) 772 773 #define DISP_INTERRUPT_STATUS 0x60f4 774 # define LB_D1_VLINE_INTERRUPT (1 << 2) 775 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 776 # define DC_HPD1_INTERRUPT (1 << 17) 777 # define DC_HPD1_RX_INTERRUPT (1 << 18) 778 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 779 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 780 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 781 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 782 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 783 # define LB_D2_VLINE_INTERRUPT (1 << 2) 784 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 785 # define DC_HPD2_INTERRUPT (1 << 17) 786 # define DC_HPD2_RX_INTERRUPT (1 << 18) 787 # define DISP_TIMER_INTERRUPT (1 << 24) 788 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 789 # define LB_D3_VLINE_INTERRUPT (1 << 2) 790 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 791 # define DC_HPD3_INTERRUPT (1 << 17) 792 # define DC_HPD3_RX_INTERRUPT (1 << 18) 793 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 794 # define LB_D4_VLINE_INTERRUPT (1 << 2) 795 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 796 # define DC_HPD4_INTERRUPT (1 << 17) 797 # define DC_HPD4_RX_INTERRUPT (1 << 18) 798 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 799 # define LB_D5_VLINE_INTERRUPT (1 << 2) 800 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 801 # define DC_HPD5_INTERRUPT (1 << 17) 802 # define DC_HPD5_RX_INTERRUPT (1 << 18) 803 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 804 # define LB_D6_VLINE_INTERRUPT (1 << 2) 805 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 806 # define DC_HPD6_INTERRUPT (1 << 17) 807 # define DC_HPD6_RX_INTERRUPT (1 << 18) 808 809 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 810 #define GRPH_INT_STATUS 0x6858 811 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 812 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 813 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 814 #define GRPH_INT_CONTROL 0x685c 815 # define GRPH_PFLIP_INT_MASK (1 << 0) 816 # define GRPH_PFLIP_INT_TYPE (1 << 8) 817 818 #define DACA_AUTODETECT_INT_CONTROL 0x66c8 819 #define DACB_AUTODETECT_INT_CONTROL 0x67c8 820 821 #define DC_HPD1_INT_STATUS 0x601c 822 #define DC_HPD2_INT_STATUS 0x6028 823 #define DC_HPD3_INT_STATUS 0x6034 824 #define DC_HPD4_INT_STATUS 0x6040 825 #define DC_HPD5_INT_STATUS 0x604c 826 #define DC_HPD6_INT_STATUS 0x6058 827 # define DC_HPDx_INT_STATUS (1 << 0) 828 # define DC_HPDx_SENSE (1 << 1) 829 # define DC_HPDx_RX_INT_STATUS (1 << 8) 830 831 #define DC_HPD1_INT_CONTROL 0x6020 832 #define DC_HPD2_INT_CONTROL 0x602c 833 #define DC_HPD3_INT_CONTROL 0x6038 834 #define DC_HPD4_INT_CONTROL 0x6044 835 #define DC_HPD5_INT_CONTROL 0x6050 836 #define DC_HPD6_INT_CONTROL 0x605c 837 # define DC_HPDx_INT_ACK (1 << 0) 838 # define DC_HPDx_INT_POLARITY (1 << 8) 839 # define DC_HPDx_INT_EN (1 << 16) 840 # define DC_HPDx_RX_INT_ACK (1 << 20) 841 # define DC_HPDx_RX_INT_EN (1 << 24) 842 843 #define DC_HPD1_CONTROL 0x6024 844 #define DC_HPD2_CONTROL 0x6030 845 #define DC_HPD3_CONTROL 0x603c 846 #define DC_HPD4_CONTROL 0x6048 847 #define DC_HPD5_CONTROL 0x6054 848 #define DC_HPD6_CONTROL 0x6060 849 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 850 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 851 # define DC_HPDx_EN (1 << 28) 852 853 /* PCIE link stuff */ 854 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 855 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 856 # define LC_LINK_WIDTH_SHIFT 0 857 # define LC_LINK_WIDTH_MASK 0x7 858 # define LC_LINK_WIDTH_X0 0 859 # define LC_LINK_WIDTH_X1 1 860 # define LC_LINK_WIDTH_X2 2 861 # define LC_LINK_WIDTH_X4 3 862 # define LC_LINK_WIDTH_X8 4 863 # define LC_LINK_WIDTH_X16 6 864 # define LC_LINK_WIDTH_RD_SHIFT 4 865 # define LC_LINK_WIDTH_RD_MASK 0x70 866 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 867 # define LC_RECONFIG_NOW (1 << 8) 868 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 869 # define LC_RENEGOTIATE_EN (1 << 10) 870 # define LC_SHORT_RECONFIG_EN (1 << 11) 871 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 872 # define LC_UPCONFIGURE_DIS (1 << 13) 873 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 874 # define LC_GEN2_EN_STRAP (1 << 0) 875 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 876 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 877 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 878 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 879 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 880 # define LC_CURRENT_DATA_RATE (1 << 11) 881 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 882 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 883 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 884 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 885 #define MM_CFGREGS_CNTL 0x544c 886 # define MM_WR_TO_CFG_EN (1 << 3) 887 #define LINK_CNTL2 0x88 /* F0 */ 888 # define TARGET_LINK_SPEED_MASK (0xf << 0) 889 # define SELECTABLE_DEEMPHASIS (1 << 6) 890 891 /* 892 * PM4 893 */ 894 #define PACKET_TYPE0 0 895 #define PACKET_TYPE1 1 896 #define PACKET_TYPE2 2 897 #define PACKET_TYPE3 3 898 899 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 900 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 901 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 902 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 903 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 904 (((reg) >> 2) & 0xFFFF) | \ 905 ((n) & 0x3FFF) << 16) 906 #define CP_PACKET2 0x80000000 907 #define PACKET2_PAD_SHIFT 0 908 #define PACKET2_PAD_MASK (0x3fffffff << 0) 909 910 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 911 912 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 913 (((op) & 0xFF) << 8) | \ 914 ((n) & 0x3FFF) << 16) 915 916 /* Packet 3 types */ 917 #define PACKET3_NOP 0x10 918 #define PACKET3_SET_BASE 0x11 919 #define PACKET3_CLEAR_STATE 0x12 920 #define PACKET3_INDEX_BUFFER_SIZE 0x13 921 #define PACKET3_DISPATCH_DIRECT 0x15 922 #define PACKET3_DISPATCH_INDIRECT 0x16 923 #define PACKET3_INDIRECT_BUFFER_END 0x17 924 #define PACKET3_MODE_CONTROL 0x18 925 #define PACKET3_SET_PREDICATION 0x20 926 #define PACKET3_REG_RMW 0x21 927 #define PACKET3_COND_EXEC 0x22 928 #define PACKET3_PRED_EXEC 0x23 929 #define PACKET3_DRAW_INDIRECT 0x24 930 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 931 #define PACKET3_INDEX_BASE 0x26 932 #define PACKET3_DRAW_INDEX_2 0x27 933 #define PACKET3_CONTEXT_CONTROL 0x28 934 #define PACKET3_DRAW_INDEX_OFFSET 0x29 935 #define PACKET3_INDEX_TYPE 0x2A 936 #define PACKET3_DRAW_INDEX 0x2B 937 #define PACKET3_DRAW_INDEX_AUTO 0x2D 938 #define PACKET3_DRAW_INDEX_IMMD 0x2E 939 #define PACKET3_NUM_INSTANCES 0x2F 940 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 941 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 942 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 943 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 944 #define PACKET3_MEM_SEMAPHORE 0x39 945 #define PACKET3_MPEG_INDEX 0x3A 946 #define PACKET3_COPY_DW 0x3B 947 #define PACKET3_WAIT_REG_MEM 0x3C 948 #define PACKET3_MEM_WRITE 0x3D 949 #define PACKET3_INDIRECT_BUFFER 0x32 950 #define PACKET3_SURFACE_SYNC 0x43 951 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 952 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 953 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 954 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 955 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 956 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 957 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 958 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 959 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 960 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 961 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 962 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 963 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 964 # define PACKET3_FULL_CACHE_ENA (1 << 20) 965 # define PACKET3_TC_ACTION_ENA (1 << 23) 966 # define PACKET3_VC_ACTION_ENA (1 << 24) 967 # define PACKET3_CB_ACTION_ENA (1 << 25) 968 # define PACKET3_DB_ACTION_ENA (1 << 26) 969 # define PACKET3_SH_ACTION_ENA (1 << 27) 970 # define PACKET3_SX_ACTION_ENA (1 << 28) 971 #define PACKET3_ME_INITIALIZE 0x44 972 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 973 #define PACKET3_COND_WRITE 0x45 974 #define PACKET3_EVENT_WRITE 0x46 975 #define PACKET3_EVENT_WRITE_EOP 0x47 976 #define PACKET3_EVENT_WRITE_EOS 0x48 977 #define PACKET3_PREAMBLE_CNTL 0x4A 978 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 979 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 980 #define PACKET3_RB_OFFSET 0x4B 981 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 982 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 983 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E 984 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F 985 #define PACKET3_ONE_REG_WRITE 0x57 986 #define PACKET3_SET_CONFIG_REG 0x68 987 #define PACKET3_SET_CONFIG_REG_START 0x00008000 988 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 989 #define PACKET3_SET_CONTEXT_REG 0x69 990 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 991 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 992 #define PACKET3_SET_ALU_CONST 0x6A 993 /* alu const buffers only; no reg file */ 994 #define PACKET3_SET_BOOL_CONST 0x6B 995 #define PACKET3_SET_BOOL_CONST_START 0x0003a500 996 #define PACKET3_SET_BOOL_CONST_END 0x0003a518 997 #define PACKET3_SET_LOOP_CONST 0x6C 998 #define PACKET3_SET_LOOP_CONST_START 0x0003a200 999 #define PACKET3_SET_LOOP_CONST_END 0x0003a500 1000 #define PACKET3_SET_RESOURCE 0x6D 1001 #define PACKET3_SET_RESOURCE_START 0x00030000 1002 #define PACKET3_SET_RESOURCE_END 0x00038000 1003 #define PACKET3_SET_SAMPLER 0x6E 1004 #define PACKET3_SET_SAMPLER_START 0x0003c000 1005 #define PACKET3_SET_SAMPLER_END 0x0003c600 1006 #define PACKET3_SET_CTL_CONST 0x6F 1007 #define PACKET3_SET_CTL_CONST_START 0x0003cff0 1008 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c 1009 #define PACKET3_SET_RESOURCE_OFFSET 0x70 1010 #define PACKET3_SET_ALU_CONST_VS 0x71 1011 #define PACKET3_SET_ALU_CONST_DI 0x72 1012 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1013 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 1014 #define PACKET3_SET_APPEND_CNT 0x75 1015 1016 #define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c 1017 #define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) 1018 #define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) 1019 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 1020 #define SQ_TEX_VTX_INVALID_BUFFER 0x1 1021 #define SQ_TEX_VTX_VALID_TEXTURE 0x2 1022 #define SQ_TEX_VTX_VALID_BUFFER 0x3 1023 1024 #define VGT_VTX_VECT_EJECT_REG 0x88b0 1025 1026 #define SQ_CONST_MEM_BASE 0x8df8 1027 1028 #define SQ_ESGS_RING_BASE 0x8c40 1029 #define SQ_ESGS_RING_SIZE 0x8c44 1030 #define SQ_GSVS_RING_BASE 0x8c48 1031 #define SQ_GSVS_RING_SIZE 0x8c4c 1032 #define SQ_ESTMP_RING_BASE 0x8c50 1033 #define SQ_ESTMP_RING_SIZE 0x8c54 1034 #define SQ_GSTMP_RING_BASE 0x8c58 1035 #define SQ_GSTMP_RING_SIZE 0x8c5c 1036 #define SQ_VSTMP_RING_BASE 0x8c60 1037 #define SQ_VSTMP_RING_SIZE 0x8c64 1038 #define SQ_PSTMP_RING_BASE 0x8c68 1039 #define SQ_PSTMP_RING_SIZE 0x8c6c 1040 #define SQ_LSTMP_RING_BASE 0x8e10 1041 #define SQ_LSTMP_RING_SIZE 0x8e14 1042 #define SQ_HSTMP_RING_BASE 0x8e18 1043 #define SQ_HSTMP_RING_SIZE 0x8e1c 1044 #define VGT_TF_RING_SIZE 0x8988 1045 1046 #define SQ_ESGS_RING_ITEMSIZE 0x28900 1047 #define SQ_GSVS_RING_ITEMSIZE 0x28904 1048 #define SQ_ESTMP_RING_ITEMSIZE 0x28908 1049 #define SQ_GSTMP_RING_ITEMSIZE 0x2890c 1050 #define SQ_VSTMP_RING_ITEMSIZE 0x28910 1051 #define SQ_PSTMP_RING_ITEMSIZE 0x28914 1052 #define SQ_LSTMP_RING_ITEMSIZE 0x28830 1053 #define SQ_HSTMP_RING_ITEMSIZE 0x28834 1054 1055 #define SQ_GS_VERT_ITEMSIZE 0x2891c 1056 #define SQ_GS_VERT_ITEMSIZE_1 0x28920 1057 #define SQ_GS_VERT_ITEMSIZE_2 0x28924 1058 #define SQ_GS_VERT_ITEMSIZE_3 0x28928 1059 #define SQ_GSVS_RING_OFFSET_1 0x2892c 1060 #define SQ_GSVS_RING_OFFSET_2 0x28930 1061 #define SQ_GSVS_RING_OFFSET_3 0x28934 1062 1063 #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 1064 #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 1065 1066 #define SQ_ALU_CONST_CACHE_PS_0 0x28940 1067 #define SQ_ALU_CONST_CACHE_PS_1 0x28944 1068 #define SQ_ALU_CONST_CACHE_PS_2 0x28948 1069 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c 1070 #define SQ_ALU_CONST_CACHE_PS_4 0x28950 1071 #define SQ_ALU_CONST_CACHE_PS_5 0x28954 1072 #define SQ_ALU_CONST_CACHE_PS_6 0x28958 1073 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c 1074 #define SQ_ALU_CONST_CACHE_PS_8 0x28960 1075 #define SQ_ALU_CONST_CACHE_PS_9 0x28964 1076 #define SQ_ALU_CONST_CACHE_PS_10 0x28968 1077 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c 1078 #define SQ_ALU_CONST_CACHE_PS_12 0x28970 1079 #define SQ_ALU_CONST_CACHE_PS_13 0x28974 1080 #define SQ_ALU_CONST_CACHE_PS_14 0x28978 1081 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c 1082 #define SQ_ALU_CONST_CACHE_VS_0 0x28980 1083 #define SQ_ALU_CONST_CACHE_VS_1 0x28984 1084 #define SQ_ALU_CONST_CACHE_VS_2 0x28988 1085 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c 1086 #define SQ_ALU_CONST_CACHE_VS_4 0x28990 1087 #define SQ_ALU_CONST_CACHE_VS_5 0x28994 1088 #define SQ_ALU_CONST_CACHE_VS_6 0x28998 1089 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c 1090 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 1091 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 1092 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 1093 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac 1094 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 1095 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 1096 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 1097 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc 1098 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 1099 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 1100 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 1101 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc 1102 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 1103 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 1104 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 1105 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc 1106 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 1107 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 1108 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 1109 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec 1110 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 1111 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 1112 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 1113 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc 1114 #define SQ_ALU_CONST_CACHE_HS_0 0x28f00 1115 #define SQ_ALU_CONST_CACHE_HS_1 0x28f04 1116 #define SQ_ALU_CONST_CACHE_HS_2 0x28f08 1117 #define SQ_ALU_CONST_CACHE_HS_3 0x28f0c 1118 #define SQ_ALU_CONST_CACHE_HS_4 0x28f10 1119 #define SQ_ALU_CONST_CACHE_HS_5 0x28f14 1120 #define SQ_ALU_CONST_CACHE_HS_6 0x28f18 1121 #define SQ_ALU_CONST_CACHE_HS_7 0x28f1c 1122 #define SQ_ALU_CONST_CACHE_HS_8 0x28f20 1123 #define SQ_ALU_CONST_CACHE_HS_9 0x28f24 1124 #define SQ_ALU_CONST_CACHE_HS_10 0x28f28 1125 #define SQ_ALU_CONST_CACHE_HS_11 0x28f2c 1126 #define SQ_ALU_CONST_CACHE_HS_12 0x28f30 1127 #define SQ_ALU_CONST_CACHE_HS_13 0x28f34 1128 #define SQ_ALU_CONST_CACHE_HS_14 0x28f38 1129 #define SQ_ALU_CONST_CACHE_HS_15 0x28f3c 1130 #define SQ_ALU_CONST_CACHE_LS_0 0x28f40 1131 #define SQ_ALU_CONST_CACHE_LS_1 0x28f44 1132 #define SQ_ALU_CONST_CACHE_LS_2 0x28f48 1133 #define SQ_ALU_CONST_CACHE_LS_3 0x28f4c 1134 #define SQ_ALU_CONST_CACHE_LS_4 0x28f50 1135 #define SQ_ALU_CONST_CACHE_LS_5 0x28f54 1136 #define SQ_ALU_CONST_CACHE_LS_6 0x28f58 1137 #define SQ_ALU_CONST_CACHE_LS_7 0x28f5c 1138 #define SQ_ALU_CONST_CACHE_LS_8 0x28f60 1139 #define SQ_ALU_CONST_CACHE_LS_9 0x28f64 1140 #define SQ_ALU_CONST_CACHE_LS_10 0x28f68 1141 #define SQ_ALU_CONST_CACHE_LS_11 0x28f6c 1142 #define SQ_ALU_CONST_CACHE_LS_12 0x28f70 1143 #define SQ_ALU_CONST_CACHE_LS_13 0x28f74 1144 #define SQ_ALU_CONST_CACHE_LS_14 0x28f78 1145 #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c 1146 1147 #define PA_SC_SCREEN_SCISSOR_TL 0x28030 1148 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 1149 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 1150 1151 #define VGT_PRIMITIVE_TYPE 0x8958 1152 #define VGT_INDEX_TYPE 0x895C 1153 1154 #define VGT_NUM_INDICES 0x8970 1155 1156 #define VGT_COMPUTE_DIM_X 0x8990 1157 #define VGT_COMPUTE_DIM_Y 0x8994 1158 #define VGT_COMPUTE_DIM_Z 0x8998 1159 #define VGT_COMPUTE_START_X 0x899C 1160 #define VGT_COMPUTE_START_Y 0x89A0 1161 #define VGT_COMPUTE_START_Z 0x89A4 1162 #define VGT_COMPUTE_INDEX 0x89A8 1163 #define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC 1164 #define VGT_HS_OFFCHIP_PARAM 0x89B0 1165 1166 #define DB_DEBUG 0x9830 1167 #define DB_DEBUG2 0x9834 1168 #define DB_DEBUG3 0x9838 1169 #define DB_DEBUG4 0x983C 1170 #define DB_WATERMARKS 0x9854 1171 #define DB_DEPTH_CONTROL 0x28800 1172 #define R_028800_DB_DEPTH_CONTROL 0x028800 1173 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 1174 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 1175 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE 1176 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 1177 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 1178 #define C_028800_Z_ENABLE 0xFFFFFFFD 1179 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 1180 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 1181 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 1182 #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 1183 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 1184 #define C_028800_ZFUNC 0xFFFFFF8F 1185 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 1186 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 1187 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 1188 #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 1189 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 1190 #define C_028800_STENCILFUNC 0xFFFFF8FF 1191 #define V_028800_STENCILFUNC_NEVER 0x00000000 1192 #define V_028800_STENCILFUNC_LESS 0x00000001 1193 #define V_028800_STENCILFUNC_EQUAL 0x00000002 1194 #define V_028800_STENCILFUNC_LEQUAL 0x00000003 1195 #define V_028800_STENCILFUNC_GREATER 0x00000004 1196 #define V_028800_STENCILFUNC_NOTEQUAL 0x00000005 1197 #define V_028800_STENCILFUNC_GEQUAL 0x00000006 1198 #define V_028800_STENCILFUNC_ALWAYS 0x00000007 1199 #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 1200 #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 1201 #define C_028800_STENCILFAIL 0xFFFFC7FF 1202 #define V_028800_STENCIL_KEEP 0x00000000 1203 #define V_028800_STENCIL_ZERO 0x00000001 1204 #define V_028800_STENCIL_REPLACE 0x00000002 1205 #define V_028800_STENCIL_INCR 0x00000003 1206 #define V_028800_STENCIL_DECR 0x00000004 1207 #define V_028800_STENCIL_INVERT 0x00000005 1208 #define V_028800_STENCIL_INCR_WRAP 0x00000006 1209 #define V_028800_STENCIL_DECR_WRAP 0x00000007 1210 #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 1211 #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 1212 #define C_028800_STENCILZPASS 0xFFFE3FFF 1213 #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 1214 #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 1215 #define C_028800_STENCILZFAIL 0xFFF1FFFF 1216 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 1217 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 1218 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF 1219 #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 1220 #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 1221 #define C_028800_STENCILFAIL_BF 0xFC7FFFFF 1222 #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 1223 #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 1224 #define C_028800_STENCILZPASS_BF 0xE3FFFFFF 1225 #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 1226 #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 1227 #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 1228 #define DB_DEPTH_VIEW 0x28008 1229 #define R_028008_DB_DEPTH_VIEW 0x00028008 1230 #define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) 1231 #define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) 1232 #define C_028008_SLICE_START 0xFFFFF800 1233 #define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1234 #define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1235 #define C_028008_SLICE_MAX 0xFF001FFF 1236 #define DB_HTILE_DATA_BASE 0x28014 1237 #define DB_HTILE_SURFACE 0x28abc 1238 #define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0) 1239 #define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 1240 #define C_028ABC_HTILE_WIDTH 0xFFFFFFFE 1241 #define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 1242 #define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 1243 #define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD 1244 #define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1) 1245 #define DB_Z_INFO 0x28040 1246 # define Z_ARRAY_MODE(x) ((x) << 4) 1247 # define DB_TILE_SPLIT(x) (((x) & 0x7) << 8) 1248 # define DB_NUM_BANKS(x) (((x) & 0x3) << 12) 1249 # define DB_BANK_WIDTH(x) (((x) & 0x3) << 16) 1250 # define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1251 # define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1252 #define R_028040_DB_Z_INFO 0x028040 1253 #define S_028040_FORMAT(x) (((x) & 0x3) << 0) 1254 #define G_028040_FORMAT(x) (((x) >> 0) & 0x3) 1255 #define C_028040_FORMAT 0xFFFFFFFC 1256 #define V_028040_Z_INVALID 0x00000000 1257 #define V_028040_Z_16 0x00000001 1258 #define V_028040_Z_24 0x00000002 1259 #define V_028040_Z_32_FLOAT 0x00000003 1260 #define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4) 1261 #define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF) 1262 #define C_028040_ARRAY_MODE 0xFFFFFF0F 1263 #define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) 1264 #define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) 1265 #define C_028040_READ_SIZE 0xEFFFFFFF 1266 #define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) 1267 #define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) 1268 #define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF 1269 #define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1270 #define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1271 #define C_028040_ZRANGE_PRECISION 0x7FFFFFFF 1272 #define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8) 1273 #define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1274 #define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12) 1275 #define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3) 1276 #define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16) 1277 #define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3) 1278 #define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1279 #define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3) 1280 #define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1281 #define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3) 1282 #define DB_STENCIL_INFO 0x28044 1283 #define R_028044_DB_STENCIL_INFO 0x028044 1284 #define S_028044_FORMAT(x) (((x) & 0x1) << 0) 1285 #define G_028044_FORMAT(x) (((x) >> 0) & 0x1) 1286 #define C_028044_FORMAT 0xFFFFFFFE 1287 #define V_028044_STENCIL_INVALID 0 1288 #define V_028044_STENCIL_8 1 1289 #define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1290 #define DB_Z_READ_BASE 0x28048 1291 #define DB_STENCIL_READ_BASE 0x2804c 1292 #define DB_Z_WRITE_BASE 0x28050 1293 #define DB_STENCIL_WRITE_BASE 0x28054 1294 #define DB_DEPTH_SIZE 0x28058 1295 #define R_028058_DB_DEPTH_SIZE 0x028058 1296 #define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) 1297 #define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) 1298 #define C_028058_PITCH_TILE_MAX 0xFFFFF800 1299 #define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) 1300 #define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) 1301 #define C_028058_HEIGHT_TILE_MAX 0xFFC007FF 1302 #define R_02805C_DB_DEPTH_SLICE 0x02805C 1303 #define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) 1304 #define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) 1305 #define C_02805C_SLICE_TILE_MAX 0xFFC00000 1306 1307 #define SQ_PGM_START_PS 0x28840 1308 #define SQ_PGM_START_VS 0x2885c 1309 #define SQ_PGM_START_GS 0x28874 1310 #define SQ_PGM_START_ES 0x2888c 1311 #define SQ_PGM_START_FS 0x288a4 1312 #define SQ_PGM_START_HS 0x288b8 1313 #define SQ_PGM_START_LS 0x288d0 1314 1315 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 1316 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 1317 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 1318 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 1319 #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 1320 #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 1321 #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 1322 #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 1323 #define VGT_STRMOUT_CONFIG 0x28b94 1324 #define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 1325 1326 #define CB_TARGET_MASK 0x28238 1327 #define CB_SHADER_MASK 0x2823c 1328 1329 #define GDS_ADDR_BASE 0x28720 1330 1331 #define CB_IMMED0_BASE 0x28b9c 1332 #define CB_IMMED1_BASE 0x28ba0 1333 #define CB_IMMED2_BASE 0x28ba4 1334 #define CB_IMMED3_BASE 0x28ba8 1335 #define CB_IMMED4_BASE 0x28bac 1336 #define CB_IMMED5_BASE 0x28bb0 1337 #define CB_IMMED6_BASE 0x28bb4 1338 #define CB_IMMED7_BASE 0x28bb8 1339 #define CB_IMMED8_BASE 0x28bbc 1340 #define CB_IMMED9_BASE 0x28bc0 1341 #define CB_IMMED10_BASE 0x28bc4 1342 #define CB_IMMED11_BASE 0x28bc8 1343 1344 /* all 12 CB blocks have these regs */ 1345 #define CB_COLOR0_BASE 0x28c60 1346 #define CB_COLOR0_PITCH 0x28c64 1347 #define CB_COLOR0_SLICE 0x28c68 1348 #define CB_COLOR0_VIEW 0x28c6c 1349 #define R_028C6C_CB_COLOR0_VIEW 0x00028C6C 1350 #define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) 1351 #define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) 1352 #define C_028C6C_SLICE_START 0xFFFFF800 1353 #define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1354 #define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1355 #define C_028C6C_SLICE_MAX 0xFF001FFF 1356 #define R_028C70_CB_COLOR0_INFO 0x028C70 1357 #define S_028C70_ENDIAN(x) (((x) & 0x3) << 0) 1358 #define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3) 1359 #define C_028C70_ENDIAN 0xFFFFFFFC 1360 #define S_028C70_FORMAT(x) (((x) & 0x3F) << 2) 1361 #define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F) 1362 #define C_028C70_FORMAT 0xFFFFFF03 1363 #define V_028C70_COLOR_INVALID 0x00000000 1364 #define V_028C70_COLOR_8 0x00000001 1365 #define V_028C70_COLOR_4_4 0x00000002 1366 #define V_028C70_COLOR_3_3_2 0x00000003 1367 #define V_028C70_COLOR_16 0x00000005 1368 #define V_028C70_COLOR_16_FLOAT 0x00000006 1369 #define V_028C70_COLOR_8_8 0x00000007 1370 #define V_028C70_COLOR_5_6_5 0x00000008 1371 #define V_028C70_COLOR_6_5_5 0x00000009 1372 #define V_028C70_COLOR_1_5_5_5 0x0000000A 1373 #define V_028C70_COLOR_4_4_4_4 0x0000000B 1374 #define V_028C70_COLOR_5_5_5_1 0x0000000C 1375 #define V_028C70_COLOR_32 0x0000000D 1376 #define V_028C70_COLOR_32_FLOAT 0x0000000E 1377 #define V_028C70_COLOR_16_16 0x0000000F 1378 #define V_028C70_COLOR_16_16_FLOAT 0x00000010 1379 #define V_028C70_COLOR_8_24 0x00000011 1380 #define V_028C70_COLOR_8_24_FLOAT 0x00000012 1381 #define V_028C70_COLOR_24_8 0x00000013 1382 #define V_028C70_COLOR_24_8_FLOAT 0x00000014 1383 #define V_028C70_COLOR_10_11_11 0x00000015 1384 #define V_028C70_COLOR_10_11_11_FLOAT 0x00000016 1385 #define V_028C70_COLOR_11_11_10 0x00000017 1386 #define V_028C70_COLOR_11_11_10_FLOAT 0x00000018 1387 #define V_028C70_COLOR_2_10_10_10 0x00000019 1388 #define V_028C70_COLOR_8_8_8_8 0x0000001A 1389 #define V_028C70_COLOR_10_10_10_2 0x0000001B 1390 #define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C 1391 #define V_028C70_COLOR_32_32 0x0000001D 1392 #define V_028C70_COLOR_32_32_FLOAT 0x0000001E 1393 #define V_028C70_COLOR_16_16_16_16 0x0000001F 1394 #define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020 1395 #define V_028C70_COLOR_32_32_32_32 0x00000022 1396 #define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023 1397 #define V_028C70_COLOR_32_32_32_FLOAT 0x00000030 1398 #define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8) 1399 #define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1400 #define C_028C70_ARRAY_MODE 0xFFFFF0FF 1401 #define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000 1402 #define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001 1403 #define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002 1404 #define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004 1405 #define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1406 #define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1407 #define C_028C70_NUMBER_TYPE 0xFFFF8FFF 1408 #define V_028C70_NUMBER_UNORM 0x00000000 1409 #define V_028C70_NUMBER_SNORM 0x00000001 1410 #define V_028C70_NUMBER_USCALED 0x00000002 1411 #define V_028C70_NUMBER_SSCALED 0x00000003 1412 #define V_028C70_NUMBER_UINT 0x00000004 1413 #define V_028C70_NUMBER_SINT 0x00000005 1414 #define V_028C70_NUMBER_SRGB 0x00000006 1415 #define V_028C70_NUMBER_FLOAT 0x00000007 1416 #define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15) 1417 #define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3) 1418 #define C_028C70_COMP_SWAP 0xFFFE7FFF 1419 #define V_028C70_SWAP_STD 0x00000000 1420 #define V_028C70_SWAP_ALT 0x00000001 1421 #define V_028C70_SWAP_STD_REV 0x00000002 1422 #define V_028C70_SWAP_ALT_REV 0x00000003 1423 #define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17) 1424 #define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1) 1425 #define C_028C70_FAST_CLEAR 0xFFFDFFFF 1426 #define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18) 1427 #define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3) 1428 #define C_028C70_COMPRESSION 0xFFF3FFFF 1429 #define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19) 1430 #define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1) 1431 #define C_028C70_BLEND_CLAMP 0xFFF7FFFF 1432 #define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20) 1433 #define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1) 1434 #define C_028C70_BLEND_BYPASS 0xFFEFFFFF 1435 #define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21) 1436 #define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1) 1437 #define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF 1438 #define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22) 1439 #define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1) 1440 #define C_028C70_ROUND_MODE 0xFFBFFFFF 1441 #define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23) 1442 #define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1) 1443 #define C_028C70_TILE_COMPACT 0xFF7FFFFF 1444 #define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24) 1445 #define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3) 1446 #define C_028C70_SOURCE_FORMAT 0xFCFFFFFF 1447 #define V_028C70_EXPORT_4C_32BPC 0x0 1448 #define V_028C70_EXPORT_4C_16BPC 0x1 1449 #define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */ 1450 #define S_028C70_RAT(x) (((x) & 0x1) << 26) 1451 #define G_028C70_RAT(x) (((x) >> 26) & 0x1) 1452 #define C_028C70_RAT 0xFBFFFFFF 1453 #define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27) 1454 #define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7) 1455 #define C_028C70_RESOURCE_TYPE 0xC7FFFFFF 1456 1457 #define CB_COLOR0_INFO 0x28c70 1458 # define CB_FORMAT(x) ((x) << 2) 1459 # define CB_ARRAY_MODE(x) ((x) << 8) 1460 # define ARRAY_LINEAR_GENERAL 0 1461 # define ARRAY_LINEAR_ALIGNED 1 1462 # define ARRAY_1D_TILED_THIN1 2 1463 # define ARRAY_2D_TILED_THIN1 4 1464 # define CB_SOURCE_FORMAT(x) ((x) << 24) 1465 # define CB_SF_EXPORT_FULL 0 1466 # define CB_SF_EXPORT_NORM 1 1467 #define R_028C74_CB_COLOR0_ATTRIB 0x028C74 1468 #define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4) 1469 #define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1) 1470 #define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF 1471 #define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5) 1472 #define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf) 1473 #define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10) 1474 #define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3) 1475 #define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13) 1476 #define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3) 1477 #define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16) 1478 #define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3) 1479 #define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 1480 #define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3) 1481 #define CB_COLOR0_ATTRIB 0x28c74 1482 # define CB_TILE_SPLIT(x) (((x) & 0x7) << 5) 1483 # define ADDR_SURF_TILE_SPLIT_64B 0 1484 # define ADDR_SURF_TILE_SPLIT_128B 1 1485 # define ADDR_SURF_TILE_SPLIT_256B 2 1486 # define ADDR_SURF_TILE_SPLIT_512B 3 1487 # define ADDR_SURF_TILE_SPLIT_1KB 4 1488 # define ADDR_SURF_TILE_SPLIT_2KB 5 1489 # define ADDR_SURF_TILE_SPLIT_4KB 6 1490 # define CB_NUM_BANKS(x) (((x) & 0x3) << 10) 1491 # define ADDR_SURF_2_BANK 0 1492 # define ADDR_SURF_4_BANK 1 1493 # define ADDR_SURF_8_BANK 2 1494 # define ADDR_SURF_16_BANK 3 1495 # define CB_BANK_WIDTH(x) (((x) & 0x3) << 13) 1496 # define ADDR_SURF_BANK_WIDTH_1 0 1497 # define ADDR_SURF_BANK_WIDTH_2 1 1498 # define ADDR_SURF_BANK_WIDTH_4 2 1499 # define ADDR_SURF_BANK_WIDTH_8 3 1500 # define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16) 1501 # define ADDR_SURF_BANK_HEIGHT_1 0 1502 # define ADDR_SURF_BANK_HEIGHT_2 1 1503 # define ADDR_SURF_BANK_HEIGHT_4 2 1504 # define ADDR_SURF_BANK_HEIGHT_8 3 1505 # define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 1506 #define CB_COLOR0_DIM 0x28c78 1507 /* only CB0-7 blocks have these regs */ 1508 #define CB_COLOR0_CMASK 0x28c7c 1509 #define CB_COLOR0_CMASK_SLICE 0x28c80 1510 #define CB_COLOR0_FMASK 0x28c84 1511 #define CB_COLOR0_FMASK_SLICE 0x28c88 1512 #define CB_COLOR0_CLEAR_WORD0 0x28c8c 1513 #define CB_COLOR0_CLEAR_WORD1 0x28c90 1514 #define CB_COLOR0_CLEAR_WORD2 0x28c94 1515 #define CB_COLOR0_CLEAR_WORD3 0x28c98 1516 1517 #define CB_COLOR1_BASE 0x28c9c 1518 #define CB_COLOR2_BASE 0x28cd8 1519 #define CB_COLOR3_BASE 0x28d14 1520 #define CB_COLOR4_BASE 0x28d50 1521 #define CB_COLOR5_BASE 0x28d8c 1522 #define CB_COLOR6_BASE 0x28dc8 1523 #define CB_COLOR7_BASE 0x28e04 1524 #define CB_COLOR8_BASE 0x28e40 1525 #define CB_COLOR9_BASE 0x28e5c 1526 #define CB_COLOR10_BASE 0x28e78 1527 #define CB_COLOR11_BASE 0x28e94 1528 1529 #define CB_COLOR1_PITCH 0x28ca0 1530 #define CB_COLOR2_PITCH 0x28cdc 1531 #define CB_COLOR3_PITCH 0x28d18 1532 #define CB_COLOR4_PITCH 0x28d54 1533 #define CB_COLOR5_PITCH 0x28d90 1534 #define CB_COLOR6_PITCH 0x28dcc 1535 #define CB_COLOR7_PITCH 0x28e08 1536 #define CB_COLOR8_PITCH 0x28e44 1537 #define CB_COLOR9_PITCH 0x28e60 1538 #define CB_COLOR10_PITCH 0x28e7c 1539 #define CB_COLOR11_PITCH 0x28e98 1540 1541 #define CB_COLOR1_SLICE 0x28ca4 1542 #define CB_COLOR2_SLICE 0x28ce0 1543 #define CB_COLOR3_SLICE 0x28d1c 1544 #define CB_COLOR4_SLICE 0x28d58 1545 #define CB_COLOR5_SLICE 0x28d94 1546 #define CB_COLOR6_SLICE 0x28dd0 1547 #define CB_COLOR7_SLICE 0x28e0c 1548 #define CB_COLOR8_SLICE 0x28e48 1549 #define CB_COLOR9_SLICE 0x28e64 1550 #define CB_COLOR10_SLICE 0x28e80 1551 #define CB_COLOR11_SLICE 0x28e9c 1552 1553 #define CB_COLOR1_VIEW 0x28ca8 1554 #define CB_COLOR2_VIEW 0x28ce4 1555 #define CB_COLOR3_VIEW 0x28d20 1556 #define CB_COLOR4_VIEW 0x28d5c 1557 #define CB_COLOR5_VIEW 0x28d98 1558 #define CB_COLOR6_VIEW 0x28dd4 1559 #define CB_COLOR7_VIEW 0x28e10 1560 #define CB_COLOR8_VIEW 0x28e4c 1561 #define CB_COLOR9_VIEW 0x28e68 1562 #define CB_COLOR10_VIEW 0x28e84 1563 #define CB_COLOR11_VIEW 0x28ea0 1564 1565 #define CB_COLOR1_INFO 0x28cac 1566 #define CB_COLOR2_INFO 0x28ce8 1567 #define CB_COLOR3_INFO 0x28d24 1568 #define CB_COLOR4_INFO 0x28d60 1569 #define CB_COLOR5_INFO 0x28d9c 1570 #define CB_COLOR6_INFO 0x28dd8 1571 #define CB_COLOR7_INFO 0x28e14 1572 #define CB_COLOR8_INFO 0x28e50 1573 #define CB_COLOR9_INFO 0x28e6c 1574 #define CB_COLOR10_INFO 0x28e88 1575 #define CB_COLOR11_INFO 0x28ea4 1576 1577 #define CB_COLOR1_ATTRIB 0x28cb0 1578 #define CB_COLOR2_ATTRIB 0x28cec 1579 #define CB_COLOR3_ATTRIB 0x28d28 1580 #define CB_COLOR4_ATTRIB 0x28d64 1581 #define CB_COLOR5_ATTRIB 0x28da0 1582 #define CB_COLOR6_ATTRIB 0x28ddc 1583 #define CB_COLOR7_ATTRIB 0x28e18 1584 #define CB_COLOR8_ATTRIB 0x28e54 1585 #define CB_COLOR9_ATTRIB 0x28e70 1586 #define CB_COLOR10_ATTRIB 0x28e8c 1587 #define CB_COLOR11_ATTRIB 0x28ea8 1588 1589 #define CB_COLOR1_DIM 0x28cb4 1590 #define CB_COLOR2_DIM 0x28cf0 1591 #define CB_COLOR3_DIM 0x28d2c 1592 #define CB_COLOR4_DIM 0x28d68 1593 #define CB_COLOR5_DIM 0x28da4 1594 #define CB_COLOR6_DIM 0x28de0 1595 #define CB_COLOR7_DIM 0x28e1c 1596 #define CB_COLOR8_DIM 0x28e58 1597 #define CB_COLOR9_DIM 0x28e74 1598 #define CB_COLOR10_DIM 0x28e90 1599 #define CB_COLOR11_DIM 0x28eac 1600 1601 #define CB_COLOR1_CMASK 0x28cb8 1602 #define CB_COLOR2_CMASK 0x28cf4 1603 #define CB_COLOR3_CMASK 0x28d30 1604 #define CB_COLOR4_CMASK 0x28d6c 1605 #define CB_COLOR5_CMASK 0x28da8 1606 #define CB_COLOR6_CMASK 0x28de4 1607 #define CB_COLOR7_CMASK 0x28e20 1608 1609 #define CB_COLOR1_CMASK_SLICE 0x28cbc 1610 #define CB_COLOR2_CMASK_SLICE 0x28cf8 1611 #define CB_COLOR3_CMASK_SLICE 0x28d34 1612 #define CB_COLOR4_CMASK_SLICE 0x28d70 1613 #define CB_COLOR5_CMASK_SLICE 0x28dac 1614 #define CB_COLOR6_CMASK_SLICE 0x28de8 1615 #define CB_COLOR7_CMASK_SLICE 0x28e24 1616 1617 #define CB_COLOR1_FMASK 0x28cc0 1618 #define CB_COLOR2_FMASK 0x28cfc 1619 #define CB_COLOR3_FMASK 0x28d38 1620 #define CB_COLOR4_FMASK 0x28d74 1621 #define CB_COLOR5_FMASK 0x28db0 1622 #define CB_COLOR6_FMASK 0x28dec 1623 #define CB_COLOR7_FMASK 0x28e28 1624 1625 #define CB_COLOR1_FMASK_SLICE 0x28cc4 1626 #define CB_COLOR2_FMASK_SLICE 0x28d00 1627 #define CB_COLOR3_FMASK_SLICE 0x28d3c 1628 #define CB_COLOR4_FMASK_SLICE 0x28d78 1629 #define CB_COLOR5_FMASK_SLICE 0x28db4 1630 #define CB_COLOR6_FMASK_SLICE 0x28df0 1631 #define CB_COLOR7_FMASK_SLICE 0x28e2c 1632 1633 #define CB_COLOR1_CLEAR_WORD0 0x28cc8 1634 #define CB_COLOR2_CLEAR_WORD0 0x28d04 1635 #define CB_COLOR3_CLEAR_WORD0 0x28d40 1636 #define CB_COLOR4_CLEAR_WORD0 0x28d7c 1637 #define CB_COLOR5_CLEAR_WORD0 0x28db8 1638 #define CB_COLOR6_CLEAR_WORD0 0x28df4 1639 #define CB_COLOR7_CLEAR_WORD0 0x28e30 1640 1641 #define CB_COLOR1_CLEAR_WORD1 0x28ccc 1642 #define CB_COLOR2_CLEAR_WORD1 0x28d08 1643 #define CB_COLOR3_CLEAR_WORD1 0x28d44 1644 #define CB_COLOR4_CLEAR_WORD1 0x28d80 1645 #define CB_COLOR5_CLEAR_WORD1 0x28dbc 1646 #define CB_COLOR6_CLEAR_WORD1 0x28df8 1647 #define CB_COLOR7_CLEAR_WORD1 0x28e34 1648 1649 #define CB_COLOR1_CLEAR_WORD2 0x28cd0 1650 #define CB_COLOR2_CLEAR_WORD2 0x28d0c 1651 #define CB_COLOR3_CLEAR_WORD2 0x28d48 1652 #define CB_COLOR4_CLEAR_WORD2 0x28d84 1653 #define CB_COLOR5_CLEAR_WORD2 0x28dc0 1654 #define CB_COLOR6_CLEAR_WORD2 0x28dfc 1655 #define CB_COLOR7_CLEAR_WORD2 0x28e38 1656 1657 #define CB_COLOR1_CLEAR_WORD3 0x28cd4 1658 #define CB_COLOR2_CLEAR_WORD3 0x28d10 1659 #define CB_COLOR3_CLEAR_WORD3 0x28d4c 1660 #define CB_COLOR4_CLEAR_WORD3 0x28d88 1661 #define CB_COLOR5_CLEAR_WORD3 0x28dc4 1662 #define CB_COLOR6_CLEAR_WORD3 0x28e00 1663 #define CB_COLOR7_CLEAR_WORD3 0x28e3c 1664 1665 #define SQ_TEX_RESOURCE_WORD0_0 0x30000 1666 # define TEX_DIM(x) ((x) << 0) 1667 # define SQ_TEX_DIM_1D 0 1668 # define SQ_TEX_DIM_2D 1 1669 # define SQ_TEX_DIM_3D 2 1670 # define SQ_TEX_DIM_CUBEMAP 3 1671 # define SQ_TEX_DIM_1D_ARRAY 4 1672 # define SQ_TEX_DIM_2D_ARRAY 5 1673 # define SQ_TEX_DIM_2D_MSAA 6 1674 # define SQ_TEX_DIM_2D_ARRAY_MSAA 7 1675 #define SQ_TEX_RESOURCE_WORD1_0 0x30004 1676 # define TEX_ARRAY_MODE(x) ((x) << 28) 1677 #define SQ_TEX_RESOURCE_WORD2_0 0x30008 1678 #define SQ_TEX_RESOURCE_WORD3_0 0x3000C 1679 #define SQ_TEX_RESOURCE_WORD4_0 0x30010 1680 # define TEX_DST_SEL_X(x) ((x) << 16) 1681 # define TEX_DST_SEL_Y(x) ((x) << 19) 1682 # define TEX_DST_SEL_Z(x) ((x) << 22) 1683 # define TEX_DST_SEL_W(x) ((x) << 25) 1684 # define SQ_SEL_X 0 1685 # define SQ_SEL_Y 1 1686 # define SQ_SEL_Z 2 1687 # define SQ_SEL_W 3 1688 # define SQ_SEL_0 4 1689 # define SQ_SEL_1 5 1690 #define SQ_TEX_RESOURCE_WORD5_0 0x30014 1691 #define SQ_TEX_RESOURCE_WORD6_0 0x30018 1692 # define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29) 1693 #define SQ_TEX_RESOURCE_WORD7_0 0x3001c 1694 # define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 1695 # define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8) 1696 # define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10) 1697 # define TEX_NUM_BANKS(x) (((x) & 0x3) << 16) 1698 #define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000 1699 #define S_030000_DIM(x) (((x) & 0x7) << 0) 1700 #define G_030000_DIM(x) (((x) >> 0) & 0x7) 1701 #define C_030000_DIM 0xFFFFFFF8 1702 #define V_030000_SQ_TEX_DIM_1D 0x00000000 1703 #define V_030000_SQ_TEX_DIM_2D 0x00000001 1704 #define V_030000_SQ_TEX_DIM_3D 0x00000002 1705 #define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003 1706 #define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004 1707 #define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005 1708 #define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006 1709 #define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 1710 #define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5) 1711 #define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1) 1712 #define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF 1713 #define S_030000_PITCH(x) (((x) & 0xFFF) << 6) 1714 #define G_030000_PITCH(x) (((x) >> 6) & 0xFFF) 1715 #define C_030000_PITCH 0xFFFC003F 1716 #define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18) 1717 #define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF) 1718 #define C_030000_TEX_WIDTH 0x0003FFFF 1719 #define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004 1720 #define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0) 1721 #define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF) 1722 #define C_030004_TEX_HEIGHT 0xFFFFC000 1723 #define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14) 1724 #define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF) 1725 #define C_030004_TEX_DEPTH 0xF8003FFF 1726 #define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28) 1727 #define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF) 1728 #define C_030004_ARRAY_MODE 0x0FFFFFFF 1729 #define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008 1730 #define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 1731 #define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 1732 #define C_030008_BASE_ADDRESS 0x00000000 1733 #define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C 1734 #define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 1735 #define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 1736 #define C_03000C_MIP_ADDRESS 0x00000000 1737 #define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010 1738 #define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 1739 #define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 1740 #define C_030010_FORMAT_COMP_X 0xFFFFFFFC 1741 #define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000 1742 #define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001 1743 #define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002 1744 #define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 1745 #define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 1746 #define C_030010_FORMAT_COMP_Y 0xFFFFFFF3 1747 #define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 1748 #define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 1749 #define C_030010_FORMAT_COMP_Z 0xFFFFFFCF 1750 #define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 1751 #define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 1752 #define C_030010_FORMAT_COMP_W 0xFFFFFF3F 1753 #define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 1754 #define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 1755 #define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF 1756 #define V_030010_SQ_NUM_FORMAT_NORM 0x00000000 1757 #define V_030010_SQ_NUM_FORMAT_INT 0x00000001 1758 #define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002 1759 #define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 1760 #define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 1761 #define C_030010_SRF_MODE_ALL 0xFFFFFBFF 1762 #define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000 1763 #define V_030010_SRF_MODE_NO_ZERO 0x00000001 1764 #define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 1765 #define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 1766 #define C_030010_FORCE_DEGAMMA 0xFFFFF7FF 1767 #define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 1768 #define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 1769 #define C_030010_ENDIAN_SWAP 0xFFFFCFFF 1770 #define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16) 1771 #define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7) 1772 #define C_030010_DST_SEL_X 0xFFF8FFFF 1773 #define V_030010_SQ_SEL_X 0x00000000 1774 #define V_030010_SQ_SEL_Y 0x00000001 1775 #define V_030010_SQ_SEL_Z 0x00000002 1776 #define V_030010_SQ_SEL_W 0x00000003 1777 #define V_030010_SQ_SEL_0 0x00000004 1778 #define V_030010_SQ_SEL_1 0x00000005 1779 #define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19) 1780 #define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 1781 #define C_030010_DST_SEL_Y 0xFFC7FFFF 1782 #define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22) 1783 #define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 1784 #define C_030010_DST_SEL_Z 0xFE3FFFFF 1785 #define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25) 1786 #define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7) 1787 #define C_030010_DST_SEL_W 0xF1FFFFFF 1788 #define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28) 1789 #define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 1790 #define C_030010_BASE_LEVEL 0x0FFFFFFF 1791 #define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014 1792 #define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0) 1793 #define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 1794 #define C_030014_LAST_LEVEL 0xFFFFFFF0 1795 #define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 1796 #define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 1797 #define C_030014_BASE_ARRAY 0xFFFE000F 1798 #define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 1799 #define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 1800 #define C_030014_LAST_ARRAY 0xC001FFFF 1801 #define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018 1802 #define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0) 1803 #define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7) 1804 #define C_030018_MAX_ANISO 0xFFFFFFF8 1805 #define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3) 1806 #define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7) 1807 #define C_030018_PERF_MODULATION 0xFFFFFFC7 1808 #define S_030018_INTERLACED(x) (((x) & 0x1) << 6) 1809 #define G_030018_INTERLACED(x) (((x) >> 6) & 0x1) 1810 #define C_030018_INTERLACED 0xFFFFFFBF 1811 #define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29) 1812 #define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7) 1813 #define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C 1814 #define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 1815 #define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3) 1816 #define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8) 1817 #define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3) 1818 #define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10) 1819 #define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3) 1820 #define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16) 1821 #define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3) 1822 #define S_03001C_TYPE(x) (((x) & 0x3) << 30) 1823 #define G_03001C_TYPE(x) (((x) >> 30) & 0x3) 1824 #define C_03001C_TYPE 0x3FFFFFFF 1825 #define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000 1826 #define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001 1827 #define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002 1828 #define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003 1829 #define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0) 1830 #define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F) 1831 #define C_03001C_DATA_FORMAT 0xFFFFFFC0 1832 1833 #define SQ_VTX_CONSTANT_WORD0_0 0x30000 1834 #define SQ_VTX_CONSTANT_WORD1_0 0x30004 1835 #define SQ_VTX_CONSTANT_WORD2_0 0x30008 1836 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 1837 # define SQ_VTXC_STRIDE(x) ((x) << 8) 1838 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 1839 # define SQ_ENDIAN_NONE 0 1840 # define SQ_ENDIAN_8IN16 1 1841 # define SQ_ENDIAN_8IN32 2 1842 #define SQ_VTX_CONSTANT_WORD3_0 0x3000C 1843 # define SQ_VTCX_SEL_X(x) ((x) << 3) 1844 # define SQ_VTCX_SEL_Y(x) ((x) << 6) 1845 # define SQ_VTCX_SEL_Z(x) ((x) << 9) 1846 # define SQ_VTCX_SEL_W(x) ((x) << 12) 1847 #define SQ_VTX_CONSTANT_WORD4_0 0x30010 1848 #define SQ_VTX_CONSTANT_WORD5_0 0x30014 1849 #define SQ_VTX_CONSTANT_WORD6_0 0x30018 1850 #define SQ_VTX_CONSTANT_WORD7_0 0x3001c 1851 1852 #define TD_PS_BORDER_COLOR_INDEX 0xA400 1853 #define TD_PS_BORDER_COLOR_RED 0xA404 1854 #define TD_PS_BORDER_COLOR_GREEN 0xA408 1855 #define TD_PS_BORDER_COLOR_BLUE 0xA40C 1856 #define TD_PS_BORDER_COLOR_ALPHA 0xA410 1857 #define TD_VS_BORDER_COLOR_INDEX 0xA414 1858 #define TD_VS_BORDER_COLOR_RED 0xA418 1859 #define TD_VS_BORDER_COLOR_GREEN 0xA41C 1860 #define TD_VS_BORDER_COLOR_BLUE 0xA420 1861 #define TD_VS_BORDER_COLOR_ALPHA 0xA424 1862 #define TD_GS_BORDER_COLOR_INDEX 0xA428 1863 #define TD_GS_BORDER_COLOR_RED 0xA42C 1864 #define TD_GS_BORDER_COLOR_GREEN 0xA430 1865 #define TD_GS_BORDER_COLOR_BLUE 0xA434 1866 #define TD_GS_BORDER_COLOR_ALPHA 0xA438 1867 #define TD_HS_BORDER_COLOR_INDEX 0xA43C 1868 #define TD_HS_BORDER_COLOR_RED 0xA440 1869 #define TD_HS_BORDER_COLOR_GREEN 0xA444 1870 #define TD_HS_BORDER_COLOR_BLUE 0xA448 1871 #define TD_HS_BORDER_COLOR_ALPHA 0xA44C 1872 #define TD_LS_BORDER_COLOR_INDEX 0xA450 1873 #define TD_LS_BORDER_COLOR_RED 0xA454 1874 #define TD_LS_BORDER_COLOR_GREEN 0xA458 1875 #define TD_LS_BORDER_COLOR_BLUE 0xA45C 1876 #define TD_LS_BORDER_COLOR_ALPHA 0xA460 1877 #define TD_CS_BORDER_COLOR_INDEX 0xA464 1878 #define TD_CS_BORDER_COLOR_RED 0xA468 1879 #define TD_CS_BORDER_COLOR_GREEN 0xA46C 1880 #define TD_CS_BORDER_COLOR_BLUE 0xA470 1881 #define TD_CS_BORDER_COLOR_ALPHA 0xA474 1882 1883 /* cayman 3D regs */ 1884 #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4 1885 #define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48 1886 #define CAYMAN_DB_EQAA 0x28804 1887 #define CAYMAN_DB_DEPTH_INFO 0x2803C 1888 #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 1889 #define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 1890 #define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 1891 #define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 1892 /* cayman packet3 addition */ 1893 #define CAYMAN_PACKET3_DEALLOC_STATE 0x14 1894 1895 #endif 1896