1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef EVERGREEND_H 25 #define EVERGREEND_H 26 27 #define EVERGREEN_MAX_SH_GPRS 256 28 #define EVERGREEN_MAX_TEMP_GPRS 16 29 #define EVERGREEN_MAX_SH_THREADS 256 30 #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 31 #define EVERGREEN_MAX_FRC_EOV_CNT 16384 32 #define EVERGREEN_MAX_BACKENDS 8 33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF 34 #define EVERGREEN_MAX_SIMDS 16 35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF 36 #define EVERGREEN_MAX_PIPES 8 37 #define EVERGREEN_MAX_PIPES_MASK 0xFF 38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF 39 40 #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003 41 #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003 42 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 43 #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002 44 #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002 45 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 46 #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 47 #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 48 49 /* Registers */ 50 51 #define RCU_IND_INDEX 0x100 52 #define RCU_IND_DATA 0x104 53 54 #define GRBM_GFX_INDEX 0x802C 55 #define INSTANCE_INDEX(x) ((x) << 0) 56 #define SE_INDEX(x) ((x) << 16) 57 #define INSTANCE_BROADCAST_WRITES (1 << 30) 58 #define SE_BROADCAST_WRITES (1 << 31) 59 #define RLC_GFX_INDEX 0x3fC4 60 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 61 #define WRITE_DIS (1 << 0) 62 #define CC_RB_BACKEND_DISABLE 0x98F4 63 #define BACKEND_DISABLE(x) ((x) << 16) 64 #define GB_ADDR_CONFIG 0x98F8 65 #define NUM_PIPES(x) ((x) << 0) 66 #define NUM_PIPES_MASK 0x0000000f 67 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 68 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 69 #define NUM_SHADER_ENGINES(x) ((x) << 12) 70 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 71 #define NUM_GPUS(x) ((x) << 20) 72 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 73 #define ROW_SIZE(x) ((x) << 28) 74 #define GB_BACKEND_MAP 0x98FC 75 #define DMIF_ADDR_CONFIG 0xBD4 76 #define HDP_ADDR_CONFIG 0x2F48 77 #define HDP_MISC_CNTL 0x2F4C 78 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 79 80 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88 81 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 82 83 #define CGTS_SYS_TCC_DISABLE 0x3F90 84 #define CGTS_TCC_DISABLE 0x9148 85 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94 86 #define CGTS_USER_TCC_DISABLE 0x914C 87 88 #define CONFIG_MEMSIZE 0x5428 89 90 #define BIF_FB_EN 0x5490 91 #define FB_READ_EN (1 << 0) 92 #define FB_WRITE_EN (1 << 1) 93 94 #define CP_STRMOUT_CNTL 0x84FC 95 96 #define CP_COHER_CNTL 0x85F0 97 #define CP_COHER_SIZE 0x85F4 98 #define CP_COHER_BASE 0x85F8 99 #define CP_STALLED_STAT1 0x8674 100 #define CP_STALLED_STAT2 0x8678 101 #define CP_BUSY_STAT 0x867C 102 #define CP_STAT 0x8680 103 #define CP_ME_CNTL 0x86D8 104 #define CP_ME_HALT (1 << 28) 105 #define CP_PFP_HALT (1 << 26) 106 #define CP_ME_RAM_DATA 0xC160 107 #define CP_ME_RAM_RADDR 0xC158 108 #define CP_ME_RAM_WADDR 0xC15C 109 #define CP_MEQ_THRESHOLDS 0x8764 110 #define STQ_SPLIT(x) ((x) << 0) 111 #define CP_PERFMON_CNTL 0x87FC 112 #define CP_PFP_UCODE_ADDR 0xC150 113 #define CP_PFP_UCODE_DATA 0xC154 114 #define CP_QUEUE_THRESHOLDS 0x8760 115 #define ROQ_IB1_START(x) ((x) << 0) 116 #define ROQ_IB2_START(x) ((x) << 8) 117 #define CP_RB_BASE 0xC100 118 #define CP_RB_CNTL 0xC104 119 #define RB_BUFSZ(x) ((x) << 0) 120 #define RB_BLKSZ(x) ((x) << 8) 121 #define RB_NO_UPDATE (1 << 27) 122 #define RB_RPTR_WR_ENA (1 << 31) 123 #define BUF_SWAP_32BIT (2 << 16) 124 #define CP_RB_RPTR 0x8700 125 #define CP_RB_RPTR_ADDR 0xC10C 126 #define RB_RPTR_SWAP(x) ((x) << 0) 127 #define CP_RB_RPTR_ADDR_HI 0xC110 128 #define CP_RB_RPTR_WR 0xC108 129 #define CP_RB_WPTR 0xC114 130 #define CP_RB_WPTR_ADDR 0xC118 131 #define CP_RB_WPTR_ADDR_HI 0xC11C 132 #define CP_RB_WPTR_DELAY 0x8704 133 #define CP_SEM_WAIT_TIMER 0x85BC 134 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 135 #define CP_DEBUG 0xC1FC 136 137 /* Audio clocks */ 138 #define DCCG_AUDIO_DTO_SOURCE 0x05ac 139 # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ 140 # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */ 141 142 #define DCCG_AUDIO_DTO0_PHASE 0x05b0 143 #define DCCG_AUDIO_DTO0_MODULE 0x05b4 144 #define DCCG_AUDIO_DTO0_LOAD 0x05b8 145 #define DCCG_AUDIO_DTO0_CNTL 0x05bc 146 147 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 148 #define DCCG_AUDIO_DTO1_MODULE 0x05c4 149 #define DCCG_AUDIO_DTO1_LOAD 0x05c8 150 #define DCCG_AUDIO_DTO1_CNTL 0x05cc 151 152 /* DCE 4.0 AFMT */ 153 #define HDMI_CONTROL 0x7030 154 # define HDMI_KEEPOUT_MODE (1 << 0) 155 # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ 156 # define HDMI_ERROR_ACK (1 << 8) 157 # define HDMI_ERROR_MASK (1 << 9) 158 # define HDMI_DEEP_COLOR_ENABLE (1 << 24) 159 # define HDMI_DEEP_COLOR_DEPTH (((x) & 3) << 28) 160 # define HDMI_24BIT_DEEP_COLOR 0 161 # define HDMI_30BIT_DEEP_COLOR 1 162 # define HDMI_36BIT_DEEP_COLOR 2 163 #define HDMI_STATUS 0x7034 164 # define HDMI_ACTIVE_AVMUTE (1 << 0) 165 # define HDMI_AUDIO_PACKET_ERROR (1 << 16) 166 # define HDMI_VBI_PACKET_ERROR (1 << 20) 167 #define HDMI_AUDIO_PACKET_CONTROL 0x7038 168 # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 169 # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 170 #define HDMI_ACR_PACKET_CONTROL 0x703c 171 # define HDMI_ACR_SEND (1 << 0) 172 # define HDMI_ACR_CONT (1 << 1) 173 # define HDMI_ACR_SELECT(x) (((x) & 3) << 4) 174 # define HDMI_ACR_HW 0 175 # define HDMI_ACR_32 1 176 # define HDMI_ACR_44 2 177 # define HDMI_ACR_48 3 178 # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 179 # define HDMI_ACR_AUTO_SEND (1 << 12) 180 # define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16) 181 # define HDMI_ACR_X1 1 182 # define HDMI_ACR_X2 2 183 # define HDMI_ACR_X4 4 184 # define HDMI_ACR_AUDIO_PRIORITY (1 << 31) 185 #define HDMI_VBI_PACKET_CONTROL 0x7040 186 # define HDMI_NULL_SEND (1 << 0) 187 # define HDMI_GC_SEND (1 << 4) 188 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 189 #define HDMI_INFOFRAME_CONTROL0 0x7044 190 # define HDMI_AVI_INFO_SEND (1 << 0) 191 # define HDMI_AVI_INFO_CONT (1 << 1) 192 # define HDMI_AUDIO_INFO_SEND (1 << 4) 193 # define HDMI_AUDIO_INFO_CONT (1 << 5) 194 # define HDMI_MPEG_INFO_SEND (1 << 8) 195 # define HDMI_MPEG_INFO_CONT (1 << 9) 196 #define HDMI_INFOFRAME_CONTROL1 0x7048 197 # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 198 # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 199 # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 200 #define HDMI_GENERIC_PACKET_CONTROL 0x704c 201 # define HDMI_GENERIC0_SEND (1 << 0) 202 # define HDMI_GENERIC0_CONT (1 << 1) 203 # define HDMI_GENERIC1_SEND (1 << 4) 204 # define HDMI_GENERIC1_CONT (1 << 5) 205 # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 206 # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 207 #define HDMI_GC 0x7058 208 # define HDMI_GC_AVMUTE (1 << 0) 209 # define HDMI_GC_AVMUTE_CONT (1 << 2) 210 #define AFMT_AUDIO_PACKET_CONTROL2 0x705c 211 # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) 212 # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) 213 # define AFMT_60958_CS_SOURCE (1 << 4) 214 # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) 215 # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) 216 #define AFMT_AVI_INFO0 0x7084 217 # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 218 # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) 219 # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) 220 # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) 221 # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) 222 # define AFMT_AVI_INFO_Y_RGB 0 223 # define AFMT_AVI_INFO_Y_YCBCR422 1 224 # define AFMT_AVI_INFO_Y_YCBCR444 2 225 # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 226 # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) 227 # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) 228 # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) 229 # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 230 # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) 231 # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) 232 # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) 233 # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) 234 # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 235 #define AFMT_AVI_INFO1 0x7088 236 # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 237 # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 238 # define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12) 239 # define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14) 240 # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 241 #define AFMT_AVI_INFO2 0x708c 242 # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 243 # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 244 #define AFMT_AVI_INFO3 0x7090 245 # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 246 # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) 247 #define AFMT_MPEG_INFO0 0x7094 248 # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 249 # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 250 # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 251 # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 252 #define AFMT_MPEG_INFO1 0x7098 253 # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 254 # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) 255 # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) 256 #define AFMT_GENERIC0_HDR 0x709c 257 #define AFMT_GENERIC0_0 0x70a0 258 #define AFMT_GENERIC0_1 0x70a4 259 #define AFMT_GENERIC0_2 0x70a8 260 #define AFMT_GENERIC0_3 0x70ac 261 #define AFMT_GENERIC0_4 0x70b0 262 #define AFMT_GENERIC0_5 0x70b4 263 #define AFMT_GENERIC0_6 0x70b8 264 #define AFMT_GENERIC1_HDR 0x70bc 265 #define AFMT_GENERIC1_0 0x70c0 266 #define AFMT_GENERIC1_1 0x70c4 267 #define AFMT_GENERIC1_2 0x70c8 268 #define AFMT_GENERIC1_3 0x70cc 269 #define AFMT_GENERIC1_4 0x70d0 270 #define AFMT_GENERIC1_5 0x70d4 271 #define AFMT_GENERIC1_6 0x70d8 272 #define HDMI_ACR_32_0 0x70dc 273 # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 274 #define HDMI_ACR_32_1 0x70e0 275 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) 276 #define HDMI_ACR_44_0 0x70e4 277 # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 278 #define HDMI_ACR_44_1 0x70e8 279 # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) 280 #define HDMI_ACR_48_0 0x70ec 281 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 282 #define HDMI_ACR_48_1 0x70f0 283 # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) 284 #define HDMI_ACR_STATUS_0 0x70f4 285 #define HDMI_ACR_STATUS_1 0x70f8 286 #define AFMT_AUDIO_INFO0 0x70fc 287 # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 288 # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) 289 # define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11) 290 # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) 291 # define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24) 292 #define AFMT_AUDIO_INFO1 0x7100 293 # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 294 # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 295 # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 296 # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 297 # define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16) 298 #define AFMT_60958_0 0x7104 299 # define AFMT_60958_CS_A(x) (((x) & 1) << 0) 300 # define AFMT_60958_CS_B(x) (((x) & 1) << 1) 301 # define AFMT_60958_CS_C(x) (((x) & 1) << 2) 302 # define AFMT_60958_CS_D(x) (((x) & 3) << 3) 303 # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) 304 # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 305 # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 306 # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 307 # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 308 # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 309 #define AFMT_60958_1 0x7108 310 # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 311 # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 312 # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) 313 # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) 314 # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 315 #define AFMT_AUDIO_CRC_CONTROL 0x710c 316 # define AFMT_AUDIO_CRC_EN (1 << 0) 317 #define AFMT_RAMP_CONTROL0 0x7110 318 # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 319 # define AFMT_RAMP_DATA_SIGN (1 << 31) 320 #define AFMT_RAMP_CONTROL1 0x7114 321 # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 322 # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) 323 #define AFMT_RAMP_CONTROL2 0x7118 324 # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 325 #define AFMT_RAMP_CONTROL3 0x711c 326 # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 327 #define AFMT_60958_2 0x7120 328 # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 329 # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 330 # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 331 # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 332 # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 333 # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 334 #define AFMT_STATUS 0x7128 335 # define AFMT_AUDIO_ENABLE (1 << 4) 336 # define AFMT_AUDIO_HBR_ENABLE (1 << 8) 337 # define AFMT_AZ_FORMAT_WTRIG (1 << 28) 338 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 339 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 340 #define AFMT_AUDIO_PACKET_CONTROL 0x712c 341 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 342 # define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */ 343 # define AFMT_AUDIO_TEST_EN (1 << 12) 344 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 345 # define AFMT_60958_CS_UPDATE (1 << 26) 346 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 347 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 348 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 349 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 350 #define AFMT_VBI_PACKET_CONTROL 0x7130 351 # define AFMT_GENERIC0_UPDATE (1 << 2) 352 #define AFMT_INFOFRAME_CONTROL0 0x7134 353 # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */ 354 # define AFMT_AUDIO_INFO_UPDATE (1 << 7) 355 # define AFMT_MPEG_INFO_UPDATE (1 << 10) 356 #define AFMT_GENERIC0_7 0x7138 357 358 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 359 #define INACTIVE_QD_PIPES(x) ((x) << 8) 360 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 361 #define INACTIVE_SIMDS(x) ((x) << 16) 362 #define INACTIVE_SIMDS_MASK 0x00FF0000 363 364 #define GRBM_CNTL 0x8000 365 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 366 #define GRBM_SOFT_RESET 0x8020 367 #define SOFT_RESET_CP (1 << 0) 368 #define SOFT_RESET_CB (1 << 1) 369 #define SOFT_RESET_DB (1 << 3) 370 #define SOFT_RESET_PA (1 << 5) 371 #define SOFT_RESET_SC (1 << 6) 372 #define SOFT_RESET_SPI (1 << 8) 373 #define SOFT_RESET_SH (1 << 9) 374 #define SOFT_RESET_SX (1 << 10) 375 #define SOFT_RESET_TC (1 << 11) 376 #define SOFT_RESET_TA (1 << 12) 377 #define SOFT_RESET_VC (1 << 13) 378 #define SOFT_RESET_VGT (1 << 14) 379 380 #define GRBM_STATUS 0x8010 381 #define CMDFIFO_AVAIL_MASK 0x0000000F 382 #define SRBM_RQ_PENDING (1 << 5) 383 #define CF_RQ_PENDING (1 << 7) 384 #define PF_RQ_PENDING (1 << 8) 385 #define GRBM_EE_BUSY (1 << 10) 386 #define SX_CLEAN (1 << 11) 387 #define DB_CLEAN (1 << 12) 388 #define CB_CLEAN (1 << 13) 389 #define TA_BUSY (1 << 14) 390 #define VGT_BUSY_NO_DMA (1 << 16) 391 #define VGT_BUSY (1 << 17) 392 #define SX_BUSY (1 << 20) 393 #define SH_BUSY (1 << 21) 394 #define SPI_BUSY (1 << 22) 395 #define SC_BUSY (1 << 24) 396 #define PA_BUSY (1 << 25) 397 #define DB_BUSY (1 << 26) 398 #define CP_COHERENCY_BUSY (1 << 28) 399 #define CP_BUSY (1 << 29) 400 #define CB_BUSY (1 << 30) 401 #define GUI_ACTIVE (1 << 31) 402 #define GRBM_STATUS_SE0 0x8014 403 #define GRBM_STATUS_SE1 0x8018 404 #define SE_SX_CLEAN (1 << 0) 405 #define SE_DB_CLEAN (1 << 1) 406 #define SE_CB_CLEAN (1 << 2) 407 #define SE_TA_BUSY (1 << 25) 408 #define SE_SX_BUSY (1 << 26) 409 #define SE_SPI_BUSY (1 << 27) 410 #define SE_SH_BUSY (1 << 28) 411 #define SE_SC_BUSY (1 << 29) 412 #define SE_DB_BUSY (1 << 30) 413 #define SE_CB_BUSY (1 << 31) 414 /* evergreen */ 415 #define CG_THERMAL_CTRL 0x72c 416 #define TOFFSET_MASK 0x00003FE0 417 #define TOFFSET_SHIFT 5 418 #define CG_MULT_THERMAL_STATUS 0x740 419 #define ASIC_T(x) ((x) << 16) 420 #define ASIC_T_MASK 0x07FF0000 421 #define ASIC_T_SHIFT 16 422 #define CG_TS0_STATUS 0x760 423 #define TS0_ADC_DOUT_MASK 0x000003FF 424 #define TS0_ADC_DOUT_SHIFT 0 425 /* APU */ 426 #define CG_THERMAL_STATUS 0x678 427 428 #define HDP_HOST_PATH_CNTL 0x2C00 429 #define HDP_NONSURFACE_BASE 0x2C04 430 #define HDP_NONSURFACE_INFO 0x2C08 431 #define HDP_NONSURFACE_SIZE 0x2C0C 432 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 433 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 434 #define HDP_TILING_CONFIG 0x2F3C 435 436 #define MC_SHARED_CHMAP 0x2004 437 #define NOOFCHAN_SHIFT 12 438 #define NOOFCHAN_MASK 0x00003000 439 #define MC_SHARED_CHREMAP 0x2008 440 441 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 442 #define BLACKOUT_MODE_MASK 0x00000007 443 444 #define MC_ARB_RAMCFG 0x2760 445 #define NOOFBANK_SHIFT 0 446 #define NOOFBANK_MASK 0x00000003 447 #define NOOFRANK_SHIFT 2 448 #define NOOFRANK_MASK 0x00000004 449 #define NOOFROWS_SHIFT 3 450 #define NOOFROWS_MASK 0x00000038 451 #define NOOFCOLS_SHIFT 6 452 #define NOOFCOLS_MASK 0x000000C0 453 #define CHANSIZE_SHIFT 8 454 #define CHANSIZE_MASK 0x00000100 455 #define BURSTLENGTH_SHIFT 9 456 #define BURSTLENGTH_MASK 0x00000200 457 #define CHANSIZE_OVERRIDE (1 << 11) 458 #define FUS_MC_ARB_RAMCFG 0x2768 459 #define MC_VM_AGP_TOP 0x2028 460 #define MC_VM_AGP_BOT 0x202C 461 #define MC_VM_AGP_BASE 0x2030 462 #define MC_VM_FB_LOCATION 0x2024 463 #define MC_FUS_VM_FB_OFFSET 0x2898 464 #define MC_VM_MB_L1_TLB0_CNTL 0x2234 465 #define MC_VM_MB_L1_TLB1_CNTL 0x2238 466 #define MC_VM_MB_L1_TLB2_CNTL 0x223C 467 #define MC_VM_MB_L1_TLB3_CNTL 0x2240 468 #define ENABLE_L1_TLB (1 << 0) 469 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 470 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 471 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 472 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 473 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 474 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 475 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 476 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 477 #define MC_VM_MD_L1_TLB0_CNTL 0x2654 478 #define MC_VM_MD_L1_TLB1_CNTL 0x2658 479 #define MC_VM_MD_L1_TLB2_CNTL 0x265C 480 #define MC_VM_MD_L1_TLB3_CNTL 0x2698 481 482 #define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C 483 #define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660 484 #define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664 485 486 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 487 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 488 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 489 490 #define PA_CL_ENHANCE 0x8A14 491 #define CLIP_VTX_REORDER_ENA (1 << 0) 492 #define NUM_CLIP_SEQ(x) ((x) << 1) 493 #define PA_SC_ENHANCE 0x8BF0 494 #define PA_SC_AA_CONFIG 0x28C04 495 #define MSAA_NUM_SAMPLES_SHIFT 0 496 #define MSAA_NUM_SAMPLES_MASK 0x3 497 #define PA_SC_CLIPRECT_RULE 0x2820C 498 #define PA_SC_EDGERULE 0x28230 499 #define PA_SC_FIFO_SIZE 0x8BCC 500 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 501 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 502 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 503 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 504 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 505 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 506 #define PA_SC_LINE_STIPPLE 0x28A0C 507 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 508 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 509 510 #define SCRATCH_REG0 0x8500 511 #define SCRATCH_REG1 0x8504 512 #define SCRATCH_REG2 0x8508 513 #define SCRATCH_REG3 0x850C 514 #define SCRATCH_REG4 0x8510 515 #define SCRATCH_REG5 0x8514 516 #define SCRATCH_REG6 0x8518 517 #define SCRATCH_REG7 0x851C 518 #define SCRATCH_UMSK 0x8540 519 #define SCRATCH_ADDR 0x8544 520 521 #define SMX_SAR_CTL0 0xA008 522 #define SMX_DC_CTL0 0xA020 523 #define USE_HASH_FUNCTION (1 << 0) 524 #define NUMBER_OF_SETS(x) ((x) << 1) 525 #define FLUSH_ALL_ON_EVENT (1 << 10) 526 #define STALL_ON_EVENT (1 << 11) 527 #define SMX_EVENT_CTL 0xA02C 528 #define ES_FLUSH_CTL(x) ((x) << 0) 529 #define GS_FLUSH_CTL(x) ((x) << 3) 530 #define ACK_FLUSH_CTL(x) ((x) << 6) 531 #define SYNC_FLUSH_CTL (1 << 8) 532 533 #define SPI_CONFIG_CNTL 0x9100 534 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 535 #define SPI_CONFIG_CNTL_1 0x913C 536 #define VTX_DONE_DELAY(x) ((x) << 0) 537 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 538 #define SPI_INPUT_Z 0x286D8 539 #define SPI_PS_IN_CONTROL_0 0x286CC 540 #define NUM_INTERP(x) ((x)<<0) 541 #define POSITION_ENA (1<<8) 542 #define POSITION_CENTROID (1<<9) 543 #define POSITION_ADDR(x) ((x)<<10) 544 #define PARAM_GEN(x) ((x)<<15) 545 #define PARAM_GEN_ADDR(x) ((x)<<19) 546 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 547 #define PERSP_GRADIENT_ENA (1<<28) 548 #define LINEAR_GRADIENT_ENA (1<<29) 549 #define POSITION_SAMPLE (1<<30) 550 #define BARYC_AT_SAMPLE_ENA (1<<31) 551 552 #define SQ_CONFIG 0x8C00 553 #define VC_ENABLE (1 << 0) 554 #define EXPORT_SRC_C (1 << 1) 555 #define CS_PRIO(x) ((x) << 18) 556 #define LS_PRIO(x) ((x) << 20) 557 #define HS_PRIO(x) ((x) << 22) 558 #define PS_PRIO(x) ((x) << 24) 559 #define VS_PRIO(x) ((x) << 26) 560 #define GS_PRIO(x) ((x) << 28) 561 #define ES_PRIO(x) ((x) << 30) 562 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04 563 #define NUM_PS_GPRS(x) ((x) << 0) 564 #define NUM_VS_GPRS(x) ((x) << 16) 565 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 566 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08 567 #define NUM_GS_GPRS(x) ((x) << 0) 568 #define NUM_ES_GPRS(x) ((x) << 16) 569 #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C 570 #define NUM_HS_GPRS(x) ((x) << 0) 571 #define NUM_LS_GPRS(x) ((x) << 16) 572 #define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10 573 #define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14 574 #define SQ_THREAD_RESOURCE_MGMT 0x8C18 575 #define NUM_PS_THREADS(x) ((x) << 0) 576 #define NUM_VS_THREADS(x) ((x) << 8) 577 #define NUM_GS_THREADS(x) ((x) << 16) 578 #define NUM_ES_THREADS(x) ((x) << 24) 579 #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C 580 #define NUM_HS_THREADS(x) ((x) << 0) 581 #define NUM_LS_THREADS(x) ((x) << 8) 582 #define SQ_STACK_RESOURCE_MGMT_1 0x8C20 583 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 584 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 585 #define SQ_STACK_RESOURCE_MGMT_2 0x8C24 586 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 587 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 588 #define SQ_STACK_RESOURCE_MGMT_3 0x8C28 589 #define NUM_HS_STACK_ENTRIES(x) ((x) << 0) 590 #define NUM_LS_STACK_ENTRIES(x) ((x) << 16) 591 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 592 #define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94 593 #define SQ_STATIC_THREAD_MGMT_1 0x8E20 594 #define SQ_STATIC_THREAD_MGMT_2 0x8E24 595 #define SQ_STATIC_THREAD_MGMT_3 0x8E28 596 #define SQ_LDS_RESOURCE_MGMT 0x8E2C 597 598 #define SQ_MS_FIFO_SIZES 0x8CF0 599 #define CACHE_FIFO_SIZE(x) ((x) << 0) 600 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 601 #define DONE_FIFO_HIWATER(x) ((x) << 16) 602 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 603 604 #define SX_DEBUG_1 0x9058 605 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 606 #define SX_EXPORT_BUFFER_SIZES 0x900C 607 #define COLOR_BUFFER_SIZE(x) ((x) << 0) 608 #define POSITION_BUFFER_SIZE(x) ((x) << 8) 609 #define SMX_BUFFER_SIZE(x) ((x) << 16) 610 #define SX_MEMORY_EXPORT_BASE 0x9010 611 #define SX_MISC 0x28350 612 613 #define CB_PERF_CTR0_SEL_0 0x9A20 614 #define CB_PERF_CTR0_SEL_1 0x9A24 615 #define CB_PERF_CTR1_SEL_0 0x9A28 616 #define CB_PERF_CTR1_SEL_1 0x9A2C 617 #define CB_PERF_CTR2_SEL_0 0x9A30 618 #define CB_PERF_CTR2_SEL_1 0x9A34 619 #define CB_PERF_CTR3_SEL_0 0x9A38 620 #define CB_PERF_CTR3_SEL_1 0x9A3C 621 622 #define TA_CNTL_AUX 0x9508 623 #define DISABLE_CUBE_WRAP (1 << 0) 624 #define DISABLE_CUBE_ANISO (1 << 1) 625 #define SYNC_GRADIENT (1 << 24) 626 #define SYNC_WALKER (1 << 25) 627 #define SYNC_ALIGNER (1 << 26) 628 629 #define TCP_CHAN_STEER_LO 0x960c 630 #define TCP_CHAN_STEER_HI 0x9610 631 632 #define VGT_CACHE_INVALIDATION 0x88C4 633 #define CACHE_INVALIDATION(x) ((x) << 0) 634 #define VC_ONLY 0 635 #define TC_ONLY 1 636 #define VC_AND_TC 2 637 #define AUTO_INVLD_EN(x) ((x) << 6) 638 #define NO_AUTO 0 639 #define ES_AUTO 1 640 #define GS_AUTO 2 641 #define ES_AND_GS_AUTO 3 642 #define VGT_GS_VERTEX_REUSE 0x88D4 643 #define VGT_NUM_INSTANCES 0x8974 644 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 645 #define DEALLOC_DIST_MASK 0x0000007F 646 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 647 #define VTX_REUSE_DEPTH_MASK 0x000000FF 648 649 #define VM_CONTEXT0_CNTL 0x1410 650 #define ENABLE_CONTEXT (1 << 0) 651 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 652 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 653 #define VM_CONTEXT1_CNTL 0x1414 654 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 655 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 656 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 657 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 658 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 659 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 660 #define RESPONSE_TYPE_MASK 0x000000F0 661 #define RESPONSE_TYPE_SHIFT 4 662 #define VM_L2_CNTL 0x1400 663 #define ENABLE_L2_CACHE (1 << 0) 664 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 665 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 666 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 667 #define VM_L2_CNTL2 0x1404 668 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 669 #define INVALIDATE_L2_CACHE (1 << 1) 670 #define VM_L2_CNTL3 0x1408 671 #define BANK_SELECT(x) ((x) << 0) 672 #define CACHE_UPDATE_MODE(x) ((x) << 6) 673 #define VM_L2_STATUS 0x140C 674 #define L2_BUSY (1 << 0) 675 676 #define WAIT_UNTIL 0x8040 677 678 #define SRBM_STATUS 0x0E50 679 #define SRBM_SOFT_RESET 0x0E60 680 #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 681 #define SOFT_RESET_BIF (1 << 1) 682 #define SOFT_RESET_CG (1 << 2) 683 #define SOFT_RESET_DC (1 << 5) 684 #define SOFT_RESET_GRBM (1 << 8) 685 #define SOFT_RESET_HDP (1 << 9) 686 #define SOFT_RESET_IH (1 << 10) 687 #define SOFT_RESET_MC (1 << 11) 688 #define SOFT_RESET_RLC (1 << 13) 689 #define SOFT_RESET_ROM (1 << 14) 690 #define SOFT_RESET_SEM (1 << 15) 691 #define SOFT_RESET_VMC (1 << 17) 692 #define SOFT_RESET_TST (1 << 21) 693 #define SOFT_RESET_REGBB (1 << 22) 694 #define SOFT_RESET_ORB (1 << 23) 695 696 /* display watermarks */ 697 #define DC_LB_MEMORY_SPLIT 0x6b0c 698 #define PRIORITY_A_CNT 0x6b18 699 #define PRIORITY_MARK_MASK 0x7fff 700 #define PRIORITY_OFF (1 << 16) 701 #define PRIORITY_ALWAYS_ON (1 << 20) 702 #define PRIORITY_B_CNT 0x6b1c 703 #define PIPE0_ARBITRATION_CONTROL3 0x0bf0 704 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 705 #define PIPE0_LATENCY_CONTROL 0x0bf4 706 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 707 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 708 709 #define IH_RB_CNTL 0x3e00 710 # define IH_RB_ENABLE (1 << 0) 711 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 712 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 713 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 714 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 715 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 716 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 717 #define IH_RB_BASE 0x3e04 718 #define IH_RB_RPTR 0x3e08 719 #define IH_RB_WPTR 0x3e0c 720 # define RB_OVERFLOW (1 << 0) 721 # define WPTR_OFFSET_MASK 0x3fffc 722 #define IH_RB_WPTR_ADDR_HI 0x3e10 723 #define IH_RB_WPTR_ADDR_LO 0x3e14 724 #define IH_CNTL 0x3e18 725 # define ENABLE_INTR (1 << 0) 726 # define IH_MC_SWAP(x) ((x) << 1) 727 # define IH_MC_SWAP_NONE 0 728 # define IH_MC_SWAP_16BIT 1 729 # define IH_MC_SWAP_32BIT 2 730 # define IH_MC_SWAP_64BIT 3 731 # define RPTR_REARM (1 << 4) 732 # define MC_WRREQ_CREDIT(x) ((x) << 15) 733 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 734 735 #define CP_INT_CNTL 0xc124 736 # define CNTX_BUSY_INT_ENABLE (1 << 19) 737 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 738 # define SCRATCH_INT_ENABLE (1 << 25) 739 # define TIME_STAMP_INT_ENABLE (1 << 26) 740 # define IB2_INT_ENABLE (1 << 29) 741 # define IB1_INT_ENABLE (1 << 30) 742 # define RB_INT_ENABLE (1 << 31) 743 #define CP_INT_STATUS 0xc128 744 # define SCRATCH_INT_STAT (1 << 25) 745 # define TIME_STAMP_INT_STAT (1 << 26) 746 # define IB2_INT_STAT (1 << 29) 747 # define IB1_INT_STAT (1 << 30) 748 # define RB_INT_STAT (1 << 31) 749 750 #define GRBM_INT_CNTL 0x8060 751 # define RDERR_INT_ENABLE (1 << 0) 752 # define GUI_IDLE_INT_ENABLE (1 << 19) 753 754 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 755 #define CRTC_STATUS_FRAME_COUNT 0x6e98 756 757 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 758 #define VLINE_STATUS 0x6bb8 759 # define VLINE_OCCURRED (1 << 0) 760 # define VLINE_ACK (1 << 4) 761 # define VLINE_STAT (1 << 12) 762 # define VLINE_INTERRUPT (1 << 16) 763 # define VLINE_INTERRUPT_TYPE (1 << 17) 764 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 765 #define VBLANK_STATUS 0x6bbc 766 # define VBLANK_OCCURRED (1 << 0) 767 # define VBLANK_ACK (1 << 4) 768 # define VBLANK_STAT (1 << 12) 769 # define VBLANK_INTERRUPT (1 << 16) 770 # define VBLANK_INTERRUPT_TYPE (1 << 17) 771 772 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 773 #define INT_MASK 0x6b40 774 # define VBLANK_INT_MASK (1 << 0) 775 # define VLINE_INT_MASK (1 << 4) 776 777 #define DISP_INTERRUPT_STATUS 0x60f4 778 # define LB_D1_VLINE_INTERRUPT (1 << 2) 779 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 780 # define DC_HPD1_INTERRUPT (1 << 17) 781 # define DC_HPD1_RX_INTERRUPT (1 << 18) 782 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 783 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 784 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 785 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 786 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 787 # define LB_D2_VLINE_INTERRUPT (1 << 2) 788 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 789 # define DC_HPD2_INTERRUPT (1 << 17) 790 # define DC_HPD2_RX_INTERRUPT (1 << 18) 791 # define DISP_TIMER_INTERRUPT (1 << 24) 792 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 793 # define LB_D3_VLINE_INTERRUPT (1 << 2) 794 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 795 # define DC_HPD3_INTERRUPT (1 << 17) 796 # define DC_HPD3_RX_INTERRUPT (1 << 18) 797 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 798 # define LB_D4_VLINE_INTERRUPT (1 << 2) 799 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 800 # define DC_HPD4_INTERRUPT (1 << 17) 801 # define DC_HPD4_RX_INTERRUPT (1 << 18) 802 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 803 # define LB_D5_VLINE_INTERRUPT (1 << 2) 804 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 805 # define DC_HPD5_INTERRUPT (1 << 17) 806 # define DC_HPD5_RX_INTERRUPT (1 << 18) 807 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 808 # define LB_D6_VLINE_INTERRUPT (1 << 2) 809 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 810 # define DC_HPD6_INTERRUPT (1 << 17) 811 # define DC_HPD6_RX_INTERRUPT (1 << 18) 812 813 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 814 #define GRPH_INT_STATUS 0x6858 815 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 816 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 817 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 818 #define GRPH_INT_CONTROL 0x685c 819 # define GRPH_PFLIP_INT_MASK (1 << 0) 820 # define GRPH_PFLIP_INT_TYPE (1 << 8) 821 822 #define DACA_AUTODETECT_INT_CONTROL 0x66c8 823 #define DACB_AUTODETECT_INT_CONTROL 0x67c8 824 825 #define DC_HPD1_INT_STATUS 0x601c 826 #define DC_HPD2_INT_STATUS 0x6028 827 #define DC_HPD3_INT_STATUS 0x6034 828 #define DC_HPD4_INT_STATUS 0x6040 829 #define DC_HPD5_INT_STATUS 0x604c 830 #define DC_HPD6_INT_STATUS 0x6058 831 # define DC_HPDx_INT_STATUS (1 << 0) 832 # define DC_HPDx_SENSE (1 << 1) 833 # define DC_HPDx_RX_INT_STATUS (1 << 8) 834 835 #define DC_HPD1_INT_CONTROL 0x6020 836 #define DC_HPD2_INT_CONTROL 0x602c 837 #define DC_HPD3_INT_CONTROL 0x6038 838 #define DC_HPD4_INT_CONTROL 0x6044 839 #define DC_HPD5_INT_CONTROL 0x6050 840 #define DC_HPD6_INT_CONTROL 0x605c 841 # define DC_HPDx_INT_ACK (1 << 0) 842 # define DC_HPDx_INT_POLARITY (1 << 8) 843 # define DC_HPDx_INT_EN (1 << 16) 844 # define DC_HPDx_RX_INT_ACK (1 << 20) 845 # define DC_HPDx_RX_INT_EN (1 << 24) 846 847 #define DC_HPD1_CONTROL 0x6024 848 #define DC_HPD2_CONTROL 0x6030 849 #define DC_HPD3_CONTROL 0x603c 850 #define DC_HPD4_CONTROL 0x6048 851 #define DC_HPD5_CONTROL 0x6054 852 #define DC_HPD6_CONTROL 0x6060 853 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 854 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 855 # define DC_HPDx_EN (1 << 28) 856 857 /* PCIE link stuff */ 858 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 859 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 860 # define LC_LINK_WIDTH_SHIFT 0 861 # define LC_LINK_WIDTH_MASK 0x7 862 # define LC_LINK_WIDTH_X0 0 863 # define LC_LINK_WIDTH_X1 1 864 # define LC_LINK_WIDTH_X2 2 865 # define LC_LINK_WIDTH_X4 3 866 # define LC_LINK_WIDTH_X8 4 867 # define LC_LINK_WIDTH_X16 6 868 # define LC_LINK_WIDTH_RD_SHIFT 4 869 # define LC_LINK_WIDTH_RD_MASK 0x70 870 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 871 # define LC_RECONFIG_NOW (1 << 8) 872 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 873 # define LC_RENEGOTIATE_EN (1 << 10) 874 # define LC_SHORT_RECONFIG_EN (1 << 11) 875 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 876 # define LC_UPCONFIGURE_DIS (1 << 13) 877 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 878 # define LC_GEN2_EN_STRAP (1 << 0) 879 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 880 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 881 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 882 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 883 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 884 # define LC_CURRENT_DATA_RATE (1 << 11) 885 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 886 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 887 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 888 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 889 #define MM_CFGREGS_CNTL 0x544c 890 # define MM_WR_TO_CFG_EN (1 << 3) 891 #define LINK_CNTL2 0x88 /* F0 */ 892 # define TARGET_LINK_SPEED_MASK (0xf << 0) 893 # define SELECTABLE_DEEMPHASIS (1 << 6) 894 895 /* 896 * PM4 897 */ 898 #define PACKET_TYPE0 0 899 #define PACKET_TYPE1 1 900 #define PACKET_TYPE2 2 901 #define PACKET_TYPE3 3 902 903 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 904 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 905 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 906 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 907 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 908 (((reg) >> 2) & 0xFFFF) | \ 909 ((n) & 0x3FFF) << 16) 910 #define CP_PACKET2 0x80000000 911 #define PACKET2_PAD_SHIFT 0 912 #define PACKET2_PAD_MASK (0x3fffffff << 0) 913 914 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 915 916 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 917 (((op) & 0xFF) << 8) | \ 918 ((n) & 0x3FFF) << 16) 919 920 /* Packet 3 types */ 921 #define PACKET3_NOP 0x10 922 #define PACKET3_SET_BASE 0x11 923 #define PACKET3_CLEAR_STATE 0x12 924 #define PACKET3_INDEX_BUFFER_SIZE 0x13 925 #define PACKET3_DISPATCH_DIRECT 0x15 926 #define PACKET3_DISPATCH_INDIRECT 0x16 927 #define PACKET3_INDIRECT_BUFFER_END 0x17 928 #define PACKET3_MODE_CONTROL 0x18 929 #define PACKET3_SET_PREDICATION 0x20 930 #define PACKET3_REG_RMW 0x21 931 #define PACKET3_COND_EXEC 0x22 932 #define PACKET3_PRED_EXEC 0x23 933 #define PACKET3_DRAW_INDIRECT 0x24 934 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 935 #define PACKET3_INDEX_BASE 0x26 936 #define PACKET3_DRAW_INDEX_2 0x27 937 #define PACKET3_CONTEXT_CONTROL 0x28 938 #define PACKET3_DRAW_INDEX_OFFSET 0x29 939 #define PACKET3_INDEX_TYPE 0x2A 940 #define PACKET3_DRAW_INDEX 0x2B 941 #define PACKET3_DRAW_INDEX_AUTO 0x2D 942 #define PACKET3_DRAW_INDEX_IMMD 0x2E 943 #define PACKET3_NUM_INSTANCES 0x2F 944 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 945 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 946 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 947 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 948 #define PACKET3_MEM_SEMAPHORE 0x39 949 #define PACKET3_MPEG_INDEX 0x3A 950 #define PACKET3_COPY_DW 0x3B 951 #define PACKET3_WAIT_REG_MEM 0x3C 952 #define PACKET3_MEM_WRITE 0x3D 953 #define PACKET3_INDIRECT_BUFFER 0x32 954 #define PACKET3_SURFACE_SYNC 0x43 955 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 956 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 957 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 958 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 959 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 960 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 961 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 962 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 963 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 964 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 965 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 966 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 967 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 968 # define PACKET3_FULL_CACHE_ENA (1 << 20) 969 # define PACKET3_TC_ACTION_ENA (1 << 23) 970 # define PACKET3_VC_ACTION_ENA (1 << 24) 971 # define PACKET3_CB_ACTION_ENA (1 << 25) 972 # define PACKET3_DB_ACTION_ENA (1 << 26) 973 # define PACKET3_SH_ACTION_ENA (1 << 27) 974 # define PACKET3_SX_ACTION_ENA (1 << 28) 975 #define PACKET3_ME_INITIALIZE 0x44 976 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 977 #define PACKET3_COND_WRITE 0x45 978 #define PACKET3_EVENT_WRITE 0x46 979 #define PACKET3_EVENT_WRITE_EOP 0x47 980 #define PACKET3_EVENT_WRITE_EOS 0x48 981 #define PACKET3_PREAMBLE_CNTL 0x4A 982 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 983 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 984 #define PACKET3_RB_OFFSET 0x4B 985 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 986 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 987 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E 988 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F 989 #define PACKET3_ONE_REG_WRITE 0x57 990 #define PACKET3_SET_CONFIG_REG 0x68 991 #define PACKET3_SET_CONFIG_REG_START 0x00008000 992 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 993 #define PACKET3_SET_CONTEXT_REG 0x69 994 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 995 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 996 #define PACKET3_SET_ALU_CONST 0x6A 997 /* alu const buffers only; no reg file */ 998 #define PACKET3_SET_BOOL_CONST 0x6B 999 #define PACKET3_SET_BOOL_CONST_START 0x0003a500 1000 #define PACKET3_SET_BOOL_CONST_END 0x0003a518 1001 #define PACKET3_SET_LOOP_CONST 0x6C 1002 #define PACKET3_SET_LOOP_CONST_START 0x0003a200 1003 #define PACKET3_SET_LOOP_CONST_END 0x0003a500 1004 #define PACKET3_SET_RESOURCE 0x6D 1005 #define PACKET3_SET_RESOURCE_START 0x00030000 1006 #define PACKET3_SET_RESOURCE_END 0x00038000 1007 #define PACKET3_SET_SAMPLER 0x6E 1008 #define PACKET3_SET_SAMPLER_START 0x0003c000 1009 #define PACKET3_SET_SAMPLER_END 0x0003c600 1010 #define PACKET3_SET_CTL_CONST 0x6F 1011 #define PACKET3_SET_CTL_CONST_START 0x0003cff0 1012 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c 1013 #define PACKET3_SET_RESOURCE_OFFSET 0x70 1014 #define PACKET3_SET_ALU_CONST_VS 0x71 1015 #define PACKET3_SET_ALU_CONST_DI 0x72 1016 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1017 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 1018 #define PACKET3_SET_APPEND_CNT 0x75 1019 1020 #define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c 1021 #define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) 1022 #define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) 1023 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 1024 #define SQ_TEX_VTX_INVALID_BUFFER 0x1 1025 #define SQ_TEX_VTX_VALID_TEXTURE 0x2 1026 #define SQ_TEX_VTX_VALID_BUFFER 0x3 1027 1028 #define VGT_VTX_VECT_EJECT_REG 0x88b0 1029 1030 #define SQ_CONST_MEM_BASE 0x8df8 1031 1032 #define SQ_ESGS_RING_BASE 0x8c40 1033 #define SQ_ESGS_RING_SIZE 0x8c44 1034 #define SQ_GSVS_RING_BASE 0x8c48 1035 #define SQ_GSVS_RING_SIZE 0x8c4c 1036 #define SQ_ESTMP_RING_BASE 0x8c50 1037 #define SQ_ESTMP_RING_SIZE 0x8c54 1038 #define SQ_GSTMP_RING_BASE 0x8c58 1039 #define SQ_GSTMP_RING_SIZE 0x8c5c 1040 #define SQ_VSTMP_RING_BASE 0x8c60 1041 #define SQ_VSTMP_RING_SIZE 0x8c64 1042 #define SQ_PSTMP_RING_BASE 0x8c68 1043 #define SQ_PSTMP_RING_SIZE 0x8c6c 1044 #define SQ_LSTMP_RING_BASE 0x8e10 1045 #define SQ_LSTMP_RING_SIZE 0x8e14 1046 #define SQ_HSTMP_RING_BASE 0x8e18 1047 #define SQ_HSTMP_RING_SIZE 0x8e1c 1048 #define VGT_TF_RING_SIZE 0x8988 1049 1050 #define SQ_ESGS_RING_ITEMSIZE 0x28900 1051 #define SQ_GSVS_RING_ITEMSIZE 0x28904 1052 #define SQ_ESTMP_RING_ITEMSIZE 0x28908 1053 #define SQ_GSTMP_RING_ITEMSIZE 0x2890c 1054 #define SQ_VSTMP_RING_ITEMSIZE 0x28910 1055 #define SQ_PSTMP_RING_ITEMSIZE 0x28914 1056 #define SQ_LSTMP_RING_ITEMSIZE 0x28830 1057 #define SQ_HSTMP_RING_ITEMSIZE 0x28834 1058 1059 #define SQ_GS_VERT_ITEMSIZE 0x2891c 1060 #define SQ_GS_VERT_ITEMSIZE_1 0x28920 1061 #define SQ_GS_VERT_ITEMSIZE_2 0x28924 1062 #define SQ_GS_VERT_ITEMSIZE_3 0x28928 1063 #define SQ_GSVS_RING_OFFSET_1 0x2892c 1064 #define SQ_GSVS_RING_OFFSET_2 0x28930 1065 #define SQ_GSVS_RING_OFFSET_3 0x28934 1066 1067 #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 1068 #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 1069 1070 #define SQ_ALU_CONST_CACHE_PS_0 0x28940 1071 #define SQ_ALU_CONST_CACHE_PS_1 0x28944 1072 #define SQ_ALU_CONST_CACHE_PS_2 0x28948 1073 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c 1074 #define SQ_ALU_CONST_CACHE_PS_4 0x28950 1075 #define SQ_ALU_CONST_CACHE_PS_5 0x28954 1076 #define SQ_ALU_CONST_CACHE_PS_6 0x28958 1077 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c 1078 #define SQ_ALU_CONST_CACHE_PS_8 0x28960 1079 #define SQ_ALU_CONST_CACHE_PS_9 0x28964 1080 #define SQ_ALU_CONST_CACHE_PS_10 0x28968 1081 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c 1082 #define SQ_ALU_CONST_CACHE_PS_12 0x28970 1083 #define SQ_ALU_CONST_CACHE_PS_13 0x28974 1084 #define SQ_ALU_CONST_CACHE_PS_14 0x28978 1085 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c 1086 #define SQ_ALU_CONST_CACHE_VS_0 0x28980 1087 #define SQ_ALU_CONST_CACHE_VS_1 0x28984 1088 #define SQ_ALU_CONST_CACHE_VS_2 0x28988 1089 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c 1090 #define SQ_ALU_CONST_CACHE_VS_4 0x28990 1091 #define SQ_ALU_CONST_CACHE_VS_5 0x28994 1092 #define SQ_ALU_CONST_CACHE_VS_6 0x28998 1093 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c 1094 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 1095 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 1096 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 1097 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac 1098 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 1099 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 1100 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 1101 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc 1102 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 1103 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 1104 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 1105 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc 1106 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 1107 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 1108 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 1109 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc 1110 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 1111 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 1112 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 1113 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec 1114 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 1115 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 1116 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 1117 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc 1118 #define SQ_ALU_CONST_CACHE_HS_0 0x28f00 1119 #define SQ_ALU_CONST_CACHE_HS_1 0x28f04 1120 #define SQ_ALU_CONST_CACHE_HS_2 0x28f08 1121 #define SQ_ALU_CONST_CACHE_HS_3 0x28f0c 1122 #define SQ_ALU_CONST_CACHE_HS_4 0x28f10 1123 #define SQ_ALU_CONST_CACHE_HS_5 0x28f14 1124 #define SQ_ALU_CONST_CACHE_HS_6 0x28f18 1125 #define SQ_ALU_CONST_CACHE_HS_7 0x28f1c 1126 #define SQ_ALU_CONST_CACHE_HS_8 0x28f20 1127 #define SQ_ALU_CONST_CACHE_HS_9 0x28f24 1128 #define SQ_ALU_CONST_CACHE_HS_10 0x28f28 1129 #define SQ_ALU_CONST_CACHE_HS_11 0x28f2c 1130 #define SQ_ALU_CONST_CACHE_HS_12 0x28f30 1131 #define SQ_ALU_CONST_CACHE_HS_13 0x28f34 1132 #define SQ_ALU_CONST_CACHE_HS_14 0x28f38 1133 #define SQ_ALU_CONST_CACHE_HS_15 0x28f3c 1134 #define SQ_ALU_CONST_CACHE_LS_0 0x28f40 1135 #define SQ_ALU_CONST_CACHE_LS_1 0x28f44 1136 #define SQ_ALU_CONST_CACHE_LS_2 0x28f48 1137 #define SQ_ALU_CONST_CACHE_LS_3 0x28f4c 1138 #define SQ_ALU_CONST_CACHE_LS_4 0x28f50 1139 #define SQ_ALU_CONST_CACHE_LS_5 0x28f54 1140 #define SQ_ALU_CONST_CACHE_LS_6 0x28f58 1141 #define SQ_ALU_CONST_CACHE_LS_7 0x28f5c 1142 #define SQ_ALU_CONST_CACHE_LS_8 0x28f60 1143 #define SQ_ALU_CONST_CACHE_LS_9 0x28f64 1144 #define SQ_ALU_CONST_CACHE_LS_10 0x28f68 1145 #define SQ_ALU_CONST_CACHE_LS_11 0x28f6c 1146 #define SQ_ALU_CONST_CACHE_LS_12 0x28f70 1147 #define SQ_ALU_CONST_CACHE_LS_13 0x28f74 1148 #define SQ_ALU_CONST_CACHE_LS_14 0x28f78 1149 #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c 1150 1151 #define PA_SC_SCREEN_SCISSOR_TL 0x28030 1152 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 1153 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 1154 1155 #define VGT_PRIMITIVE_TYPE 0x8958 1156 #define VGT_INDEX_TYPE 0x895C 1157 1158 #define VGT_NUM_INDICES 0x8970 1159 1160 #define VGT_COMPUTE_DIM_X 0x8990 1161 #define VGT_COMPUTE_DIM_Y 0x8994 1162 #define VGT_COMPUTE_DIM_Z 0x8998 1163 #define VGT_COMPUTE_START_X 0x899C 1164 #define VGT_COMPUTE_START_Y 0x89A0 1165 #define VGT_COMPUTE_START_Z 0x89A4 1166 #define VGT_COMPUTE_INDEX 0x89A8 1167 #define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC 1168 #define VGT_HS_OFFCHIP_PARAM 0x89B0 1169 1170 #define DB_DEBUG 0x9830 1171 #define DB_DEBUG2 0x9834 1172 #define DB_DEBUG3 0x9838 1173 #define DB_DEBUG4 0x983C 1174 #define DB_WATERMARKS 0x9854 1175 #define DB_DEPTH_CONTROL 0x28800 1176 #define R_028800_DB_DEPTH_CONTROL 0x028800 1177 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 1178 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 1179 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE 1180 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 1181 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 1182 #define C_028800_Z_ENABLE 0xFFFFFFFD 1183 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 1184 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 1185 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 1186 #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 1187 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 1188 #define C_028800_ZFUNC 0xFFFFFF8F 1189 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 1190 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 1191 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 1192 #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 1193 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 1194 #define C_028800_STENCILFUNC 0xFFFFF8FF 1195 #define V_028800_STENCILFUNC_NEVER 0x00000000 1196 #define V_028800_STENCILFUNC_LESS 0x00000001 1197 #define V_028800_STENCILFUNC_EQUAL 0x00000002 1198 #define V_028800_STENCILFUNC_LEQUAL 0x00000003 1199 #define V_028800_STENCILFUNC_GREATER 0x00000004 1200 #define V_028800_STENCILFUNC_NOTEQUAL 0x00000005 1201 #define V_028800_STENCILFUNC_GEQUAL 0x00000006 1202 #define V_028800_STENCILFUNC_ALWAYS 0x00000007 1203 #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 1204 #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 1205 #define C_028800_STENCILFAIL 0xFFFFC7FF 1206 #define V_028800_STENCIL_KEEP 0x00000000 1207 #define V_028800_STENCIL_ZERO 0x00000001 1208 #define V_028800_STENCIL_REPLACE 0x00000002 1209 #define V_028800_STENCIL_INCR 0x00000003 1210 #define V_028800_STENCIL_DECR 0x00000004 1211 #define V_028800_STENCIL_INVERT 0x00000005 1212 #define V_028800_STENCIL_INCR_WRAP 0x00000006 1213 #define V_028800_STENCIL_DECR_WRAP 0x00000007 1214 #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 1215 #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 1216 #define C_028800_STENCILZPASS 0xFFFE3FFF 1217 #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 1218 #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 1219 #define C_028800_STENCILZFAIL 0xFFF1FFFF 1220 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 1221 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 1222 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF 1223 #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 1224 #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 1225 #define C_028800_STENCILFAIL_BF 0xFC7FFFFF 1226 #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 1227 #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 1228 #define C_028800_STENCILZPASS_BF 0xE3FFFFFF 1229 #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 1230 #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 1231 #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 1232 #define DB_DEPTH_VIEW 0x28008 1233 #define R_028008_DB_DEPTH_VIEW 0x00028008 1234 #define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) 1235 #define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) 1236 #define C_028008_SLICE_START 0xFFFFF800 1237 #define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1238 #define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1239 #define C_028008_SLICE_MAX 0xFF001FFF 1240 #define DB_HTILE_DATA_BASE 0x28014 1241 #define DB_HTILE_SURFACE 0x28abc 1242 #define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0) 1243 #define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 1244 #define C_028ABC_HTILE_WIDTH 0xFFFFFFFE 1245 #define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 1246 #define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 1247 #define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD 1248 #define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1) 1249 #define DB_Z_INFO 0x28040 1250 # define Z_ARRAY_MODE(x) ((x) << 4) 1251 # define DB_TILE_SPLIT(x) (((x) & 0x7) << 8) 1252 # define DB_NUM_BANKS(x) (((x) & 0x3) << 12) 1253 # define DB_BANK_WIDTH(x) (((x) & 0x3) << 16) 1254 # define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1255 # define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1256 #define R_028040_DB_Z_INFO 0x028040 1257 #define S_028040_FORMAT(x) (((x) & 0x3) << 0) 1258 #define G_028040_FORMAT(x) (((x) >> 0) & 0x3) 1259 #define C_028040_FORMAT 0xFFFFFFFC 1260 #define V_028040_Z_INVALID 0x00000000 1261 #define V_028040_Z_16 0x00000001 1262 #define V_028040_Z_24 0x00000002 1263 #define V_028040_Z_32_FLOAT 0x00000003 1264 #define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4) 1265 #define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF) 1266 #define C_028040_ARRAY_MODE 0xFFFFFF0F 1267 #define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) 1268 #define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) 1269 #define C_028040_READ_SIZE 0xEFFFFFFF 1270 #define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) 1271 #define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) 1272 #define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF 1273 #define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1274 #define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1275 #define C_028040_ZRANGE_PRECISION 0x7FFFFFFF 1276 #define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8) 1277 #define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1278 #define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12) 1279 #define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3) 1280 #define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16) 1281 #define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3) 1282 #define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1283 #define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3) 1284 #define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1285 #define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3) 1286 #define DB_STENCIL_INFO 0x28044 1287 #define R_028044_DB_STENCIL_INFO 0x028044 1288 #define S_028044_FORMAT(x) (((x) & 0x1) << 0) 1289 #define G_028044_FORMAT(x) (((x) >> 0) & 0x1) 1290 #define C_028044_FORMAT 0xFFFFFFFE 1291 #define V_028044_STENCIL_INVALID 0 1292 #define V_028044_STENCIL_8 1 1293 #define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1294 #define DB_Z_READ_BASE 0x28048 1295 #define DB_STENCIL_READ_BASE 0x2804c 1296 #define DB_Z_WRITE_BASE 0x28050 1297 #define DB_STENCIL_WRITE_BASE 0x28054 1298 #define DB_DEPTH_SIZE 0x28058 1299 #define R_028058_DB_DEPTH_SIZE 0x028058 1300 #define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) 1301 #define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) 1302 #define C_028058_PITCH_TILE_MAX 0xFFFFF800 1303 #define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) 1304 #define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) 1305 #define C_028058_HEIGHT_TILE_MAX 0xFFC007FF 1306 #define R_02805C_DB_DEPTH_SLICE 0x02805C 1307 #define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) 1308 #define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) 1309 #define C_02805C_SLICE_TILE_MAX 0xFFC00000 1310 1311 #define SQ_PGM_START_PS 0x28840 1312 #define SQ_PGM_START_VS 0x2885c 1313 #define SQ_PGM_START_GS 0x28874 1314 #define SQ_PGM_START_ES 0x2888c 1315 #define SQ_PGM_START_FS 0x288a4 1316 #define SQ_PGM_START_HS 0x288b8 1317 #define SQ_PGM_START_LS 0x288d0 1318 1319 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 1320 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 1321 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 1322 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 1323 #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 1324 #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 1325 #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 1326 #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 1327 #define VGT_STRMOUT_CONFIG 0x28b94 1328 #define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 1329 1330 #define CB_TARGET_MASK 0x28238 1331 #define CB_SHADER_MASK 0x2823c 1332 1333 #define GDS_ADDR_BASE 0x28720 1334 1335 #define CB_IMMED0_BASE 0x28b9c 1336 #define CB_IMMED1_BASE 0x28ba0 1337 #define CB_IMMED2_BASE 0x28ba4 1338 #define CB_IMMED3_BASE 0x28ba8 1339 #define CB_IMMED4_BASE 0x28bac 1340 #define CB_IMMED5_BASE 0x28bb0 1341 #define CB_IMMED6_BASE 0x28bb4 1342 #define CB_IMMED7_BASE 0x28bb8 1343 #define CB_IMMED8_BASE 0x28bbc 1344 #define CB_IMMED9_BASE 0x28bc0 1345 #define CB_IMMED10_BASE 0x28bc4 1346 #define CB_IMMED11_BASE 0x28bc8 1347 1348 /* all 12 CB blocks have these regs */ 1349 #define CB_COLOR0_BASE 0x28c60 1350 #define CB_COLOR0_PITCH 0x28c64 1351 #define CB_COLOR0_SLICE 0x28c68 1352 #define CB_COLOR0_VIEW 0x28c6c 1353 #define R_028C6C_CB_COLOR0_VIEW 0x00028C6C 1354 #define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) 1355 #define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) 1356 #define C_028C6C_SLICE_START 0xFFFFF800 1357 #define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1358 #define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1359 #define C_028C6C_SLICE_MAX 0xFF001FFF 1360 #define R_028C70_CB_COLOR0_INFO 0x028C70 1361 #define S_028C70_ENDIAN(x) (((x) & 0x3) << 0) 1362 #define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3) 1363 #define C_028C70_ENDIAN 0xFFFFFFFC 1364 #define S_028C70_FORMAT(x) (((x) & 0x3F) << 2) 1365 #define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F) 1366 #define C_028C70_FORMAT 0xFFFFFF03 1367 #define V_028C70_COLOR_INVALID 0x00000000 1368 #define V_028C70_COLOR_8 0x00000001 1369 #define V_028C70_COLOR_4_4 0x00000002 1370 #define V_028C70_COLOR_3_3_2 0x00000003 1371 #define V_028C70_COLOR_16 0x00000005 1372 #define V_028C70_COLOR_16_FLOAT 0x00000006 1373 #define V_028C70_COLOR_8_8 0x00000007 1374 #define V_028C70_COLOR_5_6_5 0x00000008 1375 #define V_028C70_COLOR_6_5_5 0x00000009 1376 #define V_028C70_COLOR_1_5_5_5 0x0000000A 1377 #define V_028C70_COLOR_4_4_4_4 0x0000000B 1378 #define V_028C70_COLOR_5_5_5_1 0x0000000C 1379 #define V_028C70_COLOR_32 0x0000000D 1380 #define V_028C70_COLOR_32_FLOAT 0x0000000E 1381 #define V_028C70_COLOR_16_16 0x0000000F 1382 #define V_028C70_COLOR_16_16_FLOAT 0x00000010 1383 #define V_028C70_COLOR_8_24 0x00000011 1384 #define V_028C70_COLOR_8_24_FLOAT 0x00000012 1385 #define V_028C70_COLOR_24_8 0x00000013 1386 #define V_028C70_COLOR_24_8_FLOAT 0x00000014 1387 #define V_028C70_COLOR_10_11_11 0x00000015 1388 #define V_028C70_COLOR_10_11_11_FLOAT 0x00000016 1389 #define V_028C70_COLOR_11_11_10 0x00000017 1390 #define V_028C70_COLOR_11_11_10_FLOAT 0x00000018 1391 #define V_028C70_COLOR_2_10_10_10 0x00000019 1392 #define V_028C70_COLOR_8_8_8_8 0x0000001A 1393 #define V_028C70_COLOR_10_10_10_2 0x0000001B 1394 #define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C 1395 #define V_028C70_COLOR_32_32 0x0000001D 1396 #define V_028C70_COLOR_32_32_FLOAT 0x0000001E 1397 #define V_028C70_COLOR_16_16_16_16 0x0000001F 1398 #define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020 1399 #define V_028C70_COLOR_32_32_32_32 0x00000022 1400 #define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023 1401 #define V_028C70_COLOR_32_32_32_FLOAT 0x00000030 1402 #define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8) 1403 #define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1404 #define C_028C70_ARRAY_MODE 0xFFFFF0FF 1405 #define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000 1406 #define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001 1407 #define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002 1408 #define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004 1409 #define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1410 #define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1411 #define C_028C70_NUMBER_TYPE 0xFFFF8FFF 1412 #define V_028C70_NUMBER_UNORM 0x00000000 1413 #define V_028C70_NUMBER_SNORM 0x00000001 1414 #define V_028C70_NUMBER_USCALED 0x00000002 1415 #define V_028C70_NUMBER_SSCALED 0x00000003 1416 #define V_028C70_NUMBER_UINT 0x00000004 1417 #define V_028C70_NUMBER_SINT 0x00000005 1418 #define V_028C70_NUMBER_SRGB 0x00000006 1419 #define V_028C70_NUMBER_FLOAT 0x00000007 1420 #define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15) 1421 #define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3) 1422 #define C_028C70_COMP_SWAP 0xFFFE7FFF 1423 #define V_028C70_SWAP_STD 0x00000000 1424 #define V_028C70_SWAP_ALT 0x00000001 1425 #define V_028C70_SWAP_STD_REV 0x00000002 1426 #define V_028C70_SWAP_ALT_REV 0x00000003 1427 #define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17) 1428 #define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1) 1429 #define C_028C70_FAST_CLEAR 0xFFFDFFFF 1430 #define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18) 1431 #define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3) 1432 #define C_028C70_COMPRESSION 0xFFF3FFFF 1433 #define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19) 1434 #define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1) 1435 #define C_028C70_BLEND_CLAMP 0xFFF7FFFF 1436 #define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20) 1437 #define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1) 1438 #define C_028C70_BLEND_BYPASS 0xFFEFFFFF 1439 #define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21) 1440 #define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1) 1441 #define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF 1442 #define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22) 1443 #define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1) 1444 #define C_028C70_ROUND_MODE 0xFFBFFFFF 1445 #define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23) 1446 #define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1) 1447 #define C_028C70_TILE_COMPACT 0xFF7FFFFF 1448 #define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24) 1449 #define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3) 1450 #define C_028C70_SOURCE_FORMAT 0xFCFFFFFF 1451 #define V_028C70_EXPORT_4C_32BPC 0x0 1452 #define V_028C70_EXPORT_4C_16BPC 0x1 1453 #define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */ 1454 #define S_028C70_RAT(x) (((x) & 0x1) << 26) 1455 #define G_028C70_RAT(x) (((x) >> 26) & 0x1) 1456 #define C_028C70_RAT 0xFBFFFFFF 1457 #define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27) 1458 #define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7) 1459 #define C_028C70_RESOURCE_TYPE 0xC7FFFFFF 1460 1461 #define CB_COLOR0_INFO 0x28c70 1462 # define CB_FORMAT(x) ((x) << 2) 1463 # define CB_ARRAY_MODE(x) ((x) << 8) 1464 # define ARRAY_LINEAR_GENERAL 0 1465 # define ARRAY_LINEAR_ALIGNED 1 1466 # define ARRAY_1D_TILED_THIN1 2 1467 # define ARRAY_2D_TILED_THIN1 4 1468 # define CB_SOURCE_FORMAT(x) ((x) << 24) 1469 # define CB_SF_EXPORT_FULL 0 1470 # define CB_SF_EXPORT_NORM 1 1471 #define R_028C74_CB_COLOR0_ATTRIB 0x028C74 1472 #define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4) 1473 #define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1) 1474 #define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF 1475 #define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5) 1476 #define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf) 1477 #define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10) 1478 #define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3) 1479 #define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13) 1480 #define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3) 1481 #define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16) 1482 #define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3) 1483 #define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 1484 #define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3) 1485 #define CB_COLOR0_ATTRIB 0x28c74 1486 # define CB_TILE_SPLIT(x) (((x) & 0x7) << 5) 1487 # define ADDR_SURF_TILE_SPLIT_64B 0 1488 # define ADDR_SURF_TILE_SPLIT_128B 1 1489 # define ADDR_SURF_TILE_SPLIT_256B 2 1490 # define ADDR_SURF_TILE_SPLIT_512B 3 1491 # define ADDR_SURF_TILE_SPLIT_1KB 4 1492 # define ADDR_SURF_TILE_SPLIT_2KB 5 1493 # define ADDR_SURF_TILE_SPLIT_4KB 6 1494 # define CB_NUM_BANKS(x) (((x) & 0x3) << 10) 1495 # define ADDR_SURF_2_BANK 0 1496 # define ADDR_SURF_4_BANK 1 1497 # define ADDR_SURF_8_BANK 2 1498 # define ADDR_SURF_16_BANK 3 1499 # define CB_BANK_WIDTH(x) (((x) & 0x3) << 13) 1500 # define ADDR_SURF_BANK_WIDTH_1 0 1501 # define ADDR_SURF_BANK_WIDTH_2 1 1502 # define ADDR_SURF_BANK_WIDTH_4 2 1503 # define ADDR_SURF_BANK_WIDTH_8 3 1504 # define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16) 1505 # define ADDR_SURF_BANK_HEIGHT_1 0 1506 # define ADDR_SURF_BANK_HEIGHT_2 1 1507 # define ADDR_SURF_BANK_HEIGHT_4 2 1508 # define ADDR_SURF_BANK_HEIGHT_8 3 1509 # define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 1510 #define CB_COLOR0_DIM 0x28c78 1511 /* only CB0-7 blocks have these regs */ 1512 #define CB_COLOR0_CMASK 0x28c7c 1513 #define CB_COLOR0_CMASK_SLICE 0x28c80 1514 #define CB_COLOR0_FMASK 0x28c84 1515 #define CB_COLOR0_FMASK_SLICE 0x28c88 1516 #define CB_COLOR0_CLEAR_WORD0 0x28c8c 1517 #define CB_COLOR0_CLEAR_WORD1 0x28c90 1518 #define CB_COLOR0_CLEAR_WORD2 0x28c94 1519 #define CB_COLOR0_CLEAR_WORD3 0x28c98 1520 1521 #define CB_COLOR1_BASE 0x28c9c 1522 #define CB_COLOR2_BASE 0x28cd8 1523 #define CB_COLOR3_BASE 0x28d14 1524 #define CB_COLOR4_BASE 0x28d50 1525 #define CB_COLOR5_BASE 0x28d8c 1526 #define CB_COLOR6_BASE 0x28dc8 1527 #define CB_COLOR7_BASE 0x28e04 1528 #define CB_COLOR8_BASE 0x28e40 1529 #define CB_COLOR9_BASE 0x28e5c 1530 #define CB_COLOR10_BASE 0x28e78 1531 #define CB_COLOR11_BASE 0x28e94 1532 1533 #define CB_COLOR1_PITCH 0x28ca0 1534 #define CB_COLOR2_PITCH 0x28cdc 1535 #define CB_COLOR3_PITCH 0x28d18 1536 #define CB_COLOR4_PITCH 0x28d54 1537 #define CB_COLOR5_PITCH 0x28d90 1538 #define CB_COLOR6_PITCH 0x28dcc 1539 #define CB_COLOR7_PITCH 0x28e08 1540 #define CB_COLOR8_PITCH 0x28e44 1541 #define CB_COLOR9_PITCH 0x28e60 1542 #define CB_COLOR10_PITCH 0x28e7c 1543 #define CB_COLOR11_PITCH 0x28e98 1544 1545 #define CB_COLOR1_SLICE 0x28ca4 1546 #define CB_COLOR2_SLICE 0x28ce0 1547 #define CB_COLOR3_SLICE 0x28d1c 1548 #define CB_COLOR4_SLICE 0x28d58 1549 #define CB_COLOR5_SLICE 0x28d94 1550 #define CB_COLOR6_SLICE 0x28dd0 1551 #define CB_COLOR7_SLICE 0x28e0c 1552 #define CB_COLOR8_SLICE 0x28e48 1553 #define CB_COLOR9_SLICE 0x28e64 1554 #define CB_COLOR10_SLICE 0x28e80 1555 #define CB_COLOR11_SLICE 0x28e9c 1556 1557 #define CB_COLOR1_VIEW 0x28ca8 1558 #define CB_COLOR2_VIEW 0x28ce4 1559 #define CB_COLOR3_VIEW 0x28d20 1560 #define CB_COLOR4_VIEW 0x28d5c 1561 #define CB_COLOR5_VIEW 0x28d98 1562 #define CB_COLOR6_VIEW 0x28dd4 1563 #define CB_COLOR7_VIEW 0x28e10 1564 #define CB_COLOR8_VIEW 0x28e4c 1565 #define CB_COLOR9_VIEW 0x28e68 1566 #define CB_COLOR10_VIEW 0x28e84 1567 #define CB_COLOR11_VIEW 0x28ea0 1568 1569 #define CB_COLOR1_INFO 0x28cac 1570 #define CB_COLOR2_INFO 0x28ce8 1571 #define CB_COLOR3_INFO 0x28d24 1572 #define CB_COLOR4_INFO 0x28d60 1573 #define CB_COLOR5_INFO 0x28d9c 1574 #define CB_COLOR6_INFO 0x28dd8 1575 #define CB_COLOR7_INFO 0x28e14 1576 #define CB_COLOR8_INFO 0x28e50 1577 #define CB_COLOR9_INFO 0x28e6c 1578 #define CB_COLOR10_INFO 0x28e88 1579 #define CB_COLOR11_INFO 0x28ea4 1580 1581 #define CB_COLOR1_ATTRIB 0x28cb0 1582 #define CB_COLOR2_ATTRIB 0x28cec 1583 #define CB_COLOR3_ATTRIB 0x28d28 1584 #define CB_COLOR4_ATTRIB 0x28d64 1585 #define CB_COLOR5_ATTRIB 0x28da0 1586 #define CB_COLOR6_ATTRIB 0x28ddc 1587 #define CB_COLOR7_ATTRIB 0x28e18 1588 #define CB_COLOR8_ATTRIB 0x28e54 1589 #define CB_COLOR9_ATTRIB 0x28e70 1590 #define CB_COLOR10_ATTRIB 0x28e8c 1591 #define CB_COLOR11_ATTRIB 0x28ea8 1592 1593 #define CB_COLOR1_DIM 0x28cb4 1594 #define CB_COLOR2_DIM 0x28cf0 1595 #define CB_COLOR3_DIM 0x28d2c 1596 #define CB_COLOR4_DIM 0x28d68 1597 #define CB_COLOR5_DIM 0x28da4 1598 #define CB_COLOR6_DIM 0x28de0 1599 #define CB_COLOR7_DIM 0x28e1c 1600 #define CB_COLOR8_DIM 0x28e58 1601 #define CB_COLOR9_DIM 0x28e74 1602 #define CB_COLOR10_DIM 0x28e90 1603 #define CB_COLOR11_DIM 0x28eac 1604 1605 #define CB_COLOR1_CMASK 0x28cb8 1606 #define CB_COLOR2_CMASK 0x28cf4 1607 #define CB_COLOR3_CMASK 0x28d30 1608 #define CB_COLOR4_CMASK 0x28d6c 1609 #define CB_COLOR5_CMASK 0x28da8 1610 #define CB_COLOR6_CMASK 0x28de4 1611 #define CB_COLOR7_CMASK 0x28e20 1612 1613 #define CB_COLOR1_CMASK_SLICE 0x28cbc 1614 #define CB_COLOR2_CMASK_SLICE 0x28cf8 1615 #define CB_COLOR3_CMASK_SLICE 0x28d34 1616 #define CB_COLOR4_CMASK_SLICE 0x28d70 1617 #define CB_COLOR5_CMASK_SLICE 0x28dac 1618 #define CB_COLOR6_CMASK_SLICE 0x28de8 1619 #define CB_COLOR7_CMASK_SLICE 0x28e24 1620 1621 #define CB_COLOR1_FMASK 0x28cc0 1622 #define CB_COLOR2_FMASK 0x28cfc 1623 #define CB_COLOR3_FMASK 0x28d38 1624 #define CB_COLOR4_FMASK 0x28d74 1625 #define CB_COLOR5_FMASK 0x28db0 1626 #define CB_COLOR6_FMASK 0x28dec 1627 #define CB_COLOR7_FMASK 0x28e28 1628 1629 #define CB_COLOR1_FMASK_SLICE 0x28cc4 1630 #define CB_COLOR2_FMASK_SLICE 0x28d00 1631 #define CB_COLOR3_FMASK_SLICE 0x28d3c 1632 #define CB_COLOR4_FMASK_SLICE 0x28d78 1633 #define CB_COLOR5_FMASK_SLICE 0x28db4 1634 #define CB_COLOR6_FMASK_SLICE 0x28df0 1635 #define CB_COLOR7_FMASK_SLICE 0x28e2c 1636 1637 #define CB_COLOR1_CLEAR_WORD0 0x28cc8 1638 #define CB_COLOR2_CLEAR_WORD0 0x28d04 1639 #define CB_COLOR3_CLEAR_WORD0 0x28d40 1640 #define CB_COLOR4_CLEAR_WORD0 0x28d7c 1641 #define CB_COLOR5_CLEAR_WORD0 0x28db8 1642 #define CB_COLOR6_CLEAR_WORD0 0x28df4 1643 #define CB_COLOR7_CLEAR_WORD0 0x28e30 1644 1645 #define CB_COLOR1_CLEAR_WORD1 0x28ccc 1646 #define CB_COLOR2_CLEAR_WORD1 0x28d08 1647 #define CB_COLOR3_CLEAR_WORD1 0x28d44 1648 #define CB_COLOR4_CLEAR_WORD1 0x28d80 1649 #define CB_COLOR5_CLEAR_WORD1 0x28dbc 1650 #define CB_COLOR6_CLEAR_WORD1 0x28df8 1651 #define CB_COLOR7_CLEAR_WORD1 0x28e34 1652 1653 #define CB_COLOR1_CLEAR_WORD2 0x28cd0 1654 #define CB_COLOR2_CLEAR_WORD2 0x28d0c 1655 #define CB_COLOR3_CLEAR_WORD2 0x28d48 1656 #define CB_COLOR4_CLEAR_WORD2 0x28d84 1657 #define CB_COLOR5_CLEAR_WORD2 0x28dc0 1658 #define CB_COLOR6_CLEAR_WORD2 0x28dfc 1659 #define CB_COLOR7_CLEAR_WORD2 0x28e38 1660 1661 #define CB_COLOR1_CLEAR_WORD3 0x28cd4 1662 #define CB_COLOR2_CLEAR_WORD3 0x28d10 1663 #define CB_COLOR3_CLEAR_WORD3 0x28d4c 1664 #define CB_COLOR4_CLEAR_WORD3 0x28d88 1665 #define CB_COLOR5_CLEAR_WORD3 0x28dc4 1666 #define CB_COLOR6_CLEAR_WORD3 0x28e00 1667 #define CB_COLOR7_CLEAR_WORD3 0x28e3c 1668 1669 #define SQ_TEX_RESOURCE_WORD0_0 0x30000 1670 # define TEX_DIM(x) ((x) << 0) 1671 # define SQ_TEX_DIM_1D 0 1672 # define SQ_TEX_DIM_2D 1 1673 # define SQ_TEX_DIM_3D 2 1674 # define SQ_TEX_DIM_CUBEMAP 3 1675 # define SQ_TEX_DIM_1D_ARRAY 4 1676 # define SQ_TEX_DIM_2D_ARRAY 5 1677 # define SQ_TEX_DIM_2D_MSAA 6 1678 # define SQ_TEX_DIM_2D_ARRAY_MSAA 7 1679 #define SQ_TEX_RESOURCE_WORD1_0 0x30004 1680 # define TEX_ARRAY_MODE(x) ((x) << 28) 1681 #define SQ_TEX_RESOURCE_WORD2_0 0x30008 1682 #define SQ_TEX_RESOURCE_WORD3_0 0x3000C 1683 #define SQ_TEX_RESOURCE_WORD4_0 0x30010 1684 # define TEX_DST_SEL_X(x) ((x) << 16) 1685 # define TEX_DST_SEL_Y(x) ((x) << 19) 1686 # define TEX_DST_SEL_Z(x) ((x) << 22) 1687 # define TEX_DST_SEL_W(x) ((x) << 25) 1688 # define SQ_SEL_X 0 1689 # define SQ_SEL_Y 1 1690 # define SQ_SEL_Z 2 1691 # define SQ_SEL_W 3 1692 # define SQ_SEL_0 4 1693 # define SQ_SEL_1 5 1694 #define SQ_TEX_RESOURCE_WORD5_0 0x30014 1695 #define SQ_TEX_RESOURCE_WORD6_0 0x30018 1696 # define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29) 1697 #define SQ_TEX_RESOURCE_WORD7_0 0x3001c 1698 # define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 1699 # define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8) 1700 # define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10) 1701 # define TEX_NUM_BANKS(x) (((x) & 0x3) << 16) 1702 #define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000 1703 #define S_030000_DIM(x) (((x) & 0x7) << 0) 1704 #define G_030000_DIM(x) (((x) >> 0) & 0x7) 1705 #define C_030000_DIM 0xFFFFFFF8 1706 #define V_030000_SQ_TEX_DIM_1D 0x00000000 1707 #define V_030000_SQ_TEX_DIM_2D 0x00000001 1708 #define V_030000_SQ_TEX_DIM_3D 0x00000002 1709 #define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003 1710 #define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004 1711 #define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005 1712 #define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006 1713 #define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 1714 #define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5) 1715 #define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1) 1716 #define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF 1717 #define S_030000_PITCH(x) (((x) & 0xFFF) << 6) 1718 #define G_030000_PITCH(x) (((x) >> 6) & 0xFFF) 1719 #define C_030000_PITCH 0xFFFC003F 1720 #define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18) 1721 #define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF) 1722 #define C_030000_TEX_WIDTH 0x0003FFFF 1723 #define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004 1724 #define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0) 1725 #define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF) 1726 #define C_030004_TEX_HEIGHT 0xFFFFC000 1727 #define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14) 1728 #define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF) 1729 #define C_030004_TEX_DEPTH 0xF8003FFF 1730 #define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28) 1731 #define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF) 1732 #define C_030004_ARRAY_MODE 0x0FFFFFFF 1733 #define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008 1734 #define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 1735 #define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 1736 #define C_030008_BASE_ADDRESS 0x00000000 1737 #define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C 1738 #define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 1739 #define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 1740 #define C_03000C_MIP_ADDRESS 0x00000000 1741 #define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010 1742 #define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 1743 #define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 1744 #define C_030010_FORMAT_COMP_X 0xFFFFFFFC 1745 #define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000 1746 #define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001 1747 #define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002 1748 #define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 1749 #define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 1750 #define C_030010_FORMAT_COMP_Y 0xFFFFFFF3 1751 #define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 1752 #define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 1753 #define C_030010_FORMAT_COMP_Z 0xFFFFFFCF 1754 #define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 1755 #define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 1756 #define C_030010_FORMAT_COMP_W 0xFFFFFF3F 1757 #define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 1758 #define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 1759 #define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF 1760 #define V_030010_SQ_NUM_FORMAT_NORM 0x00000000 1761 #define V_030010_SQ_NUM_FORMAT_INT 0x00000001 1762 #define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002 1763 #define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 1764 #define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 1765 #define C_030010_SRF_MODE_ALL 0xFFFFFBFF 1766 #define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000 1767 #define V_030010_SRF_MODE_NO_ZERO 0x00000001 1768 #define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 1769 #define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 1770 #define C_030010_FORCE_DEGAMMA 0xFFFFF7FF 1771 #define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 1772 #define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 1773 #define C_030010_ENDIAN_SWAP 0xFFFFCFFF 1774 #define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16) 1775 #define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7) 1776 #define C_030010_DST_SEL_X 0xFFF8FFFF 1777 #define V_030010_SQ_SEL_X 0x00000000 1778 #define V_030010_SQ_SEL_Y 0x00000001 1779 #define V_030010_SQ_SEL_Z 0x00000002 1780 #define V_030010_SQ_SEL_W 0x00000003 1781 #define V_030010_SQ_SEL_0 0x00000004 1782 #define V_030010_SQ_SEL_1 0x00000005 1783 #define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19) 1784 #define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 1785 #define C_030010_DST_SEL_Y 0xFFC7FFFF 1786 #define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22) 1787 #define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 1788 #define C_030010_DST_SEL_Z 0xFE3FFFFF 1789 #define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25) 1790 #define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7) 1791 #define C_030010_DST_SEL_W 0xF1FFFFFF 1792 #define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28) 1793 #define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 1794 #define C_030010_BASE_LEVEL 0x0FFFFFFF 1795 #define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014 1796 #define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0) 1797 #define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 1798 #define C_030014_LAST_LEVEL 0xFFFFFFF0 1799 #define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 1800 #define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 1801 #define C_030014_BASE_ARRAY 0xFFFE000F 1802 #define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 1803 #define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 1804 #define C_030014_LAST_ARRAY 0xC001FFFF 1805 #define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018 1806 #define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0) 1807 #define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7) 1808 #define C_030018_MAX_ANISO 0xFFFFFFF8 1809 #define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3) 1810 #define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7) 1811 #define C_030018_PERF_MODULATION 0xFFFFFFC7 1812 #define S_030018_INTERLACED(x) (((x) & 0x1) << 6) 1813 #define G_030018_INTERLACED(x) (((x) >> 6) & 0x1) 1814 #define C_030018_INTERLACED 0xFFFFFFBF 1815 #define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29) 1816 #define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7) 1817 #define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C 1818 #define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 1819 #define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3) 1820 #define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8) 1821 #define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3) 1822 #define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10) 1823 #define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3) 1824 #define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16) 1825 #define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3) 1826 #define S_03001C_TYPE(x) (((x) & 0x3) << 30) 1827 #define G_03001C_TYPE(x) (((x) >> 30) & 0x3) 1828 #define C_03001C_TYPE 0x3FFFFFFF 1829 #define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000 1830 #define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001 1831 #define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002 1832 #define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003 1833 #define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0) 1834 #define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F) 1835 #define C_03001C_DATA_FORMAT 0xFFFFFFC0 1836 1837 #define SQ_VTX_CONSTANT_WORD0_0 0x30000 1838 #define SQ_VTX_CONSTANT_WORD1_0 0x30004 1839 #define SQ_VTX_CONSTANT_WORD2_0 0x30008 1840 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 1841 # define SQ_VTXC_STRIDE(x) ((x) << 8) 1842 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 1843 # define SQ_ENDIAN_NONE 0 1844 # define SQ_ENDIAN_8IN16 1 1845 # define SQ_ENDIAN_8IN32 2 1846 #define SQ_VTX_CONSTANT_WORD3_0 0x3000C 1847 # define SQ_VTCX_SEL_X(x) ((x) << 3) 1848 # define SQ_VTCX_SEL_Y(x) ((x) << 6) 1849 # define SQ_VTCX_SEL_Z(x) ((x) << 9) 1850 # define SQ_VTCX_SEL_W(x) ((x) << 12) 1851 #define SQ_VTX_CONSTANT_WORD4_0 0x30010 1852 #define SQ_VTX_CONSTANT_WORD5_0 0x30014 1853 #define SQ_VTX_CONSTANT_WORD6_0 0x30018 1854 #define SQ_VTX_CONSTANT_WORD7_0 0x3001c 1855 1856 #define TD_PS_BORDER_COLOR_INDEX 0xA400 1857 #define TD_PS_BORDER_COLOR_RED 0xA404 1858 #define TD_PS_BORDER_COLOR_GREEN 0xA408 1859 #define TD_PS_BORDER_COLOR_BLUE 0xA40C 1860 #define TD_PS_BORDER_COLOR_ALPHA 0xA410 1861 #define TD_VS_BORDER_COLOR_INDEX 0xA414 1862 #define TD_VS_BORDER_COLOR_RED 0xA418 1863 #define TD_VS_BORDER_COLOR_GREEN 0xA41C 1864 #define TD_VS_BORDER_COLOR_BLUE 0xA420 1865 #define TD_VS_BORDER_COLOR_ALPHA 0xA424 1866 #define TD_GS_BORDER_COLOR_INDEX 0xA428 1867 #define TD_GS_BORDER_COLOR_RED 0xA42C 1868 #define TD_GS_BORDER_COLOR_GREEN 0xA430 1869 #define TD_GS_BORDER_COLOR_BLUE 0xA434 1870 #define TD_GS_BORDER_COLOR_ALPHA 0xA438 1871 #define TD_HS_BORDER_COLOR_INDEX 0xA43C 1872 #define TD_HS_BORDER_COLOR_RED 0xA440 1873 #define TD_HS_BORDER_COLOR_GREEN 0xA444 1874 #define TD_HS_BORDER_COLOR_BLUE 0xA448 1875 #define TD_HS_BORDER_COLOR_ALPHA 0xA44C 1876 #define TD_LS_BORDER_COLOR_INDEX 0xA450 1877 #define TD_LS_BORDER_COLOR_RED 0xA454 1878 #define TD_LS_BORDER_COLOR_GREEN 0xA458 1879 #define TD_LS_BORDER_COLOR_BLUE 0xA45C 1880 #define TD_LS_BORDER_COLOR_ALPHA 0xA460 1881 #define TD_CS_BORDER_COLOR_INDEX 0xA464 1882 #define TD_CS_BORDER_COLOR_RED 0xA468 1883 #define TD_CS_BORDER_COLOR_GREEN 0xA46C 1884 #define TD_CS_BORDER_COLOR_BLUE 0xA470 1885 #define TD_CS_BORDER_COLOR_ALPHA 0xA474 1886 1887 /* cayman 3D regs */ 1888 #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4 1889 #define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48 1890 #define CAYMAN_DB_EQAA 0x28804 1891 #define CAYMAN_DB_DEPTH_INFO 0x2803C 1892 #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 1893 #define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 1894 #define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 1895 #define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 1896 /* cayman packet3 addition */ 1897 #define CAYMAN_PACKET3_DEALLOC_STATE 0x14 1898 1899 #endif 1900