1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include "drmP.h" 29 #include "radeon.h" 30 #include "evergreend.h" 31 #include "evergreen_reg_safe.h" 32 #include "cayman_reg_safe.h" 33 34 #define MAX(a,b) (((a)>(b))?(a):(b)) 35 #define MIN(a,b) (((a)<(b))?(a):(b)) 36 37 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p, 38 struct radeon_cs_reloc **cs_reloc); 39 40 struct evergreen_cs_track { 41 u32 group_size; 42 u32 nbanks; 43 u32 npipes; 44 u32 row_size; 45 /* value we track */ 46 u32 nsamples; /* unused */ 47 struct radeon_bo *cb_color_bo[12]; 48 u32 cb_color_bo_offset[12]; 49 struct radeon_bo *cb_color_fmask_bo[8]; /* unused */ 50 struct radeon_bo *cb_color_cmask_bo[8]; /* unused */ 51 u32 cb_color_info[12]; 52 u32 cb_color_view[12]; 53 u32 cb_color_pitch[12]; 54 u32 cb_color_slice[12]; 55 u32 cb_color_slice_idx[12]; 56 u32 cb_color_attrib[12]; 57 u32 cb_color_cmask_slice[8];/* unused */ 58 u32 cb_color_fmask_slice[8];/* unused */ 59 u32 cb_target_mask; 60 u32 cb_shader_mask; /* unused */ 61 u32 vgt_strmout_config; 62 u32 vgt_strmout_buffer_config; 63 struct radeon_bo *vgt_strmout_bo[4]; 64 u32 vgt_strmout_bo_offset[4]; 65 u32 vgt_strmout_size[4]; 66 u32 db_depth_control; 67 u32 db_depth_view; 68 u32 db_depth_slice; 69 u32 db_depth_size; 70 u32 db_z_info; 71 u32 db_z_read_offset; 72 u32 db_z_write_offset; 73 struct radeon_bo *db_z_read_bo; 74 struct radeon_bo *db_z_write_bo; 75 u32 db_s_info; 76 u32 db_s_read_offset; 77 u32 db_s_write_offset; 78 struct radeon_bo *db_s_read_bo; 79 struct radeon_bo *db_s_write_bo; 80 bool sx_misc_kill_all_prims; 81 bool cb_dirty; 82 bool db_dirty; 83 bool streamout_dirty; 84 u32 htile_offset; 85 u32 htile_surface; 86 struct radeon_bo *htile_bo; 87 }; 88 89 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) 90 { 91 if (tiling_flags & RADEON_TILING_MACRO) 92 return ARRAY_2D_TILED_THIN1; 93 else if (tiling_flags & RADEON_TILING_MICRO) 94 return ARRAY_1D_TILED_THIN1; 95 else 96 return ARRAY_LINEAR_GENERAL; 97 } 98 99 static u32 evergreen_cs_get_num_banks(u32 nbanks) 100 { 101 switch (nbanks) { 102 case 2: 103 return ADDR_SURF_2_BANK; 104 case 4: 105 return ADDR_SURF_4_BANK; 106 case 8: 107 default: 108 return ADDR_SURF_8_BANK; 109 case 16: 110 return ADDR_SURF_16_BANK; 111 } 112 } 113 114 static void evergreen_cs_track_init(struct evergreen_cs_track *track) 115 { 116 int i; 117 118 for (i = 0; i < 8; i++) { 119 track->cb_color_fmask_bo[i] = NULL; 120 track->cb_color_cmask_bo[i] = NULL; 121 track->cb_color_cmask_slice[i] = 0; 122 track->cb_color_fmask_slice[i] = 0; 123 } 124 125 for (i = 0; i < 12; i++) { 126 track->cb_color_bo[i] = NULL; 127 track->cb_color_bo_offset[i] = 0xFFFFFFFF; 128 track->cb_color_info[i] = 0; 129 track->cb_color_view[i] = 0xFFFFFFFF; 130 track->cb_color_pitch[i] = 0; 131 track->cb_color_slice[i] = 0xfffffff; 132 track->cb_color_slice_idx[i] = 0; 133 } 134 track->cb_target_mask = 0xFFFFFFFF; 135 track->cb_shader_mask = 0xFFFFFFFF; 136 track->cb_dirty = true; 137 138 track->db_depth_slice = 0xffffffff; 139 track->db_depth_view = 0xFFFFC000; 140 track->db_depth_size = 0xFFFFFFFF; 141 track->db_depth_control = 0xFFFFFFFF; 142 track->db_z_info = 0xFFFFFFFF; 143 track->db_z_read_offset = 0xFFFFFFFF; 144 track->db_z_write_offset = 0xFFFFFFFF; 145 track->db_z_read_bo = NULL; 146 track->db_z_write_bo = NULL; 147 track->db_s_info = 0xFFFFFFFF; 148 track->db_s_read_offset = 0xFFFFFFFF; 149 track->db_s_write_offset = 0xFFFFFFFF; 150 track->db_s_read_bo = NULL; 151 track->db_s_write_bo = NULL; 152 track->db_dirty = true; 153 track->htile_bo = NULL; 154 track->htile_offset = 0xFFFFFFFF; 155 track->htile_surface = 0; 156 157 for (i = 0; i < 4; i++) { 158 track->vgt_strmout_size[i] = 0; 159 track->vgt_strmout_bo[i] = NULL; 160 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF; 161 } 162 track->streamout_dirty = true; 163 track->sx_misc_kill_all_prims = false; 164 } 165 166 struct eg_surface { 167 /* value gathered from cs */ 168 unsigned nbx; 169 unsigned nby; 170 unsigned format; 171 unsigned mode; 172 unsigned nbanks; 173 unsigned bankw; 174 unsigned bankh; 175 unsigned tsplit; 176 unsigned mtilea; 177 unsigned nsamples; 178 /* output value */ 179 unsigned bpe; 180 unsigned layer_size; 181 unsigned palign; 182 unsigned halign; 183 unsigned long base_align; 184 }; 185 186 static int evergreen_surface_check_linear(struct radeon_cs_parser *p, 187 struct eg_surface *surf, 188 const char *prefix) 189 { 190 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples; 191 surf->base_align = surf->bpe; 192 surf->palign = 1; 193 surf->halign = 1; 194 return 0; 195 } 196 197 static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p, 198 struct eg_surface *surf, 199 const char *prefix) 200 { 201 struct evergreen_cs_track *track = p->track; 202 unsigned palign; 203 204 palign = MAX(64, track->group_size / surf->bpe); 205 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples; 206 surf->base_align = track->group_size; 207 surf->palign = palign; 208 surf->halign = 1; 209 if (surf->nbx & (palign - 1)) { 210 if (prefix) { 211 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", 212 __func__, __LINE__, prefix, surf->nbx, palign); 213 } 214 return -EINVAL; 215 } 216 return 0; 217 } 218 219 static int evergreen_surface_check_1d(struct radeon_cs_parser *p, 220 struct eg_surface *surf, 221 const char *prefix) 222 { 223 struct evergreen_cs_track *track = p->track; 224 unsigned palign; 225 226 palign = track->group_size / (8 * surf->bpe * surf->nsamples); 227 palign = MAX(8, palign); 228 surf->layer_size = surf->nbx * surf->nby * surf->bpe; 229 surf->base_align = track->group_size; 230 surf->palign = palign; 231 surf->halign = 8; 232 if ((surf->nbx & (palign - 1))) { 233 if (prefix) { 234 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n", 235 __func__, __LINE__, prefix, surf->nbx, palign, 236 track->group_size, surf->bpe, surf->nsamples); 237 } 238 return -EINVAL; 239 } 240 if ((surf->nby & (8 - 1))) { 241 if (prefix) { 242 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n", 243 __func__, __LINE__, prefix, surf->nby); 244 } 245 return -EINVAL; 246 } 247 return 0; 248 } 249 250 static int evergreen_surface_check_2d(struct radeon_cs_parser *p, 251 struct eg_surface *surf, 252 const char *prefix) 253 { 254 struct evergreen_cs_track *track = p->track; 255 unsigned palign, halign, tileb, slice_pt; 256 unsigned mtile_pr, mtile_ps, mtileb; 257 258 tileb = 64 * surf->bpe * surf->nsamples; 259 slice_pt = 1; 260 if (tileb > surf->tsplit) { 261 slice_pt = tileb / surf->tsplit; 262 } 263 tileb = tileb / slice_pt; 264 /* macro tile width & height */ 265 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; 266 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea; 267 mtileb = (palign / 8) * (halign / 8) * tileb;; 268 mtile_pr = surf->nbx / palign; 269 mtile_ps = (mtile_pr * surf->nby) / halign; 270 surf->layer_size = mtile_ps * mtileb * slice_pt; 271 surf->base_align = (palign / 8) * (halign / 8) * tileb; 272 surf->palign = palign; 273 surf->halign = halign; 274 275 if ((surf->nbx & (palign - 1))) { 276 if (prefix) { 277 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", 278 __func__, __LINE__, prefix, surf->nbx, palign); 279 } 280 return -EINVAL; 281 } 282 if ((surf->nby & (halign - 1))) { 283 if (prefix) { 284 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n", 285 __func__, __LINE__, prefix, surf->nby, halign); 286 } 287 return -EINVAL; 288 } 289 290 return 0; 291 } 292 293 static int evergreen_surface_check(struct radeon_cs_parser *p, 294 struct eg_surface *surf, 295 const char *prefix) 296 { 297 /* some common value computed here */ 298 surf->bpe = r600_fmt_get_blocksize(surf->format); 299 300 switch (surf->mode) { 301 case ARRAY_LINEAR_GENERAL: 302 return evergreen_surface_check_linear(p, surf, prefix); 303 case ARRAY_LINEAR_ALIGNED: 304 return evergreen_surface_check_linear_aligned(p, surf, prefix); 305 case ARRAY_1D_TILED_THIN1: 306 return evergreen_surface_check_1d(p, surf, prefix); 307 case ARRAY_2D_TILED_THIN1: 308 return evergreen_surface_check_2d(p, surf, prefix); 309 default: 310 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", 311 __func__, __LINE__, prefix, surf->mode); 312 return -EINVAL; 313 } 314 return -EINVAL; 315 } 316 317 static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p, 318 struct eg_surface *surf, 319 const char *prefix) 320 { 321 switch (surf->mode) { 322 case ARRAY_2D_TILED_THIN1: 323 break; 324 case ARRAY_LINEAR_GENERAL: 325 case ARRAY_LINEAR_ALIGNED: 326 case ARRAY_1D_TILED_THIN1: 327 return 0; 328 default: 329 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", 330 __func__, __LINE__, prefix, surf->mode); 331 return -EINVAL; 332 } 333 334 switch (surf->nbanks) { 335 case 0: surf->nbanks = 2; break; 336 case 1: surf->nbanks = 4; break; 337 case 2: surf->nbanks = 8; break; 338 case 3: surf->nbanks = 16; break; 339 default: 340 dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n", 341 __func__, __LINE__, prefix, surf->nbanks); 342 return -EINVAL; 343 } 344 switch (surf->bankw) { 345 case 0: surf->bankw = 1; break; 346 case 1: surf->bankw = 2; break; 347 case 2: surf->bankw = 4; break; 348 case 3: surf->bankw = 8; break; 349 default: 350 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n", 351 __func__, __LINE__, prefix, surf->bankw); 352 return -EINVAL; 353 } 354 switch (surf->bankh) { 355 case 0: surf->bankh = 1; break; 356 case 1: surf->bankh = 2; break; 357 case 2: surf->bankh = 4; break; 358 case 3: surf->bankh = 8; break; 359 default: 360 dev_warn(p->dev, "%s:%d %s invalid bankh %d\n", 361 __func__, __LINE__, prefix, surf->bankh); 362 return -EINVAL; 363 } 364 switch (surf->mtilea) { 365 case 0: surf->mtilea = 1; break; 366 case 1: surf->mtilea = 2; break; 367 case 2: surf->mtilea = 4; break; 368 case 3: surf->mtilea = 8; break; 369 default: 370 dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n", 371 __func__, __LINE__, prefix, surf->mtilea); 372 return -EINVAL; 373 } 374 switch (surf->tsplit) { 375 case 0: surf->tsplit = 64; break; 376 case 1: surf->tsplit = 128; break; 377 case 2: surf->tsplit = 256; break; 378 case 3: surf->tsplit = 512; break; 379 case 4: surf->tsplit = 1024; break; 380 case 5: surf->tsplit = 2048; break; 381 case 6: surf->tsplit = 4096; break; 382 default: 383 dev_warn(p->dev, "%s:%d %s invalid tile split %d\n", 384 __func__, __LINE__, prefix, surf->tsplit); 385 return -EINVAL; 386 } 387 return 0; 388 } 389 390 static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id) 391 { 392 struct evergreen_cs_track *track = p->track; 393 struct eg_surface surf; 394 unsigned pitch, slice, mslice; 395 unsigned long offset; 396 int r; 397 398 mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1; 399 pitch = track->cb_color_pitch[id]; 400 slice = track->cb_color_slice[id]; 401 surf.nbx = (pitch + 1) * 8; 402 surf.nby = ((slice + 1) * 64) / surf.nbx; 403 surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]); 404 surf.format = G_028C70_FORMAT(track->cb_color_info[id]); 405 surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]); 406 surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]); 407 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]); 408 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]); 409 surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]); 410 surf.nsamples = 1; 411 412 if (!r600_fmt_is_valid_color(surf.format)) { 413 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n", 414 __func__, __LINE__, surf.format, 415 id, track->cb_color_info[id]); 416 return -EINVAL; 417 } 418 419 r = evergreen_surface_value_conv_check(p, &surf, "cb"); 420 if (r) { 421 return r; 422 } 423 424 r = evergreen_surface_check(p, &surf, "cb"); 425 if (r) { 426 dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", 427 __func__, __LINE__, id, track->cb_color_pitch[id], 428 track->cb_color_slice[id], track->cb_color_attrib[id], 429 track->cb_color_info[id]); 430 return r; 431 } 432 433 offset = track->cb_color_bo_offset[id] << 8; 434 if (offset & (surf.base_align - 1)) { 435 dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n", 436 __func__, __LINE__, id, offset, surf.base_align); 437 return -EINVAL; 438 } 439 440 offset += surf.layer_size * mslice; 441 if (offset > radeon_bo_size(track->cb_color_bo[id])) { 442 /* old ddx are broken they allocate bo with w*h*bpp but 443 * program slice with ALIGN(h, 8), catch this and patch 444 * command stream. 445 */ 446 if (!surf.mode) { 447 volatile u32 *ib = p->ib.ptr; 448 unsigned long tmp, nby, bsize, size, min = 0; 449 450 /* find the height the ddx wants */ 451 if (surf.nby > 8) { 452 min = surf.nby - 8; 453 } 454 bsize = radeon_bo_size(track->cb_color_bo[id]); 455 tmp = track->cb_color_bo_offset[id] << 8; 456 for (nby = surf.nby; nby > min; nby--) { 457 size = nby * surf.nbx * surf.bpe * surf.nsamples; 458 if ((tmp + size * mslice) <= bsize) { 459 break; 460 } 461 } 462 if (nby > min) { 463 surf.nby = nby; 464 slice = ((nby * surf.nbx) / 64) - 1; 465 if (!evergreen_surface_check(p, &surf, "cb")) { 466 /* check if this one works */ 467 tmp += surf.layer_size * mslice; 468 if (tmp <= bsize) { 469 ib[track->cb_color_slice_idx[id]] = slice; 470 goto old_ddx_ok; 471 } 472 } 473 } 474 } 475 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, " 476 "offset %d, max layer %d, bo size %ld, slice %d)\n", 477 __func__, __LINE__, id, surf.layer_size, 478 track->cb_color_bo_offset[id] << 8, mslice, 479 radeon_bo_size(track->cb_color_bo[id]), slice); 480 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", 481 __func__, __LINE__, surf.nbx, surf.nby, 482 surf.mode, surf.bpe, surf.nsamples, 483 surf.bankw, surf.bankh, 484 surf.tsplit, surf.mtilea); 485 return -EINVAL; 486 } 487 old_ddx_ok: 488 489 return 0; 490 } 491 492 static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p, 493 unsigned nbx, unsigned nby) 494 { 495 struct evergreen_cs_track *track = p->track; 496 unsigned long size; 497 498 if (track->htile_bo == NULL) { 499 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n", 500 __func__, __LINE__, track->db_z_info); 501 return -EINVAL; 502 } 503 504 if (G_028ABC_LINEAR(track->htile_surface)) { 505 /* pitch must be 16 htiles aligned == 16 * 8 pixel aligned */ 506 nbx = round_up(nbx, 16 * 8); 507 /* height is npipes htiles aligned == npipes * 8 pixel aligned */ 508 nby = round_up(nby, track->npipes * 8); 509 } else { 510 switch (track->npipes) { 511 case 8: 512 nbx = round_up(nbx, 64 * 8); 513 nby = round_up(nby, 64 * 8); 514 break; 515 case 4: 516 nbx = round_up(nbx, 64 * 8); 517 nby = round_up(nby, 32 * 8); 518 break; 519 case 2: 520 nbx = round_up(nbx, 32 * 8); 521 nby = round_up(nby, 32 * 8); 522 break; 523 case 1: 524 nbx = round_up(nbx, 32 * 8); 525 nby = round_up(nby, 16 * 8); 526 break; 527 default: 528 dev_warn(p->dev, "%s:%d invalid num pipes %d\n", 529 __func__, __LINE__, track->npipes); 530 return -EINVAL; 531 } 532 } 533 /* compute number of htile */ 534 nbx = nbx / 8; 535 nby = nby / 8; 536 size = nbx * nby * 4; 537 size += track->htile_offset; 538 539 if (size > radeon_bo_size(track->htile_bo)) { 540 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", 541 __func__, __LINE__, radeon_bo_size(track->htile_bo), 542 size, nbx, nby); 543 return -EINVAL; 544 } 545 return 0; 546 } 547 548 static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p) 549 { 550 struct evergreen_cs_track *track = p->track; 551 struct eg_surface surf; 552 unsigned pitch, slice, mslice; 553 unsigned long offset; 554 int r; 555 556 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; 557 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); 558 slice = track->db_depth_slice; 559 surf.nbx = (pitch + 1) * 8; 560 surf.nby = ((slice + 1) * 64) / surf.nbx; 561 surf.mode = G_028040_ARRAY_MODE(track->db_z_info); 562 surf.format = G_028044_FORMAT(track->db_s_info); 563 surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info); 564 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); 565 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); 566 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); 567 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); 568 surf.nsamples = 1; 569 570 if (surf.format != 1) { 571 dev_warn(p->dev, "%s:%d stencil invalid format %d\n", 572 __func__, __LINE__, surf.format); 573 return -EINVAL; 574 } 575 /* replace by color format so we can use same code */ 576 surf.format = V_028C70_COLOR_8; 577 578 r = evergreen_surface_value_conv_check(p, &surf, "stencil"); 579 if (r) { 580 return r; 581 } 582 583 r = evergreen_surface_check(p, &surf, NULL); 584 if (r) { 585 /* old userspace doesn't compute proper depth/stencil alignment 586 * check that alignment against a bigger byte per elements and 587 * only report if that alignment is wrong too. 588 */ 589 surf.format = V_028C70_COLOR_8_8_8_8; 590 r = evergreen_surface_check(p, &surf, "stencil"); 591 if (r) { 592 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", 593 __func__, __LINE__, track->db_depth_size, 594 track->db_depth_slice, track->db_s_info, track->db_z_info); 595 } 596 return r; 597 } 598 599 offset = track->db_s_read_offset << 8; 600 if (offset & (surf.base_align - 1)) { 601 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n", 602 __func__, __LINE__, offset, surf.base_align); 603 return -EINVAL; 604 } 605 offset += surf.layer_size * mslice; 606 if (offset > radeon_bo_size(track->db_s_read_bo)) { 607 dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, " 608 "offset %ld, max layer %d, bo size %ld)\n", 609 __func__, __LINE__, surf.layer_size, 610 (unsigned long)track->db_s_read_offset << 8, mslice, 611 radeon_bo_size(track->db_s_read_bo)); 612 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", 613 __func__, __LINE__, track->db_depth_size, 614 track->db_depth_slice, track->db_s_info, track->db_z_info); 615 return -EINVAL; 616 } 617 618 offset = track->db_s_write_offset << 8; 619 if (offset & (surf.base_align - 1)) { 620 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n", 621 __func__, __LINE__, offset, surf.base_align); 622 return -EINVAL; 623 } 624 offset += surf.layer_size * mslice; 625 if (offset > radeon_bo_size(track->db_s_write_bo)) { 626 dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, " 627 "offset %ld, max layer %d, bo size %ld)\n", 628 __func__, __LINE__, surf.layer_size, 629 (unsigned long)track->db_s_write_offset << 8, mslice, 630 radeon_bo_size(track->db_s_write_bo)); 631 return -EINVAL; 632 } 633 634 /* hyperz */ 635 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) { 636 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby); 637 if (r) { 638 return r; 639 } 640 } 641 642 return 0; 643 } 644 645 static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p) 646 { 647 struct evergreen_cs_track *track = p->track; 648 struct eg_surface surf; 649 unsigned pitch, slice, mslice; 650 unsigned long offset; 651 int r; 652 653 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; 654 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); 655 slice = track->db_depth_slice; 656 surf.nbx = (pitch + 1) * 8; 657 surf.nby = ((slice + 1) * 64) / surf.nbx; 658 surf.mode = G_028040_ARRAY_MODE(track->db_z_info); 659 surf.format = G_028040_FORMAT(track->db_z_info); 660 surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info); 661 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info); 662 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info); 663 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info); 664 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info); 665 surf.nsamples = 1; 666 667 switch (surf.format) { 668 case V_028040_Z_16: 669 surf.format = V_028C70_COLOR_16; 670 break; 671 case V_028040_Z_24: 672 case V_028040_Z_32_FLOAT: 673 surf.format = V_028C70_COLOR_8_8_8_8; 674 break; 675 default: 676 dev_warn(p->dev, "%s:%d depth invalid format %d\n", 677 __func__, __LINE__, surf.format); 678 return -EINVAL; 679 } 680 681 r = evergreen_surface_value_conv_check(p, &surf, "depth"); 682 if (r) { 683 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", 684 __func__, __LINE__, track->db_depth_size, 685 track->db_depth_slice, track->db_z_info); 686 return r; 687 } 688 689 r = evergreen_surface_check(p, &surf, "depth"); 690 if (r) { 691 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", 692 __func__, __LINE__, track->db_depth_size, 693 track->db_depth_slice, track->db_z_info); 694 return r; 695 } 696 697 offset = track->db_z_read_offset << 8; 698 if (offset & (surf.base_align - 1)) { 699 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n", 700 __func__, __LINE__, offset, surf.base_align); 701 return -EINVAL; 702 } 703 offset += surf.layer_size * mslice; 704 if (offset > radeon_bo_size(track->db_z_read_bo)) { 705 dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, " 706 "offset %ld, max layer %d, bo size %ld)\n", 707 __func__, __LINE__, surf.layer_size, 708 (unsigned long)track->db_z_read_offset << 8, mslice, 709 radeon_bo_size(track->db_z_read_bo)); 710 return -EINVAL; 711 } 712 713 offset = track->db_z_write_offset << 8; 714 if (offset & (surf.base_align - 1)) { 715 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n", 716 __func__, __LINE__, offset, surf.base_align); 717 return -EINVAL; 718 } 719 offset += surf.layer_size * mslice; 720 if (offset > radeon_bo_size(track->db_z_write_bo)) { 721 dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, " 722 "offset %ld, max layer %d, bo size %ld)\n", 723 __func__, __LINE__, surf.layer_size, 724 (unsigned long)track->db_z_write_offset << 8, mslice, 725 radeon_bo_size(track->db_z_write_bo)); 726 return -EINVAL; 727 } 728 729 /* hyperz */ 730 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) { 731 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby); 732 if (r) { 733 return r; 734 } 735 } 736 737 return 0; 738 } 739 740 static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p, 741 struct radeon_bo *texture, 742 struct radeon_bo *mipmap, 743 unsigned idx) 744 { 745 struct eg_surface surf; 746 unsigned long toffset, moffset; 747 unsigned dim, llevel, mslice, width, height, depth, i; 748 u32 texdw[8]; 749 int r; 750 751 texdw[0] = radeon_get_ib_value(p, idx + 0); 752 texdw[1] = radeon_get_ib_value(p, idx + 1); 753 texdw[2] = radeon_get_ib_value(p, idx + 2); 754 texdw[3] = radeon_get_ib_value(p, idx + 3); 755 texdw[4] = radeon_get_ib_value(p, idx + 4); 756 texdw[5] = radeon_get_ib_value(p, idx + 5); 757 texdw[6] = radeon_get_ib_value(p, idx + 6); 758 texdw[7] = radeon_get_ib_value(p, idx + 7); 759 dim = G_030000_DIM(texdw[0]); 760 llevel = G_030014_LAST_LEVEL(texdw[5]); 761 mslice = G_030014_LAST_ARRAY(texdw[5]) + 1; 762 width = G_030000_TEX_WIDTH(texdw[0]) + 1; 763 height = G_030004_TEX_HEIGHT(texdw[1]) + 1; 764 depth = G_030004_TEX_DEPTH(texdw[1]) + 1; 765 surf.format = G_03001C_DATA_FORMAT(texdw[7]); 766 surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8; 767 surf.nbx = r600_fmt_get_nblocksx(surf.format, surf.nbx); 768 surf.nby = r600_fmt_get_nblocksy(surf.format, height); 769 surf.mode = G_030004_ARRAY_MODE(texdw[1]); 770 surf.tsplit = G_030018_TILE_SPLIT(texdw[6]); 771 surf.nbanks = G_03001C_NUM_BANKS(texdw[7]); 772 surf.bankw = G_03001C_BANK_WIDTH(texdw[7]); 773 surf.bankh = G_03001C_BANK_HEIGHT(texdw[7]); 774 surf.mtilea = G_03001C_MACRO_TILE_ASPECT(texdw[7]); 775 surf.nsamples = 1; 776 toffset = texdw[2] << 8; 777 moffset = texdw[3] << 8; 778 779 if (!r600_fmt_is_valid_texture(surf.format, p->family)) { 780 dev_warn(p->dev, "%s:%d texture invalid format %d\n", 781 __func__, __LINE__, surf.format); 782 return -EINVAL; 783 } 784 switch (dim) { 785 case V_030000_SQ_TEX_DIM_1D: 786 case V_030000_SQ_TEX_DIM_2D: 787 case V_030000_SQ_TEX_DIM_CUBEMAP: 788 case V_030000_SQ_TEX_DIM_1D_ARRAY: 789 case V_030000_SQ_TEX_DIM_2D_ARRAY: 790 depth = 1; 791 case V_030000_SQ_TEX_DIM_3D: 792 break; 793 default: 794 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n", 795 __func__, __LINE__, dim); 796 return -EINVAL; 797 } 798 799 r = evergreen_surface_value_conv_check(p, &surf, "texture"); 800 if (r) { 801 return r; 802 } 803 804 /* align height */ 805 evergreen_surface_check(p, &surf, NULL); 806 surf.nby = ALIGN(surf.nby, surf.halign); 807 808 r = evergreen_surface_check(p, &surf, "texture"); 809 if (r) { 810 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 811 __func__, __LINE__, texdw[0], texdw[1], texdw[4], 812 texdw[5], texdw[6], texdw[7]); 813 return r; 814 } 815 816 /* check texture size */ 817 if (toffset & (surf.base_align - 1)) { 818 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n", 819 __func__, __LINE__, toffset, surf.base_align); 820 return -EINVAL; 821 } 822 if (moffset & (surf.base_align - 1)) { 823 dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n", 824 __func__, __LINE__, moffset, surf.base_align); 825 return -EINVAL; 826 } 827 if (dim == SQ_TEX_DIM_3D) { 828 toffset += surf.layer_size * depth; 829 } else { 830 toffset += surf.layer_size * mslice; 831 } 832 if (toffset > radeon_bo_size(texture)) { 833 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, " 834 "offset %ld, max layer %d, depth %d, bo size %ld) (%d %d)\n", 835 __func__, __LINE__, surf.layer_size, 836 (unsigned long)texdw[2] << 8, mslice, 837 depth, radeon_bo_size(texture), 838 surf.nbx, surf.nby); 839 return -EINVAL; 840 } 841 842 /* check mipmap size */ 843 for (i = 1; i <= llevel; i++) { 844 unsigned w, h, d; 845 846 w = r600_mip_minify(width, i); 847 h = r600_mip_minify(height, i); 848 d = r600_mip_minify(depth, i); 849 surf.nbx = r600_fmt_get_nblocksx(surf.format, w); 850 surf.nby = r600_fmt_get_nblocksy(surf.format, h); 851 852 switch (surf.mode) { 853 case ARRAY_2D_TILED_THIN1: 854 if (surf.nbx < surf.palign || surf.nby < surf.halign) { 855 surf.mode = ARRAY_1D_TILED_THIN1; 856 } 857 /* recompute alignment */ 858 evergreen_surface_check(p, &surf, NULL); 859 break; 860 case ARRAY_LINEAR_GENERAL: 861 case ARRAY_LINEAR_ALIGNED: 862 case ARRAY_1D_TILED_THIN1: 863 break; 864 default: 865 dev_warn(p->dev, "%s:%d invalid array mode %d\n", 866 __func__, __LINE__, surf.mode); 867 return -EINVAL; 868 } 869 surf.nbx = ALIGN(surf.nbx, surf.palign); 870 surf.nby = ALIGN(surf.nby, surf.halign); 871 872 r = evergreen_surface_check(p, &surf, "mipmap"); 873 if (r) { 874 return r; 875 } 876 877 if (dim == SQ_TEX_DIM_3D) { 878 moffset += surf.layer_size * d; 879 } else { 880 moffset += surf.layer_size * mslice; 881 } 882 if (moffset > radeon_bo_size(mipmap)) { 883 dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, " 884 "offset %ld, coffset %ld, max layer %d, depth %d, " 885 "bo size %ld) level0 (%d %d %d)\n", 886 __func__, __LINE__, i, surf.layer_size, 887 (unsigned long)texdw[3] << 8, moffset, mslice, 888 d, radeon_bo_size(mipmap), 889 width, height, depth); 890 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", 891 __func__, __LINE__, surf.nbx, surf.nby, 892 surf.mode, surf.bpe, surf.nsamples, 893 surf.bankw, surf.bankh, 894 surf.tsplit, surf.mtilea); 895 return -EINVAL; 896 } 897 } 898 899 return 0; 900 } 901 902 static int evergreen_cs_track_check(struct radeon_cs_parser *p) 903 { 904 struct evergreen_cs_track *track = p->track; 905 unsigned tmp, i; 906 int r; 907 unsigned buffer_mask = 0; 908 909 /* check streamout */ 910 if (track->streamout_dirty && track->vgt_strmout_config) { 911 for (i = 0; i < 4; i++) { 912 if (track->vgt_strmout_config & (1 << i)) { 913 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf; 914 } 915 } 916 917 for (i = 0; i < 4; i++) { 918 if (buffer_mask & (1 << i)) { 919 if (track->vgt_strmout_bo[i]) { 920 u64 offset = (u64)track->vgt_strmout_bo_offset[i] + 921 (u64)track->vgt_strmout_size[i]; 922 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) { 923 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n", 924 i, offset, 925 radeon_bo_size(track->vgt_strmout_bo[i])); 926 return -EINVAL; 927 } 928 } else { 929 dev_warn(p->dev, "No buffer for streamout %d\n", i); 930 return -EINVAL; 931 } 932 } 933 } 934 track->streamout_dirty = false; 935 } 936 937 if (track->sx_misc_kill_all_prims) 938 return 0; 939 940 /* check that we have a cb for each enabled target 941 */ 942 if (track->cb_dirty) { 943 tmp = track->cb_target_mask; 944 for (i = 0; i < 8; i++) { 945 if ((tmp >> (i * 4)) & 0xF) { 946 /* at least one component is enabled */ 947 if (track->cb_color_bo[i] == NULL) { 948 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", 949 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i); 950 return -EINVAL; 951 } 952 /* check cb */ 953 r = evergreen_cs_track_validate_cb(p, i); 954 if (r) { 955 return r; 956 } 957 } 958 } 959 track->cb_dirty = false; 960 } 961 962 if (track->db_dirty) { 963 /* Check stencil buffer */ 964 if (G_028800_STENCIL_ENABLE(track->db_depth_control)) { 965 r = evergreen_cs_track_validate_stencil(p); 966 if (r) 967 return r; 968 } 969 /* Check depth buffer */ 970 if (G_028800_Z_ENABLE(track->db_depth_control)) { 971 r = evergreen_cs_track_validate_depth(p); 972 if (r) 973 return r; 974 } 975 track->db_dirty = false; 976 } 977 978 return 0; 979 } 980 981 /** 982 * evergreen_cs_packet_parse() - parse cp packet and point ib index to next packet 983 * @parser: parser structure holding parsing context. 984 * @pkt: where to store packet informations 985 * 986 * Assume that chunk_ib_index is properly set. Will return -EINVAL 987 * if packet is bigger than remaining ib size. or if packets is unknown. 988 **/ 989 int evergreen_cs_packet_parse(struct radeon_cs_parser *p, 990 struct radeon_cs_packet *pkt, 991 unsigned idx) 992 { 993 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 994 uint32_t header; 995 996 if (idx >= ib_chunk->length_dw) { 997 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 998 idx, ib_chunk->length_dw); 999 return -EINVAL; 1000 } 1001 header = radeon_get_ib_value(p, idx); 1002 pkt->idx = idx; 1003 pkt->type = CP_PACKET_GET_TYPE(header); 1004 pkt->count = CP_PACKET_GET_COUNT(header); 1005 pkt->one_reg_wr = 0; 1006 switch (pkt->type) { 1007 case PACKET_TYPE0: 1008 pkt->reg = CP_PACKET0_GET_REG(header); 1009 break; 1010 case PACKET_TYPE3: 1011 pkt->opcode = CP_PACKET3_GET_OPCODE(header); 1012 break; 1013 case PACKET_TYPE2: 1014 pkt->count = -1; 1015 break; 1016 default: 1017 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 1018 return -EINVAL; 1019 } 1020 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 1021 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 1022 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 1023 return -EINVAL; 1024 } 1025 return 0; 1026 } 1027 1028 /** 1029 * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3 1030 * @parser: parser structure holding parsing context. 1031 * @data: pointer to relocation data 1032 * @offset_start: starting offset 1033 * @offset_mask: offset mask (to align start offset on) 1034 * @reloc: reloc informations 1035 * 1036 * Check next packet is relocation packet3, do bo validation and compute 1037 * GPU offset using the provided start. 1038 **/ 1039 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p, 1040 struct radeon_cs_reloc **cs_reloc) 1041 { 1042 struct radeon_cs_chunk *relocs_chunk; 1043 struct radeon_cs_packet p3reloc; 1044 unsigned idx; 1045 int r; 1046 1047 if (p->chunk_relocs_idx == -1) { 1048 DRM_ERROR("No relocation chunk !\n"); 1049 return -EINVAL; 1050 } 1051 *cs_reloc = NULL; 1052 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 1053 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx); 1054 if (r) { 1055 return r; 1056 } 1057 p->idx += p3reloc.count + 2; 1058 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 1059 DRM_ERROR("No packet3 for relocation for packet at %d.\n", 1060 p3reloc.idx); 1061 return -EINVAL; 1062 } 1063 idx = radeon_get_ib_value(p, p3reloc.idx + 1); 1064 if (idx >= relocs_chunk->length_dw) { 1065 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 1066 idx, relocs_chunk->length_dw); 1067 return -EINVAL; 1068 } 1069 /* FIXME: we assume reloc size is 4 dwords */ 1070 *cs_reloc = p->relocs_ptr[(idx / 4)]; 1071 return 0; 1072 } 1073 1074 /** 1075 * evergreen_cs_packet_next_vline() - parse userspace VLINE packet 1076 * @parser: parser structure holding parsing context. 1077 * 1078 * Userspace sends a special sequence for VLINE waits. 1079 * PACKET0 - VLINE_START_END + value 1080 * PACKET3 - WAIT_REG_MEM poll vline status reg 1081 * RELOC (P3) - crtc_id in reloc. 1082 * 1083 * This function parses this and relocates the VLINE START END 1084 * and WAIT_REG_MEM packets to the correct crtc. 1085 * It also detects a switched off crtc and nulls out the 1086 * wait in that case. 1087 */ 1088 static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p) 1089 { 1090 struct drm_mode_object *obj; 1091 struct drm_crtc *crtc; 1092 struct radeon_crtc *radeon_crtc; 1093 struct radeon_cs_packet p3reloc, wait_reg_mem; 1094 int crtc_id; 1095 int r; 1096 uint32_t header, h_idx, reg, wait_reg_mem_info; 1097 volatile uint32_t *ib; 1098 1099 ib = p->ib.ptr; 1100 1101 /* parse the WAIT_REG_MEM */ 1102 r = evergreen_cs_packet_parse(p, &wait_reg_mem, p->idx); 1103 if (r) 1104 return r; 1105 1106 /* check its a WAIT_REG_MEM */ 1107 if (wait_reg_mem.type != PACKET_TYPE3 || 1108 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { 1109 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); 1110 return -EINVAL; 1111 } 1112 1113 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); 1114 /* bit 4 is reg (0) or mem (1) */ 1115 if (wait_reg_mem_info & 0x10) { 1116 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n"); 1117 return -EINVAL; 1118 } 1119 /* waiting for value to be equal */ 1120 if ((wait_reg_mem_info & 0x7) != 0x3) { 1121 DRM_ERROR("vline WAIT_REG_MEM function not equal\n"); 1122 return -EINVAL; 1123 } 1124 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) { 1125 DRM_ERROR("vline WAIT_REG_MEM bad reg\n"); 1126 return -EINVAL; 1127 } 1128 1129 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) { 1130 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n"); 1131 return -EINVAL; 1132 } 1133 1134 /* jump over the NOP */ 1135 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); 1136 if (r) 1137 return r; 1138 1139 h_idx = p->idx - 2; 1140 p->idx += wait_reg_mem.count + 2; 1141 p->idx += p3reloc.count + 2; 1142 1143 header = radeon_get_ib_value(p, h_idx); 1144 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); 1145 reg = CP_PACKET0_GET_REG(header); 1146 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1147 if (!obj) { 1148 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1149 return -EINVAL; 1150 } 1151 crtc = obj_to_crtc(obj); 1152 radeon_crtc = to_radeon_crtc(crtc); 1153 crtc_id = radeon_crtc->crtc_id; 1154 1155 if (!crtc->enabled) { 1156 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */ 1157 ib[h_idx + 2] = PACKET2(0); 1158 ib[h_idx + 3] = PACKET2(0); 1159 ib[h_idx + 4] = PACKET2(0); 1160 ib[h_idx + 5] = PACKET2(0); 1161 ib[h_idx + 6] = PACKET2(0); 1162 ib[h_idx + 7] = PACKET2(0); 1163 ib[h_idx + 8] = PACKET2(0); 1164 } else { 1165 switch (reg) { 1166 case EVERGREEN_VLINE_START_END: 1167 header &= ~R600_CP_PACKET0_REG_MASK; 1168 header |= (EVERGREEN_VLINE_START_END + radeon_crtc->crtc_offset) >> 2; 1169 ib[h_idx] = header; 1170 ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2; 1171 break; 1172 default: 1173 DRM_ERROR("unknown crtc reloc\n"); 1174 return -EINVAL; 1175 } 1176 } 1177 return 0; 1178 } 1179 1180 static int evergreen_packet0_check(struct radeon_cs_parser *p, 1181 struct radeon_cs_packet *pkt, 1182 unsigned idx, unsigned reg) 1183 { 1184 int r; 1185 1186 switch (reg) { 1187 case EVERGREEN_VLINE_START_END: 1188 r = evergreen_cs_packet_parse_vline(p); 1189 if (r) { 1190 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1191 idx, reg); 1192 return r; 1193 } 1194 break; 1195 default: 1196 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1197 reg, idx); 1198 return -EINVAL; 1199 } 1200 return 0; 1201 } 1202 1203 static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p, 1204 struct radeon_cs_packet *pkt) 1205 { 1206 unsigned reg, i; 1207 unsigned idx; 1208 int r; 1209 1210 idx = pkt->idx + 1; 1211 reg = pkt->reg; 1212 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { 1213 r = evergreen_packet0_check(p, pkt, idx, reg); 1214 if (r) { 1215 return r; 1216 } 1217 } 1218 return 0; 1219 } 1220 1221 /** 1222 * evergreen_cs_check_reg() - check if register is authorized or not 1223 * @parser: parser structure holding parsing context 1224 * @reg: register we are testing 1225 * @idx: index into the cs buffer 1226 * 1227 * This function will test against evergreen_reg_safe_bm and return 0 1228 * if register is safe. If register is not flag as safe this function 1229 * will test it against a list of register needind special handling. 1230 */ 1231 static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 1232 { 1233 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track; 1234 struct radeon_cs_reloc *reloc; 1235 u32 last_reg; 1236 u32 m, i, tmp, *ib; 1237 int r; 1238 1239 if (p->rdev->family >= CHIP_CAYMAN) 1240 last_reg = ARRAY_SIZE(cayman_reg_safe_bm); 1241 else 1242 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm); 1243 1244 i = (reg >> 7); 1245 if (i >= last_reg) { 1246 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1247 return -EINVAL; 1248 } 1249 m = 1 << ((reg >> 2) & 31); 1250 if (p->rdev->family >= CHIP_CAYMAN) { 1251 if (!(cayman_reg_safe_bm[i] & m)) 1252 return 0; 1253 } else { 1254 if (!(evergreen_reg_safe_bm[i] & m)) 1255 return 0; 1256 } 1257 ib = p->ib.ptr; 1258 switch (reg) { 1259 /* force following reg to 0 in an attempt to disable out buffer 1260 * which will need us to better understand how it works to perform 1261 * security check on it (Jerome) 1262 */ 1263 case SQ_ESGS_RING_SIZE: 1264 case SQ_GSVS_RING_SIZE: 1265 case SQ_ESTMP_RING_SIZE: 1266 case SQ_GSTMP_RING_SIZE: 1267 case SQ_HSTMP_RING_SIZE: 1268 case SQ_LSTMP_RING_SIZE: 1269 case SQ_PSTMP_RING_SIZE: 1270 case SQ_VSTMP_RING_SIZE: 1271 case SQ_ESGS_RING_ITEMSIZE: 1272 case SQ_ESTMP_RING_ITEMSIZE: 1273 case SQ_GSTMP_RING_ITEMSIZE: 1274 case SQ_GSVS_RING_ITEMSIZE: 1275 case SQ_GS_VERT_ITEMSIZE: 1276 case SQ_GS_VERT_ITEMSIZE_1: 1277 case SQ_GS_VERT_ITEMSIZE_2: 1278 case SQ_GS_VERT_ITEMSIZE_3: 1279 case SQ_GSVS_RING_OFFSET_1: 1280 case SQ_GSVS_RING_OFFSET_2: 1281 case SQ_GSVS_RING_OFFSET_3: 1282 case SQ_HSTMP_RING_ITEMSIZE: 1283 case SQ_LSTMP_RING_ITEMSIZE: 1284 case SQ_PSTMP_RING_ITEMSIZE: 1285 case SQ_VSTMP_RING_ITEMSIZE: 1286 case VGT_TF_RING_SIZE: 1287 /* get value to populate the IB don't remove */ 1288 /*tmp =radeon_get_ib_value(p, idx); 1289 ib[idx] = 0;*/ 1290 break; 1291 case SQ_ESGS_RING_BASE: 1292 case SQ_GSVS_RING_BASE: 1293 case SQ_ESTMP_RING_BASE: 1294 case SQ_GSTMP_RING_BASE: 1295 case SQ_HSTMP_RING_BASE: 1296 case SQ_LSTMP_RING_BASE: 1297 case SQ_PSTMP_RING_BASE: 1298 case SQ_VSTMP_RING_BASE: 1299 r = evergreen_cs_packet_next_reloc(p, &reloc); 1300 if (r) { 1301 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1302 "0x%04X\n", reg); 1303 return -EINVAL; 1304 } 1305 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1306 break; 1307 case DB_DEPTH_CONTROL: 1308 track->db_depth_control = radeon_get_ib_value(p, idx); 1309 track->db_dirty = true; 1310 break; 1311 case CAYMAN_DB_EQAA: 1312 if (p->rdev->family < CHIP_CAYMAN) { 1313 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1314 "0x%04X\n", reg); 1315 return -EINVAL; 1316 } 1317 break; 1318 case CAYMAN_DB_DEPTH_INFO: 1319 if (p->rdev->family < CHIP_CAYMAN) { 1320 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1321 "0x%04X\n", reg); 1322 return -EINVAL; 1323 } 1324 break; 1325 case DB_Z_INFO: 1326 track->db_z_info = radeon_get_ib_value(p, idx); 1327 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1328 r = evergreen_cs_packet_next_reloc(p, &reloc); 1329 if (r) { 1330 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1331 "0x%04X\n", reg); 1332 return -EINVAL; 1333 } 1334 ib[idx] &= ~Z_ARRAY_MODE(0xf); 1335 track->db_z_info &= ~Z_ARRAY_MODE(0xf); 1336 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); 1337 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); 1338 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 1339 unsigned bankw, bankh, mtaspect, tile_split; 1340 1341 evergreen_tiling_fields(reloc->lobj.tiling_flags, 1342 &bankw, &bankh, &mtaspect, 1343 &tile_split); 1344 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); 1345 ib[idx] |= DB_TILE_SPLIT(tile_split) | 1346 DB_BANK_WIDTH(bankw) | 1347 DB_BANK_HEIGHT(bankh) | 1348 DB_MACRO_TILE_ASPECT(mtaspect); 1349 } 1350 } 1351 track->db_dirty = true; 1352 break; 1353 case DB_STENCIL_INFO: 1354 track->db_s_info = radeon_get_ib_value(p, idx); 1355 track->db_dirty = true; 1356 break; 1357 case DB_DEPTH_VIEW: 1358 track->db_depth_view = radeon_get_ib_value(p, idx); 1359 track->db_dirty = true; 1360 break; 1361 case DB_DEPTH_SIZE: 1362 track->db_depth_size = radeon_get_ib_value(p, idx); 1363 track->db_dirty = true; 1364 break; 1365 case R_02805C_DB_DEPTH_SLICE: 1366 track->db_depth_slice = radeon_get_ib_value(p, idx); 1367 track->db_dirty = true; 1368 break; 1369 case DB_Z_READ_BASE: 1370 r = evergreen_cs_packet_next_reloc(p, &reloc); 1371 if (r) { 1372 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1373 "0x%04X\n", reg); 1374 return -EINVAL; 1375 } 1376 track->db_z_read_offset = radeon_get_ib_value(p, idx); 1377 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1378 track->db_z_read_bo = reloc->robj; 1379 track->db_dirty = true; 1380 break; 1381 case DB_Z_WRITE_BASE: 1382 r = evergreen_cs_packet_next_reloc(p, &reloc); 1383 if (r) { 1384 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1385 "0x%04X\n", reg); 1386 return -EINVAL; 1387 } 1388 track->db_z_write_offset = radeon_get_ib_value(p, idx); 1389 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1390 track->db_z_write_bo = reloc->robj; 1391 track->db_dirty = true; 1392 break; 1393 case DB_STENCIL_READ_BASE: 1394 r = evergreen_cs_packet_next_reloc(p, &reloc); 1395 if (r) { 1396 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1397 "0x%04X\n", reg); 1398 return -EINVAL; 1399 } 1400 track->db_s_read_offset = radeon_get_ib_value(p, idx); 1401 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1402 track->db_s_read_bo = reloc->robj; 1403 track->db_dirty = true; 1404 break; 1405 case DB_STENCIL_WRITE_BASE: 1406 r = evergreen_cs_packet_next_reloc(p, &reloc); 1407 if (r) { 1408 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1409 "0x%04X\n", reg); 1410 return -EINVAL; 1411 } 1412 track->db_s_write_offset = radeon_get_ib_value(p, idx); 1413 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1414 track->db_s_write_bo = reloc->robj; 1415 track->db_dirty = true; 1416 break; 1417 case VGT_STRMOUT_CONFIG: 1418 track->vgt_strmout_config = radeon_get_ib_value(p, idx); 1419 track->streamout_dirty = true; 1420 break; 1421 case VGT_STRMOUT_BUFFER_CONFIG: 1422 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); 1423 track->streamout_dirty = true; 1424 break; 1425 case VGT_STRMOUT_BUFFER_BASE_0: 1426 case VGT_STRMOUT_BUFFER_BASE_1: 1427 case VGT_STRMOUT_BUFFER_BASE_2: 1428 case VGT_STRMOUT_BUFFER_BASE_3: 1429 r = evergreen_cs_packet_next_reloc(p, &reloc); 1430 if (r) { 1431 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1432 "0x%04X\n", reg); 1433 return -EINVAL; 1434 } 1435 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16; 1436 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; 1437 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1438 track->vgt_strmout_bo[tmp] = reloc->robj; 1439 track->streamout_dirty = true; 1440 break; 1441 case VGT_STRMOUT_BUFFER_SIZE_0: 1442 case VGT_STRMOUT_BUFFER_SIZE_1: 1443 case VGT_STRMOUT_BUFFER_SIZE_2: 1444 case VGT_STRMOUT_BUFFER_SIZE_3: 1445 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16; 1446 /* size in register is DWs, convert to bytes */ 1447 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; 1448 track->streamout_dirty = true; 1449 break; 1450 case CP_COHER_BASE: 1451 r = evergreen_cs_packet_next_reloc(p, &reloc); 1452 if (r) { 1453 dev_warn(p->dev, "missing reloc for CP_COHER_BASE " 1454 "0x%04X\n", reg); 1455 return -EINVAL; 1456 } 1457 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1458 case CB_TARGET_MASK: 1459 track->cb_target_mask = radeon_get_ib_value(p, idx); 1460 track->cb_dirty = true; 1461 break; 1462 case CB_SHADER_MASK: 1463 track->cb_shader_mask = radeon_get_ib_value(p, idx); 1464 track->cb_dirty = true; 1465 break; 1466 case PA_SC_AA_CONFIG: 1467 if (p->rdev->family >= CHIP_CAYMAN) { 1468 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1469 "0x%04X\n", reg); 1470 return -EINVAL; 1471 } 1472 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK; 1473 track->nsamples = 1 << tmp; 1474 break; 1475 case CAYMAN_PA_SC_AA_CONFIG: 1476 if (p->rdev->family < CHIP_CAYMAN) { 1477 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1478 "0x%04X\n", reg); 1479 return -EINVAL; 1480 } 1481 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK; 1482 track->nsamples = 1 << tmp; 1483 break; 1484 case CB_COLOR0_VIEW: 1485 case CB_COLOR1_VIEW: 1486 case CB_COLOR2_VIEW: 1487 case CB_COLOR3_VIEW: 1488 case CB_COLOR4_VIEW: 1489 case CB_COLOR5_VIEW: 1490 case CB_COLOR6_VIEW: 1491 case CB_COLOR7_VIEW: 1492 tmp = (reg - CB_COLOR0_VIEW) / 0x3c; 1493 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); 1494 track->cb_dirty = true; 1495 break; 1496 case CB_COLOR8_VIEW: 1497 case CB_COLOR9_VIEW: 1498 case CB_COLOR10_VIEW: 1499 case CB_COLOR11_VIEW: 1500 tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8; 1501 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); 1502 track->cb_dirty = true; 1503 break; 1504 case CB_COLOR0_INFO: 1505 case CB_COLOR1_INFO: 1506 case CB_COLOR2_INFO: 1507 case CB_COLOR3_INFO: 1508 case CB_COLOR4_INFO: 1509 case CB_COLOR5_INFO: 1510 case CB_COLOR6_INFO: 1511 case CB_COLOR7_INFO: 1512 tmp = (reg - CB_COLOR0_INFO) / 0x3c; 1513 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1514 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1515 r = evergreen_cs_packet_next_reloc(p, &reloc); 1516 if (r) { 1517 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1518 "0x%04X\n", reg); 1519 return -EINVAL; 1520 } 1521 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); 1522 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); 1523 } 1524 track->cb_dirty = true; 1525 break; 1526 case CB_COLOR8_INFO: 1527 case CB_COLOR9_INFO: 1528 case CB_COLOR10_INFO: 1529 case CB_COLOR11_INFO: 1530 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8; 1531 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1532 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1533 r = evergreen_cs_packet_next_reloc(p, &reloc); 1534 if (r) { 1535 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1536 "0x%04X\n", reg); 1537 return -EINVAL; 1538 } 1539 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); 1540 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); 1541 } 1542 track->cb_dirty = true; 1543 break; 1544 case CB_COLOR0_PITCH: 1545 case CB_COLOR1_PITCH: 1546 case CB_COLOR2_PITCH: 1547 case CB_COLOR3_PITCH: 1548 case CB_COLOR4_PITCH: 1549 case CB_COLOR5_PITCH: 1550 case CB_COLOR6_PITCH: 1551 case CB_COLOR7_PITCH: 1552 tmp = (reg - CB_COLOR0_PITCH) / 0x3c; 1553 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); 1554 track->cb_dirty = true; 1555 break; 1556 case CB_COLOR8_PITCH: 1557 case CB_COLOR9_PITCH: 1558 case CB_COLOR10_PITCH: 1559 case CB_COLOR11_PITCH: 1560 tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8; 1561 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); 1562 track->cb_dirty = true; 1563 break; 1564 case CB_COLOR0_SLICE: 1565 case CB_COLOR1_SLICE: 1566 case CB_COLOR2_SLICE: 1567 case CB_COLOR3_SLICE: 1568 case CB_COLOR4_SLICE: 1569 case CB_COLOR5_SLICE: 1570 case CB_COLOR6_SLICE: 1571 case CB_COLOR7_SLICE: 1572 tmp = (reg - CB_COLOR0_SLICE) / 0x3c; 1573 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); 1574 track->cb_color_slice_idx[tmp] = idx; 1575 track->cb_dirty = true; 1576 break; 1577 case CB_COLOR8_SLICE: 1578 case CB_COLOR9_SLICE: 1579 case CB_COLOR10_SLICE: 1580 case CB_COLOR11_SLICE: 1581 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8; 1582 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); 1583 track->cb_color_slice_idx[tmp] = idx; 1584 track->cb_dirty = true; 1585 break; 1586 case CB_COLOR0_ATTRIB: 1587 case CB_COLOR1_ATTRIB: 1588 case CB_COLOR2_ATTRIB: 1589 case CB_COLOR3_ATTRIB: 1590 case CB_COLOR4_ATTRIB: 1591 case CB_COLOR5_ATTRIB: 1592 case CB_COLOR6_ATTRIB: 1593 case CB_COLOR7_ATTRIB: 1594 r = evergreen_cs_packet_next_reloc(p, &reloc); 1595 if (r) { 1596 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1597 "0x%04X\n", reg); 1598 return -EINVAL; 1599 } 1600 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1601 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 1602 unsigned bankw, bankh, mtaspect, tile_split; 1603 1604 evergreen_tiling_fields(reloc->lobj.tiling_flags, 1605 &bankw, &bankh, &mtaspect, 1606 &tile_split); 1607 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); 1608 ib[idx] |= CB_TILE_SPLIT(tile_split) | 1609 CB_BANK_WIDTH(bankw) | 1610 CB_BANK_HEIGHT(bankh) | 1611 CB_MACRO_TILE_ASPECT(mtaspect); 1612 } 1613 } 1614 tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c); 1615 track->cb_color_attrib[tmp] = ib[idx]; 1616 track->cb_dirty = true; 1617 break; 1618 case CB_COLOR8_ATTRIB: 1619 case CB_COLOR9_ATTRIB: 1620 case CB_COLOR10_ATTRIB: 1621 case CB_COLOR11_ATTRIB: 1622 r = evergreen_cs_packet_next_reloc(p, &reloc); 1623 if (r) { 1624 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1625 "0x%04X\n", reg); 1626 return -EINVAL; 1627 } 1628 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1629 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 1630 unsigned bankw, bankh, mtaspect, tile_split; 1631 1632 evergreen_tiling_fields(reloc->lobj.tiling_flags, 1633 &bankw, &bankh, &mtaspect, 1634 &tile_split); 1635 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); 1636 ib[idx] |= CB_TILE_SPLIT(tile_split) | 1637 CB_BANK_WIDTH(bankw) | 1638 CB_BANK_HEIGHT(bankh) | 1639 CB_MACRO_TILE_ASPECT(mtaspect); 1640 } 1641 } 1642 tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8; 1643 track->cb_color_attrib[tmp] = ib[idx]; 1644 track->cb_dirty = true; 1645 break; 1646 case CB_COLOR0_FMASK: 1647 case CB_COLOR1_FMASK: 1648 case CB_COLOR2_FMASK: 1649 case CB_COLOR3_FMASK: 1650 case CB_COLOR4_FMASK: 1651 case CB_COLOR5_FMASK: 1652 case CB_COLOR6_FMASK: 1653 case CB_COLOR7_FMASK: 1654 tmp = (reg - CB_COLOR0_FMASK) / 0x3c; 1655 r = evergreen_cs_packet_next_reloc(p, &reloc); 1656 if (r) { 1657 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1658 return -EINVAL; 1659 } 1660 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1661 track->cb_color_fmask_bo[tmp] = reloc->robj; 1662 break; 1663 case CB_COLOR0_CMASK: 1664 case CB_COLOR1_CMASK: 1665 case CB_COLOR2_CMASK: 1666 case CB_COLOR3_CMASK: 1667 case CB_COLOR4_CMASK: 1668 case CB_COLOR5_CMASK: 1669 case CB_COLOR6_CMASK: 1670 case CB_COLOR7_CMASK: 1671 tmp = (reg - CB_COLOR0_CMASK) / 0x3c; 1672 r = evergreen_cs_packet_next_reloc(p, &reloc); 1673 if (r) { 1674 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1675 return -EINVAL; 1676 } 1677 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1678 track->cb_color_cmask_bo[tmp] = reloc->robj; 1679 break; 1680 case CB_COLOR0_FMASK_SLICE: 1681 case CB_COLOR1_FMASK_SLICE: 1682 case CB_COLOR2_FMASK_SLICE: 1683 case CB_COLOR3_FMASK_SLICE: 1684 case CB_COLOR4_FMASK_SLICE: 1685 case CB_COLOR5_FMASK_SLICE: 1686 case CB_COLOR6_FMASK_SLICE: 1687 case CB_COLOR7_FMASK_SLICE: 1688 tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c; 1689 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); 1690 break; 1691 case CB_COLOR0_CMASK_SLICE: 1692 case CB_COLOR1_CMASK_SLICE: 1693 case CB_COLOR2_CMASK_SLICE: 1694 case CB_COLOR3_CMASK_SLICE: 1695 case CB_COLOR4_CMASK_SLICE: 1696 case CB_COLOR5_CMASK_SLICE: 1697 case CB_COLOR6_CMASK_SLICE: 1698 case CB_COLOR7_CMASK_SLICE: 1699 tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c; 1700 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); 1701 break; 1702 case CB_COLOR0_BASE: 1703 case CB_COLOR1_BASE: 1704 case CB_COLOR2_BASE: 1705 case CB_COLOR3_BASE: 1706 case CB_COLOR4_BASE: 1707 case CB_COLOR5_BASE: 1708 case CB_COLOR6_BASE: 1709 case CB_COLOR7_BASE: 1710 r = evergreen_cs_packet_next_reloc(p, &reloc); 1711 if (r) { 1712 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1713 "0x%04X\n", reg); 1714 return -EINVAL; 1715 } 1716 tmp = (reg - CB_COLOR0_BASE) / 0x3c; 1717 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); 1718 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1719 track->cb_color_bo[tmp] = reloc->robj; 1720 track->cb_dirty = true; 1721 break; 1722 case CB_COLOR8_BASE: 1723 case CB_COLOR9_BASE: 1724 case CB_COLOR10_BASE: 1725 case CB_COLOR11_BASE: 1726 r = evergreen_cs_packet_next_reloc(p, &reloc); 1727 if (r) { 1728 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1729 "0x%04X\n", reg); 1730 return -EINVAL; 1731 } 1732 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8; 1733 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); 1734 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1735 track->cb_color_bo[tmp] = reloc->robj; 1736 track->cb_dirty = true; 1737 break; 1738 case DB_HTILE_DATA_BASE: 1739 r = evergreen_cs_packet_next_reloc(p, &reloc); 1740 if (r) { 1741 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1742 "0x%04X\n", reg); 1743 return -EINVAL; 1744 } 1745 track->htile_offset = radeon_get_ib_value(p, idx); 1746 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1747 track->htile_bo = reloc->robj; 1748 track->db_dirty = true; 1749 break; 1750 case DB_HTILE_SURFACE: 1751 /* 8x8 only */ 1752 track->htile_surface = radeon_get_ib_value(p, idx); 1753 track->db_dirty = true; 1754 break; 1755 case CB_IMMED0_BASE: 1756 case CB_IMMED1_BASE: 1757 case CB_IMMED2_BASE: 1758 case CB_IMMED3_BASE: 1759 case CB_IMMED4_BASE: 1760 case CB_IMMED5_BASE: 1761 case CB_IMMED6_BASE: 1762 case CB_IMMED7_BASE: 1763 case CB_IMMED8_BASE: 1764 case CB_IMMED9_BASE: 1765 case CB_IMMED10_BASE: 1766 case CB_IMMED11_BASE: 1767 case SQ_PGM_START_FS: 1768 case SQ_PGM_START_ES: 1769 case SQ_PGM_START_VS: 1770 case SQ_PGM_START_GS: 1771 case SQ_PGM_START_PS: 1772 case SQ_PGM_START_HS: 1773 case SQ_PGM_START_LS: 1774 case SQ_CONST_MEM_BASE: 1775 case SQ_ALU_CONST_CACHE_GS_0: 1776 case SQ_ALU_CONST_CACHE_GS_1: 1777 case SQ_ALU_CONST_CACHE_GS_2: 1778 case SQ_ALU_CONST_CACHE_GS_3: 1779 case SQ_ALU_CONST_CACHE_GS_4: 1780 case SQ_ALU_CONST_CACHE_GS_5: 1781 case SQ_ALU_CONST_CACHE_GS_6: 1782 case SQ_ALU_CONST_CACHE_GS_7: 1783 case SQ_ALU_CONST_CACHE_GS_8: 1784 case SQ_ALU_CONST_CACHE_GS_9: 1785 case SQ_ALU_CONST_CACHE_GS_10: 1786 case SQ_ALU_CONST_CACHE_GS_11: 1787 case SQ_ALU_CONST_CACHE_GS_12: 1788 case SQ_ALU_CONST_CACHE_GS_13: 1789 case SQ_ALU_CONST_CACHE_GS_14: 1790 case SQ_ALU_CONST_CACHE_GS_15: 1791 case SQ_ALU_CONST_CACHE_PS_0: 1792 case SQ_ALU_CONST_CACHE_PS_1: 1793 case SQ_ALU_CONST_CACHE_PS_2: 1794 case SQ_ALU_CONST_CACHE_PS_3: 1795 case SQ_ALU_CONST_CACHE_PS_4: 1796 case SQ_ALU_CONST_CACHE_PS_5: 1797 case SQ_ALU_CONST_CACHE_PS_6: 1798 case SQ_ALU_CONST_CACHE_PS_7: 1799 case SQ_ALU_CONST_CACHE_PS_8: 1800 case SQ_ALU_CONST_CACHE_PS_9: 1801 case SQ_ALU_CONST_CACHE_PS_10: 1802 case SQ_ALU_CONST_CACHE_PS_11: 1803 case SQ_ALU_CONST_CACHE_PS_12: 1804 case SQ_ALU_CONST_CACHE_PS_13: 1805 case SQ_ALU_CONST_CACHE_PS_14: 1806 case SQ_ALU_CONST_CACHE_PS_15: 1807 case SQ_ALU_CONST_CACHE_VS_0: 1808 case SQ_ALU_CONST_CACHE_VS_1: 1809 case SQ_ALU_CONST_CACHE_VS_2: 1810 case SQ_ALU_CONST_CACHE_VS_3: 1811 case SQ_ALU_CONST_CACHE_VS_4: 1812 case SQ_ALU_CONST_CACHE_VS_5: 1813 case SQ_ALU_CONST_CACHE_VS_6: 1814 case SQ_ALU_CONST_CACHE_VS_7: 1815 case SQ_ALU_CONST_CACHE_VS_8: 1816 case SQ_ALU_CONST_CACHE_VS_9: 1817 case SQ_ALU_CONST_CACHE_VS_10: 1818 case SQ_ALU_CONST_CACHE_VS_11: 1819 case SQ_ALU_CONST_CACHE_VS_12: 1820 case SQ_ALU_CONST_CACHE_VS_13: 1821 case SQ_ALU_CONST_CACHE_VS_14: 1822 case SQ_ALU_CONST_CACHE_VS_15: 1823 case SQ_ALU_CONST_CACHE_HS_0: 1824 case SQ_ALU_CONST_CACHE_HS_1: 1825 case SQ_ALU_CONST_CACHE_HS_2: 1826 case SQ_ALU_CONST_CACHE_HS_3: 1827 case SQ_ALU_CONST_CACHE_HS_4: 1828 case SQ_ALU_CONST_CACHE_HS_5: 1829 case SQ_ALU_CONST_CACHE_HS_6: 1830 case SQ_ALU_CONST_CACHE_HS_7: 1831 case SQ_ALU_CONST_CACHE_HS_8: 1832 case SQ_ALU_CONST_CACHE_HS_9: 1833 case SQ_ALU_CONST_CACHE_HS_10: 1834 case SQ_ALU_CONST_CACHE_HS_11: 1835 case SQ_ALU_CONST_CACHE_HS_12: 1836 case SQ_ALU_CONST_CACHE_HS_13: 1837 case SQ_ALU_CONST_CACHE_HS_14: 1838 case SQ_ALU_CONST_CACHE_HS_15: 1839 case SQ_ALU_CONST_CACHE_LS_0: 1840 case SQ_ALU_CONST_CACHE_LS_1: 1841 case SQ_ALU_CONST_CACHE_LS_2: 1842 case SQ_ALU_CONST_CACHE_LS_3: 1843 case SQ_ALU_CONST_CACHE_LS_4: 1844 case SQ_ALU_CONST_CACHE_LS_5: 1845 case SQ_ALU_CONST_CACHE_LS_6: 1846 case SQ_ALU_CONST_CACHE_LS_7: 1847 case SQ_ALU_CONST_CACHE_LS_8: 1848 case SQ_ALU_CONST_CACHE_LS_9: 1849 case SQ_ALU_CONST_CACHE_LS_10: 1850 case SQ_ALU_CONST_CACHE_LS_11: 1851 case SQ_ALU_CONST_CACHE_LS_12: 1852 case SQ_ALU_CONST_CACHE_LS_13: 1853 case SQ_ALU_CONST_CACHE_LS_14: 1854 case SQ_ALU_CONST_CACHE_LS_15: 1855 r = evergreen_cs_packet_next_reloc(p, &reloc); 1856 if (r) { 1857 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1858 "0x%04X\n", reg); 1859 return -EINVAL; 1860 } 1861 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1862 break; 1863 case SX_MEMORY_EXPORT_BASE: 1864 if (p->rdev->family >= CHIP_CAYMAN) { 1865 dev_warn(p->dev, "bad SET_CONFIG_REG " 1866 "0x%04X\n", reg); 1867 return -EINVAL; 1868 } 1869 r = evergreen_cs_packet_next_reloc(p, &reloc); 1870 if (r) { 1871 dev_warn(p->dev, "bad SET_CONFIG_REG " 1872 "0x%04X\n", reg); 1873 return -EINVAL; 1874 } 1875 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1876 break; 1877 case CAYMAN_SX_SCATTER_EXPORT_BASE: 1878 if (p->rdev->family < CHIP_CAYMAN) { 1879 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1880 "0x%04X\n", reg); 1881 return -EINVAL; 1882 } 1883 r = evergreen_cs_packet_next_reloc(p, &reloc); 1884 if (r) { 1885 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1886 "0x%04X\n", reg); 1887 return -EINVAL; 1888 } 1889 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1890 break; 1891 case SX_MISC: 1892 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; 1893 break; 1894 default: 1895 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1896 return -EINVAL; 1897 } 1898 return 0; 1899 } 1900 1901 static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 1902 { 1903 u32 last_reg, m, i; 1904 1905 if (p->rdev->family >= CHIP_CAYMAN) 1906 last_reg = ARRAY_SIZE(cayman_reg_safe_bm); 1907 else 1908 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm); 1909 1910 i = (reg >> 7); 1911 if (i >= last_reg) { 1912 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1913 return false; 1914 } 1915 m = 1 << ((reg >> 2) & 31); 1916 if (p->rdev->family >= CHIP_CAYMAN) { 1917 if (!(cayman_reg_safe_bm[i] & m)) 1918 return true; 1919 } else { 1920 if (!(evergreen_reg_safe_bm[i] & m)) 1921 return true; 1922 } 1923 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); 1924 return false; 1925 } 1926 1927 static int evergreen_packet3_check(struct radeon_cs_parser *p, 1928 struct radeon_cs_packet *pkt) 1929 { 1930 struct radeon_cs_reloc *reloc; 1931 struct evergreen_cs_track *track; 1932 volatile u32 *ib; 1933 unsigned idx; 1934 unsigned i; 1935 unsigned start_reg, end_reg, reg; 1936 int r; 1937 u32 idx_value; 1938 1939 track = (struct evergreen_cs_track *)p->track; 1940 ib = p->ib.ptr; 1941 idx = pkt->idx + 1; 1942 idx_value = radeon_get_ib_value(p, idx); 1943 1944 switch (pkt->opcode) { 1945 case PACKET3_SET_PREDICATION: 1946 { 1947 int pred_op; 1948 int tmp; 1949 uint64_t offset; 1950 1951 if (pkt->count != 1) { 1952 DRM_ERROR("bad SET PREDICATION\n"); 1953 return -EINVAL; 1954 } 1955 1956 tmp = radeon_get_ib_value(p, idx + 1); 1957 pred_op = (tmp >> 16) & 0x7; 1958 1959 /* for the clear predicate operation */ 1960 if (pred_op == 0) 1961 return 0; 1962 1963 if (pred_op > 2) { 1964 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op); 1965 return -EINVAL; 1966 } 1967 1968 r = evergreen_cs_packet_next_reloc(p, &reloc); 1969 if (r) { 1970 DRM_ERROR("bad SET PREDICATION\n"); 1971 return -EINVAL; 1972 } 1973 1974 offset = reloc->lobj.gpu_offset + 1975 (idx_value & 0xfffffff0) + 1976 ((u64)(tmp & 0xff) << 32); 1977 1978 ib[idx + 0] = offset; 1979 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); 1980 } 1981 break; 1982 case PACKET3_CONTEXT_CONTROL: 1983 if (pkt->count != 1) { 1984 DRM_ERROR("bad CONTEXT_CONTROL\n"); 1985 return -EINVAL; 1986 } 1987 break; 1988 case PACKET3_INDEX_TYPE: 1989 case PACKET3_NUM_INSTANCES: 1990 case PACKET3_CLEAR_STATE: 1991 if (pkt->count) { 1992 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n"); 1993 return -EINVAL; 1994 } 1995 break; 1996 case CAYMAN_PACKET3_DEALLOC_STATE: 1997 if (p->rdev->family < CHIP_CAYMAN) { 1998 DRM_ERROR("bad PACKET3_DEALLOC_STATE\n"); 1999 return -EINVAL; 2000 } 2001 if (pkt->count) { 2002 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n"); 2003 return -EINVAL; 2004 } 2005 break; 2006 case PACKET3_INDEX_BASE: 2007 { 2008 uint64_t offset; 2009 2010 if (pkt->count != 1) { 2011 DRM_ERROR("bad INDEX_BASE\n"); 2012 return -EINVAL; 2013 } 2014 r = evergreen_cs_packet_next_reloc(p, &reloc); 2015 if (r) { 2016 DRM_ERROR("bad INDEX_BASE\n"); 2017 return -EINVAL; 2018 } 2019 2020 offset = reloc->lobj.gpu_offset + 2021 idx_value + 2022 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 2023 2024 ib[idx+0] = offset; 2025 ib[idx+1] = upper_32_bits(offset) & 0xff; 2026 2027 r = evergreen_cs_track_check(p); 2028 if (r) { 2029 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2030 return r; 2031 } 2032 break; 2033 } 2034 case PACKET3_DRAW_INDEX: 2035 { 2036 uint64_t offset; 2037 if (pkt->count != 3) { 2038 DRM_ERROR("bad DRAW_INDEX\n"); 2039 return -EINVAL; 2040 } 2041 r = evergreen_cs_packet_next_reloc(p, &reloc); 2042 if (r) { 2043 DRM_ERROR("bad DRAW_INDEX\n"); 2044 return -EINVAL; 2045 } 2046 2047 offset = reloc->lobj.gpu_offset + 2048 idx_value + 2049 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); 2050 2051 ib[idx+0] = offset; 2052 ib[idx+1] = upper_32_bits(offset) & 0xff; 2053 2054 r = evergreen_cs_track_check(p); 2055 if (r) { 2056 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2057 return r; 2058 } 2059 break; 2060 } 2061 case PACKET3_DRAW_INDEX_2: 2062 { 2063 uint64_t offset; 2064 2065 if (pkt->count != 4) { 2066 DRM_ERROR("bad DRAW_INDEX_2\n"); 2067 return -EINVAL; 2068 } 2069 r = evergreen_cs_packet_next_reloc(p, &reloc); 2070 if (r) { 2071 DRM_ERROR("bad DRAW_INDEX_2\n"); 2072 return -EINVAL; 2073 } 2074 2075 offset = reloc->lobj.gpu_offset + 2076 radeon_get_ib_value(p, idx+1) + 2077 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2078 2079 ib[idx+1] = offset; 2080 ib[idx+2] = upper_32_bits(offset) & 0xff; 2081 2082 r = evergreen_cs_track_check(p); 2083 if (r) { 2084 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2085 return r; 2086 } 2087 break; 2088 } 2089 case PACKET3_DRAW_INDEX_AUTO: 2090 if (pkt->count != 1) { 2091 DRM_ERROR("bad DRAW_INDEX_AUTO\n"); 2092 return -EINVAL; 2093 } 2094 r = evergreen_cs_track_check(p); 2095 if (r) { 2096 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 2097 return r; 2098 } 2099 break; 2100 case PACKET3_DRAW_INDEX_MULTI_AUTO: 2101 if (pkt->count != 2) { 2102 DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n"); 2103 return -EINVAL; 2104 } 2105 r = evergreen_cs_track_check(p); 2106 if (r) { 2107 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 2108 return r; 2109 } 2110 break; 2111 case PACKET3_DRAW_INDEX_IMMD: 2112 if (pkt->count < 2) { 2113 DRM_ERROR("bad DRAW_INDEX_IMMD\n"); 2114 return -EINVAL; 2115 } 2116 r = evergreen_cs_track_check(p); 2117 if (r) { 2118 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2119 return r; 2120 } 2121 break; 2122 case PACKET3_DRAW_INDEX_OFFSET: 2123 if (pkt->count != 2) { 2124 DRM_ERROR("bad DRAW_INDEX_OFFSET\n"); 2125 return -EINVAL; 2126 } 2127 r = evergreen_cs_track_check(p); 2128 if (r) { 2129 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2130 return r; 2131 } 2132 break; 2133 case PACKET3_DRAW_INDEX_OFFSET_2: 2134 if (pkt->count != 3) { 2135 DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n"); 2136 return -EINVAL; 2137 } 2138 r = evergreen_cs_track_check(p); 2139 if (r) { 2140 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2141 return r; 2142 } 2143 break; 2144 case PACKET3_DISPATCH_DIRECT: 2145 if (pkt->count != 3) { 2146 DRM_ERROR("bad DISPATCH_DIRECT\n"); 2147 return -EINVAL; 2148 } 2149 r = evergreen_cs_track_check(p); 2150 if (r) { 2151 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); 2152 return r; 2153 } 2154 break; 2155 case PACKET3_DISPATCH_INDIRECT: 2156 if (pkt->count != 1) { 2157 DRM_ERROR("bad DISPATCH_INDIRECT\n"); 2158 return -EINVAL; 2159 } 2160 r = evergreen_cs_packet_next_reloc(p, &reloc); 2161 if (r) { 2162 DRM_ERROR("bad DISPATCH_INDIRECT\n"); 2163 return -EINVAL; 2164 } 2165 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); 2166 r = evergreen_cs_track_check(p); 2167 if (r) { 2168 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); 2169 return r; 2170 } 2171 break; 2172 case PACKET3_WAIT_REG_MEM: 2173 if (pkt->count != 5) { 2174 DRM_ERROR("bad WAIT_REG_MEM\n"); 2175 return -EINVAL; 2176 } 2177 /* bit 4 is reg (0) or mem (1) */ 2178 if (idx_value & 0x10) { 2179 uint64_t offset; 2180 2181 r = evergreen_cs_packet_next_reloc(p, &reloc); 2182 if (r) { 2183 DRM_ERROR("bad WAIT_REG_MEM\n"); 2184 return -EINVAL; 2185 } 2186 2187 offset = reloc->lobj.gpu_offset + 2188 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + 2189 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2190 2191 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); 2192 ib[idx+2] = upper_32_bits(offset) & 0xff; 2193 } 2194 break; 2195 case PACKET3_SURFACE_SYNC: 2196 if (pkt->count != 3) { 2197 DRM_ERROR("bad SURFACE_SYNC\n"); 2198 return -EINVAL; 2199 } 2200 /* 0xffffffff/0x0 is flush all cache flag */ 2201 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || 2202 radeon_get_ib_value(p, idx + 2) != 0) { 2203 r = evergreen_cs_packet_next_reloc(p, &reloc); 2204 if (r) { 2205 DRM_ERROR("bad SURFACE_SYNC\n"); 2206 return -EINVAL; 2207 } 2208 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 2209 } 2210 break; 2211 case PACKET3_EVENT_WRITE: 2212 if (pkt->count != 2 && pkt->count != 0) { 2213 DRM_ERROR("bad EVENT_WRITE\n"); 2214 return -EINVAL; 2215 } 2216 if (pkt->count) { 2217 uint64_t offset; 2218 2219 r = evergreen_cs_packet_next_reloc(p, &reloc); 2220 if (r) { 2221 DRM_ERROR("bad EVENT_WRITE\n"); 2222 return -EINVAL; 2223 } 2224 offset = reloc->lobj.gpu_offset + 2225 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + 2226 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2227 2228 ib[idx+1] = offset & 0xfffffff8; 2229 ib[idx+2] = upper_32_bits(offset) & 0xff; 2230 } 2231 break; 2232 case PACKET3_EVENT_WRITE_EOP: 2233 { 2234 uint64_t offset; 2235 2236 if (pkt->count != 4) { 2237 DRM_ERROR("bad EVENT_WRITE_EOP\n"); 2238 return -EINVAL; 2239 } 2240 r = evergreen_cs_packet_next_reloc(p, &reloc); 2241 if (r) { 2242 DRM_ERROR("bad EVENT_WRITE_EOP\n"); 2243 return -EINVAL; 2244 } 2245 2246 offset = reloc->lobj.gpu_offset + 2247 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + 2248 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2249 2250 ib[idx+1] = offset & 0xfffffffc; 2251 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); 2252 break; 2253 } 2254 case PACKET3_EVENT_WRITE_EOS: 2255 { 2256 uint64_t offset; 2257 2258 if (pkt->count != 3) { 2259 DRM_ERROR("bad EVENT_WRITE_EOS\n"); 2260 return -EINVAL; 2261 } 2262 r = evergreen_cs_packet_next_reloc(p, &reloc); 2263 if (r) { 2264 DRM_ERROR("bad EVENT_WRITE_EOS\n"); 2265 return -EINVAL; 2266 } 2267 2268 offset = reloc->lobj.gpu_offset + 2269 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + 2270 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); 2271 2272 ib[idx+1] = offset & 0xfffffffc; 2273 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); 2274 break; 2275 } 2276 case PACKET3_SET_CONFIG_REG: 2277 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; 2278 end_reg = 4 * pkt->count + start_reg - 4; 2279 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || 2280 (start_reg >= PACKET3_SET_CONFIG_REG_END) || 2281 (end_reg >= PACKET3_SET_CONFIG_REG_END)) { 2282 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); 2283 return -EINVAL; 2284 } 2285 for (i = 0; i < pkt->count; i++) { 2286 reg = start_reg + (4 * i); 2287 r = evergreen_cs_check_reg(p, reg, idx+1+i); 2288 if (r) 2289 return r; 2290 } 2291 break; 2292 case PACKET3_SET_CONTEXT_REG: 2293 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START; 2294 end_reg = 4 * pkt->count + start_reg - 4; 2295 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) || 2296 (start_reg >= PACKET3_SET_CONTEXT_REG_END) || 2297 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) { 2298 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n"); 2299 return -EINVAL; 2300 } 2301 for (i = 0; i < pkt->count; i++) { 2302 reg = start_reg + (4 * i); 2303 r = evergreen_cs_check_reg(p, reg, idx+1+i); 2304 if (r) 2305 return r; 2306 } 2307 break; 2308 case PACKET3_SET_RESOURCE: 2309 if (pkt->count % 8) { 2310 DRM_ERROR("bad SET_RESOURCE\n"); 2311 return -EINVAL; 2312 } 2313 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START; 2314 end_reg = 4 * pkt->count + start_reg - 4; 2315 if ((start_reg < PACKET3_SET_RESOURCE_START) || 2316 (start_reg >= PACKET3_SET_RESOURCE_END) || 2317 (end_reg >= PACKET3_SET_RESOURCE_END)) { 2318 DRM_ERROR("bad SET_RESOURCE\n"); 2319 return -EINVAL; 2320 } 2321 for (i = 0; i < (pkt->count / 8); i++) { 2322 struct radeon_bo *texture, *mipmap; 2323 u32 toffset, moffset; 2324 u32 size, offset; 2325 2326 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { 2327 case SQ_TEX_VTX_VALID_TEXTURE: 2328 /* tex base */ 2329 r = evergreen_cs_packet_next_reloc(p, &reloc); 2330 if (r) { 2331 DRM_ERROR("bad SET_RESOURCE (tex)\n"); 2332 return -EINVAL; 2333 } 2334 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 2335 ib[idx+1+(i*8)+1] |= 2336 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); 2337 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { 2338 unsigned bankw, bankh, mtaspect, tile_split; 2339 2340 evergreen_tiling_fields(reloc->lobj.tiling_flags, 2341 &bankw, &bankh, &mtaspect, 2342 &tile_split); 2343 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); 2344 ib[idx+1+(i*8)+7] |= 2345 TEX_BANK_WIDTH(bankw) | 2346 TEX_BANK_HEIGHT(bankh) | 2347 MACRO_TILE_ASPECT(mtaspect) | 2348 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); 2349 } 2350 } 2351 texture = reloc->robj; 2352 toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 2353 /* tex mip base */ 2354 r = evergreen_cs_packet_next_reloc(p, &reloc); 2355 if (r) { 2356 DRM_ERROR("bad SET_RESOURCE (tex)\n"); 2357 return -EINVAL; 2358 } 2359 moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 2360 mipmap = reloc->robj; 2361 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8)); 2362 if (r) 2363 return r; 2364 ib[idx+1+(i*8)+2] += toffset; 2365 ib[idx+1+(i*8)+3] += moffset; 2366 break; 2367 case SQ_TEX_VTX_VALID_BUFFER: 2368 { 2369 uint64_t offset64; 2370 /* vtx base */ 2371 r = evergreen_cs_packet_next_reloc(p, &reloc); 2372 if (r) { 2373 DRM_ERROR("bad SET_RESOURCE (vtx)\n"); 2374 return -EINVAL; 2375 } 2376 offset = radeon_get_ib_value(p, idx+1+(i*8)+0); 2377 size = radeon_get_ib_value(p, idx+1+(i*8)+1); 2378 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { 2379 /* force size to size of the buffer */ 2380 dev_warn(p->dev, "vbo resource seems too big for the bo\n"); 2381 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; 2382 } 2383 2384 offset64 = reloc->lobj.gpu_offset + offset; 2385 ib[idx+1+(i*8)+0] = offset64; 2386 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | 2387 (upper_32_bits(offset64) & 0xff); 2388 break; 2389 } 2390 case SQ_TEX_VTX_INVALID_TEXTURE: 2391 case SQ_TEX_VTX_INVALID_BUFFER: 2392 default: 2393 DRM_ERROR("bad SET_RESOURCE\n"); 2394 return -EINVAL; 2395 } 2396 } 2397 break; 2398 case PACKET3_SET_ALU_CONST: 2399 /* XXX fix me ALU const buffers only */ 2400 break; 2401 case PACKET3_SET_BOOL_CONST: 2402 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START; 2403 end_reg = 4 * pkt->count + start_reg - 4; 2404 if ((start_reg < PACKET3_SET_BOOL_CONST_START) || 2405 (start_reg >= PACKET3_SET_BOOL_CONST_END) || 2406 (end_reg >= PACKET3_SET_BOOL_CONST_END)) { 2407 DRM_ERROR("bad SET_BOOL_CONST\n"); 2408 return -EINVAL; 2409 } 2410 break; 2411 case PACKET3_SET_LOOP_CONST: 2412 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START; 2413 end_reg = 4 * pkt->count + start_reg - 4; 2414 if ((start_reg < PACKET3_SET_LOOP_CONST_START) || 2415 (start_reg >= PACKET3_SET_LOOP_CONST_END) || 2416 (end_reg >= PACKET3_SET_LOOP_CONST_END)) { 2417 DRM_ERROR("bad SET_LOOP_CONST\n"); 2418 return -EINVAL; 2419 } 2420 break; 2421 case PACKET3_SET_CTL_CONST: 2422 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START; 2423 end_reg = 4 * pkt->count + start_reg - 4; 2424 if ((start_reg < PACKET3_SET_CTL_CONST_START) || 2425 (start_reg >= PACKET3_SET_CTL_CONST_END) || 2426 (end_reg >= PACKET3_SET_CTL_CONST_END)) { 2427 DRM_ERROR("bad SET_CTL_CONST\n"); 2428 return -EINVAL; 2429 } 2430 break; 2431 case PACKET3_SET_SAMPLER: 2432 if (pkt->count % 3) { 2433 DRM_ERROR("bad SET_SAMPLER\n"); 2434 return -EINVAL; 2435 } 2436 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START; 2437 end_reg = 4 * pkt->count + start_reg - 4; 2438 if ((start_reg < PACKET3_SET_SAMPLER_START) || 2439 (start_reg >= PACKET3_SET_SAMPLER_END) || 2440 (end_reg >= PACKET3_SET_SAMPLER_END)) { 2441 DRM_ERROR("bad SET_SAMPLER\n"); 2442 return -EINVAL; 2443 } 2444 break; 2445 case PACKET3_STRMOUT_BUFFER_UPDATE: 2446 if (pkt->count != 4) { 2447 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n"); 2448 return -EINVAL; 2449 } 2450 /* Updating memory at DST_ADDRESS. */ 2451 if (idx_value & 0x1) { 2452 u64 offset; 2453 r = evergreen_cs_packet_next_reloc(p, &reloc); 2454 if (r) { 2455 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); 2456 return -EINVAL; 2457 } 2458 offset = radeon_get_ib_value(p, idx+1); 2459 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2460 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2461 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n", 2462 offset + 4, radeon_bo_size(reloc->robj)); 2463 return -EINVAL; 2464 } 2465 offset += reloc->lobj.gpu_offset; 2466 ib[idx+1] = offset; 2467 ib[idx+2] = upper_32_bits(offset) & 0xff; 2468 } 2469 /* Reading data from SRC_ADDRESS. */ 2470 if (((idx_value >> 1) & 0x3) == 2) { 2471 u64 offset; 2472 r = evergreen_cs_packet_next_reloc(p, &reloc); 2473 if (r) { 2474 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); 2475 return -EINVAL; 2476 } 2477 offset = radeon_get_ib_value(p, idx+3); 2478 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2479 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2480 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n", 2481 offset + 4, radeon_bo_size(reloc->robj)); 2482 return -EINVAL; 2483 } 2484 offset += reloc->lobj.gpu_offset; 2485 ib[idx+3] = offset; 2486 ib[idx+4] = upper_32_bits(offset) & 0xff; 2487 } 2488 break; 2489 case PACKET3_COPY_DW: 2490 if (pkt->count != 4) { 2491 DRM_ERROR("bad COPY_DW (invalid count)\n"); 2492 return -EINVAL; 2493 } 2494 if (idx_value & 0x1) { 2495 u64 offset; 2496 /* SRC is memory. */ 2497 r = evergreen_cs_packet_next_reloc(p, &reloc); 2498 if (r) { 2499 DRM_ERROR("bad COPY_DW (missing src reloc)\n"); 2500 return -EINVAL; 2501 } 2502 offset = radeon_get_ib_value(p, idx+1); 2503 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; 2504 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2505 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n", 2506 offset + 4, radeon_bo_size(reloc->robj)); 2507 return -EINVAL; 2508 } 2509 offset += reloc->lobj.gpu_offset; 2510 ib[idx+1] = offset; 2511 ib[idx+2] = upper_32_bits(offset) & 0xff; 2512 } else { 2513 /* SRC is a reg. */ 2514 reg = radeon_get_ib_value(p, idx+1) << 2; 2515 if (!evergreen_is_safe_reg(p, reg, idx+1)) 2516 return -EINVAL; 2517 } 2518 if (idx_value & 0x2) { 2519 u64 offset; 2520 /* DST is memory. */ 2521 r = evergreen_cs_packet_next_reloc(p, &reloc); 2522 if (r) { 2523 DRM_ERROR("bad COPY_DW (missing dst reloc)\n"); 2524 return -EINVAL; 2525 } 2526 offset = radeon_get_ib_value(p, idx+3); 2527 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; 2528 if ((offset + 4) > radeon_bo_size(reloc->robj)) { 2529 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n", 2530 offset + 4, radeon_bo_size(reloc->robj)); 2531 return -EINVAL; 2532 } 2533 offset += reloc->lobj.gpu_offset; 2534 ib[idx+3] = offset; 2535 ib[idx+4] = upper_32_bits(offset) & 0xff; 2536 } else { 2537 /* DST is a reg. */ 2538 reg = radeon_get_ib_value(p, idx+3) << 2; 2539 if (!evergreen_is_safe_reg(p, reg, idx+3)) 2540 return -EINVAL; 2541 } 2542 break; 2543 case PACKET3_NOP: 2544 break; 2545 default: 2546 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2547 return -EINVAL; 2548 } 2549 return 0; 2550 } 2551 2552 int evergreen_cs_parse(struct radeon_cs_parser *p) 2553 { 2554 struct radeon_cs_packet pkt; 2555 struct evergreen_cs_track *track; 2556 u32 tmp; 2557 int r; 2558 2559 if (p->track == NULL) { 2560 /* initialize tracker, we are in kms */ 2561 track = kzalloc(sizeof(*track), GFP_KERNEL); 2562 if (track == NULL) 2563 return -ENOMEM; 2564 evergreen_cs_track_init(track); 2565 if (p->rdev->family >= CHIP_CAYMAN) 2566 tmp = p->rdev->config.cayman.tile_config; 2567 else 2568 tmp = p->rdev->config.evergreen.tile_config; 2569 2570 switch (tmp & 0xf) { 2571 case 0: 2572 track->npipes = 1; 2573 break; 2574 case 1: 2575 default: 2576 track->npipes = 2; 2577 break; 2578 case 2: 2579 track->npipes = 4; 2580 break; 2581 case 3: 2582 track->npipes = 8; 2583 break; 2584 } 2585 2586 switch ((tmp & 0xf0) >> 4) { 2587 case 0: 2588 track->nbanks = 4; 2589 break; 2590 case 1: 2591 default: 2592 track->nbanks = 8; 2593 break; 2594 case 2: 2595 track->nbanks = 16; 2596 break; 2597 } 2598 2599 switch ((tmp & 0xf00) >> 8) { 2600 case 0: 2601 track->group_size = 256; 2602 break; 2603 case 1: 2604 default: 2605 track->group_size = 512; 2606 break; 2607 } 2608 2609 switch ((tmp & 0xf000) >> 12) { 2610 case 0: 2611 track->row_size = 1; 2612 break; 2613 case 1: 2614 default: 2615 track->row_size = 2; 2616 break; 2617 case 2: 2618 track->row_size = 4; 2619 break; 2620 } 2621 2622 p->track = track; 2623 } 2624 do { 2625 r = evergreen_cs_packet_parse(p, &pkt, p->idx); 2626 if (r) { 2627 kfree(p->track); 2628 p->track = NULL; 2629 return r; 2630 } 2631 p->idx += pkt.count + 2; 2632 switch (pkt.type) { 2633 case PACKET_TYPE0: 2634 r = evergreen_cs_parse_packet0(p, &pkt); 2635 break; 2636 case PACKET_TYPE2: 2637 break; 2638 case PACKET_TYPE3: 2639 r = evergreen_packet3_check(p, &pkt); 2640 break; 2641 default: 2642 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 2643 kfree(p->track); 2644 p->track = NULL; 2645 return -EINVAL; 2646 } 2647 if (r) { 2648 kfree(p->track); 2649 p->track = NULL; 2650 return r; 2651 } 2652 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 2653 #if 0 2654 for (r = 0; r < p->ib.length_dw; r++) { 2655 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); 2656 mdelay(1); 2657 } 2658 #endif 2659 kfree(p->track); 2660 p->track = NULL; 2661 return 0; 2662 } 2663 2664 /* vm parser */ 2665 static bool evergreen_vm_reg_valid(u32 reg) 2666 { 2667 /* context regs are fine */ 2668 if (reg >= 0x28000) 2669 return true; 2670 2671 /* check config regs */ 2672 switch (reg) { 2673 case GRBM_GFX_INDEX: 2674 case VGT_VTX_VECT_EJECT_REG: 2675 case VGT_CACHE_INVALIDATION: 2676 case VGT_GS_VERTEX_REUSE: 2677 case VGT_PRIMITIVE_TYPE: 2678 case VGT_INDEX_TYPE: 2679 case VGT_NUM_INDICES: 2680 case VGT_NUM_INSTANCES: 2681 case VGT_COMPUTE_DIM_X: 2682 case VGT_COMPUTE_DIM_Y: 2683 case VGT_COMPUTE_DIM_Z: 2684 case VGT_COMPUTE_START_X: 2685 case VGT_COMPUTE_START_Y: 2686 case VGT_COMPUTE_START_Z: 2687 case VGT_COMPUTE_INDEX: 2688 case VGT_COMPUTE_THREAD_GROUP_SIZE: 2689 case VGT_HS_OFFCHIP_PARAM: 2690 case PA_CL_ENHANCE: 2691 case PA_SU_LINE_STIPPLE_VALUE: 2692 case PA_SC_LINE_STIPPLE_STATE: 2693 case PA_SC_ENHANCE: 2694 case SQ_DYN_GPR_CNTL_PS_FLUSH_REQ: 2695 case SQ_DYN_GPR_SIMD_LOCK_EN: 2696 case SQ_CONFIG: 2697 case SQ_GPR_RESOURCE_MGMT_1: 2698 case SQ_GLOBAL_GPR_RESOURCE_MGMT_1: 2699 case SQ_GLOBAL_GPR_RESOURCE_MGMT_2: 2700 case SQ_CONST_MEM_BASE: 2701 case SQ_STATIC_THREAD_MGMT_1: 2702 case SQ_STATIC_THREAD_MGMT_2: 2703 case SQ_STATIC_THREAD_MGMT_3: 2704 case SPI_CONFIG_CNTL: 2705 case SPI_CONFIG_CNTL_1: 2706 case TA_CNTL_AUX: 2707 case DB_DEBUG: 2708 case DB_DEBUG2: 2709 case DB_DEBUG3: 2710 case DB_DEBUG4: 2711 case DB_WATERMARKS: 2712 case TD_PS_BORDER_COLOR_INDEX: 2713 case TD_PS_BORDER_COLOR_RED: 2714 case TD_PS_BORDER_COLOR_GREEN: 2715 case TD_PS_BORDER_COLOR_BLUE: 2716 case TD_PS_BORDER_COLOR_ALPHA: 2717 case TD_VS_BORDER_COLOR_INDEX: 2718 case TD_VS_BORDER_COLOR_RED: 2719 case TD_VS_BORDER_COLOR_GREEN: 2720 case TD_VS_BORDER_COLOR_BLUE: 2721 case TD_VS_BORDER_COLOR_ALPHA: 2722 case TD_GS_BORDER_COLOR_INDEX: 2723 case TD_GS_BORDER_COLOR_RED: 2724 case TD_GS_BORDER_COLOR_GREEN: 2725 case TD_GS_BORDER_COLOR_BLUE: 2726 case TD_GS_BORDER_COLOR_ALPHA: 2727 case TD_HS_BORDER_COLOR_INDEX: 2728 case TD_HS_BORDER_COLOR_RED: 2729 case TD_HS_BORDER_COLOR_GREEN: 2730 case TD_HS_BORDER_COLOR_BLUE: 2731 case TD_HS_BORDER_COLOR_ALPHA: 2732 case TD_LS_BORDER_COLOR_INDEX: 2733 case TD_LS_BORDER_COLOR_RED: 2734 case TD_LS_BORDER_COLOR_GREEN: 2735 case TD_LS_BORDER_COLOR_BLUE: 2736 case TD_LS_BORDER_COLOR_ALPHA: 2737 case TD_CS_BORDER_COLOR_INDEX: 2738 case TD_CS_BORDER_COLOR_RED: 2739 case TD_CS_BORDER_COLOR_GREEN: 2740 case TD_CS_BORDER_COLOR_BLUE: 2741 case TD_CS_BORDER_COLOR_ALPHA: 2742 case SQ_ESGS_RING_SIZE: 2743 case SQ_GSVS_RING_SIZE: 2744 case SQ_ESTMP_RING_SIZE: 2745 case SQ_GSTMP_RING_SIZE: 2746 case SQ_HSTMP_RING_SIZE: 2747 case SQ_LSTMP_RING_SIZE: 2748 case SQ_PSTMP_RING_SIZE: 2749 case SQ_VSTMP_RING_SIZE: 2750 case SQ_ESGS_RING_ITEMSIZE: 2751 case SQ_ESTMP_RING_ITEMSIZE: 2752 case SQ_GSTMP_RING_ITEMSIZE: 2753 case SQ_GSVS_RING_ITEMSIZE: 2754 case SQ_GS_VERT_ITEMSIZE: 2755 case SQ_GS_VERT_ITEMSIZE_1: 2756 case SQ_GS_VERT_ITEMSIZE_2: 2757 case SQ_GS_VERT_ITEMSIZE_3: 2758 case SQ_GSVS_RING_OFFSET_1: 2759 case SQ_GSVS_RING_OFFSET_2: 2760 case SQ_GSVS_RING_OFFSET_3: 2761 case SQ_HSTMP_RING_ITEMSIZE: 2762 case SQ_LSTMP_RING_ITEMSIZE: 2763 case SQ_PSTMP_RING_ITEMSIZE: 2764 case SQ_VSTMP_RING_ITEMSIZE: 2765 case VGT_TF_RING_SIZE: 2766 case SQ_ESGS_RING_BASE: 2767 case SQ_GSVS_RING_BASE: 2768 case SQ_ESTMP_RING_BASE: 2769 case SQ_GSTMP_RING_BASE: 2770 case SQ_HSTMP_RING_BASE: 2771 case SQ_LSTMP_RING_BASE: 2772 case SQ_PSTMP_RING_BASE: 2773 case SQ_VSTMP_RING_BASE: 2774 case CAYMAN_VGT_OFFCHIP_LDS_BASE: 2775 case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS: 2776 return true; 2777 default: 2778 return false; 2779 } 2780 } 2781 2782 static int evergreen_vm_packet3_check(struct radeon_device *rdev, 2783 u32 *ib, struct radeon_cs_packet *pkt) 2784 { 2785 u32 idx = pkt->idx + 1; 2786 u32 idx_value = ib[idx]; 2787 u32 start_reg, end_reg, reg, i; 2788 2789 switch (pkt->opcode) { 2790 case PACKET3_NOP: 2791 case PACKET3_SET_BASE: 2792 case PACKET3_CLEAR_STATE: 2793 case PACKET3_INDEX_BUFFER_SIZE: 2794 case PACKET3_DISPATCH_DIRECT: 2795 case PACKET3_DISPATCH_INDIRECT: 2796 case PACKET3_MODE_CONTROL: 2797 case PACKET3_SET_PREDICATION: 2798 case PACKET3_COND_EXEC: 2799 case PACKET3_PRED_EXEC: 2800 case PACKET3_DRAW_INDIRECT: 2801 case PACKET3_DRAW_INDEX_INDIRECT: 2802 case PACKET3_INDEX_BASE: 2803 case PACKET3_DRAW_INDEX_2: 2804 case PACKET3_CONTEXT_CONTROL: 2805 case PACKET3_DRAW_INDEX_OFFSET: 2806 case PACKET3_INDEX_TYPE: 2807 case PACKET3_DRAW_INDEX: 2808 case PACKET3_DRAW_INDEX_AUTO: 2809 case PACKET3_DRAW_INDEX_IMMD: 2810 case PACKET3_NUM_INSTANCES: 2811 case PACKET3_DRAW_INDEX_MULTI_AUTO: 2812 case PACKET3_STRMOUT_BUFFER_UPDATE: 2813 case PACKET3_DRAW_INDEX_OFFSET_2: 2814 case PACKET3_DRAW_INDEX_MULTI_ELEMENT: 2815 case PACKET3_MPEG_INDEX: 2816 case PACKET3_WAIT_REG_MEM: 2817 case PACKET3_MEM_WRITE: 2818 case PACKET3_SURFACE_SYNC: 2819 case PACKET3_EVENT_WRITE: 2820 case PACKET3_EVENT_WRITE_EOP: 2821 case PACKET3_EVENT_WRITE_EOS: 2822 case PACKET3_SET_CONTEXT_REG: 2823 case PACKET3_SET_BOOL_CONST: 2824 case PACKET3_SET_LOOP_CONST: 2825 case PACKET3_SET_RESOURCE: 2826 case PACKET3_SET_SAMPLER: 2827 case PACKET3_SET_CTL_CONST: 2828 case PACKET3_SET_RESOURCE_OFFSET: 2829 case PACKET3_SET_CONTEXT_REG_INDIRECT: 2830 case PACKET3_SET_RESOURCE_INDIRECT: 2831 case CAYMAN_PACKET3_DEALLOC_STATE: 2832 break; 2833 case PACKET3_COND_WRITE: 2834 if (idx_value & 0x100) { 2835 reg = ib[idx + 5] * 4; 2836 if (!evergreen_vm_reg_valid(reg)) 2837 return -EINVAL; 2838 } 2839 break; 2840 case PACKET3_COPY_DW: 2841 if (idx_value & 0x2) { 2842 reg = ib[idx + 3] * 4; 2843 if (!evergreen_vm_reg_valid(reg)) 2844 return -EINVAL; 2845 } 2846 break; 2847 case PACKET3_SET_CONFIG_REG: 2848 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; 2849 end_reg = 4 * pkt->count + start_reg - 4; 2850 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || 2851 (start_reg >= PACKET3_SET_CONFIG_REG_END) || 2852 (end_reg >= PACKET3_SET_CONFIG_REG_END)) { 2853 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); 2854 return -EINVAL; 2855 } 2856 for (i = 0; i < pkt->count; i++) { 2857 reg = start_reg + (4 * i); 2858 if (!evergreen_vm_reg_valid(reg)) 2859 return -EINVAL; 2860 } 2861 break; 2862 default: 2863 return -EINVAL; 2864 } 2865 return 0; 2866 } 2867 2868 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) 2869 { 2870 int ret = 0; 2871 u32 idx = 0; 2872 struct radeon_cs_packet pkt; 2873 2874 do { 2875 pkt.idx = idx; 2876 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]); 2877 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]); 2878 pkt.one_reg_wr = 0; 2879 switch (pkt.type) { 2880 case PACKET_TYPE0: 2881 dev_err(rdev->dev, "Packet0 not allowed!\n"); 2882 ret = -EINVAL; 2883 break; 2884 case PACKET_TYPE2: 2885 idx += 1; 2886 break; 2887 case PACKET_TYPE3: 2888 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]); 2889 ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt); 2890 idx += pkt.count + 2; 2891 break; 2892 default: 2893 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type); 2894 ret = -EINVAL; 2895 break; 2896 } 2897 if (ret) 2898 break; 2899 } while (idx < ib->length_dw); 2900 2901 return ret; 2902 } 2903