1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 #include "drmP.h" 28 #include "radeon.h" 29 #include "radeon_asic.h" 30 #include "radeon_drm.h" 31 #include "evergreend.h" 32 #include "atom.h" 33 #include "avivod.h" 34 #include "evergreen_reg.h" 35 #include "evergreen_blit_shaders.h" 36 37 #define EVERGREEN_PFP_UCODE_SIZE 1120 38 #define EVERGREEN_PM4_UCODE_SIZE 1376 39 40 static void evergreen_gpu_init(struct radeon_device *rdev); 41 void evergreen_fini(struct radeon_device *rdev); 42 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 43 44 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc) 45 { 46 /* enable the pflip int */ 47 radeon_irq_kms_pflip_irq_get(rdev, crtc); 48 } 49 50 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc) 51 { 52 /* disable the pflip int */ 53 radeon_irq_kms_pflip_irq_put(rdev, crtc); 54 } 55 56 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 57 { 58 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 59 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); 60 61 /* Lock the graphics update lock */ 62 tmp |= EVERGREEN_GRPH_UPDATE_LOCK; 63 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 64 65 /* update the scanout addresses */ 66 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 67 upper_32_bits(crtc_base)); 68 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 69 (u32)crtc_base); 70 71 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 72 upper_32_bits(crtc_base)); 73 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 74 (u32)crtc_base); 75 76 /* Wait for update_pending to go high. */ 77 while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)); 78 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 79 80 /* Unlock the lock, so double-buffering can take place inside vblank */ 81 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; 82 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 83 84 /* Return current update_pending status: */ 85 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING; 86 } 87 88 /* get temperature in millidegrees */ 89 int evergreen_get_temp(struct radeon_device *rdev) 90 { 91 u32 temp, toffset; 92 int actual_temp = 0; 93 94 if (rdev->family == CHIP_JUNIPER) { 95 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> 96 TOFFSET_SHIFT; 97 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >> 98 TS0_ADC_DOUT_SHIFT; 99 100 if (toffset & 0x100) 101 actual_temp = temp / 2 - (0x200 - toffset); 102 else 103 actual_temp = temp / 2 + toffset; 104 105 actual_temp = actual_temp * 1000; 106 107 } else { 108 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> 109 ASIC_T_SHIFT; 110 111 if (temp & 0x400) 112 actual_temp = -256; 113 else if (temp & 0x200) 114 actual_temp = 255; 115 else if (temp & 0x100) { 116 actual_temp = temp & 0x1ff; 117 actual_temp |= ~0x1ff; 118 } else 119 actual_temp = temp & 0xff; 120 121 actual_temp = (actual_temp * 1000) / 2; 122 } 123 124 return actual_temp; 125 } 126 127 int sumo_get_temp(struct radeon_device *rdev) 128 { 129 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff; 130 int actual_temp = temp - 49; 131 132 return actual_temp * 1000; 133 } 134 135 void evergreen_pm_misc(struct radeon_device *rdev) 136 { 137 int req_ps_idx = rdev->pm.requested_power_state_index; 138 int req_cm_idx = rdev->pm.requested_clock_mode_index; 139 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 140 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 141 142 if (voltage->type == VOLTAGE_SW) { 143 /* 0xff01 is a flag rather then an actual voltage */ 144 if (voltage->voltage == 0xff01) 145 return; 146 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { 147 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 148 rdev->pm.current_vddc = voltage->voltage; 149 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage); 150 } 151 /* 0xff01 is a flag rather then an actual voltage */ 152 if (voltage->vddci == 0xff01) 153 return; 154 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { 155 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); 156 rdev->pm.current_vddci = voltage->vddci; 157 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci); 158 } 159 } 160 } 161 162 void evergreen_pm_prepare(struct radeon_device *rdev) 163 { 164 struct drm_device *ddev = rdev->ddev; 165 struct drm_crtc *crtc; 166 struct radeon_crtc *radeon_crtc; 167 u32 tmp; 168 169 /* disable any active CRTCs */ 170 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 171 radeon_crtc = to_radeon_crtc(crtc); 172 if (radeon_crtc->enabled) { 173 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); 174 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; 175 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 176 } 177 } 178 } 179 180 void evergreen_pm_finish(struct radeon_device *rdev) 181 { 182 struct drm_device *ddev = rdev->ddev; 183 struct drm_crtc *crtc; 184 struct radeon_crtc *radeon_crtc; 185 u32 tmp; 186 187 /* enable any active CRTCs */ 188 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 189 radeon_crtc = to_radeon_crtc(crtc); 190 if (radeon_crtc->enabled) { 191 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); 192 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; 193 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 194 } 195 } 196 } 197 198 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 199 { 200 bool connected = false; 201 202 switch (hpd) { 203 case RADEON_HPD_1: 204 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 205 connected = true; 206 break; 207 case RADEON_HPD_2: 208 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 209 connected = true; 210 break; 211 case RADEON_HPD_3: 212 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 213 connected = true; 214 break; 215 case RADEON_HPD_4: 216 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 217 connected = true; 218 break; 219 case RADEON_HPD_5: 220 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 221 connected = true; 222 break; 223 case RADEON_HPD_6: 224 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 225 connected = true; 226 break; 227 default: 228 break; 229 } 230 231 return connected; 232 } 233 234 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 235 enum radeon_hpd_id hpd) 236 { 237 u32 tmp; 238 bool connected = evergreen_hpd_sense(rdev, hpd); 239 240 switch (hpd) { 241 case RADEON_HPD_1: 242 tmp = RREG32(DC_HPD1_INT_CONTROL); 243 if (connected) 244 tmp &= ~DC_HPDx_INT_POLARITY; 245 else 246 tmp |= DC_HPDx_INT_POLARITY; 247 WREG32(DC_HPD1_INT_CONTROL, tmp); 248 break; 249 case RADEON_HPD_2: 250 tmp = RREG32(DC_HPD2_INT_CONTROL); 251 if (connected) 252 tmp &= ~DC_HPDx_INT_POLARITY; 253 else 254 tmp |= DC_HPDx_INT_POLARITY; 255 WREG32(DC_HPD2_INT_CONTROL, tmp); 256 break; 257 case RADEON_HPD_3: 258 tmp = RREG32(DC_HPD3_INT_CONTROL); 259 if (connected) 260 tmp &= ~DC_HPDx_INT_POLARITY; 261 else 262 tmp |= DC_HPDx_INT_POLARITY; 263 WREG32(DC_HPD3_INT_CONTROL, tmp); 264 break; 265 case RADEON_HPD_4: 266 tmp = RREG32(DC_HPD4_INT_CONTROL); 267 if (connected) 268 tmp &= ~DC_HPDx_INT_POLARITY; 269 else 270 tmp |= DC_HPDx_INT_POLARITY; 271 WREG32(DC_HPD4_INT_CONTROL, tmp); 272 break; 273 case RADEON_HPD_5: 274 tmp = RREG32(DC_HPD5_INT_CONTROL); 275 if (connected) 276 tmp &= ~DC_HPDx_INT_POLARITY; 277 else 278 tmp |= DC_HPDx_INT_POLARITY; 279 WREG32(DC_HPD5_INT_CONTROL, tmp); 280 break; 281 case RADEON_HPD_6: 282 tmp = RREG32(DC_HPD6_INT_CONTROL); 283 if (connected) 284 tmp &= ~DC_HPDx_INT_POLARITY; 285 else 286 tmp |= DC_HPDx_INT_POLARITY; 287 WREG32(DC_HPD6_INT_CONTROL, tmp); 288 break; 289 default: 290 break; 291 } 292 } 293 294 void evergreen_hpd_init(struct radeon_device *rdev) 295 { 296 struct drm_device *dev = rdev->ddev; 297 struct drm_connector *connector; 298 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | 299 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN; 300 301 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 302 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 303 switch (radeon_connector->hpd.hpd) { 304 case RADEON_HPD_1: 305 WREG32(DC_HPD1_CONTROL, tmp); 306 rdev->irq.hpd[0] = true; 307 break; 308 case RADEON_HPD_2: 309 WREG32(DC_HPD2_CONTROL, tmp); 310 rdev->irq.hpd[1] = true; 311 break; 312 case RADEON_HPD_3: 313 WREG32(DC_HPD3_CONTROL, tmp); 314 rdev->irq.hpd[2] = true; 315 break; 316 case RADEON_HPD_4: 317 WREG32(DC_HPD4_CONTROL, tmp); 318 rdev->irq.hpd[3] = true; 319 break; 320 case RADEON_HPD_5: 321 WREG32(DC_HPD5_CONTROL, tmp); 322 rdev->irq.hpd[4] = true; 323 break; 324 case RADEON_HPD_6: 325 WREG32(DC_HPD6_CONTROL, tmp); 326 rdev->irq.hpd[5] = true; 327 break; 328 default: 329 break; 330 } 331 } 332 if (rdev->irq.installed) 333 evergreen_irq_set(rdev); 334 } 335 336 void evergreen_hpd_fini(struct radeon_device *rdev) 337 { 338 struct drm_device *dev = rdev->ddev; 339 struct drm_connector *connector; 340 341 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 342 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 343 switch (radeon_connector->hpd.hpd) { 344 case RADEON_HPD_1: 345 WREG32(DC_HPD1_CONTROL, 0); 346 rdev->irq.hpd[0] = false; 347 break; 348 case RADEON_HPD_2: 349 WREG32(DC_HPD2_CONTROL, 0); 350 rdev->irq.hpd[1] = false; 351 break; 352 case RADEON_HPD_3: 353 WREG32(DC_HPD3_CONTROL, 0); 354 rdev->irq.hpd[2] = false; 355 break; 356 case RADEON_HPD_4: 357 WREG32(DC_HPD4_CONTROL, 0); 358 rdev->irq.hpd[3] = false; 359 break; 360 case RADEON_HPD_5: 361 WREG32(DC_HPD5_CONTROL, 0); 362 rdev->irq.hpd[4] = false; 363 break; 364 case RADEON_HPD_6: 365 WREG32(DC_HPD6_CONTROL, 0); 366 rdev->irq.hpd[5] = false; 367 break; 368 default: 369 break; 370 } 371 } 372 } 373 374 /* watermark setup */ 375 376 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, 377 struct radeon_crtc *radeon_crtc, 378 struct drm_display_mode *mode, 379 struct drm_display_mode *other_mode) 380 { 381 u32 tmp; 382 /* 383 * Line Buffer Setup 384 * There are 3 line buffers, each one shared by 2 display controllers. 385 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 386 * the display controllers. The paritioning is done via one of four 387 * preset allocations specified in bits 2:0: 388 * first display controller 389 * 0 - first half of lb (3840 * 2) 390 * 1 - first 3/4 of lb (5760 * 2) 391 * 2 - whole lb (7680 * 2), other crtc must be disabled 392 * 3 - first 1/4 of lb (1920 * 2) 393 * second display controller 394 * 4 - second half of lb (3840 * 2) 395 * 5 - second 3/4 of lb (5760 * 2) 396 * 6 - whole lb (7680 * 2), other crtc must be disabled 397 * 7 - last 1/4 of lb (1920 * 2) 398 */ 399 /* this can get tricky if we have two large displays on a paired group 400 * of crtcs. Ideally for multiple large displays we'd assign them to 401 * non-linked crtcs for maximum line buffer allocation. 402 */ 403 if (radeon_crtc->base.enabled && mode) { 404 if (other_mode) 405 tmp = 0; /* 1/2 */ 406 else 407 tmp = 2; /* whole */ 408 } else 409 tmp = 0; 410 411 /* second controller of the pair uses second half of the lb */ 412 if (radeon_crtc->crtc_id % 2) 413 tmp += 4; 414 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); 415 416 if (radeon_crtc->base.enabled && mode) { 417 switch (tmp) { 418 case 0: 419 case 4: 420 default: 421 if (ASIC_IS_DCE5(rdev)) 422 return 4096 * 2; 423 else 424 return 3840 * 2; 425 case 1: 426 case 5: 427 if (ASIC_IS_DCE5(rdev)) 428 return 6144 * 2; 429 else 430 return 5760 * 2; 431 case 2: 432 case 6: 433 if (ASIC_IS_DCE5(rdev)) 434 return 8192 * 2; 435 else 436 return 7680 * 2; 437 case 3: 438 case 7: 439 if (ASIC_IS_DCE5(rdev)) 440 return 2048 * 2; 441 else 442 return 1920 * 2; 443 } 444 } 445 446 /* controller not enabled, so no lb used */ 447 return 0; 448 } 449 450 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev) 451 { 452 u32 tmp = RREG32(MC_SHARED_CHMAP); 453 454 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 455 case 0: 456 default: 457 return 1; 458 case 1: 459 return 2; 460 case 2: 461 return 4; 462 case 3: 463 return 8; 464 } 465 } 466 467 struct evergreen_wm_params { 468 u32 dram_channels; /* number of dram channels */ 469 u32 yclk; /* bandwidth per dram data pin in kHz */ 470 u32 sclk; /* engine clock in kHz */ 471 u32 disp_clk; /* display clock in kHz */ 472 u32 src_width; /* viewport width */ 473 u32 active_time; /* active display time in ns */ 474 u32 blank_time; /* blank time in ns */ 475 bool interlaced; /* mode is interlaced */ 476 fixed20_12 vsc; /* vertical scale ratio */ 477 u32 num_heads; /* number of active crtcs */ 478 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 479 u32 lb_size; /* line buffer allocated to pipe */ 480 u32 vtaps; /* vertical scaler taps */ 481 }; 482 483 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm) 484 { 485 /* Calculate DRAM Bandwidth and the part allocated to display. */ 486 fixed20_12 dram_efficiency; /* 0.7 */ 487 fixed20_12 yclk, dram_channels, bandwidth; 488 fixed20_12 a; 489 490 a.full = dfixed_const(1000); 491 yclk.full = dfixed_const(wm->yclk); 492 yclk.full = dfixed_div(yclk, a); 493 dram_channels.full = dfixed_const(wm->dram_channels * 4); 494 a.full = dfixed_const(10); 495 dram_efficiency.full = dfixed_const(7); 496 dram_efficiency.full = dfixed_div(dram_efficiency, a); 497 bandwidth.full = dfixed_mul(dram_channels, yclk); 498 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 499 500 return dfixed_trunc(bandwidth); 501 } 502 503 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm) 504 { 505 /* Calculate DRAM Bandwidth and the part allocated to display. */ 506 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 507 fixed20_12 yclk, dram_channels, bandwidth; 508 fixed20_12 a; 509 510 a.full = dfixed_const(1000); 511 yclk.full = dfixed_const(wm->yclk); 512 yclk.full = dfixed_div(yclk, a); 513 dram_channels.full = dfixed_const(wm->dram_channels * 4); 514 a.full = dfixed_const(10); 515 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 516 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 517 bandwidth.full = dfixed_mul(dram_channels, yclk); 518 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 519 520 return dfixed_trunc(bandwidth); 521 } 522 523 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm) 524 { 525 /* Calculate the display Data return Bandwidth */ 526 fixed20_12 return_efficiency; /* 0.8 */ 527 fixed20_12 sclk, bandwidth; 528 fixed20_12 a; 529 530 a.full = dfixed_const(1000); 531 sclk.full = dfixed_const(wm->sclk); 532 sclk.full = dfixed_div(sclk, a); 533 a.full = dfixed_const(10); 534 return_efficiency.full = dfixed_const(8); 535 return_efficiency.full = dfixed_div(return_efficiency, a); 536 a.full = dfixed_const(32); 537 bandwidth.full = dfixed_mul(a, sclk); 538 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 539 540 return dfixed_trunc(bandwidth); 541 } 542 543 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm) 544 { 545 /* Calculate the DMIF Request Bandwidth */ 546 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 547 fixed20_12 disp_clk, bandwidth; 548 fixed20_12 a; 549 550 a.full = dfixed_const(1000); 551 disp_clk.full = dfixed_const(wm->disp_clk); 552 disp_clk.full = dfixed_div(disp_clk, a); 553 a.full = dfixed_const(10); 554 disp_clk_request_efficiency.full = dfixed_const(8); 555 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 556 a.full = dfixed_const(32); 557 bandwidth.full = dfixed_mul(a, disp_clk); 558 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency); 559 560 return dfixed_trunc(bandwidth); 561 } 562 563 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm) 564 { 565 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 566 u32 dram_bandwidth = evergreen_dram_bandwidth(wm); 567 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm); 568 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm); 569 570 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 571 } 572 573 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm) 574 { 575 /* Calculate the display mode Average Bandwidth 576 * DisplayMode should contain the source and destination dimensions, 577 * timing, etc. 578 */ 579 fixed20_12 bpp; 580 fixed20_12 line_time; 581 fixed20_12 src_width; 582 fixed20_12 bandwidth; 583 fixed20_12 a; 584 585 a.full = dfixed_const(1000); 586 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 587 line_time.full = dfixed_div(line_time, a); 588 bpp.full = dfixed_const(wm->bytes_per_pixel); 589 src_width.full = dfixed_const(wm->src_width); 590 bandwidth.full = dfixed_mul(src_width, bpp); 591 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 592 bandwidth.full = dfixed_div(bandwidth, line_time); 593 594 return dfixed_trunc(bandwidth); 595 } 596 597 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm) 598 { 599 /* First calcualte the latency in ns */ 600 u32 mc_latency = 2000; /* 2000 ns. */ 601 u32 available_bandwidth = evergreen_available_bandwidth(wm); 602 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 603 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 604 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 605 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 606 (wm->num_heads * cursor_line_pair_return_time); 607 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 608 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 609 fixed20_12 a, b, c; 610 611 if (wm->num_heads == 0) 612 return 0; 613 614 a.full = dfixed_const(2); 615 b.full = dfixed_const(1); 616 if ((wm->vsc.full > a.full) || 617 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 618 (wm->vtaps >= 5) || 619 ((wm->vsc.full >= a.full) && wm->interlaced)) 620 max_src_lines_per_dst_line = 4; 621 else 622 max_src_lines_per_dst_line = 2; 623 624 a.full = dfixed_const(available_bandwidth); 625 b.full = dfixed_const(wm->num_heads); 626 a.full = dfixed_div(a, b); 627 628 b.full = dfixed_const(1000); 629 c.full = dfixed_const(wm->disp_clk); 630 b.full = dfixed_div(c, b); 631 c.full = dfixed_const(wm->bytes_per_pixel); 632 b.full = dfixed_mul(b, c); 633 634 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b)); 635 636 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 637 b.full = dfixed_const(1000); 638 c.full = dfixed_const(lb_fill_bw); 639 b.full = dfixed_div(c, b); 640 a.full = dfixed_div(a, b); 641 line_fill_time = dfixed_trunc(a); 642 643 if (line_fill_time < wm->active_time) 644 return latency; 645 else 646 return latency + (line_fill_time - wm->active_time); 647 648 } 649 650 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm) 651 { 652 if (evergreen_average_bandwidth(wm) <= 653 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads)) 654 return true; 655 else 656 return false; 657 }; 658 659 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm) 660 { 661 if (evergreen_average_bandwidth(wm) <= 662 (evergreen_available_bandwidth(wm) / wm->num_heads)) 663 return true; 664 else 665 return false; 666 }; 667 668 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm) 669 { 670 u32 lb_partitions = wm->lb_size / wm->src_width; 671 u32 line_time = wm->active_time + wm->blank_time; 672 u32 latency_tolerant_lines; 673 u32 latency_hiding; 674 fixed20_12 a; 675 676 a.full = dfixed_const(1); 677 if (wm->vsc.full > a.full) 678 latency_tolerant_lines = 1; 679 else { 680 if (lb_partitions <= (wm->vtaps + 1)) 681 latency_tolerant_lines = 1; 682 else 683 latency_tolerant_lines = 2; 684 } 685 686 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 687 688 if (evergreen_latency_watermark(wm) <= latency_hiding) 689 return true; 690 else 691 return false; 692 } 693 694 static void evergreen_program_watermarks(struct radeon_device *rdev, 695 struct radeon_crtc *radeon_crtc, 696 u32 lb_size, u32 num_heads) 697 { 698 struct drm_display_mode *mode = &radeon_crtc->base.mode; 699 struct evergreen_wm_params wm; 700 u32 pixel_period; 701 u32 line_time = 0; 702 u32 latency_watermark_a = 0, latency_watermark_b = 0; 703 u32 priority_a_mark = 0, priority_b_mark = 0; 704 u32 priority_a_cnt = PRIORITY_OFF; 705 u32 priority_b_cnt = PRIORITY_OFF; 706 u32 pipe_offset = radeon_crtc->crtc_id * 16; 707 u32 tmp, arb_control3; 708 fixed20_12 a, b, c; 709 710 if (radeon_crtc->base.enabled && num_heads && mode) { 711 pixel_period = 1000000 / (u32)mode->clock; 712 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 713 priority_a_cnt = 0; 714 priority_b_cnt = 0; 715 716 wm.yclk = rdev->pm.current_mclk * 10; 717 wm.sclk = rdev->pm.current_sclk * 10; 718 wm.disp_clk = mode->clock; 719 wm.src_width = mode->crtc_hdisplay; 720 wm.active_time = mode->crtc_hdisplay * pixel_period; 721 wm.blank_time = line_time - wm.active_time; 722 wm.interlaced = false; 723 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 724 wm.interlaced = true; 725 wm.vsc = radeon_crtc->vsc; 726 wm.vtaps = 1; 727 if (radeon_crtc->rmx_type != RMX_OFF) 728 wm.vtaps = 2; 729 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */ 730 wm.lb_size = lb_size; 731 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev); 732 wm.num_heads = num_heads; 733 734 /* set for high clocks */ 735 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535); 736 /* set for low clocks */ 737 /* wm.yclk = low clk; wm.sclk = low clk */ 738 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535); 739 740 /* possibly force display priority to high */ 741 /* should really do this at mode validation time... */ 742 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) || 743 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) || 744 !evergreen_check_latency_hiding(&wm) || 745 (rdev->disp_priority == 2)) { 746 DRM_INFO("force priority to high\n"); 747 priority_a_cnt |= PRIORITY_ALWAYS_ON; 748 priority_b_cnt |= PRIORITY_ALWAYS_ON; 749 } 750 751 a.full = dfixed_const(1000); 752 b.full = dfixed_const(mode->clock); 753 b.full = dfixed_div(b, a); 754 c.full = dfixed_const(latency_watermark_a); 755 c.full = dfixed_mul(c, b); 756 c.full = dfixed_mul(c, radeon_crtc->hsc); 757 c.full = dfixed_div(c, a); 758 a.full = dfixed_const(16); 759 c.full = dfixed_div(c, a); 760 priority_a_mark = dfixed_trunc(c); 761 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 762 763 a.full = dfixed_const(1000); 764 b.full = dfixed_const(mode->clock); 765 b.full = dfixed_div(b, a); 766 c.full = dfixed_const(latency_watermark_b); 767 c.full = dfixed_mul(c, b); 768 c.full = dfixed_mul(c, radeon_crtc->hsc); 769 c.full = dfixed_div(c, a); 770 a.full = dfixed_const(16); 771 c.full = dfixed_div(c, a); 772 priority_b_mark = dfixed_trunc(c); 773 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 774 } 775 776 /* select wm A */ 777 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); 778 tmp = arb_control3; 779 tmp &= ~LATENCY_WATERMARK_MASK(3); 780 tmp |= LATENCY_WATERMARK_MASK(1); 781 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); 782 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, 783 (LATENCY_LOW_WATERMARK(latency_watermark_a) | 784 LATENCY_HIGH_WATERMARK(line_time))); 785 /* select wm B */ 786 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); 787 tmp &= ~LATENCY_WATERMARK_MASK(3); 788 tmp |= LATENCY_WATERMARK_MASK(2); 789 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); 790 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, 791 (LATENCY_LOW_WATERMARK(latency_watermark_b) | 792 LATENCY_HIGH_WATERMARK(line_time))); 793 /* restore original selection */ 794 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3); 795 796 /* write the priority marks */ 797 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); 798 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); 799 800 } 801 802 void evergreen_bandwidth_update(struct radeon_device *rdev) 803 { 804 struct drm_display_mode *mode0 = NULL; 805 struct drm_display_mode *mode1 = NULL; 806 u32 num_heads = 0, lb_size; 807 int i; 808 809 radeon_update_display_priority(rdev); 810 811 for (i = 0; i < rdev->num_crtc; i++) { 812 if (rdev->mode_info.crtcs[i]->base.enabled) 813 num_heads++; 814 } 815 for (i = 0; i < rdev->num_crtc; i += 2) { 816 mode0 = &rdev->mode_info.crtcs[i]->base.mode; 817 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; 818 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); 819 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); 820 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); 821 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); 822 } 823 } 824 825 int evergreen_mc_wait_for_idle(struct radeon_device *rdev) 826 { 827 unsigned i; 828 u32 tmp; 829 830 for (i = 0; i < rdev->usec_timeout; i++) { 831 /* read MC_STATUS */ 832 tmp = RREG32(SRBM_STATUS) & 0x1F00; 833 if (!tmp) 834 return 0; 835 udelay(1); 836 } 837 return -1; 838 } 839 840 /* 841 * GART 842 */ 843 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev) 844 { 845 unsigned i; 846 u32 tmp; 847 848 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 849 850 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 851 for (i = 0; i < rdev->usec_timeout; i++) { 852 /* read MC_STATUS */ 853 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 854 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 855 if (tmp == 2) { 856 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 857 return; 858 } 859 if (tmp) { 860 return; 861 } 862 udelay(1); 863 } 864 } 865 866 int evergreen_pcie_gart_enable(struct radeon_device *rdev) 867 { 868 u32 tmp; 869 int r; 870 871 if (rdev->gart.table.vram.robj == NULL) { 872 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 873 return -EINVAL; 874 } 875 r = radeon_gart_table_vram_pin(rdev); 876 if (r) 877 return r; 878 radeon_gart_restore(rdev); 879 /* Setup L2 cache */ 880 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 881 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 882 EFFECTIVE_L2_QUEUE_SIZE(7)); 883 WREG32(VM_L2_CNTL2, 0); 884 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 885 /* Setup TLB control */ 886 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 887 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 888 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 889 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 890 if (rdev->flags & RADEON_IS_IGP) { 891 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp); 892 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp); 893 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp); 894 } else { 895 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 896 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 897 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 898 } 899 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 900 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 901 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 902 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 903 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 904 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 905 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 906 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 907 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 908 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 909 (u32)(rdev->dummy_page.addr >> 12)); 910 WREG32(VM_CONTEXT1_CNTL, 0); 911 912 evergreen_pcie_gart_tlb_flush(rdev); 913 rdev->gart.ready = true; 914 return 0; 915 } 916 917 void evergreen_pcie_gart_disable(struct radeon_device *rdev) 918 { 919 u32 tmp; 920 int r; 921 922 /* Disable all tables */ 923 WREG32(VM_CONTEXT0_CNTL, 0); 924 WREG32(VM_CONTEXT1_CNTL, 0); 925 926 /* Setup L2 cache */ 927 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 928 EFFECTIVE_L2_QUEUE_SIZE(7)); 929 WREG32(VM_L2_CNTL2, 0); 930 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 931 /* Setup TLB control */ 932 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 933 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 934 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 935 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 936 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 937 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 938 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 939 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 940 if (rdev->gart.table.vram.robj) { 941 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 942 if (likely(r == 0)) { 943 radeon_bo_kunmap(rdev->gart.table.vram.robj); 944 radeon_bo_unpin(rdev->gart.table.vram.robj); 945 radeon_bo_unreserve(rdev->gart.table.vram.robj); 946 } 947 } 948 } 949 950 void evergreen_pcie_gart_fini(struct radeon_device *rdev) 951 { 952 evergreen_pcie_gart_disable(rdev); 953 radeon_gart_table_vram_free(rdev); 954 radeon_gart_fini(rdev); 955 } 956 957 958 void evergreen_agp_enable(struct radeon_device *rdev) 959 { 960 u32 tmp; 961 962 /* Setup L2 cache */ 963 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 964 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 965 EFFECTIVE_L2_QUEUE_SIZE(7)); 966 WREG32(VM_L2_CNTL2, 0); 967 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 968 /* Setup TLB control */ 969 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 970 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 971 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 972 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 973 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 974 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 975 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 976 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 977 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 978 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 979 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 980 WREG32(VM_CONTEXT0_CNTL, 0); 981 WREG32(VM_CONTEXT1_CNTL, 0); 982 } 983 984 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) 985 { 986 save->vga_control[0] = RREG32(D1VGA_CONTROL); 987 save->vga_control[1] = RREG32(D2VGA_CONTROL); 988 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 989 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 990 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 991 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 992 if (rdev->num_crtc >= 4) { 993 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL); 994 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL); 995 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 996 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 997 } 998 if (rdev->num_crtc >= 6) { 999 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL); 1000 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL); 1001 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 1002 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 1003 } 1004 1005 /* Stop all video */ 1006 WREG32(VGA_RENDER_CONTROL, 0); 1007 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1008 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1009 if (rdev->num_crtc >= 4) { 1010 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1011 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1012 } 1013 if (rdev->num_crtc >= 6) { 1014 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1015 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1016 } 1017 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1018 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1019 if (rdev->num_crtc >= 4) { 1020 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1021 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1022 } 1023 if (rdev->num_crtc >= 6) { 1024 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1025 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1026 } 1027 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1028 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1029 if (rdev->num_crtc >= 4) { 1030 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1031 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1032 } 1033 if (rdev->num_crtc >= 6) { 1034 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1035 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1036 } 1037 1038 WREG32(D1VGA_CONTROL, 0); 1039 WREG32(D2VGA_CONTROL, 0); 1040 if (rdev->num_crtc >= 4) { 1041 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1042 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1043 } 1044 if (rdev->num_crtc >= 6) { 1045 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1046 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1047 } 1048 } 1049 1050 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) 1051 { 1052 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, 1053 upper_32_bits(rdev->mc.vram_start)); 1054 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, 1055 upper_32_bits(rdev->mc.vram_start)); 1056 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, 1057 (u32)rdev->mc.vram_start); 1058 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, 1059 (u32)rdev->mc.vram_start); 1060 1061 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, 1062 upper_32_bits(rdev->mc.vram_start)); 1063 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, 1064 upper_32_bits(rdev->mc.vram_start)); 1065 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, 1066 (u32)rdev->mc.vram_start); 1067 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, 1068 (u32)rdev->mc.vram_start); 1069 1070 if (rdev->num_crtc >= 4) { 1071 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1072 upper_32_bits(rdev->mc.vram_start)); 1073 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1074 upper_32_bits(rdev->mc.vram_start)); 1075 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, 1076 (u32)rdev->mc.vram_start); 1077 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, 1078 (u32)rdev->mc.vram_start); 1079 1080 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, 1081 upper_32_bits(rdev->mc.vram_start)); 1082 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, 1083 upper_32_bits(rdev->mc.vram_start)); 1084 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1085 (u32)rdev->mc.vram_start); 1086 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1087 (u32)rdev->mc.vram_start); 1088 } 1089 if (rdev->num_crtc >= 6) { 1090 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1091 upper_32_bits(rdev->mc.vram_start)); 1092 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1093 upper_32_bits(rdev->mc.vram_start)); 1094 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, 1095 (u32)rdev->mc.vram_start); 1096 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, 1097 (u32)rdev->mc.vram_start); 1098 1099 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, 1100 upper_32_bits(rdev->mc.vram_start)); 1101 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, 1102 upper_32_bits(rdev->mc.vram_start)); 1103 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, 1104 (u32)rdev->mc.vram_start); 1105 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, 1106 (u32)rdev->mc.vram_start); 1107 } 1108 1109 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); 1110 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 1111 /* Unlock host access */ 1112 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); 1113 mdelay(1); 1114 /* Restore video state */ 1115 WREG32(D1VGA_CONTROL, save->vga_control[0]); 1116 WREG32(D2VGA_CONTROL, save->vga_control[1]); 1117 if (rdev->num_crtc >= 4) { 1118 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); 1119 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); 1120 } 1121 if (rdev->num_crtc >= 6) { 1122 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); 1123 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); 1124 } 1125 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1126 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1127 if (rdev->num_crtc >= 4) { 1128 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1129 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1130 } 1131 if (rdev->num_crtc >= 6) { 1132 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1133 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1134 } 1135 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); 1136 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); 1137 if (rdev->num_crtc >= 4) { 1138 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); 1139 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); 1140 } 1141 if (rdev->num_crtc >= 6) { 1142 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); 1143 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); 1144 } 1145 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1146 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1147 if (rdev->num_crtc >= 4) { 1148 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1149 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1150 } 1151 if (rdev->num_crtc >= 6) { 1152 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1153 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1154 } 1155 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); 1156 } 1157 1158 void evergreen_mc_program(struct radeon_device *rdev) 1159 { 1160 struct evergreen_mc_save save; 1161 u32 tmp; 1162 int i, j; 1163 1164 /* Initialize HDP */ 1165 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1166 WREG32((0x2c14 + j), 0x00000000); 1167 WREG32((0x2c18 + j), 0x00000000); 1168 WREG32((0x2c1c + j), 0x00000000); 1169 WREG32((0x2c20 + j), 0x00000000); 1170 WREG32((0x2c24 + j), 0x00000000); 1171 } 1172 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1173 1174 evergreen_mc_stop(rdev, &save); 1175 if (evergreen_mc_wait_for_idle(rdev)) { 1176 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1177 } 1178 /* Lockout access through VGA aperture*/ 1179 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1180 /* Update configuration */ 1181 if (rdev->flags & RADEON_IS_AGP) { 1182 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1183 /* VRAM before AGP */ 1184 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1185 rdev->mc.vram_start >> 12); 1186 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1187 rdev->mc.gtt_end >> 12); 1188 } else { 1189 /* VRAM after AGP */ 1190 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1191 rdev->mc.gtt_start >> 12); 1192 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1193 rdev->mc.vram_end >> 12); 1194 } 1195 } else { 1196 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1197 rdev->mc.vram_start >> 12); 1198 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1199 rdev->mc.vram_end >> 12); 1200 } 1201 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 1202 if (rdev->flags & RADEON_IS_IGP) { 1203 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; 1204 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24; 1205 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; 1206 WREG32(MC_FUS_VM_FB_OFFSET, tmp); 1207 } 1208 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1209 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1210 WREG32(MC_VM_FB_LOCATION, tmp); 1211 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1212 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 1213 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1214 if (rdev->flags & RADEON_IS_AGP) { 1215 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 1216 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 1217 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1218 } else { 1219 WREG32(MC_VM_AGP_BASE, 0); 1220 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1221 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1222 } 1223 if (evergreen_mc_wait_for_idle(rdev)) { 1224 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1225 } 1226 evergreen_mc_resume(rdev, &save); 1227 /* we need to own VRAM, so turn off the VGA renderer here 1228 * to stop it overwriting our objects */ 1229 rv515_vga_render_disable(rdev); 1230 } 1231 1232 /* 1233 * CP. 1234 */ 1235 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1236 { 1237 /* set to DX10/11 mode */ 1238 radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0)); 1239 radeon_ring_write(rdev, 1); 1240 /* FIXME: implement */ 1241 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 1242 radeon_ring_write(rdev, 1243 #ifdef __BIG_ENDIAN 1244 (2 << 0) | 1245 #endif 1246 (ib->gpu_addr & 0xFFFFFFFC)); 1247 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); 1248 radeon_ring_write(rdev, ib->length_dw); 1249 } 1250 1251 1252 static int evergreen_cp_load_microcode(struct radeon_device *rdev) 1253 { 1254 const __be32 *fw_data; 1255 int i; 1256 1257 if (!rdev->me_fw || !rdev->pfp_fw) 1258 return -EINVAL; 1259 1260 r700_cp_stop(rdev); 1261 WREG32(CP_RB_CNTL, 1262 #ifdef __BIG_ENDIAN 1263 BUF_SWAP_32BIT | 1264 #endif 1265 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 1266 1267 fw_data = (const __be32 *)rdev->pfp_fw->data; 1268 WREG32(CP_PFP_UCODE_ADDR, 0); 1269 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++) 1270 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1271 WREG32(CP_PFP_UCODE_ADDR, 0); 1272 1273 fw_data = (const __be32 *)rdev->me_fw->data; 1274 WREG32(CP_ME_RAM_WADDR, 0); 1275 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++) 1276 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1277 1278 WREG32(CP_PFP_UCODE_ADDR, 0); 1279 WREG32(CP_ME_RAM_WADDR, 0); 1280 WREG32(CP_ME_RAM_RADDR, 0); 1281 return 0; 1282 } 1283 1284 static int evergreen_cp_start(struct radeon_device *rdev) 1285 { 1286 int r, i; 1287 uint32_t cp_me; 1288 1289 r = radeon_ring_lock(rdev, 7); 1290 if (r) { 1291 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1292 return r; 1293 } 1294 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1295 radeon_ring_write(rdev, 0x1); 1296 radeon_ring_write(rdev, 0x0); 1297 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1); 1298 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1299 radeon_ring_write(rdev, 0); 1300 radeon_ring_write(rdev, 0); 1301 radeon_ring_unlock_commit(rdev); 1302 1303 cp_me = 0xff; 1304 WREG32(CP_ME_CNTL, cp_me); 1305 1306 r = radeon_ring_lock(rdev, evergreen_default_size + 19); 1307 if (r) { 1308 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1309 return r; 1310 } 1311 1312 /* setup clear context state */ 1313 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1314 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1315 1316 for (i = 0; i < evergreen_default_size; i++) 1317 radeon_ring_write(rdev, evergreen_default_state[i]); 1318 1319 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1320 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE); 1321 1322 /* set clear context state */ 1323 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); 1324 radeon_ring_write(rdev, 0); 1325 1326 /* SQ_VTX_BASE_VTX_LOC */ 1327 radeon_ring_write(rdev, 0xc0026f00); 1328 radeon_ring_write(rdev, 0x00000000); 1329 radeon_ring_write(rdev, 0x00000000); 1330 radeon_ring_write(rdev, 0x00000000); 1331 1332 /* Clear consts */ 1333 radeon_ring_write(rdev, 0xc0036f00); 1334 radeon_ring_write(rdev, 0x00000bc4); 1335 radeon_ring_write(rdev, 0xffffffff); 1336 radeon_ring_write(rdev, 0xffffffff); 1337 radeon_ring_write(rdev, 0xffffffff); 1338 1339 radeon_ring_write(rdev, 0xc0026900); 1340 radeon_ring_write(rdev, 0x00000316); 1341 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 1342 radeon_ring_write(rdev, 0x00000010); /* */ 1343 1344 radeon_ring_unlock_commit(rdev); 1345 1346 return 0; 1347 } 1348 1349 int evergreen_cp_resume(struct radeon_device *rdev) 1350 { 1351 u32 tmp; 1352 u32 rb_bufsz; 1353 int r; 1354 1355 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ 1356 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | 1357 SOFT_RESET_PA | 1358 SOFT_RESET_SH | 1359 SOFT_RESET_VGT | 1360 SOFT_RESET_SX)); 1361 RREG32(GRBM_SOFT_RESET); 1362 mdelay(15); 1363 WREG32(GRBM_SOFT_RESET, 0); 1364 RREG32(GRBM_SOFT_RESET); 1365 1366 /* Set ring buffer size */ 1367 rb_bufsz = drm_order(rdev->cp.ring_size / 8); 1368 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1369 #ifdef __BIG_ENDIAN 1370 tmp |= BUF_SWAP_32BIT; 1371 #endif 1372 WREG32(CP_RB_CNTL, tmp); 1373 WREG32(CP_SEM_WAIT_TIMER, 0x4); 1374 1375 /* Set the write pointer delay */ 1376 WREG32(CP_RB_WPTR_DELAY, 0); 1377 1378 /* Initialize the ring buffer's read and write pointers */ 1379 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 1380 WREG32(CP_RB_RPTR_WR, 0); 1381 WREG32(CP_RB_WPTR, 0); 1382 1383 /* set the wb address wether it's enabled or not */ 1384 WREG32(CP_RB_RPTR_ADDR, 1385 #ifdef __BIG_ENDIAN 1386 RB_RPTR_SWAP(2) | 1387 #endif 1388 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 1389 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 1390 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 1391 1392 if (rdev->wb.enabled) 1393 WREG32(SCRATCH_UMSK, 0xff); 1394 else { 1395 tmp |= RB_NO_UPDATE; 1396 WREG32(SCRATCH_UMSK, 0); 1397 } 1398 1399 mdelay(1); 1400 WREG32(CP_RB_CNTL, tmp); 1401 1402 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); 1403 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 1404 1405 rdev->cp.rptr = RREG32(CP_RB_RPTR); 1406 rdev->cp.wptr = RREG32(CP_RB_WPTR); 1407 1408 evergreen_cp_start(rdev); 1409 rdev->cp.ready = true; 1410 r = radeon_ring_test(rdev); 1411 if (r) { 1412 rdev->cp.ready = false; 1413 return r; 1414 } 1415 return 0; 1416 } 1417 1418 /* 1419 * Core functions 1420 */ 1421 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 1422 u32 num_tile_pipes, 1423 u32 num_backends, 1424 u32 backend_disable_mask) 1425 { 1426 u32 backend_map = 0; 1427 u32 enabled_backends_mask = 0; 1428 u32 enabled_backends_count = 0; 1429 u32 cur_pipe; 1430 u32 swizzle_pipe[EVERGREEN_MAX_PIPES]; 1431 u32 cur_backend = 0; 1432 u32 i; 1433 bool force_no_swizzle; 1434 1435 if (num_tile_pipes > EVERGREEN_MAX_PIPES) 1436 num_tile_pipes = EVERGREEN_MAX_PIPES; 1437 if (num_tile_pipes < 1) 1438 num_tile_pipes = 1; 1439 if (num_backends > EVERGREEN_MAX_BACKENDS) 1440 num_backends = EVERGREEN_MAX_BACKENDS; 1441 if (num_backends < 1) 1442 num_backends = 1; 1443 1444 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) { 1445 if (((backend_disable_mask >> i) & 1) == 0) { 1446 enabled_backends_mask |= (1 << i); 1447 ++enabled_backends_count; 1448 } 1449 if (enabled_backends_count == num_backends) 1450 break; 1451 } 1452 1453 if (enabled_backends_count == 0) { 1454 enabled_backends_mask = 1; 1455 enabled_backends_count = 1; 1456 } 1457 1458 if (enabled_backends_count != num_backends) 1459 num_backends = enabled_backends_count; 1460 1461 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES); 1462 switch (rdev->family) { 1463 case CHIP_CEDAR: 1464 case CHIP_REDWOOD: 1465 case CHIP_PALM: 1466 case CHIP_SUMO: 1467 case CHIP_SUMO2: 1468 case CHIP_TURKS: 1469 case CHIP_CAICOS: 1470 force_no_swizzle = false; 1471 break; 1472 case CHIP_CYPRESS: 1473 case CHIP_HEMLOCK: 1474 case CHIP_JUNIPER: 1475 case CHIP_BARTS: 1476 default: 1477 force_no_swizzle = true; 1478 break; 1479 } 1480 if (force_no_swizzle) { 1481 bool last_backend_enabled = false; 1482 1483 force_no_swizzle = false; 1484 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) { 1485 if (((enabled_backends_mask >> i) & 1) == 1) { 1486 if (last_backend_enabled) 1487 force_no_swizzle = true; 1488 last_backend_enabled = true; 1489 } else 1490 last_backend_enabled = false; 1491 } 1492 } 1493 1494 switch (num_tile_pipes) { 1495 case 1: 1496 case 3: 1497 case 5: 1498 case 7: 1499 DRM_ERROR("odd number of pipes!\n"); 1500 break; 1501 case 2: 1502 swizzle_pipe[0] = 0; 1503 swizzle_pipe[1] = 1; 1504 break; 1505 case 4: 1506 if (force_no_swizzle) { 1507 swizzle_pipe[0] = 0; 1508 swizzle_pipe[1] = 1; 1509 swizzle_pipe[2] = 2; 1510 swizzle_pipe[3] = 3; 1511 } else { 1512 swizzle_pipe[0] = 0; 1513 swizzle_pipe[1] = 2; 1514 swizzle_pipe[2] = 1; 1515 swizzle_pipe[3] = 3; 1516 } 1517 break; 1518 case 6: 1519 if (force_no_swizzle) { 1520 swizzle_pipe[0] = 0; 1521 swizzle_pipe[1] = 1; 1522 swizzle_pipe[2] = 2; 1523 swizzle_pipe[3] = 3; 1524 swizzle_pipe[4] = 4; 1525 swizzle_pipe[5] = 5; 1526 } else { 1527 swizzle_pipe[0] = 0; 1528 swizzle_pipe[1] = 2; 1529 swizzle_pipe[2] = 4; 1530 swizzle_pipe[3] = 1; 1531 swizzle_pipe[4] = 3; 1532 swizzle_pipe[5] = 5; 1533 } 1534 break; 1535 case 8: 1536 if (force_no_swizzle) { 1537 swizzle_pipe[0] = 0; 1538 swizzle_pipe[1] = 1; 1539 swizzle_pipe[2] = 2; 1540 swizzle_pipe[3] = 3; 1541 swizzle_pipe[4] = 4; 1542 swizzle_pipe[5] = 5; 1543 swizzle_pipe[6] = 6; 1544 swizzle_pipe[7] = 7; 1545 } else { 1546 swizzle_pipe[0] = 0; 1547 swizzle_pipe[1] = 2; 1548 swizzle_pipe[2] = 4; 1549 swizzle_pipe[3] = 6; 1550 swizzle_pipe[4] = 1; 1551 swizzle_pipe[5] = 3; 1552 swizzle_pipe[6] = 5; 1553 swizzle_pipe[7] = 7; 1554 } 1555 break; 1556 } 1557 1558 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1559 while (((1 << cur_backend) & enabled_backends_mask) == 0) 1560 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS; 1561 1562 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4))); 1563 1564 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS; 1565 } 1566 1567 return backend_map; 1568 } 1569 1570 static void evergreen_program_channel_remap(struct radeon_device *rdev) 1571 { 1572 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp; 1573 1574 tmp = RREG32(MC_SHARED_CHMAP); 1575 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1576 case 0: 1577 case 1: 1578 case 2: 1579 case 3: 1580 default: 1581 /* default mapping */ 1582 mc_shared_chremap = 0x00fac688; 1583 break; 1584 } 1585 1586 switch (rdev->family) { 1587 case CHIP_HEMLOCK: 1588 case CHIP_CYPRESS: 1589 case CHIP_BARTS: 1590 tcp_chan_steer_lo = 0x54763210; 1591 tcp_chan_steer_hi = 0x0000ba98; 1592 break; 1593 case CHIP_JUNIPER: 1594 case CHIP_REDWOOD: 1595 case CHIP_CEDAR: 1596 case CHIP_PALM: 1597 case CHIP_SUMO: 1598 case CHIP_SUMO2: 1599 case CHIP_TURKS: 1600 case CHIP_CAICOS: 1601 default: 1602 tcp_chan_steer_lo = 0x76543210; 1603 tcp_chan_steer_hi = 0x0000ba98; 1604 break; 1605 } 1606 1607 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo); 1608 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi); 1609 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); 1610 } 1611 1612 static void evergreen_gpu_init(struct radeon_device *rdev) 1613 { 1614 u32 cc_rb_backend_disable = 0; 1615 u32 cc_gc_shader_pipe_config; 1616 u32 gb_addr_config = 0; 1617 u32 mc_shared_chmap, mc_arb_ramcfg; 1618 u32 gb_backend_map; 1619 u32 grbm_gfx_index; 1620 u32 sx_debug_1; 1621 u32 smx_dc_ctl0; 1622 u32 sq_config; 1623 u32 sq_lds_resource_mgmt; 1624 u32 sq_gpr_resource_mgmt_1; 1625 u32 sq_gpr_resource_mgmt_2; 1626 u32 sq_gpr_resource_mgmt_3; 1627 u32 sq_thread_resource_mgmt; 1628 u32 sq_thread_resource_mgmt_2; 1629 u32 sq_stack_resource_mgmt_1; 1630 u32 sq_stack_resource_mgmt_2; 1631 u32 sq_stack_resource_mgmt_3; 1632 u32 vgt_cache_invalidation; 1633 u32 hdp_host_path_cntl, tmp; 1634 int i, j, num_shader_engines, ps_thread_count; 1635 1636 switch (rdev->family) { 1637 case CHIP_CYPRESS: 1638 case CHIP_HEMLOCK: 1639 rdev->config.evergreen.num_ses = 2; 1640 rdev->config.evergreen.max_pipes = 4; 1641 rdev->config.evergreen.max_tile_pipes = 8; 1642 rdev->config.evergreen.max_simds = 10; 1643 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; 1644 rdev->config.evergreen.max_gprs = 256; 1645 rdev->config.evergreen.max_threads = 248; 1646 rdev->config.evergreen.max_gs_threads = 32; 1647 rdev->config.evergreen.max_stack_entries = 512; 1648 rdev->config.evergreen.sx_num_of_sets = 4; 1649 rdev->config.evergreen.sx_max_export_size = 256; 1650 rdev->config.evergreen.sx_max_export_pos_size = 64; 1651 rdev->config.evergreen.sx_max_export_smx_size = 192; 1652 rdev->config.evergreen.max_hw_contexts = 8; 1653 rdev->config.evergreen.sq_num_cf_insts = 2; 1654 1655 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1656 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1657 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1658 break; 1659 case CHIP_JUNIPER: 1660 rdev->config.evergreen.num_ses = 1; 1661 rdev->config.evergreen.max_pipes = 4; 1662 rdev->config.evergreen.max_tile_pipes = 4; 1663 rdev->config.evergreen.max_simds = 10; 1664 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; 1665 rdev->config.evergreen.max_gprs = 256; 1666 rdev->config.evergreen.max_threads = 248; 1667 rdev->config.evergreen.max_gs_threads = 32; 1668 rdev->config.evergreen.max_stack_entries = 512; 1669 rdev->config.evergreen.sx_num_of_sets = 4; 1670 rdev->config.evergreen.sx_max_export_size = 256; 1671 rdev->config.evergreen.sx_max_export_pos_size = 64; 1672 rdev->config.evergreen.sx_max_export_smx_size = 192; 1673 rdev->config.evergreen.max_hw_contexts = 8; 1674 rdev->config.evergreen.sq_num_cf_insts = 2; 1675 1676 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1677 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1678 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1679 break; 1680 case CHIP_REDWOOD: 1681 rdev->config.evergreen.num_ses = 1; 1682 rdev->config.evergreen.max_pipes = 4; 1683 rdev->config.evergreen.max_tile_pipes = 4; 1684 rdev->config.evergreen.max_simds = 5; 1685 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; 1686 rdev->config.evergreen.max_gprs = 256; 1687 rdev->config.evergreen.max_threads = 248; 1688 rdev->config.evergreen.max_gs_threads = 32; 1689 rdev->config.evergreen.max_stack_entries = 256; 1690 rdev->config.evergreen.sx_num_of_sets = 4; 1691 rdev->config.evergreen.sx_max_export_size = 256; 1692 rdev->config.evergreen.sx_max_export_pos_size = 64; 1693 rdev->config.evergreen.sx_max_export_smx_size = 192; 1694 rdev->config.evergreen.max_hw_contexts = 8; 1695 rdev->config.evergreen.sq_num_cf_insts = 2; 1696 1697 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1698 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1699 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1700 break; 1701 case CHIP_CEDAR: 1702 default: 1703 rdev->config.evergreen.num_ses = 1; 1704 rdev->config.evergreen.max_pipes = 2; 1705 rdev->config.evergreen.max_tile_pipes = 2; 1706 rdev->config.evergreen.max_simds = 2; 1707 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1708 rdev->config.evergreen.max_gprs = 256; 1709 rdev->config.evergreen.max_threads = 192; 1710 rdev->config.evergreen.max_gs_threads = 16; 1711 rdev->config.evergreen.max_stack_entries = 256; 1712 rdev->config.evergreen.sx_num_of_sets = 4; 1713 rdev->config.evergreen.sx_max_export_size = 128; 1714 rdev->config.evergreen.sx_max_export_pos_size = 32; 1715 rdev->config.evergreen.sx_max_export_smx_size = 96; 1716 rdev->config.evergreen.max_hw_contexts = 4; 1717 rdev->config.evergreen.sq_num_cf_insts = 1; 1718 1719 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1720 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1721 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1722 break; 1723 case CHIP_PALM: 1724 rdev->config.evergreen.num_ses = 1; 1725 rdev->config.evergreen.max_pipes = 2; 1726 rdev->config.evergreen.max_tile_pipes = 2; 1727 rdev->config.evergreen.max_simds = 2; 1728 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1729 rdev->config.evergreen.max_gprs = 256; 1730 rdev->config.evergreen.max_threads = 192; 1731 rdev->config.evergreen.max_gs_threads = 16; 1732 rdev->config.evergreen.max_stack_entries = 256; 1733 rdev->config.evergreen.sx_num_of_sets = 4; 1734 rdev->config.evergreen.sx_max_export_size = 128; 1735 rdev->config.evergreen.sx_max_export_pos_size = 32; 1736 rdev->config.evergreen.sx_max_export_smx_size = 96; 1737 rdev->config.evergreen.max_hw_contexts = 4; 1738 rdev->config.evergreen.sq_num_cf_insts = 1; 1739 1740 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1741 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1742 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1743 break; 1744 case CHIP_SUMO: 1745 rdev->config.evergreen.num_ses = 1; 1746 rdev->config.evergreen.max_pipes = 4; 1747 rdev->config.evergreen.max_tile_pipes = 2; 1748 if (rdev->pdev->device == 0x9648) 1749 rdev->config.evergreen.max_simds = 3; 1750 else if ((rdev->pdev->device == 0x9647) || 1751 (rdev->pdev->device == 0x964a)) 1752 rdev->config.evergreen.max_simds = 4; 1753 else 1754 rdev->config.evergreen.max_simds = 5; 1755 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; 1756 rdev->config.evergreen.max_gprs = 256; 1757 rdev->config.evergreen.max_threads = 248; 1758 rdev->config.evergreen.max_gs_threads = 32; 1759 rdev->config.evergreen.max_stack_entries = 256; 1760 rdev->config.evergreen.sx_num_of_sets = 4; 1761 rdev->config.evergreen.sx_max_export_size = 256; 1762 rdev->config.evergreen.sx_max_export_pos_size = 64; 1763 rdev->config.evergreen.sx_max_export_smx_size = 192; 1764 rdev->config.evergreen.max_hw_contexts = 8; 1765 rdev->config.evergreen.sq_num_cf_insts = 2; 1766 1767 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1768 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1769 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1770 break; 1771 case CHIP_SUMO2: 1772 rdev->config.evergreen.num_ses = 1; 1773 rdev->config.evergreen.max_pipes = 4; 1774 rdev->config.evergreen.max_tile_pipes = 4; 1775 rdev->config.evergreen.max_simds = 2; 1776 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1777 rdev->config.evergreen.max_gprs = 256; 1778 rdev->config.evergreen.max_threads = 248; 1779 rdev->config.evergreen.max_gs_threads = 32; 1780 rdev->config.evergreen.max_stack_entries = 512; 1781 rdev->config.evergreen.sx_num_of_sets = 4; 1782 rdev->config.evergreen.sx_max_export_size = 256; 1783 rdev->config.evergreen.sx_max_export_pos_size = 64; 1784 rdev->config.evergreen.sx_max_export_smx_size = 192; 1785 rdev->config.evergreen.max_hw_contexts = 8; 1786 rdev->config.evergreen.sq_num_cf_insts = 2; 1787 1788 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1789 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1790 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1791 break; 1792 case CHIP_BARTS: 1793 rdev->config.evergreen.num_ses = 2; 1794 rdev->config.evergreen.max_pipes = 4; 1795 rdev->config.evergreen.max_tile_pipes = 8; 1796 rdev->config.evergreen.max_simds = 7; 1797 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; 1798 rdev->config.evergreen.max_gprs = 256; 1799 rdev->config.evergreen.max_threads = 248; 1800 rdev->config.evergreen.max_gs_threads = 32; 1801 rdev->config.evergreen.max_stack_entries = 512; 1802 rdev->config.evergreen.sx_num_of_sets = 4; 1803 rdev->config.evergreen.sx_max_export_size = 256; 1804 rdev->config.evergreen.sx_max_export_pos_size = 64; 1805 rdev->config.evergreen.sx_max_export_smx_size = 192; 1806 rdev->config.evergreen.max_hw_contexts = 8; 1807 rdev->config.evergreen.sq_num_cf_insts = 2; 1808 1809 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1810 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1811 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1812 break; 1813 case CHIP_TURKS: 1814 rdev->config.evergreen.num_ses = 1; 1815 rdev->config.evergreen.max_pipes = 4; 1816 rdev->config.evergreen.max_tile_pipes = 4; 1817 rdev->config.evergreen.max_simds = 6; 1818 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; 1819 rdev->config.evergreen.max_gprs = 256; 1820 rdev->config.evergreen.max_threads = 248; 1821 rdev->config.evergreen.max_gs_threads = 32; 1822 rdev->config.evergreen.max_stack_entries = 256; 1823 rdev->config.evergreen.sx_num_of_sets = 4; 1824 rdev->config.evergreen.sx_max_export_size = 256; 1825 rdev->config.evergreen.sx_max_export_pos_size = 64; 1826 rdev->config.evergreen.sx_max_export_smx_size = 192; 1827 rdev->config.evergreen.max_hw_contexts = 8; 1828 rdev->config.evergreen.sq_num_cf_insts = 2; 1829 1830 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1831 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1832 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1833 break; 1834 case CHIP_CAICOS: 1835 rdev->config.evergreen.num_ses = 1; 1836 rdev->config.evergreen.max_pipes = 4; 1837 rdev->config.evergreen.max_tile_pipes = 2; 1838 rdev->config.evergreen.max_simds = 2; 1839 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1840 rdev->config.evergreen.max_gprs = 256; 1841 rdev->config.evergreen.max_threads = 192; 1842 rdev->config.evergreen.max_gs_threads = 16; 1843 rdev->config.evergreen.max_stack_entries = 256; 1844 rdev->config.evergreen.sx_num_of_sets = 4; 1845 rdev->config.evergreen.sx_max_export_size = 128; 1846 rdev->config.evergreen.sx_max_export_pos_size = 32; 1847 rdev->config.evergreen.sx_max_export_smx_size = 96; 1848 rdev->config.evergreen.max_hw_contexts = 4; 1849 rdev->config.evergreen.sq_num_cf_insts = 1; 1850 1851 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1852 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1853 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1854 break; 1855 } 1856 1857 /* Initialize HDP */ 1858 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1859 WREG32((0x2c14 + j), 0x00000000); 1860 WREG32((0x2c18 + j), 0x00000000); 1861 WREG32((0x2c1c + j), 0x00000000); 1862 WREG32((0x2c20 + j), 0x00000000); 1863 WREG32((0x2c24 + j), 0x00000000); 1864 } 1865 1866 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1867 1868 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2; 1869 1870 cc_gc_shader_pipe_config |= 1871 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes) 1872 & EVERGREEN_MAX_PIPES_MASK); 1873 cc_gc_shader_pipe_config |= 1874 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds) 1875 & EVERGREEN_MAX_SIMDS_MASK); 1876 1877 cc_rb_backend_disable = 1878 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends) 1879 & EVERGREEN_MAX_BACKENDS_MASK); 1880 1881 1882 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1883 if (rdev->flags & RADEON_IS_IGP) 1884 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG); 1885 else 1886 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1887 1888 switch (rdev->config.evergreen.max_tile_pipes) { 1889 case 1: 1890 default: 1891 gb_addr_config |= NUM_PIPES(0); 1892 break; 1893 case 2: 1894 gb_addr_config |= NUM_PIPES(1); 1895 break; 1896 case 4: 1897 gb_addr_config |= NUM_PIPES(2); 1898 break; 1899 case 8: 1900 gb_addr_config |= NUM_PIPES(3); 1901 break; 1902 } 1903 1904 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1905 gb_addr_config |= BANK_INTERLEAVE_SIZE(0); 1906 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1); 1907 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1); 1908 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */ 1909 gb_addr_config |= MULTI_GPU_TILE_SIZE(2); 1910 1911 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2) 1912 gb_addr_config |= ROW_SIZE(2); 1913 else 1914 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT); 1915 1916 if (rdev->ddev->pdev->device == 0x689e) { 1917 u32 efuse_straps_4; 1918 u32 efuse_straps_3; 1919 u8 efuse_box_bit_131_124; 1920 1921 WREG32(RCU_IND_INDEX, 0x204); 1922 efuse_straps_4 = RREG32(RCU_IND_DATA); 1923 WREG32(RCU_IND_INDEX, 0x203); 1924 efuse_straps_3 = RREG32(RCU_IND_DATA); 1925 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28)); 1926 1927 switch(efuse_box_bit_131_124) { 1928 case 0x00: 1929 gb_backend_map = 0x76543210; 1930 break; 1931 case 0x55: 1932 gb_backend_map = 0x77553311; 1933 break; 1934 case 0x56: 1935 gb_backend_map = 0x77553300; 1936 break; 1937 case 0x59: 1938 gb_backend_map = 0x77552211; 1939 break; 1940 case 0x66: 1941 gb_backend_map = 0x77443300; 1942 break; 1943 case 0x99: 1944 gb_backend_map = 0x66552211; 1945 break; 1946 case 0x5a: 1947 gb_backend_map = 0x77552200; 1948 break; 1949 case 0xaa: 1950 gb_backend_map = 0x66442200; 1951 break; 1952 case 0x95: 1953 gb_backend_map = 0x66553311; 1954 break; 1955 default: 1956 DRM_ERROR("bad backend map, using default\n"); 1957 gb_backend_map = 1958 evergreen_get_tile_pipe_to_backend_map(rdev, 1959 rdev->config.evergreen.max_tile_pipes, 1960 rdev->config.evergreen.max_backends, 1961 ((EVERGREEN_MAX_BACKENDS_MASK << 1962 rdev->config.evergreen.max_backends) & 1963 EVERGREEN_MAX_BACKENDS_MASK)); 1964 break; 1965 } 1966 } else if (rdev->ddev->pdev->device == 0x68b9) { 1967 u32 efuse_straps_3; 1968 u8 efuse_box_bit_127_124; 1969 1970 WREG32(RCU_IND_INDEX, 0x203); 1971 efuse_straps_3 = RREG32(RCU_IND_DATA); 1972 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28); 1973 1974 switch(efuse_box_bit_127_124) { 1975 case 0x0: 1976 gb_backend_map = 0x00003210; 1977 break; 1978 case 0x5: 1979 case 0x6: 1980 case 0x9: 1981 case 0xa: 1982 gb_backend_map = 0x00003311; 1983 break; 1984 default: 1985 DRM_ERROR("bad backend map, using default\n"); 1986 gb_backend_map = 1987 evergreen_get_tile_pipe_to_backend_map(rdev, 1988 rdev->config.evergreen.max_tile_pipes, 1989 rdev->config.evergreen.max_backends, 1990 ((EVERGREEN_MAX_BACKENDS_MASK << 1991 rdev->config.evergreen.max_backends) & 1992 EVERGREEN_MAX_BACKENDS_MASK)); 1993 break; 1994 } 1995 } else { 1996 switch (rdev->family) { 1997 case CHIP_CYPRESS: 1998 case CHIP_HEMLOCK: 1999 case CHIP_BARTS: 2000 gb_backend_map = 0x66442200; 2001 break; 2002 case CHIP_JUNIPER: 2003 gb_backend_map = 0x00002200; 2004 break; 2005 default: 2006 gb_backend_map = 2007 evergreen_get_tile_pipe_to_backend_map(rdev, 2008 rdev->config.evergreen.max_tile_pipes, 2009 rdev->config.evergreen.max_backends, 2010 ((EVERGREEN_MAX_BACKENDS_MASK << 2011 rdev->config.evergreen.max_backends) & 2012 EVERGREEN_MAX_BACKENDS_MASK)); 2013 } 2014 } 2015 2016 /* setup tiling info dword. gb_addr_config is not adequate since it does 2017 * not have bank info, so create a custom tiling dword. 2018 * bits 3:0 num_pipes 2019 * bits 7:4 num_banks 2020 * bits 11:8 group_size 2021 * bits 15:12 row_size 2022 */ 2023 rdev->config.evergreen.tile_config = 0; 2024 switch (rdev->config.evergreen.max_tile_pipes) { 2025 case 1: 2026 default: 2027 rdev->config.evergreen.tile_config |= (0 << 0); 2028 break; 2029 case 2: 2030 rdev->config.evergreen.tile_config |= (1 << 0); 2031 break; 2032 case 4: 2033 rdev->config.evergreen.tile_config |= (2 << 0); 2034 break; 2035 case 8: 2036 rdev->config.evergreen.tile_config |= (3 << 0); 2037 break; 2038 } 2039 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ 2040 if (rdev->flags & RADEON_IS_IGP) 2041 rdev->config.evergreen.tile_config |= 1 << 4; 2042 else 2043 rdev->config.evergreen.tile_config |= 2044 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; 2045 rdev->config.evergreen.tile_config |= 2046 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8; 2047 rdev->config.evergreen.tile_config |= 2048 ((gb_addr_config & 0x30000000) >> 28) << 12; 2049 2050 WREG32(GB_BACKEND_MAP, gb_backend_map); 2051 WREG32(GB_ADDR_CONFIG, gb_addr_config); 2052 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 2053 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 2054 2055 evergreen_program_channel_remap(rdev); 2056 2057 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1; 2058 grbm_gfx_index = INSTANCE_BROADCAST_WRITES; 2059 2060 for (i = 0; i < rdev->config.evergreen.num_ses; i++) { 2061 u32 rb = cc_rb_backend_disable | (0xf0 << 16); 2062 u32 sp = cc_gc_shader_pipe_config; 2063 u32 gfx = grbm_gfx_index | SE_INDEX(i); 2064 2065 if (i == num_shader_engines) { 2066 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK); 2067 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK); 2068 } 2069 2070 WREG32(GRBM_GFX_INDEX, gfx); 2071 WREG32(RLC_GFX_INDEX, gfx); 2072 2073 WREG32(CC_RB_BACKEND_DISABLE, rb); 2074 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb); 2075 WREG32(GC_USER_RB_BACKEND_DISABLE, rb); 2076 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp); 2077 } 2078 2079 grbm_gfx_index |= SE_BROADCAST_WRITES; 2080 WREG32(GRBM_GFX_INDEX, grbm_gfx_index); 2081 WREG32(RLC_GFX_INDEX, grbm_gfx_index); 2082 2083 WREG32(CGTS_SYS_TCC_DISABLE, 0); 2084 WREG32(CGTS_TCC_DISABLE, 0); 2085 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); 2086 WREG32(CGTS_USER_TCC_DISABLE, 0); 2087 2088 /* set HW defaults for 3D engine */ 2089 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 2090 ROQ_IB2_START(0x2b))); 2091 2092 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); 2093 2094 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | 2095 SYNC_GRADIENT | 2096 SYNC_WALKER | 2097 SYNC_ALIGNER)); 2098 2099 sx_debug_1 = RREG32(SX_DEBUG_1); 2100 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 2101 WREG32(SX_DEBUG_1, sx_debug_1); 2102 2103 2104 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 2105 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); 2106 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); 2107 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 2108 2109 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) | 2110 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | 2111 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); 2112 2113 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | 2114 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) | 2115 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size))); 2116 2117 WREG32(VGT_NUM_INSTANCES, 1); 2118 WREG32(SPI_CONFIG_CNTL, 0); 2119 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 2120 WREG32(CP_PERFMON_CNTL, 0); 2121 2122 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | 2123 FETCH_FIFO_HIWATER(0x4) | 2124 DONE_FIFO_HIWATER(0xe0) | 2125 ALU_UPDATE_FIFO_HIWATER(0x8))); 2126 2127 sq_config = RREG32(SQ_CONFIG); 2128 sq_config &= ~(PS_PRIO(3) | 2129 VS_PRIO(3) | 2130 GS_PRIO(3) | 2131 ES_PRIO(3)); 2132 sq_config |= (VC_ENABLE | 2133 EXPORT_SRC_C | 2134 PS_PRIO(0) | 2135 VS_PRIO(1) | 2136 GS_PRIO(2) | 2137 ES_PRIO(3)); 2138 2139 switch (rdev->family) { 2140 case CHIP_CEDAR: 2141 case CHIP_PALM: 2142 case CHIP_SUMO: 2143 case CHIP_SUMO2: 2144 case CHIP_CAICOS: 2145 /* no vertex cache */ 2146 sq_config &= ~VC_ENABLE; 2147 break; 2148 default: 2149 break; 2150 } 2151 2152 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT); 2153 2154 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32); 2155 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32); 2156 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4); 2157 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); 2158 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); 2159 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); 2160 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); 2161 2162 switch (rdev->family) { 2163 case CHIP_CEDAR: 2164 case CHIP_PALM: 2165 case CHIP_SUMO: 2166 case CHIP_SUMO2: 2167 ps_thread_count = 96; 2168 break; 2169 default: 2170 ps_thread_count = 128; 2171 break; 2172 } 2173 2174 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count); 2175 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2176 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2177 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2178 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2179 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2180 2181 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2182 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2183 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2184 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2185 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2186 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2187 2188 WREG32(SQ_CONFIG, sq_config); 2189 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2190 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2191 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3); 2192 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2193 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2); 2194 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2195 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2196 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3); 2197 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); 2198 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt); 2199 2200 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 2201 FORCE_EOV_MAX_REZ_CNT(255))); 2202 2203 switch (rdev->family) { 2204 case CHIP_CEDAR: 2205 case CHIP_PALM: 2206 case CHIP_SUMO: 2207 case CHIP_SUMO2: 2208 case CHIP_CAICOS: 2209 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY); 2210 break; 2211 default: 2212 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC); 2213 break; 2214 } 2215 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO); 2216 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation); 2217 2218 WREG32(VGT_GS_VERTEX_REUSE, 16); 2219 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0); 2220 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2221 2222 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14); 2223 WREG32(VGT_OUT_DEALLOC_CNTL, 16); 2224 2225 WREG32(CB_PERF_CTR0_SEL_0, 0); 2226 WREG32(CB_PERF_CTR0_SEL_1, 0); 2227 WREG32(CB_PERF_CTR1_SEL_0, 0); 2228 WREG32(CB_PERF_CTR1_SEL_1, 0); 2229 WREG32(CB_PERF_CTR2_SEL_0, 0); 2230 WREG32(CB_PERF_CTR2_SEL_1, 0); 2231 WREG32(CB_PERF_CTR3_SEL_0, 0); 2232 WREG32(CB_PERF_CTR3_SEL_1, 0); 2233 2234 /* clear render buffer base addresses */ 2235 WREG32(CB_COLOR0_BASE, 0); 2236 WREG32(CB_COLOR1_BASE, 0); 2237 WREG32(CB_COLOR2_BASE, 0); 2238 WREG32(CB_COLOR3_BASE, 0); 2239 WREG32(CB_COLOR4_BASE, 0); 2240 WREG32(CB_COLOR5_BASE, 0); 2241 WREG32(CB_COLOR6_BASE, 0); 2242 WREG32(CB_COLOR7_BASE, 0); 2243 WREG32(CB_COLOR8_BASE, 0); 2244 WREG32(CB_COLOR9_BASE, 0); 2245 WREG32(CB_COLOR10_BASE, 0); 2246 WREG32(CB_COLOR11_BASE, 0); 2247 2248 /* set the shader const cache sizes to 0 */ 2249 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4) 2250 WREG32(i, 0); 2251 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4) 2252 WREG32(i, 0); 2253 2254 tmp = RREG32(HDP_MISC_CNTL); 2255 tmp |= HDP_FLUSH_INVALIDATE_CACHE; 2256 WREG32(HDP_MISC_CNTL, tmp); 2257 2258 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 2259 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 2260 2261 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 2262 2263 udelay(50); 2264 2265 } 2266 2267 int evergreen_mc_init(struct radeon_device *rdev) 2268 { 2269 u32 tmp; 2270 int chansize, numchan; 2271 2272 /* Get VRAM informations */ 2273 rdev->mc.vram_is_ddr = true; 2274 if (rdev->flags & RADEON_IS_IGP) 2275 tmp = RREG32(FUS_MC_ARB_RAMCFG); 2276 else 2277 tmp = RREG32(MC_ARB_RAMCFG); 2278 if (tmp & CHANSIZE_OVERRIDE) { 2279 chansize = 16; 2280 } else if (tmp & CHANSIZE_MASK) { 2281 chansize = 64; 2282 } else { 2283 chansize = 32; 2284 } 2285 tmp = RREG32(MC_SHARED_CHMAP); 2286 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 2287 case 0: 2288 default: 2289 numchan = 1; 2290 break; 2291 case 1: 2292 numchan = 2; 2293 break; 2294 case 2: 2295 numchan = 4; 2296 break; 2297 case 3: 2298 numchan = 8; 2299 break; 2300 } 2301 rdev->mc.vram_width = numchan * chansize; 2302 /* Could aper size report 0 ? */ 2303 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2304 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2305 /* Setup GPU memory space */ 2306 if (rdev->flags & RADEON_IS_IGP) { 2307 /* size in bytes on fusion */ 2308 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 2309 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 2310 } else { 2311 /* size in MB on evergreen */ 2312 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2313 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2314 } 2315 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2316 r700_vram_gtt_location(rdev, &rdev->mc); 2317 radeon_update_bandwidth_info(rdev); 2318 2319 return 0; 2320 } 2321 2322 bool evergreen_gpu_is_lockup(struct radeon_device *rdev) 2323 { 2324 u32 srbm_status; 2325 u32 grbm_status; 2326 u32 grbm_status_se0, grbm_status_se1; 2327 struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup; 2328 int r; 2329 2330 srbm_status = RREG32(SRBM_STATUS); 2331 grbm_status = RREG32(GRBM_STATUS); 2332 grbm_status_se0 = RREG32(GRBM_STATUS_SE0); 2333 grbm_status_se1 = RREG32(GRBM_STATUS_SE1); 2334 if (!(grbm_status & GUI_ACTIVE)) { 2335 r100_gpu_lockup_update(lockup, &rdev->cp); 2336 return false; 2337 } 2338 /* force CP activities */ 2339 r = radeon_ring_lock(rdev, 2); 2340 if (!r) { 2341 /* PACKET2 NOP */ 2342 radeon_ring_write(rdev, 0x80000000); 2343 radeon_ring_write(rdev, 0x80000000); 2344 radeon_ring_unlock_commit(rdev); 2345 } 2346 rdev->cp.rptr = RREG32(CP_RB_RPTR); 2347 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp); 2348 } 2349 2350 static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 2351 { 2352 struct evergreen_mc_save save; 2353 u32 grbm_reset = 0; 2354 2355 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2356 return 0; 2357 2358 dev_info(rdev->dev, "GPU softreset \n"); 2359 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2360 RREG32(GRBM_STATUS)); 2361 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2362 RREG32(GRBM_STATUS_SE0)); 2363 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2364 RREG32(GRBM_STATUS_SE1)); 2365 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 2366 RREG32(SRBM_STATUS)); 2367 evergreen_mc_stop(rdev, &save); 2368 if (evergreen_mc_wait_for_idle(rdev)) { 2369 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2370 } 2371 /* Disable CP parsing/prefetching */ 2372 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); 2373 2374 /* reset all the gfx blocks */ 2375 grbm_reset = (SOFT_RESET_CP | 2376 SOFT_RESET_CB | 2377 SOFT_RESET_DB | 2378 SOFT_RESET_PA | 2379 SOFT_RESET_SC | 2380 SOFT_RESET_SPI | 2381 SOFT_RESET_SH | 2382 SOFT_RESET_SX | 2383 SOFT_RESET_TC | 2384 SOFT_RESET_TA | 2385 SOFT_RESET_VC | 2386 SOFT_RESET_VGT); 2387 2388 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); 2389 WREG32(GRBM_SOFT_RESET, grbm_reset); 2390 (void)RREG32(GRBM_SOFT_RESET); 2391 udelay(50); 2392 WREG32(GRBM_SOFT_RESET, 0); 2393 (void)RREG32(GRBM_SOFT_RESET); 2394 /* Wait a little for things to settle down */ 2395 udelay(50); 2396 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2397 RREG32(GRBM_STATUS)); 2398 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2399 RREG32(GRBM_STATUS_SE0)); 2400 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2401 RREG32(GRBM_STATUS_SE1)); 2402 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 2403 RREG32(SRBM_STATUS)); 2404 evergreen_mc_resume(rdev, &save); 2405 return 0; 2406 } 2407 2408 int evergreen_asic_reset(struct radeon_device *rdev) 2409 { 2410 return evergreen_gpu_soft_reset(rdev); 2411 } 2412 2413 /* Interrupts */ 2414 2415 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc) 2416 { 2417 switch (crtc) { 2418 case 0: 2419 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET); 2420 case 1: 2421 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET); 2422 case 2: 2423 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET); 2424 case 3: 2425 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET); 2426 case 4: 2427 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET); 2428 case 5: 2429 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET); 2430 default: 2431 return 0; 2432 } 2433 } 2434 2435 void evergreen_disable_interrupt_state(struct radeon_device *rdev) 2436 { 2437 u32 tmp; 2438 2439 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 2440 WREG32(GRBM_INT_CNTL, 0); 2441 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2442 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2443 if (rdev->num_crtc >= 4) { 2444 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2445 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2446 } 2447 if (rdev->num_crtc >= 6) { 2448 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2449 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2450 } 2451 2452 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2453 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2454 if (rdev->num_crtc >= 4) { 2455 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2456 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2457 } 2458 if (rdev->num_crtc >= 6) { 2459 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2460 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2461 } 2462 2463 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 2464 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 2465 2466 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2467 WREG32(DC_HPD1_INT_CONTROL, tmp); 2468 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2469 WREG32(DC_HPD2_INT_CONTROL, tmp); 2470 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2471 WREG32(DC_HPD3_INT_CONTROL, tmp); 2472 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2473 WREG32(DC_HPD4_INT_CONTROL, tmp); 2474 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2475 WREG32(DC_HPD5_INT_CONTROL, tmp); 2476 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2477 WREG32(DC_HPD6_INT_CONTROL, tmp); 2478 2479 } 2480 2481 int evergreen_irq_set(struct radeon_device *rdev) 2482 { 2483 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 2484 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 2485 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 2486 u32 grbm_int_cntl = 0; 2487 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; 2488 2489 if (!rdev->irq.installed) { 2490 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 2491 return -EINVAL; 2492 } 2493 /* don't enable anything if the ih is disabled */ 2494 if (!rdev->ih.enabled) { 2495 r600_disable_interrupts(rdev); 2496 /* force the active interrupt state to all disabled */ 2497 evergreen_disable_interrupt_state(rdev); 2498 return 0; 2499 } 2500 2501 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 2502 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 2503 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 2504 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 2505 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 2506 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 2507 2508 if (rdev->irq.sw_int) { 2509 DRM_DEBUG("evergreen_irq_set: sw int\n"); 2510 cp_int_cntl |= RB_INT_ENABLE; 2511 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 2512 } 2513 if (rdev->irq.crtc_vblank_int[0] || 2514 rdev->irq.pflip[0]) { 2515 DRM_DEBUG("evergreen_irq_set: vblank 0\n"); 2516 crtc1 |= VBLANK_INT_MASK; 2517 } 2518 if (rdev->irq.crtc_vblank_int[1] || 2519 rdev->irq.pflip[1]) { 2520 DRM_DEBUG("evergreen_irq_set: vblank 1\n"); 2521 crtc2 |= VBLANK_INT_MASK; 2522 } 2523 if (rdev->irq.crtc_vblank_int[2] || 2524 rdev->irq.pflip[2]) { 2525 DRM_DEBUG("evergreen_irq_set: vblank 2\n"); 2526 crtc3 |= VBLANK_INT_MASK; 2527 } 2528 if (rdev->irq.crtc_vblank_int[3] || 2529 rdev->irq.pflip[3]) { 2530 DRM_DEBUG("evergreen_irq_set: vblank 3\n"); 2531 crtc4 |= VBLANK_INT_MASK; 2532 } 2533 if (rdev->irq.crtc_vblank_int[4] || 2534 rdev->irq.pflip[4]) { 2535 DRM_DEBUG("evergreen_irq_set: vblank 4\n"); 2536 crtc5 |= VBLANK_INT_MASK; 2537 } 2538 if (rdev->irq.crtc_vblank_int[5] || 2539 rdev->irq.pflip[5]) { 2540 DRM_DEBUG("evergreen_irq_set: vblank 5\n"); 2541 crtc6 |= VBLANK_INT_MASK; 2542 } 2543 if (rdev->irq.hpd[0]) { 2544 DRM_DEBUG("evergreen_irq_set: hpd 1\n"); 2545 hpd1 |= DC_HPDx_INT_EN; 2546 } 2547 if (rdev->irq.hpd[1]) { 2548 DRM_DEBUG("evergreen_irq_set: hpd 2\n"); 2549 hpd2 |= DC_HPDx_INT_EN; 2550 } 2551 if (rdev->irq.hpd[2]) { 2552 DRM_DEBUG("evergreen_irq_set: hpd 3\n"); 2553 hpd3 |= DC_HPDx_INT_EN; 2554 } 2555 if (rdev->irq.hpd[3]) { 2556 DRM_DEBUG("evergreen_irq_set: hpd 4\n"); 2557 hpd4 |= DC_HPDx_INT_EN; 2558 } 2559 if (rdev->irq.hpd[4]) { 2560 DRM_DEBUG("evergreen_irq_set: hpd 5\n"); 2561 hpd5 |= DC_HPDx_INT_EN; 2562 } 2563 if (rdev->irq.hpd[5]) { 2564 DRM_DEBUG("evergreen_irq_set: hpd 6\n"); 2565 hpd6 |= DC_HPDx_INT_EN; 2566 } 2567 if (rdev->irq.gui_idle) { 2568 DRM_DEBUG("gui idle\n"); 2569 grbm_int_cntl |= GUI_IDLE_INT_ENABLE; 2570 } 2571 2572 WREG32(CP_INT_CNTL, cp_int_cntl); 2573 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 2574 2575 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 2576 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 2577 if (rdev->num_crtc >= 4) { 2578 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 2579 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 2580 } 2581 if (rdev->num_crtc >= 6) { 2582 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 2583 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 2584 } 2585 2586 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 2587 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 2588 if (rdev->num_crtc >= 4) { 2589 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 2590 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 2591 } 2592 if (rdev->num_crtc >= 6) { 2593 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 2594 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 2595 } 2596 2597 WREG32(DC_HPD1_INT_CONTROL, hpd1); 2598 WREG32(DC_HPD2_INT_CONTROL, hpd2); 2599 WREG32(DC_HPD3_INT_CONTROL, hpd3); 2600 WREG32(DC_HPD4_INT_CONTROL, hpd4); 2601 WREG32(DC_HPD5_INT_CONTROL, hpd5); 2602 WREG32(DC_HPD6_INT_CONTROL, hpd6); 2603 2604 return 0; 2605 } 2606 2607 static inline void evergreen_irq_ack(struct radeon_device *rdev) 2608 { 2609 u32 tmp; 2610 2611 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); 2612 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 2613 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); 2614 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); 2615 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); 2616 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 2617 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 2618 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 2619 if (rdev->num_crtc >= 4) { 2620 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 2621 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 2622 } 2623 if (rdev->num_crtc >= 6) { 2624 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 2625 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 2626 } 2627 2628 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) 2629 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2630 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) 2631 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2632 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) 2633 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 2634 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) 2635 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); 2636 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) 2637 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); 2638 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) 2639 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 2640 2641 if (rdev->num_crtc >= 4) { 2642 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) 2643 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2644 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) 2645 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2646 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 2647 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 2648 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 2649 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 2650 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 2651 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 2652 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 2653 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 2654 } 2655 2656 if (rdev->num_crtc >= 6) { 2657 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) 2658 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2659 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) 2660 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2661 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 2662 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 2663 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 2664 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 2665 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 2666 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 2667 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 2668 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 2669 } 2670 2671 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 2672 tmp = RREG32(DC_HPD1_INT_CONTROL); 2673 tmp |= DC_HPDx_INT_ACK; 2674 WREG32(DC_HPD1_INT_CONTROL, tmp); 2675 } 2676 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 2677 tmp = RREG32(DC_HPD2_INT_CONTROL); 2678 tmp |= DC_HPDx_INT_ACK; 2679 WREG32(DC_HPD2_INT_CONTROL, tmp); 2680 } 2681 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 2682 tmp = RREG32(DC_HPD3_INT_CONTROL); 2683 tmp |= DC_HPDx_INT_ACK; 2684 WREG32(DC_HPD3_INT_CONTROL, tmp); 2685 } 2686 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 2687 tmp = RREG32(DC_HPD4_INT_CONTROL); 2688 tmp |= DC_HPDx_INT_ACK; 2689 WREG32(DC_HPD4_INT_CONTROL, tmp); 2690 } 2691 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 2692 tmp = RREG32(DC_HPD5_INT_CONTROL); 2693 tmp |= DC_HPDx_INT_ACK; 2694 WREG32(DC_HPD5_INT_CONTROL, tmp); 2695 } 2696 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 2697 tmp = RREG32(DC_HPD5_INT_CONTROL); 2698 tmp |= DC_HPDx_INT_ACK; 2699 WREG32(DC_HPD6_INT_CONTROL, tmp); 2700 } 2701 } 2702 2703 void evergreen_irq_disable(struct radeon_device *rdev) 2704 { 2705 r600_disable_interrupts(rdev); 2706 /* Wait and acknowledge irq */ 2707 mdelay(1); 2708 evergreen_irq_ack(rdev); 2709 evergreen_disable_interrupt_state(rdev); 2710 } 2711 2712 void evergreen_irq_suspend(struct radeon_device *rdev) 2713 { 2714 evergreen_irq_disable(rdev); 2715 r600_rlc_stop(rdev); 2716 } 2717 2718 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev) 2719 { 2720 u32 wptr, tmp; 2721 2722 if (rdev->wb.enabled) 2723 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 2724 else 2725 wptr = RREG32(IH_RB_WPTR); 2726 2727 if (wptr & RB_OVERFLOW) { 2728 /* When a ring buffer overflow happen start parsing interrupt 2729 * from the last not overwritten vector (wptr + 16). Hopefully 2730 * this should allow us to catchup. 2731 */ 2732 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 2733 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 2734 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 2735 tmp = RREG32(IH_RB_CNTL); 2736 tmp |= IH_WPTR_OVERFLOW_CLEAR; 2737 WREG32(IH_RB_CNTL, tmp); 2738 } 2739 return (wptr & rdev->ih.ptr_mask); 2740 } 2741 2742 int evergreen_irq_process(struct radeon_device *rdev) 2743 { 2744 u32 wptr; 2745 u32 rptr; 2746 u32 src_id, src_data; 2747 u32 ring_index; 2748 unsigned long flags; 2749 bool queue_hotplug = false; 2750 2751 if (!rdev->ih.enabled || rdev->shutdown) 2752 return IRQ_NONE; 2753 2754 wptr = evergreen_get_ih_wptr(rdev); 2755 rptr = rdev->ih.rptr; 2756 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 2757 2758 spin_lock_irqsave(&rdev->ih.lock, flags); 2759 if (rptr == wptr) { 2760 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2761 return IRQ_NONE; 2762 } 2763 restart_ih: 2764 /* display interrupts */ 2765 evergreen_irq_ack(rdev); 2766 2767 rdev->ih.wptr = wptr; 2768 while (rptr != wptr) { 2769 /* wptr/rptr are in bytes! */ 2770 ring_index = rptr / 4; 2771 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 2772 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 2773 2774 switch (src_id) { 2775 case 1: /* D1 vblank/vline */ 2776 switch (src_data) { 2777 case 0: /* D1 vblank */ 2778 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { 2779 if (rdev->irq.crtc_vblank_int[0]) { 2780 drm_handle_vblank(rdev->ddev, 0); 2781 rdev->pm.vblank_sync = true; 2782 wake_up(&rdev->irq.vblank_queue); 2783 } 2784 if (rdev->irq.pflip[0]) 2785 radeon_crtc_handle_flip(rdev, 0); 2786 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 2787 DRM_DEBUG("IH: D1 vblank\n"); 2788 } 2789 break; 2790 case 1: /* D1 vline */ 2791 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { 2792 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; 2793 DRM_DEBUG("IH: D1 vline\n"); 2794 } 2795 break; 2796 default: 2797 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2798 break; 2799 } 2800 break; 2801 case 2: /* D2 vblank/vline */ 2802 switch (src_data) { 2803 case 0: /* D2 vblank */ 2804 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { 2805 if (rdev->irq.crtc_vblank_int[1]) { 2806 drm_handle_vblank(rdev->ddev, 1); 2807 rdev->pm.vblank_sync = true; 2808 wake_up(&rdev->irq.vblank_queue); 2809 } 2810 if (rdev->irq.pflip[1]) 2811 radeon_crtc_handle_flip(rdev, 1); 2812 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 2813 DRM_DEBUG("IH: D2 vblank\n"); 2814 } 2815 break; 2816 case 1: /* D2 vline */ 2817 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { 2818 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 2819 DRM_DEBUG("IH: D2 vline\n"); 2820 } 2821 break; 2822 default: 2823 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2824 break; 2825 } 2826 break; 2827 case 3: /* D3 vblank/vline */ 2828 switch (src_data) { 2829 case 0: /* D3 vblank */ 2830 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { 2831 if (rdev->irq.crtc_vblank_int[2]) { 2832 drm_handle_vblank(rdev->ddev, 2); 2833 rdev->pm.vblank_sync = true; 2834 wake_up(&rdev->irq.vblank_queue); 2835 } 2836 if (rdev->irq.pflip[2]) 2837 radeon_crtc_handle_flip(rdev, 2); 2838 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 2839 DRM_DEBUG("IH: D3 vblank\n"); 2840 } 2841 break; 2842 case 1: /* D3 vline */ 2843 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { 2844 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 2845 DRM_DEBUG("IH: D3 vline\n"); 2846 } 2847 break; 2848 default: 2849 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2850 break; 2851 } 2852 break; 2853 case 4: /* D4 vblank/vline */ 2854 switch (src_data) { 2855 case 0: /* D4 vblank */ 2856 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { 2857 if (rdev->irq.crtc_vblank_int[3]) { 2858 drm_handle_vblank(rdev->ddev, 3); 2859 rdev->pm.vblank_sync = true; 2860 wake_up(&rdev->irq.vblank_queue); 2861 } 2862 if (rdev->irq.pflip[3]) 2863 radeon_crtc_handle_flip(rdev, 3); 2864 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 2865 DRM_DEBUG("IH: D4 vblank\n"); 2866 } 2867 break; 2868 case 1: /* D4 vline */ 2869 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { 2870 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 2871 DRM_DEBUG("IH: D4 vline\n"); 2872 } 2873 break; 2874 default: 2875 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2876 break; 2877 } 2878 break; 2879 case 5: /* D5 vblank/vline */ 2880 switch (src_data) { 2881 case 0: /* D5 vblank */ 2882 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { 2883 if (rdev->irq.crtc_vblank_int[4]) { 2884 drm_handle_vblank(rdev->ddev, 4); 2885 rdev->pm.vblank_sync = true; 2886 wake_up(&rdev->irq.vblank_queue); 2887 } 2888 if (rdev->irq.pflip[4]) 2889 radeon_crtc_handle_flip(rdev, 4); 2890 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 2891 DRM_DEBUG("IH: D5 vblank\n"); 2892 } 2893 break; 2894 case 1: /* D5 vline */ 2895 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { 2896 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 2897 DRM_DEBUG("IH: D5 vline\n"); 2898 } 2899 break; 2900 default: 2901 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2902 break; 2903 } 2904 break; 2905 case 6: /* D6 vblank/vline */ 2906 switch (src_data) { 2907 case 0: /* D6 vblank */ 2908 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { 2909 if (rdev->irq.crtc_vblank_int[5]) { 2910 drm_handle_vblank(rdev->ddev, 5); 2911 rdev->pm.vblank_sync = true; 2912 wake_up(&rdev->irq.vblank_queue); 2913 } 2914 if (rdev->irq.pflip[5]) 2915 radeon_crtc_handle_flip(rdev, 5); 2916 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 2917 DRM_DEBUG("IH: D6 vblank\n"); 2918 } 2919 break; 2920 case 1: /* D6 vline */ 2921 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { 2922 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 2923 DRM_DEBUG("IH: D6 vline\n"); 2924 } 2925 break; 2926 default: 2927 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2928 break; 2929 } 2930 break; 2931 case 42: /* HPD hotplug */ 2932 switch (src_data) { 2933 case 0: 2934 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 2935 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; 2936 queue_hotplug = true; 2937 DRM_DEBUG("IH: HPD1\n"); 2938 } 2939 break; 2940 case 1: 2941 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 2942 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; 2943 queue_hotplug = true; 2944 DRM_DEBUG("IH: HPD2\n"); 2945 } 2946 break; 2947 case 2: 2948 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 2949 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 2950 queue_hotplug = true; 2951 DRM_DEBUG("IH: HPD3\n"); 2952 } 2953 break; 2954 case 3: 2955 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 2956 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 2957 queue_hotplug = true; 2958 DRM_DEBUG("IH: HPD4\n"); 2959 } 2960 break; 2961 case 4: 2962 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 2963 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 2964 queue_hotplug = true; 2965 DRM_DEBUG("IH: HPD5\n"); 2966 } 2967 break; 2968 case 5: 2969 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 2970 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 2971 queue_hotplug = true; 2972 DRM_DEBUG("IH: HPD6\n"); 2973 } 2974 break; 2975 default: 2976 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2977 break; 2978 } 2979 break; 2980 case 176: /* CP_INT in ring buffer */ 2981 case 177: /* CP_INT in IB1 */ 2982 case 178: /* CP_INT in IB2 */ 2983 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 2984 radeon_fence_process(rdev); 2985 break; 2986 case 181: /* CP EOP event */ 2987 DRM_DEBUG("IH: CP EOP\n"); 2988 radeon_fence_process(rdev); 2989 break; 2990 case 233: /* GUI IDLE */ 2991 DRM_DEBUG("IH: GUI idle\n"); 2992 rdev->pm.gui_idle = true; 2993 wake_up(&rdev->irq.idle_queue); 2994 break; 2995 default: 2996 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2997 break; 2998 } 2999 3000 /* wptr/rptr are in bytes! */ 3001 rptr += 16; 3002 rptr &= rdev->ih.ptr_mask; 3003 } 3004 /* make sure wptr hasn't changed while processing */ 3005 wptr = evergreen_get_ih_wptr(rdev); 3006 if (wptr != rdev->ih.wptr) 3007 goto restart_ih; 3008 if (queue_hotplug) 3009 schedule_work(&rdev->hotplug_work); 3010 rdev->ih.rptr = rptr; 3011 WREG32(IH_RB_RPTR, rdev->ih.rptr); 3012 spin_unlock_irqrestore(&rdev->ih.lock, flags); 3013 return IRQ_HANDLED; 3014 } 3015 3016 static int evergreen_startup(struct radeon_device *rdev) 3017 { 3018 int r; 3019 3020 /* enable pcie gen2 link */ 3021 if (!ASIC_IS_DCE5(rdev)) 3022 evergreen_pcie_gen2_enable(rdev); 3023 3024 if (ASIC_IS_DCE5(rdev)) { 3025 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { 3026 r = ni_init_microcode(rdev); 3027 if (r) { 3028 DRM_ERROR("Failed to load firmware!\n"); 3029 return r; 3030 } 3031 } 3032 r = ni_mc_load_microcode(rdev); 3033 if (r) { 3034 DRM_ERROR("Failed to load MC firmware!\n"); 3035 return r; 3036 } 3037 } else { 3038 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3039 r = r600_init_microcode(rdev); 3040 if (r) { 3041 DRM_ERROR("Failed to load firmware!\n"); 3042 return r; 3043 } 3044 } 3045 } 3046 3047 evergreen_mc_program(rdev); 3048 if (rdev->flags & RADEON_IS_AGP) { 3049 evergreen_agp_enable(rdev); 3050 } else { 3051 r = evergreen_pcie_gart_enable(rdev); 3052 if (r) 3053 return r; 3054 } 3055 evergreen_gpu_init(rdev); 3056 3057 r = evergreen_blit_init(rdev); 3058 if (r) { 3059 evergreen_blit_fini(rdev); 3060 rdev->asic->copy = NULL; 3061 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 3062 } 3063 3064 /* allocate wb buffer */ 3065 r = radeon_wb_init(rdev); 3066 if (r) 3067 return r; 3068 3069 /* Enable IRQ */ 3070 r = r600_irq_init(rdev); 3071 if (r) { 3072 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3073 radeon_irq_kms_fini(rdev); 3074 return r; 3075 } 3076 evergreen_irq_set(rdev); 3077 3078 r = radeon_ring_init(rdev, rdev->cp.ring_size); 3079 if (r) 3080 return r; 3081 r = evergreen_cp_load_microcode(rdev); 3082 if (r) 3083 return r; 3084 r = evergreen_cp_resume(rdev); 3085 if (r) 3086 return r; 3087 3088 return 0; 3089 } 3090 3091 int evergreen_resume(struct radeon_device *rdev) 3092 { 3093 int r; 3094 3095 /* reset the asic, the gfx blocks are often in a bad state 3096 * after the driver is unloaded or after a resume 3097 */ 3098 if (radeon_asic_reset(rdev)) 3099 dev_warn(rdev->dev, "GPU reset failed !\n"); 3100 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 3101 * posting will perform necessary task to bring back GPU into good 3102 * shape. 3103 */ 3104 /* post card */ 3105 atom_asic_init(rdev->mode_info.atom_context); 3106 3107 r = evergreen_startup(rdev); 3108 if (r) { 3109 DRM_ERROR("evergreen startup failed on resume\n"); 3110 return r; 3111 } 3112 3113 r = r600_ib_test(rdev); 3114 if (r) { 3115 DRM_ERROR("radeon: failed testing IB (%d).\n", r); 3116 return r; 3117 } 3118 3119 return r; 3120 3121 } 3122 3123 int evergreen_suspend(struct radeon_device *rdev) 3124 { 3125 int r; 3126 3127 /* FIXME: we should wait for ring to be empty */ 3128 r700_cp_stop(rdev); 3129 rdev->cp.ready = false; 3130 evergreen_irq_suspend(rdev); 3131 radeon_wb_disable(rdev); 3132 evergreen_pcie_gart_disable(rdev); 3133 3134 /* unpin shaders bo */ 3135 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 3136 if (likely(r == 0)) { 3137 radeon_bo_unpin(rdev->r600_blit.shader_obj); 3138 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 3139 } 3140 3141 return 0; 3142 } 3143 3144 int evergreen_copy_blit(struct radeon_device *rdev, 3145 uint64_t src_offset, uint64_t dst_offset, 3146 unsigned num_pages, struct radeon_fence *fence) 3147 { 3148 int r; 3149 3150 mutex_lock(&rdev->r600_blit.mutex); 3151 rdev->r600_blit.vb_ib = NULL; 3152 r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); 3153 if (r) { 3154 if (rdev->r600_blit.vb_ib) 3155 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); 3156 mutex_unlock(&rdev->r600_blit.mutex); 3157 return r; 3158 } 3159 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); 3160 evergreen_blit_done_copy(rdev, fence); 3161 mutex_unlock(&rdev->r600_blit.mutex); 3162 return 0; 3163 } 3164 3165 /* Plan is to move initialization in that function and use 3166 * helper function so that radeon_device_init pretty much 3167 * do nothing more than calling asic specific function. This 3168 * should also allow to remove a bunch of callback function 3169 * like vram_info. 3170 */ 3171 int evergreen_init(struct radeon_device *rdev) 3172 { 3173 int r; 3174 3175 /* This don't do much */ 3176 r = radeon_gem_init(rdev); 3177 if (r) 3178 return r; 3179 /* Read BIOS */ 3180 if (!radeon_get_bios(rdev)) { 3181 if (ASIC_IS_AVIVO(rdev)) 3182 return -EINVAL; 3183 } 3184 /* Must be an ATOMBIOS */ 3185 if (!rdev->is_atom_bios) { 3186 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n"); 3187 return -EINVAL; 3188 } 3189 r = radeon_atombios_init(rdev); 3190 if (r) 3191 return r; 3192 /* reset the asic, the gfx blocks are often in a bad state 3193 * after the driver is unloaded or after a resume 3194 */ 3195 if (radeon_asic_reset(rdev)) 3196 dev_warn(rdev->dev, "GPU reset failed !\n"); 3197 /* Post card if necessary */ 3198 if (!radeon_card_posted(rdev)) { 3199 if (!rdev->bios) { 3200 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3201 return -EINVAL; 3202 } 3203 DRM_INFO("GPU not posted. posting now...\n"); 3204 atom_asic_init(rdev->mode_info.atom_context); 3205 } 3206 /* Initialize scratch registers */ 3207 r600_scratch_init(rdev); 3208 /* Initialize surface registers */ 3209 radeon_surface_init(rdev); 3210 /* Initialize clocks */ 3211 radeon_get_clock_info(rdev->ddev); 3212 /* Fence driver */ 3213 r = radeon_fence_driver_init(rdev); 3214 if (r) 3215 return r; 3216 /* initialize AGP */ 3217 if (rdev->flags & RADEON_IS_AGP) { 3218 r = radeon_agp_init(rdev); 3219 if (r) 3220 radeon_agp_disable(rdev); 3221 } 3222 /* initialize memory controller */ 3223 r = evergreen_mc_init(rdev); 3224 if (r) 3225 return r; 3226 /* Memory manager */ 3227 r = radeon_bo_init(rdev); 3228 if (r) 3229 return r; 3230 3231 r = radeon_irq_kms_init(rdev); 3232 if (r) 3233 return r; 3234 3235 rdev->cp.ring_obj = NULL; 3236 r600_ring_init(rdev, 1024 * 1024); 3237 3238 rdev->ih.ring_obj = NULL; 3239 r600_ih_ring_init(rdev, 64 * 1024); 3240 3241 r = r600_pcie_gart_init(rdev); 3242 if (r) 3243 return r; 3244 3245 rdev->accel_working = true; 3246 r = evergreen_startup(rdev); 3247 if (r) { 3248 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3249 r700_cp_fini(rdev); 3250 r600_irq_fini(rdev); 3251 radeon_wb_fini(rdev); 3252 radeon_irq_kms_fini(rdev); 3253 evergreen_pcie_gart_fini(rdev); 3254 rdev->accel_working = false; 3255 } 3256 if (rdev->accel_working) { 3257 r = radeon_ib_pool_init(rdev); 3258 if (r) { 3259 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); 3260 rdev->accel_working = false; 3261 } 3262 r = r600_ib_test(rdev); 3263 if (r) { 3264 DRM_ERROR("radeon: failed testing IB (%d).\n", r); 3265 rdev->accel_working = false; 3266 } 3267 } 3268 return 0; 3269 } 3270 3271 void evergreen_fini(struct radeon_device *rdev) 3272 { 3273 evergreen_blit_fini(rdev); 3274 r700_cp_fini(rdev); 3275 r600_irq_fini(rdev); 3276 radeon_wb_fini(rdev); 3277 radeon_ib_pool_fini(rdev); 3278 radeon_irq_kms_fini(rdev); 3279 evergreen_pcie_gart_fini(rdev); 3280 radeon_gem_fini(rdev); 3281 radeon_fence_driver_fini(rdev); 3282 radeon_agp_fini(rdev); 3283 radeon_bo_fini(rdev); 3284 radeon_atombios_fini(rdev); 3285 kfree(rdev->bios); 3286 rdev->bios = NULL; 3287 } 3288 3289 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev) 3290 { 3291 u32 link_width_cntl, speed_cntl; 3292 3293 if (radeon_pcie_gen2 == 0) 3294 return; 3295 3296 if (rdev->flags & RADEON_IS_IGP) 3297 return; 3298 3299 if (!(rdev->flags & RADEON_IS_PCIE)) 3300 return; 3301 3302 /* x2 cards have a special sequence */ 3303 if (ASIC_IS_X2(rdev)) 3304 return; 3305 3306 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3307 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || 3308 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 3309 3310 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 3311 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 3312 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 3313 3314 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3315 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 3316 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3317 3318 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3319 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; 3320 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3321 3322 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3323 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 3324 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3325 3326 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3327 speed_cntl |= LC_GEN2_EN_STRAP; 3328 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3329 3330 } else { 3331 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 3332 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 3333 if (1) 3334 link_width_cntl |= LC_UPCONFIGURE_DIS; 3335 else 3336 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 3337 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 3338 } 3339 } 3340