1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 #include "drmP.h" 28 #include "radeon.h" 29 #include "radeon_asic.h" 30 #include "radeon_drm.h" 31 #include "evergreend.h" 32 #include "atom.h" 33 #include "avivod.h" 34 #include "evergreen_reg.h" 35 #include "evergreen_blit_shaders.h" 36 37 #define EVERGREEN_PFP_UCODE_SIZE 1120 38 #define EVERGREEN_PM4_UCODE_SIZE 1376 39 40 static void evergreen_gpu_init(struct radeon_device *rdev); 41 void evergreen_fini(struct radeon_device *rdev); 42 void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 43 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 44 int ring, u32 cp_int_cntl); 45 46 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 47 unsigned *bankh, unsigned *mtaspect, 48 unsigned *tile_split) 49 { 50 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 51 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 52 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 53 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 54 switch (*bankw) { 55 default: 56 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break; 57 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break; 58 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break; 59 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break; 60 } 61 switch (*bankh) { 62 default: 63 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break; 64 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break; 65 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break; 66 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break; 67 } 68 switch (*mtaspect) { 69 default: 70 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break; 71 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break; 72 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break; 73 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break; 74 } 75 } 76 77 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) 78 { 79 u16 ctl, v; 80 int cap, err; 81 82 cap = pci_pcie_cap(rdev->pdev); 83 if (!cap) 84 return; 85 86 err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl); 87 if (err) 88 return; 89 90 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12; 91 92 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it 93 * to avoid hangs or perfomance issues 94 */ 95 if ((v == 0) || (v == 6) || (v == 7)) { 96 ctl &= ~PCI_EXP_DEVCTL_READRQ; 97 ctl |= (2 << 12); 98 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl); 99 } 100 } 101 102 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc) 103 { 104 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc]; 105 int i; 106 107 if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) { 108 for (i = 0; i < rdev->usec_timeout; i++) { 109 if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)) 110 break; 111 udelay(1); 112 } 113 for (i = 0; i < rdev->usec_timeout; i++) { 114 if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK) 115 break; 116 udelay(1); 117 } 118 } 119 } 120 121 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc) 122 { 123 /* enable the pflip int */ 124 radeon_irq_kms_pflip_irq_get(rdev, crtc); 125 } 126 127 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc) 128 { 129 /* disable the pflip int */ 130 radeon_irq_kms_pflip_irq_put(rdev, crtc); 131 } 132 133 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 134 { 135 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 136 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); 137 int i; 138 139 /* Lock the graphics update lock */ 140 tmp |= EVERGREEN_GRPH_UPDATE_LOCK; 141 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 142 143 /* update the scanout addresses */ 144 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 145 upper_32_bits(crtc_base)); 146 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 147 (u32)crtc_base); 148 149 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 150 upper_32_bits(crtc_base)); 151 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 152 (u32)crtc_base); 153 154 /* Wait for update_pending to go high. */ 155 for (i = 0; i < rdev->usec_timeout; i++) { 156 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) 157 break; 158 udelay(1); 159 } 160 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 161 162 /* Unlock the lock, so double-buffering can take place inside vblank */ 163 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; 164 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 165 166 /* Return current update_pending status: */ 167 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING; 168 } 169 170 /* get temperature in millidegrees */ 171 int evergreen_get_temp(struct radeon_device *rdev) 172 { 173 u32 temp, toffset; 174 int actual_temp = 0; 175 176 if (rdev->family == CHIP_JUNIPER) { 177 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> 178 TOFFSET_SHIFT; 179 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >> 180 TS0_ADC_DOUT_SHIFT; 181 182 if (toffset & 0x100) 183 actual_temp = temp / 2 - (0x200 - toffset); 184 else 185 actual_temp = temp / 2 + toffset; 186 187 actual_temp = actual_temp * 1000; 188 189 } else { 190 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> 191 ASIC_T_SHIFT; 192 193 if (temp & 0x400) 194 actual_temp = -256; 195 else if (temp & 0x200) 196 actual_temp = 255; 197 else if (temp & 0x100) { 198 actual_temp = temp & 0x1ff; 199 actual_temp |= ~0x1ff; 200 } else 201 actual_temp = temp & 0xff; 202 203 actual_temp = (actual_temp * 1000) / 2; 204 } 205 206 return actual_temp; 207 } 208 209 int sumo_get_temp(struct radeon_device *rdev) 210 { 211 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff; 212 int actual_temp = temp - 49; 213 214 return actual_temp * 1000; 215 } 216 217 void sumo_pm_init_profile(struct radeon_device *rdev) 218 { 219 int idx; 220 221 /* default */ 222 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 223 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 224 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 225 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 226 227 /* low,mid sh/mh */ 228 if (rdev->flags & RADEON_IS_MOBILITY) 229 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 230 else 231 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 232 233 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 234 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 235 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 236 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 237 238 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 239 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 240 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 241 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 242 243 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 244 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 245 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 246 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 247 248 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 249 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 250 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 251 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 252 253 /* high sh/mh */ 254 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 255 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 256 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 257 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 258 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 259 rdev->pm.power_state[idx].num_clock_modes - 1; 260 261 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 262 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 263 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 264 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 265 rdev->pm.power_state[idx].num_clock_modes - 1; 266 } 267 268 void evergreen_pm_misc(struct radeon_device *rdev) 269 { 270 int req_ps_idx = rdev->pm.requested_power_state_index; 271 int req_cm_idx = rdev->pm.requested_clock_mode_index; 272 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 273 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 274 275 if (voltage->type == VOLTAGE_SW) { 276 /* 0xff01 is a flag rather then an actual voltage */ 277 if (voltage->voltage == 0xff01) 278 return; 279 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { 280 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 281 rdev->pm.current_vddc = voltage->voltage; 282 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage); 283 } 284 /* 0xff01 is a flag rather then an actual voltage */ 285 if (voltage->vddci == 0xff01) 286 return; 287 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { 288 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); 289 rdev->pm.current_vddci = voltage->vddci; 290 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci); 291 } 292 } 293 } 294 295 void evergreen_pm_prepare(struct radeon_device *rdev) 296 { 297 struct drm_device *ddev = rdev->ddev; 298 struct drm_crtc *crtc; 299 struct radeon_crtc *radeon_crtc; 300 u32 tmp; 301 302 /* disable any active CRTCs */ 303 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 304 radeon_crtc = to_radeon_crtc(crtc); 305 if (radeon_crtc->enabled) { 306 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); 307 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; 308 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 309 } 310 } 311 } 312 313 void evergreen_pm_finish(struct radeon_device *rdev) 314 { 315 struct drm_device *ddev = rdev->ddev; 316 struct drm_crtc *crtc; 317 struct radeon_crtc *radeon_crtc; 318 u32 tmp; 319 320 /* enable any active CRTCs */ 321 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 322 radeon_crtc = to_radeon_crtc(crtc); 323 if (radeon_crtc->enabled) { 324 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); 325 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; 326 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 327 } 328 } 329 } 330 331 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 332 { 333 bool connected = false; 334 335 switch (hpd) { 336 case RADEON_HPD_1: 337 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 338 connected = true; 339 break; 340 case RADEON_HPD_2: 341 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 342 connected = true; 343 break; 344 case RADEON_HPD_3: 345 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 346 connected = true; 347 break; 348 case RADEON_HPD_4: 349 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 350 connected = true; 351 break; 352 case RADEON_HPD_5: 353 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 354 connected = true; 355 break; 356 case RADEON_HPD_6: 357 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 358 connected = true; 359 break; 360 default: 361 break; 362 } 363 364 return connected; 365 } 366 367 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 368 enum radeon_hpd_id hpd) 369 { 370 u32 tmp; 371 bool connected = evergreen_hpd_sense(rdev, hpd); 372 373 switch (hpd) { 374 case RADEON_HPD_1: 375 tmp = RREG32(DC_HPD1_INT_CONTROL); 376 if (connected) 377 tmp &= ~DC_HPDx_INT_POLARITY; 378 else 379 tmp |= DC_HPDx_INT_POLARITY; 380 WREG32(DC_HPD1_INT_CONTROL, tmp); 381 break; 382 case RADEON_HPD_2: 383 tmp = RREG32(DC_HPD2_INT_CONTROL); 384 if (connected) 385 tmp &= ~DC_HPDx_INT_POLARITY; 386 else 387 tmp |= DC_HPDx_INT_POLARITY; 388 WREG32(DC_HPD2_INT_CONTROL, tmp); 389 break; 390 case RADEON_HPD_3: 391 tmp = RREG32(DC_HPD3_INT_CONTROL); 392 if (connected) 393 tmp &= ~DC_HPDx_INT_POLARITY; 394 else 395 tmp |= DC_HPDx_INT_POLARITY; 396 WREG32(DC_HPD3_INT_CONTROL, tmp); 397 break; 398 case RADEON_HPD_4: 399 tmp = RREG32(DC_HPD4_INT_CONTROL); 400 if (connected) 401 tmp &= ~DC_HPDx_INT_POLARITY; 402 else 403 tmp |= DC_HPDx_INT_POLARITY; 404 WREG32(DC_HPD4_INT_CONTROL, tmp); 405 break; 406 case RADEON_HPD_5: 407 tmp = RREG32(DC_HPD5_INT_CONTROL); 408 if (connected) 409 tmp &= ~DC_HPDx_INT_POLARITY; 410 else 411 tmp |= DC_HPDx_INT_POLARITY; 412 WREG32(DC_HPD5_INT_CONTROL, tmp); 413 break; 414 case RADEON_HPD_6: 415 tmp = RREG32(DC_HPD6_INT_CONTROL); 416 if (connected) 417 tmp &= ~DC_HPDx_INT_POLARITY; 418 else 419 tmp |= DC_HPDx_INT_POLARITY; 420 WREG32(DC_HPD6_INT_CONTROL, tmp); 421 break; 422 default: 423 break; 424 } 425 } 426 427 void evergreen_hpd_init(struct radeon_device *rdev) 428 { 429 struct drm_device *dev = rdev->ddev; 430 struct drm_connector *connector; 431 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | 432 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN; 433 434 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 435 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 436 switch (radeon_connector->hpd.hpd) { 437 case RADEON_HPD_1: 438 WREG32(DC_HPD1_CONTROL, tmp); 439 rdev->irq.hpd[0] = true; 440 break; 441 case RADEON_HPD_2: 442 WREG32(DC_HPD2_CONTROL, tmp); 443 rdev->irq.hpd[1] = true; 444 break; 445 case RADEON_HPD_3: 446 WREG32(DC_HPD3_CONTROL, tmp); 447 rdev->irq.hpd[2] = true; 448 break; 449 case RADEON_HPD_4: 450 WREG32(DC_HPD4_CONTROL, tmp); 451 rdev->irq.hpd[3] = true; 452 break; 453 case RADEON_HPD_5: 454 WREG32(DC_HPD5_CONTROL, tmp); 455 rdev->irq.hpd[4] = true; 456 break; 457 case RADEON_HPD_6: 458 WREG32(DC_HPD6_CONTROL, tmp); 459 rdev->irq.hpd[5] = true; 460 break; 461 default: 462 break; 463 } 464 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 465 } 466 if (rdev->irq.installed) 467 evergreen_irq_set(rdev); 468 } 469 470 void evergreen_hpd_fini(struct radeon_device *rdev) 471 { 472 struct drm_device *dev = rdev->ddev; 473 struct drm_connector *connector; 474 475 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 476 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 477 switch (radeon_connector->hpd.hpd) { 478 case RADEON_HPD_1: 479 WREG32(DC_HPD1_CONTROL, 0); 480 rdev->irq.hpd[0] = false; 481 break; 482 case RADEON_HPD_2: 483 WREG32(DC_HPD2_CONTROL, 0); 484 rdev->irq.hpd[1] = false; 485 break; 486 case RADEON_HPD_3: 487 WREG32(DC_HPD3_CONTROL, 0); 488 rdev->irq.hpd[2] = false; 489 break; 490 case RADEON_HPD_4: 491 WREG32(DC_HPD4_CONTROL, 0); 492 rdev->irq.hpd[3] = false; 493 break; 494 case RADEON_HPD_5: 495 WREG32(DC_HPD5_CONTROL, 0); 496 rdev->irq.hpd[4] = false; 497 break; 498 case RADEON_HPD_6: 499 WREG32(DC_HPD6_CONTROL, 0); 500 rdev->irq.hpd[5] = false; 501 break; 502 default: 503 break; 504 } 505 } 506 } 507 508 /* watermark setup */ 509 510 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, 511 struct radeon_crtc *radeon_crtc, 512 struct drm_display_mode *mode, 513 struct drm_display_mode *other_mode) 514 { 515 u32 tmp; 516 /* 517 * Line Buffer Setup 518 * There are 3 line buffers, each one shared by 2 display controllers. 519 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 520 * the display controllers. The paritioning is done via one of four 521 * preset allocations specified in bits 2:0: 522 * first display controller 523 * 0 - first half of lb (3840 * 2) 524 * 1 - first 3/4 of lb (5760 * 2) 525 * 2 - whole lb (7680 * 2), other crtc must be disabled 526 * 3 - first 1/4 of lb (1920 * 2) 527 * second display controller 528 * 4 - second half of lb (3840 * 2) 529 * 5 - second 3/4 of lb (5760 * 2) 530 * 6 - whole lb (7680 * 2), other crtc must be disabled 531 * 7 - last 1/4 of lb (1920 * 2) 532 */ 533 /* this can get tricky if we have two large displays on a paired group 534 * of crtcs. Ideally for multiple large displays we'd assign them to 535 * non-linked crtcs for maximum line buffer allocation. 536 */ 537 if (radeon_crtc->base.enabled && mode) { 538 if (other_mode) 539 tmp = 0; /* 1/2 */ 540 else 541 tmp = 2; /* whole */ 542 } else 543 tmp = 0; 544 545 /* second controller of the pair uses second half of the lb */ 546 if (radeon_crtc->crtc_id % 2) 547 tmp += 4; 548 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); 549 550 if (radeon_crtc->base.enabled && mode) { 551 switch (tmp) { 552 case 0: 553 case 4: 554 default: 555 if (ASIC_IS_DCE5(rdev)) 556 return 4096 * 2; 557 else 558 return 3840 * 2; 559 case 1: 560 case 5: 561 if (ASIC_IS_DCE5(rdev)) 562 return 6144 * 2; 563 else 564 return 5760 * 2; 565 case 2: 566 case 6: 567 if (ASIC_IS_DCE5(rdev)) 568 return 8192 * 2; 569 else 570 return 7680 * 2; 571 case 3: 572 case 7: 573 if (ASIC_IS_DCE5(rdev)) 574 return 2048 * 2; 575 else 576 return 1920 * 2; 577 } 578 } 579 580 /* controller not enabled, so no lb used */ 581 return 0; 582 } 583 584 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev) 585 { 586 u32 tmp = RREG32(MC_SHARED_CHMAP); 587 588 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 589 case 0: 590 default: 591 return 1; 592 case 1: 593 return 2; 594 case 2: 595 return 4; 596 case 3: 597 return 8; 598 } 599 } 600 601 struct evergreen_wm_params { 602 u32 dram_channels; /* number of dram channels */ 603 u32 yclk; /* bandwidth per dram data pin in kHz */ 604 u32 sclk; /* engine clock in kHz */ 605 u32 disp_clk; /* display clock in kHz */ 606 u32 src_width; /* viewport width */ 607 u32 active_time; /* active display time in ns */ 608 u32 blank_time; /* blank time in ns */ 609 bool interlaced; /* mode is interlaced */ 610 fixed20_12 vsc; /* vertical scale ratio */ 611 u32 num_heads; /* number of active crtcs */ 612 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 613 u32 lb_size; /* line buffer allocated to pipe */ 614 u32 vtaps; /* vertical scaler taps */ 615 }; 616 617 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm) 618 { 619 /* Calculate DRAM Bandwidth and the part allocated to display. */ 620 fixed20_12 dram_efficiency; /* 0.7 */ 621 fixed20_12 yclk, dram_channels, bandwidth; 622 fixed20_12 a; 623 624 a.full = dfixed_const(1000); 625 yclk.full = dfixed_const(wm->yclk); 626 yclk.full = dfixed_div(yclk, a); 627 dram_channels.full = dfixed_const(wm->dram_channels * 4); 628 a.full = dfixed_const(10); 629 dram_efficiency.full = dfixed_const(7); 630 dram_efficiency.full = dfixed_div(dram_efficiency, a); 631 bandwidth.full = dfixed_mul(dram_channels, yclk); 632 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 633 634 return dfixed_trunc(bandwidth); 635 } 636 637 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm) 638 { 639 /* Calculate DRAM Bandwidth and the part allocated to display. */ 640 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 641 fixed20_12 yclk, dram_channels, bandwidth; 642 fixed20_12 a; 643 644 a.full = dfixed_const(1000); 645 yclk.full = dfixed_const(wm->yclk); 646 yclk.full = dfixed_div(yclk, a); 647 dram_channels.full = dfixed_const(wm->dram_channels * 4); 648 a.full = dfixed_const(10); 649 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 650 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 651 bandwidth.full = dfixed_mul(dram_channels, yclk); 652 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 653 654 return dfixed_trunc(bandwidth); 655 } 656 657 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm) 658 { 659 /* Calculate the display Data return Bandwidth */ 660 fixed20_12 return_efficiency; /* 0.8 */ 661 fixed20_12 sclk, bandwidth; 662 fixed20_12 a; 663 664 a.full = dfixed_const(1000); 665 sclk.full = dfixed_const(wm->sclk); 666 sclk.full = dfixed_div(sclk, a); 667 a.full = dfixed_const(10); 668 return_efficiency.full = dfixed_const(8); 669 return_efficiency.full = dfixed_div(return_efficiency, a); 670 a.full = dfixed_const(32); 671 bandwidth.full = dfixed_mul(a, sclk); 672 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 673 674 return dfixed_trunc(bandwidth); 675 } 676 677 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm) 678 { 679 /* Calculate the DMIF Request Bandwidth */ 680 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 681 fixed20_12 disp_clk, bandwidth; 682 fixed20_12 a; 683 684 a.full = dfixed_const(1000); 685 disp_clk.full = dfixed_const(wm->disp_clk); 686 disp_clk.full = dfixed_div(disp_clk, a); 687 a.full = dfixed_const(10); 688 disp_clk_request_efficiency.full = dfixed_const(8); 689 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 690 a.full = dfixed_const(32); 691 bandwidth.full = dfixed_mul(a, disp_clk); 692 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency); 693 694 return dfixed_trunc(bandwidth); 695 } 696 697 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm) 698 { 699 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 700 u32 dram_bandwidth = evergreen_dram_bandwidth(wm); 701 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm); 702 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm); 703 704 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 705 } 706 707 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm) 708 { 709 /* Calculate the display mode Average Bandwidth 710 * DisplayMode should contain the source and destination dimensions, 711 * timing, etc. 712 */ 713 fixed20_12 bpp; 714 fixed20_12 line_time; 715 fixed20_12 src_width; 716 fixed20_12 bandwidth; 717 fixed20_12 a; 718 719 a.full = dfixed_const(1000); 720 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 721 line_time.full = dfixed_div(line_time, a); 722 bpp.full = dfixed_const(wm->bytes_per_pixel); 723 src_width.full = dfixed_const(wm->src_width); 724 bandwidth.full = dfixed_mul(src_width, bpp); 725 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 726 bandwidth.full = dfixed_div(bandwidth, line_time); 727 728 return dfixed_trunc(bandwidth); 729 } 730 731 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm) 732 { 733 /* First calcualte the latency in ns */ 734 u32 mc_latency = 2000; /* 2000 ns. */ 735 u32 available_bandwidth = evergreen_available_bandwidth(wm); 736 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 737 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 738 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 739 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 740 (wm->num_heads * cursor_line_pair_return_time); 741 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 742 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 743 fixed20_12 a, b, c; 744 745 if (wm->num_heads == 0) 746 return 0; 747 748 a.full = dfixed_const(2); 749 b.full = dfixed_const(1); 750 if ((wm->vsc.full > a.full) || 751 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 752 (wm->vtaps >= 5) || 753 ((wm->vsc.full >= a.full) && wm->interlaced)) 754 max_src_lines_per_dst_line = 4; 755 else 756 max_src_lines_per_dst_line = 2; 757 758 a.full = dfixed_const(available_bandwidth); 759 b.full = dfixed_const(wm->num_heads); 760 a.full = dfixed_div(a, b); 761 762 b.full = dfixed_const(1000); 763 c.full = dfixed_const(wm->disp_clk); 764 b.full = dfixed_div(c, b); 765 c.full = dfixed_const(wm->bytes_per_pixel); 766 b.full = dfixed_mul(b, c); 767 768 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b)); 769 770 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 771 b.full = dfixed_const(1000); 772 c.full = dfixed_const(lb_fill_bw); 773 b.full = dfixed_div(c, b); 774 a.full = dfixed_div(a, b); 775 line_fill_time = dfixed_trunc(a); 776 777 if (line_fill_time < wm->active_time) 778 return latency; 779 else 780 return latency + (line_fill_time - wm->active_time); 781 782 } 783 784 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm) 785 { 786 if (evergreen_average_bandwidth(wm) <= 787 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads)) 788 return true; 789 else 790 return false; 791 }; 792 793 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm) 794 { 795 if (evergreen_average_bandwidth(wm) <= 796 (evergreen_available_bandwidth(wm) / wm->num_heads)) 797 return true; 798 else 799 return false; 800 }; 801 802 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm) 803 { 804 u32 lb_partitions = wm->lb_size / wm->src_width; 805 u32 line_time = wm->active_time + wm->blank_time; 806 u32 latency_tolerant_lines; 807 u32 latency_hiding; 808 fixed20_12 a; 809 810 a.full = dfixed_const(1); 811 if (wm->vsc.full > a.full) 812 latency_tolerant_lines = 1; 813 else { 814 if (lb_partitions <= (wm->vtaps + 1)) 815 latency_tolerant_lines = 1; 816 else 817 latency_tolerant_lines = 2; 818 } 819 820 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 821 822 if (evergreen_latency_watermark(wm) <= latency_hiding) 823 return true; 824 else 825 return false; 826 } 827 828 static void evergreen_program_watermarks(struct radeon_device *rdev, 829 struct radeon_crtc *radeon_crtc, 830 u32 lb_size, u32 num_heads) 831 { 832 struct drm_display_mode *mode = &radeon_crtc->base.mode; 833 struct evergreen_wm_params wm; 834 u32 pixel_period; 835 u32 line_time = 0; 836 u32 latency_watermark_a = 0, latency_watermark_b = 0; 837 u32 priority_a_mark = 0, priority_b_mark = 0; 838 u32 priority_a_cnt = PRIORITY_OFF; 839 u32 priority_b_cnt = PRIORITY_OFF; 840 u32 pipe_offset = radeon_crtc->crtc_id * 16; 841 u32 tmp, arb_control3; 842 fixed20_12 a, b, c; 843 844 if (radeon_crtc->base.enabled && num_heads && mode) { 845 pixel_period = 1000000 / (u32)mode->clock; 846 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 847 priority_a_cnt = 0; 848 priority_b_cnt = 0; 849 850 wm.yclk = rdev->pm.current_mclk * 10; 851 wm.sclk = rdev->pm.current_sclk * 10; 852 wm.disp_clk = mode->clock; 853 wm.src_width = mode->crtc_hdisplay; 854 wm.active_time = mode->crtc_hdisplay * pixel_period; 855 wm.blank_time = line_time - wm.active_time; 856 wm.interlaced = false; 857 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 858 wm.interlaced = true; 859 wm.vsc = radeon_crtc->vsc; 860 wm.vtaps = 1; 861 if (radeon_crtc->rmx_type != RMX_OFF) 862 wm.vtaps = 2; 863 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */ 864 wm.lb_size = lb_size; 865 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev); 866 wm.num_heads = num_heads; 867 868 /* set for high clocks */ 869 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535); 870 /* set for low clocks */ 871 /* wm.yclk = low clk; wm.sclk = low clk */ 872 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535); 873 874 /* possibly force display priority to high */ 875 /* should really do this at mode validation time... */ 876 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) || 877 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) || 878 !evergreen_check_latency_hiding(&wm) || 879 (rdev->disp_priority == 2)) { 880 DRM_DEBUG_KMS("force priority to high\n"); 881 priority_a_cnt |= PRIORITY_ALWAYS_ON; 882 priority_b_cnt |= PRIORITY_ALWAYS_ON; 883 } 884 885 a.full = dfixed_const(1000); 886 b.full = dfixed_const(mode->clock); 887 b.full = dfixed_div(b, a); 888 c.full = dfixed_const(latency_watermark_a); 889 c.full = dfixed_mul(c, b); 890 c.full = dfixed_mul(c, radeon_crtc->hsc); 891 c.full = dfixed_div(c, a); 892 a.full = dfixed_const(16); 893 c.full = dfixed_div(c, a); 894 priority_a_mark = dfixed_trunc(c); 895 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 896 897 a.full = dfixed_const(1000); 898 b.full = dfixed_const(mode->clock); 899 b.full = dfixed_div(b, a); 900 c.full = dfixed_const(latency_watermark_b); 901 c.full = dfixed_mul(c, b); 902 c.full = dfixed_mul(c, radeon_crtc->hsc); 903 c.full = dfixed_div(c, a); 904 a.full = dfixed_const(16); 905 c.full = dfixed_div(c, a); 906 priority_b_mark = dfixed_trunc(c); 907 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 908 } 909 910 /* select wm A */ 911 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); 912 tmp = arb_control3; 913 tmp &= ~LATENCY_WATERMARK_MASK(3); 914 tmp |= LATENCY_WATERMARK_MASK(1); 915 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); 916 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, 917 (LATENCY_LOW_WATERMARK(latency_watermark_a) | 918 LATENCY_HIGH_WATERMARK(line_time))); 919 /* select wm B */ 920 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); 921 tmp &= ~LATENCY_WATERMARK_MASK(3); 922 tmp |= LATENCY_WATERMARK_MASK(2); 923 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); 924 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, 925 (LATENCY_LOW_WATERMARK(latency_watermark_b) | 926 LATENCY_HIGH_WATERMARK(line_time))); 927 /* restore original selection */ 928 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3); 929 930 /* write the priority marks */ 931 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); 932 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); 933 934 } 935 936 void evergreen_bandwidth_update(struct radeon_device *rdev) 937 { 938 struct drm_display_mode *mode0 = NULL; 939 struct drm_display_mode *mode1 = NULL; 940 u32 num_heads = 0, lb_size; 941 int i; 942 943 radeon_update_display_priority(rdev); 944 945 for (i = 0; i < rdev->num_crtc; i++) { 946 if (rdev->mode_info.crtcs[i]->base.enabled) 947 num_heads++; 948 } 949 for (i = 0; i < rdev->num_crtc; i += 2) { 950 mode0 = &rdev->mode_info.crtcs[i]->base.mode; 951 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; 952 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); 953 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); 954 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); 955 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); 956 } 957 } 958 959 int evergreen_mc_wait_for_idle(struct radeon_device *rdev) 960 { 961 unsigned i; 962 u32 tmp; 963 964 for (i = 0; i < rdev->usec_timeout; i++) { 965 /* read MC_STATUS */ 966 tmp = RREG32(SRBM_STATUS) & 0x1F00; 967 if (!tmp) 968 return 0; 969 udelay(1); 970 } 971 return -1; 972 } 973 974 /* 975 * GART 976 */ 977 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev) 978 { 979 unsigned i; 980 u32 tmp; 981 982 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 983 984 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 985 for (i = 0; i < rdev->usec_timeout; i++) { 986 /* read MC_STATUS */ 987 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 988 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 989 if (tmp == 2) { 990 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 991 return; 992 } 993 if (tmp) { 994 return; 995 } 996 udelay(1); 997 } 998 } 999 1000 int evergreen_pcie_gart_enable(struct radeon_device *rdev) 1001 { 1002 u32 tmp; 1003 int r; 1004 1005 if (rdev->gart.robj == NULL) { 1006 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1007 return -EINVAL; 1008 } 1009 r = radeon_gart_table_vram_pin(rdev); 1010 if (r) 1011 return r; 1012 radeon_gart_restore(rdev); 1013 /* Setup L2 cache */ 1014 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1015 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1016 EFFECTIVE_L2_QUEUE_SIZE(7)); 1017 WREG32(VM_L2_CNTL2, 0); 1018 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 1019 /* Setup TLB control */ 1020 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1021 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1022 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 1023 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 1024 if (rdev->flags & RADEON_IS_IGP) { 1025 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp); 1026 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp); 1027 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp); 1028 } else { 1029 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 1030 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 1031 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 1032 if ((rdev->family == CHIP_JUNIPER) || 1033 (rdev->family == CHIP_CYPRESS) || 1034 (rdev->family == CHIP_HEMLOCK) || 1035 (rdev->family == CHIP_BARTS)) 1036 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); 1037 } 1038 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 1039 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 1040 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 1041 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 1042 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1043 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1044 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1045 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1046 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1047 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1048 (u32)(rdev->dummy_page.addr >> 12)); 1049 WREG32(VM_CONTEXT1_CNTL, 0); 1050 1051 evergreen_pcie_gart_tlb_flush(rdev); 1052 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1053 (unsigned)(rdev->mc.gtt_size >> 20), 1054 (unsigned long long)rdev->gart.table_addr); 1055 rdev->gart.ready = true; 1056 return 0; 1057 } 1058 1059 void evergreen_pcie_gart_disable(struct radeon_device *rdev) 1060 { 1061 u32 tmp; 1062 1063 /* Disable all tables */ 1064 WREG32(VM_CONTEXT0_CNTL, 0); 1065 WREG32(VM_CONTEXT1_CNTL, 0); 1066 1067 /* Setup L2 cache */ 1068 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 1069 EFFECTIVE_L2_QUEUE_SIZE(7)); 1070 WREG32(VM_L2_CNTL2, 0); 1071 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 1072 /* Setup TLB control */ 1073 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 1074 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 1075 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 1076 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 1077 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 1078 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 1079 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 1080 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 1081 radeon_gart_table_vram_unpin(rdev); 1082 } 1083 1084 void evergreen_pcie_gart_fini(struct radeon_device *rdev) 1085 { 1086 evergreen_pcie_gart_disable(rdev); 1087 radeon_gart_table_vram_free(rdev); 1088 radeon_gart_fini(rdev); 1089 } 1090 1091 1092 void evergreen_agp_enable(struct radeon_device *rdev) 1093 { 1094 u32 tmp; 1095 1096 /* Setup L2 cache */ 1097 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1098 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1099 EFFECTIVE_L2_QUEUE_SIZE(7)); 1100 WREG32(VM_L2_CNTL2, 0); 1101 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 1102 /* Setup TLB control */ 1103 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1104 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1105 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 1106 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 1107 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 1108 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 1109 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 1110 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 1111 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 1112 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 1113 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 1114 WREG32(VM_CONTEXT0_CNTL, 0); 1115 WREG32(VM_CONTEXT1_CNTL, 0); 1116 } 1117 1118 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) 1119 { 1120 save->vga_control[0] = RREG32(D1VGA_CONTROL); 1121 save->vga_control[1] = RREG32(D2VGA_CONTROL); 1122 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 1123 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 1124 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 1125 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 1126 if (rdev->num_crtc >= 4) { 1127 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL); 1128 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL); 1129 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 1130 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 1131 } 1132 if (rdev->num_crtc >= 6) { 1133 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL); 1134 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL); 1135 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 1136 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 1137 } 1138 1139 /* Stop all video */ 1140 WREG32(VGA_RENDER_CONTROL, 0); 1141 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1142 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1143 if (rdev->num_crtc >= 4) { 1144 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1145 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1146 } 1147 if (rdev->num_crtc >= 6) { 1148 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1149 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1150 } 1151 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1152 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1153 if (rdev->num_crtc >= 4) { 1154 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1155 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1156 } 1157 if (rdev->num_crtc >= 6) { 1158 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1159 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1160 } 1161 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1162 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1163 if (rdev->num_crtc >= 4) { 1164 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1165 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1166 } 1167 if (rdev->num_crtc >= 6) { 1168 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1169 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1170 } 1171 1172 WREG32(D1VGA_CONTROL, 0); 1173 WREG32(D2VGA_CONTROL, 0); 1174 if (rdev->num_crtc >= 4) { 1175 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1176 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1177 } 1178 if (rdev->num_crtc >= 6) { 1179 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1180 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1181 } 1182 } 1183 1184 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) 1185 { 1186 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, 1187 upper_32_bits(rdev->mc.vram_start)); 1188 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, 1189 upper_32_bits(rdev->mc.vram_start)); 1190 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, 1191 (u32)rdev->mc.vram_start); 1192 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, 1193 (u32)rdev->mc.vram_start); 1194 1195 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, 1196 upper_32_bits(rdev->mc.vram_start)); 1197 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, 1198 upper_32_bits(rdev->mc.vram_start)); 1199 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, 1200 (u32)rdev->mc.vram_start); 1201 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, 1202 (u32)rdev->mc.vram_start); 1203 1204 if (rdev->num_crtc >= 4) { 1205 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1206 upper_32_bits(rdev->mc.vram_start)); 1207 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1208 upper_32_bits(rdev->mc.vram_start)); 1209 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, 1210 (u32)rdev->mc.vram_start); 1211 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, 1212 (u32)rdev->mc.vram_start); 1213 1214 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, 1215 upper_32_bits(rdev->mc.vram_start)); 1216 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, 1217 upper_32_bits(rdev->mc.vram_start)); 1218 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1219 (u32)rdev->mc.vram_start); 1220 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1221 (u32)rdev->mc.vram_start); 1222 } 1223 if (rdev->num_crtc >= 6) { 1224 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1225 upper_32_bits(rdev->mc.vram_start)); 1226 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1227 upper_32_bits(rdev->mc.vram_start)); 1228 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, 1229 (u32)rdev->mc.vram_start); 1230 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, 1231 (u32)rdev->mc.vram_start); 1232 1233 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, 1234 upper_32_bits(rdev->mc.vram_start)); 1235 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, 1236 upper_32_bits(rdev->mc.vram_start)); 1237 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, 1238 (u32)rdev->mc.vram_start); 1239 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, 1240 (u32)rdev->mc.vram_start); 1241 } 1242 1243 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); 1244 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 1245 /* Unlock host access */ 1246 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); 1247 mdelay(1); 1248 /* Restore video state */ 1249 WREG32(D1VGA_CONTROL, save->vga_control[0]); 1250 WREG32(D2VGA_CONTROL, save->vga_control[1]); 1251 if (rdev->num_crtc >= 4) { 1252 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); 1253 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); 1254 } 1255 if (rdev->num_crtc >= 6) { 1256 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); 1257 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); 1258 } 1259 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1260 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1261 if (rdev->num_crtc >= 4) { 1262 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1263 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1264 } 1265 if (rdev->num_crtc >= 6) { 1266 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1267 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1268 } 1269 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); 1270 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); 1271 if (rdev->num_crtc >= 4) { 1272 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); 1273 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); 1274 } 1275 if (rdev->num_crtc >= 6) { 1276 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); 1277 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); 1278 } 1279 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1280 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1281 if (rdev->num_crtc >= 4) { 1282 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1283 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1284 } 1285 if (rdev->num_crtc >= 6) { 1286 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1287 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1288 } 1289 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); 1290 } 1291 1292 void evergreen_mc_program(struct radeon_device *rdev) 1293 { 1294 struct evergreen_mc_save save; 1295 u32 tmp; 1296 int i, j; 1297 1298 /* Initialize HDP */ 1299 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1300 WREG32((0x2c14 + j), 0x00000000); 1301 WREG32((0x2c18 + j), 0x00000000); 1302 WREG32((0x2c1c + j), 0x00000000); 1303 WREG32((0x2c20 + j), 0x00000000); 1304 WREG32((0x2c24 + j), 0x00000000); 1305 } 1306 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1307 1308 evergreen_mc_stop(rdev, &save); 1309 if (evergreen_mc_wait_for_idle(rdev)) { 1310 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1311 } 1312 /* Lockout access through VGA aperture*/ 1313 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1314 /* Update configuration */ 1315 if (rdev->flags & RADEON_IS_AGP) { 1316 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1317 /* VRAM before AGP */ 1318 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1319 rdev->mc.vram_start >> 12); 1320 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1321 rdev->mc.gtt_end >> 12); 1322 } else { 1323 /* VRAM after AGP */ 1324 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1325 rdev->mc.gtt_start >> 12); 1326 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1327 rdev->mc.vram_end >> 12); 1328 } 1329 } else { 1330 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1331 rdev->mc.vram_start >> 12); 1332 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1333 rdev->mc.vram_end >> 12); 1334 } 1335 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1336 /* llano/ontario only */ 1337 if ((rdev->family == CHIP_PALM) || 1338 (rdev->family == CHIP_SUMO) || 1339 (rdev->family == CHIP_SUMO2)) { 1340 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; 1341 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24; 1342 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; 1343 WREG32(MC_FUS_VM_FB_OFFSET, tmp); 1344 } 1345 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1346 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1347 WREG32(MC_VM_FB_LOCATION, tmp); 1348 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1349 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 1350 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1351 if (rdev->flags & RADEON_IS_AGP) { 1352 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 1353 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 1354 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1355 } else { 1356 WREG32(MC_VM_AGP_BASE, 0); 1357 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1358 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1359 } 1360 if (evergreen_mc_wait_for_idle(rdev)) { 1361 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1362 } 1363 evergreen_mc_resume(rdev, &save); 1364 /* we need to own VRAM, so turn off the VGA renderer here 1365 * to stop it overwriting our objects */ 1366 rv515_vga_render_disable(rdev); 1367 } 1368 1369 /* 1370 * CP. 1371 */ 1372 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1373 { 1374 struct radeon_ring *ring = &rdev->ring[ib->fence->ring]; 1375 1376 /* set to DX10/11 mode */ 1377 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); 1378 radeon_ring_write(ring, 1); 1379 /* FIXME: implement */ 1380 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 1381 radeon_ring_write(ring, 1382 #ifdef __BIG_ENDIAN 1383 (2 << 0) | 1384 #endif 1385 (ib->gpu_addr & 0xFFFFFFFC)); 1386 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 1387 radeon_ring_write(ring, ib->length_dw); 1388 } 1389 1390 1391 static int evergreen_cp_load_microcode(struct radeon_device *rdev) 1392 { 1393 const __be32 *fw_data; 1394 int i; 1395 1396 if (!rdev->me_fw || !rdev->pfp_fw) 1397 return -EINVAL; 1398 1399 r700_cp_stop(rdev); 1400 WREG32(CP_RB_CNTL, 1401 #ifdef __BIG_ENDIAN 1402 BUF_SWAP_32BIT | 1403 #endif 1404 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 1405 1406 fw_data = (const __be32 *)rdev->pfp_fw->data; 1407 WREG32(CP_PFP_UCODE_ADDR, 0); 1408 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++) 1409 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1410 WREG32(CP_PFP_UCODE_ADDR, 0); 1411 1412 fw_data = (const __be32 *)rdev->me_fw->data; 1413 WREG32(CP_ME_RAM_WADDR, 0); 1414 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++) 1415 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1416 1417 WREG32(CP_PFP_UCODE_ADDR, 0); 1418 WREG32(CP_ME_RAM_WADDR, 0); 1419 WREG32(CP_ME_RAM_RADDR, 0); 1420 return 0; 1421 } 1422 1423 static int evergreen_cp_start(struct radeon_device *rdev) 1424 { 1425 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1426 int r, i; 1427 uint32_t cp_me; 1428 1429 r = radeon_ring_lock(rdev, ring, 7); 1430 if (r) { 1431 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1432 return r; 1433 } 1434 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1435 radeon_ring_write(ring, 0x1); 1436 radeon_ring_write(ring, 0x0); 1437 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1); 1438 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1439 radeon_ring_write(ring, 0); 1440 radeon_ring_write(ring, 0); 1441 radeon_ring_unlock_commit(rdev, ring); 1442 1443 cp_me = 0xff; 1444 WREG32(CP_ME_CNTL, cp_me); 1445 1446 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19); 1447 if (r) { 1448 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1449 return r; 1450 } 1451 1452 /* setup clear context state */ 1453 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1454 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1455 1456 for (i = 0; i < evergreen_default_size; i++) 1457 radeon_ring_write(ring, evergreen_default_state[i]); 1458 1459 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1460 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 1461 1462 /* set clear context state */ 1463 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 1464 radeon_ring_write(ring, 0); 1465 1466 /* SQ_VTX_BASE_VTX_LOC */ 1467 radeon_ring_write(ring, 0xc0026f00); 1468 radeon_ring_write(ring, 0x00000000); 1469 radeon_ring_write(ring, 0x00000000); 1470 radeon_ring_write(ring, 0x00000000); 1471 1472 /* Clear consts */ 1473 radeon_ring_write(ring, 0xc0036f00); 1474 radeon_ring_write(ring, 0x00000bc4); 1475 radeon_ring_write(ring, 0xffffffff); 1476 radeon_ring_write(ring, 0xffffffff); 1477 radeon_ring_write(ring, 0xffffffff); 1478 1479 radeon_ring_write(ring, 0xc0026900); 1480 radeon_ring_write(ring, 0x00000316); 1481 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 1482 radeon_ring_write(ring, 0x00000010); /* */ 1483 1484 radeon_ring_unlock_commit(rdev, ring); 1485 1486 return 0; 1487 } 1488 1489 int evergreen_cp_resume(struct radeon_device *rdev) 1490 { 1491 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1492 u32 tmp; 1493 u32 rb_bufsz; 1494 int r; 1495 1496 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ 1497 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | 1498 SOFT_RESET_PA | 1499 SOFT_RESET_SH | 1500 SOFT_RESET_VGT | 1501 SOFT_RESET_SPI | 1502 SOFT_RESET_SX)); 1503 RREG32(GRBM_SOFT_RESET); 1504 mdelay(15); 1505 WREG32(GRBM_SOFT_RESET, 0); 1506 RREG32(GRBM_SOFT_RESET); 1507 1508 /* Set ring buffer size */ 1509 rb_bufsz = drm_order(ring->ring_size / 8); 1510 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1511 #ifdef __BIG_ENDIAN 1512 tmp |= BUF_SWAP_32BIT; 1513 #endif 1514 WREG32(CP_RB_CNTL, tmp); 1515 WREG32(CP_SEM_WAIT_TIMER, 0x0); 1516 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 1517 1518 /* Set the write pointer delay */ 1519 WREG32(CP_RB_WPTR_DELAY, 0); 1520 1521 /* Initialize the ring buffer's read and write pointers */ 1522 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 1523 WREG32(CP_RB_RPTR_WR, 0); 1524 ring->wptr = 0; 1525 WREG32(CP_RB_WPTR, ring->wptr); 1526 1527 /* set the wb address wether it's enabled or not */ 1528 WREG32(CP_RB_RPTR_ADDR, 1529 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 1530 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 1531 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 1532 1533 if (rdev->wb.enabled) 1534 WREG32(SCRATCH_UMSK, 0xff); 1535 else { 1536 tmp |= RB_NO_UPDATE; 1537 WREG32(SCRATCH_UMSK, 0); 1538 } 1539 1540 mdelay(1); 1541 WREG32(CP_RB_CNTL, tmp); 1542 1543 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 1544 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 1545 1546 ring->rptr = RREG32(CP_RB_RPTR); 1547 1548 evergreen_cp_start(rdev); 1549 ring->ready = true; 1550 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 1551 if (r) { 1552 ring->ready = false; 1553 return r; 1554 } 1555 return 0; 1556 } 1557 1558 /* 1559 * Core functions 1560 */ 1561 static void evergreen_gpu_init(struct radeon_device *rdev) 1562 { 1563 u32 gb_addr_config; 1564 u32 mc_shared_chmap, mc_arb_ramcfg; 1565 u32 sx_debug_1; 1566 u32 smx_dc_ctl0; 1567 u32 sq_config; 1568 u32 sq_lds_resource_mgmt; 1569 u32 sq_gpr_resource_mgmt_1; 1570 u32 sq_gpr_resource_mgmt_2; 1571 u32 sq_gpr_resource_mgmt_3; 1572 u32 sq_thread_resource_mgmt; 1573 u32 sq_thread_resource_mgmt_2; 1574 u32 sq_stack_resource_mgmt_1; 1575 u32 sq_stack_resource_mgmt_2; 1576 u32 sq_stack_resource_mgmt_3; 1577 u32 vgt_cache_invalidation; 1578 u32 hdp_host_path_cntl, tmp; 1579 u32 disabled_rb_mask; 1580 int i, j, num_shader_engines, ps_thread_count; 1581 1582 switch (rdev->family) { 1583 case CHIP_CYPRESS: 1584 case CHIP_HEMLOCK: 1585 rdev->config.evergreen.num_ses = 2; 1586 rdev->config.evergreen.max_pipes = 4; 1587 rdev->config.evergreen.max_tile_pipes = 8; 1588 rdev->config.evergreen.max_simds = 10; 1589 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; 1590 rdev->config.evergreen.max_gprs = 256; 1591 rdev->config.evergreen.max_threads = 248; 1592 rdev->config.evergreen.max_gs_threads = 32; 1593 rdev->config.evergreen.max_stack_entries = 512; 1594 rdev->config.evergreen.sx_num_of_sets = 4; 1595 rdev->config.evergreen.sx_max_export_size = 256; 1596 rdev->config.evergreen.sx_max_export_pos_size = 64; 1597 rdev->config.evergreen.sx_max_export_smx_size = 192; 1598 rdev->config.evergreen.max_hw_contexts = 8; 1599 rdev->config.evergreen.sq_num_cf_insts = 2; 1600 1601 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1602 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1603 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1604 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN; 1605 break; 1606 case CHIP_JUNIPER: 1607 rdev->config.evergreen.num_ses = 1; 1608 rdev->config.evergreen.max_pipes = 4; 1609 rdev->config.evergreen.max_tile_pipes = 4; 1610 rdev->config.evergreen.max_simds = 10; 1611 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; 1612 rdev->config.evergreen.max_gprs = 256; 1613 rdev->config.evergreen.max_threads = 248; 1614 rdev->config.evergreen.max_gs_threads = 32; 1615 rdev->config.evergreen.max_stack_entries = 512; 1616 rdev->config.evergreen.sx_num_of_sets = 4; 1617 rdev->config.evergreen.sx_max_export_size = 256; 1618 rdev->config.evergreen.sx_max_export_pos_size = 64; 1619 rdev->config.evergreen.sx_max_export_smx_size = 192; 1620 rdev->config.evergreen.max_hw_contexts = 8; 1621 rdev->config.evergreen.sq_num_cf_insts = 2; 1622 1623 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1624 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1625 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1626 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN; 1627 break; 1628 case CHIP_REDWOOD: 1629 rdev->config.evergreen.num_ses = 1; 1630 rdev->config.evergreen.max_pipes = 4; 1631 rdev->config.evergreen.max_tile_pipes = 4; 1632 rdev->config.evergreen.max_simds = 5; 1633 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; 1634 rdev->config.evergreen.max_gprs = 256; 1635 rdev->config.evergreen.max_threads = 248; 1636 rdev->config.evergreen.max_gs_threads = 32; 1637 rdev->config.evergreen.max_stack_entries = 256; 1638 rdev->config.evergreen.sx_num_of_sets = 4; 1639 rdev->config.evergreen.sx_max_export_size = 256; 1640 rdev->config.evergreen.sx_max_export_pos_size = 64; 1641 rdev->config.evergreen.sx_max_export_smx_size = 192; 1642 rdev->config.evergreen.max_hw_contexts = 8; 1643 rdev->config.evergreen.sq_num_cf_insts = 2; 1644 1645 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1646 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1647 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1648 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; 1649 break; 1650 case CHIP_CEDAR: 1651 default: 1652 rdev->config.evergreen.num_ses = 1; 1653 rdev->config.evergreen.max_pipes = 2; 1654 rdev->config.evergreen.max_tile_pipes = 2; 1655 rdev->config.evergreen.max_simds = 2; 1656 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1657 rdev->config.evergreen.max_gprs = 256; 1658 rdev->config.evergreen.max_threads = 192; 1659 rdev->config.evergreen.max_gs_threads = 16; 1660 rdev->config.evergreen.max_stack_entries = 256; 1661 rdev->config.evergreen.sx_num_of_sets = 4; 1662 rdev->config.evergreen.sx_max_export_size = 128; 1663 rdev->config.evergreen.sx_max_export_pos_size = 32; 1664 rdev->config.evergreen.sx_max_export_smx_size = 96; 1665 rdev->config.evergreen.max_hw_contexts = 4; 1666 rdev->config.evergreen.sq_num_cf_insts = 1; 1667 1668 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1669 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1670 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1671 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; 1672 break; 1673 case CHIP_PALM: 1674 rdev->config.evergreen.num_ses = 1; 1675 rdev->config.evergreen.max_pipes = 2; 1676 rdev->config.evergreen.max_tile_pipes = 2; 1677 rdev->config.evergreen.max_simds = 2; 1678 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1679 rdev->config.evergreen.max_gprs = 256; 1680 rdev->config.evergreen.max_threads = 192; 1681 rdev->config.evergreen.max_gs_threads = 16; 1682 rdev->config.evergreen.max_stack_entries = 256; 1683 rdev->config.evergreen.sx_num_of_sets = 4; 1684 rdev->config.evergreen.sx_max_export_size = 128; 1685 rdev->config.evergreen.sx_max_export_pos_size = 32; 1686 rdev->config.evergreen.sx_max_export_smx_size = 96; 1687 rdev->config.evergreen.max_hw_contexts = 4; 1688 rdev->config.evergreen.sq_num_cf_insts = 1; 1689 1690 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1691 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1692 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1693 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; 1694 break; 1695 case CHIP_SUMO: 1696 rdev->config.evergreen.num_ses = 1; 1697 rdev->config.evergreen.max_pipes = 4; 1698 rdev->config.evergreen.max_tile_pipes = 2; 1699 if (rdev->pdev->device == 0x9648) 1700 rdev->config.evergreen.max_simds = 3; 1701 else if ((rdev->pdev->device == 0x9647) || 1702 (rdev->pdev->device == 0x964a)) 1703 rdev->config.evergreen.max_simds = 4; 1704 else 1705 rdev->config.evergreen.max_simds = 5; 1706 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; 1707 rdev->config.evergreen.max_gprs = 256; 1708 rdev->config.evergreen.max_threads = 248; 1709 rdev->config.evergreen.max_gs_threads = 32; 1710 rdev->config.evergreen.max_stack_entries = 256; 1711 rdev->config.evergreen.sx_num_of_sets = 4; 1712 rdev->config.evergreen.sx_max_export_size = 256; 1713 rdev->config.evergreen.sx_max_export_pos_size = 64; 1714 rdev->config.evergreen.sx_max_export_smx_size = 192; 1715 rdev->config.evergreen.max_hw_contexts = 8; 1716 rdev->config.evergreen.sq_num_cf_insts = 2; 1717 1718 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1719 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1720 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1721 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; 1722 break; 1723 case CHIP_SUMO2: 1724 rdev->config.evergreen.num_ses = 1; 1725 rdev->config.evergreen.max_pipes = 4; 1726 rdev->config.evergreen.max_tile_pipes = 4; 1727 rdev->config.evergreen.max_simds = 2; 1728 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1729 rdev->config.evergreen.max_gprs = 256; 1730 rdev->config.evergreen.max_threads = 248; 1731 rdev->config.evergreen.max_gs_threads = 32; 1732 rdev->config.evergreen.max_stack_entries = 512; 1733 rdev->config.evergreen.sx_num_of_sets = 4; 1734 rdev->config.evergreen.sx_max_export_size = 256; 1735 rdev->config.evergreen.sx_max_export_pos_size = 64; 1736 rdev->config.evergreen.sx_max_export_smx_size = 192; 1737 rdev->config.evergreen.max_hw_contexts = 8; 1738 rdev->config.evergreen.sq_num_cf_insts = 2; 1739 1740 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1741 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1742 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1743 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; 1744 break; 1745 case CHIP_BARTS: 1746 rdev->config.evergreen.num_ses = 2; 1747 rdev->config.evergreen.max_pipes = 4; 1748 rdev->config.evergreen.max_tile_pipes = 8; 1749 rdev->config.evergreen.max_simds = 7; 1750 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; 1751 rdev->config.evergreen.max_gprs = 256; 1752 rdev->config.evergreen.max_threads = 248; 1753 rdev->config.evergreen.max_gs_threads = 32; 1754 rdev->config.evergreen.max_stack_entries = 512; 1755 rdev->config.evergreen.sx_num_of_sets = 4; 1756 rdev->config.evergreen.sx_max_export_size = 256; 1757 rdev->config.evergreen.sx_max_export_pos_size = 64; 1758 rdev->config.evergreen.sx_max_export_smx_size = 192; 1759 rdev->config.evergreen.max_hw_contexts = 8; 1760 rdev->config.evergreen.sq_num_cf_insts = 2; 1761 1762 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1763 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1764 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1765 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN; 1766 break; 1767 case CHIP_TURKS: 1768 rdev->config.evergreen.num_ses = 1; 1769 rdev->config.evergreen.max_pipes = 4; 1770 rdev->config.evergreen.max_tile_pipes = 4; 1771 rdev->config.evergreen.max_simds = 6; 1772 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; 1773 rdev->config.evergreen.max_gprs = 256; 1774 rdev->config.evergreen.max_threads = 248; 1775 rdev->config.evergreen.max_gs_threads = 32; 1776 rdev->config.evergreen.max_stack_entries = 256; 1777 rdev->config.evergreen.sx_num_of_sets = 4; 1778 rdev->config.evergreen.sx_max_export_size = 256; 1779 rdev->config.evergreen.sx_max_export_pos_size = 64; 1780 rdev->config.evergreen.sx_max_export_smx_size = 192; 1781 rdev->config.evergreen.max_hw_contexts = 8; 1782 rdev->config.evergreen.sq_num_cf_insts = 2; 1783 1784 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1785 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1786 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1787 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN; 1788 break; 1789 case CHIP_CAICOS: 1790 rdev->config.evergreen.num_ses = 1; 1791 rdev->config.evergreen.max_pipes = 4; 1792 rdev->config.evergreen.max_tile_pipes = 2; 1793 rdev->config.evergreen.max_simds = 2; 1794 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1795 rdev->config.evergreen.max_gprs = 256; 1796 rdev->config.evergreen.max_threads = 192; 1797 rdev->config.evergreen.max_gs_threads = 16; 1798 rdev->config.evergreen.max_stack_entries = 256; 1799 rdev->config.evergreen.sx_num_of_sets = 4; 1800 rdev->config.evergreen.sx_max_export_size = 128; 1801 rdev->config.evergreen.sx_max_export_pos_size = 32; 1802 rdev->config.evergreen.sx_max_export_smx_size = 96; 1803 rdev->config.evergreen.max_hw_contexts = 4; 1804 rdev->config.evergreen.sq_num_cf_insts = 1; 1805 1806 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1807 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1808 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1809 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN; 1810 break; 1811 } 1812 1813 /* Initialize HDP */ 1814 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1815 WREG32((0x2c14 + j), 0x00000000); 1816 WREG32((0x2c18 + j), 0x00000000); 1817 WREG32((0x2c1c + j), 0x00000000); 1818 WREG32((0x2c20 + j), 0x00000000); 1819 WREG32((0x2c24 + j), 0x00000000); 1820 } 1821 1822 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1823 1824 evergreen_fix_pci_max_read_req_size(rdev); 1825 1826 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1827 if ((rdev->family == CHIP_PALM) || 1828 (rdev->family == CHIP_SUMO) || 1829 (rdev->family == CHIP_SUMO2)) 1830 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG); 1831 else 1832 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1833 1834 /* setup tiling info dword. gb_addr_config is not adequate since it does 1835 * not have bank info, so create a custom tiling dword. 1836 * bits 3:0 num_pipes 1837 * bits 7:4 num_banks 1838 * bits 11:8 group_size 1839 * bits 15:12 row_size 1840 */ 1841 rdev->config.evergreen.tile_config = 0; 1842 switch (rdev->config.evergreen.max_tile_pipes) { 1843 case 1: 1844 default: 1845 rdev->config.evergreen.tile_config |= (0 << 0); 1846 break; 1847 case 2: 1848 rdev->config.evergreen.tile_config |= (1 << 0); 1849 break; 1850 case 4: 1851 rdev->config.evergreen.tile_config |= (2 << 0); 1852 break; 1853 case 8: 1854 rdev->config.evergreen.tile_config |= (3 << 0); 1855 break; 1856 } 1857 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ 1858 if (rdev->flags & RADEON_IS_IGP) 1859 rdev->config.evergreen.tile_config |= 1 << 4; 1860 else { 1861 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) 1862 rdev->config.evergreen.tile_config |= 1 << 4; 1863 else 1864 rdev->config.evergreen.tile_config |= 0 << 4; 1865 } 1866 rdev->config.evergreen.tile_config |= 0 << 8; 1867 rdev->config.evergreen.tile_config |= 1868 ((gb_addr_config & 0x30000000) >> 28) << 12; 1869 1870 num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1; 1871 1872 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) { 1873 u32 efuse_straps_4; 1874 u32 efuse_straps_3; 1875 1876 WREG32(RCU_IND_INDEX, 0x204); 1877 efuse_straps_4 = RREG32(RCU_IND_DATA); 1878 WREG32(RCU_IND_INDEX, 0x203); 1879 efuse_straps_3 = RREG32(RCU_IND_DATA); 1880 tmp = (((efuse_straps_4 & 0xf) << 4) | 1881 ((efuse_straps_3 & 0xf0000000) >> 28)); 1882 } else { 1883 tmp = 0; 1884 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) { 1885 u32 rb_disable_bitmap; 1886 1887 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1888 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 1889 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; 1890 tmp <<= 4; 1891 tmp |= rb_disable_bitmap; 1892 } 1893 } 1894 /* enabled rb are just the one not disabled :) */ 1895 disabled_rb_mask = tmp; 1896 1897 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 1898 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 1899 1900 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1901 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1902 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1903 1904 tmp = gb_addr_config & NUM_PIPES_MASK; 1905 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends, 1906 EVERGREEN_MAX_BACKENDS, disabled_rb_mask); 1907 WREG32(GB_BACKEND_MAP, tmp); 1908 1909 WREG32(CGTS_SYS_TCC_DISABLE, 0); 1910 WREG32(CGTS_TCC_DISABLE, 0); 1911 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); 1912 WREG32(CGTS_USER_TCC_DISABLE, 0); 1913 1914 /* set HW defaults for 3D engine */ 1915 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 1916 ROQ_IB2_START(0x2b))); 1917 1918 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); 1919 1920 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | 1921 SYNC_GRADIENT | 1922 SYNC_WALKER | 1923 SYNC_ALIGNER)); 1924 1925 sx_debug_1 = RREG32(SX_DEBUG_1); 1926 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 1927 WREG32(SX_DEBUG_1, sx_debug_1); 1928 1929 1930 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 1931 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); 1932 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); 1933 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 1934 1935 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) | 1936 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | 1937 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); 1938 1939 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | 1940 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) | 1941 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size))); 1942 1943 WREG32(VGT_NUM_INSTANCES, 1); 1944 WREG32(SPI_CONFIG_CNTL, 0); 1945 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 1946 WREG32(CP_PERFMON_CNTL, 0); 1947 1948 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | 1949 FETCH_FIFO_HIWATER(0x4) | 1950 DONE_FIFO_HIWATER(0xe0) | 1951 ALU_UPDATE_FIFO_HIWATER(0x8))); 1952 1953 sq_config = RREG32(SQ_CONFIG); 1954 sq_config &= ~(PS_PRIO(3) | 1955 VS_PRIO(3) | 1956 GS_PRIO(3) | 1957 ES_PRIO(3)); 1958 sq_config |= (VC_ENABLE | 1959 EXPORT_SRC_C | 1960 PS_PRIO(0) | 1961 VS_PRIO(1) | 1962 GS_PRIO(2) | 1963 ES_PRIO(3)); 1964 1965 switch (rdev->family) { 1966 case CHIP_CEDAR: 1967 case CHIP_PALM: 1968 case CHIP_SUMO: 1969 case CHIP_SUMO2: 1970 case CHIP_CAICOS: 1971 /* no vertex cache */ 1972 sq_config &= ~VC_ENABLE; 1973 break; 1974 default: 1975 break; 1976 } 1977 1978 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT); 1979 1980 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32); 1981 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32); 1982 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4); 1983 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); 1984 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); 1985 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); 1986 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); 1987 1988 switch (rdev->family) { 1989 case CHIP_CEDAR: 1990 case CHIP_PALM: 1991 case CHIP_SUMO: 1992 case CHIP_SUMO2: 1993 ps_thread_count = 96; 1994 break; 1995 default: 1996 ps_thread_count = 128; 1997 break; 1998 } 1999 2000 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count); 2001 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2002 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2003 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2004 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2005 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2006 2007 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2008 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2009 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2010 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2011 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2012 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2013 2014 WREG32(SQ_CONFIG, sq_config); 2015 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2016 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2017 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3); 2018 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2019 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2); 2020 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2021 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2022 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3); 2023 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); 2024 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt); 2025 2026 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 2027 FORCE_EOV_MAX_REZ_CNT(255))); 2028 2029 switch (rdev->family) { 2030 case CHIP_CEDAR: 2031 case CHIP_PALM: 2032 case CHIP_SUMO: 2033 case CHIP_SUMO2: 2034 case CHIP_CAICOS: 2035 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY); 2036 break; 2037 default: 2038 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC); 2039 break; 2040 } 2041 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO); 2042 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation); 2043 2044 WREG32(VGT_GS_VERTEX_REUSE, 16); 2045 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0); 2046 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2047 2048 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14); 2049 WREG32(VGT_OUT_DEALLOC_CNTL, 16); 2050 2051 WREG32(CB_PERF_CTR0_SEL_0, 0); 2052 WREG32(CB_PERF_CTR0_SEL_1, 0); 2053 WREG32(CB_PERF_CTR1_SEL_0, 0); 2054 WREG32(CB_PERF_CTR1_SEL_1, 0); 2055 WREG32(CB_PERF_CTR2_SEL_0, 0); 2056 WREG32(CB_PERF_CTR2_SEL_1, 0); 2057 WREG32(CB_PERF_CTR3_SEL_0, 0); 2058 WREG32(CB_PERF_CTR3_SEL_1, 0); 2059 2060 /* clear render buffer base addresses */ 2061 WREG32(CB_COLOR0_BASE, 0); 2062 WREG32(CB_COLOR1_BASE, 0); 2063 WREG32(CB_COLOR2_BASE, 0); 2064 WREG32(CB_COLOR3_BASE, 0); 2065 WREG32(CB_COLOR4_BASE, 0); 2066 WREG32(CB_COLOR5_BASE, 0); 2067 WREG32(CB_COLOR6_BASE, 0); 2068 WREG32(CB_COLOR7_BASE, 0); 2069 WREG32(CB_COLOR8_BASE, 0); 2070 WREG32(CB_COLOR9_BASE, 0); 2071 WREG32(CB_COLOR10_BASE, 0); 2072 WREG32(CB_COLOR11_BASE, 0); 2073 2074 /* set the shader const cache sizes to 0 */ 2075 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4) 2076 WREG32(i, 0); 2077 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4) 2078 WREG32(i, 0); 2079 2080 tmp = RREG32(HDP_MISC_CNTL); 2081 tmp |= HDP_FLUSH_INVALIDATE_CACHE; 2082 WREG32(HDP_MISC_CNTL, tmp); 2083 2084 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 2085 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 2086 2087 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 2088 2089 udelay(50); 2090 2091 } 2092 2093 int evergreen_mc_init(struct radeon_device *rdev) 2094 { 2095 u32 tmp; 2096 int chansize, numchan; 2097 2098 /* Get VRAM informations */ 2099 rdev->mc.vram_is_ddr = true; 2100 if ((rdev->family == CHIP_PALM) || 2101 (rdev->family == CHIP_SUMO) || 2102 (rdev->family == CHIP_SUMO2)) 2103 tmp = RREG32(FUS_MC_ARB_RAMCFG); 2104 else 2105 tmp = RREG32(MC_ARB_RAMCFG); 2106 if (tmp & CHANSIZE_OVERRIDE) { 2107 chansize = 16; 2108 } else if (tmp & CHANSIZE_MASK) { 2109 chansize = 64; 2110 } else { 2111 chansize = 32; 2112 } 2113 tmp = RREG32(MC_SHARED_CHMAP); 2114 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 2115 case 0: 2116 default: 2117 numchan = 1; 2118 break; 2119 case 1: 2120 numchan = 2; 2121 break; 2122 case 2: 2123 numchan = 4; 2124 break; 2125 case 3: 2126 numchan = 8; 2127 break; 2128 } 2129 rdev->mc.vram_width = numchan * chansize; 2130 /* Could aper size report 0 ? */ 2131 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2132 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2133 /* Setup GPU memory space */ 2134 if ((rdev->family == CHIP_PALM) || 2135 (rdev->family == CHIP_SUMO) || 2136 (rdev->family == CHIP_SUMO2)) { 2137 /* size in bytes on fusion */ 2138 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 2139 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 2140 } else { 2141 /* size in MB on evergreen/cayman/tn */ 2142 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2143 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2144 } 2145 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2146 r700_vram_gtt_location(rdev, &rdev->mc); 2147 radeon_update_bandwidth_info(rdev); 2148 2149 return 0; 2150 } 2151 2152 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2153 { 2154 u32 srbm_status; 2155 u32 grbm_status; 2156 u32 grbm_status_se0, grbm_status_se1; 2157 2158 srbm_status = RREG32(SRBM_STATUS); 2159 grbm_status = RREG32(GRBM_STATUS); 2160 grbm_status_se0 = RREG32(GRBM_STATUS_SE0); 2161 grbm_status_se1 = RREG32(GRBM_STATUS_SE1); 2162 if (!(grbm_status & GUI_ACTIVE)) { 2163 radeon_ring_lockup_update(ring); 2164 return false; 2165 } 2166 /* force CP activities */ 2167 radeon_ring_force_activity(rdev, ring); 2168 return radeon_ring_test_lockup(rdev, ring); 2169 } 2170 2171 static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 2172 { 2173 struct evergreen_mc_save save; 2174 u32 grbm_reset = 0; 2175 2176 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2177 return 0; 2178 2179 dev_info(rdev->dev, "GPU softreset \n"); 2180 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2181 RREG32(GRBM_STATUS)); 2182 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2183 RREG32(GRBM_STATUS_SE0)); 2184 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2185 RREG32(GRBM_STATUS_SE1)); 2186 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 2187 RREG32(SRBM_STATUS)); 2188 evergreen_mc_stop(rdev, &save); 2189 if (evergreen_mc_wait_for_idle(rdev)) { 2190 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2191 } 2192 /* Disable CP parsing/prefetching */ 2193 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); 2194 2195 /* reset all the gfx blocks */ 2196 grbm_reset = (SOFT_RESET_CP | 2197 SOFT_RESET_CB | 2198 SOFT_RESET_DB | 2199 SOFT_RESET_PA | 2200 SOFT_RESET_SC | 2201 SOFT_RESET_SPI | 2202 SOFT_RESET_SH | 2203 SOFT_RESET_SX | 2204 SOFT_RESET_TC | 2205 SOFT_RESET_TA | 2206 SOFT_RESET_VC | 2207 SOFT_RESET_VGT); 2208 2209 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); 2210 WREG32(GRBM_SOFT_RESET, grbm_reset); 2211 (void)RREG32(GRBM_SOFT_RESET); 2212 udelay(50); 2213 WREG32(GRBM_SOFT_RESET, 0); 2214 (void)RREG32(GRBM_SOFT_RESET); 2215 /* Wait a little for things to settle down */ 2216 udelay(50); 2217 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2218 RREG32(GRBM_STATUS)); 2219 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2220 RREG32(GRBM_STATUS_SE0)); 2221 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2222 RREG32(GRBM_STATUS_SE1)); 2223 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 2224 RREG32(SRBM_STATUS)); 2225 evergreen_mc_resume(rdev, &save); 2226 return 0; 2227 } 2228 2229 int evergreen_asic_reset(struct radeon_device *rdev) 2230 { 2231 return evergreen_gpu_soft_reset(rdev); 2232 } 2233 2234 /* Interrupts */ 2235 2236 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc) 2237 { 2238 switch (crtc) { 2239 case 0: 2240 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET); 2241 case 1: 2242 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET); 2243 case 2: 2244 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET); 2245 case 3: 2246 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET); 2247 case 4: 2248 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET); 2249 case 5: 2250 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET); 2251 default: 2252 return 0; 2253 } 2254 } 2255 2256 void evergreen_disable_interrupt_state(struct radeon_device *rdev) 2257 { 2258 u32 tmp; 2259 2260 if (rdev->family >= CHIP_CAYMAN) { 2261 cayman_cp_int_cntl_setup(rdev, 0, 2262 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 2263 cayman_cp_int_cntl_setup(rdev, 1, 0); 2264 cayman_cp_int_cntl_setup(rdev, 2, 0); 2265 } else 2266 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 2267 WREG32(GRBM_INT_CNTL, 0); 2268 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2269 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2270 if (rdev->num_crtc >= 4) { 2271 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2272 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2273 } 2274 if (rdev->num_crtc >= 6) { 2275 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2276 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2277 } 2278 2279 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2280 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2281 if (rdev->num_crtc >= 4) { 2282 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2283 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2284 } 2285 if (rdev->num_crtc >= 6) { 2286 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2287 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2288 } 2289 2290 /* only one DAC on DCE6 */ 2291 if (!ASIC_IS_DCE6(rdev)) 2292 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 2293 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 2294 2295 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2296 WREG32(DC_HPD1_INT_CONTROL, tmp); 2297 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2298 WREG32(DC_HPD2_INT_CONTROL, tmp); 2299 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2300 WREG32(DC_HPD3_INT_CONTROL, tmp); 2301 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2302 WREG32(DC_HPD4_INT_CONTROL, tmp); 2303 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2304 WREG32(DC_HPD5_INT_CONTROL, tmp); 2305 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2306 WREG32(DC_HPD6_INT_CONTROL, tmp); 2307 2308 } 2309 2310 int evergreen_irq_set(struct radeon_device *rdev) 2311 { 2312 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 2313 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; 2314 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 2315 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 2316 u32 grbm_int_cntl = 0; 2317 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; 2318 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; 2319 2320 if (!rdev->irq.installed) { 2321 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 2322 return -EINVAL; 2323 } 2324 /* don't enable anything if the ih is disabled */ 2325 if (!rdev->ih.enabled) { 2326 r600_disable_interrupts(rdev); 2327 /* force the active interrupt state to all disabled */ 2328 evergreen_disable_interrupt_state(rdev); 2329 return 0; 2330 } 2331 2332 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 2333 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 2334 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 2335 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 2336 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 2337 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 2338 2339 afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 2340 afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 2341 afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 2342 afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 2343 afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 2344 afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 2345 2346 if (rdev->family >= CHIP_CAYMAN) { 2347 /* enable CP interrupts on all rings */ 2348 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) { 2349 DRM_DEBUG("evergreen_irq_set: sw int gfx\n"); 2350 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 2351 } 2352 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) { 2353 DRM_DEBUG("evergreen_irq_set: sw int cp1\n"); 2354 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; 2355 } 2356 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) { 2357 DRM_DEBUG("evergreen_irq_set: sw int cp2\n"); 2358 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; 2359 } 2360 } else { 2361 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) { 2362 DRM_DEBUG("evergreen_irq_set: sw int gfx\n"); 2363 cp_int_cntl |= RB_INT_ENABLE; 2364 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 2365 } 2366 } 2367 2368 if (rdev->irq.crtc_vblank_int[0] || 2369 rdev->irq.pflip[0]) { 2370 DRM_DEBUG("evergreen_irq_set: vblank 0\n"); 2371 crtc1 |= VBLANK_INT_MASK; 2372 } 2373 if (rdev->irq.crtc_vblank_int[1] || 2374 rdev->irq.pflip[1]) { 2375 DRM_DEBUG("evergreen_irq_set: vblank 1\n"); 2376 crtc2 |= VBLANK_INT_MASK; 2377 } 2378 if (rdev->irq.crtc_vblank_int[2] || 2379 rdev->irq.pflip[2]) { 2380 DRM_DEBUG("evergreen_irq_set: vblank 2\n"); 2381 crtc3 |= VBLANK_INT_MASK; 2382 } 2383 if (rdev->irq.crtc_vblank_int[3] || 2384 rdev->irq.pflip[3]) { 2385 DRM_DEBUG("evergreen_irq_set: vblank 3\n"); 2386 crtc4 |= VBLANK_INT_MASK; 2387 } 2388 if (rdev->irq.crtc_vblank_int[4] || 2389 rdev->irq.pflip[4]) { 2390 DRM_DEBUG("evergreen_irq_set: vblank 4\n"); 2391 crtc5 |= VBLANK_INT_MASK; 2392 } 2393 if (rdev->irq.crtc_vblank_int[5] || 2394 rdev->irq.pflip[5]) { 2395 DRM_DEBUG("evergreen_irq_set: vblank 5\n"); 2396 crtc6 |= VBLANK_INT_MASK; 2397 } 2398 if (rdev->irq.hpd[0]) { 2399 DRM_DEBUG("evergreen_irq_set: hpd 1\n"); 2400 hpd1 |= DC_HPDx_INT_EN; 2401 } 2402 if (rdev->irq.hpd[1]) { 2403 DRM_DEBUG("evergreen_irq_set: hpd 2\n"); 2404 hpd2 |= DC_HPDx_INT_EN; 2405 } 2406 if (rdev->irq.hpd[2]) { 2407 DRM_DEBUG("evergreen_irq_set: hpd 3\n"); 2408 hpd3 |= DC_HPDx_INT_EN; 2409 } 2410 if (rdev->irq.hpd[3]) { 2411 DRM_DEBUG("evergreen_irq_set: hpd 4\n"); 2412 hpd4 |= DC_HPDx_INT_EN; 2413 } 2414 if (rdev->irq.hpd[4]) { 2415 DRM_DEBUG("evergreen_irq_set: hpd 5\n"); 2416 hpd5 |= DC_HPDx_INT_EN; 2417 } 2418 if (rdev->irq.hpd[5]) { 2419 DRM_DEBUG("evergreen_irq_set: hpd 6\n"); 2420 hpd6 |= DC_HPDx_INT_EN; 2421 } 2422 if (rdev->irq.afmt[0]) { 2423 DRM_DEBUG("evergreen_irq_set: hdmi 0\n"); 2424 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK; 2425 } 2426 if (rdev->irq.afmt[1]) { 2427 DRM_DEBUG("evergreen_irq_set: hdmi 1\n"); 2428 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK; 2429 } 2430 if (rdev->irq.afmt[2]) { 2431 DRM_DEBUG("evergreen_irq_set: hdmi 2\n"); 2432 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK; 2433 } 2434 if (rdev->irq.afmt[3]) { 2435 DRM_DEBUG("evergreen_irq_set: hdmi 3\n"); 2436 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK; 2437 } 2438 if (rdev->irq.afmt[4]) { 2439 DRM_DEBUG("evergreen_irq_set: hdmi 4\n"); 2440 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK; 2441 } 2442 if (rdev->irq.afmt[5]) { 2443 DRM_DEBUG("evergreen_irq_set: hdmi 5\n"); 2444 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK; 2445 } 2446 if (rdev->irq.gui_idle) { 2447 DRM_DEBUG("gui idle\n"); 2448 grbm_int_cntl |= GUI_IDLE_INT_ENABLE; 2449 } 2450 2451 if (rdev->family >= CHIP_CAYMAN) { 2452 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); 2453 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1); 2454 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2); 2455 } else 2456 WREG32(CP_INT_CNTL, cp_int_cntl); 2457 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 2458 2459 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 2460 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 2461 if (rdev->num_crtc >= 4) { 2462 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 2463 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 2464 } 2465 if (rdev->num_crtc >= 6) { 2466 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 2467 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 2468 } 2469 2470 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 2471 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 2472 if (rdev->num_crtc >= 4) { 2473 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 2474 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 2475 } 2476 if (rdev->num_crtc >= 6) { 2477 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 2478 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 2479 } 2480 2481 WREG32(DC_HPD1_INT_CONTROL, hpd1); 2482 WREG32(DC_HPD2_INT_CONTROL, hpd2); 2483 WREG32(DC_HPD3_INT_CONTROL, hpd3); 2484 WREG32(DC_HPD4_INT_CONTROL, hpd4); 2485 WREG32(DC_HPD5_INT_CONTROL, hpd5); 2486 WREG32(DC_HPD6_INT_CONTROL, hpd6); 2487 2488 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1); 2489 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2); 2490 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3); 2491 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4); 2492 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5); 2493 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6); 2494 2495 return 0; 2496 } 2497 2498 static void evergreen_irq_ack(struct radeon_device *rdev) 2499 { 2500 u32 tmp; 2501 2502 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); 2503 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 2504 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); 2505 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); 2506 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); 2507 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 2508 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 2509 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 2510 if (rdev->num_crtc >= 4) { 2511 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 2512 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 2513 } 2514 if (rdev->num_crtc >= 6) { 2515 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 2516 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 2517 } 2518 2519 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 2520 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 2521 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 2522 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 2523 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 2524 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 2525 2526 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) 2527 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2528 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) 2529 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2530 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) 2531 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 2532 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) 2533 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); 2534 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) 2535 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); 2536 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) 2537 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 2538 2539 if (rdev->num_crtc >= 4) { 2540 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) 2541 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2542 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) 2543 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2544 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 2545 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 2546 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 2547 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 2548 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 2549 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 2550 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 2551 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 2552 } 2553 2554 if (rdev->num_crtc >= 6) { 2555 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) 2556 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2557 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) 2558 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2559 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 2560 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 2561 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 2562 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 2563 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 2564 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 2565 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 2566 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 2567 } 2568 2569 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 2570 tmp = RREG32(DC_HPD1_INT_CONTROL); 2571 tmp |= DC_HPDx_INT_ACK; 2572 WREG32(DC_HPD1_INT_CONTROL, tmp); 2573 } 2574 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 2575 tmp = RREG32(DC_HPD2_INT_CONTROL); 2576 tmp |= DC_HPDx_INT_ACK; 2577 WREG32(DC_HPD2_INT_CONTROL, tmp); 2578 } 2579 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 2580 tmp = RREG32(DC_HPD3_INT_CONTROL); 2581 tmp |= DC_HPDx_INT_ACK; 2582 WREG32(DC_HPD3_INT_CONTROL, tmp); 2583 } 2584 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 2585 tmp = RREG32(DC_HPD4_INT_CONTROL); 2586 tmp |= DC_HPDx_INT_ACK; 2587 WREG32(DC_HPD4_INT_CONTROL, tmp); 2588 } 2589 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 2590 tmp = RREG32(DC_HPD5_INT_CONTROL); 2591 tmp |= DC_HPDx_INT_ACK; 2592 WREG32(DC_HPD5_INT_CONTROL, tmp); 2593 } 2594 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 2595 tmp = RREG32(DC_HPD5_INT_CONTROL); 2596 tmp |= DC_HPDx_INT_ACK; 2597 WREG32(DC_HPD6_INT_CONTROL, tmp); 2598 } 2599 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { 2600 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 2601 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 2602 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp); 2603 } 2604 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) { 2605 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 2606 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 2607 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp); 2608 } 2609 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) { 2610 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 2611 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 2612 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp); 2613 } 2614 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) { 2615 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 2616 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 2617 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp); 2618 } 2619 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) { 2620 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 2621 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 2622 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp); 2623 } 2624 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) { 2625 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 2626 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 2627 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp); 2628 } 2629 } 2630 2631 void evergreen_irq_disable(struct radeon_device *rdev) 2632 { 2633 r600_disable_interrupts(rdev); 2634 /* Wait and acknowledge irq */ 2635 mdelay(1); 2636 evergreen_irq_ack(rdev); 2637 evergreen_disable_interrupt_state(rdev); 2638 } 2639 2640 void evergreen_irq_suspend(struct radeon_device *rdev) 2641 { 2642 evergreen_irq_disable(rdev); 2643 r600_rlc_stop(rdev); 2644 } 2645 2646 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev) 2647 { 2648 u32 wptr, tmp; 2649 2650 if (rdev->wb.enabled) 2651 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 2652 else 2653 wptr = RREG32(IH_RB_WPTR); 2654 2655 if (wptr & RB_OVERFLOW) { 2656 /* When a ring buffer overflow happen start parsing interrupt 2657 * from the last not overwritten vector (wptr + 16). Hopefully 2658 * this should allow us to catchup. 2659 */ 2660 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 2661 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 2662 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 2663 tmp = RREG32(IH_RB_CNTL); 2664 tmp |= IH_WPTR_OVERFLOW_CLEAR; 2665 WREG32(IH_RB_CNTL, tmp); 2666 } 2667 return (wptr & rdev->ih.ptr_mask); 2668 } 2669 2670 int evergreen_irq_process(struct radeon_device *rdev) 2671 { 2672 u32 wptr; 2673 u32 rptr; 2674 u32 src_id, src_data; 2675 u32 ring_index; 2676 unsigned long flags; 2677 bool queue_hotplug = false; 2678 bool queue_hdmi = false; 2679 2680 if (!rdev->ih.enabled || rdev->shutdown) 2681 return IRQ_NONE; 2682 2683 wptr = evergreen_get_ih_wptr(rdev); 2684 rptr = rdev->ih.rptr; 2685 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 2686 2687 spin_lock_irqsave(&rdev->ih.lock, flags); 2688 if (rptr == wptr) { 2689 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2690 return IRQ_NONE; 2691 } 2692 restart_ih: 2693 /* Order reading of wptr vs. reading of IH ring data */ 2694 rmb(); 2695 2696 /* display interrupts */ 2697 evergreen_irq_ack(rdev); 2698 2699 rdev->ih.wptr = wptr; 2700 while (rptr != wptr) { 2701 /* wptr/rptr are in bytes! */ 2702 ring_index = rptr / 4; 2703 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 2704 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 2705 2706 switch (src_id) { 2707 case 1: /* D1 vblank/vline */ 2708 switch (src_data) { 2709 case 0: /* D1 vblank */ 2710 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { 2711 if (rdev->irq.crtc_vblank_int[0]) { 2712 drm_handle_vblank(rdev->ddev, 0); 2713 rdev->pm.vblank_sync = true; 2714 wake_up(&rdev->irq.vblank_queue); 2715 } 2716 if (rdev->irq.pflip[0]) 2717 radeon_crtc_handle_flip(rdev, 0); 2718 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 2719 DRM_DEBUG("IH: D1 vblank\n"); 2720 } 2721 break; 2722 case 1: /* D1 vline */ 2723 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { 2724 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; 2725 DRM_DEBUG("IH: D1 vline\n"); 2726 } 2727 break; 2728 default: 2729 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2730 break; 2731 } 2732 break; 2733 case 2: /* D2 vblank/vline */ 2734 switch (src_data) { 2735 case 0: /* D2 vblank */ 2736 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { 2737 if (rdev->irq.crtc_vblank_int[1]) { 2738 drm_handle_vblank(rdev->ddev, 1); 2739 rdev->pm.vblank_sync = true; 2740 wake_up(&rdev->irq.vblank_queue); 2741 } 2742 if (rdev->irq.pflip[1]) 2743 radeon_crtc_handle_flip(rdev, 1); 2744 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 2745 DRM_DEBUG("IH: D2 vblank\n"); 2746 } 2747 break; 2748 case 1: /* D2 vline */ 2749 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { 2750 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 2751 DRM_DEBUG("IH: D2 vline\n"); 2752 } 2753 break; 2754 default: 2755 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2756 break; 2757 } 2758 break; 2759 case 3: /* D3 vblank/vline */ 2760 switch (src_data) { 2761 case 0: /* D3 vblank */ 2762 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { 2763 if (rdev->irq.crtc_vblank_int[2]) { 2764 drm_handle_vblank(rdev->ddev, 2); 2765 rdev->pm.vblank_sync = true; 2766 wake_up(&rdev->irq.vblank_queue); 2767 } 2768 if (rdev->irq.pflip[2]) 2769 radeon_crtc_handle_flip(rdev, 2); 2770 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 2771 DRM_DEBUG("IH: D3 vblank\n"); 2772 } 2773 break; 2774 case 1: /* D3 vline */ 2775 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { 2776 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 2777 DRM_DEBUG("IH: D3 vline\n"); 2778 } 2779 break; 2780 default: 2781 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2782 break; 2783 } 2784 break; 2785 case 4: /* D4 vblank/vline */ 2786 switch (src_data) { 2787 case 0: /* D4 vblank */ 2788 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { 2789 if (rdev->irq.crtc_vblank_int[3]) { 2790 drm_handle_vblank(rdev->ddev, 3); 2791 rdev->pm.vblank_sync = true; 2792 wake_up(&rdev->irq.vblank_queue); 2793 } 2794 if (rdev->irq.pflip[3]) 2795 radeon_crtc_handle_flip(rdev, 3); 2796 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 2797 DRM_DEBUG("IH: D4 vblank\n"); 2798 } 2799 break; 2800 case 1: /* D4 vline */ 2801 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { 2802 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 2803 DRM_DEBUG("IH: D4 vline\n"); 2804 } 2805 break; 2806 default: 2807 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2808 break; 2809 } 2810 break; 2811 case 5: /* D5 vblank/vline */ 2812 switch (src_data) { 2813 case 0: /* D5 vblank */ 2814 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { 2815 if (rdev->irq.crtc_vblank_int[4]) { 2816 drm_handle_vblank(rdev->ddev, 4); 2817 rdev->pm.vblank_sync = true; 2818 wake_up(&rdev->irq.vblank_queue); 2819 } 2820 if (rdev->irq.pflip[4]) 2821 radeon_crtc_handle_flip(rdev, 4); 2822 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 2823 DRM_DEBUG("IH: D5 vblank\n"); 2824 } 2825 break; 2826 case 1: /* D5 vline */ 2827 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { 2828 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 2829 DRM_DEBUG("IH: D5 vline\n"); 2830 } 2831 break; 2832 default: 2833 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2834 break; 2835 } 2836 break; 2837 case 6: /* D6 vblank/vline */ 2838 switch (src_data) { 2839 case 0: /* D6 vblank */ 2840 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { 2841 if (rdev->irq.crtc_vblank_int[5]) { 2842 drm_handle_vblank(rdev->ddev, 5); 2843 rdev->pm.vblank_sync = true; 2844 wake_up(&rdev->irq.vblank_queue); 2845 } 2846 if (rdev->irq.pflip[5]) 2847 radeon_crtc_handle_flip(rdev, 5); 2848 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 2849 DRM_DEBUG("IH: D6 vblank\n"); 2850 } 2851 break; 2852 case 1: /* D6 vline */ 2853 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { 2854 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 2855 DRM_DEBUG("IH: D6 vline\n"); 2856 } 2857 break; 2858 default: 2859 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2860 break; 2861 } 2862 break; 2863 case 42: /* HPD hotplug */ 2864 switch (src_data) { 2865 case 0: 2866 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 2867 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; 2868 queue_hotplug = true; 2869 DRM_DEBUG("IH: HPD1\n"); 2870 } 2871 break; 2872 case 1: 2873 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 2874 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; 2875 queue_hotplug = true; 2876 DRM_DEBUG("IH: HPD2\n"); 2877 } 2878 break; 2879 case 2: 2880 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 2881 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 2882 queue_hotplug = true; 2883 DRM_DEBUG("IH: HPD3\n"); 2884 } 2885 break; 2886 case 3: 2887 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 2888 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 2889 queue_hotplug = true; 2890 DRM_DEBUG("IH: HPD4\n"); 2891 } 2892 break; 2893 case 4: 2894 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 2895 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 2896 queue_hotplug = true; 2897 DRM_DEBUG("IH: HPD5\n"); 2898 } 2899 break; 2900 case 5: 2901 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 2902 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 2903 queue_hotplug = true; 2904 DRM_DEBUG("IH: HPD6\n"); 2905 } 2906 break; 2907 default: 2908 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2909 break; 2910 } 2911 break; 2912 case 44: /* hdmi */ 2913 switch (src_data) { 2914 case 0: 2915 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { 2916 rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG; 2917 queue_hdmi = true; 2918 DRM_DEBUG("IH: HDMI0\n"); 2919 } 2920 break; 2921 case 1: 2922 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) { 2923 rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG; 2924 queue_hdmi = true; 2925 DRM_DEBUG("IH: HDMI1\n"); 2926 } 2927 break; 2928 case 2: 2929 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) { 2930 rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG; 2931 queue_hdmi = true; 2932 DRM_DEBUG("IH: HDMI2\n"); 2933 } 2934 break; 2935 case 3: 2936 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) { 2937 rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG; 2938 queue_hdmi = true; 2939 DRM_DEBUG("IH: HDMI3\n"); 2940 } 2941 break; 2942 case 4: 2943 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) { 2944 rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG; 2945 queue_hdmi = true; 2946 DRM_DEBUG("IH: HDMI4\n"); 2947 } 2948 break; 2949 case 5: 2950 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) { 2951 rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG; 2952 queue_hdmi = true; 2953 DRM_DEBUG("IH: HDMI5\n"); 2954 } 2955 break; 2956 default: 2957 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2958 break; 2959 } 2960 break; 2961 case 176: /* CP_INT in ring buffer */ 2962 case 177: /* CP_INT in IB1 */ 2963 case 178: /* CP_INT in IB2 */ 2964 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 2965 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 2966 break; 2967 case 181: /* CP EOP event */ 2968 DRM_DEBUG("IH: CP EOP\n"); 2969 if (rdev->family >= CHIP_CAYMAN) { 2970 switch (src_data) { 2971 case 0: 2972 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 2973 break; 2974 case 1: 2975 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 2976 break; 2977 case 2: 2978 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 2979 break; 2980 } 2981 } else 2982 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 2983 break; 2984 case 233: /* GUI IDLE */ 2985 DRM_DEBUG("IH: GUI idle\n"); 2986 rdev->pm.gui_idle = true; 2987 wake_up(&rdev->irq.idle_queue); 2988 break; 2989 default: 2990 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2991 break; 2992 } 2993 2994 /* wptr/rptr are in bytes! */ 2995 rptr += 16; 2996 rptr &= rdev->ih.ptr_mask; 2997 } 2998 /* make sure wptr hasn't changed while processing */ 2999 wptr = evergreen_get_ih_wptr(rdev); 3000 if (wptr != rdev->ih.wptr) 3001 goto restart_ih; 3002 if (queue_hotplug) 3003 schedule_work(&rdev->hotplug_work); 3004 if (queue_hdmi) 3005 schedule_work(&rdev->audio_work); 3006 rdev->ih.rptr = rptr; 3007 WREG32(IH_RB_RPTR, rdev->ih.rptr); 3008 spin_unlock_irqrestore(&rdev->ih.lock, flags); 3009 return IRQ_HANDLED; 3010 } 3011 3012 static int evergreen_startup(struct radeon_device *rdev) 3013 { 3014 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3015 int r; 3016 3017 /* enable pcie gen2 link */ 3018 evergreen_pcie_gen2_enable(rdev); 3019 3020 if (ASIC_IS_DCE5(rdev)) { 3021 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { 3022 r = ni_init_microcode(rdev); 3023 if (r) { 3024 DRM_ERROR("Failed to load firmware!\n"); 3025 return r; 3026 } 3027 } 3028 r = ni_mc_load_microcode(rdev); 3029 if (r) { 3030 DRM_ERROR("Failed to load MC firmware!\n"); 3031 return r; 3032 } 3033 } else { 3034 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3035 r = r600_init_microcode(rdev); 3036 if (r) { 3037 DRM_ERROR("Failed to load firmware!\n"); 3038 return r; 3039 } 3040 } 3041 } 3042 3043 r = r600_vram_scratch_init(rdev); 3044 if (r) 3045 return r; 3046 3047 evergreen_mc_program(rdev); 3048 if (rdev->flags & RADEON_IS_AGP) { 3049 evergreen_agp_enable(rdev); 3050 } else { 3051 r = evergreen_pcie_gart_enable(rdev); 3052 if (r) 3053 return r; 3054 } 3055 evergreen_gpu_init(rdev); 3056 3057 r = evergreen_blit_init(rdev); 3058 if (r) { 3059 r600_blit_fini(rdev); 3060 rdev->asic->copy.copy = NULL; 3061 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 3062 } 3063 3064 /* allocate wb buffer */ 3065 r = radeon_wb_init(rdev); 3066 if (r) 3067 return r; 3068 3069 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3070 if (r) { 3071 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3072 return r; 3073 } 3074 3075 /* Enable IRQ */ 3076 r = r600_irq_init(rdev); 3077 if (r) { 3078 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3079 radeon_irq_kms_fini(rdev); 3080 return r; 3081 } 3082 evergreen_irq_set(rdev); 3083 3084 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3085 R600_CP_RB_RPTR, R600_CP_RB_WPTR, 3086 0, 0xfffff, RADEON_CP_PACKET2); 3087 if (r) 3088 return r; 3089 r = evergreen_cp_load_microcode(rdev); 3090 if (r) 3091 return r; 3092 r = evergreen_cp_resume(rdev); 3093 if (r) 3094 return r; 3095 3096 r = radeon_ib_pool_start(rdev); 3097 if (r) 3098 return r; 3099 3100 r = radeon_ib_ring_tests(rdev); 3101 if (r) 3102 return r; 3103 3104 r = r600_audio_init(rdev); 3105 if (r) { 3106 DRM_ERROR("radeon: audio init failed\n"); 3107 return r; 3108 } 3109 3110 return 0; 3111 } 3112 3113 int evergreen_resume(struct radeon_device *rdev) 3114 { 3115 int r; 3116 3117 /* reset the asic, the gfx blocks are often in a bad state 3118 * after the driver is unloaded or after a resume 3119 */ 3120 if (radeon_asic_reset(rdev)) 3121 dev_warn(rdev->dev, "GPU reset failed !\n"); 3122 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 3123 * posting will perform necessary task to bring back GPU into good 3124 * shape. 3125 */ 3126 /* post card */ 3127 atom_asic_init(rdev->mode_info.atom_context); 3128 3129 rdev->accel_working = true; 3130 r = evergreen_startup(rdev); 3131 if (r) { 3132 DRM_ERROR("evergreen startup failed on resume\n"); 3133 rdev->accel_working = false; 3134 return r; 3135 } 3136 3137 return r; 3138 3139 } 3140 3141 int evergreen_suspend(struct radeon_device *rdev) 3142 { 3143 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3144 3145 r600_audio_fini(rdev); 3146 /* FIXME: we should wait for ring to be empty */ 3147 radeon_ib_pool_suspend(rdev); 3148 r600_blit_suspend(rdev); 3149 r700_cp_stop(rdev); 3150 ring->ready = false; 3151 evergreen_irq_suspend(rdev); 3152 radeon_wb_disable(rdev); 3153 evergreen_pcie_gart_disable(rdev); 3154 3155 return 0; 3156 } 3157 3158 /* Plan is to move initialization in that function and use 3159 * helper function so that radeon_device_init pretty much 3160 * do nothing more than calling asic specific function. This 3161 * should also allow to remove a bunch of callback function 3162 * like vram_info. 3163 */ 3164 int evergreen_init(struct radeon_device *rdev) 3165 { 3166 int r; 3167 3168 /* Read BIOS */ 3169 if (!radeon_get_bios(rdev)) { 3170 if (ASIC_IS_AVIVO(rdev)) 3171 return -EINVAL; 3172 } 3173 /* Must be an ATOMBIOS */ 3174 if (!rdev->is_atom_bios) { 3175 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n"); 3176 return -EINVAL; 3177 } 3178 r = radeon_atombios_init(rdev); 3179 if (r) 3180 return r; 3181 /* reset the asic, the gfx blocks are often in a bad state 3182 * after the driver is unloaded or after a resume 3183 */ 3184 if (radeon_asic_reset(rdev)) 3185 dev_warn(rdev->dev, "GPU reset failed !\n"); 3186 /* Post card if necessary */ 3187 if (!radeon_card_posted(rdev)) { 3188 if (!rdev->bios) { 3189 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3190 return -EINVAL; 3191 } 3192 DRM_INFO("GPU not posted. posting now...\n"); 3193 atom_asic_init(rdev->mode_info.atom_context); 3194 } 3195 /* Initialize scratch registers */ 3196 r600_scratch_init(rdev); 3197 /* Initialize surface registers */ 3198 radeon_surface_init(rdev); 3199 /* Initialize clocks */ 3200 radeon_get_clock_info(rdev->ddev); 3201 /* Fence driver */ 3202 r = radeon_fence_driver_init(rdev); 3203 if (r) 3204 return r; 3205 /* initialize AGP */ 3206 if (rdev->flags & RADEON_IS_AGP) { 3207 r = radeon_agp_init(rdev); 3208 if (r) 3209 radeon_agp_disable(rdev); 3210 } 3211 /* initialize memory controller */ 3212 r = evergreen_mc_init(rdev); 3213 if (r) 3214 return r; 3215 /* Memory manager */ 3216 r = radeon_bo_init(rdev); 3217 if (r) 3218 return r; 3219 3220 r = radeon_irq_kms_init(rdev); 3221 if (r) 3222 return r; 3223 3224 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3225 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3226 3227 rdev->ih.ring_obj = NULL; 3228 r600_ih_ring_init(rdev, 64 * 1024); 3229 3230 r = r600_pcie_gart_init(rdev); 3231 if (r) 3232 return r; 3233 3234 r = radeon_ib_pool_init(rdev); 3235 rdev->accel_working = true; 3236 if (r) { 3237 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3238 rdev->accel_working = false; 3239 } 3240 3241 r = evergreen_startup(rdev); 3242 if (r) { 3243 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3244 r700_cp_fini(rdev); 3245 r600_irq_fini(rdev); 3246 radeon_wb_fini(rdev); 3247 r100_ib_fini(rdev); 3248 radeon_irq_kms_fini(rdev); 3249 evergreen_pcie_gart_fini(rdev); 3250 rdev->accel_working = false; 3251 } 3252 3253 /* Don't start up if the MC ucode is missing on BTC parts. 3254 * The default clocks and voltages before the MC ucode 3255 * is loaded are not suffient for advanced operations. 3256 */ 3257 if (ASIC_IS_DCE5(rdev)) { 3258 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { 3259 DRM_ERROR("radeon: MC ucode required for NI+.\n"); 3260 return -EINVAL; 3261 } 3262 } 3263 3264 return 0; 3265 } 3266 3267 void evergreen_fini(struct radeon_device *rdev) 3268 { 3269 r600_audio_fini(rdev); 3270 r600_blit_fini(rdev); 3271 r700_cp_fini(rdev); 3272 r600_irq_fini(rdev); 3273 radeon_wb_fini(rdev); 3274 r100_ib_fini(rdev); 3275 radeon_irq_kms_fini(rdev); 3276 evergreen_pcie_gart_fini(rdev); 3277 r600_vram_scratch_fini(rdev); 3278 radeon_gem_fini(rdev); 3279 radeon_fence_driver_fini(rdev); 3280 radeon_agp_fini(rdev); 3281 radeon_bo_fini(rdev); 3282 radeon_atombios_fini(rdev); 3283 kfree(rdev->bios); 3284 rdev->bios = NULL; 3285 } 3286 3287 void evergreen_pcie_gen2_enable(struct radeon_device *rdev) 3288 { 3289 u32 link_width_cntl, speed_cntl; 3290 3291 if (radeon_pcie_gen2 == 0) 3292 return; 3293 3294 if (rdev->flags & RADEON_IS_IGP) 3295 return; 3296 3297 if (!(rdev->flags & RADEON_IS_PCIE)) 3298 return; 3299 3300 /* x2 cards have a special sequence */ 3301 if (ASIC_IS_X2(rdev)) 3302 return; 3303 3304 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3305 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || 3306 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 3307 3308 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 3309 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 3310 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 3311 3312 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3313 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 3314 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3315 3316 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3317 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; 3318 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3319 3320 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3321 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 3322 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3323 3324 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3325 speed_cntl |= LC_GEN2_EN_STRAP; 3326 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3327 3328 } else { 3329 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 3330 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 3331 if (1) 3332 link_width_cntl |= LC_UPCONFIGURE_DIS; 3333 else 3334 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 3335 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 3336 } 3337 } 3338