1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 #include "drmP.h" 28 #include "radeon.h" 29 #include "radeon_asic.h" 30 #include "radeon_drm.h" 31 #include "evergreend.h" 32 #include "atom.h" 33 #include "avivod.h" 34 #include "evergreen_reg.h" 35 #include "evergreen_blit_shaders.h" 36 37 #define EVERGREEN_PFP_UCODE_SIZE 1120 38 #define EVERGREEN_PM4_UCODE_SIZE 1376 39 40 static void evergreen_gpu_init(struct radeon_device *rdev); 41 void evergreen_fini(struct radeon_device *rdev); 42 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 43 44 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc) 45 { 46 /* enable the pflip int */ 47 radeon_irq_kms_pflip_irq_get(rdev, crtc); 48 } 49 50 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc) 51 { 52 /* disable the pflip int */ 53 radeon_irq_kms_pflip_irq_put(rdev, crtc); 54 } 55 56 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 57 { 58 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 59 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); 60 61 /* Lock the graphics update lock */ 62 tmp |= EVERGREEN_GRPH_UPDATE_LOCK; 63 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 64 65 /* update the scanout addresses */ 66 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 67 upper_32_bits(crtc_base)); 68 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 69 (u32)crtc_base); 70 71 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 72 upper_32_bits(crtc_base)); 73 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 74 (u32)crtc_base); 75 76 /* Wait for update_pending to go high. */ 77 while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)); 78 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 79 80 /* Unlock the lock, so double-buffering can take place inside vblank */ 81 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; 82 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 83 84 /* Return current update_pending status: */ 85 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING; 86 } 87 88 /* get temperature in millidegrees */ 89 int evergreen_get_temp(struct radeon_device *rdev) 90 { 91 u32 temp, toffset, actual_temp = 0; 92 93 if (rdev->family == CHIP_JUNIPER) { 94 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> 95 TOFFSET_SHIFT; 96 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >> 97 TS0_ADC_DOUT_SHIFT; 98 99 if (toffset & 0x100) 100 actual_temp = temp / 2 - (0x200 - toffset); 101 else 102 actual_temp = temp / 2 + toffset; 103 104 actual_temp = actual_temp * 1000; 105 106 } else { 107 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> 108 ASIC_T_SHIFT; 109 110 if (temp & 0x400) 111 actual_temp = -256; 112 else if (temp & 0x200) 113 actual_temp = 255; 114 else if (temp & 0x100) { 115 actual_temp = temp & 0x1ff; 116 actual_temp |= ~0x1ff; 117 } else 118 actual_temp = temp & 0xff; 119 120 actual_temp = (actual_temp * 1000) / 2; 121 } 122 123 return actual_temp; 124 } 125 126 int sumo_get_temp(struct radeon_device *rdev) 127 { 128 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff; 129 int actual_temp = temp - 49; 130 131 return actual_temp * 1000; 132 } 133 134 void evergreen_pm_misc(struct radeon_device *rdev) 135 { 136 int req_ps_idx = rdev->pm.requested_power_state_index; 137 int req_cm_idx = rdev->pm.requested_clock_mode_index; 138 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 139 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 140 141 if (voltage->type == VOLTAGE_SW) { 142 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { 143 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 144 rdev->pm.current_vddc = voltage->voltage; 145 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage); 146 } 147 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { 148 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); 149 rdev->pm.current_vddci = voltage->vddci; 150 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci); 151 } 152 } 153 } 154 155 void evergreen_pm_prepare(struct radeon_device *rdev) 156 { 157 struct drm_device *ddev = rdev->ddev; 158 struct drm_crtc *crtc; 159 struct radeon_crtc *radeon_crtc; 160 u32 tmp; 161 162 /* disable any active CRTCs */ 163 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 164 radeon_crtc = to_radeon_crtc(crtc); 165 if (radeon_crtc->enabled) { 166 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); 167 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; 168 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 169 } 170 } 171 } 172 173 void evergreen_pm_finish(struct radeon_device *rdev) 174 { 175 struct drm_device *ddev = rdev->ddev; 176 struct drm_crtc *crtc; 177 struct radeon_crtc *radeon_crtc; 178 u32 tmp; 179 180 /* enable any active CRTCs */ 181 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 182 radeon_crtc = to_radeon_crtc(crtc); 183 if (radeon_crtc->enabled) { 184 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); 185 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; 186 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 187 } 188 } 189 } 190 191 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 192 { 193 bool connected = false; 194 195 switch (hpd) { 196 case RADEON_HPD_1: 197 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 198 connected = true; 199 break; 200 case RADEON_HPD_2: 201 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 202 connected = true; 203 break; 204 case RADEON_HPD_3: 205 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 206 connected = true; 207 break; 208 case RADEON_HPD_4: 209 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 210 connected = true; 211 break; 212 case RADEON_HPD_5: 213 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 214 connected = true; 215 break; 216 case RADEON_HPD_6: 217 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 218 connected = true; 219 break; 220 default: 221 break; 222 } 223 224 return connected; 225 } 226 227 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 228 enum radeon_hpd_id hpd) 229 { 230 u32 tmp; 231 bool connected = evergreen_hpd_sense(rdev, hpd); 232 233 switch (hpd) { 234 case RADEON_HPD_1: 235 tmp = RREG32(DC_HPD1_INT_CONTROL); 236 if (connected) 237 tmp &= ~DC_HPDx_INT_POLARITY; 238 else 239 tmp |= DC_HPDx_INT_POLARITY; 240 WREG32(DC_HPD1_INT_CONTROL, tmp); 241 break; 242 case RADEON_HPD_2: 243 tmp = RREG32(DC_HPD2_INT_CONTROL); 244 if (connected) 245 tmp &= ~DC_HPDx_INT_POLARITY; 246 else 247 tmp |= DC_HPDx_INT_POLARITY; 248 WREG32(DC_HPD2_INT_CONTROL, tmp); 249 break; 250 case RADEON_HPD_3: 251 tmp = RREG32(DC_HPD3_INT_CONTROL); 252 if (connected) 253 tmp &= ~DC_HPDx_INT_POLARITY; 254 else 255 tmp |= DC_HPDx_INT_POLARITY; 256 WREG32(DC_HPD3_INT_CONTROL, tmp); 257 break; 258 case RADEON_HPD_4: 259 tmp = RREG32(DC_HPD4_INT_CONTROL); 260 if (connected) 261 tmp &= ~DC_HPDx_INT_POLARITY; 262 else 263 tmp |= DC_HPDx_INT_POLARITY; 264 WREG32(DC_HPD4_INT_CONTROL, tmp); 265 break; 266 case RADEON_HPD_5: 267 tmp = RREG32(DC_HPD5_INT_CONTROL); 268 if (connected) 269 tmp &= ~DC_HPDx_INT_POLARITY; 270 else 271 tmp |= DC_HPDx_INT_POLARITY; 272 WREG32(DC_HPD5_INT_CONTROL, tmp); 273 break; 274 case RADEON_HPD_6: 275 tmp = RREG32(DC_HPD6_INT_CONTROL); 276 if (connected) 277 tmp &= ~DC_HPDx_INT_POLARITY; 278 else 279 tmp |= DC_HPDx_INT_POLARITY; 280 WREG32(DC_HPD6_INT_CONTROL, tmp); 281 break; 282 default: 283 break; 284 } 285 } 286 287 void evergreen_hpd_init(struct radeon_device *rdev) 288 { 289 struct drm_device *dev = rdev->ddev; 290 struct drm_connector *connector; 291 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | 292 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN; 293 294 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 295 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 296 switch (radeon_connector->hpd.hpd) { 297 case RADEON_HPD_1: 298 WREG32(DC_HPD1_CONTROL, tmp); 299 rdev->irq.hpd[0] = true; 300 break; 301 case RADEON_HPD_2: 302 WREG32(DC_HPD2_CONTROL, tmp); 303 rdev->irq.hpd[1] = true; 304 break; 305 case RADEON_HPD_3: 306 WREG32(DC_HPD3_CONTROL, tmp); 307 rdev->irq.hpd[2] = true; 308 break; 309 case RADEON_HPD_4: 310 WREG32(DC_HPD4_CONTROL, tmp); 311 rdev->irq.hpd[3] = true; 312 break; 313 case RADEON_HPD_5: 314 WREG32(DC_HPD5_CONTROL, tmp); 315 rdev->irq.hpd[4] = true; 316 break; 317 case RADEON_HPD_6: 318 WREG32(DC_HPD6_CONTROL, tmp); 319 rdev->irq.hpd[5] = true; 320 break; 321 default: 322 break; 323 } 324 } 325 if (rdev->irq.installed) 326 evergreen_irq_set(rdev); 327 } 328 329 void evergreen_hpd_fini(struct radeon_device *rdev) 330 { 331 struct drm_device *dev = rdev->ddev; 332 struct drm_connector *connector; 333 334 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 335 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 336 switch (radeon_connector->hpd.hpd) { 337 case RADEON_HPD_1: 338 WREG32(DC_HPD1_CONTROL, 0); 339 rdev->irq.hpd[0] = false; 340 break; 341 case RADEON_HPD_2: 342 WREG32(DC_HPD2_CONTROL, 0); 343 rdev->irq.hpd[1] = false; 344 break; 345 case RADEON_HPD_3: 346 WREG32(DC_HPD3_CONTROL, 0); 347 rdev->irq.hpd[2] = false; 348 break; 349 case RADEON_HPD_4: 350 WREG32(DC_HPD4_CONTROL, 0); 351 rdev->irq.hpd[3] = false; 352 break; 353 case RADEON_HPD_5: 354 WREG32(DC_HPD5_CONTROL, 0); 355 rdev->irq.hpd[4] = false; 356 break; 357 case RADEON_HPD_6: 358 WREG32(DC_HPD6_CONTROL, 0); 359 rdev->irq.hpd[5] = false; 360 break; 361 default: 362 break; 363 } 364 } 365 } 366 367 /* watermark setup */ 368 369 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, 370 struct radeon_crtc *radeon_crtc, 371 struct drm_display_mode *mode, 372 struct drm_display_mode *other_mode) 373 { 374 u32 tmp; 375 /* 376 * Line Buffer Setup 377 * There are 3 line buffers, each one shared by 2 display controllers. 378 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 379 * the display controllers. The paritioning is done via one of four 380 * preset allocations specified in bits 2:0: 381 * first display controller 382 * 0 - first half of lb (3840 * 2) 383 * 1 - first 3/4 of lb (5760 * 2) 384 * 2 - whole lb (7680 * 2), other crtc must be disabled 385 * 3 - first 1/4 of lb (1920 * 2) 386 * second display controller 387 * 4 - second half of lb (3840 * 2) 388 * 5 - second 3/4 of lb (5760 * 2) 389 * 6 - whole lb (7680 * 2), other crtc must be disabled 390 * 7 - last 1/4 of lb (1920 * 2) 391 */ 392 /* this can get tricky if we have two large displays on a paired group 393 * of crtcs. Ideally for multiple large displays we'd assign them to 394 * non-linked crtcs for maximum line buffer allocation. 395 */ 396 if (radeon_crtc->base.enabled && mode) { 397 if (other_mode) 398 tmp = 0; /* 1/2 */ 399 else 400 tmp = 2; /* whole */ 401 } else 402 tmp = 0; 403 404 /* second controller of the pair uses second half of the lb */ 405 if (radeon_crtc->crtc_id % 2) 406 tmp += 4; 407 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); 408 409 if (radeon_crtc->base.enabled && mode) { 410 switch (tmp) { 411 case 0: 412 case 4: 413 default: 414 if (ASIC_IS_DCE5(rdev)) 415 return 4096 * 2; 416 else 417 return 3840 * 2; 418 case 1: 419 case 5: 420 if (ASIC_IS_DCE5(rdev)) 421 return 6144 * 2; 422 else 423 return 5760 * 2; 424 case 2: 425 case 6: 426 if (ASIC_IS_DCE5(rdev)) 427 return 8192 * 2; 428 else 429 return 7680 * 2; 430 case 3: 431 case 7: 432 if (ASIC_IS_DCE5(rdev)) 433 return 2048 * 2; 434 else 435 return 1920 * 2; 436 } 437 } 438 439 /* controller not enabled, so no lb used */ 440 return 0; 441 } 442 443 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev) 444 { 445 u32 tmp = RREG32(MC_SHARED_CHMAP); 446 447 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 448 case 0: 449 default: 450 return 1; 451 case 1: 452 return 2; 453 case 2: 454 return 4; 455 case 3: 456 return 8; 457 } 458 } 459 460 struct evergreen_wm_params { 461 u32 dram_channels; /* number of dram channels */ 462 u32 yclk; /* bandwidth per dram data pin in kHz */ 463 u32 sclk; /* engine clock in kHz */ 464 u32 disp_clk; /* display clock in kHz */ 465 u32 src_width; /* viewport width */ 466 u32 active_time; /* active display time in ns */ 467 u32 blank_time; /* blank time in ns */ 468 bool interlaced; /* mode is interlaced */ 469 fixed20_12 vsc; /* vertical scale ratio */ 470 u32 num_heads; /* number of active crtcs */ 471 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 472 u32 lb_size; /* line buffer allocated to pipe */ 473 u32 vtaps; /* vertical scaler taps */ 474 }; 475 476 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm) 477 { 478 /* Calculate DRAM Bandwidth and the part allocated to display. */ 479 fixed20_12 dram_efficiency; /* 0.7 */ 480 fixed20_12 yclk, dram_channels, bandwidth; 481 fixed20_12 a; 482 483 a.full = dfixed_const(1000); 484 yclk.full = dfixed_const(wm->yclk); 485 yclk.full = dfixed_div(yclk, a); 486 dram_channels.full = dfixed_const(wm->dram_channels * 4); 487 a.full = dfixed_const(10); 488 dram_efficiency.full = dfixed_const(7); 489 dram_efficiency.full = dfixed_div(dram_efficiency, a); 490 bandwidth.full = dfixed_mul(dram_channels, yclk); 491 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 492 493 return dfixed_trunc(bandwidth); 494 } 495 496 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm) 497 { 498 /* Calculate DRAM Bandwidth and the part allocated to display. */ 499 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 500 fixed20_12 yclk, dram_channels, bandwidth; 501 fixed20_12 a; 502 503 a.full = dfixed_const(1000); 504 yclk.full = dfixed_const(wm->yclk); 505 yclk.full = dfixed_div(yclk, a); 506 dram_channels.full = dfixed_const(wm->dram_channels * 4); 507 a.full = dfixed_const(10); 508 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 509 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 510 bandwidth.full = dfixed_mul(dram_channels, yclk); 511 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 512 513 return dfixed_trunc(bandwidth); 514 } 515 516 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm) 517 { 518 /* Calculate the display Data return Bandwidth */ 519 fixed20_12 return_efficiency; /* 0.8 */ 520 fixed20_12 sclk, bandwidth; 521 fixed20_12 a; 522 523 a.full = dfixed_const(1000); 524 sclk.full = dfixed_const(wm->sclk); 525 sclk.full = dfixed_div(sclk, a); 526 a.full = dfixed_const(10); 527 return_efficiency.full = dfixed_const(8); 528 return_efficiency.full = dfixed_div(return_efficiency, a); 529 a.full = dfixed_const(32); 530 bandwidth.full = dfixed_mul(a, sclk); 531 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 532 533 return dfixed_trunc(bandwidth); 534 } 535 536 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm) 537 { 538 /* Calculate the DMIF Request Bandwidth */ 539 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 540 fixed20_12 disp_clk, bandwidth; 541 fixed20_12 a; 542 543 a.full = dfixed_const(1000); 544 disp_clk.full = dfixed_const(wm->disp_clk); 545 disp_clk.full = dfixed_div(disp_clk, a); 546 a.full = dfixed_const(10); 547 disp_clk_request_efficiency.full = dfixed_const(8); 548 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 549 a.full = dfixed_const(32); 550 bandwidth.full = dfixed_mul(a, disp_clk); 551 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency); 552 553 return dfixed_trunc(bandwidth); 554 } 555 556 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm) 557 { 558 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 559 u32 dram_bandwidth = evergreen_dram_bandwidth(wm); 560 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm); 561 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm); 562 563 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 564 } 565 566 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm) 567 { 568 /* Calculate the display mode Average Bandwidth 569 * DisplayMode should contain the source and destination dimensions, 570 * timing, etc. 571 */ 572 fixed20_12 bpp; 573 fixed20_12 line_time; 574 fixed20_12 src_width; 575 fixed20_12 bandwidth; 576 fixed20_12 a; 577 578 a.full = dfixed_const(1000); 579 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 580 line_time.full = dfixed_div(line_time, a); 581 bpp.full = dfixed_const(wm->bytes_per_pixel); 582 src_width.full = dfixed_const(wm->src_width); 583 bandwidth.full = dfixed_mul(src_width, bpp); 584 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 585 bandwidth.full = dfixed_div(bandwidth, line_time); 586 587 return dfixed_trunc(bandwidth); 588 } 589 590 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm) 591 { 592 /* First calcualte the latency in ns */ 593 u32 mc_latency = 2000; /* 2000 ns. */ 594 u32 available_bandwidth = evergreen_available_bandwidth(wm); 595 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 596 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 597 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 598 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 599 (wm->num_heads * cursor_line_pair_return_time); 600 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 601 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 602 fixed20_12 a, b, c; 603 604 if (wm->num_heads == 0) 605 return 0; 606 607 a.full = dfixed_const(2); 608 b.full = dfixed_const(1); 609 if ((wm->vsc.full > a.full) || 610 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 611 (wm->vtaps >= 5) || 612 ((wm->vsc.full >= a.full) && wm->interlaced)) 613 max_src_lines_per_dst_line = 4; 614 else 615 max_src_lines_per_dst_line = 2; 616 617 a.full = dfixed_const(available_bandwidth); 618 b.full = dfixed_const(wm->num_heads); 619 a.full = dfixed_div(a, b); 620 621 b.full = dfixed_const(1000); 622 c.full = dfixed_const(wm->disp_clk); 623 b.full = dfixed_div(c, b); 624 c.full = dfixed_const(wm->bytes_per_pixel); 625 b.full = dfixed_mul(b, c); 626 627 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b)); 628 629 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 630 b.full = dfixed_const(1000); 631 c.full = dfixed_const(lb_fill_bw); 632 b.full = dfixed_div(c, b); 633 a.full = dfixed_div(a, b); 634 line_fill_time = dfixed_trunc(a); 635 636 if (line_fill_time < wm->active_time) 637 return latency; 638 else 639 return latency + (line_fill_time - wm->active_time); 640 641 } 642 643 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm) 644 { 645 if (evergreen_average_bandwidth(wm) <= 646 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads)) 647 return true; 648 else 649 return false; 650 }; 651 652 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm) 653 { 654 if (evergreen_average_bandwidth(wm) <= 655 (evergreen_available_bandwidth(wm) / wm->num_heads)) 656 return true; 657 else 658 return false; 659 }; 660 661 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm) 662 { 663 u32 lb_partitions = wm->lb_size / wm->src_width; 664 u32 line_time = wm->active_time + wm->blank_time; 665 u32 latency_tolerant_lines; 666 u32 latency_hiding; 667 fixed20_12 a; 668 669 a.full = dfixed_const(1); 670 if (wm->vsc.full > a.full) 671 latency_tolerant_lines = 1; 672 else { 673 if (lb_partitions <= (wm->vtaps + 1)) 674 latency_tolerant_lines = 1; 675 else 676 latency_tolerant_lines = 2; 677 } 678 679 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 680 681 if (evergreen_latency_watermark(wm) <= latency_hiding) 682 return true; 683 else 684 return false; 685 } 686 687 static void evergreen_program_watermarks(struct radeon_device *rdev, 688 struct radeon_crtc *radeon_crtc, 689 u32 lb_size, u32 num_heads) 690 { 691 struct drm_display_mode *mode = &radeon_crtc->base.mode; 692 struct evergreen_wm_params wm; 693 u32 pixel_period; 694 u32 line_time = 0; 695 u32 latency_watermark_a = 0, latency_watermark_b = 0; 696 u32 priority_a_mark = 0, priority_b_mark = 0; 697 u32 priority_a_cnt = PRIORITY_OFF; 698 u32 priority_b_cnt = PRIORITY_OFF; 699 u32 pipe_offset = radeon_crtc->crtc_id * 16; 700 u32 tmp, arb_control3; 701 fixed20_12 a, b, c; 702 703 if (radeon_crtc->base.enabled && num_heads && mode) { 704 pixel_period = 1000000 / (u32)mode->clock; 705 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 706 priority_a_cnt = 0; 707 priority_b_cnt = 0; 708 709 wm.yclk = rdev->pm.current_mclk * 10; 710 wm.sclk = rdev->pm.current_sclk * 10; 711 wm.disp_clk = mode->clock; 712 wm.src_width = mode->crtc_hdisplay; 713 wm.active_time = mode->crtc_hdisplay * pixel_period; 714 wm.blank_time = line_time - wm.active_time; 715 wm.interlaced = false; 716 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 717 wm.interlaced = true; 718 wm.vsc = radeon_crtc->vsc; 719 wm.vtaps = 1; 720 if (radeon_crtc->rmx_type != RMX_OFF) 721 wm.vtaps = 2; 722 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */ 723 wm.lb_size = lb_size; 724 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev); 725 wm.num_heads = num_heads; 726 727 /* set for high clocks */ 728 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535); 729 /* set for low clocks */ 730 /* wm.yclk = low clk; wm.sclk = low clk */ 731 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535); 732 733 /* possibly force display priority to high */ 734 /* should really do this at mode validation time... */ 735 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) || 736 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) || 737 !evergreen_check_latency_hiding(&wm) || 738 (rdev->disp_priority == 2)) { 739 DRM_INFO("force priority to high\n"); 740 priority_a_cnt |= PRIORITY_ALWAYS_ON; 741 priority_b_cnt |= PRIORITY_ALWAYS_ON; 742 } 743 744 a.full = dfixed_const(1000); 745 b.full = dfixed_const(mode->clock); 746 b.full = dfixed_div(b, a); 747 c.full = dfixed_const(latency_watermark_a); 748 c.full = dfixed_mul(c, b); 749 c.full = dfixed_mul(c, radeon_crtc->hsc); 750 c.full = dfixed_div(c, a); 751 a.full = dfixed_const(16); 752 c.full = dfixed_div(c, a); 753 priority_a_mark = dfixed_trunc(c); 754 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 755 756 a.full = dfixed_const(1000); 757 b.full = dfixed_const(mode->clock); 758 b.full = dfixed_div(b, a); 759 c.full = dfixed_const(latency_watermark_b); 760 c.full = dfixed_mul(c, b); 761 c.full = dfixed_mul(c, radeon_crtc->hsc); 762 c.full = dfixed_div(c, a); 763 a.full = dfixed_const(16); 764 c.full = dfixed_div(c, a); 765 priority_b_mark = dfixed_trunc(c); 766 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 767 } 768 769 /* select wm A */ 770 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); 771 tmp = arb_control3; 772 tmp &= ~LATENCY_WATERMARK_MASK(3); 773 tmp |= LATENCY_WATERMARK_MASK(1); 774 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); 775 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, 776 (LATENCY_LOW_WATERMARK(latency_watermark_a) | 777 LATENCY_HIGH_WATERMARK(line_time))); 778 /* select wm B */ 779 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); 780 tmp &= ~LATENCY_WATERMARK_MASK(3); 781 tmp |= LATENCY_WATERMARK_MASK(2); 782 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); 783 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, 784 (LATENCY_LOW_WATERMARK(latency_watermark_b) | 785 LATENCY_HIGH_WATERMARK(line_time))); 786 /* restore original selection */ 787 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3); 788 789 /* write the priority marks */ 790 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); 791 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); 792 793 } 794 795 void evergreen_bandwidth_update(struct radeon_device *rdev) 796 { 797 struct drm_display_mode *mode0 = NULL; 798 struct drm_display_mode *mode1 = NULL; 799 u32 num_heads = 0, lb_size; 800 int i; 801 802 radeon_update_display_priority(rdev); 803 804 for (i = 0; i < rdev->num_crtc; i++) { 805 if (rdev->mode_info.crtcs[i]->base.enabled) 806 num_heads++; 807 } 808 for (i = 0; i < rdev->num_crtc; i += 2) { 809 mode0 = &rdev->mode_info.crtcs[i]->base.mode; 810 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; 811 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); 812 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); 813 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); 814 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); 815 } 816 } 817 818 int evergreen_mc_wait_for_idle(struct radeon_device *rdev) 819 { 820 unsigned i; 821 u32 tmp; 822 823 for (i = 0; i < rdev->usec_timeout; i++) { 824 /* read MC_STATUS */ 825 tmp = RREG32(SRBM_STATUS) & 0x1F00; 826 if (!tmp) 827 return 0; 828 udelay(1); 829 } 830 return -1; 831 } 832 833 /* 834 * GART 835 */ 836 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev) 837 { 838 unsigned i; 839 u32 tmp; 840 841 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 842 843 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 844 for (i = 0; i < rdev->usec_timeout; i++) { 845 /* read MC_STATUS */ 846 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 847 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 848 if (tmp == 2) { 849 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 850 return; 851 } 852 if (tmp) { 853 return; 854 } 855 udelay(1); 856 } 857 } 858 859 int evergreen_pcie_gart_enable(struct radeon_device *rdev) 860 { 861 u32 tmp; 862 int r; 863 864 if (rdev->gart.table.vram.robj == NULL) { 865 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 866 return -EINVAL; 867 } 868 r = radeon_gart_table_vram_pin(rdev); 869 if (r) 870 return r; 871 radeon_gart_restore(rdev); 872 /* Setup L2 cache */ 873 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 874 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 875 EFFECTIVE_L2_QUEUE_SIZE(7)); 876 WREG32(VM_L2_CNTL2, 0); 877 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 878 /* Setup TLB control */ 879 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 880 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 881 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 882 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 883 if (rdev->flags & RADEON_IS_IGP) { 884 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp); 885 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp); 886 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp); 887 } else { 888 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 889 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 890 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 891 } 892 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 893 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 894 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 895 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 896 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 897 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 898 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 899 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 900 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 901 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 902 (u32)(rdev->dummy_page.addr >> 12)); 903 WREG32(VM_CONTEXT1_CNTL, 0); 904 905 evergreen_pcie_gart_tlb_flush(rdev); 906 rdev->gart.ready = true; 907 return 0; 908 } 909 910 void evergreen_pcie_gart_disable(struct radeon_device *rdev) 911 { 912 u32 tmp; 913 int r; 914 915 /* Disable all tables */ 916 WREG32(VM_CONTEXT0_CNTL, 0); 917 WREG32(VM_CONTEXT1_CNTL, 0); 918 919 /* Setup L2 cache */ 920 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 921 EFFECTIVE_L2_QUEUE_SIZE(7)); 922 WREG32(VM_L2_CNTL2, 0); 923 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 924 /* Setup TLB control */ 925 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 926 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 927 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 928 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 929 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 930 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 931 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 932 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 933 if (rdev->gart.table.vram.robj) { 934 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); 935 if (likely(r == 0)) { 936 radeon_bo_kunmap(rdev->gart.table.vram.robj); 937 radeon_bo_unpin(rdev->gart.table.vram.robj); 938 radeon_bo_unreserve(rdev->gart.table.vram.robj); 939 } 940 } 941 } 942 943 void evergreen_pcie_gart_fini(struct radeon_device *rdev) 944 { 945 evergreen_pcie_gart_disable(rdev); 946 radeon_gart_table_vram_free(rdev); 947 radeon_gart_fini(rdev); 948 } 949 950 951 void evergreen_agp_enable(struct radeon_device *rdev) 952 { 953 u32 tmp; 954 955 /* Setup L2 cache */ 956 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 957 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 958 EFFECTIVE_L2_QUEUE_SIZE(7)); 959 WREG32(VM_L2_CNTL2, 0); 960 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 961 /* Setup TLB control */ 962 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 963 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 964 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 965 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 966 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 967 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 968 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 969 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 970 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 971 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 972 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 973 WREG32(VM_CONTEXT0_CNTL, 0); 974 WREG32(VM_CONTEXT1_CNTL, 0); 975 } 976 977 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) 978 { 979 save->vga_control[0] = RREG32(D1VGA_CONTROL); 980 save->vga_control[1] = RREG32(D2VGA_CONTROL); 981 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL); 982 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL); 983 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL); 984 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL); 985 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 986 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 987 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 988 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 989 if (!(rdev->flags & RADEON_IS_IGP)) { 990 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 991 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 992 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 993 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 994 } 995 996 /* Stop all video */ 997 WREG32(VGA_RENDER_CONTROL, 0); 998 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 999 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1000 if (!(rdev->flags & RADEON_IS_IGP)) { 1001 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1002 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1003 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1004 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1005 } 1006 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1007 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1008 if (!(rdev->flags & RADEON_IS_IGP)) { 1009 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1010 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1011 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1012 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1013 } 1014 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1015 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1016 if (!(rdev->flags & RADEON_IS_IGP)) { 1017 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1018 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1019 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1020 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1021 } 1022 1023 WREG32(D1VGA_CONTROL, 0); 1024 WREG32(D2VGA_CONTROL, 0); 1025 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1026 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1027 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1028 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1029 } 1030 1031 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) 1032 { 1033 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, 1034 upper_32_bits(rdev->mc.vram_start)); 1035 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, 1036 upper_32_bits(rdev->mc.vram_start)); 1037 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, 1038 (u32)rdev->mc.vram_start); 1039 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, 1040 (u32)rdev->mc.vram_start); 1041 1042 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, 1043 upper_32_bits(rdev->mc.vram_start)); 1044 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, 1045 upper_32_bits(rdev->mc.vram_start)); 1046 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, 1047 (u32)rdev->mc.vram_start); 1048 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, 1049 (u32)rdev->mc.vram_start); 1050 1051 if (!(rdev->flags & RADEON_IS_IGP)) { 1052 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1053 upper_32_bits(rdev->mc.vram_start)); 1054 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1055 upper_32_bits(rdev->mc.vram_start)); 1056 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, 1057 (u32)rdev->mc.vram_start); 1058 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, 1059 (u32)rdev->mc.vram_start); 1060 1061 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, 1062 upper_32_bits(rdev->mc.vram_start)); 1063 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, 1064 upper_32_bits(rdev->mc.vram_start)); 1065 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1066 (u32)rdev->mc.vram_start); 1067 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1068 (u32)rdev->mc.vram_start); 1069 1070 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1071 upper_32_bits(rdev->mc.vram_start)); 1072 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1073 upper_32_bits(rdev->mc.vram_start)); 1074 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, 1075 (u32)rdev->mc.vram_start); 1076 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, 1077 (u32)rdev->mc.vram_start); 1078 1079 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, 1080 upper_32_bits(rdev->mc.vram_start)); 1081 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, 1082 upper_32_bits(rdev->mc.vram_start)); 1083 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, 1084 (u32)rdev->mc.vram_start); 1085 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, 1086 (u32)rdev->mc.vram_start); 1087 } 1088 1089 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); 1090 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 1091 /* Unlock host access */ 1092 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); 1093 mdelay(1); 1094 /* Restore video state */ 1095 WREG32(D1VGA_CONTROL, save->vga_control[0]); 1096 WREG32(D2VGA_CONTROL, save->vga_control[1]); 1097 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); 1098 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); 1099 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); 1100 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); 1101 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1102 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1103 if (!(rdev->flags & RADEON_IS_IGP)) { 1104 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1105 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1106 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1107 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1108 } 1109 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); 1110 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); 1111 if (!(rdev->flags & RADEON_IS_IGP)) { 1112 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); 1113 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); 1114 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); 1115 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); 1116 } 1117 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1118 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1119 if (!(rdev->flags & RADEON_IS_IGP)) { 1120 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1121 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1122 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1123 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1124 } 1125 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); 1126 } 1127 1128 void evergreen_mc_program(struct radeon_device *rdev) 1129 { 1130 struct evergreen_mc_save save; 1131 u32 tmp; 1132 int i, j; 1133 1134 /* Initialize HDP */ 1135 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1136 WREG32((0x2c14 + j), 0x00000000); 1137 WREG32((0x2c18 + j), 0x00000000); 1138 WREG32((0x2c1c + j), 0x00000000); 1139 WREG32((0x2c20 + j), 0x00000000); 1140 WREG32((0x2c24 + j), 0x00000000); 1141 } 1142 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1143 1144 evergreen_mc_stop(rdev, &save); 1145 if (evergreen_mc_wait_for_idle(rdev)) { 1146 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1147 } 1148 /* Lockout access through VGA aperture*/ 1149 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1150 /* Update configuration */ 1151 if (rdev->flags & RADEON_IS_AGP) { 1152 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1153 /* VRAM before AGP */ 1154 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1155 rdev->mc.vram_start >> 12); 1156 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1157 rdev->mc.gtt_end >> 12); 1158 } else { 1159 /* VRAM after AGP */ 1160 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1161 rdev->mc.gtt_start >> 12); 1162 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1163 rdev->mc.vram_end >> 12); 1164 } 1165 } else { 1166 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1167 rdev->mc.vram_start >> 12); 1168 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1169 rdev->mc.vram_end >> 12); 1170 } 1171 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 1172 if (rdev->flags & RADEON_IS_IGP) { 1173 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; 1174 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24; 1175 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; 1176 WREG32(MC_FUS_VM_FB_OFFSET, tmp); 1177 } 1178 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1179 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1180 WREG32(MC_VM_FB_LOCATION, tmp); 1181 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1182 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 1183 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1184 if (rdev->flags & RADEON_IS_AGP) { 1185 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 1186 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 1187 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1188 } else { 1189 WREG32(MC_VM_AGP_BASE, 0); 1190 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1191 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1192 } 1193 if (evergreen_mc_wait_for_idle(rdev)) { 1194 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1195 } 1196 evergreen_mc_resume(rdev, &save); 1197 /* we need to own VRAM, so turn off the VGA renderer here 1198 * to stop it overwriting our objects */ 1199 rv515_vga_render_disable(rdev); 1200 } 1201 1202 /* 1203 * CP. 1204 */ 1205 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1206 { 1207 /* set to DX10/11 mode */ 1208 radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0)); 1209 radeon_ring_write(rdev, 1); 1210 /* FIXME: implement */ 1211 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 1212 radeon_ring_write(rdev, 1213 #ifdef __BIG_ENDIAN 1214 (2 << 0) | 1215 #endif 1216 (ib->gpu_addr & 0xFFFFFFFC)); 1217 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); 1218 radeon_ring_write(rdev, ib->length_dw); 1219 } 1220 1221 1222 static int evergreen_cp_load_microcode(struct radeon_device *rdev) 1223 { 1224 const __be32 *fw_data; 1225 int i; 1226 1227 if (!rdev->me_fw || !rdev->pfp_fw) 1228 return -EINVAL; 1229 1230 r700_cp_stop(rdev); 1231 WREG32(CP_RB_CNTL, 1232 #ifdef __BIG_ENDIAN 1233 BUF_SWAP_32BIT | 1234 #endif 1235 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 1236 1237 fw_data = (const __be32 *)rdev->pfp_fw->data; 1238 WREG32(CP_PFP_UCODE_ADDR, 0); 1239 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++) 1240 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1241 WREG32(CP_PFP_UCODE_ADDR, 0); 1242 1243 fw_data = (const __be32 *)rdev->me_fw->data; 1244 WREG32(CP_ME_RAM_WADDR, 0); 1245 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++) 1246 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1247 1248 WREG32(CP_PFP_UCODE_ADDR, 0); 1249 WREG32(CP_ME_RAM_WADDR, 0); 1250 WREG32(CP_ME_RAM_RADDR, 0); 1251 return 0; 1252 } 1253 1254 static int evergreen_cp_start(struct radeon_device *rdev) 1255 { 1256 int r, i; 1257 uint32_t cp_me; 1258 1259 r = radeon_ring_lock(rdev, 7); 1260 if (r) { 1261 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1262 return r; 1263 } 1264 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1265 radeon_ring_write(rdev, 0x1); 1266 radeon_ring_write(rdev, 0x0); 1267 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1); 1268 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1269 radeon_ring_write(rdev, 0); 1270 radeon_ring_write(rdev, 0); 1271 radeon_ring_unlock_commit(rdev); 1272 1273 cp_me = 0xff; 1274 WREG32(CP_ME_CNTL, cp_me); 1275 1276 r = radeon_ring_lock(rdev, evergreen_default_size + 19); 1277 if (r) { 1278 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1279 return r; 1280 } 1281 1282 /* setup clear context state */ 1283 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1284 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1285 1286 for (i = 0; i < evergreen_default_size; i++) 1287 radeon_ring_write(rdev, evergreen_default_state[i]); 1288 1289 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1290 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE); 1291 1292 /* set clear context state */ 1293 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); 1294 radeon_ring_write(rdev, 0); 1295 1296 /* SQ_VTX_BASE_VTX_LOC */ 1297 radeon_ring_write(rdev, 0xc0026f00); 1298 radeon_ring_write(rdev, 0x00000000); 1299 radeon_ring_write(rdev, 0x00000000); 1300 radeon_ring_write(rdev, 0x00000000); 1301 1302 /* Clear consts */ 1303 radeon_ring_write(rdev, 0xc0036f00); 1304 radeon_ring_write(rdev, 0x00000bc4); 1305 radeon_ring_write(rdev, 0xffffffff); 1306 radeon_ring_write(rdev, 0xffffffff); 1307 radeon_ring_write(rdev, 0xffffffff); 1308 1309 radeon_ring_write(rdev, 0xc0026900); 1310 radeon_ring_write(rdev, 0x00000316); 1311 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 1312 radeon_ring_write(rdev, 0x00000010); /* */ 1313 1314 radeon_ring_unlock_commit(rdev); 1315 1316 return 0; 1317 } 1318 1319 int evergreen_cp_resume(struct radeon_device *rdev) 1320 { 1321 u32 tmp; 1322 u32 rb_bufsz; 1323 int r; 1324 1325 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ 1326 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | 1327 SOFT_RESET_PA | 1328 SOFT_RESET_SH | 1329 SOFT_RESET_VGT | 1330 SOFT_RESET_SX)); 1331 RREG32(GRBM_SOFT_RESET); 1332 mdelay(15); 1333 WREG32(GRBM_SOFT_RESET, 0); 1334 RREG32(GRBM_SOFT_RESET); 1335 1336 /* Set ring buffer size */ 1337 rb_bufsz = drm_order(rdev->cp.ring_size / 8); 1338 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1339 #ifdef __BIG_ENDIAN 1340 tmp |= BUF_SWAP_32BIT; 1341 #endif 1342 WREG32(CP_RB_CNTL, tmp); 1343 WREG32(CP_SEM_WAIT_TIMER, 0x4); 1344 1345 /* Set the write pointer delay */ 1346 WREG32(CP_RB_WPTR_DELAY, 0); 1347 1348 /* Initialize the ring buffer's read and write pointers */ 1349 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 1350 WREG32(CP_RB_RPTR_WR, 0); 1351 WREG32(CP_RB_WPTR, 0); 1352 1353 /* set the wb address wether it's enabled or not */ 1354 WREG32(CP_RB_RPTR_ADDR, 1355 #ifdef __BIG_ENDIAN 1356 RB_RPTR_SWAP(2) | 1357 #endif 1358 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 1359 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 1360 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 1361 1362 if (rdev->wb.enabled) 1363 WREG32(SCRATCH_UMSK, 0xff); 1364 else { 1365 tmp |= RB_NO_UPDATE; 1366 WREG32(SCRATCH_UMSK, 0); 1367 } 1368 1369 mdelay(1); 1370 WREG32(CP_RB_CNTL, tmp); 1371 1372 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); 1373 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 1374 1375 rdev->cp.rptr = RREG32(CP_RB_RPTR); 1376 rdev->cp.wptr = RREG32(CP_RB_WPTR); 1377 1378 evergreen_cp_start(rdev); 1379 rdev->cp.ready = true; 1380 r = radeon_ring_test(rdev); 1381 if (r) { 1382 rdev->cp.ready = false; 1383 return r; 1384 } 1385 return 0; 1386 } 1387 1388 /* 1389 * Core functions 1390 */ 1391 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 1392 u32 num_tile_pipes, 1393 u32 num_backends, 1394 u32 backend_disable_mask) 1395 { 1396 u32 backend_map = 0; 1397 u32 enabled_backends_mask = 0; 1398 u32 enabled_backends_count = 0; 1399 u32 cur_pipe; 1400 u32 swizzle_pipe[EVERGREEN_MAX_PIPES]; 1401 u32 cur_backend = 0; 1402 u32 i; 1403 bool force_no_swizzle; 1404 1405 if (num_tile_pipes > EVERGREEN_MAX_PIPES) 1406 num_tile_pipes = EVERGREEN_MAX_PIPES; 1407 if (num_tile_pipes < 1) 1408 num_tile_pipes = 1; 1409 if (num_backends > EVERGREEN_MAX_BACKENDS) 1410 num_backends = EVERGREEN_MAX_BACKENDS; 1411 if (num_backends < 1) 1412 num_backends = 1; 1413 1414 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) { 1415 if (((backend_disable_mask >> i) & 1) == 0) { 1416 enabled_backends_mask |= (1 << i); 1417 ++enabled_backends_count; 1418 } 1419 if (enabled_backends_count == num_backends) 1420 break; 1421 } 1422 1423 if (enabled_backends_count == 0) { 1424 enabled_backends_mask = 1; 1425 enabled_backends_count = 1; 1426 } 1427 1428 if (enabled_backends_count != num_backends) 1429 num_backends = enabled_backends_count; 1430 1431 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES); 1432 switch (rdev->family) { 1433 case CHIP_CEDAR: 1434 case CHIP_REDWOOD: 1435 case CHIP_PALM: 1436 case CHIP_SUMO: 1437 case CHIP_SUMO2: 1438 case CHIP_TURKS: 1439 case CHIP_CAICOS: 1440 force_no_swizzle = false; 1441 break; 1442 case CHIP_CYPRESS: 1443 case CHIP_HEMLOCK: 1444 case CHIP_JUNIPER: 1445 case CHIP_BARTS: 1446 default: 1447 force_no_swizzle = true; 1448 break; 1449 } 1450 if (force_no_swizzle) { 1451 bool last_backend_enabled = false; 1452 1453 force_no_swizzle = false; 1454 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) { 1455 if (((enabled_backends_mask >> i) & 1) == 1) { 1456 if (last_backend_enabled) 1457 force_no_swizzle = true; 1458 last_backend_enabled = true; 1459 } else 1460 last_backend_enabled = false; 1461 } 1462 } 1463 1464 switch (num_tile_pipes) { 1465 case 1: 1466 case 3: 1467 case 5: 1468 case 7: 1469 DRM_ERROR("odd number of pipes!\n"); 1470 break; 1471 case 2: 1472 swizzle_pipe[0] = 0; 1473 swizzle_pipe[1] = 1; 1474 break; 1475 case 4: 1476 if (force_no_swizzle) { 1477 swizzle_pipe[0] = 0; 1478 swizzle_pipe[1] = 1; 1479 swizzle_pipe[2] = 2; 1480 swizzle_pipe[3] = 3; 1481 } else { 1482 swizzle_pipe[0] = 0; 1483 swizzle_pipe[1] = 2; 1484 swizzle_pipe[2] = 1; 1485 swizzle_pipe[3] = 3; 1486 } 1487 break; 1488 case 6: 1489 if (force_no_swizzle) { 1490 swizzle_pipe[0] = 0; 1491 swizzle_pipe[1] = 1; 1492 swizzle_pipe[2] = 2; 1493 swizzle_pipe[3] = 3; 1494 swizzle_pipe[4] = 4; 1495 swizzle_pipe[5] = 5; 1496 } else { 1497 swizzle_pipe[0] = 0; 1498 swizzle_pipe[1] = 2; 1499 swizzle_pipe[2] = 4; 1500 swizzle_pipe[3] = 1; 1501 swizzle_pipe[4] = 3; 1502 swizzle_pipe[5] = 5; 1503 } 1504 break; 1505 case 8: 1506 if (force_no_swizzle) { 1507 swizzle_pipe[0] = 0; 1508 swizzle_pipe[1] = 1; 1509 swizzle_pipe[2] = 2; 1510 swizzle_pipe[3] = 3; 1511 swizzle_pipe[4] = 4; 1512 swizzle_pipe[5] = 5; 1513 swizzle_pipe[6] = 6; 1514 swizzle_pipe[7] = 7; 1515 } else { 1516 swizzle_pipe[0] = 0; 1517 swizzle_pipe[1] = 2; 1518 swizzle_pipe[2] = 4; 1519 swizzle_pipe[3] = 6; 1520 swizzle_pipe[4] = 1; 1521 swizzle_pipe[5] = 3; 1522 swizzle_pipe[6] = 5; 1523 swizzle_pipe[7] = 7; 1524 } 1525 break; 1526 } 1527 1528 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1529 while (((1 << cur_backend) & enabled_backends_mask) == 0) 1530 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS; 1531 1532 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4))); 1533 1534 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS; 1535 } 1536 1537 return backend_map; 1538 } 1539 1540 static void evergreen_program_channel_remap(struct radeon_device *rdev) 1541 { 1542 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp; 1543 1544 tmp = RREG32(MC_SHARED_CHMAP); 1545 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1546 case 0: 1547 case 1: 1548 case 2: 1549 case 3: 1550 default: 1551 /* default mapping */ 1552 mc_shared_chremap = 0x00fac688; 1553 break; 1554 } 1555 1556 switch (rdev->family) { 1557 case CHIP_HEMLOCK: 1558 case CHIP_CYPRESS: 1559 case CHIP_BARTS: 1560 tcp_chan_steer_lo = 0x54763210; 1561 tcp_chan_steer_hi = 0x0000ba98; 1562 break; 1563 case CHIP_JUNIPER: 1564 case CHIP_REDWOOD: 1565 case CHIP_CEDAR: 1566 case CHIP_PALM: 1567 case CHIP_SUMO: 1568 case CHIP_SUMO2: 1569 case CHIP_TURKS: 1570 case CHIP_CAICOS: 1571 default: 1572 tcp_chan_steer_lo = 0x76543210; 1573 tcp_chan_steer_hi = 0x0000ba98; 1574 break; 1575 } 1576 1577 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo); 1578 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi); 1579 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); 1580 } 1581 1582 static void evergreen_gpu_init(struct radeon_device *rdev) 1583 { 1584 u32 cc_rb_backend_disable = 0; 1585 u32 cc_gc_shader_pipe_config; 1586 u32 gb_addr_config = 0; 1587 u32 mc_shared_chmap, mc_arb_ramcfg; 1588 u32 gb_backend_map; 1589 u32 grbm_gfx_index; 1590 u32 sx_debug_1; 1591 u32 smx_dc_ctl0; 1592 u32 sq_config; 1593 u32 sq_lds_resource_mgmt; 1594 u32 sq_gpr_resource_mgmt_1; 1595 u32 sq_gpr_resource_mgmt_2; 1596 u32 sq_gpr_resource_mgmt_3; 1597 u32 sq_thread_resource_mgmt; 1598 u32 sq_thread_resource_mgmt_2; 1599 u32 sq_stack_resource_mgmt_1; 1600 u32 sq_stack_resource_mgmt_2; 1601 u32 sq_stack_resource_mgmt_3; 1602 u32 vgt_cache_invalidation; 1603 u32 hdp_host_path_cntl, tmp; 1604 int i, j, num_shader_engines, ps_thread_count; 1605 1606 switch (rdev->family) { 1607 case CHIP_CYPRESS: 1608 case CHIP_HEMLOCK: 1609 rdev->config.evergreen.num_ses = 2; 1610 rdev->config.evergreen.max_pipes = 4; 1611 rdev->config.evergreen.max_tile_pipes = 8; 1612 rdev->config.evergreen.max_simds = 10; 1613 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; 1614 rdev->config.evergreen.max_gprs = 256; 1615 rdev->config.evergreen.max_threads = 248; 1616 rdev->config.evergreen.max_gs_threads = 32; 1617 rdev->config.evergreen.max_stack_entries = 512; 1618 rdev->config.evergreen.sx_num_of_sets = 4; 1619 rdev->config.evergreen.sx_max_export_size = 256; 1620 rdev->config.evergreen.sx_max_export_pos_size = 64; 1621 rdev->config.evergreen.sx_max_export_smx_size = 192; 1622 rdev->config.evergreen.max_hw_contexts = 8; 1623 rdev->config.evergreen.sq_num_cf_insts = 2; 1624 1625 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1626 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1627 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1628 break; 1629 case CHIP_JUNIPER: 1630 rdev->config.evergreen.num_ses = 1; 1631 rdev->config.evergreen.max_pipes = 4; 1632 rdev->config.evergreen.max_tile_pipes = 4; 1633 rdev->config.evergreen.max_simds = 10; 1634 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; 1635 rdev->config.evergreen.max_gprs = 256; 1636 rdev->config.evergreen.max_threads = 248; 1637 rdev->config.evergreen.max_gs_threads = 32; 1638 rdev->config.evergreen.max_stack_entries = 512; 1639 rdev->config.evergreen.sx_num_of_sets = 4; 1640 rdev->config.evergreen.sx_max_export_size = 256; 1641 rdev->config.evergreen.sx_max_export_pos_size = 64; 1642 rdev->config.evergreen.sx_max_export_smx_size = 192; 1643 rdev->config.evergreen.max_hw_contexts = 8; 1644 rdev->config.evergreen.sq_num_cf_insts = 2; 1645 1646 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1647 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1648 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1649 break; 1650 case CHIP_REDWOOD: 1651 rdev->config.evergreen.num_ses = 1; 1652 rdev->config.evergreen.max_pipes = 4; 1653 rdev->config.evergreen.max_tile_pipes = 4; 1654 rdev->config.evergreen.max_simds = 5; 1655 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; 1656 rdev->config.evergreen.max_gprs = 256; 1657 rdev->config.evergreen.max_threads = 248; 1658 rdev->config.evergreen.max_gs_threads = 32; 1659 rdev->config.evergreen.max_stack_entries = 256; 1660 rdev->config.evergreen.sx_num_of_sets = 4; 1661 rdev->config.evergreen.sx_max_export_size = 256; 1662 rdev->config.evergreen.sx_max_export_pos_size = 64; 1663 rdev->config.evergreen.sx_max_export_smx_size = 192; 1664 rdev->config.evergreen.max_hw_contexts = 8; 1665 rdev->config.evergreen.sq_num_cf_insts = 2; 1666 1667 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1668 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1669 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1670 break; 1671 case CHIP_CEDAR: 1672 default: 1673 rdev->config.evergreen.num_ses = 1; 1674 rdev->config.evergreen.max_pipes = 2; 1675 rdev->config.evergreen.max_tile_pipes = 2; 1676 rdev->config.evergreen.max_simds = 2; 1677 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1678 rdev->config.evergreen.max_gprs = 256; 1679 rdev->config.evergreen.max_threads = 192; 1680 rdev->config.evergreen.max_gs_threads = 16; 1681 rdev->config.evergreen.max_stack_entries = 256; 1682 rdev->config.evergreen.sx_num_of_sets = 4; 1683 rdev->config.evergreen.sx_max_export_size = 128; 1684 rdev->config.evergreen.sx_max_export_pos_size = 32; 1685 rdev->config.evergreen.sx_max_export_smx_size = 96; 1686 rdev->config.evergreen.max_hw_contexts = 4; 1687 rdev->config.evergreen.sq_num_cf_insts = 1; 1688 1689 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1690 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1691 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1692 break; 1693 case CHIP_PALM: 1694 rdev->config.evergreen.num_ses = 1; 1695 rdev->config.evergreen.max_pipes = 2; 1696 rdev->config.evergreen.max_tile_pipes = 2; 1697 rdev->config.evergreen.max_simds = 2; 1698 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1699 rdev->config.evergreen.max_gprs = 256; 1700 rdev->config.evergreen.max_threads = 192; 1701 rdev->config.evergreen.max_gs_threads = 16; 1702 rdev->config.evergreen.max_stack_entries = 256; 1703 rdev->config.evergreen.sx_num_of_sets = 4; 1704 rdev->config.evergreen.sx_max_export_size = 128; 1705 rdev->config.evergreen.sx_max_export_pos_size = 32; 1706 rdev->config.evergreen.sx_max_export_smx_size = 96; 1707 rdev->config.evergreen.max_hw_contexts = 4; 1708 rdev->config.evergreen.sq_num_cf_insts = 1; 1709 1710 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1711 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1712 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1713 break; 1714 case CHIP_SUMO: 1715 rdev->config.evergreen.num_ses = 1; 1716 rdev->config.evergreen.max_pipes = 4; 1717 rdev->config.evergreen.max_tile_pipes = 2; 1718 if (rdev->pdev->device == 0x9648) 1719 rdev->config.evergreen.max_simds = 3; 1720 else if ((rdev->pdev->device == 0x9647) || 1721 (rdev->pdev->device == 0x964a)) 1722 rdev->config.evergreen.max_simds = 4; 1723 else 1724 rdev->config.evergreen.max_simds = 5; 1725 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; 1726 rdev->config.evergreen.max_gprs = 256; 1727 rdev->config.evergreen.max_threads = 248; 1728 rdev->config.evergreen.max_gs_threads = 32; 1729 rdev->config.evergreen.max_stack_entries = 256; 1730 rdev->config.evergreen.sx_num_of_sets = 4; 1731 rdev->config.evergreen.sx_max_export_size = 256; 1732 rdev->config.evergreen.sx_max_export_pos_size = 64; 1733 rdev->config.evergreen.sx_max_export_smx_size = 192; 1734 rdev->config.evergreen.max_hw_contexts = 8; 1735 rdev->config.evergreen.sq_num_cf_insts = 2; 1736 1737 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1738 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1739 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1740 break; 1741 case CHIP_SUMO2: 1742 rdev->config.evergreen.num_ses = 1; 1743 rdev->config.evergreen.max_pipes = 4; 1744 rdev->config.evergreen.max_tile_pipes = 4; 1745 rdev->config.evergreen.max_simds = 2; 1746 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1747 rdev->config.evergreen.max_gprs = 256; 1748 rdev->config.evergreen.max_threads = 248; 1749 rdev->config.evergreen.max_gs_threads = 32; 1750 rdev->config.evergreen.max_stack_entries = 512; 1751 rdev->config.evergreen.sx_num_of_sets = 4; 1752 rdev->config.evergreen.sx_max_export_size = 256; 1753 rdev->config.evergreen.sx_max_export_pos_size = 64; 1754 rdev->config.evergreen.sx_max_export_smx_size = 192; 1755 rdev->config.evergreen.max_hw_contexts = 8; 1756 rdev->config.evergreen.sq_num_cf_insts = 2; 1757 1758 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1759 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1760 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1761 break; 1762 case CHIP_BARTS: 1763 rdev->config.evergreen.num_ses = 2; 1764 rdev->config.evergreen.max_pipes = 4; 1765 rdev->config.evergreen.max_tile_pipes = 8; 1766 rdev->config.evergreen.max_simds = 7; 1767 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; 1768 rdev->config.evergreen.max_gprs = 256; 1769 rdev->config.evergreen.max_threads = 248; 1770 rdev->config.evergreen.max_gs_threads = 32; 1771 rdev->config.evergreen.max_stack_entries = 512; 1772 rdev->config.evergreen.sx_num_of_sets = 4; 1773 rdev->config.evergreen.sx_max_export_size = 256; 1774 rdev->config.evergreen.sx_max_export_pos_size = 64; 1775 rdev->config.evergreen.sx_max_export_smx_size = 192; 1776 rdev->config.evergreen.max_hw_contexts = 8; 1777 rdev->config.evergreen.sq_num_cf_insts = 2; 1778 1779 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1780 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1781 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1782 break; 1783 case CHIP_TURKS: 1784 rdev->config.evergreen.num_ses = 1; 1785 rdev->config.evergreen.max_pipes = 4; 1786 rdev->config.evergreen.max_tile_pipes = 4; 1787 rdev->config.evergreen.max_simds = 6; 1788 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; 1789 rdev->config.evergreen.max_gprs = 256; 1790 rdev->config.evergreen.max_threads = 248; 1791 rdev->config.evergreen.max_gs_threads = 32; 1792 rdev->config.evergreen.max_stack_entries = 256; 1793 rdev->config.evergreen.sx_num_of_sets = 4; 1794 rdev->config.evergreen.sx_max_export_size = 256; 1795 rdev->config.evergreen.sx_max_export_pos_size = 64; 1796 rdev->config.evergreen.sx_max_export_smx_size = 192; 1797 rdev->config.evergreen.max_hw_contexts = 8; 1798 rdev->config.evergreen.sq_num_cf_insts = 2; 1799 1800 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1801 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1802 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1803 break; 1804 case CHIP_CAICOS: 1805 rdev->config.evergreen.num_ses = 1; 1806 rdev->config.evergreen.max_pipes = 4; 1807 rdev->config.evergreen.max_tile_pipes = 2; 1808 rdev->config.evergreen.max_simds = 2; 1809 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1810 rdev->config.evergreen.max_gprs = 256; 1811 rdev->config.evergreen.max_threads = 192; 1812 rdev->config.evergreen.max_gs_threads = 16; 1813 rdev->config.evergreen.max_stack_entries = 256; 1814 rdev->config.evergreen.sx_num_of_sets = 4; 1815 rdev->config.evergreen.sx_max_export_size = 128; 1816 rdev->config.evergreen.sx_max_export_pos_size = 32; 1817 rdev->config.evergreen.sx_max_export_smx_size = 96; 1818 rdev->config.evergreen.max_hw_contexts = 4; 1819 rdev->config.evergreen.sq_num_cf_insts = 1; 1820 1821 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1822 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1823 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1824 break; 1825 } 1826 1827 /* Initialize HDP */ 1828 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1829 WREG32((0x2c14 + j), 0x00000000); 1830 WREG32((0x2c18 + j), 0x00000000); 1831 WREG32((0x2c1c + j), 0x00000000); 1832 WREG32((0x2c20 + j), 0x00000000); 1833 WREG32((0x2c24 + j), 0x00000000); 1834 } 1835 1836 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1837 1838 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2; 1839 1840 cc_gc_shader_pipe_config |= 1841 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes) 1842 & EVERGREEN_MAX_PIPES_MASK); 1843 cc_gc_shader_pipe_config |= 1844 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds) 1845 & EVERGREEN_MAX_SIMDS_MASK); 1846 1847 cc_rb_backend_disable = 1848 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends) 1849 & EVERGREEN_MAX_BACKENDS_MASK); 1850 1851 1852 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1853 if (rdev->flags & RADEON_IS_IGP) 1854 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG); 1855 else 1856 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1857 1858 switch (rdev->config.evergreen.max_tile_pipes) { 1859 case 1: 1860 default: 1861 gb_addr_config |= NUM_PIPES(0); 1862 break; 1863 case 2: 1864 gb_addr_config |= NUM_PIPES(1); 1865 break; 1866 case 4: 1867 gb_addr_config |= NUM_PIPES(2); 1868 break; 1869 case 8: 1870 gb_addr_config |= NUM_PIPES(3); 1871 break; 1872 } 1873 1874 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1875 gb_addr_config |= BANK_INTERLEAVE_SIZE(0); 1876 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1); 1877 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1); 1878 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */ 1879 gb_addr_config |= MULTI_GPU_TILE_SIZE(2); 1880 1881 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2) 1882 gb_addr_config |= ROW_SIZE(2); 1883 else 1884 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT); 1885 1886 if (rdev->ddev->pdev->device == 0x689e) { 1887 u32 efuse_straps_4; 1888 u32 efuse_straps_3; 1889 u8 efuse_box_bit_131_124; 1890 1891 WREG32(RCU_IND_INDEX, 0x204); 1892 efuse_straps_4 = RREG32(RCU_IND_DATA); 1893 WREG32(RCU_IND_INDEX, 0x203); 1894 efuse_straps_3 = RREG32(RCU_IND_DATA); 1895 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28)); 1896 1897 switch(efuse_box_bit_131_124) { 1898 case 0x00: 1899 gb_backend_map = 0x76543210; 1900 break; 1901 case 0x55: 1902 gb_backend_map = 0x77553311; 1903 break; 1904 case 0x56: 1905 gb_backend_map = 0x77553300; 1906 break; 1907 case 0x59: 1908 gb_backend_map = 0x77552211; 1909 break; 1910 case 0x66: 1911 gb_backend_map = 0x77443300; 1912 break; 1913 case 0x99: 1914 gb_backend_map = 0x66552211; 1915 break; 1916 case 0x5a: 1917 gb_backend_map = 0x77552200; 1918 break; 1919 case 0xaa: 1920 gb_backend_map = 0x66442200; 1921 break; 1922 case 0x95: 1923 gb_backend_map = 0x66553311; 1924 break; 1925 default: 1926 DRM_ERROR("bad backend map, using default\n"); 1927 gb_backend_map = 1928 evergreen_get_tile_pipe_to_backend_map(rdev, 1929 rdev->config.evergreen.max_tile_pipes, 1930 rdev->config.evergreen.max_backends, 1931 ((EVERGREEN_MAX_BACKENDS_MASK << 1932 rdev->config.evergreen.max_backends) & 1933 EVERGREEN_MAX_BACKENDS_MASK)); 1934 break; 1935 } 1936 } else if (rdev->ddev->pdev->device == 0x68b9) { 1937 u32 efuse_straps_3; 1938 u8 efuse_box_bit_127_124; 1939 1940 WREG32(RCU_IND_INDEX, 0x203); 1941 efuse_straps_3 = RREG32(RCU_IND_DATA); 1942 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28); 1943 1944 switch(efuse_box_bit_127_124) { 1945 case 0x0: 1946 gb_backend_map = 0x00003210; 1947 break; 1948 case 0x5: 1949 case 0x6: 1950 case 0x9: 1951 case 0xa: 1952 gb_backend_map = 0x00003311; 1953 break; 1954 default: 1955 DRM_ERROR("bad backend map, using default\n"); 1956 gb_backend_map = 1957 evergreen_get_tile_pipe_to_backend_map(rdev, 1958 rdev->config.evergreen.max_tile_pipes, 1959 rdev->config.evergreen.max_backends, 1960 ((EVERGREEN_MAX_BACKENDS_MASK << 1961 rdev->config.evergreen.max_backends) & 1962 EVERGREEN_MAX_BACKENDS_MASK)); 1963 break; 1964 } 1965 } else { 1966 switch (rdev->family) { 1967 case CHIP_CYPRESS: 1968 case CHIP_HEMLOCK: 1969 case CHIP_BARTS: 1970 gb_backend_map = 0x66442200; 1971 break; 1972 case CHIP_JUNIPER: 1973 gb_backend_map = 0x00006420; 1974 break; 1975 default: 1976 gb_backend_map = 1977 evergreen_get_tile_pipe_to_backend_map(rdev, 1978 rdev->config.evergreen.max_tile_pipes, 1979 rdev->config.evergreen.max_backends, 1980 ((EVERGREEN_MAX_BACKENDS_MASK << 1981 rdev->config.evergreen.max_backends) & 1982 EVERGREEN_MAX_BACKENDS_MASK)); 1983 } 1984 } 1985 1986 /* setup tiling info dword. gb_addr_config is not adequate since it does 1987 * not have bank info, so create a custom tiling dword. 1988 * bits 3:0 num_pipes 1989 * bits 7:4 num_banks 1990 * bits 11:8 group_size 1991 * bits 15:12 row_size 1992 */ 1993 rdev->config.evergreen.tile_config = 0; 1994 switch (rdev->config.evergreen.max_tile_pipes) { 1995 case 1: 1996 default: 1997 rdev->config.evergreen.tile_config |= (0 << 0); 1998 break; 1999 case 2: 2000 rdev->config.evergreen.tile_config |= (1 << 0); 2001 break; 2002 case 4: 2003 rdev->config.evergreen.tile_config |= (2 << 0); 2004 break; 2005 case 8: 2006 rdev->config.evergreen.tile_config |= (3 << 0); 2007 break; 2008 } 2009 /* num banks is 8 on all fusion asics */ 2010 if (rdev->flags & RADEON_IS_IGP) 2011 rdev->config.evergreen.tile_config |= 8 << 4; 2012 else 2013 rdev->config.evergreen.tile_config |= 2014 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; 2015 rdev->config.evergreen.tile_config |= 2016 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8; 2017 rdev->config.evergreen.tile_config |= 2018 ((gb_addr_config & 0x30000000) >> 28) << 12; 2019 2020 WREG32(GB_BACKEND_MAP, gb_backend_map); 2021 WREG32(GB_ADDR_CONFIG, gb_addr_config); 2022 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 2023 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 2024 2025 evergreen_program_channel_remap(rdev); 2026 2027 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1; 2028 grbm_gfx_index = INSTANCE_BROADCAST_WRITES; 2029 2030 for (i = 0; i < rdev->config.evergreen.num_ses; i++) { 2031 u32 rb = cc_rb_backend_disable | (0xf0 << 16); 2032 u32 sp = cc_gc_shader_pipe_config; 2033 u32 gfx = grbm_gfx_index | SE_INDEX(i); 2034 2035 if (i == num_shader_engines) { 2036 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK); 2037 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK); 2038 } 2039 2040 WREG32(GRBM_GFX_INDEX, gfx); 2041 WREG32(RLC_GFX_INDEX, gfx); 2042 2043 WREG32(CC_RB_BACKEND_DISABLE, rb); 2044 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb); 2045 WREG32(GC_USER_RB_BACKEND_DISABLE, rb); 2046 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp); 2047 } 2048 2049 grbm_gfx_index |= SE_BROADCAST_WRITES; 2050 WREG32(GRBM_GFX_INDEX, grbm_gfx_index); 2051 WREG32(RLC_GFX_INDEX, grbm_gfx_index); 2052 2053 WREG32(CGTS_SYS_TCC_DISABLE, 0); 2054 WREG32(CGTS_TCC_DISABLE, 0); 2055 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); 2056 WREG32(CGTS_USER_TCC_DISABLE, 0); 2057 2058 /* set HW defaults for 3D engine */ 2059 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 2060 ROQ_IB2_START(0x2b))); 2061 2062 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); 2063 2064 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | 2065 SYNC_GRADIENT | 2066 SYNC_WALKER | 2067 SYNC_ALIGNER)); 2068 2069 sx_debug_1 = RREG32(SX_DEBUG_1); 2070 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 2071 WREG32(SX_DEBUG_1, sx_debug_1); 2072 2073 2074 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 2075 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); 2076 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); 2077 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 2078 2079 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) | 2080 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | 2081 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); 2082 2083 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | 2084 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) | 2085 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size))); 2086 2087 WREG32(VGT_NUM_INSTANCES, 1); 2088 WREG32(SPI_CONFIG_CNTL, 0); 2089 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 2090 WREG32(CP_PERFMON_CNTL, 0); 2091 2092 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | 2093 FETCH_FIFO_HIWATER(0x4) | 2094 DONE_FIFO_HIWATER(0xe0) | 2095 ALU_UPDATE_FIFO_HIWATER(0x8))); 2096 2097 sq_config = RREG32(SQ_CONFIG); 2098 sq_config &= ~(PS_PRIO(3) | 2099 VS_PRIO(3) | 2100 GS_PRIO(3) | 2101 ES_PRIO(3)); 2102 sq_config |= (VC_ENABLE | 2103 EXPORT_SRC_C | 2104 PS_PRIO(0) | 2105 VS_PRIO(1) | 2106 GS_PRIO(2) | 2107 ES_PRIO(3)); 2108 2109 switch (rdev->family) { 2110 case CHIP_CEDAR: 2111 case CHIP_PALM: 2112 case CHIP_SUMO: 2113 case CHIP_SUMO2: 2114 case CHIP_CAICOS: 2115 /* no vertex cache */ 2116 sq_config &= ~VC_ENABLE; 2117 break; 2118 default: 2119 break; 2120 } 2121 2122 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT); 2123 2124 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32); 2125 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32); 2126 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4); 2127 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); 2128 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); 2129 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); 2130 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); 2131 2132 switch (rdev->family) { 2133 case CHIP_CEDAR: 2134 case CHIP_PALM: 2135 case CHIP_SUMO: 2136 case CHIP_SUMO2: 2137 ps_thread_count = 96; 2138 break; 2139 default: 2140 ps_thread_count = 128; 2141 break; 2142 } 2143 2144 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count); 2145 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2146 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2147 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2148 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2149 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2150 2151 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2152 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2153 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2154 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2155 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2156 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2157 2158 WREG32(SQ_CONFIG, sq_config); 2159 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2160 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2161 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3); 2162 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2163 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2); 2164 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2165 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2166 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3); 2167 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); 2168 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt); 2169 2170 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 2171 FORCE_EOV_MAX_REZ_CNT(255))); 2172 2173 switch (rdev->family) { 2174 case CHIP_CEDAR: 2175 case CHIP_PALM: 2176 case CHIP_SUMO: 2177 case CHIP_SUMO2: 2178 case CHIP_CAICOS: 2179 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY); 2180 break; 2181 default: 2182 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC); 2183 break; 2184 } 2185 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO); 2186 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation); 2187 2188 WREG32(VGT_GS_VERTEX_REUSE, 16); 2189 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0); 2190 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2191 2192 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14); 2193 WREG32(VGT_OUT_DEALLOC_CNTL, 16); 2194 2195 WREG32(CB_PERF_CTR0_SEL_0, 0); 2196 WREG32(CB_PERF_CTR0_SEL_1, 0); 2197 WREG32(CB_PERF_CTR1_SEL_0, 0); 2198 WREG32(CB_PERF_CTR1_SEL_1, 0); 2199 WREG32(CB_PERF_CTR2_SEL_0, 0); 2200 WREG32(CB_PERF_CTR2_SEL_1, 0); 2201 WREG32(CB_PERF_CTR3_SEL_0, 0); 2202 WREG32(CB_PERF_CTR3_SEL_1, 0); 2203 2204 /* clear render buffer base addresses */ 2205 WREG32(CB_COLOR0_BASE, 0); 2206 WREG32(CB_COLOR1_BASE, 0); 2207 WREG32(CB_COLOR2_BASE, 0); 2208 WREG32(CB_COLOR3_BASE, 0); 2209 WREG32(CB_COLOR4_BASE, 0); 2210 WREG32(CB_COLOR5_BASE, 0); 2211 WREG32(CB_COLOR6_BASE, 0); 2212 WREG32(CB_COLOR7_BASE, 0); 2213 WREG32(CB_COLOR8_BASE, 0); 2214 WREG32(CB_COLOR9_BASE, 0); 2215 WREG32(CB_COLOR10_BASE, 0); 2216 WREG32(CB_COLOR11_BASE, 0); 2217 2218 /* set the shader const cache sizes to 0 */ 2219 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4) 2220 WREG32(i, 0); 2221 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4) 2222 WREG32(i, 0); 2223 2224 tmp = RREG32(HDP_MISC_CNTL); 2225 tmp |= HDP_FLUSH_INVALIDATE_CACHE; 2226 WREG32(HDP_MISC_CNTL, tmp); 2227 2228 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 2229 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 2230 2231 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 2232 2233 udelay(50); 2234 2235 } 2236 2237 int evergreen_mc_init(struct radeon_device *rdev) 2238 { 2239 u32 tmp; 2240 int chansize, numchan; 2241 2242 /* Get VRAM informations */ 2243 rdev->mc.vram_is_ddr = true; 2244 tmp = RREG32(MC_ARB_RAMCFG); 2245 if (tmp & CHANSIZE_OVERRIDE) { 2246 chansize = 16; 2247 } else if (tmp & CHANSIZE_MASK) { 2248 chansize = 64; 2249 } else { 2250 chansize = 32; 2251 } 2252 tmp = RREG32(MC_SHARED_CHMAP); 2253 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 2254 case 0: 2255 default: 2256 numchan = 1; 2257 break; 2258 case 1: 2259 numchan = 2; 2260 break; 2261 case 2: 2262 numchan = 4; 2263 break; 2264 case 3: 2265 numchan = 8; 2266 break; 2267 } 2268 rdev->mc.vram_width = numchan * chansize; 2269 /* Could aper size report 0 ? */ 2270 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2271 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2272 /* Setup GPU memory space */ 2273 if (rdev->flags & RADEON_IS_IGP) { 2274 /* size in bytes on fusion */ 2275 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 2276 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 2277 } else { 2278 /* size in MB on evergreen */ 2279 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2280 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2281 } 2282 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2283 r700_vram_gtt_location(rdev, &rdev->mc); 2284 radeon_update_bandwidth_info(rdev); 2285 2286 return 0; 2287 } 2288 2289 bool evergreen_gpu_is_lockup(struct radeon_device *rdev) 2290 { 2291 u32 srbm_status; 2292 u32 grbm_status; 2293 u32 grbm_status_se0, grbm_status_se1; 2294 struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup; 2295 int r; 2296 2297 srbm_status = RREG32(SRBM_STATUS); 2298 grbm_status = RREG32(GRBM_STATUS); 2299 grbm_status_se0 = RREG32(GRBM_STATUS_SE0); 2300 grbm_status_se1 = RREG32(GRBM_STATUS_SE1); 2301 if (!(grbm_status & GUI_ACTIVE)) { 2302 r100_gpu_lockup_update(lockup, &rdev->cp); 2303 return false; 2304 } 2305 /* force CP activities */ 2306 r = radeon_ring_lock(rdev, 2); 2307 if (!r) { 2308 /* PACKET2 NOP */ 2309 radeon_ring_write(rdev, 0x80000000); 2310 radeon_ring_write(rdev, 0x80000000); 2311 radeon_ring_unlock_commit(rdev); 2312 } 2313 rdev->cp.rptr = RREG32(CP_RB_RPTR); 2314 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp); 2315 } 2316 2317 static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 2318 { 2319 struct evergreen_mc_save save; 2320 u32 grbm_reset = 0; 2321 2322 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2323 return 0; 2324 2325 dev_info(rdev->dev, "GPU softreset \n"); 2326 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2327 RREG32(GRBM_STATUS)); 2328 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2329 RREG32(GRBM_STATUS_SE0)); 2330 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2331 RREG32(GRBM_STATUS_SE1)); 2332 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 2333 RREG32(SRBM_STATUS)); 2334 evergreen_mc_stop(rdev, &save); 2335 if (evergreen_mc_wait_for_idle(rdev)) { 2336 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2337 } 2338 /* Disable CP parsing/prefetching */ 2339 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); 2340 2341 /* reset all the gfx blocks */ 2342 grbm_reset = (SOFT_RESET_CP | 2343 SOFT_RESET_CB | 2344 SOFT_RESET_DB | 2345 SOFT_RESET_PA | 2346 SOFT_RESET_SC | 2347 SOFT_RESET_SPI | 2348 SOFT_RESET_SH | 2349 SOFT_RESET_SX | 2350 SOFT_RESET_TC | 2351 SOFT_RESET_TA | 2352 SOFT_RESET_VC | 2353 SOFT_RESET_VGT); 2354 2355 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); 2356 WREG32(GRBM_SOFT_RESET, grbm_reset); 2357 (void)RREG32(GRBM_SOFT_RESET); 2358 udelay(50); 2359 WREG32(GRBM_SOFT_RESET, 0); 2360 (void)RREG32(GRBM_SOFT_RESET); 2361 /* Wait a little for things to settle down */ 2362 udelay(50); 2363 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2364 RREG32(GRBM_STATUS)); 2365 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2366 RREG32(GRBM_STATUS_SE0)); 2367 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2368 RREG32(GRBM_STATUS_SE1)); 2369 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 2370 RREG32(SRBM_STATUS)); 2371 evergreen_mc_resume(rdev, &save); 2372 return 0; 2373 } 2374 2375 int evergreen_asic_reset(struct radeon_device *rdev) 2376 { 2377 return evergreen_gpu_soft_reset(rdev); 2378 } 2379 2380 /* Interrupts */ 2381 2382 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc) 2383 { 2384 switch (crtc) { 2385 case 0: 2386 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET); 2387 case 1: 2388 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET); 2389 case 2: 2390 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET); 2391 case 3: 2392 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET); 2393 case 4: 2394 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET); 2395 case 5: 2396 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET); 2397 default: 2398 return 0; 2399 } 2400 } 2401 2402 void evergreen_disable_interrupt_state(struct radeon_device *rdev) 2403 { 2404 u32 tmp; 2405 2406 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 2407 WREG32(GRBM_INT_CNTL, 0); 2408 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2409 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2410 if (!(rdev->flags & RADEON_IS_IGP)) { 2411 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2412 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2413 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2414 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2415 } 2416 2417 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2418 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2419 if (!(rdev->flags & RADEON_IS_IGP)) { 2420 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2421 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2422 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2423 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2424 } 2425 2426 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 2427 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 2428 2429 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2430 WREG32(DC_HPD1_INT_CONTROL, tmp); 2431 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2432 WREG32(DC_HPD2_INT_CONTROL, tmp); 2433 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2434 WREG32(DC_HPD3_INT_CONTROL, tmp); 2435 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2436 WREG32(DC_HPD4_INT_CONTROL, tmp); 2437 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2438 WREG32(DC_HPD5_INT_CONTROL, tmp); 2439 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2440 WREG32(DC_HPD6_INT_CONTROL, tmp); 2441 2442 } 2443 2444 int evergreen_irq_set(struct radeon_device *rdev) 2445 { 2446 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 2447 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 2448 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 2449 u32 grbm_int_cntl = 0; 2450 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; 2451 2452 if (!rdev->irq.installed) { 2453 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 2454 return -EINVAL; 2455 } 2456 /* don't enable anything if the ih is disabled */ 2457 if (!rdev->ih.enabled) { 2458 r600_disable_interrupts(rdev); 2459 /* force the active interrupt state to all disabled */ 2460 evergreen_disable_interrupt_state(rdev); 2461 return 0; 2462 } 2463 2464 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 2465 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 2466 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 2467 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 2468 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 2469 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 2470 2471 if (rdev->irq.sw_int) { 2472 DRM_DEBUG("evergreen_irq_set: sw int\n"); 2473 cp_int_cntl |= RB_INT_ENABLE; 2474 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 2475 } 2476 if (rdev->irq.crtc_vblank_int[0] || 2477 rdev->irq.pflip[0]) { 2478 DRM_DEBUG("evergreen_irq_set: vblank 0\n"); 2479 crtc1 |= VBLANK_INT_MASK; 2480 } 2481 if (rdev->irq.crtc_vblank_int[1] || 2482 rdev->irq.pflip[1]) { 2483 DRM_DEBUG("evergreen_irq_set: vblank 1\n"); 2484 crtc2 |= VBLANK_INT_MASK; 2485 } 2486 if (rdev->irq.crtc_vblank_int[2] || 2487 rdev->irq.pflip[2]) { 2488 DRM_DEBUG("evergreen_irq_set: vblank 2\n"); 2489 crtc3 |= VBLANK_INT_MASK; 2490 } 2491 if (rdev->irq.crtc_vblank_int[3] || 2492 rdev->irq.pflip[3]) { 2493 DRM_DEBUG("evergreen_irq_set: vblank 3\n"); 2494 crtc4 |= VBLANK_INT_MASK; 2495 } 2496 if (rdev->irq.crtc_vblank_int[4] || 2497 rdev->irq.pflip[4]) { 2498 DRM_DEBUG("evergreen_irq_set: vblank 4\n"); 2499 crtc5 |= VBLANK_INT_MASK; 2500 } 2501 if (rdev->irq.crtc_vblank_int[5] || 2502 rdev->irq.pflip[5]) { 2503 DRM_DEBUG("evergreen_irq_set: vblank 5\n"); 2504 crtc6 |= VBLANK_INT_MASK; 2505 } 2506 if (rdev->irq.hpd[0]) { 2507 DRM_DEBUG("evergreen_irq_set: hpd 1\n"); 2508 hpd1 |= DC_HPDx_INT_EN; 2509 } 2510 if (rdev->irq.hpd[1]) { 2511 DRM_DEBUG("evergreen_irq_set: hpd 2\n"); 2512 hpd2 |= DC_HPDx_INT_EN; 2513 } 2514 if (rdev->irq.hpd[2]) { 2515 DRM_DEBUG("evergreen_irq_set: hpd 3\n"); 2516 hpd3 |= DC_HPDx_INT_EN; 2517 } 2518 if (rdev->irq.hpd[3]) { 2519 DRM_DEBUG("evergreen_irq_set: hpd 4\n"); 2520 hpd4 |= DC_HPDx_INT_EN; 2521 } 2522 if (rdev->irq.hpd[4]) { 2523 DRM_DEBUG("evergreen_irq_set: hpd 5\n"); 2524 hpd5 |= DC_HPDx_INT_EN; 2525 } 2526 if (rdev->irq.hpd[5]) { 2527 DRM_DEBUG("evergreen_irq_set: hpd 6\n"); 2528 hpd6 |= DC_HPDx_INT_EN; 2529 } 2530 if (rdev->irq.gui_idle) { 2531 DRM_DEBUG("gui idle\n"); 2532 grbm_int_cntl |= GUI_IDLE_INT_ENABLE; 2533 } 2534 2535 WREG32(CP_INT_CNTL, cp_int_cntl); 2536 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 2537 2538 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 2539 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 2540 if (!(rdev->flags & RADEON_IS_IGP)) { 2541 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 2542 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 2543 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 2544 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 2545 } 2546 2547 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 2548 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 2549 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 2550 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 2551 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 2552 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 2553 2554 WREG32(DC_HPD1_INT_CONTROL, hpd1); 2555 WREG32(DC_HPD2_INT_CONTROL, hpd2); 2556 WREG32(DC_HPD3_INT_CONTROL, hpd3); 2557 WREG32(DC_HPD4_INT_CONTROL, hpd4); 2558 WREG32(DC_HPD5_INT_CONTROL, hpd5); 2559 WREG32(DC_HPD6_INT_CONTROL, hpd6); 2560 2561 return 0; 2562 } 2563 2564 static inline void evergreen_irq_ack(struct radeon_device *rdev) 2565 { 2566 u32 tmp; 2567 2568 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); 2569 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 2570 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); 2571 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); 2572 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); 2573 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 2574 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 2575 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 2576 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 2577 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 2578 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 2579 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 2580 2581 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) 2582 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2583 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) 2584 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2585 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) 2586 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2587 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) 2588 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2589 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) 2590 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2591 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) 2592 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2593 2594 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) 2595 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 2596 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) 2597 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); 2598 2599 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) 2600 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); 2601 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) 2602 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 2603 2604 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 2605 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 2606 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 2607 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 2608 2609 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 2610 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 2611 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 2612 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 2613 2614 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 2615 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 2616 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 2617 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 2618 2619 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 2620 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 2621 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 2622 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 2623 2624 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 2625 tmp = RREG32(DC_HPD1_INT_CONTROL); 2626 tmp |= DC_HPDx_INT_ACK; 2627 WREG32(DC_HPD1_INT_CONTROL, tmp); 2628 } 2629 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 2630 tmp = RREG32(DC_HPD2_INT_CONTROL); 2631 tmp |= DC_HPDx_INT_ACK; 2632 WREG32(DC_HPD2_INT_CONTROL, tmp); 2633 } 2634 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 2635 tmp = RREG32(DC_HPD3_INT_CONTROL); 2636 tmp |= DC_HPDx_INT_ACK; 2637 WREG32(DC_HPD3_INT_CONTROL, tmp); 2638 } 2639 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 2640 tmp = RREG32(DC_HPD4_INT_CONTROL); 2641 tmp |= DC_HPDx_INT_ACK; 2642 WREG32(DC_HPD4_INT_CONTROL, tmp); 2643 } 2644 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 2645 tmp = RREG32(DC_HPD5_INT_CONTROL); 2646 tmp |= DC_HPDx_INT_ACK; 2647 WREG32(DC_HPD5_INT_CONTROL, tmp); 2648 } 2649 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 2650 tmp = RREG32(DC_HPD5_INT_CONTROL); 2651 tmp |= DC_HPDx_INT_ACK; 2652 WREG32(DC_HPD6_INT_CONTROL, tmp); 2653 } 2654 } 2655 2656 void evergreen_irq_disable(struct radeon_device *rdev) 2657 { 2658 r600_disable_interrupts(rdev); 2659 /* Wait and acknowledge irq */ 2660 mdelay(1); 2661 evergreen_irq_ack(rdev); 2662 evergreen_disable_interrupt_state(rdev); 2663 } 2664 2665 void evergreen_irq_suspend(struct radeon_device *rdev) 2666 { 2667 evergreen_irq_disable(rdev); 2668 r600_rlc_stop(rdev); 2669 } 2670 2671 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev) 2672 { 2673 u32 wptr, tmp; 2674 2675 if (rdev->wb.enabled) 2676 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 2677 else 2678 wptr = RREG32(IH_RB_WPTR); 2679 2680 if (wptr & RB_OVERFLOW) { 2681 /* When a ring buffer overflow happen start parsing interrupt 2682 * from the last not overwritten vector (wptr + 16). Hopefully 2683 * this should allow us to catchup. 2684 */ 2685 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 2686 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 2687 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 2688 tmp = RREG32(IH_RB_CNTL); 2689 tmp |= IH_WPTR_OVERFLOW_CLEAR; 2690 WREG32(IH_RB_CNTL, tmp); 2691 } 2692 return (wptr & rdev->ih.ptr_mask); 2693 } 2694 2695 int evergreen_irq_process(struct radeon_device *rdev) 2696 { 2697 u32 wptr = evergreen_get_ih_wptr(rdev); 2698 u32 rptr = rdev->ih.rptr; 2699 u32 src_id, src_data; 2700 u32 ring_index; 2701 unsigned long flags; 2702 bool queue_hotplug = false; 2703 2704 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 2705 if (!rdev->ih.enabled) 2706 return IRQ_NONE; 2707 2708 spin_lock_irqsave(&rdev->ih.lock, flags); 2709 2710 if (rptr == wptr) { 2711 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2712 return IRQ_NONE; 2713 } 2714 if (rdev->shutdown) { 2715 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2716 return IRQ_NONE; 2717 } 2718 2719 restart_ih: 2720 /* display interrupts */ 2721 evergreen_irq_ack(rdev); 2722 2723 rdev->ih.wptr = wptr; 2724 while (rptr != wptr) { 2725 /* wptr/rptr are in bytes! */ 2726 ring_index = rptr / 4; 2727 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 2728 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 2729 2730 switch (src_id) { 2731 case 1: /* D1 vblank/vline */ 2732 switch (src_data) { 2733 case 0: /* D1 vblank */ 2734 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { 2735 if (rdev->irq.crtc_vblank_int[0]) { 2736 drm_handle_vblank(rdev->ddev, 0); 2737 rdev->pm.vblank_sync = true; 2738 wake_up(&rdev->irq.vblank_queue); 2739 } 2740 if (rdev->irq.pflip[0]) 2741 radeon_crtc_handle_flip(rdev, 0); 2742 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 2743 DRM_DEBUG("IH: D1 vblank\n"); 2744 } 2745 break; 2746 case 1: /* D1 vline */ 2747 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { 2748 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; 2749 DRM_DEBUG("IH: D1 vline\n"); 2750 } 2751 break; 2752 default: 2753 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2754 break; 2755 } 2756 break; 2757 case 2: /* D2 vblank/vline */ 2758 switch (src_data) { 2759 case 0: /* D2 vblank */ 2760 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { 2761 if (rdev->irq.crtc_vblank_int[1]) { 2762 drm_handle_vblank(rdev->ddev, 1); 2763 rdev->pm.vblank_sync = true; 2764 wake_up(&rdev->irq.vblank_queue); 2765 } 2766 if (rdev->irq.pflip[1]) 2767 radeon_crtc_handle_flip(rdev, 1); 2768 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 2769 DRM_DEBUG("IH: D2 vblank\n"); 2770 } 2771 break; 2772 case 1: /* D2 vline */ 2773 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { 2774 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 2775 DRM_DEBUG("IH: D2 vline\n"); 2776 } 2777 break; 2778 default: 2779 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2780 break; 2781 } 2782 break; 2783 case 3: /* D3 vblank/vline */ 2784 switch (src_data) { 2785 case 0: /* D3 vblank */ 2786 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { 2787 if (rdev->irq.crtc_vblank_int[2]) { 2788 drm_handle_vblank(rdev->ddev, 2); 2789 rdev->pm.vblank_sync = true; 2790 wake_up(&rdev->irq.vblank_queue); 2791 } 2792 if (rdev->irq.pflip[2]) 2793 radeon_crtc_handle_flip(rdev, 2); 2794 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 2795 DRM_DEBUG("IH: D3 vblank\n"); 2796 } 2797 break; 2798 case 1: /* D3 vline */ 2799 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { 2800 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 2801 DRM_DEBUG("IH: D3 vline\n"); 2802 } 2803 break; 2804 default: 2805 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2806 break; 2807 } 2808 break; 2809 case 4: /* D4 vblank/vline */ 2810 switch (src_data) { 2811 case 0: /* D4 vblank */ 2812 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { 2813 if (rdev->irq.crtc_vblank_int[3]) { 2814 drm_handle_vblank(rdev->ddev, 3); 2815 rdev->pm.vblank_sync = true; 2816 wake_up(&rdev->irq.vblank_queue); 2817 } 2818 if (rdev->irq.pflip[3]) 2819 radeon_crtc_handle_flip(rdev, 3); 2820 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 2821 DRM_DEBUG("IH: D4 vblank\n"); 2822 } 2823 break; 2824 case 1: /* D4 vline */ 2825 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { 2826 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 2827 DRM_DEBUG("IH: D4 vline\n"); 2828 } 2829 break; 2830 default: 2831 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2832 break; 2833 } 2834 break; 2835 case 5: /* D5 vblank/vline */ 2836 switch (src_data) { 2837 case 0: /* D5 vblank */ 2838 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { 2839 if (rdev->irq.crtc_vblank_int[4]) { 2840 drm_handle_vblank(rdev->ddev, 4); 2841 rdev->pm.vblank_sync = true; 2842 wake_up(&rdev->irq.vblank_queue); 2843 } 2844 if (rdev->irq.pflip[4]) 2845 radeon_crtc_handle_flip(rdev, 4); 2846 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 2847 DRM_DEBUG("IH: D5 vblank\n"); 2848 } 2849 break; 2850 case 1: /* D5 vline */ 2851 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { 2852 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 2853 DRM_DEBUG("IH: D5 vline\n"); 2854 } 2855 break; 2856 default: 2857 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2858 break; 2859 } 2860 break; 2861 case 6: /* D6 vblank/vline */ 2862 switch (src_data) { 2863 case 0: /* D6 vblank */ 2864 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { 2865 if (rdev->irq.crtc_vblank_int[5]) { 2866 drm_handle_vblank(rdev->ddev, 5); 2867 rdev->pm.vblank_sync = true; 2868 wake_up(&rdev->irq.vblank_queue); 2869 } 2870 if (rdev->irq.pflip[5]) 2871 radeon_crtc_handle_flip(rdev, 5); 2872 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 2873 DRM_DEBUG("IH: D6 vblank\n"); 2874 } 2875 break; 2876 case 1: /* D6 vline */ 2877 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { 2878 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 2879 DRM_DEBUG("IH: D6 vline\n"); 2880 } 2881 break; 2882 default: 2883 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2884 break; 2885 } 2886 break; 2887 case 42: /* HPD hotplug */ 2888 switch (src_data) { 2889 case 0: 2890 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 2891 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; 2892 queue_hotplug = true; 2893 DRM_DEBUG("IH: HPD1\n"); 2894 } 2895 break; 2896 case 1: 2897 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 2898 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; 2899 queue_hotplug = true; 2900 DRM_DEBUG("IH: HPD2\n"); 2901 } 2902 break; 2903 case 2: 2904 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 2905 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 2906 queue_hotplug = true; 2907 DRM_DEBUG("IH: HPD3\n"); 2908 } 2909 break; 2910 case 3: 2911 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 2912 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 2913 queue_hotplug = true; 2914 DRM_DEBUG("IH: HPD4\n"); 2915 } 2916 break; 2917 case 4: 2918 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 2919 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 2920 queue_hotplug = true; 2921 DRM_DEBUG("IH: HPD5\n"); 2922 } 2923 break; 2924 case 5: 2925 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 2926 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 2927 queue_hotplug = true; 2928 DRM_DEBUG("IH: HPD6\n"); 2929 } 2930 break; 2931 default: 2932 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2933 break; 2934 } 2935 break; 2936 case 176: /* CP_INT in ring buffer */ 2937 case 177: /* CP_INT in IB1 */ 2938 case 178: /* CP_INT in IB2 */ 2939 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 2940 radeon_fence_process(rdev); 2941 break; 2942 case 181: /* CP EOP event */ 2943 DRM_DEBUG("IH: CP EOP\n"); 2944 radeon_fence_process(rdev); 2945 break; 2946 case 233: /* GUI IDLE */ 2947 DRM_DEBUG("IH: CP EOP\n"); 2948 rdev->pm.gui_idle = true; 2949 wake_up(&rdev->irq.idle_queue); 2950 break; 2951 default: 2952 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 2953 break; 2954 } 2955 2956 /* wptr/rptr are in bytes! */ 2957 rptr += 16; 2958 rptr &= rdev->ih.ptr_mask; 2959 } 2960 /* make sure wptr hasn't changed while processing */ 2961 wptr = evergreen_get_ih_wptr(rdev); 2962 if (wptr != rdev->ih.wptr) 2963 goto restart_ih; 2964 if (queue_hotplug) 2965 schedule_work(&rdev->hotplug_work); 2966 rdev->ih.rptr = rptr; 2967 WREG32(IH_RB_RPTR, rdev->ih.rptr); 2968 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2969 return IRQ_HANDLED; 2970 } 2971 2972 static int evergreen_startup(struct radeon_device *rdev) 2973 { 2974 int r; 2975 2976 /* enable pcie gen2 link */ 2977 if (!ASIC_IS_DCE5(rdev)) 2978 evergreen_pcie_gen2_enable(rdev); 2979 2980 if (ASIC_IS_DCE5(rdev)) { 2981 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { 2982 r = ni_init_microcode(rdev); 2983 if (r) { 2984 DRM_ERROR("Failed to load firmware!\n"); 2985 return r; 2986 } 2987 } 2988 r = ni_mc_load_microcode(rdev); 2989 if (r) { 2990 DRM_ERROR("Failed to load MC firmware!\n"); 2991 return r; 2992 } 2993 } else { 2994 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2995 r = r600_init_microcode(rdev); 2996 if (r) { 2997 DRM_ERROR("Failed to load firmware!\n"); 2998 return r; 2999 } 3000 } 3001 } 3002 3003 evergreen_mc_program(rdev); 3004 if (rdev->flags & RADEON_IS_AGP) { 3005 evergreen_agp_enable(rdev); 3006 } else { 3007 r = evergreen_pcie_gart_enable(rdev); 3008 if (r) 3009 return r; 3010 } 3011 evergreen_gpu_init(rdev); 3012 3013 r = evergreen_blit_init(rdev); 3014 if (r) { 3015 evergreen_blit_fini(rdev); 3016 rdev->asic->copy = NULL; 3017 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 3018 } 3019 3020 /* allocate wb buffer */ 3021 r = radeon_wb_init(rdev); 3022 if (r) 3023 return r; 3024 3025 /* Enable IRQ */ 3026 r = r600_irq_init(rdev); 3027 if (r) { 3028 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3029 radeon_irq_kms_fini(rdev); 3030 return r; 3031 } 3032 evergreen_irq_set(rdev); 3033 3034 r = radeon_ring_init(rdev, rdev->cp.ring_size); 3035 if (r) 3036 return r; 3037 r = evergreen_cp_load_microcode(rdev); 3038 if (r) 3039 return r; 3040 r = evergreen_cp_resume(rdev); 3041 if (r) 3042 return r; 3043 3044 return 0; 3045 } 3046 3047 int evergreen_resume(struct radeon_device *rdev) 3048 { 3049 int r; 3050 3051 /* reset the asic, the gfx blocks are often in a bad state 3052 * after the driver is unloaded or after a resume 3053 */ 3054 if (radeon_asic_reset(rdev)) 3055 dev_warn(rdev->dev, "GPU reset failed !\n"); 3056 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 3057 * posting will perform necessary task to bring back GPU into good 3058 * shape. 3059 */ 3060 /* post card */ 3061 atom_asic_init(rdev->mode_info.atom_context); 3062 3063 r = evergreen_startup(rdev); 3064 if (r) { 3065 DRM_ERROR("evergreen startup failed on resume\n"); 3066 return r; 3067 } 3068 3069 r = r600_ib_test(rdev); 3070 if (r) { 3071 DRM_ERROR("radeon: failed testing IB (%d).\n", r); 3072 return r; 3073 } 3074 3075 return r; 3076 3077 } 3078 3079 int evergreen_suspend(struct radeon_device *rdev) 3080 { 3081 int r; 3082 3083 /* FIXME: we should wait for ring to be empty */ 3084 r700_cp_stop(rdev); 3085 rdev->cp.ready = false; 3086 evergreen_irq_suspend(rdev); 3087 radeon_wb_disable(rdev); 3088 evergreen_pcie_gart_disable(rdev); 3089 3090 /* unpin shaders bo */ 3091 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 3092 if (likely(r == 0)) { 3093 radeon_bo_unpin(rdev->r600_blit.shader_obj); 3094 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 3095 } 3096 3097 return 0; 3098 } 3099 3100 int evergreen_copy_blit(struct radeon_device *rdev, 3101 uint64_t src_offset, uint64_t dst_offset, 3102 unsigned num_pages, struct radeon_fence *fence) 3103 { 3104 int r; 3105 3106 mutex_lock(&rdev->r600_blit.mutex); 3107 rdev->r600_blit.vb_ib = NULL; 3108 r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); 3109 if (r) { 3110 if (rdev->r600_blit.vb_ib) 3111 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); 3112 mutex_unlock(&rdev->r600_blit.mutex); 3113 return r; 3114 } 3115 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); 3116 evergreen_blit_done_copy(rdev, fence); 3117 mutex_unlock(&rdev->r600_blit.mutex); 3118 return 0; 3119 } 3120 3121 /* Plan is to move initialization in that function and use 3122 * helper function so that radeon_device_init pretty much 3123 * do nothing more than calling asic specific function. This 3124 * should also allow to remove a bunch of callback function 3125 * like vram_info. 3126 */ 3127 int evergreen_init(struct radeon_device *rdev) 3128 { 3129 int r; 3130 3131 /* This don't do much */ 3132 r = radeon_gem_init(rdev); 3133 if (r) 3134 return r; 3135 /* Read BIOS */ 3136 if (!radeon_get_bios(rdev)) { 3137 if (ASIC_IS_AVIVO(rdev)) 3138 return -EINVAL; 3139 } 3140 /* Must be an ATOMBIOS */ 3141 if (!rdev->is_atom_bios) { 3142 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n"); 3143 return -EINVAL; 3144 } 3145 r = radeon_atombios_init(rdev); 3146 if (r) 3147 return r; 3148 /* reset the asic, the gfx blocks are often in a bad state 3149 * after the driver is unloaded or after a resume 3150 */ 3151 if (radeon_asic_reset(rdev)) 3152 dev_warn(rdev->dev, "GPU reset failed !\n"); 3153 /* Post card if necessary */ 3154 if (!radeon_card_posted(rdev)) { 3155 if (!rdev->bios) { 3156 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3157 return -EINVAL; 3158 } 3159 DRM_INFO("GPU not posted. posting now...\n"); 3160 atom_asic_init(rdev->mode_info.atom_context); 3161 } 3162 /* Initialize scratch registers */ 3163 r600_scratch_init(rdev); 3164 /* Initialize surface registers */ 3165 radeon_surface_init(rdev); 3166 /* Initialize clocks */ 3167 radeon_get_clock_info(rdev->ddev); 3168 /* Fence driver */ 3169 r = radeon_fence_driver_init(rdev); 3170 if (r) 3171 return r; 3172 /* initialize AGP */ 3173 if (rdev->flags & RADEON_IS_AGP) { 3174 r = radeon_agp_init(rdev); 3175 if (r) 3176 radeon_agp_disable(rdev); 3177 } 3178 /* initialize memory controller */ 3179 r = evergreen_mc_init(rdev); 3180 if (r) 3181 return r; 3182 /* Memory manager */ 3183 r = radeon_bo_init(rdev); 3184 if (r) 3185 return r; 3186 3187 r = radeon_irq_kms_init(rdev); 3188 if (r) 3189 return r; 3190 3191 rdev->cp.ring_obj = NULL; 3192 r600_ring_init(rdev, 1024 * 1024); 3193 3194 rdev->ih.ring_obj = NULL; 3195 r600_ih_ring_init(rdev, 64 * 1024); 3196 3197 r = r600_pcie_gart_init(rdev); 3198 if (r) 3199 return r; 3200 3201 rdev->accel_working = true; 3202 r = evergreen_startup(rdev); 3203 if (r) { 3204 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3205 r700_cp_fini(rdev); 3206 r600_irq_fini(rdev); 3207 radeon_wb_fini(rdev); 3208 radeon_irq_kms_fini(rdev); 3209 evergreen_pcie_gart_fini(rdev); 3210 rdev->accel_working = false; 3211 } 3212 if (rdev->accel_working) { 3213 r = radeon_ib_pool_init(rdev); 3214 if (r) { 3215 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); 3216 rdev->accel_working = false; 3217 } 3218 r = r600_ib_test(rdev); 3219 if (r) { 3220 DRM_ERROR("radeon: failed testing IB (%d).\n", r); 3221 rdev->accel_working = false; 3222 } 3223 } 3224 return 0; 3225 } 3226 3227 void evergreen_fini(struct radeon_device *rdev) 3228 { 3229 evergreen_blit_fini(rdev); 3230 r700_cp_fini(rdev); 3231 r600_irq_fini(rdev); 3232 radeon_wb_fini(rdev); 3233 radeon_irq_kms_fini(rdev); 3234 evergreen_pcie_gart_fini(rdev); 3235 radeon_gem_fini(rdev); 3236 radeon_fence_driver_fini(rdev); 3237 radeon_agp_fini(rdev); 3238 radeon_bo_fini(rdev); 3239 radeon_atombios_fini(rdev); 3240 kfree(rdev->bios); 3241 rdev->bios = NULL; 3242 } 3243 3244 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev) 3245 { 3246 u32 link_width_cntl, speed_cntl; 3247 3248 if (radeon_pcie_gen2 == 0) 3249 return; 3250 3251 if (rdev->flags & RADEON_IS_IGP) 3252 return; 3253 3254 if (!(rdev->flags & RADEON_IS_PCIE)) 3255 return; 3256 3257 /* x2 cards have a special sequence */ 3258 if (ASIC_IS_X2(rdev)) 3259 return; 3260 3261 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3262 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || 3263 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 3264 3265 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 3266 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 3267 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 3268 3269 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3270 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 3271 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3272 3273 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3274 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; 3275 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3276 3277 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3278 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 3279 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3280 3281 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3282 speed_cntl |= LC_GEN2_EN_STRAP; 3283 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3284 3285 } else { 3286 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 3287 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 3288 if (1) 3289 link_width_cntl |= LC_UPCONFIGURE_DIS; 3290 else 3291 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 3292 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 3293 } 3294 } 3295