1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/hdmi.h> 24 #include <drm/drmP.h> 25 #include "radeon.h" 26 #include "radeon_audio.h" 27 #include "sid.h" 28 29 #define DCE8_DCCG_AUDIO_DTO1_PHASE 0x05b8 30 #define DCE8_DCCG_AUDIO_DTO1_MODULE 0x05bc 31 32 u32 dce6_endpoint_rreg(struct radeon_device *rdev, 33 u32 block_offset, u32 reg) 34 { 35 unsigned long flags; 36 u32 r; 37 38 spin_lock_irqsave(&rdev->end_idx_lock, flags); 39 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 40 r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); 41 spin_unlock_irqrestore(&rdev->end_idx_lock, flags); 42 43 return r; 44 } 45 46 void dce6_endpoint_wreg(struct radeon_device *rdev, 47 u32 block_offset, u32 reg, u32 v) 48 { 49 unsigned long flags; 50 51 spin_lock_irqsave(&rdev->end_idx_lock, flags); 52 if (ASIC_IS_DCE8(rdev)) 53 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 54 else 55 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, 56 AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg)); 57 WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); 58 spin_unlock_irqrestore(&rdev->end_idx_lock, flags); 59 } 60 61 static void dce6_afmt_get_connected_pins(struct radeon_device *rdev) 62 { 63 int i; 64 u32 offset, tmp; 65 66 for (i = 0; i < rdev->audio.num_pins; i++) { 67 offset = rdev->audio.pin[i].offset; 68 tmp = RREG32_ENDPOINT(offset, 69 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 70 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) 71 rdev->audio.pin[i].connected = false; 72 else 73 rdev->audio.pin[i].connected = true; 74 } 75 } 76 77 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev) 78 { 79 int i; 80 81 dce6_afmt_get_connected_pins(rdev); 82 83 for (i = 0; i < rdev->audio.num_pins; i++) { 84 if (rdev->audio.pin[i].connected) 85 return &rdev->audio.pin[i]; 86 } 87 DRM_ERROR("No connected audio pins found!\n"); 88 return NULL; 89 } 90 91 void dce6_afmt_select_pin(struct drm_encoder *encoder) 92 { 93 struct radeon_device *rdev = encoder->dev->dev_private; 94 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 95 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 96 97 if (!dig || !dig->afmt || !dig->pin) 98 return; 99 100 WREG32(AFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, 101 AFMT_AUDIO_SRC_SELECT(dig->pin->id)); 102 } 103 104 void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, 105 struct drm_connector *connector, 106 struct drm_display_mode *mode) 107 { 108 struct radeon_device *rdev = encoder->dev->dev_private; 109 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 110 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 111 u32 tmp = 0; 112 113 if (!dig || !dig->afmt || !dig->pin) 114 return; 115 116 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 117 if (connector->latency_present[1]) 118 tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | 119 AUDIO_LIPSYNC(connector->audio_latency[1]); 120 else 121 tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); 122 } else { 123 if (connector->latency_present[0]) 124 tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | 125 AUDIO_LIPSYNC(connector->audio_latency[0]); 126 else 127 tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); 128 } 129 WREG32_ENDPOINT(dig->pin->offset, 130 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 131 } 132 133 void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, 134 u8 *sadb, int sad_count) 135 { 136 struct radeon_device *rdev = encoder->dev->dev_private; 137 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 138 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 139 u32 tmp; 140 141 if (!dig || !dig->afmt || !dig->pin) 142 return; 143 144 /* program the speaker allocation */ 145 tmp = RREG32_ENDPOINT(dig->pin->offset, 146 AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 147 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); 148 /* set HDMI mode */ 149 tmp |= HDMI_CONNECTION; 150 if (sad_count) 151 tmp |= SPEAKER_ALLOCATION(sadb[0]); 152 else 153 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 154 WREG32_ENDPOINT(dig->pin->offset, 155 AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 156 } 157 158 void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, 159 u8 *sadb, int sad_count) 160 { 161 struct radeon_device *rdev = encoder->dev->dev_private; 162 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 163 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 164 u32 tmp; 165 166 if (!dig || !dig->afmt || !dig->pin) 167 return; 168 169 /* program the speaker allocation */ 170 tmp = RREG32_ENDPOINT(dig->pin->offset, 171 AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 172 tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); 173 /* set DP mode */ 174 tmp |= DP_CONNECTION; 175 if (sad_count) 176 tmp |= SPEAKER_ALLOCATION(sadb[0]); 177 else 178 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 179 WREG32_ENDPOINT(dig->pin->offset, 180 AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 181 } 182 183 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder, 184 struct cea_sad *sads, int sad_count) 185 { 186 int i; 187 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 188 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 189 struct radeon_device *rdev = encoder->dev->dev_private; 190 static const u16 eld_reg_to_type[][2] = { 191 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 192 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 193 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 194 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 195 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 196 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 197 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 198 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 199 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 200 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 201 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 202 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 203 }; 204 205 if (!dig || !dig->afmt || !dig->pin) 206 return; 207 208 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 209 u32 value = 0; 210 u8 stereo_freqs = 0; 211 int max_channels = -1; 212 int j; 213 214 for (j = 0; j < sad_count; j++) { 215 struct cea_sad *sad = &sads[j]; 216 217 if (sad->format == eld_reg_to_type[i][1]) { 218 if (sad->channels > max_channels) { 219 value = MAX_CHANNELS(sad->channels) | 220 DESCRIPTOR_BYTE_2(sad->byte2) | 221 SUPPORTED_FREQUENCIES(sad->freq); 222 max_channels = sad->channels; 223 } 224 225 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 226 stereo_freqs |= sad->freq; 227 else 228 break; 229 } 230 } 231 232 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); 233 234 WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value); 235 } 236 } 237 238 void dce6_audio_enable(struct radeon_device *rdev, 239 struct r600_audio_pin *pin, 240 u8 enable_mask) 241 { 242 if (!pin) 243 return; 244 245 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 246 enable_mask ? AUDIO_ENABLED : 0); 247 } 248 249 void dce6_hdmi_audio_set_dto(struct radeon_device *rdev, 250 struct radeon_crtc *crtc, unsigned int clock) 251 { 252 /* Two dtos; generally use dto0 for HDMI */ 253 u32 value = 0; 254 255 if (crtc) 256 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); 257 258 WREG32(DCCG_AUDIO_DTO_SOURCE, value); 259 260 /* Express [24MHz / target pixel clock] as an exact rational 261 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 262 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 263 */ 264 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000); 265 WREG32(DCCG_AUDIO_DTO0_MODULE, clock); 266 } 267 268 void dce6_dp_audio_set_dto(struct radeon_device *rdev, 269 struct radeon_crtc *crtc, unsigned int clock) 270 { 271 /* Two dtos; generally use dto1 for DP */ 272 u32 value = 0; 273 value |= DCCG_AUDIO_DTO_SEL; 274 275 if (crtc) 276 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); 277 278 WREG32(DCCG_AUDIO_DTO_SOURCE, value); 279 280 /* Express [24MHz / target pixel clock] as an exact rational 281 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 282 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 283 */ 284 if (ASIC_IS_DCE8(rdev)) { 285 WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000); 286 WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock); 287 } else { 288 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); 289 WREG32(DCCG_AUDIO_DTO1_MODULE, clock); 290 } 291 } 292