1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __CYPRESS_DPM_H__ 24 #define __CYPRESS_DPM_H__ 25 26 #include "rv770_dpm.h" 27 #include "evergreen_smc.h" 28 29 struct evergreen_mc_reg_entry { 30 u32 mclk_max; 31 u32 mc_data[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 32 }; 33 34 struct evergreen_mc_reg_table { 35 u8 last; 36 u8 num_entries; 37 u16 valid_flag; 38 struct evergreen_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 39 SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; 40 }; 41 42 struct evergreen_ulv_param { 43 bool supported; 44 struct rv7xx_pl *pl; 45 }; 46 47 struct evergreen_arb_registers { 48 u32 mc_arb_dram_timing; 49 u32 mc_arb_dram_timing2; 50 u32 mc_arb_rfsh_rate; 51 u32 mc_arb_burst_time; 52 }; 53 54 struct evergreen_power_info { 55 /* must be first! */ 56 struct rv7xx_power_info rv7xx; 57 /* flags */ 58 bool vddci_control; 59 bool dynamic_ac_timing; 60 bool abm; 61 bool mcls; 62 bool light_sleep; 63 bool memory_transition; 64 bool pcie_performance_request; 65 bool pcie_performance_request_registered; 66 bool sclk_deep_sleep; 67 bool dll_default_on; 68 bool ls_clock_gating; 69 /* stored values */ 70 u16 acpi_vddci; 71 u8 mvdd_high_index; 72 u8 mvdd_low_index; 73 u32 mclk_edc_wr_enable_threshold; 74 struct evergreen_mc_reg_table mc_reg_table; 75 struct atom_voltage_table vddc_voltage_table; 76 struct atom_voltage_table vddci_voltage_table; 77 struct evergreen_arb_registers bootup_arb_registers; 78 struct evergreen_ulv_param ulv; 79 /* smc offsets */ 80 u16 mc_reg_table_start; 81 }; 82 83 #define CYPRESS_HASI_DFLT 400000 84 #define CYPRESS_MGCGTTLOCAL0_DFLT 0x00000000 85 #define CYPRESS_MGCGTTLOCAL1_DFLT 0x00000000 86 #define CYPRESS_MGCGTTLOCAL2_DFLT 0x00000000 87 #define CYPRESS_MGCGTTLOCAL3_DFLT 0x00000000 88 #define CYPRESS_MGCGCGTSSMCTRL_DFLT 0x81944bc0 89 #define REDWOOD_MGCGCGTSSMCTRL_DFLT 0x6e944040 90 #define CEDAR_MGCGCGTSSMCTRL_DFLT 0x46944040 91 #define CYPRESS_VRC_DFLT 0xC00033 92 93 #define PCIE_PERF_REQ_REMOVE_REGISTRY 0 94 #define PCIE_PERF_REQ_FORCE_LOWPOWER 1 95 #define PCIE_PERF_REQ_PECI_GEN1 2 96 #define PCIE_PERF_REQ_PECI_GEN2 3 97 #define PCIE_PERF_REQ_PECI_GEN3 4 98 99 int cypress_convert_power_level_to_smc(struct radeon_device *rdev, 100 struct rv7xx_pl *pl, 101 RV770_SMC_HW_PERFORMANCE_LEVEL *level, 102 u8 watermark_level); 103 int cypress_populate_smc_acpi_state(struct radeon_device *rdev, 104 RV770_SMC_STATETABLE *table); 105 int cypress_populate_smc_voltage_tables(struct radeon_device *rdev, 106 RV770_SMC_STATETABLE *table); 107 int cypress_populate_smc_initial_state(struct radeon_device *rdev, 108 struct radeon_ps *radeon_initial_state, 109 RV770_SMC_STATETABLE *table); 110 u32 cypress_calculate_burst_time(struct radeon_device *rdev, 111 u32 engine_clock, u32 memory_clock); 112 void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev); 113 int cypress_upload_sw_state(struct radeon_device *rdev); 114 int cypress_upload_mc_reg_table(struct radeon_device *rdev); 115 void cypress_program_memory_timing_parameters(struct radeon_device *rdev); 116 void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev); 117 int cypress_construct_voltage_tables(struct radeon_device *rdev); 118 int cypress_get_mvdd_configuration(struct radeon_device *rdev); 119 void cypress_enable_spread_spectrum(struct radeon_device *rdev, 120 bool enable); 121 void cypress_enable_display_gap(struct radeon_device *rdev); 122 int cypress_get_table_locations(struct radeon_device *rdev); 123 int cypress_populate_mc_reg_table(struct radeon_device *rdev); 124 void cypress_program_response_times(struct radeon_device *rdev); 125 int cypress_notify_smc_display_change(struct radeon_device *rdev, 126 bool has_display); 127 void cypress_enable_sclk_control(struct radeon_device *rdev, 128 bool enable); 129 void cypress_enable_mclk_control(struct radeon_device *rdev, 130 bool enable); 131 void cypress_start_dpm(struct radeon_device *rdev); 132 void cypress_advertise_gen2_capability(struct radeon_device *rdev); 133 134 #endif 135