18cc1a532SAlex Deucher /* 28cc1a532SAlex Deucher * Copyright 2012 Advanced Micro Devices, Inc. 38cc1a532SAlex Deucher * 48cc1a532SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 58cc1a532SAlex Deucher * copy of this software and associated documentation files (the "Software"), 68cc1a532SAlex Deucher * to deal in the Software without restriction, including without limitation 78cc1a532SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 88cc1a532SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 98cc1a532SAlex Deucher * Software is furnished to do so, subject to the following conditions: 108cc1a532SAlex Deucher * 118cc1a532SAlex Deucher * The above copyright notice and this permission notice shall be included in 128cc1a532SAlex Deucher * all copies or substantial portions of the Software. 138cc1a532SAlex Deucher * 148cc1a532SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 158cc1a532SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 168cc1a532SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 178cc1a532SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 188cc1a532SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 198cc1a532SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 208cc1a532SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 218cc1a532SAlex Deucher * 228cc1a532SAlex Deucher * Authors: Alex Deucher 238cc1a532SAlex Deucher */ 248cc1a532SAlex Deucher #ifndef CIK_H 258cc1a532SAlex Deucher #define CIK_H 268cc1a532SAlex Deucher 278cc1a532SAlex Deucher #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 288cc1a532SAlex Deucher 298cc1a532SAlex Deucher #define CIK_RB_BITMAP_WIDTH_PER_SH 2 308cc1a532SAlex Deucher 311c49165dSAlex Deucher #define VGA_HDP_CONTROL 0x328 321c49165dSAlex Deucher #define VGA_MEMORY_DISABLE (1 << 4) 331c49165dSAlex Deucher 348cc1a532SAlex Deucher #define DMIF_ADDR_CALC 0xC00 358cc1a532SAlex Deucher 361c49165dSAlex Deucher #define SRBM_GFX_CNTL 0xE44 371c49165dSAlex Deucher #define PIPEID(x) ((x) << 0) 381c49165dSAlex Deucher #define MEID(x) ((x) << 2) 391c49165dSAlex Deucher #define VMID(x) ((x) << 4) 401c49165dSAlex Deucher #define QUEUEID(x) ((x) << 8) 411c49165dSAlex Deucher 426f2043ceSAlex Deucher #define SRBM_STATUS2 0xE4C 436f2043ceSAlex Deucher #define SRBM_STATUS 0xE50 446f2043ceSAlex Deucher 4521a93e13SAlex Deucher #define SRBM_SOFT_RESET 0xE60 4621a93e13SAlex Deucher #define SOFT_RESET_BIF (1 << 1) 4721a93e13SAlex Deucher #define SOFT_RESET_R0PLL (1 << 4) 4821a93e13SAlex Deucher #define SOFT_RESET_DC (1 << 5) 4921a93e13SAlex Deucher #define SOFT_RESET_SDMA1 (1 << 6) 5021a93e13SAlex Deucher #define SOFT_RESET_GRBM (1 << 8) 5121a93e13SAlex Deucher #define SOFT_RESET_HDP (1 << 9) 5221a93e13SAlex Deucher #define SOFT_RESET_IH (1 << 10) 5321a93e13SAlex Deucher #define SOFT_RESET_MC (1 << 11) 5421a93e13SAlex Deucher #define SOFT_RESET_ROM (1 << 14) 5521a93e13SAlex Deucher #define SOFT_RESET_SEM (1 << 15) 5621a93e13SAlex Deucher #define SOFT_RESET_VMC (1 << 17) 5721a93e13SAlex Deucher #define SOFT_RESET_SDMA (1 << 20) 5821a93e13SAlex Deucher #define SOFT_RESET_TST (1 << 21) 5921a93e13SAlex Deucher #define SOFT_RESET_REGBB (1 << 22) 6021a93e13SAlex Deucher #define SOFT_RESET_ORB (1 << 23) 6121a93e13SAlex Deucher #define SOFT_RESET_VCE (1 << 24) 6221a93e13SAlex Deucher 631c49165dSAlex Deucher #define VM_L2_CNTL 0x1400 641c49165dSAlex Deucher #define ENABLE_L2_CACHE (1 << 0) 651c49165dSAlex Deucher #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 661c49165dSAlex Deucher #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 671c49165dSAlex Deucher #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 681c49165dSAlex Deucher #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 691c49165dSAlex Deucher #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 701c49165dSAlex Deucher #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 711c49165dSAlex Deucher #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 721c49165dSAlex Deucher #define VM_L2_CNTL2 0x1404 731c49165dSAlex Deucher #define INVALIDATE_ALL_L1_TLBS (1 << 0) 741c49165dSAlex Deucher #define INVALIDATE_L2_CACHE (1 << 1) 751c49165dSAlex Deucher #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 761c49165dSAlex Deucher #define INVALIDATE_PTE_AND_PDE_CACHES 0 771c49165dSAlex Deucher #define INVALIDATE_ONLY_PTE_CACHES 1 781c49165dSAlex Deucher #define INVALIDATE_ONLY_PDE_CACHES 2 791c49165dSAlex Deucher #define VM_L2_CNTL3 0x1408 801c49165dSAlex Deucher #define BANK_SELECT(x) ((x) << 0) 811c49165dSAlex Deucher #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 821c49165dSAlex Deucher #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 831c49165dSAlex Deucher #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 841c49165dSAlex Deucher #define VM_L2_STATUS 0x140C 851c49165dSAlex Deucher #define L2_BUSY (1 << 0) 861c49165dSAlex Deucher #define VM_CONTEXT0_CNTL 0x1410 871c49165dSAlex Deucher #define ENABLE_CONTEXT (1 << 0) 881c49165dSAlex Deucher #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 89a00024b0SAlex Deucher #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 901c49165dSAlex Deucher #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 91a00024b0SAlex Deucher #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 92a00024b0SAlex Deucher #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 93a00024b0SAlex Deucher #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 94a00024b0SAlex Deucher #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 95a00024b0SAlex Deucher #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 96a00024b0SAlex Deucher #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 97a00024b0SAlex Deucher #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 98a00024b0SAlex Deucher #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 99a00024b0SAlex Deucher #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 100a00024b0SAlex Deucher #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 1011c49165dSAlex Deucher #define VM_CONTEXT1_CNTL 0x1414 1021c49165dSAlex Deucher #define VM_CONTEXT0_CNTL2 0x1430 1031c49165dSAlex Deucher #define VM_CONTEXT1_CNTL2 0x1434 1041c49165dSAlex Deucher #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 1051c49165dSAlex Deucher #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 1061c49165dSAlex Deucher #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 1071c49165dSAlex Deucher #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 1081c49165dSAlex Deucher #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 1091c49165dSAlex Deucher #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 1101c49165dSAlex Deucher #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 1111c49165dSAlex Deucher #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 1121c49165dSAlex Deucher 1131c49165dSAlex Deucher #define VM_INVALIDATE_REQUEST 0x1478 1141c49165dSAlex Deucher #define VM_INVALIDATE_RESPONSE 0x147c 1151c49165dSAlex Deucher 1169d97c99bSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 1179d97c99bSAlex Deucher 1189d97c99bSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 1199d97c99bSAlex Deucher 1201c49165dSAlex Deucher #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 1211c49165dSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 1221c49165dSAlex Deucher 1231c49165dSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 1241c49165dSAlex Deucher #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 1251c49165dSAlex Deucher #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 1261c49165dSAlex Deucher #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 1271c49165dSAlex Deucher #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 1281c49165dSAlex Deucher #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 1291c49165dSAlex Deucher #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 1301c49165dSAlex Deucher #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 1311c49165dSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 1321c49165dSAlex Deucher #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 1331c49165dSAlex Deucher 1341c49165dSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 1351c49165dSAlex Deucher #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 1361c49165dSAlex Deucher 1378cc1a532SAlex Deucher #define MC_SHARED_CHMAP 0x2004 1388cc1a532SAlex Deucher #define NOOFCHAN_SHIFT 12 1398cc1a532SAlex Deucher #define NOOFCHAN_MASK 0x0000f000 1408cc1a532SAlex Deucher #define MC_SHARED_CHREMAP 0x2008 1418cc1a532SAlex Deucher 1421c49165dSAlex Deucher #define CHUB_CONTROL 0x1864 1431c49165dSAlex Deucher #define BYPASS_VM (1 << 0) 1441c49165dSAlex Deucher 1451c49165dSAlex Deucher #define MC_VM_FB_LOCATION 0x2024 1461c49165dSAlex Deucher #define MC_VM_AGP_TOP 0x2028 1471c49165dSAlex Deucher #define MC_VM_AGP_BOT 0x202C 1481c49165dSAlex Deucher #define MC_VM_AGP_BASE 0x2030 1491c49165dSAlex Deucher #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 1501c49165dSAlex Deucher #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 1511c49165dSAlex Deucher #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 1521c49165dSAlex Deucher 1531c49165dSAlex Deucher #define MC_VM_MX_L1_TLB_CNTL 0x2064 1541c49165dSAlex Deucher #define ENABLE_L1_TLB (1 << 0) 1551c49165dSAlex Deucher #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 1561c49165dSAlex Deucher #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 1571c49165dSAlex Deucher #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 1581c49165dSAlex Deucher #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 1591c49165dSAlex Deucher #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 1601c49165dSAlex Deucher #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 1611c49165dSAlex Deucher #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 1621c49165dSAlex Deucher #define MC_VM_FB_OFFSET 0x2068 1631c49165dSAlex Deucher 164bc8273feSAlex Deucher #define MC_SHARED_BLACKOUT_CNTL 0x20ac 165bc8273feSAlex Deucher 1668cc1a532SAlex Deucher #define MC_ARB_RAMCFG 0x2760 1678cc1a532SAlex Deucher #define NOOFBANK_SHIFT 0 1688cc1a532SAlex Deucher #define NOOFBANK_MASK 0x00000003 1698cc1a532SAlex Deucher #define NOOFRANK_SHIFT 2 1708cc1a532SAlex Deucher #define NOOFRANK_MASK 0x00000004 1718cc1a532SAlex Deucher #define NOOFROWS_SHIFT 3 1728cc1a532SAlex Deucher #define NOOFROWS_MASK 0x00000038 1738cc1a532SAlex Deucher #define NOOFCOLS_SHIFT 6 1748cc1a532SAlex Deucher #define NOOFCOLS_MASK 0x000000C0 1758cc1a532SAlex Deucher #define CHANSIZE_SHIFT 8 1768cc1a532SAlex Deucher #define CHANSIZE_MASK 0x00000100 1778cc1a532SAlex Deucher #define NOOFGROUPS_SHIFT 12 1788cc1a532SAlex Deucher #define NOOFGROUPS_MASK 0x00001000 1798cc1a532SAlex Deucher 180bc8273feSAlex Deucher #define MC_SEQ_SUP_CNTL 0x28c8 181bc8273feSAlex Deucher #define RUN_MASK (1 << 0) 182bc8273feSAlex Deucher #define MC_SEQ_SUP_PGM 0x28cc 183bc8273feSAlex Deucher 184bc8273feSAlex Deucher #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 185bc8273feSAlex Deucher #define TRAIN_DONE_D0 (1 << 30) 186bc8273feSAlex Deucher #define TRAIN_DONE_D1 (1 << 31) 187bc8273feSAlex Deucher 188bc8273feSAlex Deucher #define MC_IO_PAD_CNTL_D0 0x29d0 189bc8273feSAlex Deucher #define MEM_FALL_OUT_CMD (1 << 8) 190bc8273feSAlex Deucher 191bc8273feSAlex Deucher #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 192bc8273feSAlex Deucher #define MC_SEQ_IO_DEBUG_DATA 0x2a48 193bc8273feSAlex Deucher 1948cc1a532SAlex Deucher #define HDP_HOST_PATH_CNTL 0x2C00 1958cc1a532SAlex Deucher #define HDP_NONSURFACE_BASE 0x2C04 1968cc1a532SAlex Deucher #define HDP_NONSURFACE_INFO 0x2C08 1978cc1a532SAlex Deucher #define HDP_NONSURFACE_SIZE 0x2C0C 1988cc1a532SAlex Deucher 1998cc1a532SAlex Deucher #define HDP_ADDR_CONFIG 0x2F48 2008cc1a532SAlex Deucher #define HDP_MISC_CNTL 0x2F4C 2018cc1a532SAlex Deucher #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 2028cc1a532SAlex Deucher 203a59781bbSAlex Deucher #define IH_RB_CNTL 0x3e00 204a59781bbSAlex Deucher # define IH_RB_ENABLE (1 << 0) 205a59781bbSAlex Deucher # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 206a59781bbSAlex Deucher # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 207a59781bbSAlex Deucher # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 208a59781bbSAlex Deucher # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 209a59781bbSAlex Deucher # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 210a59781bbSAlex Deucher # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 211a59781bbSAlex Deucher #define IH_RB_BASE 0x3e04 212a59781bbSAlex Deucher #define IH_RB_RPTR 0x3e08 213a59781bbSAlex Deucher #define IH_RB_WPTR 0x3e0c 214a59781bbSAlex Deucher # define RB_OVERFLOW (1 << 0) 215a59781bbSAlex Deucher # define WPTR_OFFSET_MASK 0x3fffc 216a59781bbSAlex Deucher #define IH_RB_WPTR_ADDR_HI 0x3e10 217a59781bbSAlex Deucher #define IH_RB_WPTR_ADDR_LO 0x3e14 218a59781bbSAlex Deucher #define IH_CNTL 0x3e18 219a59781bbSAlex Deucher # define ENABLE_INTR (1 << 0) 220a59781bbSAlex Deucher # define IH_MC_SWAP(x) ((x) << 1) 221a59781bbSAlex Deucher # define IH_MC_SWAP_NONE 0 222a59781bbSAlex Deucher # define IH_MC_SWAP_16BIT 1 223a59781bbSAlex Deucher # define IH_MC_SWAP_32BIT 2 224a59781bbSAlex Deucher # define IH_MC_SWAP_64BIT 3 225a59781bbSAlex Deucher # define RPTR_REARM (1 << 4) 226a59781bbSAlex Deucher # define MC_WRREQ_CREDIT(x) ((x) << 15) 227a59781bbSAlex Deucher # define MC_WR_CLEAN_CNT(x) ((x) << 20) 228a59781bbSAlex Deucher # define MC_VMID(x) ((x) << 25) 229a59781bbSAlex Deucher 2301c49165dSAlex Deucher #define CONFIG_MEMSIZE 0x5428 2311c49165dSAlex Deucher 232a59781bbSAlex Deucher #define INTERRUPT_CNTL 0x5468 233a59781bbSAlex Deucher # define IH_DUMMY_RD_OVERRIDE (1 << 0) 234a59781bbSAlex Deucher # define IH_DUMMY_RD_EN (1 << 1) 235a59781bbSAlex Deucher # define IH_REQ_NONSNOOP_EN (1 << 3) 236a59781bbSAlex Deucher # define GEN_IH_INT_EN (1 << 8) 237a59781bbSAlex Deucher #define INTERRUPT_CNTL2 0x546c 238a59781bbSAlex Deucher 2391c49165dSAlex Deucher #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 2401c49165dSAlex Deucher 2418cc1a532SAlex Deucher #define BIF_FB_EN 0x5490 2428cc1a532SAlex Deucher #define FB_READ_EN (1 << 0) 2438cc1a532SAlex Deucher #define FB_WRITE_EN (1 << 1) 2448cc1a532SAlex Deucher 2451c49165dSAlex Deucher #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 2461c49165dSAlex Deucher 2472cae3bc3SAlex Deucher #define GPU_HDP_FLUSH_REQ 0x54DC 2482cae3bc3SAlex Deucher #define GPU_HDP_FLUSH_DONE 0x54E0 2492cae3bc3SAlex Deucher #define CP0 (1 << 0) 2502cae3bc3SAlex Deucher #define CP1 (1 << 1) 2512cae3bc3SAlex Deucher #define CP2 (1 << 2) 2522cae3bc3SAlex Deucher #define CP3 (1 << 3) 2532cae3bc3SAlex Deucher #define CP4 (1 << 4) 2542cae3bc3SAlex Deucher #define CP5 (1 << 5) 2552cae3bc3SAlex Deucher #define CP6 (1 << 6) 2562cae3bc3SAlex Deucher #define CP7 (1 << 7) 2572cae3bc3SAlex Deucher #define CP8 (1 << 8) 2582cae3bc3SAlex Deucher #define CP9 (1 << 9) 2592cae3bc3SAlex Deucher #define SDMA0 (1 << 10) 2602cae3bc3SAlex Deucher #define SDMA1 (1 << 11) 2612cae3bc3SAlex Deucher 262*cd84a27dSAlex Deucher /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */ 263*cd84a27dSAlex Deucher #define LB_MEMORY_CTRL 0x6b04 264*cd84a27dSAlex Deucher #define LB_MEMORY_SIZE(x) ((x) << 0) 265*cd84a27dSAlex Deucher #define LB_MEMORY_CONFIG(x) ((x) << 20) 266*cd84a27dSAlex Deucher 267*cd84a27dSAlex Deucher #define DPG_WATERMARK_MASK_CONTROL 0x6cc8 268*cd84a27dSAlex Deucher # define LATENCY_WATERMARK_MASK(x) ((x) << 8) 269*cd84a27dSAlex Deucher #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 270*cd84a27dSAlex Deucher # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 271*cd84a27dSAlex Deucher # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 272*cd84a27dSAlex Deucher 273a59781bbSAlex Deucher /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */ 274a59781bbSAlex Deucher #define LB_VLINE_STATUS 0x6b24 275a59781bbSAlex Deucher # define VLINE_OCCURRED (1 << 0) 276a59781bbSAlex Deucher # define VLINE_ACK (1 << 4) 277a59781bbSAlex Deucher # define VLINE_STAT (1 << 12) 278a59781bbSAlex Deucher # define VLINE_INTERRUPT (1 << 16) 279a59781bbSAlex Deucher # define VLINE_INTERRUPT_TYPE (1 << 17) 280a59781bbSAlex Deucher /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */ 281a59781bbSAlex Deucher #define LB_VBLANK_STATUS 0x6b2c 282a59781bbSAlex Deucher # define VBLANK_OCCURRED (1 << 0) 283a59781bbSAlex Deucher # define VBLANK_ACK (1 << 4) 284a59781bbSAlex Deucher # define VBLANK_STAT (1 << 12) 285a59781bbSAlex Deucher # define VBLANK_INTERRUPT (1 << 16) 286a59781bbSAlex Deucher # define VBLANK_INTERRUPT_TYPE (1 << 17) 287a59781bbSAlex Deucher 288a59781bbSAlex Deucher /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */ 289a59781bbSAlex Deucher #define LB_INTERRUPT_MASK 0x6b20 290a59781bbSAlex Deucher # define VBLANK_INTERRUPT_MASK (1 << 0) 291a59781bbSAlex Deucher # define VLINE_INTERRUPT_MASK (1 << 4) 292a59781bbSAlex Deucher # define VLINE2_INTERRUPT_MASK (1 << 8) 293a59781bbSAlex Deucher 294a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS 0x60f4 295a59781bbSAlex Deucher # define LB_D1_VLINE_INTERRUPT (1 << 2) 296a59781bbSAlex Deucher # define LB_D1_VBLANK_INTERRUPT (1 << 3) 297a59781bbSAlex Deucher # define DC_HPD1_INTERRUPT (1 << 17) 298a59781bbSAlex Deucher # define DC_HPD1_RX_INTERRUPT (1 << 18) 299a59781bbSAlex Deucher # define DACA_AUTODETECT_INTERRUPT (1 << 22) 300a59781bbSAlex Deucher # define DACB_AUTODETECT_INTERRUPT (1 << 23) 301a59781bbSAlex Deucher # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 302a59781bbSAlex Deucher # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 303a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 304a59781bbSAlex Deucher # define LB_D2_VLINE_INTERRUPT (1 << 2) 305a59781bbSAlex Deucher # define LB_D2_VBLANK_INTERRUPT (1 << 3) 306a59781bbSAlex Deucher # define DC_HPD2_INTERRUPT (1 << 17) 307a59781bbSAlex Deucher # define DC_HPD2_RX_INTERRUPT (1 << 18) 308a59781bbSAlex Deucher # define DISP_TIMER_INTERRUPT (1 << 24) 309a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 310a59781bbSAlex Deucher # define LB_D3_VLINE_INTERRUPT (1 << 2) 311a59781bbSAlex Deucher # define LB_D3_VBLANK_INTERRUPT (1 << 3) 312a59781bbSAlex Deucher # define DC_HPD3_INTERRUPT (1 << 17) 313a59781bbSAlex Deucher # define DC_HPD3_RX_INTERRUPT (1 << 18) 314a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 315a59781bbSAlex Deucher # define LB_D4_VLINE_INTERRUPT (1 << 2) 316a59781bbSAlex Deucher # define LB_D4_VBLANK_INTERRUPT (1 << 3) 317a59781bbSAlex Deucher # define DC_HPD4_INTERRUPT (1 << 17) 318a59781bbSAlex Deucher # define DC_HPD4_RX_INTERRUPT (1 << 18) 319a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 320a59781bbSAlex Deucher # define LB_D5_VLINE_INTERRUPT (1 << 2) 321a59781bbSAlex Deucher # define LB_D5_VBLANK_INTERRUPT (1 << 3) 322a59781bbSAlex Deucher # define DC_HPD5_INTERRUPT (1 << 17) 323a59781bbSAlex Deucher # define DC_HPD5_RX_INTERRUPT (1 << 18) 324a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 325a59781bbSAlex Deucher # define LB_D6_VLINE_INTERRUPT (1 << 2) 326a59781bbSAlex Deucher # define LB_D6_VBLANK_INTERRUPT (1 << 3) 327a59781bbSAlex Deucher # define DC_HPD6_INTERRUPT (1 << 17) 328a59781bbSAlex Deucher # define DC_HPD6_RX_INTERRUPT (1 << 18) 329a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 330a59781bbSAlex Deucher 331a59781bbSAlex Deucher #define DAC_AUTODETECT_INT_CONTROL 0x67c8 332a59781bbSAlex Deucher 333a59781bbSAlex Deucher #define DC_HPD1_INT_STATUS 0x601c 334a59781bbSAlex Deucher #define DC_HPD2_INT_STATUS 0x6028 335a59781bbSAlex Deucher #define DC_HPD3_INT_STATUS 0x6034 336a59781bbSAlex Deucher #define DC_HPD4_INT_STATUS 0x6040 337a59781bbSAlex Deucher #define DC_HPD5_INT_STATUS 0x604c 338a59781bbSAlex Deucher #define DC_HPD6_INT_STATUS 0x6058 339a59781bbSAlex Deucher # define DC_HPDx_INT_STATUS (1 << 0) 340a59781bbSAlex Deucher # define DC_HPDx_SENSE (1 << 1) 341a59781bbSAlex Deucher # define DC_HPDx_SENSE_DELAYED (1 << 4) 342a59781bbSAlex Deucher # define DC_HPDx_RX_INT_STATUS (1 << 8) 343a59781bbSAlex Deucher 344a59781bbSAlex Deucher #define DC_HPD1_INT_CONTROL 0x6020 345a59781bbSAlex Deucher #define DC_HPD2_INT_CONTROL 0x602c 346a59781bbSAlex Deucher #define DC_HPD3_INT_CONTROL 0x6038 347a59781bbSAlex Deucher #define DC_HPD4_INT_CONTROL 0x6044 348a59781bbSAlex Deucher #define DC_HPD5_INT_CONTROL 0x6050 349a59781bbSAlex Deucher #define DC_HPD6_INT_CONTROL 0x605c 350a59781bbSAlex Deucher # define DC_HPDx_INT_ACK (1 << 0) 351a59781bbSAlex Deucher # define DC_HPDx_INT_POLARITY (1 << 8) 352a59781bbSAlex Deucher # define DC_HPDx_INT_EN (1 << 16) 353a59781bbSAlex Deucher # define DC_HPDx_RX_INT_ACK (1 << 20) 354a59781bbSAlex Deucher # define DC_HPDx_RX_INT_EN (1 << 24) 355a59781bbSAlex Deucher 356a59781bbSAlex Deucher #define DC_HPD1_CONTROL 0x6024 357a59781bbSAlex Deucher #define DC_HPD2_CONTROL 0x6030 358a59781bbSAlex Deucher #define DC_HPD3_CONTROL 0x603c 359a59781bbSAlex Deucher #define DC_HPD4_CONTROL 0x6048 360a59781bbSAlex Deucher #define DC_HPD5_CONTROL 0x6054 361a59781bbSAlex Deucher #define DC_HPD6_CONTROL 0x6060 362a59781bbSAlex Deucher # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 363a59781bbSAlex Deucher # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 364a59781bbSAlex Deucher # define DC_HPDx_EN (1 << 28) 365a59781bbSAlex Deucher 3668cc1a532SAlex Deucher #define GRBM_CNTL 0x8000 3678cc1a532SAlex Deucher #define GRBM_READ_TIMEOUT(x) ((x) << 0) 3688cc1a532SAlex Deucher 3696f2043ceSAlex Deucher #define GRBM_STATUS2 0x8008 3706f2043ceSAlex Deucher #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F 3716f2043ceSAlex Deucher #define ME0PIPE1_CF_RQ_PENDING (1 << 4) 3726f2043ceSAlex Deucher #define ME0PIPE1_PF_RQ_PENDING (1 << 5) 3736f2043ceSAlex Deucher #define ME1PIPE0_RQ_PENDING (1 << 6) 3746f2043ceSAlex Deucher #define ME1PIPE1_RQ_PENDING (1 << 7) 3756f2043ceSAlex Deucher #define ME1PIPE2_RQ_PENDING (1 << 8) 3766f2043ceSAlex Deucher #define ME1PIPE3_RQ_PENDING (1 << 9) 3776f2043ceSAlex Deucher #define ME2PIPE0_RQ_PENDING (1 << 10) 3786f2043ceSAlex Deucher #define ME2PIPE1_RQ_PENDING (1 << 11) 3796f2043ceSAlex Deucher #define ME2PIPE2_RQ_PENDING (1 << 12) 3806f2043ceSAlex Deucher #define ME2PIPE3_RQ_PENDING (1 << 13) 3816f2043ceSAlex Deucher #define RLC_RQ_PENDING (1 << 14) 3826f2043ceSAlex Deucher #define RLC_BUSY (1 << 24) 3836f2043ceSAlex Deucher #define TC_BUSY (1 << 25) 3846f2043ceSAlex Deucher #define CPF_BUSY (1 << 28) 3856f2043ceSAlex Deucher #define CPC_BUSY (1 << 29) 3866f2043ceSAlex Deucher #define CPG_BUSY (1 << 30) 3876f2043ceSAlex Deucher 3886f2043ceSAlex Deucher #define GRBM_STATUS 0x8010 3896f2043ceSAlex Deucher #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F 3906f2043ceSAlex Deucher #define SRBM_RQ_PENDING (1 << 5) 3916f2043ceSAlex Deucher #define ME0PIPE0_CF_RQ_PENDING (1 << 7) 3926f2043ceSAlex Deucher #define ME0PIPE0_PF_RQ_PENDING (1 << 8) 3936f2043ceSAlex Deucher #define GDS_DMA_RQ_PENDING (1 << 9) 3946f2043ceSAlex Deucher #define DB_CLEAN (1 << 12) 3956f2043ceSAlex Deucher #define CB_CLEAN (1 << 13) 3966f2043ceSAlex Deucher #define TA_BUSY (1 << 14) 3976f2043ceSAlex Deucher #define GDS_BUSY (1 << 15) 3986f2043ceSAlex Deucher #define WD_BUSY_NO_DMA (1 << 16) 3996f2043ceSAlex Deucher #define VGT_BUSY (1 << 17) 4006f2043ceSAlex Deucher #define IA_BUSY_NO_DMA (1 << 18) 4016f2043ceSAlex Deucher #define IA_BUSY (1 << 19) 4026f2043ceSAlex Deucher #define SX_BUSY (1 << 20) 4036f2043ceSAlex Deucher #define WD_BUSY (1 << 21) 4046f2043ceSAlex Deucher #define SPI_BUSY (1 << 22) 4056f2043ceSAlex Deucher #define BCI_BUSY (1 << 23) 4066f2043ceSAlex Deucher #define SC_BUSY (1 << 24) 4076f2043ceSAlex Deucher #define PA_BUSY (1 << 25) 4086f2043ceSAlex Deucher #define DB_BUSY (1 << 26) 4096f2043ceSAlex Deucher #define CP_COHERENCY_BUSY (1 << 28) 4106f2043ceSAlex Deucher #define CP_BUSY (1 << 29) 4116f2043ceSAlex Deucher #define CB_BUSY (1 << 30) 4126f2043ceSAlex Deucher #define GUI_ACTIVE (1 << 31) 4136f2043ceSAlex Deucher #define GRBM_STATUS_SE0 0x8014 4146f2043ceSAlex Deucher #define GRBM_STATUS_SE1 0x8018 4156f2043ceSAlex Deucher #define GRBM_STATUS_SE2 0x8038 4166f2043ceSAlex Deucher #define GRBM_STATUS_SE3 0x803C 4176f2043ceSAlex Deucher #define SE_DB_CLEAN (1 << 1) 4186f2043ceSAlex Deucher #define SE_CB_CLEAN (1 << 2) 4196f2043ceSAlex Deucher #define SE_BCI_BUSY (1 << 22) 4206f2043ceSAlex Deucher #define SE_VGT_BUSY (1 << 23) 4216f2043ceSAlex Deucher #define SE_PA_BUSY (1 << 24) 4226f2043ceSAlex Deucher #define SE_TA_BUSY (1 << 25) 4236f2043ceSAlex Deucher #define SE_SX_BUSY (1 << 26) 4246f2043ceSAlex Deucher #define SE_SPI_BUSY (1 << 27) 4256f2043ceSAlex Deucher #define SE_SC_BUSY (1 << 29) 4266f2043ceSAlex Deucher #define SE_DB_BUSY (1 << 30) 4276f2043ceSAlex Deucher #define SE_CB_BUSY (1 << 31) 4286f2043ceSAlex Deucher 4296f2043ceSAlex Deucher #define GRBM_SOFT_RESET 0x8020 4306f2043ceSAlex Deucher #define SOFT_RESET_CP (1 << 0) /* All CP blocks */ 4316f2043ceSAlex Deucher #define SOFT_RESET_RLC (1 << 2) /* RLC */ 4326f2043ceSAlex Deucher #define SOFT_RESET_GFX (1 << 16) /* GFX */ 4336f2043ceSAlex Deucher #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */ 4346f2043ceSAlex Deucher #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */ 4356f2043ceSAlex Deucher #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */ 4366f2043ceSAlex Deucher 437a59781bbSAlex Deucher #define GRBM_INT_CNTL 0x8060 438a59781bbSAlex Deucher # define RDERR_INT_ENABLE (1 << 0) 439a59781bbSAlex Deucher # define GUI_IDLE_INT_ENABLE (1 << 19) 440a59781bbSAlex Deucher 4416f2043ceSAlex Deucher #define CP_MEC_CNTL 0x8234 4426f2043ceSAlex Deucher #define MEC_ME2_HALT (1 << 28) 4436f2043ceSAlex Deucher #define MEC_ME1_HALT (1 << 30) 4446f2043ceSAlex Deucher 445841cf442SAlex Deucher #define CP_MEC_CNTL 0x8234 446841cf442SAlex Deucher #define MEC_ME2_HALT (1 << 28) 447841cf442SAlex Deucher #define MEC_ME1_HALT (1 << 30) 448841cf442SAlex Deucher 4496f2043ceSAlex Deucher #define CP_ME_CNTL 0x86D8 4506f2043ceSAlex Deucher #define CP_CE_HALT (1 << 24) 4516f2043ceSAlex Deucher #define CP_PFP_HALT (1 << 26) 4526f2043ceSAlex Deucher #define CP_ME_HALT (1 << 28) 4536f2043ceSAlex Deucher 454841cf442SAlex Deucher #define CP_RB0_RPTR 0x8700 455841cf442SAlex Deucher #define CP_RB_WPTR_DELAY 0x8704 456841cf442SAlex Deucher 4578cc1a532SAlex Deucher #define CP_MEQ_THRESHOLDS 0x8764 4588cc1a532SAlex Deucher #define MEQ1_START(x) ((x) << 0) 4598cc1a532SAlex Deucher #define MEQ2_START(x) ((x) << 8) 4608cc1a532SAlex Deucher 4618cc1a532SAlex Deucher #define VGT_VTX_VECT_EJECT_REG 0x88B0 4628cc1a532SAlex Deucher 4638cc1a532SAlex Deucher #define VGT_CACHE_INVALIDATION 0x88C4 4648cc1a532SAlex Deucher #define CACHE_INVALIDATION(x) ((x) << 0) 4658cc1a532SAlex Deucher #define VC_ONLY 0 4668cc1a532SAlex Deucher #define TC_ONLY 1 4678cc1a532SAlex Deucher #define VC_AND_TC 2 4688cc1a532SAlex Deucher #define AUTO_INVLD_EN(x) ((x) << 6) 4698cc1a532SAlex Deucher #define NO_AUTO 0 4708cc1a532SAlex Deucher #define ES_AUTO 1 4718cc1a532SAlex Deucher #define GS_AUTO 2 4728cc1a532SAlex Deucher #define ES_AND_GS_AUTO 3 4738cc1a532SAlex Deucher 4748cc1a532SAlex Deucher #define VGT_GS_VERTEX_REUSE 0x88D4 4758cc1a532SAlex Deucher 4768cc1a532SAlex Deucher #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 4778cc1a532SAlex Deucher #define INACTIVE_CUS_MASK 0xFFFF0000 4788cc1a532SAlex Deucher #define INACTIVE_CUS_SHIFT 16 4798cc1a532SAlex Deucher #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 4808cc1a532SAlex Deucher 4818cc1a532SAlex Deucher #define PA_CL_ENHANCE 0x8A14 4828cc1a532SAlex Deucher #define CLIP_VTX_REORDER_ENA (1 << 0) 4838cc1a532SAlex Deucher #define NUM_CLIP_SEQ(x) ((x) << 1) 4848cc1a532SAlex Deucher 4858cc1a532SAlex Deucher #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 4868cc1a532SAlex Deucher #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 4878cc1a532SAlex Deucher #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 4888cc1a532SAlex Deucher 4898cc1a532SAlex Deucher #define PA_SC_FIFO_SIZE 0x8BCC 4908cc1a532SAlex Deucher #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 4918cc1a532SAlex Deucher #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 4928cc1a532SAlex Deucher #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 4938cc1a532SAlex Deucher #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 4948cc1a532SAlex Deucher 4958cc1a532SAlex Deucher #define PA_SC_ENHANCE 0x8BF0 4968cc1a532SAlex Deucher #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) 4978cc1a532SAlex Deucher #define DISABLE_PA_SC_GUIDANCE (1 << 13) 4988cc1a532SAlex Deucher 4998cc1a532SAlex Deucher #define SQ_CONFIG 0x8C00 5008cc1a532SAlex Deucher 5011c49165dSAlex Deucher #define SH_MEM_BASES 0x8C28 5021c49165dSAlex Deucher /* if PTR32, these are the bases for scratch and lds */ 5031c49165dSAlex Deucher #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 5041c49165dSAlex Deucher #define SHARED_BASE(x) ((x) << 16) /* LDS */ 5051c49165dSAlex Deucher #define SH_MEM_APE1_BASE 0x8C2C 5061c49165dSAlex Deucher /* if PTR32, this is the base location of GPUVM */ 5071c49165dSAlex Deucher #define SH_MEM_APE1_LIMIT 0x8C30 5081c49165dSAlex Deucher /* if PTR32, this is the upper limit of GPUVM */ 5091c49165dSAlex Deucher #define SH_MEM_CONFIG 0x8C34 5101c49165dSAlex Deucher #define PTR32 (1 << 0) 5111c49165dSAlex Deucher #define ALIGNMENT_MODE(x) ((x) << 2) 5121c49165dSAlex Deucher #define SH_MEM_ALIGNMENT_MODE_DWORD 0 5131c49165dSAlex Deucher #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 5141c49165dSAlex Deucher #define SH_MEM_ALIGNMENT_MODE_STRICT 2 5151c49165dSAlex Deucher #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 5161c49165dSAlex Deucher #define DEFAULT_MTYPE(x) ((x) << 4) 5171c49165dSAlex Deucher #define APE1_MTYPE(x) ((x) << 7) 5181c49165dSAlex Deucher 5198cc1a532SAlex Deucher #define SX_DEBUG_1 0x9060 5208cc1a532SAlex Deucher 5218cc1a532SAlex Deucher #define SPI_CONFIG_CNTL 0x9100 5228cc1a532SAlex Deucher 5238cc1a532SAlex Deucher #define SPI_CONFIG_CNTL_1 0x913C 5248cc1a532SAlex Deucher #define VTX_DONE_DELAY(x) ((x) << 0) 5258cc1a532SAlex Deucher #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 5268cc1a532SAlex Deucher 5278cc1a532SAlex Deucher #define TA_CNTL_AUX 0x9508 5288cc1a532SAlex Deucher 5298cc1a532SAlex Deucher #define DB_DEBUG 0x9830 5308cc1a532SAlex Deucher #define DB_DEBUG2 0x9834 5318cc1a532SAlex Deucher #define DB_DEBUG3 0x9838 5328cc1a532SAlex Deucher 5338cc1a532SAlex Deucher #define CC_RB_BACKEND_DISABLE 0x98F4 5348cc1a532SAlex Deucher #define BACKEND_DISABLE(x) ((x) << 16) 5358cc1a532SAlex Deucher #define GB_ADDR_CONFIG 0x98F8 5368cc1a532SAlex Deucher #define NUM_PIPES(x) ((x) << 0) 5378cc1a532SAlex Deucher #define NUM_PIPES_MASK 0x00000007 5388cc1a532SAlex Deucher #define NUM_PIPES_SHIFT 0 5398cc1a532SAlex Deucher #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 5408cc1a532SAlex Deucher #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 5418cc1a532SAlex Deucher #define PIPE_INTERLEAVE_SIZE_SHIFT 4 5428cc1a532SAlex Deucher #define NUM_SHADER_ENGINES(x) ((x) << 12) 5438cc1a532SAlex Deucher #define NUM_SHADER_ENGINES_MASK 0x00003000 5448cc1a532SAlex Deucher #define NUM_SHADER_ENGINES_SHIFT 12 5458cc1a532SAlex Deucher #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 5468cc1a532SAlex Deucher #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 5478cc1a532SAlex Deucher #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 5488cc1a532SAlex Deucher #define ROW_SIZE(x) ((x) << 28) 5498cc1a532SAlex Deucher #define ROW_SIZE_MASK 0x30000000 5508cc1a532SAlex Deucher #define ROW_SIZE_SHIFT 28 5518cc1a532SAlex Deucher 5528cc1a532SAlex Deucher #define GB_TILE_MODE0 0x9910 5538cc1a532SAlex Deucher # define ARRAY_MODE(x) ((x) << 2) 5548cc1a532SAlex Deucher # define ARRAY_LINEAR_GENERAL 0 5558cc1a532SAlex Deucher # define ARRAY_LINEAR_ALIGNED 1 5568cc1a532SAlex Deucher # define ARRAY_1D_TILED_THIN1 2 5578cc1a532SAlex Deucher # define ARRAY_2D_TILED_THIN1 4 5588cc1a532SAlex Deucher # define ARRAY_PRT_TILED_THIN1 5 5598cc1a532SAlex Deucher # define ARRAY_PRT_2D_TILED_THIN1 6 5608cc1a532SAlex Deucher # define PIPE_CONFIG(x) ((x) << 6) 5618cc1a532SAlex Deucher # define ADDR_SURF_P2 0 5628cc1a532SAlex Deucher # define ADDR_SURF_P4_8x16 4 5638cc1a532SAlex Deucher # define ADDR_SURF_P4_16x16 5 5648cc1a532SAlex Deucher # define ADDR_SURF_P4_16x32 6 5658cc1a532SAlex Deucher # define ADDR_SURF_P4_32x32 7 5668cc1a532SAlex Deucher # define ADDR_SURF_P8_16x16_8x16 8 5678cc1a532SAlex Deucher # define ADDR_SURF_P8_16x32_8x16 9 5688cc1a532SAlex Deucher # define ADDR_SURF_P8_32x32_8x16 10 5698cc1a532SAlex Deucher # define ADDR_SURF_P8_16x32_16x16 11 5708cc1a532SAlex Deucher # define ADDR_SURF_P8_32x32_16x16 12 5718cc1a532SAlex Deucher # define ADDR_SURF_P8_32x32_16x32 13 5728cc1a532SAlex Deucher # define ADDR_SURF_P8_32x64_32x32 14 5738cc1a532SAlex Deucher # define TILE_SPLIT(x) ((x) << 11) 5748cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_64B 0 5758cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_128B 1 5768cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_256B 2 5778cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_512B 3 5788cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_1KB 4 5798cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_2KB 5 5808cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_4KB 6 5818cc1a532SAlex Deucher # define MICRO_TILE_MODE_NEW(x) ((x) << 22) 5828cc1a532SAlex Deucher # define ADDR_SURF_DISPLAY_MICRO_TILING 0 5838cc1a532SAlex Deucher # define ADDR_SURF_THIN_MICRO_TILING 1 5848cc1a532SAlex Deucher # define ADDR_SURF_DEPTH_MICRO_TILING 2 5858cc1a532SAlex Deucher # define ADDR_SURF_ROTATED_MICRO_TILING 3 5868cc1a532SAlex Deucher # define SAMPLE_SPLIT(x) ((x) << 25) 5878cc1a532SAlex Deucher # define ADDR_SURF_SAMPLE_SPLIT_1 0 5888cc1a532SAlex Deucher # define ADDR_SURF_SAMPLE_SPLIT_2 1 5898cc1a532SAlex Deucher # define ADDR_SURF_SAMPLE_SPLIT_4 2 5908cc1a532SAlex Deucher # define ADDR_SURF_SAMPLE_SPLIT_8 3 5918cc1a532SAlex Deucher 5928cc1a532SAlex Deucher #define GB_MACROTILE_MODE0 0x9990 5938cc1a532SAlex Deucher # define BANK_WIDTH(x) ((x) << 0) 5948cc1a532SAlex Deucher # define ADDR_SURF_BANK_WIDTH_1 0 5958cc1a532SAlex Deucher # define ADDR_SURF_BANK_WIDTH_2 1 5968cc1a532SAlex Deucher # define ADDR_SURF_BANK_WIDTH_4 2 5978cc1a532SAlex Deucher # define ADDR_SURF_BANK_WIDTH_8 3 5988cc1a532SAlex Deucher # define BANK_HEIGHT(x) ((x) << 2) 5998cc1a532SAlex Deucher # define ADDR_SURF_BANK_HEIGHT_1 0 6008cc1a532SAlex Deucher # define ADDR_SURF_BANK_HEIGHT_2 1 6018cc1a532SAlex Deucher # define ADDR_SURF_BANK_HEIGHT_4 2 6028cc1a532SAlex Deucher # define ADDR_SURF_BANK_HEIGHT_8 3 6038cc1a532SAlex Deucher # define MACRO_TILE_ASPECT(x) ((x) << 4) 6048cc1a532SAlex Deucher # define ADDR_SURF_MACRO_ASPECT_1 0 6058cc1a532SAlex Deucher # define ADDR_SURF_MACRO_ASPECT_2 1 6068cc1a532SAlex Deucher # define ADDR_SURF_MACRO_ASPECT_4 2 6078cc1a532SAlex Deucher # define ADDR_SURF_MACRO_ASPECT_8 3 6088cc1a532SAlex Deucher # define NUM_BANKS(x) ((x) << 6) 6098cc1a532SAlex Deucher # define ADDR_SURF_2_BANK 0 6108cc1a532SAlex Deucher # define ADDR_SURF_4_BANK 1 6118cc1a532SAlex Deucher # define ADDR_SURF_8_BANK 2 6128cc1a532SAlex Deucher # define ADDR_SURF_16_BANK 3 6138cc1a532SAlex Deucher 6148cc1a532SAlex Deucher #define CB_HW_CONTROL 0x9A10 6158cc1a532SAlex Deucher 6168cc1a532SAlex Deucher #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 6178cc1a532SAlex Deucher #define BACKEND_DISABLE_MASK 0x00FF0000 6188cc1a532SAlex Deucher #define BACKEND_DISABLE_SHIFT 16 6198cc1a532SAlex Deucher 6208cc1a532SAlex Deucher #define TCP_CHAN_STEER_LO 0xac0c 6218cc1a532SAlex Deucher #define TCP_CHAN_STEER_HI 0xac10 6228cc1a532SAlex Deucher 6231c49165dSAlex Deucher #define TC_CFG_L1_LOAD_POLICY0 0xAC68 6241c49165dSAlex Deucher #define TC_CFG_L1_LOAD_POLICY1 0xAC6C 6251c49165dSAlex Deucher #define TC_CFG_L1_STORE_POLICY 0xAC70 6261c49165dSAlex Deucher #define TC_CFG_L2_LOAD_POLICY0 0xAC74 6271c49165dSAlex Deucher #define TC_CFG_L2_LOAD_POLICY1 0xAC78 6281c49165dSAlex Deucher #define TC_CFG_L2_STORE_POLICY0 0xAC7C 6291c49165dSAlex Deucher #define TC_CFG_L2_STORE_POLICY1 0xAC80 6301c49165dSAlex Deucher #define TC_CFG_L2_ATOMIC_POLICY 0xAC84 6311c49165dSAlex Deucher #define TC_CFG_L1_VOLATILE 0xAC88 6321c49165dSAlex Deucher #define TC_CFG_L2_VOLATILE 0xAC8C 6331c49165dSAlex Deucher 634841cf442SAlex Deucher #define CP_RB0_BASE 0xC100 635841cf442SAlex Deucher #define CP_RB0_CNTL 0xC104 636841cf442SAlex Deucher #define RB_BUFSZ(x) ((x) << 0) 637841cf442SAlex Deucher #define RB_BLKSZ(x) ((x) << 8) 638841cf442SAlex Deucher #define BUF_SWAP_32BIT (2 << 16) 639841cf442SAlex Deucher #define RB_NO_UPDATE (1 << 27) 640841cf442SAlex Deucher #define RB_RPTR_WR_ENA (1 << 31) 641841cf442SAlex Deucher 642841cf442SAlex Deucher #define CP_RB0_RPTR_ADDR 0xC10C 643841cf442SAlex Deucher #define RB_RPTR_SWAP_32BIT (2 << 0) 644841cf442SAlex Deucher #define CP_RB0_RPTR_ADDR_HI 0xC110 645841cf442SAlex Deucher #define CP_RB0_WPTR 0xC114 646841cf442SAlex Deucher 647841cf442SAlex Deucher #define CP_DEVICE_ID 0xC12C 648841cf442SAlex Deucher #define CP_ENDIAN_SWAP 0xC140 649841cf442SAlex Deucher #define CP_RB_VMID 0xC144 650841cf442SAlex Deucher 651841cf442SAlex Deucher #define CP_PFP_UCODE_ADDR 0xC150 652841cf442SAlex Deucher #define CP_PFP_UCODE_DATA 0xC154 653841cf442SAlex Deucher #define CP_ME_RAM_RADDR 0xC158 654841cf442SAlex Deucher #define CP_ME_RAM_WADDR 0xC15C 655841cf442SAlex Deucher #define CP_ME_RAM_DATA 0xC160 656841cf442SAlex Deucher 657841cf442SAlex Deucher #define CP_CE_UCODE_ADDR 0xC168 658841cf442SAlex Deucher #define CP_CE_UCODE_DATA 0xC16C 659841cf442SAlex Deucher #define CP_MEC_ME1_UCODE_ADDR 0xC170 660841cf442SAlex Deucher #define CP_MEC_ME1_UCODE_DATA 0xC174 661841cf442SAlex Deucher #define CP_MEC_ME2_UCODE_ADDR 0xC178 662841cf442SAlex Deucher #define CP_MEC_ME2_UCODE_DATA 0xC17C 663841cf442SAlex Deucher 664f6796caeSAlex Deucher #define CP_INT_CNTL_RING0 0xC1A8 665f6796caeSAlex Deucher # define CNTX_BUSY_INT_ENABLE (1 << 19) 666f6796caeSAlex Deucher # define CNTX_EMPTY_INT_ENABLE (1 << 20) 667f6796caeSAlex Deucher # define PRIV_INSTR_INT_ENABLE (1 << 22) 668f6796caeSAlex Deucher # define PRIV_REG_INT_ENABLE (1 << 23) 669f6796caeSAlex Deucher # define TIME_STAMP_INT_ENABLE (1 << 26) 670f6796caeSAlex Deucher # define CP_RINGID2_INT_ENABLE (1 << 29) 671f6796caeSAlex Deucher # define CP_RINGID1_INT_ENABLE (1 << 30) 672f6796caeSAlex Deucher # define CP_RINGID0_INT_ENABLE (1 << 31) 673f6796caeSAlex Deucher 674a59781bbSAlex Deucher #define CP_INT_STATUS_RING0 0xC1B4 675a59781bbSAlex Deucher # define PRIV_INSTR_INT_STAT (1 << 22) 676a59781bbSAlex Deucher # define PRIV_REG_INT_STAT (1 << 23) 677a59781bbSAlex Deucher # define TIME_STAMP_INT_STAT (1 << 26) 678a59781bbSAlex Deucher # define CP_RINGID2_INT_STAT (1 << 29) 679a59781bbSAlex Deucher # define CP_RINGID1_INT_STAT (1 << 30) 680a59781bbSAlex Deucher # define CP_RINGID0_INT_STAT (1 << 31) 681a59781bbSAlex Deucher 682a59781bbSAlex Deucher #define CP_ME1_PIPE0_INT_CNTL 0xC214 683a59781bbSAlex Deucher #define CP_ME1_PIPE1_INT_CNTL 0xC218 684a59781bbSAlex Deucher #define CP_ME1_PIPE2_INT_CNTL 0xC21C 685a59781bbSAlex Deucher #define CP_ME1_PIPE3_INT_CNTL 0xC220 686a59781bbSAlex Deucher #define CP_ME2_PIPE0_INT_CNTL 0xC224 687a59781bbSAlex Deucher #define CP_ME2_PIPE1_INT_CNTL 0xC228 688a59781bbSAlex Deucher #define CP_ME2_PIPE2_INT_CNTL 0xC22C 689a59781bbSAlex Deucher #define CP_ME2_PIPE3_INT_CNTL 0xC230 690a59781bbSAlex Deucher # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13) 691a59781bbSAlex Deucher # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17) 692a59781bbSAlex Deucher # define PRIV_REG_INT_ENABLE (1 << 23) 693a59781bbSAlex Deucher # define TIME_STAMP_INT_ENABLE (1 << 26) 694a59781bbSAlex Deucher # define GENERIC2_INT_ENABLE (1 << 29) 695a59781bbSAlex Deucher # define GENERIC1_INT_ENABLE (1 << 30) 696a59781bbSAlex Deucher # define GENERIC0_INT_ENABLE (1 << 31) 697a59781bbSAlex Deucher #define CP_ME1_PIPE0_INT_STATUS 0xC214 698a59781bbSAlex Deucher #define CP_ME1_PIPE1_INT_STATUS 0xC218 699a59781bbSAlex Deucher #define CP_ME1_PIPE2_INT_STATUS 0xC21C 700a59781bbSAlex Deucher #define CP_ME1_PIPE3_INT_STATUS 0xC220 701a59781bbSAlex Deucher #define CP_ME2_PIPE0_INT_STATUS 0xC224 702a59781bbSAlex Deucher #define CP_ME2_PIPE1_INT_STATUS 0xC228 703a59781bbSAlex Deucher #define CP_ME2_PIPE2_INT_STATUS 0xC22C 704a59781bbSAlex Deucher #define CP_ME2_PIPE3_INT_STATUS 0xC230 705a59781bbSAlex Deucher # define DEQUEUE_REQUEST_INT_STATUS (1 << 13) 706a59781bbSAlex Deucher # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17) 707a59781bbSAlex Deucher # define PRIV_REG_INT_STATUS (1 << 23) 708a59781bbSAlex Deucher # define TIME_STAMP_INT_STATUS (1 << 26) 709a59781bbSAlex Deucher # define GENERIC2_INT_STATUS (1 << 29) 710a59781bbSAlex Deucher # define GENERIC1_INT_STATUS (1 << 30) 711a59781bbSAlex Deucher # define GENERIC0_INT_STATUS (1 << 31) 712a59781bbSAlex Deucher 713841cf442SAlex Deucher #define CP_MAX_CONTEXT 0xC2B8 714841cf442SAlex Deucher 715841cf442SAlex Deucher #define CP_RB0_BASE_HI 0xC2C4 716841cf442SAlex Deucher 717f6796caeSAlex Deucher #define RLC_CNTL 0xC300 718f6796caeSAlex Deucher # define RLC_ENABLE (1 << 0) 719f6796caeSAlex Deucher 720f6796caeSAlex Deucher #define RLC_MC_CNTL 0xC30C 721f6796caeSAlex Deucher 722f6796caeSAlex Deucher #define RLC_LB_CNTR_MAX 0xC348 723f6796caeSAlex Deucher 724f6796caeSAlex Deucher #define RLC_LB_CNTL 0xC364 725f6796caeSAlex Deucher 726f6796caeSAlex Deucher #define RLC_LB_CNTR_INIT 0xC36C 727f6796caeSAlex Deucher 728f6796caeSAlex Deucher #define RLC_SAVE_AND_RESTORE_BASE 0xC374 729f6796caeSAlex Deucher #define RLC_DRIVER_DMA_STATUS 0xC378 730f6796caeSAlex Deucher 731f6796caeSAlex Deucher #define RLC_GPM_UCODE_ADDR 0xC388 732f6796caeSAlex Deucher #define RLC_GPM_UCODE_DATA 0xC38C 733f6796caeSAlex Deucher 734f6796caeSAlex Deucher #define RLC_UCODE_CNTL 0xC39C 735f6796caeSAlex Deucher 736f6796caeSAlex Deucher #define RLC_CGCG_CGLS_CTRL 0xC424 737f6796caeSAlex Deucher 738f6796caeSAlex Deucher #define RLC_LB_INIT_CU_MASK 0xC43C 739f6796caeSAlex Deucher 740f6796caeSAlex Deucher #define RLC_LB_PARAMS 0xC444 741f6796caeSAlex Deucher 742f6796caeSAlex Deucher #define RLC_SERDES_CU_MASTER_BUSY 0xC484 743f6796caeSAlex Deucher #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 744f6796caeSAlex Deucher # define SE_MASTER_BUSY_MASK 0x0000ffff 745f6796caeSAlex Deucher # define GC_MASTER_BUSY (1 << 16) 746f6796caeSAlex Deucher # define TC0_MASTER_BUSY (1 << 17) 747f6796caeSAlex Deucher # define TC1_MASTER_BUSY (1 << 18) 748f6796caeSAlex Deucher 749f6796caeSAlex Deucher #define RLC_GPM_SCRATCH_ADDR 0xC4B0 750f6796caeSAlex Deucher #define RLC_GPM_SCRATCH_DATA 0xC4B4 751f6796caeSAlex Deucher 7528cc1a532SAlex Deucher #define PA_SC_RASTER_CONFIG 0x28350 7538cc1a532SAlex Deucher # define RASTER_CONFIG_RB_MAP_0 0 7548cc1a532SAlex Deucher # define RASTER_CONFIG_RB_MAP_1 1 7558cc1a532SAlex Deucher # define RASTER_CONFIG_RB_MAP_2 2 7568cc1a532SAlex Deucher # define RASTER_CONFIG_RB_MAP_3 3 7578cc1a532SAlex Deucher 7582cae3bc3SAlex Deucher #define VGT_EVENT_INITIATOR 0x28a90 7592cae3bc3SAlex Deucher # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 7602cae3bc3SAlex Deucher # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 7612cae3bc3SAlex Deucher # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 7622cae3bc3SAlex Deucher # define CACHE_FLUSH_TS (4 << 0) 7632cae3bc3SAlex Deucher # define CACHE_FLUSH (6 << 0) 7642cae3bc3SAlex Deucher # define CS_PARTIAL_FLUSH (7 << 0) 7652cae3bc3SAlex Deucher # define VGT_STREAMOUT_RESET (10 << 0) 7662cae3bc3SAlex Deucher # define END_OF_PIPE_INCR_DE (11 << 0) 7672cae3bc3SAlex Deucher # define END_OF_PIPE_IB_END (12 << 0) 7682cae3bc3SAlex Deucher # define RST_PIX_CNT (13 << 0) 7692cae3bc3SAlex Deucher # define VS_PARTIAL_FLUSH (15 << 0) 7702cae3bc3SAlex Deucher # define PS_PARTIAL_FLUSH (16 << 0) 7712cae3bc3SAlex Deucher # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 7722cae3bc3SAlex Deucher # define ZPASS_DONE (21 << 0) 7732cae3bc3SAlex Deucher # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 7742cae3bc3SAlex Deucher # define PERFCOUNTER_START (23 << 0) 7752cae3bc3SAlex Deucher # define PERFCOUNTER_STOP (24 << 0) 7762cae3bc3SAlex Deucher # define PIPELINESTAT_START (25 << 0) 7772cae3bc3SAlex Deucher # define PIPELINESTAT_STOP (26 << 0) 7782cae3bc3SAlex Deucher # define PERFCOUNTER_SAMPLE (27 << 0) 7792cae3bc3SAlex Deucher # define SAMPLE_PIPELINESTAT (30 << 0) 7802cae3bc3SAlex Deucher # define SO_VGT_STREAMOUT_FLUSH (31 << 0) 7812cae3bc3SAlex Deucher # define SAMPLE_STREAMOUTSTATS (32 << 0) 7822cae3bc3SAlex Deucher # define RESET_VTX_CNT (33 << 0) 7832cae3bc3SAlex Deucher # define VGT_FLUSH (36 << 0) 7842cae3bc3SAlex Deucher # define BOTTOM_OF_PIPE_TS (40 << 0) 7852cae3bc3SAlex Deucher # define DB_CACHE_FLUSH_AND_INV (42 << 0) 7862cae3bc3SAlex Deucher # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 7872cae3bc3SAlex Deucher # define FLUSH_AND_INV_DB_META (44 << 0) 7882cae3bc3SAlex Deucher # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 7892cae3bc3SAlex Deucher # define FLUSH_AND_INV_CB_META (46 << 0) 7902cae3bc3SAlex Deucher # define CS_DONE (47 << 0) 7912cae3bc3SAlex Deucher # define PS_DONE (48 << 0) 7922cae3bc3SAlex Deucher # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 7932cae3bc3SAlex Deucher # define THREAD_TRACE_START (51 << 0) 7942cae3bc3SAlex Deucher # define THREAD_TRACE_STOP (52 << 0) 7952cae3bc3SAlex Deucher # define THREAD_TRACE_FLUSH (54 << 0) 7962cae3bc3SAlex Deucher # define THREAD_TRACE_FINISH (55 << 0) 7972cae3bc3SAlex Deucher # define PIXEL_PIPE_STAT_CONTROL (56 << 0) 7982cae3bc3SAlex Deucher # define PIXEL_PIPE_STAT_DUMP (57 << 0) 7992cae3bc3SAlex Deucher # define PIXEL_PIPE_STAT_RESET (58 << 0) 8002cae3bc3SAlex Deucher 801841cf442SAlex Deucher #define SCRATCH_REG0 0x30100 802841cf442SAlex Deucher #define SCRATCH_REG1 0x30104 803841cf442SAlex Deucher #define SCRATCH_REG2 0x30108 804841cf442SAlex Deucher #define SCRATCH_REG3 0x3010C 805841cf442SAlex Deucher #define SCRATCH_REG4 0x30110 806841cf442SAlex Deucher #define SCRATCH_REG5 0x30114 807841cf442SAlex Deucher #define SCRATCH_REG6 0x30118 808841cf442SAlex Deucher #define SCRATCH_REG7 0x3011C 809841cf442SAlex Deucher 810841cf442SAlex Deucher #define SCRATCH_UMSK 0x30140 811841cf442SAlex Deucher #define SCRATCH_ADDR 0x30144 812841cf442SAlex Deucher 813841cf442SAlex Deucher #define CP_SEM_WAIT_TIMER 0x301BC 814841cf442SAlex Deucher 815841cf442SAlex Deucher #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8 816841cf442SAlex Deucher 8172cae3bc3SAlex Deucher #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0 8182cae3bc3SAlex Deucher 8198cc1a532SAlex Deucher #define GRBM_GFX_INDEX 0x30800 8208cc1a532SAlex Deucher #define INSTANCE_INDEX(x) ((x) << 0) 8218cc1a532SAlex Deucher #define SH_INDEX(x) ((x) << 8) 8228cc1a532SAlex Deucher #define SE_INDEX(x) ((x) << 16) 8238cc1a532SAlex Deucher #define SH_BROADCAST_WRITES (1 << 29) 8248cc1a532SAlex Deucher #define INSTANCE_BROADCAST_WRITES (1 << 30) 8258cc1a532SAlex Deucher #define SE_BROADCAST_WRITES (1 << 31) 8268cc1a532SAlex Deucher 8278cc1a532SAlex Deucher #define VGT_ESGS_RING_SIZE 0x30900 8288cc1a532SAlex Deucher #define VGT_GSVS_RING_SIZE 0x30904 8298cc1a532SAlex Deucher #define VGT_PRIMITIVE_TYPE 0x30908 8308cc1a532SAlex Deucher #define VGT_INDEX_TYPE 0x3090C 8318cc1a532SAlex Deucher 8328cc1a532SAlex Deucher #define VGT_NUM_INDICES 0x30930 8338cc1a532SAlex Deucher #define VGT_NUM_INSTANCES 0x30934 8348cc1a532SAlex Deucher #define VGT_TF_RING_SIZE 0x30938 8358cc1a532SAlex Deucher #define VGT_HS_OFFCHIP_PARAM 0x3093C 8368cc1a532SAlex Deucher #define VGT_TF_MEMORY_BASE 0x30940 8378cc1a532SAlex Deucher 8388cc1a532SAlex Deucher #define PA_SU_LINE_STIPPLE_VALUE 0x30a00 8398cc1a532SAlex Deucher #define PA_SC_LINE_STIPPLE_STATE 0x30a04 8408cc1a532SAlex Deucher 8418cc1a532SAlex Deucher #define SQC_CACHES 0x30d20 8428cc1a532SAlex Deucher 8438cc1a532SAlex Deucher #define CP_PERFMON_CNTL 0x36020 8448cc1a532SAlex Deucher 8458cc1a532SAlex Deucher #define CGTS_TCC_DISABLE 0x3c00c 8468cc1a532SAlex Deucher #define CGTS_USER_TCC_DISABLE 0x3c010 8478cc1a532SAlex Deucher #define TCC_DISABLE_MASK 0xFFFF0000 8488cc1a532SAlex Deucher #define TCC_DISABLE_SHIFT 16 8498cc1a532SAlex Deucher 850f6796caeSAlex Deucher #define CB_CGTT_SCLK_CTRL 0x3c2a0 851f6796caeSAlex Deucher 852841cf442SAlex Deucher /* 853841cf442SAlex Deucher * PM4 854841cf442SAlex Deucher */ 855841cf442SAlex Deucher #define PACKET_TYPE0 0 856841cf442SAlex Deucher #define PACKET_TYPE1 1 857841cf442SAlex Deucher #define PACKET_TYPE2 2 858841cf442SAlex Deucher #define PACKET_TYPE3 3 859841cf442SAlex Deucher 860841cf442SAlex Deucher #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 861841cf442SAlex Deucher #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 862841cf442SAlex Deucher #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 863841cf442SAlex Deucher #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 864841cf442SAlex Deucher #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 865841cf442SAlex Deucher (((reg) >> 2) & 0xFFFF) | \ 866841cf442SAlex Deucher ((n) & 0x3FFF) << 16) 867841cf442SAlex Deucher #define CP_PACKET2 0x80000000 868841cf442SAlex Deucher #define PACKET2_PAD_SHIFT 0 869841cf442SAlex Deucher #define PACKET2_PAD_MASK (0x3fffffff << 0) 870841cf442SAlex Deucher 871841cf442SAlex Deucher #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 872841cf442SAlex Deucher 873841cf442SAlex Deucher #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 874841cf442SAlex Deucher (((op) & 0xFF) << 8) | \ 875841cf442SAlex Deucher ((n) & 0x3FFF) << 16) 876841cf442SAlex Deucher 877841cf442SAlex Deucher #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 878841cf442SAlex Deucher 879841cf442SAlex Deucher /* Packet 3 types */ 880841cf442SAlex Deucher #define PACKET3_NOP 0x10 881841cf442SAlex Deucher #define PACKET3_SET_BASE 0x11 882841cf442SAlex Deucher #define PACKET3_BASE_INDEX(x) ((x) << 0) 883841cf442SAlex Deucher #define CE_PARTITION_BASE 3 884841cf442SAlex Deucher #define PACKET3_CLEAR_STATE 0x12 885841cf442SAlex Deucher #define PACKET3_INDEX_BUFFER_SIZE 0x13 886841cf442SAlex Deucher #define PACKET3_DISPATCH_DIRECT 0x15 887841cf442SAlex Deucher #define PACKET3_DISPATCH_INDIRECT 0x16 888841cf442SAlex Deucher #define PACKET3_ATOMIC_GDS 0x1D 889841cf442SAlex Deucher #define PACKET3_ATOMIC_MEM 0x1E 890841cf442SAlex Deucher #define PACKET3_OCCLUSION_QUERY 0x1F 891841cf442SAlex Deucher #define PACKET3_SET_PREDICATION 0x20 892841cf442SAlex Deucher #define PACKET3_REG_RMW 0x21 893841cf442SAlex Deucher #define PACKET3_COND_EXEC 0x22 894841cf442SAlex Deucher #define PACKET3_PRED_EXEC 0x23 895841cf442SAlex Deucher #define PACKET3_DRAW_INDIRECT 0x24 896841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_INDIRECT 0x25 897841cf442SAlex Deucher #define PACKET3_INDEX_BASE 0x26 898841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_2 0x27 899841cf442SAlex Deucher #define PACKET3_CONTEXT_CONTROL 0x28 900841cf442SAlex Deucher #define PACKET3_INDEX_TYPE 0x2A 901841cf442SAlex Deucher #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 902841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_AUTO 0x2D 903841cf442SAlex Deucher #define PACKET3_NUM_INSTANCES 0x2F 904841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 905841cf442SAlex Deucher #define PACKET3_INDIRECT_BUFFER_CONST 0x33 906841cf442SAlex Deucher #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 907841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 908841cf442SAlex Deucher #define PACKET3_DRAW_PREAMBLE 0x36 909841cf442SAlex Deucher #define PACKET3_WRITE_DATA 0x37 9102cae3bc3SAlex Deucher #define WRITE_DATA_DST_SEL(x) ((x) << 8) 9112cae3bc3SAlex Deucher /* 0 - register 9122cae3bc3SAlex Deucher * 1 - memory (sync - via GRBM) 9132cae3bc3SAlex Deucher * 2 - gl2 9142cae3bc3SAlex Deucher * 3 - gds 9152cae3bc3SAlex Deucher * 4 - reserved 9162cae3bc3SAlex Deucher * 5 - memory (async - direct) 9172cae3bc3SAlex Deucher */ 9182cae3bc3SAlex Deucher #define WR_ONE_ADDR (1 << 16) 9192cae3bc3SAlex Deucher #define WR_CONFIRM (1 << 20) 9202cae3bc3SAlex Deucher #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 9212cae3bc3SAlex Deucher /* 0 - LRU 9222cae3bc3SAlex Deucher * 1 - Stream 9232cae3bc3SAlex Deucher */ 9242cae3bc3SAlex Deucher #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 9252cae3bc3SAlex Deucher /* 0 - me 9262cae3bc3SAlex Deucher * 1 - pfp 9272cae3bc3SAlex Deucher * 2 - ce 9282cae3bc3SAlex Deucher */ 929841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 930841cf442SAlex Deucher #define PACKET3_MEM_SEMAPHORE 0x39 9312cae3bc3SAlex Deucher # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 9322cae3bc3SAlex Deucher # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 9332cae3bc3SAlex Deucher # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 9342cae3bc3SAlex Deucher # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 9352cae3bc3SAlex Deucher # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 936841cf442SAlex Deucher #define PACKET3_COPY_DW 0x3B 937841cf442SAlex Deucher #define PACKET3_WAIT_REG_MEM 0x3C 9382cae3bc3SAlex Deucher #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 9392cae3bc3SAlex Deucher /* 0 - always 9402cae3bc3SAlex Deucher * 1 - < 9412cae3bc3SAlex Deucher * 2 - <= 9422cae3bc3SAlex Deucher * 3 - == 9432cae3bc3SAlex Deucher * 4 - != 9442cae3bc3SAlex Deucher * 5 - >= 9452cae3bc3SAlex Deucher * 6 - > 9462cae3bc3SAlex Deucher */ 9472cae3bc3SAlex Deucher #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 9482cae3bc3SAlex Deucher /* 0 - reg 9492cae3bc3SAlex Deucher * 1 - mem 9502cae3bc3SAlex Deucher */ 9512cae3bc3SAlex Deucher #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 9522cae3bc3SAlex Deucher /* 0 - wait_reg_mem 9532cae3bc3SAlex Deucher * 1 - wr_wait_wr_reg 9542cae3bc3SAlex Deucher */ 9552cae3bc3SAlex Deucher #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 9562cae3bc3SAlex Deucher /* 0 - me 9572cae3bc3SAlex Deucher * 1 - pfp 9582cae3bc3SAlex Deucher */ 959841cf442SAlex Deucher #define PACKET3_INDIRECT_BUFFER 0x3F 9602cae3bc3SAlex Deucher #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 9612cae3bc3SAlex Deucher #define INDIRECT_BUFFER_VALID (1 << 23) 9622cae3bc3SAlex Deucher #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 9632cae3bc3SAlex Deucher /* 0 - LRU 9642cae3bc3SAlex Deucher * 1 - Stream 9652cae3bc3SAlex Deucher * 2 - Bypass 9662cae3bc3SAlex Deucher */ 967841cf442SAlex Deucher #define PACKET3_COPY_DATA 0x40 968841cf442SAlex Deucher #define PACKET3_PFP_SYNC_ME 0x42 969841cf442SAlex Deucher #define PACKET3_SURFACE_SYNC 0x43 970841cf442SAlex Deucher # define PACKET3_DEST_BASE_0_ENA (1 << 0) 971841cf442SAlex Deucher # define PACKET3_DEST_BASE_1_ENA (1 << 1) 972841cf442SAlex Deucher # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 973841cf442SAlex Deucher # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 974841cf442SAlex Deucher # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 975841cf442SAlex Deucher # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 976841cf442SAlex Deucher # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 977841cf442SAlex Deucher # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 978841cf442SAlex Deucher # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 979841cf442SAlex Deucher # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 980841cf442SAlex Deucher # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 981841cf442SAlex Deucher # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 982841cf442SAlex Deucher # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 983841cf442SAlex Deucher # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 984841cf442SAlex Deucher # define PACKET3_DEST_BASE_2_ENA (1 << 19) 985841cf442SAlex Deucher # define PACKET3_DEST_BASE_3_ENA (1 << 21) 986841cf442SAlex Deucher # define PACKET3_TCL1_ACTION_ENA (1 << 22) 987841cf442SAlex Deucher # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 988841cf442SAlex Deucher # define PACKET3_CB_ACTION_ENA (1 << 25) 989841cf442SAlex Deucher # define PACKET3_DB_ACTION_ENA (1 << 26) 990841cf442SAlex Deucher # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 991841cf442SAlex Deucher # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 992841cf442SAlex Deucher # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 993841cf442SAlex Deucher #define PACKET3_COND_WRITE 0x45 994841cf442SAlex Deucher #define PACKET3_EVENT_WRITE 0x46 995841cf442SAlex Deucher #define EVENT_TYPE(x) ((x) << 0) 996841cf442SAlex Deucher #define EVENT_INDEX(x) ((x) << 8) 997841cf442SAlex Deucher /* 0 - any non-TS event 998841cf442SAlex Deucher * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 999841cf442SAlex Deucher * 2 - SAMPLE_PIPELINESTAT 1000841cf442SAlex Deucher * 3 - SAMPLE_STREAMOUTSTAT* 1001841cf442SAlex Deucher * 4 - *S_PARTIAL_FLUSH 1002841cf442SAlex Deucher * 5 - EOP events 1003841cf442SAlex Deucher * 6 - EOS events 1004841cf442SAlex Deucher */ 1005841cf442SAlex Deucher #define PACKET3_EVENT_WRITE_EOP 0x47 1006841cf442SAlex Deucher #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 1007841cf442SAlex Deucher #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 1008841cf442SAlex Deucher #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 1009841cf442SAlex Deucher #define EOP_TCL1_ACTION_EN (1 << 16) 1010841cf442SAlex Deucher #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 10112cae3bc3SAlex Deucher #define EOP_CACHE_POLICY(x) ((x) << 25) 1012841cf442SAlex Deucher /* 0 - LRU 1013841cf442SAlex Deucher * 1 - Stream 1014841cf442SAlex Deucher * 2 - Bypass 1015841cf442SAlex Deucher */ 10162cae3bc3SAlex Deucher #define EOP_TCL2_VOLATILE (1 << 27) 1017841cf442SAlex Deucher #define DATA_SEL(x) ((x) << 29) 1018841cf442SAlex Deucher /* 0 - discard 1019841cf442SAlex Deucher * 1 - send low 32bit data 1020841cf442SAlex Deucher * 2 - send 64bit data 1021841cf442SAlex Deucher * 3 - send 64bit GPU counter value 1022841cf442SAlex Deucher * 4 - send 64bit sys counter value 1023841cf442SAlex Deucher */ 1024841cf442SAlex Deucher #define INT_SEL(x) ((x) << 24) 1025841cf442SAlex Deucher /* 0 - none 1026841cf442SAlex Deucher * 1 - interrupt only (DATA_SEL = 0) 1027841cf442SAlex Deucher * 2 - interrupt when data write is confirmed 1028841cf442SAlex Deucher */ 1029841cf442SAlex Deucher #define DST_SEL(x) ((x) << 16) 1030841cf442SAlex Deucher /* 0 - MC 1031841cf442SAlex Deucher * 1 - TC/L2 1032841cf442SAlex Deucher */ 1033841cf442SAlex Deucher #define PACKET3_EVENT_WRITE_EOS 0x48 1034841cf442SAlex Deucher #define PACKET3_RELEASE_MEM 0x49 1035841cf442SAlex Deucher #define PACKET3_PREAMBLE_CNTL 0x4A 1036841cf442SAlex Deucher # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1037841cf442SAlex Deucher # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1038841cf442SAlex Deucher #define PACKET3_DMA_DATA 0x50 1039841cf442SAlex Deucher #define PACKET3_AQUIRE_MEM 0x58 1040841cf442SAlex Deucher #define PACKET3_REWIND 0x59 1041841cf442SAlex Deucher #define PACKET3_LOAD_UCONFIG_REG 0x5E 1042841cf442SAlex Deucher #define PACKET3_LOAD_SH_REG 0x5F 1043841cf442SAlex Deucher #define PACKET3_LOAD_CONFIG_REG 0x60 1044841cf442SAlex Deucher #define PACKET3_LOAD_CONTEXT_REG 0x61 1045841cf442SAlex Deucher #define PACKET3_SET_CONFIG_REG 0x68 1046841cf442SAlex Deucher #define PACKET3_SET_CONFIG_REG_START 0x00008000 1047841cf442SAlex Deucher #define PACKET3_SET_CONFIG_REG_END 0x0000b000 1048841cf442SAlex Deucher #define PACKET3_SET_CONTEXT_REG 0x69 1049841cf442SAlex Deucher #define PACKET3_SET_CONTEXT_REG_START 0x00028000 1050841cf442SAlex Deucher #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1051841cf442SAlex Deucher #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1052841cf442SAlex Deucher #define PACKET3_SET_SH_REG 0x76 1053841cf442SAlex Deucher #define PACKET3_SET_SH_REG_START 0x0000b000 1054841cf442SAlex Deucher #define PACKET3_SET_SH_REG_END 0x0000c000 1055841cf442SAlex Deucher #define PACKET3_SET_SH_REG_OFFSET 0x77 1056841cf442SAlex Deucher #define PACKET3_SET_QUEUE_REG 0x78 1057841cf442SAlex Deucher #define PACKET3_SET_UCONFIG_REG 0x79 10582cae3bc3SAlex Deucher #define PACKET3_SET_UCONFIG_REG_START 0x00030000 10592cae3bc3SAlex Deucher #define PACKET3_SET_UCONFIG_REG_END 0x00031000 1060841cf442SAlex Deucher #define PACKET3_SCRATCH_RAM_WRITE 0x7D 1061841cf442SAlex Deucher #define PACKET3_SCRATCH_RAM_READ 0x7E 1062841cf442SAlex Deucher #define PACKET3_LOAD_CONST_RAM 0x80 1063841cf442SAlex Deucher #define PACKET3_WRITE_CONST_RAM 0x81 1064841cf442SAlex Deucher #define PACKET3_DUMP_CONST_RAM 0x83 1065841cf442SAlex Deucher #define PACKET3_INCREMENT_CE_COUNTER 0x84 1066841cf442SAlex Deucher #define PACKET3_INCREMENT_DE_COUNTER 0x85 1067841cf442SAlex Deucher #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1068841cf442SAlex Deucher #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 10692cae3bc3SAlex Deucher #define PACKET3_SWITCH_BUFFER 0x8B 1070841cf442SAlex Deucher 107121a93e13SAlex Deucher /* SDMA - first instance at 0xd000, second at 0xd800 */ 107221a93e13SAlex Deucher #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 107321a93e13SAlex Deucher #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ 107421a93e13SAlex Deucher 107521a93e13SAlex Deucher #define SDMA0_UCODE_ADDR 0xD000 107621a93e13SAlex Deucher #define SDMA0_UCODE_DATA 0xD004 107721a93e13SAlex Deucher 107821a93e13SAlex Deucher #define SDMA0_CNTL 0xD010 107921a93e13SAlex Deucher # define TRAP_ENABLE (1 << 0) 108021a93e13SAlex Deucher # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 108121a93e13SAlex Deucher # define SEM_WAIT_INT_ENABLE (1 << 2) 108221a93e13SAlex Deucher # define DATA_SWAP_ENABLE (1 << 3) 108321a93e13SAlex Deucher # define FENCE_SWAP_ENABLE (1 << 4) 108421a93e13SAlex Deucher # define AUTO_CTXSW_ENABLE (1 << 18) 108521a93e13SAlex Deucher # define CTXEMPTY_INT_ENABLE (1 << 28) 108621a93e13SAlex Deucher 108721a93e13SAlex Deucher #define SDMA0_TILING_CONFIG 0xD018 108821a93e13SAlex Deucher 108921a93e13SAlex Deucher #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020 109021a93e13SAlex Deucher #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024 109121a93e13SAlex Deucher 109221a93e13SAlex Deucher #define SDMA0_STATUS_REG 0xd034 109321a93e13SAlex Deucher # define SDMA_IDLE (1 << 0) 109421a93e13SAlex Deucher 109521a93e13SAlex Deucher #define SDMA0_ME_CNTL 0xD048 109621a93e13SAlex Deucher # define SDMA_HALT (1 << 0) 109721a93e13SAlex Deucher 109821a93e13SAlex Deucher #define SDMA0_GFX_RB_CNTL 0xD200 109921a93e13SAlex Deucher # define SDMA_RB_ENABLE (1 << 0) 110021a93e13SAlex Deucher # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */ 110121a93e13SAlex Deucher # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 110221a93e13SAlex Deucher # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12) 110321a93e13SAlex Deucher # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 110421a93e13SAlex Deucher # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 110521a93e13SAlex Deucher #define SDMA0_GFX_RB_BASE 0xD204 110621a93e13SAlex Deucher #define SDMA0_GFX_RB_BASE_HI 0xD208 110721a93e13SAlex Deucher #define SDMA0_GFX_RB_RPTR 0xD20C 110821a93e13SAlex Deucher #define SDMA0_GFX_RB_WPTR 0xD210 110921a93e13SAlex Deucher 111021a93e13SAlex Deucher #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220 111121a93e13SAlex Deucher #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224 111221a93e13SAlex Deucher #define SDMA0_GFX_IB_CNTL 0xD228 111321a93e13SAlex Deucher # define SDMA_IB_ENABLE (1 << 0) 111421a93e13SAlex Deucher # define SDMA_IB_SWAP_ENABLE (1 << 4) 111521a93e13SAlex Deucher # define SDMA_SWITCH_INSIDE_IB (1 << 8) 111621a93e13SAlex Deucher # define SDMA_CMD_VMID(x) ((x) << 16) 111721a93e13SAlex Deucher 111821a93e13SAlex Deucher #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C 111921a93e13SAlex Deucher #define SDMA0_GFX_APE1_CNTL 0xD2A0 112021a93e13SAlex Deucher 112121a93e13SAlex Deucher #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 112221a93e13SAlex Deucher (((sub_op) & 0xFF) << 8) | \ 112321a93e13SAlex Deucher (((op) & 0xFF) << 0)) 112421a93e13SAlex Deucher /* sDMA opcodes */ 112521a93e13SAlex Deucher #define SDMA_OPCODE_NOP 0 112621a93e13SAlex Deucher #define SDMA_OPCODE_COPY 1 112721a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_LINEAR 0 112821a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_TILED 1 112921a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_SOA 3 113021a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 113121a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 113221a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 113321a93e13SAlex Deucher #define SDMA_OPCODE_WRITE 2 113421a93e13SAlex Deucher # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 113521a93e13SAlex Deucher # define SDMA_WRTIE_SUB_OPCODE_TILED 1 113621a93e13SAlex Deucher #define SDMA_OPCODE_INDIRECT_BUFFER 4 113721a93e13SAlex Deucher #define SDMA_OPCODE_FENCE 5 113821a93e13SAlex Deucher #define SDMA_OPCODE_TRAP 6 113921a93e13SAlex Deucher #define SDMA_OPCODE_SEMAPHORE 7 114021a93e13SAlex Deucher # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 114121a93e13SAlex Deucher /* 0 - increment 114221a93e13SAlex Deucher * 1 - write 1 114321a93e13SAlex Deucher */ 114421a93e13SAlex Deucher # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 114521a93e13SAlex Deucher /* 0 - wait 114621a93e13SAlex Deucher * 1 - signal 114721a93e13SAlex Deucher */ 114821a93e13SAlex Deucher # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 114921a93e13SAlex Deucher /* mailbox */ 115021a93e13SAlex Deucher #define SDMA_OPCODE_POLL_REG_MEM 8 115121a93e13SAlex Deucher # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 115221a93e13SAlex Deucher /* 0 - wait_reg_mem 115321a93e13SAlex Deucher * 1 - wr_wait_wr_reg 115421a93e13SAlex Deucher */ 115521a93e13SAlex Deucher # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 115621a93e13SAlex Deucher /* 0 - always 115721a93e13SAlex Deucher * 1 - < 115821a93e13SAlex Deucher * 2 - <= 115921a93e13SAlex Deucher * 3 - == 116021a93e13SAlex Deucher * 4 - != 116121a93e13SAlex Deucher * 5 - >= 116221a93e13SAlex Deucher * 6 - > 116321a93e13SAlex Deucher */ 116421a93e13SAlex Deucher # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 116521a93e13SAlex Deucher /* 0 = register 116621a93e13SAlex Deucher * 1 = memory 116721a93e13SAlex Deucher */ 116821a93e13SAlex Deucher #define SDMA_OPCODE_COND_EXEC 9 116921a93e13SAlex Deucher #define SDMA_OPCODE_CONSTANT_FILL 11 117021a93e13SAlex Deucher # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 117121a93e13SAlex Deucher /* 0 = byte fill 117221a93e13SAlex Deucher * 2 = DW fill 117321a93e13SAlex Deucher */ 117421a93e13SAlex Deucher #define SDMA_OPCODE_GENERATE_PTE_PDE 12 117521a93e13SAlex Deucher #define SDMA_OPCODE_TIMESTAMP 13 117621a93e13SAlex Deucher # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 117721a93e13SAlex Deucher # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 117821a93e13SAlex Deucher # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 117921a93e13SAlex Deucher #define SDMA_OPCODE_SRBM_WRITE 14 118021a93e13SAlex Deucher # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 118121a93e13SAlex Deucher /* byte mask */ 118221a93e13SAlex Deucher 11838cc1a532SAlex Deucher #endif 1184