18cc1a532SAlex Deucher /* 28cc1a532SAlex Deucher * Copyright 2012 Advanced Micro Devices, Inc. 38cc1a532SAlex Deucher * 48cc1a532SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 58cc1a532SAlex Deucher * copy of this software and associated documentation files (the "Software"), 68cc1a532SAlex Deucher * to deal in the Software without restriction, including without limitation 78cc1a532SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 88cc1a532SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 98cc1a532SAlex Deucher * Software is furnished to do so, subject to the following conditions: 108cc1a532SAlex Deucher * 118cc1a532SAlex Deucher * The above copyright notice and this permission notice shall be included in 128cc1a532SAlex Deucher * all copies or substantial portions of the Software. 138cc1a532SAlex Deucher * 148cc1a532SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 158cc1a532SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 168cc1a532SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 178cc1a532SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 188cc1a532SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 198cc1a532SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 208cc1a532SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 218cc1a532SAlex Deucher * 228cc1a532SAlex Deucher * Authors: Alex Deucher 238cc1a532SAlex Deucher */ 248cc1a532SAlex Deucher #ifndef CIK_H 258cc1a532SAlex Deucher #define CIK_H 268cc1a532SAlex Deucher 278cc1a532SAlex Deucher #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 288cc1a532SAlex Deucher 298cc1a532SAlex Deucher #define CIK_RB_BITMAP_WIDTH_PER_SH 2 308cc1a532SAlex Deucher 3141a524abSAlex Deucher /* DIDT IND registers */ 3241a524abSAlex Deucher #define DIDT_SQ_CTRL0 0x0 3341a524abSAlex Deucher # define DIDT_CTRL_EN (1 << 0) 3441a524abSAlex Deucher #define DIDT_DB_CTRL0 0x20 3541a524abSAlex Deucher #define DIDT_TD_CTRL0 0x40 3641a524abSAlex Deucher #define DIDT_TCP_CTRL0 0x60 3741a524abSAlex Deucher 382c67912cSAlex Deucher /* SMC IND registers */ 39cc8dbbb4SAlex Deucher #define DPM_TABLE_475 0x3F768 40cc8dbbb4SAlex Deucher # define SamuBootLevel(x) ((x) << 0) 41cc8dbbb4SAlex Deucher # define SamuBootLevel_MASK 0x000000ff 42cc8dbbb4SAlex Deucher # define SamuBootLevel_SHIFT 0 43cc8dbbb4SAlex Deucher # define AcpBootLevel(x) ((x) << 8) 44cc8dbbb4SAlex Deucher # define AcpBootLevel_MASK 0x0000ff00 45cc8dbbb4SAlex Deucher # define AcpBootLevel_SHIFT 8 46cc8dbbb4SAlex Deucher # define VceBootLevel(x) ((x) << 16) 47cc8dbbb4SAlex Deucher # define VceBootLevel_MASK 0x00ff0000 48cc8dbbb4SAlex Deucher # define VceBootLevel_SHIFT 16 49cc8dbbb4SAlex Deucher # define UvdBootLevel(x) ((x) << 24) 50cc8dbbb4SAlex Deucher # define UvdBootLevel_MASK 0xff000000 51cc8dbbb4SAlex Deucher # define UvdBootLevel_SHIFT 24 52cc8dbbb4SAlex Deucher 53cc8dbbb4SAlex Deucher #define FIRMWARE_FLAGS 0x3F800 54cc8dbbb4SAlex Deucher # define INTERRUPTS_ENABLED (1 << 0) 55cc8dbbb4SAlex Deucher 5641a524abSAlex Deucher #define NB_DPM_CONFIG_1 0x3F9E8 5741a524abSAlex Deucher # define Dpm0PgNbPsLo(x) ((x) << 0) 5841a524abSAlex Deucher # define Dpm0PgNbPsLo_MASK 0x000000ff 5941a524abSAlex Deucher # define Dpm0PgNbPsLo_SHIFT 0 6041a524abSAlex Deucher # define Dpm0PgNbPsHi(x) ((x) << 8) 6141a524abSAlex Deucher # define Dpm0PgNbPsHi_MASK 0x0000ff00 6241a524abSAlex Deucher # define Dpm0PgNbPsHi_SHIFT 8 6341a524abSAlex Deucher # define DpmXNbPsLo(x) ((x) << 16) 6441a524abSAlex Deucher # define DpmXNbPsLo_MASK 0x00ff0000 6541a524abSAlex Deucher # define DpmXNbPsLo_SHIFT 16 6641a524abSAlex Deucher # define DpmXNbPsHi(x) ((x) << 24) 6741a524abSAlex Deucher # define DpmXNbPsHi_MASK 0xff000000 6841a524abSAlex Deucher # define DpmXNbPsHi_SHIFT 24 6941a524abSAlex Deucher 70cc8dbbb4SAlex Deucher #define SMC_SYSCON_RESET_CNTL 0x80000000 71cc8dbbb4SAlex Deucher # define RST_REG (1 << 0) 72cc8dbbb4SAlex Deucher #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 73cc8dbbb4SAlex Deucher # define CK_DISABLE (1 << 0) 74cc8dbbb4SAlex Deucher # define CKEN (1 << 24) 75cc8dbbb4SAlex Deucher 76cc8dbbb4SAlex Deucher #define SMC_SYSCON_MISC_CNTL 0x80000010 77cc8dbbb4SAlex Deucher 7841a524abSAlex Deucher #define SMC_SYSCON_MSG_ARG_0 0x80000068 7941a524abSAlex Deucher 80cc8dbbb4SAlex Deucher #define SMC_PC_C 0x80000370 81cc8dbbb4SAlex Deucher 82cc8dbbb4SAlex Deucher #define SMC_SCRATCH9 0x80000424 83cc8dbbb4SAlex Deucher 84cc8dbbb4SAlex Deucher #define RCU_UC_EVENTS 0xC0000004 85cc8dbbb4SAlex Deucher # define BOOT_SEQ_DONE (1 << 7) 86cc8dbbb4SAlex Deucher 872c67912cSAlex Deucher #define GENERAL_PWRMGT 0xC0200000 8841a524abSAlex Deucher # define GLOBAL_PWRMGT_EN (1 << 0) 89cc8dbbb4SAlex Deucher # define STATIC_PM_EN (1 << 1) 90cc8dbbb4SAlex Deucher # define THERMAL_PROTECTION_DIS (1 << 2) 91cc8dbbb4SAlex Deucher # define THERMAL_PROTECTION_TYPE (1 << 3) 92cc8dbbb4SAlex Deucher # define SW_SMIO_INDEX(x) ((x) << 6) 93cc8dbbb4SAlex Deucher # define SW_SMIO_INDEX_MASK (1 << 6) 94cc8dbbb4SAlex Deucher # define SW_SMIO_INDEX_SHIFT 6 95cc8dbbb4SAlex Deucher # define VOLT_PWRMGT_EN (1 << 10) 962c67912cSAlex Deucher # define GPU_COUNTER_CLK (1 << 15) 97cc8dbbb4SAlex Deucher # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 98cc8dbbb4SAlex Deucher 99cc8dbbb4SAlex Deucher #define CNB_PWRMGT_CNTL 0xC0200004 100cc8dbbb4SAlex Deucher # define GNB_SLOW_MODE(x) ((x) << 0) 101cc8dbbb4SAlex Deucher # define GNB_SLOW_MODE_MASK (3 << 0) 102cc8dbbb4SAlex Deucher # define GNB_SLOW_MODE_SHIFT 0 103cc8dbbb4SAlex Deucher # define GNB_SLOW (1 << 2) 104cc8dbbb4SAlex Deucher # define FORCE_NB_PS1 (1 << 3) 105cc8dbbb4SAlex Deucher # define DPM_ENABLED (1 << 4) 1062c67912cSAlex Deucher 10741a524abSAlex Deucher #define SCLK_PWRMGT_CNTL 0xC0200008 108cc8dbbb4SAlex Deucher # define SCLK_PWRMGT_OFF (1 << 0) 10941a524abSAlex Deucher # define RESET_BUSY_CNT (1 << 4) 11041a524abSAlex Deucher # define RESET_SCLK_CNT (1 << 5) 11141a524abSAlex Deucher # define DYNAMIC_PM_EN (1 << 21) 11241a524abSAlex Deucher 11394b4adc5SAlex Deucher #define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014 11494b4adc5SAlex Deucher # define CURRENT_STATE_MASK (0xf << 4) 11594b4adc5SAlex Deucher # define CURRENT_STATE_SHIFT 4 11694b4adc5SAlex Deucher # define CURR_MCLK_INDEX_MASK (0xf << 8) 11794b4adc5SAlex Deucher # define CURR_MCLK_INDEX_SHIFT 8 11894b4adc5SAlex Deucher # define CURR_SCLK_INDEX_MASK (0x1f << 16) 11994b4adc5SAlex Deucher # define CURR_SCLK_INDEX_SHIFT 16 12094b4adc5SAlex Deucher 121cc8dbbb4SAlex Deucher #define CG_SSP 0xC0200044 122cc8dbbb4SAlex Deucher # define SST(x) ((x) << 0) 123cc8dbbb4SAlex Deucher # define SST_MASK (0xffff << 0) 124cc8dbbb4SAlex Deucher # define SSTU(x) ((x) << 16) 125cc8dbbb4SAlex Deucher # define SSTU_MASK (0xf << 16) 126cc8dbbb4SAlex Deucher 127cc8dbbb4SAlex Deucher #define CG_DISPLAY_GAP_CNTL 0xC0200060 128cc8dbbb4SAlex Deucher # define DISP_GAP(x) ((x) << 0) 129cc8dbbb4SAlex Deucher # define DISP_GAP_MASK (3 << 0) 130cc8dbbb4SAlex Deucher # define VBI_TIMER_COUNT(x) ((x) << 4) 131cc8dbbb4SAlex Deucher # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 132cc8dbbb4SAlex Deucher # define VBI_TIMER_UNIT(x) ((x) << 20) 133cc8dbbb4SAlex Deucher # define VBI_TIMER_UNIT_MASK (7 << 20) 134cc8dbbb4SAlex Deucher # define DISP_GAP_MCHG(x) ((x) << 24) 135cc8dbbb4SAlex Deucher # define DISP_GAP_MCHG_MASK (3 << 24) 136cc8dbbb4SAlex Deucher 137ae3e40e8SAlex Deucher #define SMU_VOLTAGE_STATUS 0xC0200094 138ae3e40e8SAlex Deucher # define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1) 139ae3e40e8SAlex Deucher # define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1 140ae3e40e8SAlex Deucher 14194b4adc5SAlex Deucher #define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0 14294b4adc5SAlex Deucher # define CURR_PCIE_INDEX_MASK (0xf << 24) 14394b4adc5SAlex Deucher # define CURR_PCIE_INDEX_SHIFT 24 14494b4adc5SAlex Deucher 145cc8dbbb4SAlex Deucher #define CG_ULV_PARAMETER 0xC0200158 146cc8dbbb4SAlex Deucher 14741a524abSAlex Deucher #define CG_FTV_0 0xC02001A8 148cc8dbbb4SAlex Deucher #define CG_FTV_1 0xC02001AC 149cc8dbbb4SAlex Deucher #define CG_FTV_2 0xC02001B0 150cc8dbbb4SAlex Deucher #define CG_FTV_3 0xC02001B4 151cc8dbbb4SAlex Deucher #define CG_FTV_4 0xC02001B8 152cc8dbbb4SAlex Deucher #define CG_FTV_5 0xC02001BC 153cc8dbbb4SAlex Deucher #define CG_FTV_6 0xC02001C0 154cc8dbbb4SAlex Deucher #define CG_FTV_7 0xC02001C4 155cc8dbbb4SAlex Deucher 156cc8dbbb4SAlex Deucher #define CG_DISPLAY_GAP_CNTL2 0xC0200230 15741a524abSAlex Deucher 15841a524abSAlex Deucher #define LCAC_SX0_OVR_SEL 0xC0400D04 15941a524abSAlex Deucher #define LCAC_SX0_OVR_VAL 0xC0400D08 16041a524abSAlex Deucher 161cc8dbbb4SAlex Deucher #define LCAC_MC0_CNTL 0xC0400D30 16241a524abSAlex Deucher #define LCAC_MC0_OVR_SEL 0xC0400D34 16341a524abSAlex Deucher #define LCAC_MC0_OVR_VAL 0xC0400D38 164cc8dbbb4SAlex Deucher #define LCAC_MC1_CNTL 0xC0400D3C 16541a524abSAlex Deucher #define LCAC_MC1_OVR_SEL 0xC0400D40 16641a524abSAlex Deucher #define LCAC_MC1_OVR_VAL 0xC0400D44 16741a524abSAlex Deucher 16841a524abSAlex Deucher #define LCAC_MC2_OVR_SEL 0xC0400D4C 16941a524abSAlex Deucher #define LCAC_MC2_OVR_VAL 0xC0400D50 17041a524abSAlex Deucher 17141a524abSAlex Deucher #define LCAC_MC3_OVR_SEL 0xC0400D58 17241a524abSAlex Deucher #define LCAC_MC3_OVR_VAL 0xC0400D5C 17341a524abSAlex Deucher 174cc8dbbb4SAlex Deucher #define LCAC_CPL_CNTL 0xC0400D80 17541a524abSAlex Deucher #define LCAC_CPL_OVR_SEL 0xC0400D84 17641a524abSAlex Deucher #define LCAC_CPL_OVR_VAL 0xC0400D88 17741a524abSAlex Deucher 178cc8dbbb4SAlex Deucher /* dGPU */ 179cc8dbbb4SAlex Deucher #define CG_THERMAL_CTRL 0xC0300004 180cc8dbbb4SAlex Deucher #define DPM_EVENT_SRC(x) ((x) << 0) 181cc8dbbb4SAlex Deucher #define DPM_EVENT_SRC_MASK (7 << 0) 182cc8dbbb4SAlex Deucher #define DIG_THERM_DPM(x) ((x) << 14) 183cc8dbbb4SAlex Deucher #define DIG_THERM_DPM_MASK 0x003FC000 184cc8dbbb4SAlex Deucher #define DIG_THERM_DPM_SHIFT 14 185cc8dbbb4SAlex Deucher 186cc8dbbb4SAlex Deucher #define CG_THERMAL_INT 0xC030000C 187cc8dbbb4SAlex Deucher #define CI_DIG_THERM_INTH(x) ((x) << 8) 188cc8dbbb4SAlex Deucher #define CI_DIG_THERM_INTH_MASK 0x0000FF00 189cc8dbbb4SAlex Deucher #define CI_DIG_THERM_INTH_SHIFT 8 190cc8dbbb4SAlex Deucher #define CI_DIG_THERM_INTL(x) ((x) << 16) 191cc8dbbb4SAlex Deucher #define CI_DIG_THERM_INTL_MASK 0x00FF0000 192cc8dbbb4SAlex Deucher #define CI_DIG_THERM_INTL_SHIFT 16 193cc8dbbb4SAlex Deucher #define THERM_INT_MASK_HIGH (1 << 24) 194cc8dbbb4SAlex Deucher #define THERM_INT_MASK_LOW (1 << 25) 195cc8dbbb4SAlex Deucher 196286d9cc6SAlex Deucher #define CG_MULT_THERMAL_STATUS 0xC0300014 197286d9cc6SAlex Deucher #define ASIC_MAX_TEMP(x) ((x) << 0) 198286d9cc6SAlex Deucher #define ASIC_MAX_TEMP_MASK 0x000001ff 199286d9cc6SAlex Deucher #define ASIC_MAX_TEMP_SHIFT 0 200286d9cc6SAlex Deucher #define CTF_TEMP(x) ((x) << 9) 201286d9cc6SAlex Deucher #define CTF_TEMP_MASK 0x0003fe00 202286d9cc6SAlex Deucher #define CTF_TEMP_SHIFT 9 203286d9cc6SAlex Deucher 204cc8dbbb4SAlex Deucher #define CG_SPLL_FUNC_CNTL 0xC0500140 205cc8dbbb4SAlex Deucher #define SPLL_RESET (1 << 0) 206cc8dbbb4SAlex Deucher #define SPLL_PWRON (1 << 1) 207cc8dbbb4SAlex Deucher #define SPLL_BYPASS_EN (1 << 3) 208cc8dbbb4SAlex Deucher #define SPLL_REF_DIV(x) ((x) << 5) 209cc8dbbb4SAlex Deucher #define SPLL_REF_DIV_MASK (0x3f << 5) 210cc8dbbb4SAlex Deucher #define SPLL_PDIV_A(x) ((x) << 20) 211cc8dbbb4SAlex Deucher #define SPLL_PDIV_A_MASK (0x7f << 20) 212cc8dbbb4SAlex Deucher #define SPLL_PDIV_A_SHIFT 20 213cc8dbbb4SAlex Deucher #define CG_SPLL_FUNC_CNTL_2 0xC0500144 214cc8dbbb4SAlex Deucher #define SCLK_MUX_SEL(x) ((x) << 0) 215cc8dbbb4SAlex Deucher #define SCLK_MUX_SEL_MASK (0x1ff << 0) 216cc8dbbb4SAlex Deucher #define CG_SPLL_FUNC_CNTL_3 0xC0500148 217cc8dbbb4SAlex Deucher #define SPLL_FB_DIV(x) ((x) << 0) 218cc8dbbb4SAlex Deucher #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 219cc8dbbb4SAlex Deucher #define SPLL_FB_DIV_SHIFT 0 220cc8dbbb4SAlex Deucher #define SPLL_DITHEN (1 << 28) 221cc8dbbb4SAlex Deucher #define CG_SPLL_FUNC_CNTL_4 0xC050014C 222cc8dbbb4SAlex Deucher 223cc8dbbb4SAlex Deucher #define CG_SPLL_SPREAD_SPECTRUM 0xC0500164 224cc8dbbb4SAlex Deucher #define SSEN (1 << 0) 225cc8dbbb4SAlex Deucher #define CLK_S(x) ((x) << 4) 226cc8dbbb4SAlex Deucher #define CLK_S_MASK (0xfff << 4) 227cc8dbbb4SAlex Deucher #define CLK_S_SHIFT 4 228cc8dbbb4SAlex Deucher #define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168 229cc8dbbb4SAlex Deucher #define CLK_V(x) ((x) << 0) 230cc8dbbb4SAlex Deucher #define CLK_V_MASK (0x3ffffff << 0) 231cc8dbbb4SAlex Deucher #define CLK_V_SHIFT 0 232cc8dbbb4SAlex Deucher 2337235711aSAlex Deucher #define MPLL_BYPASSCLK_SEL 0xC050019C 2347235711aSAlex Deucher # define MPLL_CLKOUT_SEL(x) ((x) << 8) 2357235711aSAlex Deucher # define MPLL_CLKOUT_SEL_MASK 0xFF00 2362c67912cSAlex Deucher #define CG_CLKPIN_CNTL 0xC05001A0 2372c67912cSAlex Deucher # define XTALIN_DIVIDE (1 << 1) 2387235711aSAlex Deucher # define BCLK_AS_XCLK (1 << 2) 2397235711aSAlex Deucher #define CG_CLKPIN_CNTL_2 0xC05001A4 2407235711aSAlex Deucher # define FORCE_BIF_REFCLK_EN (1 << 3) 2417235711aSAlex Deucher # define MUX_TCLK_TO_XCLK (1 << 8) 2427235711aSAlex Deucher #define THM_CLK_CNTL 0xC05001A8 2437235711aSAlex Deucher # define CMON_CLK_SEL(x) ((x) << 0) 2447235711aSAlex Deucher # define CMON_CLK_SEL_MASK 0xFF 2457235711aSAlex Deucher # define TMON_CLK_SEL(x) ((x) << 8) 2467235711aSAlex Deucher # define TMON_CLK_SEL_MASK 0xFF00 2477235711aSAlex Deucher #define MISC_CLK_CTRL 0xC05001AC 2487235711aSAlex Deucher # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) 2497235711aSAlex Deucher # define DEEP_SLEEP_CLK_SEL_MASK 0xFF 2507235711aSAlex Deucher # define ZCLK_SEL(x) ((x) << 8) 2517235711aSAlex Deucher # define ZCLK_SEL_MASK 0xFF00 2522c67912cSAlex Deucher 253cc8dbbb4SAlex Deucher /* KV/KB */ 25441a524abSAlex Deucher #define CG_THERMAL_INT_CTRL 0xC2100028 25541a524abSAlex Deucher #define DIG_THERM_INTH(x) ((x) << 0) 25641a524abSAlex Deucher #define DIG_THERM_INTH_MASK 0x000000FF 25741a524abSAlex Deucher #define DIG_THERM_INTH_SHIFT 0 25841a524abSAlex Deucher #define DIG_THERM_INTL(x) ((x) << 8) 25941a524abSAlex Deucher #define DIG_THERM_INTL_MASK 0x0000FF00 26041a524abSAlex Deucher #define DIG_THERM_INTL_SHIFT 8 26141a524abSAlex Deucher #define THERM_INTH_MASK (1 << 24) 26241a524abSAlex Deucher #define THERM_INTL_MASK (1 << 25) 26341a524abSAlex Deucher 2648a7cd276SAlex Deucher /* PCIE registers idx/data 0x38/0x3c */ 2657235711aSAlex Deucher #define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */ 2667235711aSAlex Deucher # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 2677235711aSAlex Deucher # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 2687235711aSAlex Deucher # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 2697235711aSAlex Deucher # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 2707235711aSAlex Deucher # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 2717235711aSAlex Deucher # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 2727235711aSAlex Deucher # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 2737235711aSAlex Deucher # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 2747235711aSAlex Deucher # define PLL_RAMP_UP_TIME_0_SHIFT 24 2757235711aSAlex Deucher #define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */ 2767235711aSAlex Deucher # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 2777235711aSAlex Deucher # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 2787235711aSAlex Deucher # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 2797235711aSAlex Deucher # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 2807235711aSAlex Deucher # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 2817235711aSAlex Deucher # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 2827235711aSAlex Deucher # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 2837235711aSAlex Deucher # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 2847235711aSAlex Deucher # define PLL_RAMP_UP_TIME_1_SHIFT 24 2857235711aSAlex Deucher 2867235711aSAlex Deucher #define PCIE_CNTL2 0x1001001c /* PCIE */ 2877235711aSAlex Deucher # define SLV_MEM_LS_EN (1 << 16) 288473359bcSAlex Deucher # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17) 2897235711aSAlex Deucher # define MST_MEM_LS_EN (1 << 18) 2907235711aSAlex Deucher # define REPLAY_MEM_LS_EN (1 << 19) 2917235711aSAlex Deucher 2928a7cd276SAlex Deucher #define PCIE_LC_STATUS1 0x1400028 /* PCIE */ 2938a7cd276SAlex Deucher # define LC_REVERSE_RCVR (1 << 0) 2948a7cd276SAlex Deucher # define LC_REVERSE_XMIT (1 << 1) 2958a7cd276SAlex Deucher # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) 2968a7cd276SAlex Deucher # define LC_OPERATING_LINK_WIDTH_SHIFT 2 2978a7cd276SAlex Deucher # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) 2988a7cd276SAlex Deucher # define LC_DETECTED_LINK_WIDTH_SHIFT 5 2998a7cd276SAlex Deucher 3007235711aSAlex Deucher #define PCIE_P_CNTL 0x1400040 /* PCIE */ 3017235711aSAlex Deucher # define P_IGNORE_EDB_ERR (1 << 6) 3027235711aSAlex Deucher 3037235711aSAlex Deucher #define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */ 3047235711aSAlex Deucher #define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */ 3057235711aSAlex Deucher 3067235711aSAlex Deucher #define PCIE_LC_CNTL 0x100100A0 /* PCIE */ 3077235711aSAlex Deucher # define LC_L0S_INACTIVITY(x) ((x) << 8) 3087235711aSAlex Deucher # define LC_L0S_INACTIVITY_MASK (0xf << 8) 3097235711aSAlex Deucher # define LC_L0S_INACTIVITY_SHIFT 8 3107235711aSAlex Deucher # define LC_L1_INACTIVITY(x) ((x) << 12) 3117235711aSAlex Deucher # define LC_L1_INACTIVITY_MASK (0xf << 12) 3127235711aSAlex Deucher # define LC_L1_INACTIVITY_SHIFT 12 3137235711aSAlex Deucher # define LC_PMI_TO_L1_DIS (1 << 16) 3147235711aSAlex Deucher # define LC_ASPM_TO_L1_DIS (1 << 24) 3157235711aSAlex Deucher 3168a7cd276SAlex Deucher #define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */ 3178a7cd276SAlex Deucher # define LC_LINK_WIDTH_SHIFT 0 3188a7cd276SAlex Deucher # define LC_LINK_WIDTH_MASK 0x7 3198a7cd276SAlex Deucher # define LC_LINK_WIDTH_X0 0 3208a7cd276SAlex Deucher # define LC_LINK_WIDTH_X1 1 3218a7cd276SAlex Deucher # define LC_LINK_WIDTH_X2 2 3228a7cd276SAlex Deucher # define LC_LINK_WIDTH_X4 3 3238a7cd276SAlex Deucher # define LC_LINK_WIDTH_X8 4 3248a7cd276SAlex Deucher # define LC_LINK_WIDTH_X16 6 3258a7cd276SAlex Deucher # define LC_LINK_WIDTH_RD_SHIFT 4 3268a7cd276SAlex Deucher # define LC_LINK_WIDTH_RD_MASK 0x70 3278a7cd276SAlex Deucher # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 3288a7cd276SAlex Deucher # define LC_RECONFIG_NOW (1 << 8) 3298a7cd276SAlex Deucher # define LC_RENEGOTIATION_SUPPORT (1 << 9) 3308a7cd276SAlex Deucher # define LC_RENEGOTIATE_EN (1 << 10) 3318a7cd276SAlex Deucher # define LC_SHORT_RECONFIG_EN (1 << 11) 3328a7cd276SAlex Deucher # define LC_UPCONFIGURE_SUPPORT (1 << 12) 3338a7cd276SAlex Deucher # define LC_UPCONFIGURE_DIS (1 << 13) 3348a7cd276SAlex Deucher # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 3358a7cd276SAlex Deucher # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 3368a7cd276SAlex Deucher # define LC_DYN_LANES_PWR_STATE_SHIFT 21 3377235711aSAlex Deucher #define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */ 3387235711aSAlex Deucher # define LC_XMIT_N_FTS(x) ((x) << 0) 3397235711aSAlex Deucher # define LC_XMIT_N_FTS_MASK (0xff << 0) 3407235711aSAlex Deucher # define LC_XMIT_N_FTS_SHIFT 0 3417235711aSAlex Deucher # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) 3427235711aSAlex Deucher # define LC_N_FTS_MASK (0xff << 24) 3438a7cd276SAlex Deucher #define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */ 3448a7cd276SAlex Deucher # define LC_GEN2_EN_STRAP (1 << 0) 3458a7cd276SAlex Deucher # define LC_GEN3_EN_STRAP (1 << 1) 3468a7cd276SAlex Deucher # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) 3478a7cd276SAlex Deucher # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) 3488a7cd276SAlex Deucher # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 3498a7cd276SAlex Deucher # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) 3508a7cd276SAlex Deucher # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) 3518a7cd276SAlex Deucher # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) 3528a7cd276SAlex Deucher # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) 3538a7cd276SAlex Deucher # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) 3548a7cd276SAlex Deucher # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) 3558a7cd276SAlex Deucher # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 3568a7cd276SAlex Deucher # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ 3578a7cd276SAlex Deucher # define LC_CURRENT_DATA_RATE_SHIFT 13 3588a7cd276SAlex Deucher # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) 3598a7cd276SAlex Deucher # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) 3608a7cd276SAlex Deucher # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) 3618a7cd276SAlex Deucher # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) 3628a7cd276SAlex Deucher # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) 3638a7cd276SAlex Deucher 3647235711aSAlex Deucher #define PCIE_LC_CNTL2 0x100100B1 /* PCIE */ 3657235711aSAlex Deucher # define LC_ALLOW_PDWN_IN_L1 (1 << 17) 3667235711aSAlex Deucher # define LC_ALLOW_PDWN_IN_L23 (1 << 18) 3677235711aSAlex Deucher 3687235711aSAlex Deucher #define PCIE_LC_CNTL3 0x100100B5 /* PCIE */ 3697235711aSAlex Deucher # define LC_GO_TO_RECOVERY (1 << 30) 3708a7cd276SAlex Deucher #define PCIE_LC_CNTL4 0x100100B6 /* PCIE */ 3718a7cd276SAlex Deucher # define LC_REDO_EQ (1 << 5) 3728a7cd276SAlex Deucher # define LC_SET_QUIESCE (1 << 13) 3738a7cd276SAlex Deucher 3748a7cd276SAlex Deucher /* direct registers */ 3756e2c3c0aSAlex Deucher #define PCIE_INDEX 0x38 3766e2c3c0aSAlex Deucher #define PCIE_DATA 0x3C 3776e2c3c0aSAlex Deucher 37841a524abSAlex Deucher #define SMC_IND_INDEX_0 0x200 37941a524abSAlex Deucher #define SMC_IND_DATA_0 0x204 38041a524abSAlex Deucher 38141a524abSAlex Deucher #define SMC_IND_ACCESS_CNTL 0x240 38241a524abSAlex Deucher #define AUTO_INCREMENT_IND_0 (1 << 0) 38341a524abSAlex Deucher 38441a524abSAlex Deucher #define SMC_MESSAGE_0 0x250 38541a524abSAlex Deucher #define SMC_MSG_MASK 0xffff 38641a524abSAlex Deucher #define SMC_RESP_0 0x254 38741a524abSAlex Deucher #define SMC_RESP_MASK 0xffff 38841a524abSAlex Deucher 38941a524abSAlex Deucher #define SMC_MSG_ARG_0 0x290 39041a524abSAlex Deucher 3911c49165dSAlex Deucher #define VGA_HDP_CONTROL 0x328 3921c49165dSAlex Deucher #define VGA_MEMORY_DISABLE (1 << 4) 3931c49165dSAlex Deucher 3948cc1a532SAlex Deucher #define DMIF_ADDR_CALC 0xC00 3958cc1a532SAlex Deucher 396bc01a8c7SAlex Deucher #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 397bc01a8c7SAlex Deucher # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 398bc01a8c7SAlex Deucher # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 399bc01a8c7SAlex Deucher 4001c49165dSAlex Deucher #define SRBM_GFX_CNTL 0xE44 4011c49165dSAlex Deucher #define PIPEID(x) ((x) << 0) 4021c49165dSAlex Deucher #define MEID(x) ((x) << 2) 4031c49165dSAlex Deucher #define VMID(x) ((x) << 4) 4041c49165dSAlex Deucher #define QUEUEID(x) ((x) << 8) 4051c49165dSAlex Deucher 4066f2043ceSAlex Deucher #define SRBM_STATUS2 0xE4C 407cc066715SAlex Deucher #define SDMA_BUSY (1 << 5) 408cc066715SAlex Deucher #define SDMA1_BUSY (1 << 6) 4096f2043ceSAlex Deucher #define SRBM_STATUS 0xE50 410cc066715SAlex Deucher #define UVD_RQ_PENDING (1 << 1) 411cc066715SAlex Deucher #define GRBM_RQ_PENDING (1 << 5) 412cc066715SAlex Deucher #define VMC_BUSY (1 << 8) 413cc066715SAlex Deucher #define MCB_BUSY (1 << 9) 414cc066715SAlex Deucher #define MCB_NON_DISPLAY_BUSY (1 << 10) 415cc066715SAlex Deucher #define MCC_BUSY (1 << 11) 416cc066715SAlex Deucher #define MCD_BUSY (1 << 12) 417cc066715SAlex Deucher #define SEM_BUSY (1 << 14) 418cc066715SAlex Deucher #define IH_BUSY (1 << 17) 419cc066715SAlex Deucher #define UVD_BUSY (1 << 19) 4206f2043ceSAlex Deucher 42121a93e13SAlex Deucher #define SRBM_SOFT_RESET 0xE60 42221a93e13SAlex Deucher #define SOFT_RESET_BIF (1 << 1) 42321a93e13SAlex Deucher #define SOFT_RESET_R0PLL (1 << 4) 42421a93e13SAlex Deucher #define SOFT_RESET_DC (1 << 5) 42521a93e13SAlex Deucher #define SOFT_RESET_SDMA1 (1 << 6) 42621a93e13SAlex Deucher #define SOFT_RESET_GRBM (1 << 8) 42721a93e13SAlex Deucher #define SOFT_RESET_HDP (1 << 9) 42821a93e13SAlex Deucher #define SOFT_RESET_IH (1 << 10) 42921a93e13SAlex Deucher #define SOFT_RESET_MC (1 << 11) 43021a93e13SAlex Deucher #define SOFT_RESET_ROM (1 << 14) 43121a93e13SAlex Deucher #define SOFT_RESET_SEM (1 << 15) 43221a93e13SAlex Deucher #define SOFT_RESET_VMC (1 << 17) 43321a93e13SAlex Deucher #define SOFT_RESET_SDMA (1 << 20) 43421a93e13SAlex Deucher #define SOFT_RESET_TST (1 << 21) 43521a93e13SAlex Deucher #define SOFT_RESET_REGBB (1 << 22) 43621a93e13SAlex Deucher #define SOFT_RESET_ORB (1 << 23) 43721a93e13SAlex Deucher #define SOFT_RESET_VCE (1 << 24) 43821a93e13SAlex Deucher 4391c49165dSAlex Deucher #define VM_L2_CNTL 0x1400 4401c49165dSAlex Deucher #define ENABLE_L2_CACHE (1 << 0) 4411c49165dSAlex Deucher #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 4421c49165dSAlex Deucher #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 4431c49165dSAlex Deucher #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 4441c49165dSAlex Deucher #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 4451c49165dSAlex Deucher #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 4461c49165dSAlex Deucher #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 4471c49165dSAlex Deucher #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 4481c49165dSAlex Deucher #define VM_L2_CNTL2 0x1404 4491c49165dSAlex Deucher #define INVALIDATE_ALL_L1_TLBS (1 << 0) 4501c49165dSAlex Deucher #define INVALIDATE_L2_CACHE (1 << 1) 4511c49165dSAlex Deucher #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 4521c49165dSAlex Deucher #define INVALIDATE_PTE_AND_PDE_CACHES 0 4531c49165dSAlex Deucher #define INVALIDATE_ONLY_PTE_CACHES 1 4541c49165dSAlex Deucher #define INVALIDATE_ONLY_PDE_CACHES 2 4551c49165dSAlex Deucher #define VM_L2_CNTL3 0x1408 4561c49165dSAlex Deucher #define BANK_SELECT(x) ((x) << 0) 4571c49165dSAlex Deucher #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 4581c49165dSAlex Deucher #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 4591c49165dSAlex Deucher #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 4601c49165dSAlex Deucher #define VM_L2_STATUS 0x140C 4611c49165dSAlex Deucher #define L2_BUSY (1 << 0) 4621c49165dSAlex Deucher #define VM_CONTEXT0_CNTL 0x1410 4631c49165dSAlex Deucher #define ENABLE_CONTEXT (1 << 0) 4641c49165dSAlex Deucher #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 465a00024b0SAlex Deucher #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 4661c49165dSAlex Deucher #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 467a00024b0SAlex Deucher #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 468a00024b0SAlex Deucher #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 469a00024b0SAlex Deucher #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 470a00024b0SAlex Deucher #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 471a00024b0SAlex Deucher #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 472a00024b0SAlex Deucher #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 473a00024b0SAlex Deucher #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 474a00024b0SAlex Deucher #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 475a00024b0SAlex Deucher #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 476a00024b0SAlex Deucher #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 4771c49165dSAlex Deucher #define VM_CONTEXT1_CNTL 0x1414 4781c49165dSAlex Deucher #define VM_CONTEXT0_CNTL2 0x1430 4791c49165dSAlex Deucher #define VM_CONTEXT1_CNTL2 0x1434 4801c49165dSAlex Deucher #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 4811c49165dSAlex Deucher #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 4821c49165dSAlex Deucher #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 4831c49165dSAlex Deucher #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 4841c49165dSAlex Deucher #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 4851c49165dSAlex Deucher #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 4861c49165dSAlex Deucher #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 4871c49165dSAlex Deucher #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 4881c49165dSAlex Deucher 4891c49165dSAlex Deucher #define VM_INVALIDATE_REQUEST 0x1478 4901c49165dSAlex Deucher #define VM_INVALIDATE_RESPONSE 0x147c 4911c49165dSAlex Deucher 4929d97c99bSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 4933ec7d11bSAlex Deucher #define PROTECTIONS_MASK (0xf << 0) 4943ec7d11bSAlex Deucher #define PROTECTIONS_SHIFT 0 4953ec7d11bSAlex Deucher /* bit 0: range 4963ec7d11bSAlex Deucher * bit 1: pde0 4973ec7d11bSAlex Deucher * bit 2: valid 4983ec7d11bSAlex Deucher * bit 3: read 4993ec7d11bSAlex Deucher * bit 4: write 5003ec7d11bSAlex Deucher */ 5013ec7d11bSAlex Deucher #define MEMORY_CLIENT_ID_MASK (0xff << 12) 5023ec7d11bSAlex Deucher #define MEMORY_CLIENT_ID_SHIFT 12 5033ec7d11bSAlex Deucher #define MEMORY_CLIENT_RW_MASK (1 << 24) 5043ec7d11bSAlex Deucher #define MEMORY_CLIENT_RW_SHIFT 24 5053ec7d11bSAlex Deucher #define FAULT_VMID_MASK (0xf << 25) 5063ec7d11bSAlex Deucher #define FAULT_VMID_SHIFT 25 5073ec7d11bSAlex Deucher 5083ec7d11bSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4 5099d97c99bSAlex Deucher 5109d97c99bSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 5119d97c99bSAlex Deucher 5121c49165dSAlex Deucher #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 5131c49165dSAlex Deucher #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 5141c49165dSAlex Deucher 5151c49165dSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 5161c49165dSAlex Deucher #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 5171c49165dSAlex Deucher #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 5181c49165dSAlex Deucher #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 5191c49165dSAlex Deucher #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 5201c49165dSAlex Deucher #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 5211c49165dSAlex Deucher #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 5221c49165dSAlex Deucher #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 5231c49165dSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 5241c49165dSAlex Deucher #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 5251c49165dSAlex Deucher 5261c49165dSAlex Deucher #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 5271c49165dSAlex Deucher #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 5281c49165dSAlex Deucher 52922c775ceSAlex Deucher #define VM_L2_CG 0x15c0 53022c775ceSAlex Deucher #define MC_CG_ENABLE (1 << 18) 53122c775ceSAlex Deucher #define MC_LS_ENABLE (1 << 19) 53222c775ceSAlex Deucher 5338cc1a532SAlex Deucher #define MC_SHARED_CHMAP 0x2004 5348cc1a532SAlex Deucher #define NOOFCHAN_SHIFT 12 5358cc1a532SAlex Deucher #define NOOFCHAN_MASK 0x0000f000 5368cc1a532SAlex Deucher #define MC_SHARED_CHREMAP 0x2008 5378cc1a532SAlex Deucher 5381c49165dSAlex Deucher #define CHUB_CONTROL 0x1864 5391c49165dSAlex Deucher #define BYPASS_VM (1 << 0) 5401c49165dSAlex Deucher 5411c49165dSAlex Deucher #define MC_VM_FB_LOCATION 0x2024 5421c49165dSAlex Deucher #define MC_VM_AGP_TOP 0x2028 5431c49165dSAlex Deucher #define MC_VM_AGP_BOT 0x202C 5441c49165dSAlex Deucher #define MC_VM_AGP_BASE 0x2030 5451c49165dSAlex Deucher #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 5461c49165dSAlex Deucher #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 5471c49165dSAlex Deucher #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 5481c49165dSAlex Deucher 5491c49165dSAlex Deucher #define MC_VM_MX_L1_TLB_CNTL 0x2064 5501c49165dSAlex Deucher #define ENABLE_L1_TLB (1 << 0) 5511c49165dSAlex Deucher #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 5521c49165dSAlex Deucher #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 5531c49165dSAlex Deucher #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 5541c49165dSAlex Deucher #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 5551c49165dSAlex Deucher #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 5561c49165dSAlex Deucher #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 5571c49165dSAlex Deucher #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 5581c49165dSAlex Deucher #define MC_VM_FB_OFFSET 0x2068 5591c49165dSAlex Deucher 560bc8273feSAlex Deucher #define MC_SHARED_BLACKOUT_CNTL 0x20ac 561bc8273feSAlex Deucher 56222c775ceSAlex Deucher #define MC_HUB_MISC_HUB_CG 0x20b8 56322c775ceSAlex Deucher #define MC_HUB_MISC_VM_CG 0x20bc 56422c775ceSAlex Deucher 56522c775ceSAlex Deucher #define MC_HUB_MISC_SIP_CG 0x20c0 56622c775ceSAlex Deucher 56722c775ceSAlex Deucher #define MC_XPB_CLK_GAT 0x2478 56822c775ceSAlex Deucher 56922c775ceSAlex Deucher #define MC_CITF_MISC_RD_CG 0x2648 57022c775ceSAlex Deucher #define MC_CITF_MISC_WR_CG 0x264c 57122c775ceSAlex Deucher #define MC_CITF_MISC_VM_CG 0x2650 57222c775ceSAlex Deucher 5738cc1a532SAlex Deucher #define MC_ARB_RAMCFG 0x2760 5748cc1a532SAlex Deucher #define NOOFBANK_SHIFT 0 5758cc1a532SAlex Deucher #define NOOFBANK_MASK 0x00000003 5768cc1a532SAlex Deucher #define NOOFRANK_SHIFT 2 5778cc1a532SAlex Deucher #define NOOFRANK_MASK 0x00000004 5788cc1a532SAlex Deucher #define NOOFROWS_SHIFT 3 5798cc1a532SAlex Deucher #define NOOFROWS_MASK 0x00000038 5808cc1a532SAlex Deucher #define NOOFCOLS_SHIFT 6 5818cc1a532SAlex Deucher #define NOOFCOLS_MASK 0x000000C0 5828cc1a532SAlex Deucher #define CHANSIZE_SHIFT 8 5838cc1a532SAlex Deucher #define CHANSIZE_MASK 0x00000100 5848cc1a532SAlex Deucher #define NOOFGROUPS_SHIFT 12 5858cc1a532SAlex Deucher #define NOOFGROUPS_MASK 0x00001000 5868cc1a532SAlex Deucher 587cc8dbbb4SAlex Deucher #define MC_ARB_DRAM_TIMING 0x2774 588cc8dbbb4SAlex Deucher #define MC_ARB_DRAM_TIMING2 0x2778 589cc8dbbb4SAlex Deucher 590cc8dbbb4SAlex Deucher #define MC_ARB_BURST_TIME 0x2808 591cc8dbbb4SAlex Deucher #define STATE0(x) ((x) << 0) 592cc8dbbb4SAlex Deucher #define STATE0_MASK (0x1f << 0) 593cc8dbbb4SAlex Deucher #define STATE0_SHIFT 0 594cc8dbbb4SAlex Deucher #define STATE1(x) ((x) << 5) 595cc8dbbb4SAlex Deucher #define STATE1_MASK (0x1f << 5) 596cc8dbbb4SAlex Deucher #define STATE1_SHIFT 5 597cc8dbbb4SAlex Deucher #define STATE2(x) ((x) << 10) 598cc8dbbb4SAlex Deucher #define STATE2_MASK (0x1f << 10) 599cc8dbbb4SAlex Deucher #define STATE2_SHIFT 10 600cc8dbbb4SAlex Deucher #define STATE3(x) ((x) << 15) 601cc8dbbb4SAlex Deucher #define STATE3_MASK (0x1f << 15) 602cc8dbbb4SAlex Deucher #define STATE3_SHIFT 15 603cc8dbbb4SAlex Deucher 604cc8dbbb4SAlex Deucher #define MC_SEQ_RAS_TIMING 0x28a0 605cc8dbbb4SAlex Deucher #define MC_SEQ_CAS_TIMING 0x28a4 606cc8dbbb4SAlex Deucher #define MC_SEQ_MISC_TIMING 0x28a8 607cc8dbbb4SAlex Deucher #define MC_SEQ_MISC_TIMING2 0x28ac 608cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_TIMING 0x28b0 609cc8dbbb4SAlex Deucher #define MC_SEQ_RD_CTL_D0 0x28b4 610cc8dbbb4SAlex Deucher #define MC_SEQ_RD_CTL_D1 0x28b8 611cc8dbbb4SAlex Deucher #define MC_SEQ_WR_CTL_D0 0x28bc 612cc8dbbb4SAlex Deucher #define MC_SEQ_WR_CTL_D1 0x28c0 613cc8dbbb4SAlex Deucher 614bc8273feSAlex Deucher #define MC_SEQ_SUP_CNTL 0x28c8 615bc8273feSAlex Deucher #define RUN_MASK (1 << 0) 616bc8273feSAlex Deucher #define MC_SEQ_SUP_PGM 0x28cc 617cc8dbbb4SAlex Deucher #define MC_PMG_AUTO_CMD 0x28d0 618bc8273feSAlex Deucher 619bc8273feSAlex Deucher #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 620bc8273feSAlex Deucher #define TRAIN_DONE_D0 (1 << 30) 621bc8273feSAlex Deucher #define TRAIN_DONE_D1 (1 << 31) 622bc8273feSAlex Deucher 623bc8273feSAlex Deucher #define MC_IO_PAD_CNTL_D0 0x29d0 624bc8273feSAlex Deucher #define MEM_FALL_OUT_CMD (1 << 8) 625bc8273feSAlex Deucher 626cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0 0x2a00 627cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 628cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 629cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_VEN_ID_VALUE 3 630cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_REV_ID_SHIFT 12 631cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 632cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_REV_ID_VALUE 1 633cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_GDDR5_SHIFT 28 634cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 635cc8dbbb4SAlex Deucher #define MC_SEQ_MISC0_GDDR5_VALUE 5 636cc8dbbb4SAlex Deucher #define MC_SEQ_MISC1 0x2a04 637cc8dbbb4SAlex Deucher #define MC_SEQ_RESERVE_M 0x2a08 638cc8dbbb4SAlex Deucher #define MC_PMG_CMD_EMRS 0x2a0c 639cc8dbbb4SAlex Deucher 640bc8273feSAlex Deucher #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 641bc8273feSAlex Deucher #define MC_SEQ_IO_DEBUG_DATA 0x2a48 642bc8273feSAlex Deucher 643cc8dbbb4SAlex Deucher #define MC_SEQ_MISC5 0x2a54 644cc8dbbb4SAlex Deucher #define MC_SEQ_MISC6 0x2a58 645cc8dbbb4SAlex Deucher 646cc8dbbb4SAlex Deucher #define MC_SEQ_MISC7 0x2a64 647cc8dbbb4SAlex Deucher 648cc8dbbb4SAlex Deucher #define MC_SEQ_RAS_TIMING_LP 0x2a6c 649cc8dbbb4SAlex Deucher #define MC_SEQ_CAS_TIMING_LP 0x2a70 650cc8dbbb4SAlex Deucher #define MC_SEQ_MISC_TIMING_LP 0x2a74 651cc8dbbb4SAlex Deucher #define MC_SEQ_MISC_TIMING2_LP 0x2a78 652cc8dbbb4SAlex Deucher #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 653cc8dbbb4SAlex Deucher #define MC_SEQ_WR_CTL_D1_LP 0x2a80 654cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 655cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 656cc8dbbb4SAlex Deucher 657cc8dbbb4SAlex Deucher #define MC_PMG_CMD_MRS 0x2aac 658cc8dbbb4SAlex Deucher 659cc8dbbb4SAlex Deucher #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 660cc8dbbb4SAlex Deucher #define MC_SEQ_RD_CTL_D1_LP 0x2b20 661cc8dbbb4SAlex Deucher 662cc8dbbb4SAlex Deucher #define MC_PMG_CMD_MRS1 0x2b44 663cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 664cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_TIMING_LP 0x2b4c 665cc8dbbb4SAlex Deucher 666cc8dbbb4SAlex Deucher #define MC_SEQ_WR_CTL_2 0x2b54 667cc8dbbb4SAlex Deucher #define MC_SEQ_WR_CTL_2_LP 0x2b58 668cc8dbbb4SAlex Deucher #define MC_PMG_CMD_MRS2 0x2b5c 669cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 670cc8dbbb4SAlex Deucher 671cc8dbbb4SAlex Deucher #define MCLK_PWRMGT_CNTL 0x2ba0 672cc8dbbb4SAlex Deucher # define DLL_SPEED(x) ((x) << 0) 673cc8dbbb4SAlex Deucher # define DLL_SPEED_MASK (0x1f << 0) 674cc8dbbb4SAlex Deucher # define DLL_READY (1 << 6) 675cc8dbbb4SAlex Deucher # define MC_INT_CNTL (1 << 7) 676cc8dbbb4SAlex Deucher # define MRDCK0_PDNB (1 << 8) 677cc8dbbb4SAlex Deucher # define MRDCK1_PDNB (1 << 9) 678cc8dbbb4SAlex Deucher # define MRDCK0_RESET (1 << 16) 679cc8dbbb4SAlex Deucher # define MRDCK1_RESET (1 << 17) 680cc8dbbb4SAlex Deucher # define DLL_READY_READ (1 << 24) 681cc8dbbb4SAlex Deucher #define DLL_CNTL 0x2ba4 682cc8dbbb4SAlex Deucher # define MRDCK0_BYPASS (1 << 24) 683cc8dbbb4SAlex Deucher # define MRDCK1_BYPASS (1 << 25) 684cc8dbbb4SAlex Deucher 685cc8dbbb4SAlex Deucher #define MPLL_FUNC_CNTL 0x2bb4 686cc8dbbb4SAlex Deucher #define BWCTRL(x) ((x) << 20) 687cc8dbbb4SAlex Deucher #define BWCTRL_MASK (0xff << 20) 688cc8dbbb4SAlex Deucher #define MPLL_FUNC_CNTL_1 0x2bb8 689cc8dbbb4SAlex Deucher #define VCO_MODE(x) ((x) << 0) 690cc8dbbb4SAlex Deucher #define VCO_MODE_MASK (3 << 0) 691cc8dbbb4SAlex Deucher #define CLKFRAC(x) ((x) << 4) 692cc8dbbb4SAlex Deucher #define CLKFRAC_MASK (0xfff << 4) 693cc8dbbb4SAlex Deucher #define CLKF(x) ((x) << 16) 694cc8dbbb4SAlex Deucher #define CLKF_MASK (0xfff << 16) 695cc8dbbb4SAlex Deucher #define MPLL_FUNC_CNTL_2 0x2bbc 696cc8dbbb4SAlex Deucher #define MPLL_AD_FUNC_CNTL 0x2bc0 697cc8dbbb4SAlex Deucher #define YCLK_POST_DIV(x) ((x) << 0) 698cc8dbbb4SAlex Deucher #define YCLK_POST_DIV_MASK (7 << 0) 699cc8dbbb4SAlex Deucher #define MPLL_DQ_FUNC_CNTL 0x2bc4 700cc8dbbb4SAlex Deucher #define YCLK_SEL(x) ((x) << 4) 701cc8dbbb4SAlex Deucher #define YCLK_SEL_MASK (1 << 4) 702cc8dbbb4SAlex Deucher 703cc8dbbb4SAlex Deucher #define MPLL_SS1 0x2bcc 704cc8dbbb4SAlex Deucher #define CLKV(x) ((x) << 0) 705cc8dbbb4SAlex Deucher #define CLKV_MASK (0x3ffffff << 0) 706cc8dbbb4SAlex Deucher #define MPLL_SS2 0x2bd0 707cc8dbbb4SAlex Deucher #define CLKS(x) ((x) << 0) 708cc8dbbb4SAlex Deucher #define CLKS_MASK (0xfff << 0) 709cc8dbbb4SAlex Deucher 7108cc1a532SAlex Deucher #define HDP_HOST_PATH_CNTL 0x2C00 71122c775ceSAlex Deucher #define CLOCK_GATING_DIS (1 << 23) 7128cc1a532SAlex Deucher #define HDP_NONSURFACE_BASE 0x2C04 7138cc1a532SAlex Deucher #define HDP_NONSURFACE_INFO 0x2C08 7148cc1a532SAlex Deucher #define HDP_NONSURFACE_SIZE 0x2C0C 7158cc1a532SAlex Deucher 7168cc1a532SAlex Deucher #define HDP_ADDR_CONFIG 0x2F48 7178cc1a532SAlex Deucher #define HDP_MISC_CNTL 0x2F4C 7188cc1a532SAlex Deucher #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 71922c775ceSAlex Deucher #define HDP_MEM_POWER_LS 0x2F50 72022c775ceSAlex Deucher #define HDP_LS_ENABLE (1 << 0) 72122c775ceSAlex Deucher 72222c775ceSAlex Deucher #define ATC_MISC_CG 0x3350 7238cc1a532SAlex Deucher 724cc8dbbb4SAlex Deucher #define MC_SEQ_CNTL_3 0x3600 725cc8dbbb4SAlex Deucher # define CAC_EN (1 << 31) 726cc8dbbb4SAlex Deucher #define MC_SEQ_G5PDX_CTRL 0x3604 727cc8dbbb4SAlex Deucher #define MC_SEQ_G5PDX_CTRL_LP 0x3608 728cc8dbbb4SAlex Deucher #define MC_SEQ_G5PDX_CMD0 0x360c 729cc8dbbb4SAlex Deucher #define MC_SEQ_G5PDX_CMD0_LP 0x3610 730cc8dbbb4SAlex Deucher #define MC_SEQ_G5PDX_CMD1 0x3614 731cc8dbbb4SAlex Deucher #define MC_SEQ_G5PDX_CMD1_LP 0x3618 732cc8dbbb4SAlex Deucher 733cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_DVS_CTL 0x3628 734cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_DVS_CTL_LP 0x362c 735cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_DVS_CMD 0x3630 736cc8dbbb4SAlex Deucher #define MC_SEQ_PMG_DVS_CMD_LP 0x3634 737cc8dbbb4SAlex Deucher #define MC_SEQ_DLL_STBY 0x3638 738cc8dbbb4SAlex Deucher #define MC_SEQ_DLL_STBY_LP 0x363c 739cc8dbbb4SAlex Deucher 740a59781bbSAlex Deucher #define IH_RB_CNTL 0x3e00 741a59781bbSAlex Deucher # define IH_RB_ENABLE (1 << 0) 742a59781bbSAlex Deucher # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 743a59781bbSAlex Deucher # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 744a59781bbSAlex Deucher # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 745a59781bbSAlex Deucher # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 746a59781bbSAlex Deucher # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 747a59781bbSAlex Deucher # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 748a59781bbSAlex Deucher #define IH_RB_BASE 0x3e04 749a59781bbSAlex Deucher #define IH_RB_RPTR 0x3e08 750a59781bbSAlex Deucher #define IH_RB_WPTR 0x3e0c 751a59781bbSAlex Deucher # define RB_OVERFLOW (1 << 0) 752a59781bbSAlex Deucher # define WPTR_OFFSET_MASK 0x3fffc 753a59781bbSAlex Deucher #define IH_RB_WPTR_ADDR_HI 0x3e10 754a59781bbSAlex Deucher #define IH_RB_WPTR_ADDR_LO 0x3e14 755a59781bbSAlex Deucher #define IH_CNTL 0x3e18 756a59781bbSAlex Deucher # define ENABLE_INTR (1 << 0) 757a59781bbSAlex Deucher # define IH_MC_SWAP(x) ((x) << 1) 758a59781bbSAlex Deucher # define IH_MC_SWAP_NONE 0 759a59781bbSAlex Deucher # define IH_MC_SWAP_16BIT 1 760a59781bbSAlex Deucher # define IH_MC_SWAP_32BIT 2 761a59781bbSAlex Deucher # define IH_MC_SWAP_64BIT 3 762a59781bbSAlex Deucher # define RPTR_REARM (1 << 4) 763a59781bbSAlex Deucher # define MC_WRREQ_CREDIT(x) ((x) << 15) 764a59781bbSAlex Deucher # define MC_WR_CLEAN_CNT(x) ((x) << 20) 765a59781bbSAlex Deucher # define MC_VMID(x) ((x) << 25) 766a59781bbSAlex Deucher 767cc8dbbb4SAlex Deucher #define BIF_LNCNT_RESET 0x5220 768cc8dbbb4SAlex Deucher # define RESET_LNCNT_EN (1 << 0) 769cc8dbbb4SAlex Deucher 7701c49165dSAlex Deucher #define CONFIG_MEMSIZE 0x5428 7711c49165dSAlex Deucher 772a59781bbSAlex Deucher #define INTERRUPT_CNTL 0x5468 773a59781bbSAlex Deucher # define IH_DUMMY_RD_OVERRIDE (1 << 0) 774a59781bbSAlex Deucher # define IH_DUMMY_RD_EN (1 << 1) 775a59781bbSAlex Deucher # define IH_REQ_NONSNOOP_EN (1 << 3) 776a59781bbSAlex Deucher # define GEN_IH_INT_EN (1 << 8) 777a59781bbSAlex Deucher #define INTERRUPT_CNTL2 0x546c 778a59781bbSAlex Deucher 7791c49165dSAlex Deucher #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 7801c49165dSAlex Deucher 7818cc1a532SAlex Deucher #define BIF_FB_EN 0x5490 7828cc1a532SAlex Deucher #define FB_READ_EN (1 << 0) 7838cc1a532SAlex Deucher #define FB_WRITE_EN (1 << 1) 7848cc1a532SAlex Deucher 7851c49165dSAlex Deucher #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 7861c49165dSAlex Deucher 7872cae3bc3SAlex Deucher #define GPU_HDP_FLUSH_REQ 0x54DC 7882cae3bc3SAlex Deucher #define GPU_HDP_FLUSH_DONE 0x54E0 7892cae3bc3SAlex Deucher #define CP0 (1 << 0) 7902cae3bc3SAlex Deucher #define CP1 (1 << 1) 7912cae3bc3SAlex Deucher #define CP2 (1 << 2) 7922cae3bc3SAlex Deucher #define CP3 (1 << 3) 7932cae3bc3SAlex Deucher #define CP4 (1 << 4) 7942cae3bc3SAlex Deucher #define CP5 (1 << 5) 7952cae3bc3SAlex Deucher #define CP6 (1 << 6) 7962cae3bc3SAlex Deucher #define CP7 (1 << 7) 7972cae3bc3SAlex Deucher #define CP8 (1 << 8) 7982cae3bc3SAlex Deucher #define CP9 (1 << 9) 7992cae3bc3SAlex Deucher #define SDMA0 (1 << 10) 8002cae3bc3SAlex Deucher #define SDMA1 (1 << 11) 8012cae3bc3SAlex Deucher 802cd84a27dSAlex Deucher /* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */ 803cd84a27dSAlex Deucher #define LB_MEMORY_CTRL 0x6b04 804cd84a27dSAlex Deucher #define LB_MEMORY_SIZE(x) ((x) << 0) 805cd84a27dSAlex Deucher #define LB_MEMORY_CONFIG(x) ((x) << 20) 806cd84a27dSAlex Deucher 807cd84a27dSAlex Deucher #define DPG_WATERMARK_MASK_CONTROL 0x6cc8 808cd84a27dSAlex Deucher # define LATENCY_WATERMARK_MASK(x) ((x) << 8) 809cd84a27dSAlex Deucher #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 810cd84a27dSAlex Deucher # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 811cd84a27dSAlex Deucher # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 812cd84a27dSAlex Deucher 813a59781bbSAlex Deucher /* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */ 814a59781bbSAlex Deucher #define LB_VLINE_STATUS 0x6b24 815a59781bbSAlex Deucher # define VLINE_OCCURRED (1 << 0) 816a59781bbSAlex Deucher # define VLINE_ACK (1 << 4) 817a59781bbSAlex Deucher # define VLINE_STAT (1 << 12) 818a59781bbSAlex Deucher # define VLINE_INTERRUPT (1 << 16) 819a59781bbSAlex Deucher # define VLINE_INTERRUPT_TYPE (1 << 17) 820a59781bbSAlex Deucher /* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */ 821a59781bbSAlex Deucher #define LB_VBLANK_STATUS 0x6b2c 822a59781bbSAlex Deucher # define VBLANK_OCCURRED (1 << 0) 823a59781bbSAlex Deucher # define VBLANK_ACK (1 << 4) 824a59781bbSAlex Deucher # define VBLANK_STAT (1 << 12) 825a59781bbSAlex Deucher # define VBLANK_INTERRUPT (1 << 16) 826a59781bbSAlex Deucher # define VBLANK_INTERRUPT_TYPE (1 << 17) 827a59781bbSAlex Deucher 828a59781bbSAlex Deucher /* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */ 829a59781bbSAlex Deucher #define LB_INTERRUPT_MASK 0x6b20 830a59781bbSAlex Deucher # define VBLANK_INTERRUPT_MASK (1 << 0) 831a59781bbSAlex Deucher # define VLINE_INTERRUPT_MASK (1 << 4) 832a59781bbSAlex Deucher # define VLINE2_INTERRUPT_MASK (1 << 8) 833a59781bbSAlex Deucher 834a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS 0x60f4 835a59781bbSAlex Deucher # define LB_D1_VLINE_INTERRUPT (1 << 2) 836a59781bbSAlex Deucher # define LB_D1_VBLANK_INTERRUPT (1 << 3) 837a59781bbSAlex Deucher # define DC_HPD1_INTERRUPT (1 << 17) 838a59781bbSAlex Deucher # define DC_HPD1_RX_INTERRUPT (1 << 18) 839a59781bbSAlex Deucher # define DACA_AUTODETECT_INTERRUPT (1 << 22) 840a59781bbSAlex Deucher # define DACB_AUTODETECT_INTERRUPT (1 << 23) 841a59781bbSAlex Deucher # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 842a59781bbSAlex Deucher # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 843a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 844a59781bbSAlex Deucher # define LB_D2_VLINE_INTERRUPT (1 << 2) 845a59781bbSAlex Deucher # define LB_D2_VBLANK_INTERRUPT (1 << 3) 846a59781bbSAlex Deucher # define DC_HPD2_INTERRUPT (1 << 17) 847a59781bbSAlex Deucher # define DC_HPD2_RX_INTERRUPT (1 << 18) 848a59781bbSAlex Deucher # define DISP_TIMER_INTERRUPT (1 << 24) 849a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 850a59781bbSAlex Deucher # define LB_D3_VLINE_INTERRUPT (1 << 2) 851a59781bbSAlex Deucher # define LB_D3_VBLANK_INTERRUPT (1 << 3) 852a59781bbSAlex Deucher # define DC_HPD3_INTERRUPT (1 << 17) 853a59781bbSAlex Deucher # define DC_HPD3_RX_INTERRUPT (1 << 18) 854a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 855a59781bbSAlex Deucher # define LB_D4_VLINE_INTERRUPT (1 << 2) 856a59781bbSAlex Deucher # define LB_D4_VBLANK_INTERRUPT (1 << 3) 857a59781bbSAlex Deucher # define DC_HPD4_INTERRUPT (1 << 17) 858a59781bbSAlex Deucher # define DC_HPD4_RX_INTERRUPT (1 << 18) 859a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 860a59781bbSAlex Deucher # define LB_D5_VLINE_INTERRUPT (1 << 2) 861a59781bbSAlex Deucher # define LB_D5_VBLANK_INTERRUPT (1 << 3) 862a59781bbSAlex Deucher # define DC_HPD5_INTERRUPT (1 << 17) 863a59781bbSAlex Deucher # define DC_HPD5_RX_INTERRUPT (1 << 18) 864a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 865a59781bbSAlex Deucher # define LB_D6_VLINE_INTERRUPT (1 << 2) 866a59781bbSAlex Deucher # define LB_D6_VBLANK_INTERRUPT (1 << 3) 867a59781bbSAlex Deucher # define DC_HPD6_INTERRUPT (1 << 17) 868a59781bbSAlex Deucher # define DC_HPD6_RX_INTERRUPT (1 << 18) 869a59781bbSAlex Deucher #define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780 870a59781bbSAlex Deucher 871a59781bbSAlex Deucher #define DAC_AUTODETECT_INT_CONTROL 0x67c8 872a59781bbSAlex Deucher 873a59781bbSAlex Deucher #define DC_HPD1_INT_STATUS 0x601c 874a59781bbSAlex Deucher #define DC_HPD2_INT_STATUS 0x6028 875a59781bbSAlex Deucher #define DC_HPD3_INT_STATUS 0x6034 876a59781bbSAlex Deucher #define DC_HPD4_INT_STATUS 0x6040 877a59781bbSAlex Deucher #define DC_HPD5_INT_STATUS 0x604c 878a59781bbSAlex Deucher #define DC_HPD6_INT_STATUS 0x6058 879a59781bbSAlex Deucher # define DC_HPDx_INT_STATUS (1 << 0) 880a59781bbSAlex Deucher # define DC_HPDx_SENSE (1 << 1) 881a59781bbSAlex Deucher # define DC_HPDx_SENSE_DELAYED (1 << 4) 882a59781bbSAlex Deucher # define DC_HPDx_RX_INT_STATUS (1 << 8) 883a59781bbSAlex Deucher 884a59781bbSAlex Deucher #define DC_HPD1_INT_CONTROL 0x6020 885a59781bbSAlex Deucher #define DC_HPD2_INT_CONTROL 0x602c 886a59781bbSAlex Deucher #define DC_HPD3_INT_CONTROL 0x6038 887a59781bbSAlex Deucher #define DC_HPD4_INT_CONTROL 0x6044 888a59781bbSAlex Deucher #define DC_HPD5_INT_CONTROL 0x6050 889a59781bbSAlex Deucher #define DC_HPD6_INT_CONTROL 0x605c 890a59781bbSAlex Deucher # define DC_HPDx_INT_ACK (1 << 0) 891a59781bbSAlex Deucher # define DC_HPDx_INT_POLARITY (1 << 8) 892a59781bbSAlex Deucher # define DC_HPDx_INT_EN (1 << 16) 893a59781bbSAlex Deucher # define DC_HPDx_RX_INT_ACK (1 << 20) 894a59781bbSAlex Deucher # define DC_HPDx_RX_INT_EN (1 << 24) 895a59781bbSAlex Deucher 896a59781bbSAlex Deucher #define DC_HPD1_CONTROL 0x6024 897a59781bbSAlex Deucher #define DC_HPD2_CONTROL 0x6030 898a59781bbSAlex Deucher #define DC_HPD3_CONTROL 0x603c 899a59781bbSAlex Deucher #define DC_HPD4_CONTROL 0x6048 900a59781bbSAlex Deucher #define DC_HPD5_CONTROL 0x6054 901a59781bbSAlex Deucher #define DC_HPD6_CONTROL 0x6060 902a59781bbSAlex Deucher # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 903a59781bbSAlex Deucher # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 904a59781bbSAlex Deucher # define DC_HPDx_EN (1 << 28) 905a59781bbSAlex Deucher 906cc8dbbb4SAlex Deucher #define DPG_PIPE_STUTTER_CONTROL 0x6cd4 907cc8dbbb4SAlex Deucher # define STUTTER_ENABLE (1 << 0) 908cc8dbbb4SAlex Deucher 909134b480fSAlex Deucher /* DCE8 FMT blocks */ 910134b480fSAlex Deucher #define FMT_DYNAMIC_EXP_CNTL 0x6fb4 911134b480fSAlex Deucher # define FMT_DYNAMIC_EXP_EN (1 << 0) 912134b480fSAlex Deucher # define FMT_DYNAMIC_EXP_MODE (1 << 4) 913134b480fSAlex Deucher /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */ 914134b480fSAlex Deucher #define FMT_CONTROL 0x6fb8 915134b480fSAlex Deucher # define FMT_PIXEL_ENCODING (1 << 16) 916134b480fSAlex Deucher /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ 917134b480fSAlex Deucher #define FMT_BIT_DEPTH_CONTROL 0x6fc8 918134b480fSAlex Deucher # define FMT_TRUNCATE_EN (1 << 0) 919134b480fSAlex Deucher # define FMT_TRUNCATE_MODE (1 << 1) 920134b480fSAlex Deucher # define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 921134b480fSAlex Deucher # define FMT_SPATIAL_DITHER_EN (1 << 8) 922134b480fSAlex Deucher # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) 923134b480fSAlex Deucher # define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 924134b480fSAlex Deucher # define FMT_FRAME_RANDOM_ENABLE (1 << 13) 925134b480fSAlex Deucher # define FMT_RGB_RANDOM_ENABLE (1 << 14) 926134b480fSAlex Deucher # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) 927134b480fSAlex Deucher # define FMT_TEMPORAL_DITHER_EN (1 << 16) 928134b480fSAlex Deucher # define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ 929134b480fSAlex Deucher # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) 930134b480fSAlex Deucher # define FMT_TEMPORAL_LEVEL (1 << 24) 931134b480fSAlex Deucher # define FMT_TEMPORAL_DITHER_RESET (1 << 25) 932134b480fSAlex Deucher # define FMT_25FRC_SEL(x) ((x) << 26) 933134b480fSAlex Deucher # define FMT_50FRC_SEL(x) ((x) << 28) 934134b480fSAlex Deucher # define FMT_75FRC_SEL(x) ((x) << 30) 935134b480fSAlex Deucher #define FMT_CLAMP_CONTROL 0x6fe4 936134b480fSAlex Deucher # define FMT_CLAMP_DATA_EN (1 << 0) 937134b480fSAlex Deucher # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16) 938134b480fSAlex Deucher # define FMT_CLAMP_6BPC 0 939134b480fSAlex Deucher # define FMT_CLAMP_8BPC 1 940134b480fSAlex Deucher # define FMT_CLAMP_10BPC 2 941134b480fSAlex Deucher 9428cc1a532SAlex Deucher #define GRBM_CNTL 0x8000 9438cc1a532SAlex Deucher #define GRBM_READ_TIMEOUT(x) ((x) << 0) 9448cc1a532SAlex Deucher 9456f2043ceSAlex Deucher #define GRBM_STATUS2 0x8008 9466f2043ceSAlex Deucher #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F 9476f2043ceSAlex Deucher #define ME0PIPE1_CF_RQ_PENDING (1 << 4) 9486f2043ceSAlex Deucher #define ME0PIPE1_PF_RQ_PENDING (1 << 5) 9496f2043ceSAlex Deucher #define ME1PIPE0_RQ_PENDING (1 << 6) 9506f2043ceSAlex Deucher #define ME1PIPE1_RQ_PENDING (1 << 7) 9516f2043ceSAlex Deucher #define ME1PIPE2_RQ_PENDING (1 << 8) 9526f2043ceSAlex Deucher #define ME1PIPE3_RQ_PENDING (1 << 9) 9536f2043ceSAlex Deucher #define ME2PIPE0_RQ_PENDING (1 << 10) 9546f2043ceSAlex Deucher #define ME2PIPE1_RQ_PENDING (1 << 11) 9556f2043ceSAlex Deucher #define ME2PIPE2_RQ_PENDING (1 << 12) 9566f2043ceSAlex Deucher #define ME2PIPE3_RQ_PENDING (1 << 13) 9576f2043ceSAlex Deucher #define RLC_RQ_PENDING (1 << 14) 9586f2043ceSAlex Deucher #define RLC_BUSY (1 << 24) 9596f2043ceSAlex Deucher #define TC_BUSY (1 << 25) 9606f2043ceSAlex Deucher #define CPF_BUSY (1 << 28) 9616f2043ceSAlex Deucher #define CPC_BUSY (1 << 29) 9626f2043ceSAlex Deucher #define CPG_BUSY (1 << 30) 9636f2043ceSAlex Deucher 9646f2043ceSAlex Deucher #define GRBM_STATUS 0x8010 9656f2043ceSAlex Deucher #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F 9666f2043ceSAlex Deucher #define SRBM_RQ_PENDING (1 << 5) 9676f2043ceSAlex Deucher #define ME0PIPE0_CF_RQ_PENDING (1 << 7) 9686f2043ceSAlex Deucher #define ME0PIPE0_PF_RQ_PENDING (1 << 8) 9696f2043ceSAlex Deucher #define GDS_DMA_RQ_PENDING (1 << 9) 9706f2043ceSAlex Deucher #define DB_CLEAN (1 << 12) 9716f2043ceSAlex Deucher #define CB_CLEAN (1 << 13) 9726f2043ceSAlex Deucher #define TA_BUSY (1 << 14) 9736f2043ceSAlex Deucher #define GDS_BUSY (1 << 15) 9746f2043ceSAlex Deucher #define WD_BUSY_NO_DMA (1 << 16) 9756f2043ceSAlex Deucher #define VGT_BUSY (1 << 17) 9766f2043ceSAlex Deucher #define IA_BUSY_NO_DMA (1 << 18) 9776f2043ceSAlex Deucher #define IA_BUSY (1 << 19) 9786f2043ceSAlex Deucher #define SX_BUSY (1 << 20) 9796f2043ceSAlex Deucher #define WD_BUSY (1 << 21) 9806f2043ceSAlex Deucher #define SPI_BUSY (1 << 22) 9816f2043ceSAlex Deucher #define BCI_BUSY (1 << 23) 9826f2043ceSAlex Deucher #define SC_BUSY (1 << 24) 9836f2043ceSAlex Deucher #define PA_BUSY (1 << 25) 9846f2043ceSAlex Deucher #define DB_BUSY (1 << 26) 9856f2043ceSAlex Deucher #define CP_COHERENCY_BUSY (1 << 28) 9866f2043ceSAlex Deucher #define CP_BUSY (1 << 29) 9876f2043ceSAlex Deucher #define CB_BUSY (1 << 30) 9886f2043ceSAlex Deucher #define GUI_ACTIVE (1 << 31) 9896f2043ceSAlex Deucher #define GRBM_STATUS_SE0 0x8014 9906f2043ceSAlex Deucher #define GRBM_STATUS_SE1 0x8018 9916f2043ceSAlex Deucher #define GRBM_STATUS_SE2 0x8038 9926f2043ceSAlex Deucher #define GRBM_STATUS_SE3 0x803C 9936f2043ceSAlex Deucher #define SE_DB_CLEAN (1 << 1) 9946f2043ceSAlex Deucher #define SE_CB_CLEAN (1 << 2) 9956f2043ceSAlex Deucher #define SE_BCI_BUSY (1 << 22) 9966f2043ceSAlex Deucher #define SE_VGT_BUSY (1 << 23) 9976f2043ceSAlex Deucher #define SE_PA_BUSY (1 << 24) 9986f2043ceSAlex Deucher #define SE_TA_BUSY (1 << 25) 9996f2043ceSAlex Deucher #define SE_SX_BUSY (1 << 26) 10006f2043ceSAlex Deucher #define SE_SPI_BUSY (1 << 27) 10016f2043ceSAlex Deucher #define SE_SC_BUSY (1 << 29) 10026f2043ceSAlex Deucher #define SE_DB_BUSY (1 << 30) 10036f2043ceSAlex Deucher #define SE_CB_BUSY (1 << 31) 10046f2043ceSAlex Deucher 10056f2043ceSAlex Deucher #define GRBM_SOFT_RESET 0x8020 10066f2043ceSAlex Deucher #define SOFT_RESET_CP (1 << 0) /* All CP blocks */ 10076f2043ceSAlex Deucher #define SOFT_RESET_RLC (1 << 2) /* RLC */ 10086f2043ceSAlex Deucher #define SOFT_RESET_GFX (1 << 16) /* GFX */ 10096f2043ceSAlex Deucher #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */ 10106f2043ceSAlex Deucher #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */ 10116f2043ceSAlex Deucher #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */ 10126f2043ceSAlex Deucher 1013a59781bbSAlex Deucher #define GRBM_INT_CNTL 0x8060 1014a59781bbSAlex Deucher # define RDERR_INT_ENABLE (1 << 0) 1015a59781bbSAlex Deucher # define GUI_IDLE_INT_ENABLE (1 << 19) 1016a59781bbSAlex Deucher 1017963e81f9SAlex Deucher #define CP_CPC_STATUS 0x8210 1018963e81f9SAlex Deucher #define CP_CPC_BUSY_STAT 0x8214 1019963e81f9SAlex Deucher #define CP_CPC_STALLED_STAT1 0x8218 1020963e81f9SAlex Deucher #define CP_CPF_STATUS 0x821c 1021963e81f9SAlex Deucher #define CP_CPF_BUSY_STAT 0x8220 1022963e81f9SAlex Deucher #define CP_CPF_STALLED_STAT1 0x8224 1023963e81f9SAlex Deucher 10246f2043ceSAlex Deucher #define CP_MEC_CNTL 0x8234 10256f2043ceSAlex Deucher #define MEC_ME2_HALT (1 << 28) 10266f2043ceSAlex Deucher #define MEC_ME1_HALT (1 << 30) 10276f2043ceSAlex Deucher 1028841cf442SAlex Deucher #define CP_MEC_CNTL 0x8234 1029841cf442SAlex Deucher #define MEC_ME2_HALT (1 << 28) 1030841cf442SAlex Deucher #define MEC_ME1_HALT (1 << 30) 1031841cf442SAlex Deucher 1032963e81f9SAlex Deucher #define CP_STALLED_STAT3 0x8670 1033963e81f9SAlex Deucher #define CP_STALLED_STAT1 0x8674 1034963e81f9SAlex Deucher #define CP_STALLED_STAT2 0x8678 1035963e81f9SAlex Deucher 1036963e81f9SAlex Deucher #define CP_STAT 0x8680 1037963e81f9SAlex Deucher 10386f2043ceSAlex Deucher #define CP_ME_CNTL 0x86D8 10396f2043ceSAlex Deucher #define CP_CE_HALT (1 << 24) 10406f2043ceSAlex Deucher #define CP_PFP_HALT (1 << 26) 10416f2043ceSAlex Deucher #define CP_ME_HALT (1 << 28) 10426f2043ceSAlex Deucher 1043841cf442SAlex Deucher #define CP_RB0_RPTR 0x8700 1044841cf442SAlex Deucher #define CP_RB_WPTR_DELAY 0x8704 104522c775ceSAlex Deucher #define CP_RB_WPTR_POLL_CNTL 0x8708 104622c775ceSAlex Deucher #define IDLE_POLL_COUNT(x) ((x) << 16) 104722c775ceSAlex Deucher #define IDLE_POLL_COUNT_MASK (0xffff << 16) 1048841cf442SAlex Deucher 10498cc1a532SAlex Deucher #define CP_MEQ_THRESHOLDS 0x8764 10508cc1a532SAlex Deucher #define MEQ1_START(x) ((x) << 0) 10518cc1a532SAlex Deucher #define MEQ2_START(x) ((x) << 8) 10528cc1a532SAlex Deucher 10538cc1a532SAlex Deucher #define VGT_VTX_VECT_EJECT_REG 0x88B0 10548cc1a532SAlex Deucher 10558cc1a532SAlex Deucher #define VGT_CACHE_INVALIDATION 0x88C4 10568cc1a532SAlex Deucher #define CACHE_INVALIDATION(x) ((x) << 0) 10578cc1a532SAlex Deucher #define VC_ONLY 0 10588cc1a532SAlex Deucher #define TC_ONLY 1 10598cc1a532SAlex Deucher #define VC_AND_TC 2 10608cc1a532SAlex Deucher #define AUTO_INVLD_EN(x) ((x) << 6) 10618cc1a532SAlex Deucher #define NO_AUTO 0 10628cc1a532SAlex Deucher #define ES_AUTO 1 10638cc1a532SAlex Deucher #define GS_AUTO 2 10648cc1a532SAlex Deucher #define ES_AND_GS_AUTO 3 10658cc1a532SAlex Deucher 10668cc1a532SAlex Deucher #define VGT_GS_VERTEX_REUSE 0x88D4 10678cc1a532SAlex Deucher 10688cc1a532SAlex Deucher #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 10698cc1a532SAlex Deucher #define INACTIVE_CUS_MASK 0xFFFF0000 10708cc1a532SAlex Deucher #define INACTIVE_CUS_SHIFT 16 10718cc1a532SAlex Deucher #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 10728cc1a532SAlex Deucher 10738cc1a532SAlex Deucher #define PA_CL_ENHANCE 0x8A14 10748cc1a532SAlex Deucher #define CLIP_VTX_REORDER_ENA (1 << 0) 10758cc1a532SAlex Deucher #define NUM_CLIP_SEQ(x) ((x) << 1) 10768cc1a532SAlex Deucher 10778cc1a532SAlex Deucher #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 10788cc1a532SAlex Deucher #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 10798cc1a532SAlex Deucher #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 10808cc1a532SAlex Deucher 10818cc1a532SAlex Deucher #define PA_SC_FIFO_SIZE 0x8BCC 10828cc1a532SAlex Deucher #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 10838cc1a532SAlex Deucher #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 10848cc1a532SAlex Deucher #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 10858cc1a532SAlex Deucher #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 10868cc1a532SAlex Deucher 10878cc1a532SAlex Deucher #define PA_SC_ENHANCE 0x8BF0 10888cc1a532SAlex Deucher #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) 10898cc1a532SAlex Deucher #define DISABLE_PA_SC_GUIDANCE (1 << 13) 10908cc1a532SAlex Deucher 10918cc1a532SAlex Deucher #define SQ_CONFIG 0x8C00 10928cc1a532SAlex Deucher 10931c49165dSAlex Deucher #define SH_MEM_BASES 0x8C28 10941c49165dSAlex Deucher /* if PTR32, these are the bases for scratch and lds */ 10951c49165dSAlex Deucher #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 10961c49165dSAlex Deucher #define SHARED_BASE(x) ((x) << 16) /* LDS */ 10971c49165dSAlex Deucher #define SH_MEM_APE1_BASE 0x8C2C 10981c49165dSAlex Deucher /* if PTR32, this is the base location of GPUVM */ 10991c49165dSAlex Deucher #define SH_MEM_APE1_LIMIT 0x8C30 11001c49165dSAlex Deucher /* if PTR32, this is the upper limit of GPUVM */ 11011c49165dSAlex Deucher #define SH_MEM_CONFIG 0x8C34 11021c49165dSAlex Deucher #define PTR32 (1 << 0) 11031c49165dSAlex Deucher #define ALIGNMENT_MODE(x) ((x) << 2) 11041c49165dSAlex Deucher #define SH_MEM_ALIGNMENT_MODE_DWORD 0 11051c49165dSAlex Deucher #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1 11061c49165dSAlex Deucher #define SH_MEM_ALIGNMENT_MODE_STRICT 2 11071c49165dSAlex Deucher #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 11081c49165dSAlex Deucher #define DEFAULT_MTYPE(x) ((x) << 4) 11091c49165dSAlex Deucher #define APE1_MTYPE(x) ((x) << 7) 11101c49165dSAlex Deucher 11118cc1a532SAlex Deucher #define SX_DEBUG_1 0x9060 11128cc1a532SAlex Deucher 11138cc1a532SAlex Deucher #define SPI_CONFIG_CNTL 0x9100 11148cc1a532SAlex Deucher 11158cc1a532SAlex Deucher #define SPI_CONFIG_CNTL_1 0x913C 11168cc1a532SAlex Deucher #define VTX_DONE_DELAY(x) ((x) << 0) 11178cc1a532SAlex Deucher #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 11188cc1a532SAlex Deucher 11198cc1a532SAlex Deucher #define TA_CNTL_AUX 0x9508 11208cc1a532SAlex Deucher 11218cc1a532SAlex Deucher #define DB_DEBUG 0x9830 11228cc1a532SAlex Deucher #define DB_DEBUG2 0x9834 11238cc1a532SAlex Deucher #define DB_DEBUG3 0x9838 11248cc1a532SAlex Deucher 11258cc1a532SAlex Deucher #define CC_RB_BACKEND_DISABLE 0x98F4 11268cc1a532SAlex Deucher #define BACKEND_DISABLE(x) ((x) << 16) 11278cc1a532SAlex Deucher #define GB_ADDR_CONFIG 0x98F8 11288cc1a532SAlex Deucher #define NUM_PIPES(x) ((x) << 0) 11298cc1a532SAlex Deucher #define NUM_PIPES_MASK 0x00000007 11308cc1a532SAlex Deucher #define NUM_PIPES_SHIFT 0 11318cc1a532SAlex Deucher #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 11328cc1a532SAlex Deucher #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 11338cc1a532SAlex Deucher #define PIPE_INTERLEAVE_SIZE_SHIFT 4 11348cc1a532SAlex Deucher #define NUM_SHADER_ENGINES(x) ((x) << 12) 11358cc1a532SAlex Deucher #define NUM_SHADER_ENGINES_MASK 0x00003000 11368cc1a532SAlex Deucher #define NUM_SHADER_ENGINES_SHIFT 12 11378cc1a532SAlex Deucher #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 11388cc1a532SAlex Deucher #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 11398cc1a532SAlex Deucher #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 11408cc1a532SAlex Deucher #define ROW_SIZE(x) ((x) << 28) 11418cc1a532SAlex Deucher #define ROW_SIZE_MASK 0x30000000 11428cc1a532SAlex Deucher #define ROW_SIZE_SHIFT 28 11438cc1a532SAlex Deucher 11448cc1a532SAlex Deucher #define GB_TILE_MODE0 0x9910 11458cc1a532SAlex Deucher # define ARRAY_MODE(x) ((x) << 2) 11468cc1a532SAlex Deucher # define ARRAY_LINEAR_GENERAL 0 11478cc1a532SAlex Deucher # define ARRAY_LINEAR_ALIGNED 1 11488cc1a532SAlex Deucher # define ARRAY_1D_TILED_THIN1 2 11498cc1a532SAlex Deucher # define ARRAY_2D_TILED_THIN1 4 11508cc1a532SAlex Deucher # define ARRAY_PRT_TILED_THIN1 5 11518cc1a532SAlex Deucher # define ARRAY_PRT_2D_TILED_THIN1 6 11528cc1a532SAlex Deucher # define PIPE_CONFIG(x) ((x) << 6) 11538cc1a532SAlex Deucher # define ADDR_SURF_P2 0 11548cc1a532SAlex Deucher # define ADDR_SURF_P4_8x16 4 11558cc1a532SAlex Deucher # define ADDR_SURF_P4_16x16 5 11568cc1a532SAlex Deucher # define ADDR_SURF_P4_16x32 6 11578cc1a532SAlex Deucher # define ADDR_SURF_P4_32x32 7 11588cc1a532SAlex Deucher # define ADDR_SURF_P8_16x16_8x16 8 11598cc1a532SAlex Deucher # define ADDR_SURF_P8_16x32_8x16 9 11608cc1a532SAlex Deucher # define ADDR_SURF_P8_32x32_8x16 10 11618cc1a532SAlex Deucher # define ADDR_SURF_P8_16x32_16x16 11 11628cc1a532SAlex Deucher # define ADDR_SURF_P8_32x32_16x16 12 11638cc1a532SAlex Deucher # define ADDR_SURF_P8_32x32_16x32 13 11648cc1a532SAlex Deucher # define ADDR_SURF_P8_32x64_32x32 14 11658cc1a532SAlex Deucher # define TILE_SPLIT(x) ((x) << 11) 11668cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_64B 0 11678cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_128B 1 11688cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_256B 2 11698cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_512B 3 11708cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_1KB 4 11718cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_2KB 5 11728cc1a532SAlex Deucher # define ADDR_SURF_TILE_SPLIT_4KB 6 11738cc1a532SAlex Deucher # define MICRO_TILE_MODE_NEW(x) ((x) << 22) 11748cc1a532SAlex Deucher # define ADDR_SURF_DISPLAY_MICRO_TILING 0 11758cc1a532SAlex Deucher # define ADDR_SURF_THIN_MICRO_TILING 1 11768cc1a532SAlex Deucher # define ADDR_SURF_DEPTH_MICRO_TILING 2 11778cc1a532SAlex Deucher # define ADDR_SURF_ROTATED_MICRO_TILING 3 11788cc1a532SAlex Deucher # define SAMPLE_SPLIT(x) ((x) << 25) 11798cc1a532SAlex Deucher # define ADDR_SURF_SAMPLE_SPLIT_1 0 11808cc1a532SAlex Deucher # define ADDR_SURF_SAMPLE_SPLIT_2 1 11818cc1a532SAlex Deucher # define ADDR_SURF_SAMPLE_SPLIT_4 2 11828cc1a532SAlex Deucher # define ADDR_SURF_SAMPLE_SPLIT_8 3 11838cc1a532SAlex Deucher 11848cc1a532SAlex Deucher #define GB_MACROTILE_MODE0 0x9990 11858cc1a532SAlex Deucher # define BANK_WIDTH(x) ((x) << 0) 11868cc1a532SAlex Deucher # define ADDR_SURF_BANK_WIDTH_1 0 11878cc1a532SAlex Deucher # define ADDR_SURF_BANK_WIDTH_2 1 11888cc1a532SAlex Deucher # define ADDR_SURF_BANK_WIDTH_4 2 11898cc1a532SAlex Deucher # define ADDR_SURF_BANK_WIDTH_8 3 11908cc1a532SAlex Deucher # define BANK_HEIGHT(x) ((x) << 2) 11918cc1a532SAlex Deucher # define ADDR_SURF_BANK_HEIGHT_1 0 11928cc1a532SAlex Deucher # define ADDR_SURF_BANK_HEIGHT_2 1 11938cc1a532SAlex Deucher # define ADDR_SURF_BANK_HEIGHT_4 2 11948cc1a532SAlex Deucher # define ADDR_SURF_BANK_HEIGHT_8 3 11958cc1a532SAlex Deucher # define MACRO_TILE_ASPECT(x) ((x) << 4) 11968cc1a532SAlex Deucher # define ADDR_SURF_MACRO_ASPECT_1 0 11978cc1a532SAlex Deucher # define ADDR_SURF_MACRO_ASPECT_2 1 11988cc1a532SAlex Deucher # define ADDR_SURF_MACRO_ASPECT_4 2 11998cc1a532SAlex Deucher # define ADDR_SURF_MACRO_ASPECT_8 3 12008cc1a532SAlex Deucher # define NUM_BANKS(x) ((x) << 6) 12018cc1a532SAlex Deucher # define ADDR_SURF_2_BANK 0 12028cc1a532SAlex Deucher # define ADDR_SURF_4_BANK 1 12038cc1a532SAlex Deucher # define ADDR_SURF_8_BANK 2 12048cc1a532SAlex Deucher # define ADDR_SURF_16_BANK 3 12058cc1a532SAlex Deucher 12068cc1a532SAlex Deucher #define CB_HW_CONTROL 0x9A10 12078cc1a532SAlex Deucher 12088cc1a532SAlex Deucher #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 12098cc1a532SAlex Deucher #define BACKEND_DISABLE_MASK 0x00FF0000 12108cc1a532SAlex Deucher #define BACKEND_DISABLE_SHIFT 16 12118cc1a532SAlex Deucher 12128cc1a532SAlex Deucher #define TCP_CHAN_STEER_LO 0xac0c 12138cc1a532SAlex Deucher #define TCP_CHAN_STEER_HI 0xac10 12148cc1a532SAlex Deucher 12151c49165dSAlex Deucher #define TC_CFG_L1_LOAD_POLICY0 0xAC68 12161c49165dSAlex Deucher #define TC_CFG_L1_LOAD_POLICY1 0xAC6C 12171c49165dSAlex Deucher #define TC_CFG_L1_STORE_POLICY 0xAC70 12181c49165dSAlex Deucher #define TC_CFG_L2_LOAD_POLICY0 0xAC74 12191c49165dSAlex Deucher #define TC_CFG_L2_LOAD_POLICY1 0xAC78 12201c49165dSAlex Deucher #define TC_CFG_L2_STORE_POLICY0 0xAC7C 12211c49165dSAlex Deucher #define TC_CFG_L2_STORE_POLICY1 0xAC80 12221c49165dSAlex Deucher #define TC_CFG_L2_ATOMIC_POLICY 0xAC84 12231c49165dSAlex Deucher #define TC_CFG_L1_VOLATILE 0xAC88 12241c49165dSAlex Deucher #define TC_CFG_L2_VOLATILE 0xAC8C 12251c49165dSAlex Deucher 1226841cf442SAlex Deucher #define CP_RB0_BASE 0xC100 1227841cf442SAlex Deucher #define CP_RB0_CNTL 0xC104 1228841cf442SAlex Deucher #define RB_BUFSZ(x) ((x) << 0) 1229841cf442SAlex Deucher #define RB_BLKSZ(x) ((x) << 8) 1230841cf442SAlex Deucher #define BUF_SWAP_32BIT (2 << 16) 1231841cf442SAlex Deucher #define RB_NO_UPDATE (1 << 27) 1232841cf442SAlex Deucher #define RB_RPTR_WR_ENA (1 << 31) 1233841cf442SAlex Deucher 1234841cf442SAlex Deucher #define CP_RB0_RPTR_ADDR 0xC10C 1235841cf442SAlex Deucher #define RB_RPTR_SWAP_32BIT (2 << 0) 1236841cf442SAlex Deucher #define CP_RB0_RPTR_ADDR_HI 0xC110 1237841cf442SAlex Deucher #define CP_RB0_WPTR 0xC114 1238841cf442SAlex Deucher 1239841cf442SAlex Deucher #define CP_DEVICE_ID 0xC12C 1240841cf442SAlex Deucher #define CP_ENDIAN_SWAP 0xC140 1241841cf442SAlex Deucher #define CP_RB_VMID 0xC144 1242841cf442SAlex Deucher 1243841cf442SAlex Deucher #define CP_PFP_UCODE_ADDR 0xC150 1244841cf442SAlex Deucher #define CP_PFP_UCODE_DATA 0xC154 1245841cf442SAlex Deucher #define CP_ME_RAM_RADDR 0xC158 1246841cf442SAlex Deucher #define CP_ME_RAM_WADDR 0xC15C 1247841cf442SAlex Deucher #define CP_ME_RAM_DATA 0xC160 1248841cf442SAlex Deucher 1249841cf442SAlex Deucher #define CP_CE_UCODE_ADDR 0xC168 1250841cf442SAlex Deucher #define CP_CE_UCODE_DATA 0xC16C 1251841cf442SAlex Deucher #define CP_MEC_ME1_UCODE_ADDR 0xC170 1252841cf442SAlex Deucher #define CP_MEC_ME1_UCODE_DATA 0xC174 1253841cf442SAlex Deucher #define CP_MEC_ME2_UCODE_ADDR 0xC178 1254841cf442SAlex Deucher #define CP_MEC_ME2_UCODE_DATA 0xC17C 1255841cf442SAlex Deucher 1256f6796caeSAlex Deucher #define CP_INT_CNTL_RING0 0xC1A8 1257f6796caeSAlex Deucher # define CNTX_BUSY_INT_ENABLE (1 << 19) 1258f6796caeSAlex Deucher # define CNTX_EMPTY_INT_ENABLE (1 << 20) 1259f6796caeSAlex Deucher # define PRIV_INSTR_INT_ENABLE (1 << 22) 1260f6796caeSAlex Deucher # define PRIV_REG_INT_ENABLE (1 << 23) 1261f6796caeSAlex Deucher # define TIME_STAMP_INT_ENABLE (1 << 26) 1262f6796caeSAlex Deucher # define CP_RINGID2_INT_ENABLE (1 << 29) 1263f6796caeSAlex Deucher # define CP_RINGID1_INT_ENABLE (1 << 30) 1264f6796caeSAlex Deucher # define CP_RINGID0_INT_ENABLE (1 << 31) 1265f6796caeSAlex Deucher 1266a59781bbSAlex Deucher #define CP_INT_STATUS_RING0 0xC1B4 1267a59781bbSAlex Deucher # define PRIV_INSTR_INT_STAT (1 << 22) 1268a59781bbSAlex Deucher # define PRIV_REG_INT_STAT (1 << 23) 1269a59781bbSAlex Deucher # define TIME_STAMP_INT_STAT (1 << 26) 1270a59781bbSAlex Deucher # define CP_RINGID2_INT_STAT (1 << 29) 1271a59781bbSAlex Deucher # define CP_RINGID1_INT_STAT (1 << 30) 1272a59781bbSAlex Deucher # define CP_RINGID0_INT_STAT (1 << 31) 1273a59781bbSAlex Deucher 127422c775ceSAlex Deucher #define CP_MEM_SLP_CNTL 0xC1E4 127522c775ceSAlex Deucher # define CP_MEM_LS_EN (1 << 0) 127622c775ceSAlex Deucher 1277963e81f9SAlex Deucher #define CP_CPF_DEBUG 0xC200 1278963e81f9SAlex Deucher 1279963e81f9SAlex Deucher #define CP_PQ_WPTR_POLL_CNTL 0xC20C 1280963e81f9SAlex Deucher #define WPTR_POLL_EN (1 << 31) 1281963e81f9SAlex Deucher 1282a59781bbSAlex Deucher #define CP_ME1_PIPE0_INT_CNTL 0xC214 1283a59781bbSAlex Deucher #define CP_ME1_PIPE1_INT_CNTL 0xC218 1284a59781bbSAlex Deucher #define CP_ME1_PIPE2_INT_CNTL 0xC21C 1285a59781bbSAlex Deucher #define CP_ME1_PIPE3_INT_CNTL 0xC220 1286a59781bbSAlex Deucher #define CP_ME2_PIPE0_INT_CNTL 0xC224 1287a59781bbSAlex Deucher #define CP_ME2_PIPE1_INT_CNTL 0xC228 1288a59781bbSAlex Deucher #define CP_ME2_PIPE2_INT_CNTL 0xC22C 1289a59781bbSAlex Deucher #define CP_ME2_PIPE3_INT_CNTL 0xC230 1290a59781bbSAlex Deucher # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13) 1291a59781bbSAlex Deucher # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17) 1292a59781bbSAlex Deucher # define PRIV_REG_INT_ENABLE (1 << 23) 1293a59781bbSAlex Deucher # define TIME_STAMP_INT_ENABLE (1 << 26) 1294a59781bbSAlex Deucher # define GENERIC2_INT_ENABLE (1 << 29) 1295a59781bbSAlex Deucher # define GENERIC1_INT_ENABLE (1 << 30) 1296a59781bbSAlex Deucher # define GENERIC0_INT_ENABLE (1 << 31) 1297a59781bbSAlex Deucher #define CP_ME1_PIPE0_INT_STATUS 0xC214 1298a59781bbSAlex Deucher #define CP_ME1_PIPE1_INT_STATUS 0xC218 1299a59781bbSAlex Deucher #define CP_ME1_PIPE2_INT_STATUS 0xC21C 1300a59781bbSAlex Deucher #define CP_ME1_PIPE3_INT_STATUS 0xC220 1301a59781bbSAlex Deucher #define CP_ME2_PIPE0_INT_STATUS 0xC224 1302a59781bbSAlex Deucher #define CP_ME2_PIPE1_INT_STATUS 0xC228 1303a59781bbSAlex Deucher #define CP_ME2_PIPE2_INT_STATUS 0xC22C 1304a59781bbSAlex Deucher #define CP_ME2_PIPE3_INT_STATUS 0xC230 1305a59781bbSAlex Deucher # define DEQUEUE_REQUEST_INT_STATUS (1 << 13) 1306a59781bbSAlex Deucher # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17) 1307a59781bbSAlex Deucher # define PRIV_REG_INT_STATUS (1 << 23) 1308a59781bbSAlex Deucher # define TIME_STAMP_INT_STATUS (1 << 26) 1309a59781bbSAlex Deucher # define GENERIC2_INT_STATUS (1 << 29) 1310a59781bbSAlex Deucher # define GENERIC1_INT_STATUS (1 << 30) 1311a59781bbSAlex Deucher # define GENERIC0_INT_STATUS (1 << 31) 1312a59781bbSAlex Deucher 1313841cf442SAlex Deucher #define CP_MAX_CONTEXT 0xC2B8 1314841cf442SAlex Deucher 1315841cf442SAlex Deucher #define CP_RB0_BASE_HI 0xC2C4 1316841cf442SAlex Deucher 1317f6796caeSAlex Deucher #define RLC_CNTL 0xC300 1318f6796caeSAlex Deucher # define RLC_ENABLE (1 << 0) 1319f6796caeSAlex Deucher 1320f6796caeSAlex Deucher #define RLC_MC_CNTL 0xC30C 1321f6796caeSAlex Deucher 132222c775ceSAlex Deucher #define RLC_MEM_SLP_CNTL 0xC318 132322c775ceSAlex Deucher # define RLC_MEM_LS_EN (1 << 0) 132422c775ceSAlex Deucher 1325f6796caeSAlex Deucher #define RLC_LB_CNTR_MAX 0xC348 1326f6796caeSAlex Deucher 1327f6796caeSAlex Deucher #define RLC_LB_CNTL 0xC364 1328866d83deSAlex Deucher # define LOAD_BALANCE_ENABLE (1 << 0) 1329f6796caeSAlex Deucher 1330f6796caeSAlex Deucher #define RLC_LB_CNTR_INIT 0xC36C 1331f6796caeSAlex Deucher 1332f6796caeSAlex Deucher #define RLC_SAVE_AND_RESTORE_BASE 0xC374 133322c775ceSAlex Deucher #define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */ 133422c775ceSAlex Deucher #define RLC_CP_TABLE_RESTORE 0xC378 /* APU */ 133522c775ceSAlex Deucher #define RLC_PG_DELAY_2 0xC37C 1336f6796caeSAlex Deucher 1337f6796caeSAlex Deucher #define RLC_GPM_UCODE_ADDR 0xC388 1338f6796caeSAlex Deucher #define RLC_GPM_UCODE_DATA 0xC38C 133944fa346fSAlex Deucher #define RLC_GPU_CLOCK_COUNT_LSB 0xC390 134044fa346fSAlex Deucher #define RLC_GPU_CLOCK_COUNT_MSB 0xC394 134144fa346fSAlex Deucher #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398 1342f6796caeSAlex Deucher #define RLC_UCODE_CNTL 0xC39C 1343f6796caeSAlex Deucher 134422c775ceSAlex Deucher #define RLC_GPM_STAT 0xC400 134522c775ceSAlex Deucher # define RLC_GPM_BUSY (1 << 0) 1346a412fce0SAlex Deucher # define GFX_POWER_STATUS (1 << 1) 1347a412fce0SAlex Deucher # define GFX_CLOCK_STATUS (1 << 2) 134822c775ceSAlex Deucher 134922c775ceSAlex Deucher #define RLC_PG_CNTL 0xC40C 135022c775ceSAlex Deucher # define GFX_PG_ENABLE (1 << 0) 135122c775ceSAlex Deucher # define GFX_PG_SRC (1 << 1) 135222c775ceSAlex Deucher # define DYN_PER_CU_PG_ENABLE (1 << 2) 135322c775ceSAlex Deucher # define STATIC_PER_CU_PG_ENABLE (1 << 3) 135422c775ceSAlex Deucher # define DISABLE_GDS_PG (1 << 13) 135522c775ceSAlex Deucher # define DISABLE_CP_PG (1 << 15) 135622c775ceSAlex Deucher # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17) 135722c775ceSAlex Deucher # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18) 135822c775ceSAlex Deucher 135922c775ceSAlex Deucher #define RLC_CGTT_MGCG_OVERRIDE 0xC420 1360f6796caeSAlex Deucher #define RLC_CGCG_CGLS_CTRL 0xC424 136122c775ceSAlex Deucher # define CGCG_EN (1 << 0) 136222c775ceSAlex Deucher # define CGLS_EN (1 << 1) 136322c775ceSAlex Deucher 136422c775ceSAlex Deucher #define RLC_PG_DELAY 0xC434 1365f6796caeSAlex Deucher 1366f6796caeSAlex Deucher #define RLC_LB_INIT_CU_MASK 0xC43C 1367f6796caeSAlex Deucher 1368f6796caeSAlex Deucher #define RLC_LB_PARAMS 0xC444 1369f6796caeSAlex Deucher 137022c775ceSAlex Deucher #define RLC_PG_AO_CU_MASK 0xC44C 137122c775ceSAlex Deucher 137222c775ceSAlex Deucher #define RLC_MAX_PG_CU 0xC450 137322c775ceSAlex Deucher # define MAX_PU_CU(x) ((x) << 0) 137422c775ceSAlex Deucher # define MAX_PU_CU_MASK (0xff << 0) 137522c775ceSAlex Deucher #define RLC_AUTO_PG_CTRL 0xC454 137622c775ceSAlex Deucher # define AUTO_PG_EN (1 << 0) 137722c775ceSAlex Deucher # define GRBM_REG_SGIT(x) ((x) << 3) 137822c775ceSAlex Deucher # define GRBM_REG_SGIT_MASK (0xffff << 3) 137922c775ceSAlex Deucher 138022c775ceSAlex Deucher #define RLC_SERDES_WR_CU_MASTER_MASK 0xC474 138122c775ceSAlex Deucher #define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478 138222c775ceSAlex Deucher #define RLC_SERDES_WR_CTRL 0xC47C 138322c775ceSAlex Deucher #define BPM_ADDR(x) ((x) << 0) 138422c775ceSAlex Deucher #define BPM_ADDR_MASK (0xff << 0) 138522c775ceSAlex Deucher #define CGLS_ENABLE (1 << 16) 138622c775ceSAlex Deucher #define CGCG_OVERRIDE_0 (1 << 20) 138722c775ceSAlex Deucher #define MGCG_OVERRIDE_0 (1 << 22) 138822c775ceSAlex Deucher #define MGCG_OVERRIDE_1 (1 << 23) 138922c775ceSAlex Deucher 1390f6796caeSAlex Deucher #define RLC_SERDES_CU_MASTER_BUSY 0xC484 1391f6796caeSAlex Deucher #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 1392f6796caeSAlex Deucher # define SE_MASTER_BUSY_MASK 0x0000ffff 1393f6796caeSAlex Deucher # define GC_MASTER_BUSY (1 << 16) 1394f6796caeSAlex Deucher # define TC0_MASTER_BUSY (1 << 17) 1395f6796caeSAlex Deucher # define TC1_MASTER_BUSY (1 << 18) 1396f6796caeSAlex Deucher 1397f6796caeSAlex Deucher #define RLC_GPM_SCRATCH_ADDR 0xC4B0 1398f6796caeSAlex Deucher #define RLC_GPM_SCRATCH_DATA 0xC4B4 1399f6796caeSAlex Deucher 1400a412fce0SAlex Deucher #define RLC_GPR_REG2 0xC4E8 1401a412fce0SAlex Deucher #define REQ 0x00000001 1402a412fce0SAlex Deucher #define MESSAGE(x) ((x) << 1) 1403a412fce0SAlex Deucher #define MESSAGE_MASK 0x0000001e 1404a412fce0SAlex Deucher #define MSG_ENTER_RLC_SAFE_MODE 1 1405a412fce0SAlex Deucher #define MSG_EXIT_RLC_SAFE_MODE 0 1406a412fce0SAlex Deucher 1407963e81f9SAlex Deucher #define CP_HPD_EOP_BASE_ADDR 0xC904 1408963e81f9SAlex Deucher #define CP_HPD_EOP_BASE_ADDR_HI 0xC908 1409963e81f9SAlex Deucher #define CP_HPD_EOP_VMID 0xC90C 1410963e81f9SAlex Deucher #define CP_HPD_EOP_CONTROL 0xC910 1411963e81f9SAlex Deucher #define EOP_SIZE(x) ((x) << 0) 1412963e81f9SAlex Deucher #define EOP_SIZE_MASK (0x3f << 0) 1413963e81f9SAlex Deucher #define CP_MQD_BASE_ADDR 0xC914 1414963e81f9SAlex Deucher #define CP_MQD_BASE_ADDR_HI 0xC918 1415963e81f9SAlex Deucher #define CP_HQD_ACTIVE 0xC91C 1416963e81f9SAlex Deucher #define CP_HQD_VMID 0xC920 1417963e81f9SAlex Deucher 1418963e81f9SAlex Deucher #define CP_HQD_PQ_BASE 0xC934 1419963e81f9SAlex Deucher #define CP_HQD_PQ_BASE_HI 0xC938 1420963e81f9SAlex Deucher #define CP_HQD_PQ_RPTR 0xC93C 1421963e81f9SAlex Deucher #define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940 1422963e81f9SAlex Deucher #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944 1423963e81f9SAlex Deucher #define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948 1424963e81f9SAlex Deucher #define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C 1425963e81f9SAlex Deucher #define CP_HQD_PQ_DOORBELL_CONTROL 0xC950 1426963e81f9SAlex Deucher #define DOORBELL_OFFSET(x) ((x) << 2) 1427963e81f9SAlex Deucher #define DOORBELL_OFFSET_MASK (0x1fffff << 2) 1428963e81f9SAlex Deucher #define DOORBELL_SOURCE (1 << 28) 1429963e81f9SAlex Deucher #define DOORBELL_SCHD_HIT (1 << 29) 1430963e81f9SAlex Deucher #define DOORBELL_EN (1 << 30) 1431963e81f9SAlex Deucher #define DOORBELL_HIT (1 << 31) 1432963e81f9SAlex Deucher #define CP_HQD_PQ_WPTR 0xC954 1433963e81f9SAlex Deucher #define CP_HQD_PQ_CONTROL 0xC958 1434963e81f9SAlex Deucher #define QUEUE_SIZE(x) ((x) << 0) 1435963e81f9SAlex Deucher #define QUEUE_SIZE_MASK (0x3f << 0) 1436963e81f9SAlex Deucher #define RPTR_BLOCK_SIZE(x) ((x) << 8) 1437963e81f9SAlex Deucher #define RPTR_BLOCK_SIZE_MASK (0x3f << 8) 1438963e81f9SAlex Deucher #define PQ_VOLATILE (1 << 26) 1439963e81f9SAlex Deucher #define NO_UPDATE_RPTR (1 << 27) 1440963e81f9SAlex Deucher #define UNORD_DISPATCH (1 << 28) 1441963e81f9SAlex Deucher #define ROQ_PQ_IB_FLIP (1 << 29) 1442963e81f9SAlex Deucher #define PRIV_STATE (1 << 30) 1443963e81f9SAlex Deucher #define KMD_QUEUE (1 << 31) 1444963e81f9SAlex Deucher 1445963e81f9SAlex Deucher #define CP_HQD_DEQUEUE_REQUEST 0xC974 1446963e81f9SAlex Deucher 1447963e81f9SAlex Deucher #define CP_MQD_CONTROL 0xC99C 1448963e81f9SAlex Deucher #define MQD_VMID(x) ((x) << 0) 1449963e81f9SAlex Deucher #define MQD_VMID_MASK (0xf << 0) 1450963e81f9SAlex Deucher 145122c775ceSAlex Deucher #define DB_RENDER_CONTROL 0x28000 145222c775ceSAlex Deucher 14538cc1a532SAlex Deucher #define PA_SC_RASTER_CONFIG 0x28350 14548cc1a532SAlex Deucher # define RASTER_CONFIG_RB_MAP_0 0 14558cc1a532SAlex Deucher # define RASTER_CONFIG_RB_MAP_1 1 14568cc1a532SAlex Deucher # define RASTER_CONFIG_RB_MAP_2 2 14578cc1a532SAlex Deucher # define RASTER_CONFIG_RB_MAP_3 3 14588cc1a532SAlex Deucher 14592cae3bc3SAlex Deucher #define VGT_EVENT_INITIATOR 0x28a90 14602cae3bc3SAlex Deucher # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 14612cae3bc3SAlex Deucher # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 14622cae3bc3SAlex Deucher # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 14632cae3bc3SAlex Deucher # define CACHE_FLUSH_TS (4 << 0) 14642cae3bc3SAlex Deucher # define CACHE_FLUSH (6 << 0) 14652cae3bc3SAlex Deucher # define CS_PARTIAL_FLUSH (7 << 0) 14662cae3bc3SAlex Deucher # define VGT_STREAMOUT_RESET (10 << 0) 14672cae3bc3SAlex Deucher # define END_OF_PIPE_INCR_DE (11 << 0) 14682cae3bc3SAlex Deucher # define END_OF_PIPE_IB_END (12 << 0) 14692cae3bc3SAlex Deucher # define RST_PIX_CNT (13 << 0) 14702cae3bc3SAlex Deucher # define VS_PARTIAL_FLUSH (15 << 0) 14712cae3bc3SAlex Deucher # define PS_PARTIAL_FLUSH (16 << 0) 14722cae3bc3SAlex Deucher # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 14732cae3bc3SAlex Deucher # define ZPASS_DONE (21 << 0) 14742cae3bc3SAlex Deucher # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 14752cae3bc3SAlex Deucher # define PERFCOUNTER_START (23 << 0) 14762cae3bc3SAlex Deucher # define PERFCOUNTER_STOP (24 << 0) 14772cae3bc3SAlex Deucher # define PIPELINESTAT_START (25 << 0) 14782cae3bc3SAlex Deucher # define PIPELINESTAT_STOP (26 << 0) 14792cae3bc3SAlex Deucher # define PERFCOUNTER_SAMPLE (27 << 0) 14802cae3bc3SAlex Deucher # define SAMPLE_PIPELINESTAT (30 << 0) 14812cae3bc3SAlex Deucher # define SO_VGT_STREAMOUT_FLUSH (31 << 0) 14822cae3bc3SAlex Deucher # define SAMPLE_STREAMOUTSTATS (32 << 0) 14832cae3bc3SAlex Deucher # define RESET_VTX_CNT (33 << 0) 14842cae3bc3SAlex Deucher # define VGT_FLUSH (36 << 0) 14852cae3bc3SAlex Deucher # define BOTTOM_OF_PIPE_TS (40 << 0) 14862cae3bc3SAlex Deucher # define DB_CACHE_FLUSH_AND_INV (42 << 0) 14872cae3bc3SAlex Deucher # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 14882cae3bc3SAlex Deucher # define FLUSH_AND_INV_DB_META (44 << 0) 14892cae3bc3SAlex Deucher # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 14902cae3bc3SAlex Deucher # define FLUSH_AND_INV_CB_META (46 << 0) 14912cae3bc3SAlex Deucher # define CS_DONE (47 << 0) 14922cae3bc3SAlex Deucher # define PS_DONE (48 << 0) 14932cae3bc3SAlex Deucher # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 14942cae3bc3SAlex Deucher # define THREAD_TRACE_START (51 << 0) 14952cae3bc3SAlex Deucher # define THREAD_TRACE_STOP (52 << 0) 14962cae3bc3SAlex Deucher # define THREAD_TRACE_FLUSH (54 << 0) 14972cae3bc3SAlex Deucher # define THREAD_TRACE_FINISH (55 << 0) 14982cae3bc3SAlex Deucher # define PIXEL_PIPE_STAT_CONTROL (56 << 0) 14992cae3bc3SAlex Deucher # define PIXEL_PIPE_STAT_DUMP (57 << 0) 15002cae3bc3SAlex Deucher # define PIXEL_PIPE_STAT_RESET (58 << 0) 15012cae3bc3SAlex Deucher 1502841cf442SAlex Deucher #define SCRATCH_REG0 0x30100 1503841cf442SAlex Deucher #define SCRATCH_REG1 0x30104 1504841cf442SAlex Deucher #define SCRATCH_REG2 0x30108 1505841cf442SAlex Deucher #define SCRATCH_REG3 0x3010C 1506841cf442SAlex Deucher #define SCRATCH_REG4 0x30110 1507841cf442SAlex Deucher #define SCRATCH_REG5 0x30114 1508841cf442SAlex Deucher #define SCRATCH_REG6 0x30118 1509841cf442SAlex Deucher #define SCRATCH_REG7 0x3011C 1510841cf442SAlex Deucher 1511841cf442SAlex Deucher #define SCRATCH_UMSK 0x30140 1512841cf442SAlex Deucher #define SCRATCH_ADDR 0x30144 1513841cf442SAlex Deucher 1514841cf442SAlex Deucher #define CP_SEM_WAIT_TIMER 0x301BC 1515841cf442SAlex Deucher 1516841cf442SAlex Deucher #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8 1517841cf442SAlex Deucher 15182cae3bc3SAlex Deucher #define CP_WAIT_REG_MEM_TIMEOUT 0x301D0 15192cae3bc3SAlex Deucher 15208cc1a532SAlex Deucher #define GRBM_GFX_INDEX 0x30800 15218cc1a532SAlex Deucher #define INSTANCE_INDEX(x) ((x) << 0) 15228cc1a532SAlex Deucher #define SH_INDEX(x) ((x) << 8) 15238cc1a532SAlex Deucher #define SE_INDEX(x) ((x) << 16) 15248cc1a532SAlex Deucher #define SH_BROADCAST_WRITES (1 << 29) 15258cc1a532SAlex Deucher #define INSTANCE_BROADCAST_WRITES (1 << 30) 15268cc1a532SAlex Deucher #define SE_BROADCAST_WRITES (1 << 31) 15278cc1a532SAlex Deucher 15288cc1a532SAlex Deucher #define VGT_ESGS_RING_SIZE 0x30900 15298cc1a532SAlex Deucher #define VGT_GSVS_RING_SIZE 0x30904 15308cc1a532SAlex Deucher #define VGT_PRIMITIVE_TYPE 0x30908 15318cc1a532SAlex Deucher #define VGT_INDEX_TYPE 0x3090C 15328cc1a532SAlex Deucher 15338cc1a532SAlex Deucher #define VGT_NUM_INDICES 0x30930 15348cc1a532SAlex Deucher #define VGT_NUM_INSTANCES 0x30934 15358cc1a532SAlex Deucher #define VGT_TF_RING_SIZE 0x30938 15368cc1a532SAlex Deucher #define VGT_HS_OFFCHIP_PARAM 0x3093C 15378cc1a532SAlex Deucher #define VGT_TF_MEMORY_BASE 0x30940 15388cc1a532SAlex Deucher 15398cc1a532SAlex Deucher #define PA_SU_LINE_STIPPLE_VALUE 0x30a00 15408cc1a532SAlex Deucher #define PA_SC_LINE_STIPPLE_STATE 0x30a04 15418cc1a532SAlex Deucher 15428cc1a532SAlex Deucher #define SQC_CACHES 0x30d20 15438cc1a532SAlex Deucher 15448cc1a532SAlex Deucher #define CP_PERFMON_CNTL 0x36020 15458cc1a532SAlex Deucher 154622c775ceSAlex Deucher #define CGTS_SM_CTRL_REG 0x3c000 154722c775ceSAlex Deucher #define SM_MODE(x) ((x) << 17) 154822c775ceSAlex Deucher #define SM_MODE_MASK (0x7 << 17) 154922c775ceSAlex Deucher #define SM_MODE_ENABLE (1 << 20) 155022c775ceSAlex Deucher #define CGTS_OVERRIDE (1 << 21) 155122c775ceSAlex Deucher #define CGTS_LS_OVERRIDE (1 << 22) 155222c775ceSAlex Deucher #define ON_MONITOR_ADD_EN (1 << 23) 155322c775ceSAlex Deucher #define ON_MONITOR_ADD(x) ((x) << 24) 155422c775ceSAlex Deucher #define ON_MONITOR_ADD_MASK (0xff << 24) 155522c775ceSAlex Deucher 15568cc1a532SAlex Deucher #define CGTS_TCC_DISABLE 0x3c00c 15578cc1a532SAlex Deucher #define CGTS_USER_TCC_DISABLE 0x3c010 15588cc1a532SAlex Deucher #define TCC_DISABLE_MASK 0xFFFF0000 15598cc1a532SAlex Deucher #define TCC_DISABLE_SHIFT 16 15608cc1a532SAlex Deucher 1561f6796caeSAlex Deucher #define CB_CGTT_SCLK_CTRL 0x3c2a0 1562f6796caeSAlex Deucher 1563841cf442SAlex Deucher /* 1564841cf442SAlex Deucher * PM4 1565841cf442SAlex Deucher */ 1566841cf442SAlex Deucher #define PACKET_TYPE0 0 1567841cf442SAlex Deucher #define PACKET_TYPE1 1 1568841cf442SAlex Deucher #define PACKET_TYPE2 2 1569841cf442SAlex Deucher #define PACKET_TYPE3 3 1570841cf442SAlex Deucher 1571841cf442SAlex Deucher #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 1572841cf442SAlex Deucher #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 1573841cf442SAlex Deucher #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 1574841cf442SAlex Deucher #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 1575841cf442SAlex Deucher #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 1576841cf442SAlex Deucher (((reg) >> 2) & 0xFFFF) | \ 1577841cf442SAlex Deucher ((n) & 0x3FFF) << 16) 1578841cf442SAlex Deucher #define CP_PACKET2 0x80000000 1579841cf442SAlex Deucher #define PACKET2_PAD_SHIFT 0 1580841cf442SAlex Deucher #define PACKET2_PAD_MASK (0x3fffffff << 0) 1581841cf442SAlex Deucher 1582841cf442SAlex Deucher #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1583841cf442SAlex Deucher 1584841cf442SAlex Deucher #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 1585841cf442SAlex Deucher (((op) & 0xFF) << 8) | \ 1586841cf442SAlex Deucher ((n) & 0x3FFF) << 16) 1587841cf442SAlex Deucher 1588841cf442SAlex Deucher #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 1589841cf442SAlex Deucher 1590841cf442SAlex Deucher /* Packet 3 types */ 1591841cf442SAlex Deucher #define PACKET3_NOP 0x10 1592841cf442SAlex Deucher #define PACKET3_SET_BASE 0x11 1593841cf442SAlex Deucher #define PACKET3_BASE_INDEX(x) ((x) << 0) 1594841cf442SAlex Deucher #define CE_PARTITION_BASE 3 1595841cf442SAlex Deucher #define PACKET3_CLEAR_STATE 0x12 1596841cf442SAlex Deucher #define PACKET3_INDEX_BUFFER_SIZE 0x13 1597841cf442SAlex Deucher #define PACKET3_DISPATCH_DIRECT 0x15 1598841cf442SAlex Deucher #define PACKET3_DISPATCH_INDIRECT 0x16 1599841cf442SAlex Deucher #define PACKET3_ATOMIC_GDS 0x1D 1600841cf442SAlex Deucher #define PACKET3_ATOMIC_MEM 0x1E 1601841cf442SAlex Deucher #define PACKET3_OCCLUSION_QUERY 0x1F 1602841cf442SAlex Deucher #define PACKET3_SET_PREDICATION 0x20 1603841cf442SAlex Deucher #define PACKET3_REG_RMW 0x21 1604841cf442SAlex Deucher #define PACKET3_COND_EXEC 0x22 1605841cf442SAlex Deucher #define PACKET3_PRED_EXEC 0x23 1606841cf442SAlex Deucher #define PACKET3_DRAW_INDIRECT 0x24 1607841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1608841cf442SAlex Deucher #define PACKET3_INDEX_BASE 0x26 1609841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_2 0x27 1610841cf442SAlex Deucher #define PACKET3_CONTEXT_CONTROL 0x28 1611841cf442SAlex Deucher #define PACKET3_INDEX_TYPE 0x2A 1612841cf442SAlex Deucher #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 1613841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_AUTO 0x2D 1614841cf442SAlex Deucher #define PACKET3_NUM_INSTANCES 0x2F 1615841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1616841cf442SAlex Deucher #define PACKET3_INDIRECT_BUFFER_CONST 0x33 1617841cf442SAlex Deucher #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1618841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1619841cf442SAlex Deucher #define PACKET3_DRAW_PREAMBLE 0x36 1620841cf442SAlex Deucher #define PACKET3_WRITE_DATA 0x37 16212cae3bc3SAlex Deucher #define WRITE_DATA_DST_SEL(x) ((x) << 8) 16222cae3bc3SAlex Deucher /* 0 - register 16232cae3bc3SAlex Deucher * 1 - memory (sync - via GRBM) 16242cae3bc3SAlex Deucher * 2 - gl2 16252cae3bc3SAlex Deucher * 3 - gds 16262cae3bc3SAlex Deucher * 4 - reserved 16272cae3bc3SAlex Deucher * 5 - memory (async - direct) 16282cae3bc3SAlex Deucher */ 16292cae3bc3SAlex Deucher #define WR_ONE_ADDR (1 << 16) 16302cae3bc3SAlex Deucher #define WR_CONFIRM (1 << 20) 16312cae3bc3SAlex Deucher #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 16322cae3bc3SAlex Deucher /* 0 - LRU 16332cae3bc3SAlex Deucher * 1 - Stream 16342cae3bc3SAlex Deucher */ 16352cae3bc3SAlex Deucher #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 16362cae3bc3SAlex Deucher /* 0 - me 16372cae3bc3SAlex Deucher * 1 - pfp 16382cae3bc3SAlex Deucher * 2 - ce 16392cae3bc3SAlex Deucher */ 1640841cf442SAlex Deucher #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 1641841cf442SAlex Deucher #define PACKET3_MEM_SEMAPHORE 0x39 16422cae3bc3SAlex Deucher # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 16432cae3bc3SAlex Deucher # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 16442cae3bc3SAlex Deucher # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 16452cae3bc3SAlex Deucher # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 16462cae3bc3SAlex Deucher # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 1647841cf442SAlex Deucher #define PACKET3_COPY_DW 0x3B 1648841cf442SAlex Deucher #define PACKET3_WAIT_REG_MEM 0x3C 16492cae3bc3SAlex Deucher #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 16502cae3bc3SAlex Deucher /* 0 - always 16512cae3bc3SAlex Deucher * 1 - < 16522cae3bc3SAlex Deucher * 2 - <= 16532cae3bc3SAlex Deucher * 3 - == 16542cae3bc3SAlex Deucher * 4 - != 16552cae3bc3SAlex Deucher * 5 - >= 16562cae3bc3SAlex Deucher * 6 - > 16572cae3bc3SAlex Deucher */ 16582cae3bc3SAlex Deucher #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 16592cae3bc3SAlex Deucher /* 0 - reg 16602cae3bc3SAlex Deucher * 1 - mem 16612cae3bc3SAlex Deucher */ 16622cae3bc3SAlex Deucher #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 16632cae3bc3SAlex Deucher /* 0 - wait_reg_mem 16642cae3bc3SAlex Deucher * 1 - wr_wait_wr_reg 16652cae3bc3SAlex Deucher */ 16662cae3bc3SAlex Deucher #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 16672cae3bc3SAlex Deucher /* 0 - me 16682cae3bc3SAlex Deucher * 1 - pfp 16692cae3bc3SAlex Deucher */ 1670841cf442SAlex Deucher #define PACKET3_INDIRECT_BUFFER 0x3F 16712cae3bc3SAlex Deucher #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 16722cae3bc3SAlex Deucher #define INDIRECT_BUFFER_VALID (1 << 23) 16732cae3bc3SAlex Deucher #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 16742cae3bc3SAlex Deucher /* 0 - LRU 16752cae3bc3SAlex Deucher * 1 - Stream 16762cae3bc3SAlex Deucher * 2 - Bypass 16772cae3bc3SAlex Deucher */ 1678841cf442SAlex Deucher #define PACKET3_COPY_DATA 0x40 1679841cf442SAlex Deucher #define PACKET3_PFP_SYNC_ME 0x42 1680841cf442SAlex Deucher #define PACKET3_SURFACE_SYNC 0x43 1681841cf442SAlex Deucher # define PACKET3_DEST_BASE_0_ENA (1 << 0) 1682841cf442SAlex Deucher # define PACKET3_DEST_BASE_1_ENA (1 << 1) 1683841cf442SAlex Deucher # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1684841cf442SAlex Deucher # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1685841cf442SAlex Deucher # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1686841cf442SAlex Deucher # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1687841cf442SAlex Deucher # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1688841cf442SAlex Deucher # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1689841cf442SAlex Deucher # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1690841cf442SAlex Deucher # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1691841cf442SAlex Deucher # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1692841cf442SAlex Deucher # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 1693841cf442SAlex Deucher # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 1694841cf442SAlex Deucher # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 1695841cf442SAlex Deucher # define PACKET3_DEST_BASE_2_ENA (1 << 19) 1696841cf442SAlex Deucher # define PACKET3_DEST_BASE_3_ENA (1 << 21) 1697841cf442SAlex Deucher # define PACKET3_TCL1_ACTION_ENA (1 << 22) 1698841cf442SAlex Deucher # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 1699841cf442SAlex Deucher # define PACKET3_CB_ACTION_ENA (1 << 25) 1700841cf442SAlex Deucher # define PACKET3_DB_ACTION_ENA (1 << 26) 1701841cf442SAlex Deucher # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 1702841cf442SAlex Deucher # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 1703841cf442SAlex Deucher # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 1704841cf442SAlex Deucher #define PACKET3_COND_WRITE 0x45 1705841cf442SAlex Deucher #define PACKET3_EVENT_WRITE 0x46 1706841cf442SAlex Deucher #define EVENT_TYPE(x) ((x) << 0) 1707841cf442SAlex Deucher #define EVENT_INDEX(x) ((x) << 8) 1708841cf442SAlex Deucher /* 0 - any non-TS event 1709841cf442SAlex Deucher * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 1710841cf442SAlex Deucher * 2 - SAMPLE_PIPELINESTAT 1711841cf442SAlex Deucher * 3 - SAMPLE_STREAMOUTSTAT* 1712841cf442SAlex Deucher * 4 - *S_PARTIAL_FLUSH 1713841cf442SAlex Deucher * 5 - EOP events 1714841cf442SAlex Deucher * 6 - EOS events 1715841cf442SAlex Deucher */ 1716841cf442SAlex Deucher #define PACKET3_EVENT_WRITE_EOP 0x47 1717841cf442SAlex Deucher #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 1718841cf442SAlex Deucher #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 1719841cf442SAlex Deucher #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 1720841cf442SAlex Deucher #define EOP_TCL1_ACTION_EN (1 << 16) 1721841cf442SAlex Deucher #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 17222cae3bc3SAlex Deucher #define EOP_CACHE_POLICY(x) ((x) << 25) 1723841cf442SAlex Deucher /* 0 - LRU 1724841cf442SAlex Deucher * 1 - Stream 1725841cf442SAlex Deucher * 2 - Bypass 1726841cf442SAlex Deucher */ 17272cae3bc3SAlex Deucher #define EOP_TCL2_VOLATILE (1 << 27) 1728841cf442SAlex Deucher #define DATA_SEL(x) ((x) << 29) 1729841cf442SAlex Deucher /* 0 - discard 1730841cf442SAlex Deucher * 1 - send low 32bit data 1731841cf442SAlex Deucher * 2 - send 64bit data 1732841cf442SAlex Deucher * 3 - send 64bit GPU counter value 1733841cf442SAlex Deucher * 4 - send 64bit sys counter value 1734841cf442SAlex Deucher */ 1735841cf442SAlex Deucher #define INT_SEL(x) ((x) << 24) 1736841cf442SAlex Deucher /* 0 - none 1737841cf442SAlex Deucher * 1 - interrupt only (DATA_SEL = 0) 1738841cf442SAlex Deucher * 2 - interrupt when data write is confirmed 1739841cf442SAlex Deucher */ 1740841cf442SAlex Deucher #define DST_SEL(x) ((x) << 16) 1741841cf442SAlex Deucher /* 0 - MC 1742841cf442SAlex Deucher * 1 - TC/L2 1743841cf442SAlex Deucher */ 1744841cf442SAlex Deucher #define PACKET3_EVENT_WRITE_EOS 0x48 1745841cf442SAlex Deucher #define PACKET3_RELEASE_MEM 0x49 1746841cf442SAlex Deucher #define PACKET3_PREAMBLE_CNTL 0x4A 1747841cf442SAlex Deucher # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1748841cf442SAlex Deucher # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1749841cf442SAlex Deucher #define PACKET3_DMA_DATA 0x50 1750*c9dbd705SAlex Deucher /* 1. header 1751*c9dbd705SAlex Deucher * 2. CONTROL 1752*c9dbd705SAlex Deucher * 3. SRC_ADDR_LO or DATA [31:0] 1753*c9dbd705SAlex Deucher * 4. SRC_ADDR_HI [31:0] 1754*c9dbd705SAlex Deucher * 5. DST_ADDR_LO [31:0] 1755*c9dbd705SAlex Deucher * 6. DST_ADDR_HI [7:0] 1756*c9dbd705SAlex Deucher * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 1757*c9dbd705SAlex Deucher */ 1758*c9dbd705SAlex Deucher /* CONTROL */ 1759*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 1760*c9dbd705SAlex Deucher /* 0 - ME 1761*c9dbd705SAlex Deucher * 1 - PFP 1762*c9dbd705SAlex Deucher */ 1763*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 1764*c9dbd705SAlex Deucher /* 0 - LRU 1765*c9dbd705SAlex Deucher * 1 - Stream 1766*c9dbd705SAlex Deucher * 2 - Bypass 1767*c9dbd705SAlex Deucher */ 1768*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 1769*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 1770*c9dbd705SAlex Deucher /* 0 - DST_ADDR using DAS 1771*c9dbd705SAlex Deucher * 1 - GDS 1772*c9dbd705SAlex Deucher * 3 - DST_ADDR using L2 1773*c9dbd705SAlex Deucher */ 1774*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 1775*c9dbd705SAlex Deucher /* 0 - LRU 1776*c9dbd705SAlex Deucher * 1 - Stream 1777*c9dbd705SAlex Deucher * 2 - Bypass 1778*c9dbd705SAlex Deucher */ 1779*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 1780*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 1781*c9dbd705SAlex Deucher /* 0 - SRC_ADDR using SAS 1782*c9dbd705SAlex Deucher * 1 - GDS 1783*c9dbd705SAlex Deucher * 2 - DATA 1784*c9dbd705SAlex Deucher * 3 - SRC_ADDR using L2 1785*c9dbd705SAlex Deucher */ 1786*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 1787*c9dbd705SAlex Deucher /* COMMAND */ 1788*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_DIS_WC (1 << 21) 1789*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 1790*c9dbd705SAlex Deucher /* 0 - none 1791*c9dbd705SAlex Deucher * 1 - 8 in 16 1792*c9dbd705SAlex Deucher * 2 - 8 in 32 1793*c9dbd705SAlex Deucher * 3 - 8 in 64 1794*c9dbd705SAlex Deucher */ 1795*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 1796*c9dbd705SAlex Deucher /* 0 - none 1797*c9dbd705SAlex Deucher * 1 - 8 in 16 1798*c9dbd705SAlex Deucher * 2 - 8 in 32 1799*c9dbd705SAlex Deucher * 3 - 8 in 64 1800*c9dbd705SAlex Deucher */ 1801*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 1802*c9dbd705SAlex Deucher /* 0 - memory 1803*c9dbd705SAlex Deucher * 1 - register 1804*c9dbd705SAlex Deucher */ 1805*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 1806*c9dbd705SAlex Deucher /* 0 - memory 1807*c9dbd705SAlex Deucher * 1 - register 1808*c9dbd705SAlex Deucher */ 1809*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 1810*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 1811*c9dbd705SAlex Deucher # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 1812841cf442SAlex Deucher #define PACKET3_AQUIRE_MEM 0x58 1813841cf442SAlex Deucher #define PACKET3_REWIND 0x59 1814841cf442SAlex Deucher #define PACKET3_LOAD_UCONFIG_REG 0x5E 1815841cf442SAlex Deucher #define PACKET3_LOAD_SH_REG 0x5F 1816841cf442SAlex Deucher #define PACKET3_LOAD_CONFIG_REG 0x60 1817841cf442SAlex Deucher #define PACKET3_LOAD_CONTEXT_REG 0x61 1818841cf442SAlex Deucher #define PACKET3_SET_CONFIG_REG 0x68 1819841cf442SAlex Deucher #define PACKET3_SET_CONFIG_REG_START 0x00008000 1820841cf442SAlex Deucher #define PACKET3_SET_CONFIG_REG_END 0x0000b000 1821841cf442SAlex Deucher #define PACKET3_SET_CONTEXT_REG 0x69 1822841cf442SAlex Deucher #define PACKET3_SET_CONTEXT_REG_START 0x00028000 1823841cf442SAlex Deucher #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1824841cf442SAlex Deucher #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1825841cf442SAlex Deucher #define PACKET3_SET_SH_REG 0x76 1826841cf442SAlex Deucher #define PACKET3_SET_SH_REG_START 0x0000b000 1827841cf442SAlex Deucher #define PACKET3_SET_SH_REG_END 0x0000c000 1828841cf442SAlex Deucher #define PACKET3_SET_SH_REG_OFFSET 0x77 1829841cf442SAlex Deucher #define PACKET3_SET_QUEUE_REG 0x78 1830841cf442SAlex Deucher #define PACKET3_SET_UCONFIG_REG 0x79 18312cae3bc3SAlex Deucher #define PACKET3_SET_UCONFIG_REG_START 0x00030000 18322cae3bc3SAlex Deucher #define PACKET3_SET_UCONFIG_REG_END 0x00031000 1833841cf442SAlex Deucher #define PACKET3_SCRATCH_RAM_WRITE 0x7D 1834841cf442SAlex Deucher #define PACKET3_SCRATCH_RAM_READ 0x7E 1835841cf442SAlex Deucher #define PACKET3_LOAD_CONST_RAM 0x80 1836841cf442SAlex Deucher #define PACKET3_WRITE_CONST_RAM 0x81 1837841cf442SAlex Deucher #define PACKET3_DUMP_CONST_RAM 0x83 1838841cf442SAlex Deucher #define PACKET3_INCREMENT_CE_COUNTER 0x84 1839841cf442SAlex Deucher #define PACKET3_INCREMENT_DE_COUNTER 0x85 1840841cf442SAlex Deucher #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1841841cf442SAlex Deucher #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 18422cae3bc3SAlex Deucher #define PACKET3_SWITCH_BUFFER 0x8B 1843841cf442SAlex Deucher 184421a93e13SAlex Deucher /* SDMA - first instance at 0xd000, second at 0xd800 */ 184521a93e13SAlex Deucher #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 184621a93e13SAlex Deucher #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ 184721a93e13SAlex Deucher 184821a93e13SAlex Deucher #define SDMA0_UCODE_ADDR 0xD000 184921a93e13SAlex Deucher #define SDMA0_UCODE_DATA 0xD004 185022c775ceSAlex Deucher #define SDMA0_POWER_CNTL 0xD008 185122c775ceSAlex Deucher #define SDMA0_CLK_CTRL 0xD00C 185221a93e13SAlex Deucher 185321a93e13SAlex Deucher #define SDMA0_CNTL 0xD010 185421a93e13SAlex Deucher # define TRAP_ENABLE (1 << 0) 185521a93e13SAlex Deucher # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 185621a93e13SAlex Deucher # define SEM_WAIT_INT_ENABLE (1 << 2) 185721a93e13SAlex Deucher # define DATA_SWAP_ENABLE (1 << 3) 185821a93e13SAlex Deucher # define FENCE_SWAP_ENABLE (1 << 4) 185921a93e13SAlex Deucher # define AUTO_CTXSW_ENABLE (1 << 18) 186021a93e13SAlex Deucher # define CTXEMPTY_INT_ENABLE (1 << 28) 186121a93e13SAlex Deucher 186221a93e13SAlex Deucher #define SDMA0_TILING_CONFIG 0xD018 186321a93e13SAlex Deucher 186421a93e13SAlex Deucher #define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020 186521a93e13SAlex Deucher #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024 186621a93e13SAlex Deucher 186721a93e13SAlex Deucher #define SDMA0_STATUS_REG 0xd034 186821a93e13SAlex Deucher # define SDMA_IDLE (1 << 0) 186921a93e13SAlex Deucher 187021a93e13SAlex Deucher #define SDMA0_ME_CNTL 0xD048 187121a93e13SAlex Deucher # define SDMA_HALT (1 << 0) 187221a93e13SAlex Deucher 187321a93e13SAlex Deucher #define SDMA0_GFX_RB_CNTL 0xD200 187421a93e13SAlex Deucher # define SDMA_RB_ENABLE (1 << 0) 187521a93e13SAlex Deucher # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */ 187621a93e13SAlex Deucher # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 187721a93e13SAlex Deucher # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12) 187821a93e13SAlex Deucher # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 187921a93e13SAlex Deucher # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 188021a93e13SAlex Deucher #define SDMA0_GFX_RB_BASE 0xD204 188121a93e13SAlex Deucher #define SDMA0_GFX_RB_BASE_HI 0xD208 188221a93e13SAlex Deucher #define SDMA0_GFX_RB_RPTR 0xD20C 188321a93e13SAlex Deucher #define SDMA0_GFX_RB_WPTR 0xD210 188421a93e13SAlex Deucher 188521a93e13SAlex Deucher #define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220 188621a93e13SAlex Deucher #define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224 188721a93e13SAlex Deucher #define SDMA0_GFX_IB_CNTL 0xD228 188821a93e13SAlex Deucher # define SDMA_IB_ENABLE (1 << 0) 188921a93e13SAlex Deucher # define SDMA_IB_SWAP_ENABLE (1 << 4) 189021a93e13SAlex Deucher # define SDMA_SWITCH_INSIDE_IB (1 << 8) 189121a93e13SAlex Deucher # define SDMA_CMD_VMID(x) ((x) << 16) 189221a93e13SAlex Deucher 189321a93e13SAlex Deucher #define SDMA0_GFX_VIRTUAL_ADDR 0xD29C 189421a93e13SAlex Deucher #define SDMA0_GFX_APE1_CNTL 0xD2A0 189521a93e13SAlex Deucher 189621a93e13SAlex Deucher #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 189721a93e13SAlex Deucher (((sub_op) & 0xFF) << 8) | \ 189821a93e13SAlex Deucher (((op) & 0xFF) << 0)) 189921a93e13SAlex Deucher /* sDMA opcodes */ 190021a93e13SAlex Deucher #define SDMA_OPCODE_NOP 0 190121a93e13SAlex Deucher #define SDMA_OPCODE_COPY 1 190221a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_LINEAR 0 190321a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_TILED 1 190421a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_SOA 3 190521a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 190621a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 190721a93e13SAlex Deucher # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 190821a93e13SAlex Deucher #define SDMA_OPCODE_WRITE 2 190921a93e13SAlex Deucher # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 191021a93e13SAlex Deucher # define SDMA_WRTIE_SUB_OPCODE_TILED 1 191121a93e13SAlex Deucher #define SDMA_OPCODE_INDIRECT_BUFFER 4 191221a93e13SAlex Deucher #define SDMA_OPCODE_FENCE 5 191321a93e13SAlex Deucher #define SDMA_OPCODE_TRAP 6 191421a93e13SAlex Deucher #define SDMA_OPCODE_SEMAPHORE 7 191521a93e13SAlex Deucher # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 191621a93e13SAlex Deucher /* 0 - increment 191721a93e13SAlex Deucher * 1 - write 1 191821a93e13SAlex Deucher */ 191921a93e13SAlex Deucher # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 192021a93e13SAlex Deucher /* 0 - wait 192121a93e13SAlex Deucher * 1 - signal 192221a93e13SAlex Deucher */ 192321a93e13SAlex Deucher # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 192421a93e13SAlex Deucher /* mailbox */ 192521a93e13SAlex Deucher #define SDMA_OPCODE_POLL_REG_MEM 8 192621a93e13SAlex Deucher # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 192721a93e13SAlex Deucher /* 0 - wait_reg_mem 192821a93e13SAlex Deucher * 1 - wr_wait_wr_reg 192921a93e13SAlex Deucher */ 193021a93e13SAlex Deucher # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 193121a93e13SAlex Deucher /* 0 - always 193221a93e13SAlex Deucher * 1 - < 193321a93e13SAlex Deucher * 2 - <= 193421a93e13SAlex Deucher * 3 - == 193521a93e13SAlex Deucher * 4 - != 193621a93e13SAlex Deucher * 5 - >= 193721a93e13SAlex Deucher * 6 - > 193821a93e13SAlex Deucher */ 193921a93e13SAlex Deucher # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 194021a93e13SAlex Deucher /* 0 = register 194121a93e13SAlex Deucher * 1 = memory 194221a93e13SAlex Deucher */ 194321a93e13SAlex Deucher #define SDMA_OPCODE_COND_EXEC 9 194421a93e13SAlex Deucher #define SDMA_OPCODE_CONSTANT_FILL 11 194521a93e13SAlex Deucher # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 194621a93e13SAlex Deucher /* 0 = byte fill 194721a93e13SAlex Deucher * 2 = DW fill 194821a93e13SAlex Deucher */ 194921a93e13SAlex Deucher #define SDMA_OPCODE_GENERATE_PTE_PDE 12 195021a93e13SAlex Deucher #define SDMA_OPCODE_TIMESTAMP 13 195121a93e13SAlex Deucher # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 195221a93e13SAlex Deucher # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 195321a93e13SAlex Deucher # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 195421a93e13SAlex Deucher #define SDMA_OPCODE_SRBM_WRITE 14 195521a93e13SAlex Deucher # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 195621a93e13SAlex Deucher /* byte mask */ 195721a93e13SAlex Deucher 195887167bb1SChristian König /* UVD */ 195987167bb1SChristian König 196087167bb1SChristian König #define UVD_UDEC_ADDR_CONFIG 0xef4c 196187167bb1SChristian König #define UVD_UDEC_DB_ADDR_CONFIG 0xef50 196287167bb1SChristian König #define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 196387167bb1SChristian König 196487167bb1SChristian König #define UVD_LMI_EXT40_ADDR 0xf498 196587167bb1SChristian König #define UVD_LMI_ADDR_EXT 0xf594 196687167bb1SChristian König #define UVD_VCPU_CACHE_OFFSET0 0xf608 196787167bb1SChristian König #define UVD_VCPU_CACHE_SIZE0 0xf60c 196887167bb1SChristian König #define UVD_VCPU_CACHE_OFFSET1 0xf610 196987167bb1SChristian König #define UVD_VCPU_CACHE_SIZE1 0xf614 197087167bb1SChristian König #define UVD_VCPU_CACHE_OFFSET2 0xf618 197187167bb1SChristian König #define UVD_VCPU_CACHE_SIZE2 0xf61c 197287167bb1SChristian König 197387167bb1SChristian König #define UVD_RBC_RB_RPTR 0xf690 197487167bb1SChristian König #define UVD_RBC_RB_WPTR 0xf694 197587167bb1SChristian König 197622c775ceSAlex Deucher #define UVD_CGC_CTRL 0xF4B0 197722c775ceSAlex Deucher # define DCM (1 << 0) 197822c775ceSAlex Deucher # define CG_DT(x) ((x) << 2) 197922c775ceSAlex Deucher # define CG_DT_MASK (0xf << 2) 198022c775ceSAlex Deucher # define CLK_OD(x) ((x) << 6) 198122c775ceSAlex Deucher # define CLK_OD_MASK (0x1f << 6) 198222c775ceSAlex Deucher 198387167bb1SChristian König /* UVD clocks */ 198487167bb1SChristian König 198587167bb1SChristian König #define CG_DCLK_CNTL 0xC050009C 198687167bb1SChristian König # define DCLK_DIVIDER_MASK 0x7f 198787167bb1SChristian König # define DCLK_DIR_CNTL_EN (1 << 8) 198887167bb1SChristian König #define CG_DCLK_STATUS 0xC05000A0 198987167bb1SChristian König # define DCLK_STATUS (1 << 0) 199087167bb1SChristian König #define CG_VCLK_CNTL 0xC05000A4 199187167bb1SChristian König #define CG_VCLK_STATUS 0xC05000A8 199287167bb1SChristian König 199322c775ceSAlex Deucher /* UVD CTX indirect */ 199422c775ceSAlex Deucher #define UVD_CGC_MEM_CTRL 0xC0 199522c775ceSAlex Deucher 19968cc1a532SAlex Deucher #endif 1997