1*cc8dbbb4SAlex Deucher /* 2*cc8dbbb4SAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 3*cc8dbbb4SAlex Deucher * 4*cc8dbbb4SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5*cc8dbbb4SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6*cc8dbbb4SAlex Deucher * to deal in the Software without restriction, including without limitation 7*cc8dbbb4SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*cc8dbbb4SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9*cc8dbbb4SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10*cc8dbbb4SAlex Deucher * 11*cc8dbbb4SAlex Deucher * The above copyright notice and this permission notice shall be included in 12*cc8dbbb4SAlex Deucher * all copies or substantial portions of the Software. 13*cc8dbbb4SAlex Deucher * 14*cc8dbbb4SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*cc8dbbb4SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*cc8dbbb4SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*cc8dbbb4SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*cc8dbbb4SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*cc8dbbb4SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*cc8dbbb4SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21*cc8dbbb4SAlex Deucher * 22*cc8dbbb4SAlex Deucher */ 23*cc8dbbb4SAlex Deucher #ifndef __CI_DPM_H__ 24*cc8dbbb4SAlex Deucher #define __CI_DPM_H__ 25*cc8dbbb4SAlex Deucher 26*cc8dbbb4SAlex Deucher #include "ppsmc.h" 27*cc8dbbb4SAlex Deucher 28*cc8dbbb4SAlex Deucher #define SMU__NUM_SCLK_DPM_STATE 8 29*cc8dbbb4SAlex Deucher #define SMU__NUM_MCLK_DPM_LEVELS 6 30*cc8dbbb4SAlex Deucher #define SMU__NUM_LCLK_DPM_LEVELS 8 31*cc8dbbb4SAlex Deucher #define SMU__NUM_PCIE_DPM_LEVELS 8 32*cc8dbbb4SAlex Deucher #include "smu7_discrete.h" 33*cc8dbbb4SAlex Deucher 34*cc8dbbb4SAlex Deucher #define CISLANDS_MAX_HARDWARE_POWERLEVELS 2 35*cc8dbbb4SAlex Deucher 36*cc8dbbb4SAlex Deucher struct ci_pl { 37*cc8dbbb4SAlex Deucher u32 mclk; 38*cc8dbbb4SAlex Deucher u32 sclk; 39*cc8dbbb4SAlex Deucher enum radeon_pcie_gen pcie_gen; 40*cc8dbbb4SAlex Deucher u16 pcie_lane; 41*cc8dbbb4SAlex Deucher }; 42*cc8dbbb4SAlex Deucher 43*cc8dbbb4SAlex Deucher struct ci_ps { 44*cc8dbbb4SAlex Deucher u16 performance_level_count; 45*cc8dbbb4SAlex Deucher bool dc_compatible; 46*cc8dbbb4SAlex Deucher u32 sclk_t; 47*cc8dbbb4SAlex Deucher struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS]; 48*cc8dbbb4SAlex Deucher }; 49*cc8dbbb4SAlex Deucher 50*cc8dbbb4SAlex Deucher struct ci_dpm_level { 51*cc8dbbb4SAlex Deucher bool enabled; 52*cc8dbbb4SAlex Deucher u32 value; 53*cc8dbbb4SAlex Deucher u32 param1; 54*cc8dbbb4SAlex Deucher }; 55*cc8dbbb4SAlex Deucher 56*cc8dbbb4SAlex Deucher #define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5 57*cc8dbbb4SAlex Deucher #define MAX_REGULAR_DPM_NUMBER 8 58*cc8dbbb4SAlex Deucher #define CISLAND_MINIMUM_ENGINE_CLOCK 800 59*cc8dbbb4SAlex Deucher 60*cc8dbbb4SAlex Deucher struct ci_single_dpm_table { 61*cc8dbbb4SAlex Deucher u32 count; 62*cc8dbbb4SAlex Deucher struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 63*cc8dbbb4SAlex Deucher }; 64*cc8dbbb4SAlex Deucher 65*cc8dbbb4SAlex Deucher struct ci_dpm_table { 66*cc8dbbb4SAlex Deucher struct ci_single_dpm_table sclk_table; 67*cc8dbbb4SAlex Deucher struct ci_single_dpm_table mclk_table; 68*cc8dbbb4SAlex Deucher struct ci_single_dpm_table pcie_speed_table; 69*cc8dbbb4SAlex Deucher struct ci_single_dpm_table vddc_table; 70*cc8dbbb4SAlex Deucher struct ci_single_dpm_table vddci_table; 71*cc8dbbb4SAlex Deucher struct ci_single_dpm_table mvdd_table; 72*cc8dbbb4SAlex Deucher }; 73*cc8dbbb4SAlex Deucher 74*cc8dbbb4SAlex Deucher struct ci_mc_reg_entry { 75*cc8dbbb4SAlex Deucher u32 mclk_max; 76*cc8dbbb4SAlex Deucher u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 77*cc8dbbb4SAlex Deucher }; 78*cc8dbbb4SAlex Deucher 79*cc8dbbb4SAlex Deucher struct ci_mc_reg_table { 80*cc8dbbb4SAlex Deucher u8 last; 81*cc8dbbb4SAlex Deucher u8 num_entries; 82*cc8dbbb4SAlex Deucher u16 valid_flag; 83*cc8dbbb4SAlex Deucher struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 84*cc8dbbb4SAlex Deucher SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 85*cc8dbbb4SAlex Deucher }; 86*cc8dbbb4SAlex Deucher 87*cc8dbbb4SAlex Deucher struct ci_ulv_parm 88*cc8dbbb4SAlex Deucher { 89*cc8dbbb4SAlex Deucher bool supported; 90*cc8dbbb4SAlex Deucher u32 cg_ulv_parameter; 91*cc8dbbb4SAlex Deucher u32 volt_change_delay; 92*cc8dbbb4SAlex Deucher struct ci_pl pl; 93*cc8dbbb4SAlex Deucher }; 94*cc8dbbb4SAlex Deucher 95*cc8dbbb4SAlex Deucher #define CISLANDS_MAX_LEAKAGE_COUNT 8 96*cc8dbbb4SAlex Deucher 97*cc8dbbb4SAlex Deucher struct ci_leakage_voltage { 98*cc8dbbb4SAlex Deucher u16 count; 99*cc8dbbb4SAlex Deucher u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT]; 100*cc8dbbb4SAlex Deucher u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT]; 101*cc8dbbb4SAlex Deucher }; 102*cc8dbbb4SAlex Deucher 103*cc8dbbb4SAlex Deucher struct ci_dpm_level_enable_mask { 104*cc8dbbb4SAlex Deucher u32 uvd_dpm_enable_mask; 105*cc8dbbb4SAlex Deucher u32 vce_dpm_enable_mask; 106*cc8dbbb4SAlex Deucher u32 acp_dpm_enable_mask; 107*cc8dbbb4SAlex Deucher u32 samu_dpm_enable_mask; 108*cc8dbbb4SAlex Deucher u32 sclk_dpm_enable_mask; 109*cc8dbbb4SAlex Deucher u32 mclk_dpm_enable_mask; 110*cc8dbbb4SAlex Deucher u32 pcie_dpm_enable_mask; 111*cc8dbbb4SAlex Deucher }; 112*cc8dbbb4SAlex Deucher 113*cc8dbbb4SAlex Deucher struct ci_vbios_boot_state 114*cc8dbbb4SAlex Deucher { 115*cc8dbbb4SAlex Deucher u16 mvdd_bootup_value; 116*cc8dbbb4SAlex Deucher u16 vddc_bootup_value; 117*cc8dbbb4SAlex Deucher u16 vddci_bootup_value; 118*cc8dbbb4SAlex Deucher u32 sclk_bootup_value; 119*cc8dbbb4SAlex Deucher u32 mclk_bootup_value; 120*cc8dbbb4SAlex Deucher u16 pcie_gen_bootup_value; 121*cc8dbbb4SAlex Deucher u16 pcie_lane_bootup_value; 122*cc8dbbb4SAlex Deucher }; 123*cc8dbbb4SAlex Deucher 124*cc8dbbb4SAlex Deucher struct ci_clock_registers { 125*cc8dbbb4SAlex Deucher u32 cg_spll_func_cntl; 126*cc8dbbb4SAlex Deucher u32 cg_spll_func_cntl_2; 127*cc8dbbb4SAlex Deucher u32 cg_spll_func_cntl_3; 128*cc8dbbb4SAlex Deucher u32 cg_spll_func_cntl_4; 129*cc8dbbb4SAlex Deucher u32 cg_spll_spread_spectrum; 130*cc8dbbb4SAlex Deucher u32 cg_spll_spread_spectrum_2; 131*cc8dbbb4SAlex Deucher u32 dll_cntl; 132*cc8dbbb4SAlex Deucher u32 mclk_pwrmgt_cntl; 133*cc8dbbb4SAlex Deucher u32 mpll_ad_func_cntl; 134*cc8dbbb4SAlex Deucher u32 mpll_dq_func_cntl; 135*cc8dbbb4SAlex Deucher u32 mpll_func_cntl; 136*cc8dbbb4SAlex Deucher u32 mpll_func_cntl_1; 137*cc8dbbb4SAlex Deucher u32 mpll_func_cntl_2; 138*cc8dbbb4SAlex Deucher u32 mpll_ss1; 139*cc8dbbb4SAlex Deucher u32 mpll_ss2; 140*cc8dbbb4SAlex Deucher }; 141*cc8dbbb4SAlex Deucher 142*cc8dbbb4SAlex Deucher struct ci_thermal_temperature_setting { 143*cc8dbbb4SAlex Deucher s32 temperature_low; 144*cc8dbbb4SAlex Deucher s32 temperature_high; 145*cc8dbbb4SAlex Deucher s32 temperature_shutdown; 146*cc8dbbb4SAlex Deucher }; 147*cc8dbbb4SAlex Deucher 148*cc8dbbb4SAlex Deucher struct ci_pcie_perf_range { 149*cc8dbbb4SAlex Deucher u16 max; 150*cc8dbbb4SAlex Deucher u16 min; 151*cc8dbbb4SAlex Deucher }; 152*cc8dbbb4SAlex Deucher 153*cc8dbbb4SAlex Deucher enum ci_pt_config_reg_type { 154*cc8dbbb4SAlex Deucher CISLANDS_CONFIGREG_MMR = 0, 155*cc8dbbb4SAlex Deucher CISLANDS_CONFIGREG_SMC_IND, 156*cc8dbbb4SAlex Deucher CISLANDS_CONFIGREG_DIDT_IND, 157*cc8dbbb4SAlex Deucher CISLANDS_CONFIGREG_CACHE, 158*cc8dbbb4SAlex Deucher CISLANDS_CONFIGREG_MAX 159*cc8dbbb4SAlex Deucher }; 160*cc8dbbb4SAlex Deucher 161*cc8dbbb4SAlex Deucher #define POWERCONTAINMENT_FEATURE_BAPM 0x00000001 162*cc8dbbb4SAlex Deucher #define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002 163*cc8dbbb4SAlex Deucher #define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004 164*cc8dbbb4SAlex Deucher 165*cc8dbbb4SAlex Deucher struct ci_pt_config_reg { 166*cc8dbbb4SAlex Deucher u32 offset; 167*cc8dbbb4SAlex Deucher u32 mask; 168*cc8dbbb4SAlex Deucher u32 shift; 169*cc8dbbb4SAlex Deucher u32 value; 170*cc8dbbb4SAlex Deucher enum ci_pt_config_reg_type type; 171*cc8dbbb4SAlex Deucher }; 172*cc8dbbb4SAlex Deucher 173*cc8dbbb4SAlex Deucher struct ci_pt_defaults { 174*cc8dbbb4SAlex Deucher u8 svi_load_line_en; 175*cc8dbbb4SAlex Deucher u8 svi_load_line_vddc; 176*cc8dbbb4SAlex Deucher u8 tdc_vddc_throttle_release_limit_perc; 177*cc8dbbb4SAlex Deucher u8 tdc_mawt; 178*cc8dbbb4SAlex Deucher u8 tdc_waterfall_ctl; 179*cc8dbbb4SAlex Deucher u8 dte_ambient_temp_base; 180*cc8dbbb4SAlex Deucher u32 display_cac; 181*cc8dbbb4SAlex Deucher u32 bapm_temp_gradient; 182*cc8dbbb4SAlex Deucher u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS]; 183*cc8dbbb4SAlex Deucher u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS]; 184*cc8dbbb4SAlex Deucher }; 185*cc8dbbb4SAlex Deucher 186*cc8dbbb4SAlex Deucher #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 187*cc8dbbb4SAlex Deucher #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 188*cc8dbbb4SAlex Deucher #define DPMTABLE_UPDATE_SCLK 0x00000004 189*cc8dbbb4SAlex Deucher #define DPMTABLE_UPDATE_MCLK 0x00000008 190*cc8dbbb4SAlex Deucher 191*cc8dbbb4SAlex Deucher struct ci_power_info { 192*cc8dbbb4SAlex Deucher struct ci_dpm_table dpm_table; 193*cc8dbbb4SAlex Deucher u32 voltage_control; 194*cc8dbbb4SAlex Deucher u32 mvdd_control; 195*cc8dbbb4SAlex Deucher u32 vddci_control; 196*cc8dbbb4SAlex Deucher u32 active_auto_throttle_sources; 197*cc8dbbb4SAlex Deucher struct ci_clock_registers clock_registers; 198*cc8dbbb4SAlex Deucher u16 acpi_vddc; 199*cc8dbbb4SAlex Deucher u16 acpi_vddci; 200*cc8dbbb4SAlex Deucher enum radeon_pcie_gen force_pcie_gen; 201*cc8dbbb4SAlex Deucher enum radeon_pcie_gen acpi_pcie_gen; 202*cc8dbbb4SAlex Deucher struct ci_leakage_voltage vddc_leakage; 203*cc8dbbb4SAlex Deucher struct ci_leakage_voltage vddci_leakage; 204*cc8dbbb4SAlex Deucher u16 max_vddc_in_pp_table; 205*cc8dbbb4SAlex Deucher u16 min_vddc_in_pp_table; 206*cc8dbbb4SAlex Deucher u16 max_vddci_in_pp_table; 207*cc8dbbb4SAlex Deucher u16 min_vddci_in_pp_table; 208*cc8dbbb4SAlex Deucher u32 mclk_strobe_mode_threshold; 209*cc8dbbb4SAlex Deucher u32 mclk_stutter_mode_threshold; 210*cc8dbbb4SAlex Deucher u32 mclk_edc_enable_threshold; 211*cc8dbbb4SAlex Deucher u32 mclk_edc_wr_enable_threshold; 212*cc8dbbb4SAlex Deucher struct ci_vbios_boot_state vbios_boot_state; 213*cc8dbbb4SAlex Deucher /* smc offsets */ 214*cc8dbbb4SAlex Deucher u32 sram_end; 215*cc8dbbb4SAlex Deucher u32 dpm_table_start; 216*cc8dbbb4SAlex Deucher u32 soft_regs_start; 217*cc8dbbb4SAlex Deucher u32 mc_reg_table_start; 218*cc8dbbb4SAlex Deucher u32 fan_table_start; 219*cc8dbbb4SAlex Deucher u32 arb_table_start; 220*cc8dbbb4SAlex Deucher /* smc tables */ 221*cc8dbbb4SAlex Deucher SMU7_Discrete_DpmTable smc_state_table; 222*cc8dbbb4SAlex Deucher SMU7_Discrete_MCRegisters smc_mc_reg_table; 223*cc8dbbb4SAlex Deucher SMU7_Discrete_PmFuses smc_powertune_table; 224*cc8dbbb4SAlex Deucher /* other stuff */ 225*cc8dbbb4SAlex Deucher struct ci_mc_reg_table mc_reg_table; 226*cc8dbbb4SAlex Deucher struct atom_voltage_table vddc_voltage_table; 227*cc8dbbb4SAlex Deucher struct atom_voltage_table vddci_voltage_table; 228*cc8dbbb4SAlex Deucher struct atom_voltage_table mvdd_voltage_table; 229*cc8dbbb4SAlex Deucher struct ci_ulv_parm ulv; 230*cc8dbbb4SAlex Deucher u32 power_containment_features; 231*cc8dbbb4SAlex Deucher const struct ci_pt_defaults *powertune_defaults; 232*cc8dbbb4SAlex Deucher u32 dte_tj_offset; 233*cc8dbbb4SAlex Deucher bool vddc_phase_shed_control; 234*cc8dbbb4SAlex Deucher struct ci_thermal_temperature_setting thermal_temp_setting; 235*cc8dbbb4SAlex Deucher struct ci_dpm_level_enable_mask dpm_level_enable_mask; 236*cc8dbbb4SAlex Deucher u32 need_update_smu7_dpm_table; 237*cc8dbbb4SAlex Deucher u32 sclk_dpm_key_disabled; 238*cc8dbbb4SAlex Deucher u32 mclk_dpm_key_disabled; 239*cc8dbbb4SAlex Deucher u32 pcie_dpm_key_disabled; 240*cc8dbbb4SAlex Deucher struct ci_pcie_perf_range pcie_gen_performance; 241*cc8dbbb4SAlex Deucher struct ci_pcie_perf_range pcie_lane_performance; 242*cc8dbbb4SAlex Deucher struct ci_pcie_perf_range pcie_gen_powersaving; 243*cc8dbbb4SAlex Deucher struct ci_pcie_perf_range pcie_lane_powersaving; 244*cc8dbbb4SAlex Deucher u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS]; 245*cc8dbbb4SAlex Deucher u32 mclk_activity_target; 246*cc8dbbb4SAlex Deucher u32 low_sclk_interrupt_t; 247*cc8dbbb4SAlex Deucher u32 last_mclk_dpm_enable_mask; 248*cc8dbbb4SAlex Deucher u32 sys_pcie_mask; 249*cc8dbbb4SAlex Deucher /* caps */ 250*cc8dbbb4SAlex Deucher bool caps_power_containment; 251*cc8dbbb4SAlex Deucher bool caps_cac; 252*cc8dbbb4SAlex Deucher bool caps_sq_ramping; 253*cc8dbbb4SAlex Deucher bool caps_db_ramping; 254*cc8dbbb4SAlex Deucher bool caps_td_ramping; 255*cc8dbbb4SAlex Deucher bool caps_tcp_ramping; 256*cc8dbbb4SAlex Deucher bool caps_fps; 257*cc8dbbb4SAlex Deucher bool caps_sclk_ds; 258*cc8dbbb4SAlex Deucher bool caps_sclk_ss_support; 259*cc8dbbb4SAlex Deucher bool caps_mclk_ss_support; 260*cc8dbbb4SAlex Deucher bool caps_uvd_dpm; 261*cc8dbbb4SAlex Deucher bool caps_vce_dpm; 262*cc8dbbb4SAlex Deucher bool caps_samu_dpm; 263*cc8dbbb4SAlex Deucher bool caps_acp_dpm; 264*cc8dbbb4SAlex Deucher bool caps_automatic_dc_transition; 265*cc8dbbb4SAlex Deucher bool caps_sclk_throttle_low_notification; 266*cc8dbbb4SAlex Deucher bool caps_dynamic_ac_timing; 267*cc8dbbb4SAlex Deucher /* flags */ 268*cc8dbbb4SAlex Deucher bool thermal_protection; 269*cc8dbbb4SAlex Deucher bool pcie_performance_request; 270*cc8dbbb4SAlex Deucher bool dynamic_ss; 271*cc8dbbb4SAlex Deucher bool dll_default_on; 272*cc8dbbb4SAlex Deucher bool cac_enabled; 273*cc8dbbb4SAlex Deucher bool uvd_enabled; 274*cc8dbbb4SAlex Deucher bool battery_state; 275*cc8dbbb4SAlex Deucher bool pspp_notify_required; 276*cc8dbbb4SAlex Deucher bool mem_gddr5; 277*cc8dbbb4SAlex Deucher bool enable_bapm_feature; 278*cc8dbbb4SAlex Deucher bool enable_tdc_limit_feature; 279*cc8dbbb4SAlex Deucher bool enable_pkg_pwr_tracking_feature; 280*cc8dbbb4SAlex Deucher bool use_pcie_performance_levels; 281*cc8dbbb4SAlex Deucher bool use_pcie_powersaving_levels; 282*cc8dbbb4SAlex Deucher /* driver states */ 283*cc8dbbb4SAlex Deucher struct radeon_ps current_rps; 284*cc8dbbb4SAlex Deucher struct ci_ps current_ps; 285*cc8dbbb4SAlex Deucher struct radeon_ps requested_rps; 286*cc8dbbb4SAlex Deucher struct ci_ps requested_ps; 287*cc8dbbb4SAlex Deucher }; 288*cc8dbbb4SAlex Deucher 289*cc8dbbb4SAlex Deucher #define CISLANDS_VOLTAGE_CONTROL_NONE 0x0 290*cc8dbbb4SAlex Deucher #define CISLANDS_VOLTAGE_CONTROL_BY_GPIO 0x1 291*cc8dbbb4SAlex Deucher #define CISLANDS_VOLTAGE_CONTROL_BY_SVID2 0x2 292*cc8dbbb4SAlex Deucher 293*cc8dbbb4SAlex Deucher #define CISLANDS_Q88_FORMAT_CONVERSION_UNIT 256 294*cc8dbbb4SAlex Deucher 295*cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT0 0x3FFFC000 296*cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT1 0x000400 297*cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT2 0xC00080 298*cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT3 0xC00200 299*cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT4 0xC01680 300*cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT5 0xC00033 301*cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT6 0xC00033 302*cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT7 0x3FFFC000 303*cc8dbbb4SAlex Deucher 304*cc8dbbb4SAlex Deucher #define CISLANDS_CGULVPARAMETER_DFLT 0x00040035 305*cc8dbbb4SAlex Deucher #define CISLAND_TARGETACTIVITY_DFLT 30 306*cc8dbbb4SAlex Deucher #define CISLAND_MCLK_TARGETACTIVITY_DFLT 10 307*cc8dbbb4SAlex Deucher 308*cc8dbbb4SAlex Deucher #define PCIE_PERF_REQ_REMOVE_REGISTRY 0 309*cc8dbbb4SAlex Deucher #define PCIE_PERF_REQ_FORCE_LOWPOWER 1 310*cc8dbbb4SAlex Deucher #define PCIE_PERF_REQ_PECI_GEN1 2 311*cc8dbbb4SAlex Deucher #define PCIE_PERF_REQ_PECI_GEN2 3 312*cc8dbbb4SAlex Deucher #define PCIE_PERF_REQ_PECI_GEN3 4 313*cc8dbbb4SAlex Deucher 314*cc8dbbb4SAlex Deucher int ci_copy_bytes_to_smc(struct radeon_device *rdev, 315*cc8dbbb4SAlex Deucher u32 smc_start_address, 316*cc8dbbb4SAlex Deucher const u8 *src, u32 byte_count, u32 limit); 317*cc8dbbb4SAlex Deucher void ci_start_smc(struct radeon_device *rdev); 318*cc8dbbb4SAlex Deucher void ci_reset_smc(struct radeon_device *rdev); 319*cc8dbbb4SAlex Deucher int ci_program_jump_on_start(struct radeon_device *rdev); 320*cc8dbbb4SAlex Deucher void ci_stop_smc_clock(struct radeon_device *rdev); 321*cc8dbbb4SAlex Deucher void ci_start_smc_clock(struct radeon_device *rdev); 322*cc8dbbb4SAlex Deucher bool ci_is_smc_running(struct radeon_device *rdev); 323*cc8dbbb4SAlex Deucher PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg); 324*cc8dbbb4SAlex Deucher PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev); 325*cc8dbbb4SAlex Deucher int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit); 326*cc8dbbb4SAlex Deucher int ci_read_smc_sram_dword(struct radeon_device *rdev, 327*cc8dbbb4SAlex Deucher u32 smc_address, u32 *value, u32 limit); 328*cc8dbbb4SAlex Deucher int ci_write_smc_sram_dword(struct radeon_device *rdev, 329*cc8dbbb4SAlex Deucher u32 smc_address, u32 value, u32 limit); 330*cc8dbbb4SAlex Deucher 331*cc8dbbb4SAlex Deucher #endif 332