1cc8dbbb4SAlex Deucher /* 2cc8dbbb4SAlex Deucher * Copyright 2013 Advanced Micro Devices, Inc. 3cc8dbbb4SAlex Deucher * 4cc8dbbb4SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5cc8dbbb4SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6cc8dbbb4SAlex Deucher * to deal in the Software without restriction, including without limitation 7cc8dbbb4SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8cc8dbbb4SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9cc8dbbb4SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10cc8dbbb4SAlex Deucher * 11cc8dbbb4SAlex Deucher * The above copyright notice and this permission notice shall be included in 12cc8dbbb4SAlex Deucher * all copies or substantial portions of the Software. 13cc8dbbb4SAlex Deucher * 14cc8dbbb4SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15cc8dbbb4SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16cc8dbbb4SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17cc8dbbb4SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18cc8dbbb4SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19cc8dbbb4SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20cc8dbbb4SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21cc8dbbb4SAlex Deucher * 22cc8dbbb4SAlex Deucher */ 23cc8dbbb4SAlex Deucher #ifndef __CI_DPM_H__ 24cc8dbbb4SAlex Deucher #define __CI_DPM_H__ 25cc8dbbb4SAlex Deucher 26cc8dbbb4SAlex Deucher #include "ppsmc.h" 27cc8dbbb4SAlex Deucher 28cc8dbbb4SAlex Deucher #define SMU__NUM_SCLK_DPM_STATE 8 29cc8dbbb4SAlex Deucher #define SMU__NUM_MCLK_DPM_LEVELS 6 30cc8dbbb4SAlex Deucher #define SMU__NUM_LCLK_DPM_LEVELS 8 31cc8dbbb4SAlex Deucher #define SMU__NUM_PCIE_DPM_LEVELS 8 32cc8dbbb4SAlex Deucher #include "smu7_discrete.h" 33cc8dbbb4SAlex Deucher 34cc8dbbb4SAlex Deucher #define CISLANDS_MAX_HARDWARE_POWERLEVELS 2 35cc8dbbb4SAlex Deucher 36*34fc0b58SAlex Deucher #define CISLANDS_UNUSED_GPIO_PIN 0x7F 37*34fc0b58SAlex Deucher 38cc8dbbb4SAlex Deucher struct ci_pl { 39cc8dbbb4SAlex Deucher u32 mclk; 40cc8dbbb4SAlex Deucher u32 sclk; 41cc8dbbb4SAlex Deucher enum radeon_pcie_gen pcie_gen; 42cc8dbbb4SAlex Deucher u16 pcie_lane; 43cc8dbbb4SAlex Deucher }; 44cc8dbbb4SAlex Deucher 45cc8dbbb4SAlex Deucher struct ci_ps { 46cc8dbbb4SAlex Deucher u16 performance_level_count; 47cc8dbbb4SAlex Deucher bool dc_compatible; 48cc8dbbb4SAlex Deucher u32 sclk_t; 49cc8dbbb4SAlex Deucher struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS]; 50cc8dbbb4SAlex Deucher }; 51cc8dbbb4SAlex Deucher 52cc8dbbb4SAlex Deucher struct ci_dpm_level { 53cc8dbbb4SAlex Deucher bool enabled; 54cc8dbbb4SAlex Deucher u32 value; 55cc8dbbb4SAlex Deucher u32 param1; 56cc8dbbb4SAlex Deucher }; 57cc8dbbb4SAlex Deucher 58cc8dbbb4SAlex Deucher #define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5 59cc8dbbb4SAlex Deucher #define MAX_REGULAR_DPM_NUMBER 8 60cc8dbbb4SAlex Deucher #define CISLAND_MINIMUM_ENGINE_CLOCK 800 61cc8dbbb4SAlex Deucher 62cc8dbbb4SAlex Deucher struct ci_single_dpm_table { 63cc8dbbb4SAlex Deucher u32 count; 64cc8dbbb4SAlex Deucher struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 65cc8dbbb4SAlex Deucher }; 66cc8dbbb4SAlex Deucher 67cc8dbbb4SAlex Deucher struct ci_dpm_table { 68cc8dbbb4SAlex Deucher struct ci_single_dpm_table sclk_table; 69cc8dbbb4SAlex Deucher struct ci_single_dpm_table mclk_table; 70cc8dbbb4SAlex Deucher struct ci_single_dpm_table pcie_speed_table; 71cc8dbbb4SAlex Deucher struct ci_single_dpm_table vddc_table; 72cc8dbbb4SAlex Deucher struct ci_single_dpm_table vddci_table; 73cc8dbbb4SAlex Deucher struct ci_single_dpm_table mvdd_table; 74cc8dbbb4SAlex Deucher }; 75cc8dbbb4SAlex Deucher 76cc8dbbb4SAlex Deucher struct ci_mc_reg_entry { 77cc8dbbb4SAlex Deucher u32 mclk_max; 78cc8dbbb4SAlex Deucher u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 79cc8dbbb4SAlex Deucher }; 80cc8dbbb4SAlex Deucher 81cc8dbbb4SAlex Deucher struct ci_mc_reg_table { 82cc8dbbb4SAlex Deucher u8 last; 83cc8dbbb4SAlex Deucher u8 num_entries; 84cc8dbbb4SAlex Deucher u16 valid_flag; 85cc8dbbb4SAlex Deucher struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES]; 86cc8dbbb4SAlex Deucher SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 87cc8dbbb4SAlex Deucher }; 88cc8dbbb4SAlex Deucher 89cc8dbbb4SAlex Deucher struct ci_ulv_parm 90cc8dbbb4SAlex Deucher { 91cc8dbbb4SAlex Deucher bool supported; 92cc8dbbb4SAlex Deucher u32 cg_ulv_parameter; 93cc8dbbb4SAlex Deucher u32 volt_change_delay; 94cc8dbbb4SAlex Deucher struct ci_pl pl; 95cc8dbbb4SAlex Deucher }; 96cc8dbbb4SAlex Deucher 97cc8dbbb4SAlex Deucher #define CISLANDS_MAX_LEAKAGE_COUNT 8 98cc8dbbb4SAlex Deucher 99cc8dbbb4SAlex Deucher struct ci_leakage_voltage { 100cc8dbbb4SAlex Deucher u16 count; 101cc8dbbb4SAlex Deucher u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT]; 102cc8dbbb4SAlex Deucher u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT]; 103cc8dbbb4SAlex Deucher }; 104cc8dbbb4SAlex Deucher 105cc8dbbb4SAlex Deucher struct ci_dpm_level_enable_mask { 106cc8dbbb4SAlex Deucher u32 uvd_dpm_enable_mask; 107cc8dbbb4SAlex Deucher u32 vce_dpm_enable_mask; 108cc8dbbb4SAlex Deucher u32 acp_dpm_enable_mask; 109cc8dbbb4SAlex Deucher u32 samu_dpm_enable_mask; 110cc8dbbb4SAlex Deucher u32 sclk_dpm_enable_mask; 111cc8dbbb4SAlex Deucher u32 mclk_dpm_enable_mask; 112cc8dbbb4SAlex Deucher u32 pcie_dpm_enable_mask; 113cc8dbbb4SAlex Deucher }; 114cc8dbbb4SAlex Deucher 115cc8dbbb4SAlex Deucher struct ci_vbios_boot_state 116cc8dbbb4SAlex Deucher { 117cc8dbbb4SAlex Deucher u16 mvdd_bootup_value; 118cc8dbbb4SAlex Deucher u16 vddc_bootup_value; 119cc8dbbb4SAlex Deucher u16 vddci_bootup_value; 120cc8dbbb4SAlex Deucher u32 sclk_bootup_value; 121cc8dbbb4SAlex Deucher u32 mclk_bootup_value; 122cc8dbbb4SAlex Deucher u16 pcie_gen_bootup_value; 123cc8dbbb4SAlex Deucher u16 pcie_lane_bootup_value; 124cc8dbbb4SAlex Deucher }; 125cc8dbbb4SAlex Deucher 126cc8dbbb4SAlex Deucher struct ci_clock_registers { 127cc8dbbb4SAlex Deucher u32 cg_spll_func_cntl; 128cc8dbbb4SAlex Deucher u32 cg_spll_func_cntl_2; 129cc8dbbb4SAlex Deucher u32 cg_spll_func_cntl_3; 130cc8dbbb4SAlex Deucher u32 cg_spll_func_cntl_4; 131cc8dbbb4SAlex Deucher u32 cg_spll_spread_spectrum; 132cc8dbbb4SAlex Deucher u32 cg_spll_spread_spectrum_2; 133cc8dbbb4SAlex Deucher u32 dll_cntl; 134cc8dbbb4SAlex Deucher u32 mclk_pwrmgt_cntl; 135cc8dbbb4SAlex Deucher u32 mpll_ad_func_cntl; 136cc8dbbb4SAlex Deucher u32 mpll_dq_func_cntl; 137cc8dbbb4SAlex Deucher u32 mpll_func_cntl; 138cc8dbbb4SAlex Deucher u32 mpll_func_cntl_1; 139cc8dbbb4SAlex Deucher u32 mpll_func_cntl_2; 140cc8dbbb4SAlex Deucher u32 mpll_ss1; 141cc8dbbb4SAlex Deucher u32 mpll_ss2; 142cc8dbbb4SAlex Deucher }; 143cc8dbbb4SAlex Deucher 144cc8dbbb4SAlex Deucher struct ci_thermal_temperature_setting { 145cc8dbbb4SAlex Deucher s32 temperature_low; 146cc8dbbb4SAlex Deucher s32 temperature_high; 147cc8dbbb4SAlex Deucher s32 temperature_shutdown; 148cc8dbbb4SAlex Deucher }; 149cc8dbbb4SAlex Deucher 150cc8dbbb4SAlex Deucher struct ci_pcie_perf_range { 151cc8dbbb4SAlex Deucher u16 max; 152cc8dbbb4SAlex Deucher u16 min; 153cc8dbbb4SAlex Deucher }; 154cc8dbbb4SAlex Deucher 155cc8dbbb4SAlex Deucher enum ci_pt_config_reg_type { 156cc8dbbb4SAlex Deucher CISLANDS_CONFIGREG_MMR = 0, 157cc8dbbb4SAlex Deucher CISLANDS_CONFIGREG_SMC_IND, 158cc8dbbb4SAlex Deucher CISLANDS_CONFIGREG_DIDT_IND, 159cc8dbbb4SAlex Deucher CISLANDS_CONFIGREG_CACHE, 160cc8dbbb4SAlex Deucher CISLANDS_CONFIGREG_MAX 161cc8dbbb4SAlex Deucher }; 162cc8dbbb4SAlex Deucher 163cc8dbbb4SAlex Deucher #define POWERCONTAINMENT_FEATURE_BAPM 0x00000001 164cc8dbbb4SAlex Deucher #define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002 165cc8dbbb4SAlex Deucher #define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004 166cc8dbbb4SAlex Deucher 167cc8dbbb4SAlex Deucher struct ci_pt_config_reg { 168cc8dbbb4SAlex Deucher u32 offset; 169cc8dbbb4SAlex Deucher u32 mask; 170cc8dbbb4SAlex Deucher u32 shift; 171cc8dbbb4SAlex Deucher u32 value; 172cc8dbbb4SAlex Deucher enum ci_pt_config_reg_type type; 173cc8dbbb4SAlex Deucher }; 174cc8dbbb4SAlex Deucher 175cc8dbbb4SAlex Deucher struct ci_pt_defaults { 176cc8dbbb4SAlex Deucher u8 svi_load_line_en; 177cc8dbbb4SAlex Deucher u8 svi_load_line_vddc; 178cc8dbbb4SAlex Deucher u8 tdc_vddc_throttle_release_limit_perc; 179cc8dbbb4SAlex Deucher u8 tdc_mawt; 180cc8dbbb4SAlex Deucher u8 tdc_waterfall_ctl; 181cc8dbbb4SAlex Deucher u8 dte_ambient_temp_base; 182cc8dbbb4SAlex Deucher u32 display_cac; 183cc8dbbb4SAlex Deucher u32 bapm_temp_gradient; 184cc8dbbb4SAlex Deucher u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS]; 185cc8dbbb4SAlex Deucher u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS]; 186cc8dbbb4SAlex Deucher }; 187cc8dbbb4SAlex Deucher 188cc8dbbb4SAlex Deucher #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 189cc8dbbb4SAlex Deucher #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 190cc8dbbb4SAlex Deucher #define DPMTABLE_UPDATE_SCLK 0x00000004 191cc8dbbb4SAlex Deucher #define DPMTABLE_UPDATE_MCLK 0x00000008 192cc8dbbb4SAlex Deucher 193cc8dbbb4SAlex Deucher struct ci_power_info { 194cc8dbbb4SAlex Deucher struct ci_dpm_table dpm_table; 195cc8dbbb4SAlex Deucher u32 voltage_control; 196cc8dbbb4SAlex Deucher u32 mvdd_control; 197cc8dbbb4SAlex Deucher u32 vddci_control; 198cc8dbbb4SAlex Deucher u32 active_auto_throttle_sources; 199cc8dbbb4SAlex Deucher struct ci_clock_registers clock_registers; 200cc8dbbb4SAlex Deucher u16 acpi_vddc; 201cc8dbbb4SAlex Deucher u16 acpi_vddci; 202cc8dbbb4SAlex Deucher enum radeon_pcie_gen force_pcie_gen; 203cc8dbbb4SAlex Deucher enum radeon_pcie_gen acpi_pcie_gen; 204cc8dbbb4SAlex Deucher struct ci_leakage_voltage vddc_leakage; 205cc8dbbb4SAlex Deucher struct ci_leakage_voltage vddci_leakage; 206cc8dbbb4SAlex Deucher u16 max_vddc_in_pp_table; 207cc8dbbb4SAlex Deucher u16 min_vddc_in_pp_table; 208cc8dbbb4SAlex Deucher u16 max_vddci_in_pp_table; 209cc8dbbb4SAlex Deucher u16 min_vddci_in_pp_table; 210cc8dbbb4SAlex Deucher u32 mclk_strobe_mode_threshold; 211cc8dbbb4SAlex Deucher u32 mclk_stutter_mode_threshold; 212cc8dbbb4SAlex Deucher u32 mclk_edc_enable_threshold; 213cc8dbbb4SAlex Deucher u32 mclk_edc_wr_enable_threshold; 214cc8dbbb4SAlex Deucher struct ci_vbios_boot_state vbios_boot_state; 215cc8dbbb4SAlex Deucher /* smc offsets */ 216cc8dbbb4SAlex Deucher u32 sram_end; 217cc8dbbb4SAlex Deucher u32 dpm_table_start; 218cc8dbbb4SAlex Deucher u32 soft_regs_start; 219cc8dbbb4SAlex Deucher u32 mc_reg_table_start; 220cc8dbbb4SAlex Deucher u32 fan_table_start; 221cc8dbbb4SAlex Deucher u32 arb_table_start; 222cc8dbbb4SAlex Deucher /* smc tables */ 223cc8dbbb4SAlex Deucher SMU7_Discrete_DpmTable smc_state_table; 224cc8dbbb4SAlex Deucher SMU7_Discrete_MCRegisters smc_mc_reg_table; 225cc8dbbb4SAlex Deucher SMU7_Discrete_PmFuses smc_powertune_table; 226cc8dbbb4SAlex Deucher /* other stuff */ 227cc8dbbb4SAlex Deucher struct ci_mc_reg_table mc_reg_table; 228cc8dbbb4SAlex Deucher struct atom_voltage_table vddc_voltage_table; 229cc8dbbb4SAlex Deucher struct atom_voltage_table vddci_voltage_table; 230cc8dbbb4SAlex Deucher struct atom_voltage_table mvdd_voltage_table; 231cc8dbbb4SAlex Deucher struct ci_ulv_parm ulv; 232cc8dbbb4SAlex Deucher u32 power_containment_features; 233cc8dbbb4SAlex Deucher const struct ci_pt_defaults *powertune_defaults; 234cc8dbbb4SAlex Deucher u32 dte_tj_offset; 235cc8dbbb4SAlex Deucher bool vddc_phase_shed_control; 236cc8dbbb4SAlex Deucher struct ci_thermal_temperature_setting thermal_temp_setting; 237cc8dbbb4SAlex Deucher struct ci_dpm_level_enable_mask dpm_level_enable_mask; 238cc8dbbb4SAlex Deucher u32 need_update_smu7_dpm_table; 239cc8dbbb4SAlex Deucher u32 sclk_dpm_key_disabled; 240cc8dbbb4SAlex Deucher u32 mclk_dpm_key_disabled; 241cc8dbbb4SAlex Deucher u32 pcie_dpm_key_disabled; 242cc8dbbb4SAlex Deucher struct ci_pcie_perf_range pcie_gen_performance; 243cc8dbbb4SAlex Deucher struct ci_pcie_perf_range pcie_lane_performance; 244cc8dbbb4SAlex Deucher struct ci_pcie_perf_range pcie_gen_powersaving; 245cc8dbbb4SAlex Deucher struct ci_pcie_perf_range pcie_lane_powersaving; 246cc8dbbb4SAlex Deucher u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS]; 247cc8dbbb4SAlex Deucher u32 mclk_activity_target; 248cc8dbbb4SAlex Deucher u32 low_sclk_interrupt_t; 249cc8dbbb4SAlex Deucher u32 last_mclk_dpm_enable_mask; 250cc8dbbb4SAlex Deucher u32 sys_pcie_mask; 251cc8dbbb4SAlex Deucher /* caps */ 252cc8dbbb4SAlex Deucher bool caps_power_containment; 253cc8dbbb4SAlex Deucher bool caps_cac; 254cc8dbbb4SAlex Deucher bool caps_sq_ramping; 255cc8dbbb4SAlex Deucher bool caps_db_ramping; 256cc8dbbb4SAlex Deucher bool caps_td_ramping; 257cc8dbbb4SAlex Deucher bool caps_tcp_ramping; 258cc8dbbb4SAlex Deucher bool caps_fps; 259cc8dbbb4SAlex Deucher bool caps_sclk_ds; 260cc8dbbb4SAlex Deucher bool caps_sclk_ss_support; 261cc8dbbb4SAlex Deucher bool caps_mclk_ss_support; 262cc8dbbb4SAlex Deucher bool caps_uvd_dpm; 263cc8dbbb4SAlex Deucher bool caps_vce_dpm; 264cc8dbbb4SAlex Deucher bool caps_samu_dpm; 265cc8dbbb4SAlex Deucher bool caps_acp_dpm; 266cc8dbbb4SAlex Deucher bool caps_automatic_dc_transition; 267cc8dbbb4SAlex Deucher bool caps_sclk_throttle_low_notification; 268cc8dbbb4SAlex Deucher bool caps_dynamic_ac_timing; 269cc8dbbb4SAlex Deucher /* flags */ 270cc8dbbb4SAlex Deucher bool thermal_protection; 271cc8dbbb4SAlex Deucher bool pcie_performance_request; 272cc8dbbb4SAlex Deucher bool dynamic_ss; 273cc8dbbb4SAlex Deucher bool dll_default_on; 274cc8dbbb4SAlex Deucher bool cac_enabled; 275cc8dbbb4SAlex Deucher bool uvd_enabled; 276cc8dbbb4SAlex Deucher bool battery_state; 277cc8dbbb4SAlex Deucher bool pspp_notify_required; 278cc8dbbb4SAlex Deucher bool mem_gddr5; 279cc8dbbb4SAlex Deucher bool enable_bapm_feature; 280cc8dbbb4SAlex Deucher bool enable_tdc_limit_feature; 281cc8dbbb4SAlex Deucher bool enable_pkg_pwr_tracking_feature; 282cc8dbbb4SAlex Deucher bool use_pcie_performance_levels; 283cc8dbbb4SAlex Deucher bool use_pcie_powersaving_levels; 28447acb1ffSAlex Deucher bool uvd_power_gated; 285cc8dbbb4SAlex Deucher /* driver states */ 286cc8dbbb4SAlex Deucher struct radeon_ps current_rps; 287cc8dbbb4SAlex Deucher struct ci_ps current_ps; 288cc8dbbb4SAlex Deucher struct radeon_ps requested_rps; 289cc8dbbb4SAlex Deucher struct ci_ps requested_ps; 290cc8dbbb4SAlex Deucher }; 291cc8dbbb4SAlex Deucher 292cc8dbbb4SAlex Deucher #define CISLANDS_VOLTAGE_CONTROL_NONE 0x0 293cc8dbbb4SAlex Deucher #define CISLANDS_VOLTAGE_CONTROL_BY_GPIO 0x1 294cc8dbbb4SAlex Deucher #define CISLANDS_VOLTAGE_CONTROL_BY_SVID2 0x2 295cc8dbbb4SAlex Deucher 296cc8dbbb4SAlex Deucher #define CISLANDS_Q88_FORMAT_CONVERSION_UNIT 256 297cc8dbbb4SAlex Deucher 298cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT0 0x3FFFC000 299cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT1 0x000400 300cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT2 0xC00080 301cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT3 0xC00200 302cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT4 0xC01680 303cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT5 0xC00033 304cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT6 0xC00033 305cc8dbbb4SAlex Deucher #define CISLANDS_VRC_DFLT7 0x3FFFC000 306cc8dbbb4SAlex Deucher 307cc8dbbb4SAlex Deucher #define CISLANDS_CGULVPARAMETER_DFLT 0x00040035 308cc8dbbb4SAlex Deucher #define CISLAND_TARGETACTIVITY_DFLT 30 309cc8dbbb4SAlex Deucher #define CISLAND_MCLK_TARGETACTIVITY_DFLT 10 310cc8dbbb4SAlex Deucher 311cc8dbbb4SAlex Deucher #define PCIE_PERF_REQ_REMOVE_REGISTRY 0 312cc8dbbb4SAlex Deucher #define PCIE_PERF_REQ_FORCE_LOWPOWER 1 313cc8dbbb4SAlex Deucher #define PCIE_PERF_REQ_PECI_GEN1 2 314cc8dbbb4SAlex Deucher #define PCIE_PERF_REQ_PECI_GEN2 3 315cc8dbbb4SAlex Deucher #define PCIE_PERF_REQ_PECI_GEN3 4 316cc8dbbb4SAlex Deucher 317cc8dbbb4SAlex Deucher int ci_copy_bytes_to_smc(struct radeon_device *rdev, 318cc8dbbb4SAlex Deucher u32 smc_start_address, 319cc8dbbb4SAlex Deucher const u8 *src, u32 byte_count, u32 limit); 320cc8dbbb4SAlex Deucher void ci_start_smc(struct radeon_device *rdev); 321cc8dbbb4SAlex Deucher void ci_reset_smc(struct radeon_device *rdev); 322cc8dbbb4SAlex Deucher int ci_program_jump_on_start(struct radeon_device *rdev); 323cc8dbbb4SAlex Deucher void ci_stop_smc_clock(struct radeon_device *rdev); 324cc8dbbb4SAlex Deucher void ci_start_smc_clock(struct radeon_device *rdev); 325cc8dbbb4SAlex Deucher bool ci_is_smc_running(struct radeon_device *rdev); 326cc8dbbb4SAlex Deucher PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg); 327cc8dbbb4SAlex Deucher PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev); 328cc8dbbb4SAlex Deucher int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit); 329cc8dbbb4SAlex Deucher int ci_read_smc_sram_dword(struct radeon_device *rdev, 330cc8dbbb4SAlex Deucher u32 smc_address, u32 *value, u32 limit); 331cc8dbbb4SAlex Deucher int ci_write_smc_sram_dword(struct radeon_device *rdev, 332cc8dbbb4SAlex Deucher u32 smc_address, u32 value, u32 limit); 333cc8dbbb4SAlex Deucher 334cc8dbbb4SAlex Deucher #endif 335