1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "drm_crtc_helper.h" 28 #include "radeon_drm.h" 29 #include "radeon.h" 30 #include "atom.h" 31 32 extern int atom_debug; 33 34 /* evil but including atombios.h is much worse */ 35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 36 struct drm_display_mode *mode); 37 38 39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) 40 { 41 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 42 switch (radeon_encoder->encoder_id) { 43 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 44 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 45 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 46 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 47 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 48 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 49 case ENCODER_OBJECT_ID_INTERNAL_DDI: 50 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 51 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 52 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 53 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 54 return true; 55 default: 56 return false; 57 } 58 } 59 60 static struct drm_connector * 61 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder) 62 { 63 struct drm_device *dev = encoder->dev; 64 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 65 struct drm_connector *connector; 66 struct radeon_connector *radeon_connector; 67 68 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 69 radeon_connector = to_radeon_connector(connector); 70 if (radeon_encoder->devices & radeon_connector->devices) 71 return connector; 72 } 73 return NULL; 74 } 75 76 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 77 struct drm_display_mode *mode, 78 struct drm_display_mode *adjusted_mode) 79 { 80 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 81 struct drm_device *dev = encoder->dev; 82 struct radeon_device *rdev = dev->dev_private; 83 84 /* set the active encoder to connector routing */ 85 radeon_encoder_set_active_device(encoder); 86 drm_mode_set_crtcinfo(adjusted_mode, 0); 87 88 /* hw bug */ 89 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 90 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 91 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 92 93 /* get the native mode for LVDS */ 94 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 95 radeon_panel_mode_fixup(encoder, adjusted_mode); 96 97 /* get the native mode for TV */ 98 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 99 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 100 if (tv_dac) { 101 if (tv_dac->tv_std == TV_STD_NTSC || 102 tv_dac->tv_std == TV_STD_NTSC_J || 103 tv_dac->tv_std == TV_STD_PAL_M) 104 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 105 else 106 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 107 } 108 } 109 110 if (ASIC_IS_DCE3(rdev) && 111 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 112 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 113 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 114 radeon_dp_set_link_config(connector, mode); 115 } 116 117 return true; 118 } 119 120 static void 121 atombios_dac_setup(struct drm_encoder *encoder, int action) 122 { 123 struct drm_device *dev = encoder->dev; 124 struct radeon_device *rdev = dev->dev_private; 125 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 126 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 127 int index = 0; 128 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 129 130 memset(&args, 0, sizeof(args)); 131 132 switch (radeon_encoder->encoder_id) { 133 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 134 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 135 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 136 break; 137 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 139 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 140 break; 141 } 142 143 args.ucAction = action; 144 145 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 146 args.ucDacStandard = ATOM_DAC1_PS2; 147 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 148 args.ucDacStandard = ATOM_DAC1_CV; 149 else { 150 switch (dac_info->tv_std) { 151 case TV_STD_PAL: 152 case TV_STD_PAL_M: 153 case TV_STD_SCART_PAL: 154 case TV_STD_SECAM: 155 case TV_STD_PAL_CN: 156 args.ucDacStandard = ATOM_DAC1_PAL; 157 break; 158 case TV_STD_NTSC: 159 case TV_STD_NTSC_J: 160 case TV_STD_PAL_60: 161 default: 162 args.ucDacStandard = ATOM_DAC1_NTSC; 163 break; 164 } 165 } 166 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 167 168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 169 170 } 171 172 static void 173 atombios_tv_setup(struct drm_encoder *encoder, int action) 174 { 175 struct drm_device *dev = encoder->dev; 176 struct radeon_device *rdev = dev->dev_private; 177 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 178 TV_ENCODER_CONTROL_PS_ALLOCATION args; 179 int index = 0; 180 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 181 182 memset(&args, 0, sizeof(args)); 183 184 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 185 186 args.sTVEncoder.ucAction = action; 187 188 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 189 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 190 else { 191 switch (dac_info->tv_std) { 192 case TV_STD_NTSC: 193 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 194 break; 195 case TV_STD_PAL: 196 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 197 break; 198 case TV_STD_PAL_M: 199 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 200 break; 201 case TV_STD_PAL_60: 202 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 203 break; 204 case TV_STD_NTSC_J: 205 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 206 break; 207 case TV_STD_SCART_PAL: 208 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 209 break; 210 case TV_STD_SECAM: 211 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 212 break; 213 case TV_STD_PAL_CN: 214 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 215 break; 216 default: 217 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 218 break; 219 } 220 } 221 222 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 223 224 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 225 226 } 227 228 union dvo_encoder_control { 229 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 230 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 231 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 232 }; 233 234 void 235 atombios_dvo_setup(struct drm_encoder *encoder, int action) 236 { 237 struct drm_device *dev = encoder->dev; 238 struct radeon_device *rdev = dev->dev_private; 239 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 240 union dvo_encoder_control args; 241 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 242 uint8_t frev, crev; 243 244 memset(&args, 0, sizeof(args)); 245 246 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 247 return; 248 249 switch (frev) { 250 case 1: 251 switch (crev) { 252 case 1: 253 /* R4xx, R5xx */ 254 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 255 256 if (radeon_encoder->pixel_clock > 165000) 257 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 258 259 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 260 break; 261 case 2: 262 /* RS600/690/740 */ 263 args.dvo.sDVOEncoder.ucAction = action; 264 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 265 /* DFP1, CRT1, TV1 depending on the type of port */ 266 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 267 268 if (radeon_encoder->pixel_clock > 165000) 269 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 270 break; 271 case 3: 272 /* R6xx */ 273 args.dvo_v3.ucAction = action; 274 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 275 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 276 break; 277 default: 278 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 279 break; 280 } 281 break; 282 default: 283 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 284 break; 285 } 286 287 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 288 } 289 290 union lvds_encoder_control { 291 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 292 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 293 }; 294 295 void 296 atombios_digital_setup(struct drm_encoder *encoder, int action) 297 { 298 struct drm_device *dev = encoder->dev; 299 struct radeon_device *rdev = dev->dev_private; 300 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 301 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 302 union lvds_encoder_control args; 303 int index = 0; 304 int hdmi_detected = 0; 305 uint8_t frev, crev; 306 307 if (!dig) 308 return; 309 310 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 311 hdmi_detected = 1; 312 313 memset(&args, 0, sizeof(args)); 314 315 switch (radeon_encoder->encoder_id) { 316 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 317 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 318 break; 319 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 320 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 321 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 322 break; 323 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 324 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 325 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 326 else 327 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 328 break; 329 } 330 331 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 332 return; 333 334 switch (frev) { 335 case 1: 336 case 2: 337 switch (crev) { 338 case 1: 339 args.v1.ucMisc = 0; 340 args.v1.ucAction = action; 341 if (hdmi_detected) 342 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 343 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 344 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 345 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 346 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 347 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 348 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 349 } else { 350 if (dig->linkb) 351 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 352 if (radeon_encoder->pixel_clock > 165000) 353 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 354 /*if (pScrn->rgbBits == 8) */ 355 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 356 } 357 break; 358 case 2: 359 case 3: 360 args.v2.ucMisc = 0; 361 args.v2.ucAction = action; 362 if (crev == 3) { 363 if (dig->coherent_mode) 364 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 365 } 366 if (hdmi_detected) 367 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 368 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 369 args.v2.ucTruncate = 0; 370 args.v2.ucSpatial = 0; 371 args.v2.ucTemporal = 0; 372 args.v2.ucFRC = 0; 373 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 374 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 375 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 376 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 377 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 378 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 379 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 380 } 381 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 382 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 383 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 384 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 385 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 386 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 387 } 388 } else { 389 if (dig->linkb) 390 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 391 if (radeon_encoder->pixel_clock > 165000) 392 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 393 } 394 break; 395 default: 396 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 397 break; 398 } 399 break; 400 default: 401 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 402 break; 403 } 404 405 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 406 } 407 408 int 409 atombios_get_encoder_mode(struct drm_encoder *encoder) 410 { 411 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 412 struct drm_device *dev = encoder->dev; 413 struct radeon_device *rdev = dev->dev_private; 414 struct drm_connector *connector; 415 struct radeon_connector *radeon_connector; 416 struct radeon_connector_atom_dig *dig_connector; 417 418 /* dp bridges are always DP */ 419 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 420 return ATOM_ENCODER_MODE_DP; 421 422 /* DVO is always DVO */ 423 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO) 424 return ATOM_ENCODER_MODE_DVO; 425 426 connector = radeon_get_connector_for_encoder(encoder); 427 /* if we don't have an active device yet, just use one of 428 * the connectors tied to the encoder. 429 */ 430 if (!connector) 431 connector = radeon_get_connector_for_encoder_init(encoder); 432 radeon_connector = to_radeon_connector(connector); 433 434 switch (connector->connector_type) { 435 case DRM_MODE_CONNECTOR_DVII: 436 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 437 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { 438 /* fix me */ 439 if (ASIC_IS_DCE4(rdev)) 440 return ATOM_ENCODER_MODE_DVI; 441 else 442 return ATOM_ENCODER_MODE_HDMI; 443 } else if (radeon_connector->use_digital) 444 return ATOM_ENCODER_MODE_DVI; 445 else 446 return ATOM_ENCODER_MODE_CRT; 447 break; 448 case DRM_MODE_CONNECTOR_DVID: 449 case DRM_MODE_CONNECTOR_HDMIA: 450 default: 451 if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { 452 /* fix me */ 453 if (ASIC_IS_DCE4(rdev)) 454 return ATOM_ENCODER_MODE_DVI; 455 else 456 return ATOM_ENCODER_MODE_HDMI; 457 } else 458 return ATOM_ENCODER_MODE_DVI; 459 break; 460 case DRM_MODE_CONNECTOR_LVDS: 461 return ATOM_ENCODER_MODE_LVDS; 462 break; 463 case DRM_MODE_CONNECTOR_DisplayPort: 464 dig_connector = radeon_connector->con_priv; 465 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 466 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 467 return ATOM_ENCODER_MODE_DP; 468 else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { 469 /* fix me */ 470 if (ASIC_IS_DCE4(rdev)) 471 return ATOM_ENCODER_MODE_DVI; 472 else 473 return ATOM_ENCODER_MODE_HDMI; 474 } else 475 return ATOM_ENCODER_MODE_DVI; 476 break; 477 case DRM_MODE_CONNECTOR_eDP: 478 return ATOM_ENCODER_MODE_DP; 479 case DRM_MODE_CONNECTOR_DVIA: 480 case DRM_MODE_CONNECTOR_VGA: 481 return ATOM_ENCODER_MODE_CRT; 482 break; 483 case DRM_MODE_CONNECTOR_Composite: 484 case DRM_MODE_CONNECTOR_SVIDEO: 485 case DRM_MODE_CONNECTOR_9PinDIN: 486 /* fix me */ 487 return ATOM_ENCODER_MODE_TV; 488 /*return ATOM_ENCODER_MODE_CV;*/ 489 break; 490 } 491 } 492 493 /* 494 * DIG Encoder/Transmitter Setup 495 * 496 * DCE 3.0/3.1 497 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 498 * Supports up to 3 digital outputs 499 * - 2 DIG encoder blocks. 500 * DIG1 can drive UNIPHY link A or link B 501 * DIG2 can drive UNIPHY link B or LVTMA 502 * 503 * DCE 3.2 504 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 505 * Supports up to 5 digital outputs 506 * - 2 DIG encoder blocks. 507 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 508 * 509 * DCE 4.0/5.0 510 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 511 * Supports up to 6 digital outputs 512 * - 6 DIG encoder blocks. 513 * - DIG to PHY mapping is hardcoded 514 * DIG1 drives UNIPHY0 link A, A+B 515 * DIG2 drives UNIPHY0 link B 516 * DIG3 drives UNIPHY1 link A, A+B 517 * DIG4 drives UNIPHY1 link B 518 * DIG5 drives UNIPHY2 link A, A+B 519 * DIG6 drives UNIPHY2 link B 520 * 521 * DCE 4.1 522 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 523 * Supports up to 6 digital outputs 524 * - 2 DIG encoder blocks. 525 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 526 * 527 * Routing 528 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 529 * Examples: 530 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 531 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 532 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 533 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 534 */ 535 536 union dig_encoder_control { 537 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 538 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 539 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 540 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 541 }; 542 543 void 544 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 545 { 546 struct drm_device *dev = encoder->dev; 547 struct radeon_device *rdev = dev->dev_private; 548 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 549 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 550 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 551 union dig_encoder_control args; 552 int index = 0; 553 uint8_t frev, crev; 554 int dp_clock = 0; 555 int dp_lane_count = 0; 556 int hpd_id = RADEON_HPD_NONE; 557 int bpc = 8; 558 559 if (connector) { 560 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 561 struct radeon_connector_atom_dig *dig_connector = 562 radeon_connector->con_priv; 563 564 dp_clock = dig_connector->dp_clock; 565 dp_lane_count = dig_connector->dp_lane_count; 566 hpd_id = radeon_connector->hpd.hpd; 567 bpc = connector->display_info.bpc; 568 } 569 570 /* no dig encoder assigned */ 571 if (dig->dig_encoder == -1) 572 return; 573 574 memset(&args, 0, sizeof(args)); 575 576 if (ASIC_IS_DCE4(rdev)) 577 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 578 else { 579 if (dig->dig_encoder) 580 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 581 else 582 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 583 } 584 585 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 586 return; 587 588 switch (frev) { 589 case 1: 590 switch (crev) { 591 case 1: 592 args.v1.ucAction = action; 593 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 594 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 595 args.v3.ucPanelMode = panel_mode; 596 else 597 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 598 599 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 600 args.v1.ucLaneNum = dp_lane_count; 601 else if (radeon_encoder->pixel_clock > 165000) 602 args.v1.ucLaneNum = 8; 603 else 604 args.v1.ucLaneNum = 4; 605 606 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 607 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 608 switch (radeon_encoder->encoder_id) { 609 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 610 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 611 break; 612 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 613 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 614 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 615 break; 616 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 617 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 618 break; 619 } 620 if (dig->linkb) 621 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 622 else 623 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 624 break; 625 case 2: 626 case 3: 627 args.v3.ucAction = action; 628 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 629 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 630 args.v3.ucPanelMode = panel_mode; 631 else 632 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 633 634 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 635 args.v3.ucLaneNum = dp_lane_count; 636 else if (radeon_encoder->pixel_clock > 165000) 637 args.v3.ucLaneNum = 8; 638 else 639 args.v3.ucLaneNum = 4; 640 641 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 642 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 643 args.v3.acConfig.ucDigSel = dig->dig_encoder; 644 switch (bpc) { 645 case 0: 646 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE; 647 break; 648 case 6: 649 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR; 650 break; 651 case 8: 652 default: 653 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; 654 break; 655 case 10: 656 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR; 657 break; 658 case 12: 659 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR; 660 break; 661 case 16: 662 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR; 663 break; 664 } 665 break; 666 case 4: 667 args.v4.ucAction = action; 668 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 669 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 670 args.v4.ucPanelMode = panel_mode; 671 else 672 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 673 674 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 675 args.v4.ucLaneNum = dp_lane_count; 676 else if (radeon_encoder->pixel_clock > 165000) 677 args.v4.ucLaneNum = 8; 678 else 679 args.v4.ucLaneNum = 4; 680 681 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) { 682 if (dp_clock == 270000) 683 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 684 else if (dp_clock == 540000) 685 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 686 } 687 args.v4.acConfig.ucDigSel = dig->dig_encoder; 688 switch (bpc) { 689 case 0: 690 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE; 691 break; 692 case 6: 693 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR; 694 break; 695 case 8: 696 default: 697 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; 698 break; 699 case 10: 700 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR; 701 break; 702 case 12: 703 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR; 704 break; 705 case 16: 706 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR; 707 break; 708 } 709 if (hpd_id == RADEON_HPD_NONE) 710 args.v4.ucHPD_ID = 0; 711 else 712 args.v4.ucHPD_ID = hpd_id + 1; 713 break; 714 default: 715 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 716 break; 717 } 718 break; 719 default: 720 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 721 break; 722 } 723 724 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 725 726 } 727 728 union dig_transmitter_control { 729 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 730 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 731 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 732 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 733 }; 734 735 void 736 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 737 { 738 struct drm_device *dev = encoder->dev; 739 struct radeon_device *rdev = dev->dev_private; 740 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 741 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 742 struct drm_connector *connector; 743 union dig_transmitter_control args; 744 int index = 0; 745 uint8_t frev, crev; 746 bool is_dp = false; 747 int pll_id = 0; 748 int dp_clock = 0; 749 int dp_lane_count = 0; 750 int connector_object_id = 0; 751 int igp_lane_info = 0; 752 int dig_encoder = dig->dig_encoder; 753 754 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 755 connector = radeon_get_connector_for_encoder_init(encoder); 756 /* just needed to avoid bailing in the encoder check. the encoder 757 * isn't used for init 758 */ 759 dig_encoder = 0; 760 } else 761 connector = radeon_get_connector_for_encoder(encoder); 762 763 if (connector) { 764 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 765 struct radeon_connector_atom_dig *dig_connector = 766 radeon_connector->con_priv; 767 768 dp_clock = dig_connector->dp_clock; 769 dp_lane_count = dig_connector->dp_lane_count; 770 connector_object_id = 771 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 772 igp_lane_info = dig_connector->igp_lane_info; 773 } 774 775 if (encoder->crtc) { 776 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 777 pll_id = radeon_crtc->pll_id; 778 } 779 780 /* no dig encoder assigned */ 781 if (dig_encoder == -1) 782 return; 783 784 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 785 is_dp = true; 786 787 memset(&args, 0, sizeof(args)); 788 789 switch (radeon_encoder->encoder_id) { 790 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 791 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 792 break; 793 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 794 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 795 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 796 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 797 break; 798 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 799 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 800 break; 801 } 802 803 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 804 return; 805 806 switch (frev) { 807 case 1: 808 switch (crev) { 809 case 1: 810 args.v1.ucAction = action; 811 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 812 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 813 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 814 args.v1.asMode.ucLaneSel = lane_num; 815 args.v1.asMode.ucLaneSet = lane_set; 816 } else { 817 if (is_dp) 818 args.v1.usPixelClock = 819 cpu_to_le16(dp_clock / 10); 820 else if (radeon_encoder->pixel_clock > 165000) 821 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 822 else 823 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 824 } 825 826 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 827 828 if (dig_encoder) 829 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 830 else 831 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 832 833 if ((rdev->flags & RADEON_IS_IGP) && 834 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 835 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { 836 if (igp_lane_info & 0x1) 837 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 838 else if (igp_lane_info & 0x2) 839 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 840 else if (igp_lane_info & 0x4) 841 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 842 else if (igp_lane_info & 0x8) 843 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 844 } else { 845 if (igp_lane_info & 0x3) 846 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 847 else if (igp_lane_info & 0xc) 848 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 849 } 850 } 851 852 if (dig->linkb) 853 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 854 else 855 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 856 857 if (is_dp) 858 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 859 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 860 if (dig->coherent_mode) 861 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 862 if (radeon_encoder->pixel_clock > 165000) 863 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 864 } 865 break; 866 case 2: 867 args.v2.ucAction = action; 868 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 869 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 870 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 871 args.v2.asMode.ucLaneSel = lane_num; 872 args.v2.asMode.ucLaneSet = lane_set; 873 } else { 874 if (is_dp) 875 args.v2.usPixelClock = 876 cpu_to_le16(dp_clock / 10); 877 else if (radeon_encoder->pixel_clock > 165000) 878 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 879 else 880 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 881 } 882 883 args.v2.acConfig.ucEncoderSel = dig_encoder; 884 if (dig->linkb) 885 args.v2.acConfig.ucLinkSel = 1; 886 887 switch (radeon_encoder->encoder_id) { 888 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 889 args.v2.acConfig.ucTransmitterSel = 0; 890 break; 891 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 892 args.v2.acConfig.ucTransmitterSel = 1; 893 break; 894 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 895 args.v2.acConfig.ucTransmitterSel = 2; 896 break; 897 } 898 899 if (is_dp) { 900 args.v2.acConfig.fCoherentMode = 1; 901 args.v2.acConfig.fDPConnector = 1; 902 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 903 if (dig->coherent_mode) 904 args.v2.acConfig.fCoherentMode = 1; 905 if (radeon_encoder->pixel_clock > 165000) 906 args.v2.acConfig.fDualLinkConnector = 1; 907 } 908 break; 909 case 3: 910 args.v3.ucAction = action; 911 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 912 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 913 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 914 args.v3.asMode.ucLaneSel = lane_num; 915 args.v3.asMode.ucLaneSet = lane_set; 916 } else { 917 if (is_dp) 918 args.v3.usPixelClock = 919 cpu_to_le16(dp_clock / 10); 920 else if (radeon_encoder->pixel_clock > 165000) 921 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 922 else 923 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 924 } 925 926 if (is_dp) 927 args.v3.ucLaneNum = dp_lane_count; 928 else if (radeon_encoder->pixel_clock > 165000) 929 args.v3.ucLaneNum = 8; 930 else 931 args.v3.ucLaneNum = 4; 932 933 if (dig->linkb) 934 args.v3.acConfig.ucLinkSel = 1; 935 if (dig_encoder & 1) 936 args.v3.acConfig.ucEncoderSel = 1; 937 938 /* Select the PLL for the PHY 939 * DP PHY should be clocked from external src if there is 940 * one. 941 */ 942 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 943 if (is_dp && rdev->clock.dp_extclk) 944 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 945 else 946 args.v3.acConfig.ucRefClkSource = pll_id; 947 948 switch (radeon_encoder->encoder_id) { 949 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 950 args.v3.acConfig.ucTransmitterSel = 0; 951 break; 952 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 953 args.v3.acConfig.ucTransmitterSel = 1; 954 break; 955 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 956 args.v3.acConfig.ucTransmitterSel = 2; 957 break; 958 } 959 960 if (is_dp) 961 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 962 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 963 if (dig->coherent_mode) 964 args.v3.acConfig.fCoherentMode = 1; 965 if (radeon_encoder->pixel_clock > 165000) 966 args.v3.acConfig.fDualLinkConnector = 1; 967 } 968 break; 969 case 4: 970 args.v4.ucAction = action; 971 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 972 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 973 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 974 args.v4.asMode.ucLaneSel = lane_num; 975 args.v4.asMode.ucLaneSet = lane_set; 976 } else { 977 if (is_dp) 978 args.v4.usPixelClock = 979 cpu_to_le16(dp_clock / 10); 980 else if (radeon_encoder->pixel_clock > 165000) 981 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 982 else 983 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 984 } 985 986 if (is_dp) 987 args.v4.ucLaneNum = dp_lane_count; 988 else if (radeon_encoder->pixel_clock > 165000) 989 args.v4.ucLaneNum = 8; 990 else 991 args.v4.ucLaneNum = 4; 992 993 if (dig->linkb) 994 args.v4.acConfig.ucLinkSel = 1; 995 if (dig_encoder & 1) 996 args.v4.acConfig.ucEncoderSel = 1; 997 998 /* Select the PLL for the PHY 999 * DP PHY should be clocked from external src if there is 1000 * one. 1001 */ 1002 /* On DCE5 DCPLL usually generates the DP ref clock */ 1003 if (is_dp) { 1004 if (rdev->clock.dp_extclk) 1005 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1006 else 1007 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1008 } else 1009 args.v4.acConfig.ucRefClkSource = pll_id; 1010 1011 switch (radeon_encoder->encoder_id) { 1012 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1013 args.v4.acConfig.ucTransmitterSel = 0; 1014 break; 1015 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1016 args.v4.acConfig.ucTransmitterSel = 1; 1017 break; 1018 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1019 args.v4.acConfig.ucTransmitterSel = 2; 1020 break; 1021 } 1022 1023 if (is_dp) 1024 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1025 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1026 if (dig->coherent_mode) 1027 args.v4.acConfig.fCoherentMode = 1; 1028 if (radeon_encoder->pixel_clock > 165000) 1029 args.v4.acConfig.fDualLinkConnector = 1; 1030 } 1031 break; 1032 default: 1033 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1034 break; 1035 } 1036 break; 1037 default: 1038 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1039 break; 1040 } 1041 1042 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1043 } 1044 1045 bool 1046 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1047 { 1048 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1049 struct drm_device *dev = radeon_connector->base.dev; 1050 struct radeon_device *rdev = dev->dev_private; 1051 union dig_transmitter_control args; 1052 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1053 uint8_t frev, crev; 1054 1055 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1056 goto done; 1057 1058 if (!ASIC_IS_DCE4(rdev)) 1059 goto done; 1060 1061 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1062 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1063 goto done; 1064 1065 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1066 goto done; 1067 1068 memset(&args, 0, sizeof(args)); 1069 1070 args.v1.ucAction = action; 1071 1072 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1073 1074 /* wait for the panel to power up */ 1075 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1076 int i; 1077 1078 for (i = 0; i < 300; i++) { 1079 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1080 return true; 1081 mdelay(1); 1082 } 1083 return false; 1084 } 1085 done: 1086 return true; 1087 } 1088 1089 union external_encoder_control { 1090 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1091 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1092 }; 1093 1094 static void 1095 atombios_external_encoder_setup(struct drm_encoder *encoder, 1096 struct drm_encoder *ext_encoder, 1097 int action) 1098 { 1099 struct drm_device *dev = encoder->dev; 1100 struct radeon_device *rdev = dev->dev_private; 1101 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1102 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1103 union external_encoder_control args; 1104 struct drm_connector *connector; 1105 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1106 u8 frev, crev; 1107 int dp_clock = 0; 1108 int dp_lane_count = 0; 1109 int connector_object_id = 0; 1110 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1111 int bpc = 8; 1112 1113 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1114 connector = radeon_get_connector_for_encoder_init(encoder); 1115 else 1116 connector = radeon_get_connector_for_encoder(encoder); 1117 1118 if (connector) { 1119 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1120 struct radeon_connector_atom_dig *dig_connector = 1121 radeon_connector->con_priv; 1122 1123 dp_clock = dig_connector->dp_clock; 1124 dp_lane_count = dig_connector->dp_lane_count; 1125 connector_object_id = 1126 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1127 bpc = connector->display_info.bpc; 1128 } 1129 1130 memset(&args, 0, sizeof(args)); 1131 1132 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1133 return; 1134 1135 switch (frev) { 1136 case 1: 1137 /* no params on frev 1 */ 1138 break; 1139 case 2: 1140 switch (crev) { 1141 case 1: 1142 case 2: 1143 args.v1.sDigEncoder.ucAction = action; 1144 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1145 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1146 1147 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1148 if (dp_clock == 270000) 1149 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1150 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1151 } else if (radeon_encoder->pixel_clock > 165000) 1152 args.v1.sDigEncoder.ucLaneNum = 8; 1153 else 1154 args.v1.sDigEncoder.ucLaneNum = 4; 1155 break; 1156 case 3: 1157 args.v3.sExtEncoder.ucAction = action; 1158 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1159 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1160 else 1161 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1162 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1163 1164 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1165 if (dp_clock == 270000) 1166 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1167 else if (dp_clock == 540000) 1168 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1169 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1170 } else if (radeon_encoder->pixel_clock > 165000) 1171 args.v3.sExtEncoder.ucLaneNum = 8; 1172 else 1173 args.v3.sExtEncoder.ucLaneNum = 4; 1174 switch (ext_enum) { 1175 case GRAPH_OBJECT_ENUM_ID1: 1176 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1177 break; 1178 case GRAPH_OBJECT_ENUM_ID2: 1179 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1180 break; 1181 case GRAPH_OBJECT_ENUM_ID3: 1182 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1183 break; 1184 } 1185 switch (bpc) { 1186 case 0: 1187 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE; 1188 break; 1189 case 6: 1190 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR; 1191 break; 1192 case 8: 1193 default: 1194 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR; 1195 break; 1196 case 10: 1197 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR; 1198 break; 1199 case 12: 1200 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR; 1201 break; 1202 case 16: 1203 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR; 1204 break; 1205 } 1206 break; 1207 default: 1208 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1209 return; 1210 } 1211 break; 1212 default: 1213 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1214 return; 1215 } 1216 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1217 } 1218 1219 static void 1220 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1221 { 1222 struct drm_device *dev = encoder->dev; 1223 struct radeon_device *rdev = dev->dev_private; 1224 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1226 ENABLE_YUV_PS_ALLOCATION args; 1227 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1228 uint32_t temp, reg; 1229 1230 memset(&args, 0, sizeof(args)); 1231 1232 if (rdev->family >= CHIP_R600) 1233 reg = R600_BIOS_3_SCRATCH; 1234 else 1235 reg = RADEON_BIOS_3_SCRATCH; 1236 1237 /* XXX: fix up scratch reg handling */ 1238 temp = RREG32(reg); 1239 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1240 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1241 (radeon_crtc->crtc_id << 18))); 1242 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1243 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1244 else 1245 WREG32(reg, 0); 1246 1247 if (enable) 1248 args.ucEnable = ATOM_ENABLE; 1249 args.ucCRTC = radeon_crtc->crtc_id; 1250 1251 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1252 1253 WREG32(reg, temp); 1254 } 1255 1256 static void 1257 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1258 { 1259 struct drm_device *dev = encoder->dev; 1260 struct radeon_device *rdev = dev->dev_private; 1261 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1262 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1263 int index = 0; 1264 1265 memset(&args, 0, sizeof(args)); 1266 1267 switch (radeon_encoder->encoder_id) { 1268 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1269 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1270 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1271 break; 1272 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1273 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1274 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1275 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1276 break; 1277 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1278 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1279 break; 1280 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1281 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1282 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1283 else 1284 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1285 break; 1286 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1287 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1288 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1289 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1290 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1291 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1292 else 1293 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1294 break; 1295 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1296 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1297 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1298 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1299 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1300 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1301 else 1302 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1303 break; 1304 default: 1305 return; 1306 } 1307 1308 switch (mode) { 1309 case DRM_MODE_DPMS_ON: 1310 args.ucAction = ATOM_ENABLE; 1311 /* workaround for DVOOutputControl on some RS690 systems */ 1312 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1313 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1314 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1315 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1316 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1317 } else 1318 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1319 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1320 args.ucAction = ATOM_LCD_BLON; 1321 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1322 } 1323 break; 1324 case DRM_MODE_DPMS_STANDBY: 1325 case DRM_MODE_DPMS_SUSPEND: 1326 case DRM_MODE_DPMS_OFF: 1327 args.ucAction = ATOM_DISABLE; 1328 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1329 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1330 args.ucAction = ATOM_LCD_BLOFF; 1331 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1332 } 1333 break; 1334 } 1335 } 1336 1337 static void 1338 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1339 { 1340 struct drm_device *dev = encoder->dev; 1341 struct radeon_device *rdev = dev->dev_private; 1342 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1343 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1344 struct radeon_connector *radeon_connector = NULL; 1345 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1346 1347 if (connector) { 1348 radeon_connector = to_radeon_connector(connector); 1349 radeon_dig_connector = radeon_connector->con_priv; 1350 } 1351 1352 switch (mode) { 1353 case DRM_MODE_DPMS_ON: 1354 /* some early dce3.2 boards have a bug in their transmitter control table */ 1355 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730)) 1356 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1357 else 1358 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1359 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1360 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1361 atombios_set_edp_panel_power(connector, 1362 ATOM_TRANSMITTER_ACTION_POWER_ON); 1363 radeon_dig_connector->edp_on = true; 1364 } 1365 if (ASIC_IS_DCE4(rdev)) 1366 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1367 radeon_dp_link_train(encoder, connector); 1368 if (ASIC_IS_DCE4(rdev)) 1369 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1370 } 1371 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1372 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1373 break; 1374 case DRM_MODE_DPMS_STANDBY: 1375 case DRM_MODE_DPMS_SUSPEND: 1376 case DRM_MODE_DPMS_OFF: 1377 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1378 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1379 if (ASIC_IS_DCE4(rdev)) 1380 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1381 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1382 atombios_set_edp_panel_power(connector, 1383 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1384 radeon_dig_connector->edp_on = false; 1385 } 1386 } 1387 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1388 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1389 break; 1390 } 1391 } 1392 1393 static void 1394 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, 1395 struct drm_encoder *ext_encoder, 1396 int mode) 1397 { 1398 struct drm_device *dev = encoder->dev; 1399 struct radeon_device *rdev = dev->dev_private; 1400 1401 switch (mode) { 1402 case DRM_MODE_DPMS_ON: 1403 default: 1404 if (ASIC_IS_DCE41(rdev)) { 1405 atombios_external_encoder_setup(encoder, ext_encoder, 1406 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); 1407 atombios_external_encoder_setup(encoder, ext_encoder, 1408 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); 1409 } else 1410 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1411 break; 1412 case DRM_MODE_DPMS_STANDBY: 1413 case DRM_MODE_DPMS_SUSPEND: 1414 case DRM_MODE_DPMS_OFF: 1415 if (ASIC_IS_DCE41(rdev)) { 1416 atombios_external_encoder_setup(encoder, ext_encoder, 1417 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); 1418 atombios_external_encoder_setup(encoder, ext_encoder, 1419 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); 1420 } else 1421 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1422 break; 1423 } 1424 } 1425 1426 static void 1427 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1428 { 1429 struct drm_device *dev = encoder->dev; 1430 struct radeon_device *rdev = dev->dev_private; 1431 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1432 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1433 1434 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1435 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1436 radeon_encoder->active_device); 1437 switch (radeon_encoder->encoder_id) { 1438 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1439 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1440 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1441 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1442 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1443 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1444 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1445 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1446 radeon_atom_encoder_dpms_avivo(encoder, mode); 1447 break; 1448 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1449 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1450 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1451 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1452 radeon_atom_encoder_dpms_dig(encoder, mode); 1453 break; 1454 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1455 if (ASIC_IS_DCE5(rdev)) { 1456 switch (mode) { 1457 case DRM_MODE_DPMS_ON: 1458 atombios_dvo_setup(encoder, ATOM_ENABLE); 1459 break; 1460 case DRM_MODE_DPMS_STANDBY: 1461 case DRM_MODE_DPMS_SUSPEND: 1462 case DRM_MODE_DPMS_OFF: 1463 atombios_dvo_setup(encoder, ATOM_DISABLE); 1464 break; 1465 } 1466 } else if (ASIC_IS_DCE3(rdev)) 1467 radeon_atom_encoder_dpms_dig(encoder, mode); 1468 else 1469 radeon_atom_encoder_dpms_avivo(encoder, mode); 1470 break; 1471 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1472 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1473 if (ASIC_IS_DCE5(rdev)) { 1474 switch (mode) { 1475 case DRM_MODE_DPMS_ON: 1476 atombios_dac_setup(encoder, ATOM_ENABLE); 1477 break; 1478 case DRM_MODE_DPMS_STANDBY: 1479 case DRM_MODE_DPMS_SUSPEND: 1480 case DRM_MODE_DPMS_OFF: 1481 atombios_dac_setup(encoder, ATOM_DISABLE); 1482 break; 1483 } 1484 } else 1485 radeon_atom_encoder_dpms_avivo(encoder, mode); 1486 break; 1487 default: 1488 return; 1489 } 1490 1491 if (ext_encoder) 1492 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode); 1493 1494 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1495 1496 } 1497 1498 union crtc_source_param { 1499 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1500 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1501 }; 1502 1503 static void 1504 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1505 { 1506 struct drm_device *dev = encoder->dev; 1507 struct radeon_device *rdev = dev->dev_private; 1508 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1509 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1510 union crtc_source_param args; 1511 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1512 uint8_t frev, crev; 1513 struct radeon_encoder_atom_dig *dig; 1514 1515 memset(&args, 0, sizeof(args)); 1516 1517 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1518 return; 1519 1520 switch (frev) { 1521 case 1: 1522 switch (crev) { 1523 case 1: 1524 default: 1525 if (ASIC_IS_AVIVO(rdev)) 1526 args.v1.ucCRTC = radeon_crtc->crtc_id; 1527 else { 1528 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1529 args.v1.ucCRTC = radeon_crtc->crtc_id; 1530 } else { 1531 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1532 } 1533 } 1534 switch (radeon_encoder->encoder_id) { 1535 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1536 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1537 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1538 break; 1539 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1540 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1541 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1542 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1543 else 1544 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1545 break; 1546 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1547 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1548 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1549 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1550 break; 1551 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1552 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1553 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1554 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1555 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1556 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1557 else 1558 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1559 break; 1560 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1561 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1562 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1563 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1564 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1565 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1566 else 1567 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1568 break; 1569 } 1570 break; 1571 case 2: 1572 args.v2.ucCRTC = radeon_crtc->crtc_id; 1573 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1574 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1575 1576 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1577 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1578 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1579 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1580 else 1581 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1582 } else 1583 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1584 switch (radeon_encoder->encoder_id) { 1585 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1586 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1587 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1588 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1589 dig = radeon_encoder->enc_priv; 1590 switch (dig->dig_encoder) { 1591 case 0: 1592 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1593 break; 1594 case 1: 1595 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1596 break; 1597 case 2: 1598 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1599 break; 1600 case 3: 1601 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1602 break; 1603 case 4: 1604 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1605 break; 1606 case 5: 1607 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1608 break; 1609 } 1610 break; 1611 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1612 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1613 break; 1614 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1615 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1616 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1617 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1618 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1619 else 1620 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1621 break; 1622 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1623 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1624 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1625 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1626 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1627 else 1628 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1629 break; 1630 } 1631 break; 1632 } 1633 break; 1634 default: 1635 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1636 return; 1637 } 1638 1639 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1640 1641 /* update scratch regs with new routing */ 1642 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1643 } 1644 1645 static void 1646 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 1647 struct drm_display_mode *mode) 1648 { 1649 struct drm_device *dev = encoder->dev; 1650 struct radeon_device *rdev = dev->dev_private; 1651 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1652 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1653 1654 /* Funky macbooks */ 1655 if ((dev->pdev->device == 0x71C5) && 1656 (dev->pdev->subsystem_vendor == 0x106b) && 1657 (dev->pdev->subsystem_device == 0x0080)) { 1658 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1659 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1660 1661 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1662 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1663 1664 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 1665 } 1666 } 1667 1668 /* set scaler clears this on some chips */ 1669 if (ASIC_IS_AVIVO(rdev) && 1670 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 1671 if (ASIC_IS_DCE4(rdev)) { 1672 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1673 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 1674 EVERGREEN_INTERLEAVE_EN); 1675 else 1676 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1677 } else { 1678 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1679 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1680 AVIVO_D1MODE_INTERLEAVE_EN); 1681 else 1682 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1683 } 1684 } 1685 } 1686 1687 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 1688 { 1689 struct drm_device *dev = encoder->dev; 1690 struct radeon_device *rdev = dev->dev_private; 1691 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1692 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1693 struct drm_encoder *test_encoder; 1694 struct radeon_encoder_atom_dig *dig; 1695 uint32_t dig_enc_in_use = 0; 1696 1697 /* DCE4/5 */ 1698 if (ASIC_IS_DCE4(rdev)) { 1699 dig = radeon_encoder->enc_priv; 1700 if (ASIC_IS_DCE41(rdev)) { 1701 /* ontario follows DCE4 */ 1702 if (rdev->family == CHIP_PALM) { 1703 if (dig->linkb) 1704 return 1; 1705 else 1706 return 0; 1707 } else 1708 /* llano follows DCE3.2 */ 1709 return radeon_crtc->crtc_id; 1710 } else { 1711 switch (radeon_encoder->encoder_id) { 1712 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1713 if (dig->linkb) 1714 return 1; 1715 else 1716 return 0; 1717 break; 1718 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1719 if (dig->linkb) 1720 return 3; 1721 else 1722 return 2; 1723 break; 1724 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1725 if (dig->linkb) 1726 return 5; 1727 else 1728 return 4; 1729 break; 1730 } 1731 } 1732 } 1733 1734 /* on DCE32 and encoder can driver any block so just crtc id */ 1735 if (ASIC_IS_DCE32(rdev)) { 1736 return radeon_crtc->crtc_id; 1737 } 1738 1739 /* on DCE3 - LVTMA can only be driven by DIGB */ 1740 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1741 struct radeon_encoder *radeon_test_encoder; 1742 1743 if (encoder == test_encoder) 1744 continue; 1745 1746 if (!radeon_encoder_is_digital(test_encoder)) 1747 continue; 1748 1749 radeon_test_encoder = to_radeon_encoder(test_encoder); 1750 dig = radeon_test_encoder->enc_priv; 1751 1752 if (dig->dig_encoder >= 0) 1753 dig_enc_in_use |= (1 << dig->dig_encoder); 1754 } 1755 1756 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 1757 if (dig_enc_in_use & 0x2) 1758 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 1759 return 1; 1760 } 1761 if (!(dig_enc_in_use & 1)) 1762 return 0; 1763 return 1; 1764 } 1765 1766 /* This only needs to be called once at startup */ 1767 void 1768 radeon_atom_encoder_init(struct radeon_device *rdev) 1769 { 1770 struct drm_device *dev = rdev->ddev; 1771 struct drm_encoder *encoder; 1772 1773 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1774 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1775 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1776 1777 switch (radeon_encoder->encoder_id) { 1778 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1779 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1780 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1781 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1782 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 1783 break; 1784 default: 1785 break; 1786 } 1787 1788 if (ext_encoder && ASIC_IS_DCE41(rdev)) 1789 atombios_external_encoder_setup(encoder, ext_encoder, 1790 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 1791 } 1792 } 1793 1794 static void 1795 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 1796 struct drm_display_mode *mode, 1797 struct drm_display_mode *adjusted_mode) 1798 { 1799 struct drm_device *dev = encoder->dev; 1800 struct radeon_device *rdev = dev->dev_private; 1801 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1802 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1803 1804 radeon_encoder->pixel_clock = adjusted_mode->clock; 1805 1806 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 1807 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 1808 atombios_yuv_setup(encoder, true); 1809 else 1810 atombios_yuv_setup(encoder, false); 1811 } 1812 1813 switch (radeon_encoder->encoder_id) { 1814 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1815 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1816 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1817 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1818 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 1819 break; 1820 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1821 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1822 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1823 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1824 if (ASIC_IS_DCE4(rdev)) { 1825 /* disable the transmitter */ 1826 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1827 /* setup and enable the encoder */ 1828 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1829 1830 /* enable the transmitter */ 1831 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1832 } else { 1833 /* disable the encoder and transmitter */ 1834 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1835 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1836 1837 /* setup and enable the encoder and transmitter */ 1838 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1839 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1840 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1841 } 1842 break; 1843 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1844 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1845 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1846 atombios_dvo_setup(encoder, ATOM_ENABLE); 1847 break; 1848 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1849 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1850 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1851 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1852 atombios_dac_setup(encoder, ATOM_ENABLE); 1853 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 1854 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1855 atombios_tv_setup(encoder, ATOM_ENABLE); 1856 else 1857 atombios_tv_setup(encoder, ATOM_DISABLE); 1858 } 1859 break; 1860 } 1861 1862 if (ext_encoder) { 1863 if (ASIC_IS_DCE41(rdev)) 1864 atombios_external_encoder_setup(encoder, ext_encoder, 1865 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1866 else 1867 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1868 } 1869 1870 atombios_apply_encoder_quirks(encoder, adjusted_mode); 1871 1872 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 1873 r600_hdmi_enable(encoder); 1874 r600_hdmi_setmode(encoder, adjusted_mode); 1875 } 1876 } 1877 1878 static bool 1879 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1880 { 1881 struct drm_device *dev = encoder->dev; 1882 struct radeon_device *rdev = dev->dev_private; 1883 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1884 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1885 1886 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 1887 ATOM_DEVICE_CV_SUPPORT | 1888 ATOM_DEVICE_CRT_SUPPORT)) { 1889 DAC_LOAD_DETECTION_PS_ALLOCATION args; 1890 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 1891 uint8_t frev, crev; 1892 1893 memset(&args, 0, sizeof(args)); 1894 1895 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1896 return false; 1897 1898 args.sDacload.ucMisc = 0; 1899 1900 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 1901 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 1902 args.sDacload.ucDacType = ATOM_DAC_A; 1903 else 1904 args.sDacload.ucDacType = ATOM_DAC_B; 1905 1906 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 1907 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 1908 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 1909 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 1910 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1911 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 1912 if (crev >= 3) 1913 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1914 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1915 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 1916 if (crev >= 3) 1917 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1918 } 1919 1920 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1921 1922 return true; 1923 } else 1924 return false; 1925 } 1926 1927 static enum drm_connector_status 1928 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1929 { 1930 struct drm_device *dev = encoder->dev; 1931 struct radeon_device *rdev = dev->dev_private; 1932 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1933 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1934 uint32_t bios_0_scratch; 1935 1936 if (!atombios_dac_load_detect(encoder, connector)) { 1937 DRM_DEBUG_KMS("detect returned false \n"); 1938 return connector_status_unknown; 1939 } 1940 1941 if (rdev->family >= CHIP_R600) 1942 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 1943 else 1944 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 1945 1946 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 1947 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1948 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 1949 return connector_status_connected; 1950 } 1951 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1952 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 1953 return connector_status_connected; 1954 } 1955 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1956 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 1957 return connector_status_connected; 1958 } 1959 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1960 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 1961 return connector_status_connected; /* CTV */ 1962 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 1963 return connector_status_connected; /* STV */ 1964 } 1965 return connector_status_disconnected; 1966 } 1967 1968 static enum drm_connector_status 1969 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1970 { 1971 struct drm_device *dev = encoder->dev; 1972 struct radeon_device *rdev = dev->dev_private; 1973 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1974 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1975 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1976 u32 bios_0_scratch; 1977 1978 if (!ASIC_IS_DCE4(rdev)) 1979 return connector_status_unknown; 1980 1981 if (!ext_encoder) 1982 return connector_status_unknown; 1983 1984 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 1985 return connector_status_unknown; 1986 1987 /* load detect on the dp bridge */ 1988 atombios_external_encoder_setup(encoder, ext_encoder, 1989 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 1990 1991 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 1992 1993 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 1994 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1995 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 1996 return connector_status_connected; 1997 } 1998 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1999 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2000 return connector_status_connected; 2001 } 2002 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2003 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2004 return connector_status_connected; 2005 } 2006 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2007 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2008 return connector_status_connected; /* CTV */ 2009 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2010 return connector_status_connected; /* STV */ 2011 } 2012 return connector_status_disconnected; 2013 } 2014 2015 void 2016 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2017 { 2018 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2019 2020 if (ext_encoder) 2021 /* ddc_setup on the dp bridge */ 2022 atombios_external_encoder_setup(encoder, ext_encoder, 2023 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2024 2025 } 2026 2027 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2028 { 2029 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2030 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2031 2032 if ((radeon_encoder->active_device & 2033 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2034 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2035 ENCODER_OBJECT_ID_NONE)) { 2036 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2037 if (dig) 2038 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 2039 } 2040 2041 radeon_atom_output_lock(encoder, true); 2042 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2043 2044 if (connector) { 2045 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2046 2047 /* select the clock/data port if it uses a router */ 2048 if (radeon_connector->router.cd_valid) 2049 radeon_router_select_cd_port(radeon_connector); 2050 2051 /* turn eDP panel on for mode set */ 2052 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2053 atombios_set_edp_panel_power(connector, 2054 ATOM_TRANSMITTER_ACTION_POWER_ON); 2055 } 2056 2057 /* this is needed for the pll/ss setup to work correctly in some cases */ 2058 atombios_set_encoder_crtc_source(encoder); 2059 } 2060 2061 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2062 { 2063 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2064 radeon_atom_output_lock(encoder, false); 2065 } 2066 2067 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2068 { 2069 struct drm_device *dev = encoder->dev; 2070 struct radeon_device *rdev = dev->dev_private; 2071 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2072 struct radeon_encoder_atom_dig *dig; 2073 2074 /* check for pre-DCE3 cards with shared encoders; 2075 * can't really use the links individually, so don't disable 2076 * the encoder if it's in use by another connector 2077 */ 2078 if (!ASIC_IS_DCE3(rdev)) { 2079 struct drm_encoder *other_encoder; 2080 struct radeon_encoder *other_radeon_encoder; 2081 2082 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2083 other_radeon_encoder = to_radeon_encoder(other_encoder); 2084 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2085 drm_helper_encoder_in_use(other_encoder)) 2086 goto disable_done; 2087 } 2088 } 2089 2090 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2091 2092 switch (radeon_encoder->encoder_id) { 2093 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2094 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2095 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2096 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2097 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2098 break; 2099 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2100 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2101 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2102 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2103 if (ASIC_IS_DCE4(rdev)) 2104 /* disable the transmitter */ 2105 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 2106 else { 2107 /* disable the encoder and transmitter */ 2108 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 2109 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 2110 } 2111 break; 2112 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2113 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2114 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2115 atombios_dvo_setup(encoder, ATOM_DISABLE); 2116 break; 2117 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2118 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2119 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2121 atombios_dac_setup(encoder, ATOM_DISABLE); 2122 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2123 atombios_tv_setup(encoder, ATOM_DISABLE); 2124 break; 2125 } 2126 2127 disable_done: 2128 if (radeon_encoder_is_digital(encoder)) { 2129 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 2130 r600_hdmi_disable(encoder); 2131 dig = radeon_encoder->enc_priv; 2132 dig->dig_encoder = -1; 2133 } 2134 radeon_encoder->active_device = 0; 2135 } 2136 2137 /* these are handled by the primary encoders */ 2138 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2139 { 2140 2141 } 2142 2143 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2144 { 2145 2146 } 2147 2148 static void 2149 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2150 struct drm_display_mode *mode, 2151 struct drm_display_mode *adjusted_mode) 2152 { 2153 2154 } 2155 2156 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2157 { 2158 2159 } 2160 2161 static void 2162 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2163 { 2164 2165 } 2166 2167 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 2168 struct drm_display_mode *mode, 2169 struct drm_display_mode *adjusted_mode) 2170 { 2171 return true; 2172 } 2173 2174 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2175 .dpms = radeon_atom_ext_dpms, 2176 .mode_fixup = radeon_atom_ext_mode_fixup, 2177 .prepare = radeon_atom_ext_prepare, 2178 .mode_set = radeon_atom_ext_mode_set, 2179 .commit = radeon_atom_ext_commit, 2180 .disable = radeon_atom_ext_disable, 2181 /* no detect for TMDS/LVDS yet */ 2182 }; 2183 2184 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2185 .dpms = radeon_atom_encoder_dpms, 2186 .mode_fixup = radeon_atom_mode_fixup, 2187 .prepare = radeon_atom_encoder_prepare, 2188 .mode_set = radeon_atom_encoder_mode_set, 2189 .commit = radeon_atom_encoder_commit, 2190 .disable = radeon_atom_encoder_disable, 2191 .detect = radeon_atom_dig_detect, 2192 }; 2193 2194 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2195 .dpms = radeon_atom_encoder_dpms, 2196 .mode_fixup = radeon_atom_mode_fixup, 2197 .prepare = radeon_atom_encoder_prepare, 2198 .mode_set = radeon_atom_encoder_mode_set, 2199 .commit = radeon_atom_encoder_commit, 2200 .detect = radeon_atom_dac_detect, 2201 }; 2202 2203 void radeon_enc_destroy(struct drm_encoder *encoder) 2204 { 2205 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2206 kfree(radeon_encoder->enc_priv); 2207 drm_encoder_cleanup(encoder); 2208 kfree(radeon_encoder); 2209 } 2210 2211 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2212 .destroy = radeon_enc_destroy, 2213 }; 2214 2215 struct radeon_encoder_atom_dac * 2216 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2217 { 2218 struct drm_device *dev = radeon_encoder->base.dev; 2219 struct radeon_device *rdev = dev->dev_private; 2220 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2221 2222 if (!dac) 2223 return NULL; 2224 2225 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2226 return dac; 2227 } 2228 2229 struct radeon_encoder_atom_dig * 2230 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2231 { 2232 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2233 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2234 2235 if (!dig) 2236 return NULL; 2237 2238 /* coherent mode by default */ 2239 dig->coherent_mode = true; 2240 dig->dig_encoder = -1; 2241 2242 if (encoder_enum == 2) 2243 dig->linkb = true; 2244 else 2245 dig->linkb = false; 2246 2247 return dig; 2248 } 2249 2250 void 2251 radeon_add_atom_encoder(struct drm_device *dev, 2252 uint32_t encoder_enum, 2253 uint32_t supported_device, 2254 u16 caps) 2255 { 2256 struct radeon_device *rdev = dev->dev_private; 2257 struct drm_encoder *encoder; 2258 struct radeon_encoder *radeon_encoder; 2259 2260 /* see if we already added it */ 2261 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2262 radeon_encoder = to_radeon_encoder(encoder); 2263 if (radeon_encoder->encoder_enum == encoder_enum) { 2264 radeon_encoder->devices |= supported_device; 2265 return; 2266 } 2267 2268 } 2269 2270 /* add a new one */ 2271 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2272 if (!radeon_encoder) 2273 return; 2274 2275 encoder = &radeon_encoder->base; 2276 switch (rdev->num_crtc) { 2277 case 1: 2278 encoder->possible_crtcs = 0x1; 2279 break; 2280 case 2: 2281 default: 2282 encoder->possible_crtcs = 0x3; 2283 break; 2284 case 4: 2285 encoder->possible_crtcs = 0xf; 2286 break; 2287 case 6: 2288 encoder->possible_crtcs = 0x3f; 2289 break; 2290 } 2291 2292 radeon_encoder->enc_priv = NULL; 2293 2294 radeon_encoder->encoder_enum = encoder_enum; 2295 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2296 radeon_encoder->devices = supported_device; 2297 radeon_encoder->rmx_type = RMX_OFF; 2298 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2299 radeon_encoder->is_ext_encoder = false; 2300 radeon_encoder->caps = caps; 2301 2302 switch (radeon_encoder->encoder_id) { 2303 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2304 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2305 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2306 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2307 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2308 radeon_encoder->rmx_type = RMX_FULL; 2309 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2310 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2311 } else { 2312 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2313 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2314 } 2315 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2316 break; 2317 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2318 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2319 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2320 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2321 break; 2322 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2323 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2324 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2325 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 2326 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2327 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2328 break; 2329 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2330 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2331 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2332 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2333 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2334 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2335 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2336 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2337 radeon_encoder->rmx_type = RMX_FULL; 2338 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2339 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2340 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2341 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2342 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2343 } else { 2344 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2345 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2346 } 2347 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2348 break; 2349 case ENCODER_OBJECT_ID_SI170B: 2350 case ENCODER_OBJECT_ID_CH7303: 2351 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2352 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2353 case ENCODER_OBJECT_ID_TITFP513: 2354 case ENCODER_OBJECT_ID_VT1623: 2355 case ENCODER_OBJECT_ID_HDMI_SI1930: 2356 case ENCODER_OBJECT_ID_TRAVIS: 2357 case ENCODER_OBJECT_ID_NUTMEG: 2358 /* these are handled by the primary encoders */ 2359 radeon_encoder->is_ext_encoder = true; 2360 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2361 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2362 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2363 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2364 else 2365 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2366 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2367 break; 2368 } 2369 } 2370