1 /* 2 * Copyright 2007-11 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include "drmP.h" 27 #include "drm_crtc_helper.h" 28 #include "radeon_drm.h" 29 #include "radeon.h" 30 #include "atom.h" 31 32 extern int atom_debug; 33 34 /* evil but including atombios.h is much worse */ 35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 36 struct drm_display_mode *mode); 37 38 39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) 40 { 41 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 42 switch (radeon_encoder->encoder_id) { 43 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 44 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 45 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 46 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 47 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 48 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 49 case ENCODER_OBJECT_ID_INTERNAL_DDI: 50 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 51 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 52 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 53 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 54 return true; 55 default: 56 return false; 57 } 58 } 59 60 static struct drm_connector * 61 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder) 62 { 63 struct drm_device *dev = encoder->dev; 64 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 65 struct drm_connector *connector; 66 struct radeon_connector *radeon_connector; 67 68 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 69 radeon_connector = to_radeon_connector(connector); 70 if (radeon_encoder->devices & radeon_connector->devices) 71 return connector; 72 } 73 return NULL; 74 } 75 76 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 77 struct drm_display_mode *mode, 78 struct drm_display_mode *adjusted_mode) 79 { 80 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 81 struct drm_device *dev = encoder->dev; 82 struct radeon_device *rdev = dev->dev_private; 83 84 /* set the active encoder to connector routing */ 85 radeon_encoder_set_active_device(encoder); 86 drm_mode_set_crtcinfo(adjusted_mode, 0); 87 88 /* hw bug */ 89 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 90 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 91 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 92 93 /* get the native mode for LVDS */ 94 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 95 radeon_panel_mode_fixup(encoder, adjusted_mode); 96 97 /* get the native mode for TV */ 98 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 99 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 100 if (tv_dac) { 101 if (tv_dac->tv_std == TV_STD_NTSC || 102 tv_dac->tv_std == TV_STD_NTSC_J || 103 tv_dac->tv_std == TV_STD_PAL_M) 104 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 105 else 106 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 107 } 108 } 109 110 if (ASIC_IS_DCE3(rdev) && 111 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 112 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 113 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 114 radeon_dp_set_link_config(connector, mode); 115 } 116 117 return true; 118 } 119 120 static void 121 atombios_dac_setup(struct drm_encoder *encoder, int action) 122 { 123 struct drm_device *dev = encoder->dev; 124 struct radeon_device *rdev = dev->dev_private; 125 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 126 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 127 int index = 0; 128 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 129 130 memset(&args, 0, sizeof(args)); 131 132 switch (radeon_encoder->encoder_id) { 133 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 134 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 135 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 136 break; 137 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 138 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 139 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 140 break; 141 } 142 143 args.ucAction = action; 144 145 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 146 args.ucDacStandard = ATOM_DAC1_PS2; 147 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 148 args.ucDacStandard = ATOM_DAC1_CV; 149 else { 150 switch (dac_info->tv_std) { 151 case TV_STD_PAL: 152 case TV_STD_PAL_M: 153 case TV_STD_SCART_PAL: 154 case TV_STD_SECAM: 155 case TV_STD_PAL_CN: 156 args.ucDacStandard = ATOM_DAC1_PAL; 157 break; 158 case TV_STD_NTSC: 159 case TV_STD_NTSC_J: 160 case TV_STD_PAL_60: 161 default: 162 args.ucDacStandard = ATOM_DAC1_NTSC; 163 break; 164 } 165 } 166 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 167 168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 169 170 } 171 172 static void 173 atombios_tv_setup(struct drm_encoder *encoder, int action) 174 { 175 struct drm_device *dev = encoder->dev; 176 struct radeon_device *rdev = dev->dev_private; 177 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 178 TV_ENCODER_CONTROL_PS_ALLOCATION args; 179 int index = 0; 180 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 181 182 memset(&args, 0, sizeof(args)); 183 184 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 185 186 args.sTVEncoder.ucAction = action; 187 188 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 189 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 190 else { 191 switch (dac_info->tv_std) { 192 case TV_STD_NTSC: 193 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 194 break; 195 case TV_STD_PAL: 196 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 197 break; 198 case TV_STD_PAL_M: 199 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 200 break; 201 case TV_STD_PAL_60: 202 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 203 break; 204 case TV_STD_NTSC_J: 205 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 206 break; 207 case TV_STD_SCART_PAL: 208 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 209 break; 210 case TV_STD_SECAM: 211 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 212 break; 213 case TV_STD_PAL_CN: 214 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 215 break; 216 default: 217 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 218 break; 219 } 220 } 221 222 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 223 224 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 225 226 } 227 228 union dvo_encoder_control { 229 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 230 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 231 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 232 }; 233 234 void 235 atombios_dvo_setup(struct drm_encoder *encoder, int action) 236 { 237 struct drm_device *dev = encoder->dev; 238 struct radeon_device *rdev = dev->dev_private; 239 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 240 union dvo_encoder_control args; 241 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 242 uint8_t frev, crev; 243 244 memset(&args, 0, sizeof(args)); 245 246 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 247 return; 248 249 switch (frev) { 250 case 1: 251 switch (crev) { 252 case 1: 253 /* R4xx, R5xx */ 254 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 255 256 if (radeon_encoder->pixel_clock > 165000) 257 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 258 259 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 260 break; 261 case 2: 262 /* RS600/690/740 */ 263 args.dvo.sDVOEncoder.ucAction = action; 264 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 265 /* DFP1, CRT1, TV1 depending on the type of port */ 266 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 267 268 if (radeon_encoder->pixel_clock > 165000) 269 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 270 break; 271 case 3: 272 /* R6xx */ 273 args.dvo_v3.ucAction = action; 274 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 275 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 276 break; 277 default: 278 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 279 break; 280 } 281 break; 282 default: 283 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 284 break; 285 } 286 287 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 288 } 289 290 union lvds_encoder_control { 291 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 292 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 293 }; 294 295 void 296 atombios_digital_setup(struct drm_encoder *encoder, int action) 297 { 298 struct drm_device *dev = encoder->dev; 299 struct radeon_device *rdev = dev->dev_private; 300 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 301 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 302 union lvds_encoder_control args; 303 int index = 0; 304 int hdmi_detected = 0; 305 uint8_t frev, crev; 306 307 if (!dig) 308 return; 309 310 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 311 hdmi_detected = 1; 312 313 memset(&args, 0, sizeof(args)); 314 315 switch (radeon_encoder->encoder_id) { 316 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 317 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 318 break; 319 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 320 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 321 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 322 break; 323 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 324 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 325 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 326 else 327 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 328 break; 329 } 330 331 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 332 return; 333 334 switch (frev) { 335 case 1: 336 case 2: 337 switch (crev) { 338 case 1: 339 args.v1.ucMisc = 0; 340 args.v1.ucAction = action; 341 if (hdmi_detected) 342 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 343 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 344 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 345 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 346 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 347 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 348 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 349 } else { 350 if (dig->linkb) 351 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 352 if (radeon_encoder->pixel_clock > 165000) 353 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 354 /*if (pScrn->rgbBits == 8) */ 355 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 356 } 357 break; 358 case 2: 359 case 3: 360 args.v2.ucMisc = 0; 361 args.v2.ucAction = action; 362 if (crev == 3) { 363 if (dig->coherent_mode) 364 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 365 } 366 if (hdmi_detected) 367 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 368 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 369 args.v2.ucTruncate = 0; 370 args.v2.ucSpatial = 0; 371 args.v2.ucTemporal = 0; 372 args.v2.ucFRC = 0; 373 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 374 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 375 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 376 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 377 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 378 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 379 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 380 } 381 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 382 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 383 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 384 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 385 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 386 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 387 } 388 } else { 389 if (dig->linkb) 390 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 391 if (radeon_encoder->pixel_clock > 165000) 392 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 393 } 394 break; 395 default: 396 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 397 break; 398 } 399 break; 400 default: 401 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 402 break; 403 } 404 405 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 406 } 407 408 int 409 atombios_get_encoder_mode(struct drm_encoder *encoder) 410 { 411 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 412 struct drm_connector *connector; 413 struct radeon_connector *radeon_connector; 414 struct radeon_connector_atom_dig *dig_connector; 415 416 /* dp bridges are always DP */ 417 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 418 return ATOM_ENCODER_MODE_DP; 419 420 /* DVO is always DVO */ 421 if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO) 422 return ATOM_ENCODER_MODE_DVO; 423 424 connector = radeon_get_connector_for_encoder(encoder); 425 /* if we don't have an active device yet, just use one of 426 * the connectors tied to the encoder. 427 */ 428 if (!connector) 429 connector = radeon_get_connector_for_encoder_init(encoder); 430 radeon_connector = to_radeon_connector(connector); 431 432 switch (connector->connector_type) { 433 case DRM_MODE_CONNECTOR_DVII: 434 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 435 if (drm_detect_monitor_audio(radeon_connector->edid) && 436 radeon_audio) 437 return ATOM_ENCODER_MODE_HDMI; 438 else if (radeon_connector->use_digital) 439 return ATOM_ENCODER_MODE_DVI; 440 else 441 return ATOM_ENCODER_MODE_CRT; 442 break; 443 case DRM_MODE_CONNECTOR_DVID: 444 case DRM_MODE_CONNECTOR_HDMIA: 445 default: 446 if (drm_detect_monitor_audio(radeon_connector->edid) && 447 radeon_audio) 448 return ATOM_ENCODER_MODE_HDMI; 449 else 450 return ATOM_ENCODER_MODE_DVI; 451 break; 452 case DRM_MODE_CONNECTOR_LVDS: 453 return ATOM_ENCODER_MODE_LVDS; 454 break; 455 case DRM_MODE_CONNECTOR_DisplayPort: 456 dig_connector = radeon_connector->con_priv; 457 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 458 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 459 return ATOM_ENCODER_MODE_DP; 460 else if (drm_detect_monitor_audio(radeon_connector->edid) && 461 radeon_audio) 462 return ATOM_ENCODER_MODE_HDMI; 463 else 464 return ATOM_ENCODER_MODE_DVI; 465 break; 466 case DRM_MODE_CONNECTOR_eDP: 467 return ATOM_ENCODER_MODE_DP; 468 case DRM_MODE_CONNECTOR_DVIA: 469 case DRM_MODE_CONNECTOR_VGA: 470 return ATOM_ENCODER_MODE_CRT; 471 break; 472 case DRM_MODE_CONNECTOR_Composite: 473 case DRM_MODE_CONNECTOR_SVIDEO: 474 case DRM_MODE_CONNECTOR_9PinDIN: 475 /* fix me */ 476 return ATOM_ENCODER_MODE_TV; 477 /*return ATOM_ENCODER_MODE_CV;*/ 478 break; 479 } 480 } 481 482 /* 483 * DIG Encoder/Transmitter Setup 484 * 485 * DCE 3.0/3.1 486 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 487 * Supports up to 3 digital outputs 488 * - 2 DIG encoder blocks. 489 * DIG1 can drive UNIPHY link A or link B 490 * DIG2 can drive UNIPHY link B or LVTMA 491 * 492 * DCE 3.2 493 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 494 * Supports up to 5 digital outputs 495 * - 2 DIG encoder blocks. 496 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 497 * 498 * DCE 4.0/5.0 499 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 500 * Supports up to 6 digital outputs 501 * - 6 DIG encoder blocks. 502 * - DIG to PHY mapping is hardcoded 503 * DIG1 drives UNIPHY0 link A, A+B 504 * DIG2 drives UNIPHY0 link B 505 * DIG3 drives UNIPHY1 link A, A+B 506 * DIG4 drives UNIPHY1 link B 507 * DIG5 drives UNIPHY2 link A, A+B 508 * DIG6 drives UNIPHY2 link B 509 * 510 * DCE 4.1 511 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 512 * Supports up to 6 digital outputs 513 * - 2 DIG encoder blocks. 514 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 515 * 516 * Routing 517 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 518 * Examples: 519 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 520 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 521 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 522 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 523 */ 524 525 union dig_encoder_control { 526 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 527 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 528 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 529 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 530 }; 531 532 void 533 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 534 { 535 struct drm_device *dev = encoder->dev; 536 struct radeon_device *rdev = dev->dev_private; 537 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 538 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 539 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 540 union dig_encoder_control args; 541 int index = 0; 542 uint8_t frev, crev; 543 int dp_clock = 0; 544 int dp_lane_count = 0; 545 int hpd_id = RADEON_HPD_NONE; 546 int bpc = 8; 547 548 if (connector) { 549 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 550 struct radeon_connector_atom_dig *dig_connector = 551 radeon_connector->con_priv; 552 553 dp_clock = dig_connector->dp_clock; 554 dp_lane_count = dig_connector->dp_lane_count; 555 hpd_id = radeon_connector->hpd.hpd; 556 bpc = connector->display_info.bpc; 557 } 558 559 /* no dig encoder assigned */ 560 if (dig->dig_encoder == -1) 561 return; 562 563 memset(&args, 0, sizeof(args)); 564 565 if (ASIC_IS_DCE4(rdev)) 566 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 567 else { 568 if (dig->dig_encoder) 569 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 570 else 571 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 572 } 573 574 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 575 return; 576 577 switch (frev) { 578 case 1: 579 switch (crev) { 580 case 1: 581 args.v1.ucAction = action; 582 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 583 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 584 args.v3.ucPanelMode = panel_mode; 585 else 586 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 587 588 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 589 args.v1.ucLaneNum = dp_lane_count; 590 else if (radeon_encoder->pixel_clock > 165000) 591 args.v1.ucLaneNum = 8; 592 else 593 args.v1.ucLaneNum = 4; 594 595 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 596 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 597 switch (radeon_encoder->encoder_id) { 598 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 599 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 600 break; 601 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 602 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 603 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 604 break; 605 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 606 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 607 break; 608 } 609 if (dig->linkb) 610 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 611 else 612 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 613 break; 614 case 2: 615 case 3: 616 args.v3.ucAction = action; 617 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 618 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 619 args.v3.ucPanelMode = panel_mode; 620 else 621 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 622 623 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 624 args.v3.ucLaneNum = dp_lane_count; 625 else if (radeon_encoder->pixel_clock > 165000) 626 args.v3.ucLaneNum = 8; 627 else 628 args.v3.ucLaneNum = 4; 629 630 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 631 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 632 args.v3.acConfig.ucDigSel = dig->dig_encoder; 633 switch (bpc) { 634 case 0: 635 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE; 636 break; 637 case 6: 638 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR; 639 break; 640 case 8: 641 default: 642 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; 643 break; 644 case 10: 645 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR; 646 break; 647 case 12: 648 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR; 649 break; 650 case 16: 651 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR; 652 break; 653 } 654 break; 655 case 4: 656 args.v4.ucAction = action; 657 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 658 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 659 args.v4.ucPanelMode = panel_mode; 660 else 661 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 662 663 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 664 args.v4.ucLaneNum = dp_lane_count; 665 else if (radeon_encoder->pixel_clock > 165000) 666 args.v4.ucLaneNum = 8; 667 else 668 args.v4.ucLaneNum = 4; 669 670 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) { 671 if (dp_clock == 270000) 672 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 673 else if (dp_clock == 540000) 674 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 675 } 676 args.v4.acConfig.ucDigSel = dig->dig_encoder; 677 switch (bpc) { 678 case 0: 679 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE; 680 break; 681 case 6: 682 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR; 683 break; 684 case 8: 685 default: 686 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; 687 break; 688 case 10: 689 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR; 690 break; 691 case 12: 692 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR; 693 break; 694 case 16: 695 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR; 696 break; 697 } 698 if (hpd_id == RADEON_HPD_NONE) 699 args.v4.ucHPD_ID = 0; 700 else 701 args.v4.ucHPD_ID = hpd_id + 1; 702 break; 703 default: 704 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 705 break; 706 } 707 break; 708 default: 709 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 710 break; 711 } 712 713 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 714 715 } 716 717 union dig_transmitter_control { 718 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 719 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 720 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 721 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 722 }; 723 724 void 725 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 726 { 727 struct drm_device *dev = encoder->dev; 728 struct radeon_device *rdev = dev->dev_private; 729 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 730 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 731 struct drm_connector *connector; 732 union dig_transmitter_control args; 733 int index = 0; 734 uint8_t frev, crev; 735 bool is_dp = false; 736 int pll_id = 0; 737 int dp_clock = 0; 738 int dp_lane_count = 0; 739 int connector_object_id = 0; 740 int igp_lane_info = 0; 741 int dig_encoder = dig->dig_encoder; 742 743 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 744 connector = radeon_get_connector_for_encoder_init(encoder); 745 /* just needed to avoid bailing in the encoder check. the encoder 746 * isn't used for init 747 */ 748 dig_encoder = 0; 749 } else 750 connector = radeon_get_connector_for_encoder(encoder); 751 752 if (connector) { 753 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 754 struct radeon_connector_atom_dig *dig_connector = 755 radeon_connector->con_priv; 756 757 dp_clock = dig_connector->dp_clock; 758 dp_lane_count = dig_connector->dp_lane_count; 759 connector_object_id = 760 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 761 igp_lane_info = dig_connector->igp_lane_info; 762 } 763 764 if (encoder->crtc) { 765 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 766 pll_id = radeon_crtc->pll_id; 767 } 768 769 /* no dig encoder assigned */ 770 if (dig_encoder == -1) 771 return; 772 773 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 774 is_dp = true; 775 776 memset(&args, 0, sizeof(args)); 777 778 switch (radeon_encoder->encoder_id) { 779 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 780 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 781 break; 782 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 783 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 784 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 785 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 786 break; 787 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 788 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 789 break; 790 } 791 792 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 793 return; 794 795 switch (frev) { 796 case 1: 797 switch (crev) { 798 case 1: 799 args.v1.ucAction = action; 800 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 801 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 802 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 803 args.v1.asMode.ucLaneSel = lane_num; 804 args.v1.asMode.ucLaneSet = lane_set; 805 } else { 806 if (is_dp) 807 args.v1.usPixelClock = 808 cpu_to_le16(dp_clock / 10); 809 else if (radeon_encoder->pixel_clock > 165000) 810 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 811 else 812 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 813 } 814 815 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 816 817 if (dig_encoder) 818 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 819 else 820 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 821 822 if ((rdev->flags & RADEON_IS_IGP) && 823 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 824 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { 825 if (igp_lane_info & 0x1) 826 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 827 else if (igp_lane_info & 0x2) 828 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 829 else if (igp_lane_info & 0x4) 830 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 831 else if (igp_lane_info & 0x8) 832 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 833 } else { 834 if (igp_lane_info & 0x3) 835 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 836 else if (igp_lane_info & 0xc) 837 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 838 } 839 } 840 841 if (dig->linkb) 842 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 843 else 844 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 845 846 if (is_dp) 847 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 848 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 849 if (dig->coherent_mode) 850 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 851 if (radeon_encoder->pixel_clock > 165000) 852 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 853 } 854 break; 855 case 2: 856 args.v2.ucAction = action; 857 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 858 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 859 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 860 args.v2.asMode.ucLaneSel = lane_num; 861 args.v2.asMode.ucLaneSet = lane_set; 862 } else { 863 if (is_dp) 864 args.v2.usPixelClock = 865 cpu_to_le16(dp_clock / 10); 866 else if (radeon_encoder->pixel_clock > 165000) 867 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 868 else 869 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 870 } 871 872 args.v2.acConfig.ucEncoderSel = dig_encoder; 873 if (dig->linkb) 874 args.v2.acConfig.ucLinkSel = 1; 875 876 switch (radeon_encoder->encoder_id) { 877 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 878 args.v2.acConfig.ucTransmitterSel = 0; 879 break; 880 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 881 args.v2.acConfig.ucTransmitterSel = 1; 882 break; 883 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 884 args.v2.acConfig.ucTransmitterSel = 2; 885 break; 886 } 887 888 if (is_dp) { 889 args.v2.acConfig.fCoherentMode = 1; 890 args.v2.acConfig.fDPConnector = 1; 891 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 892 if (dig->coherent_mode) 893 args.v2.acConfig.fCoherentMode = 1; 894 if (radeon_encoder->pixel_clock > 165000) 895 args.v2.acConfig.fDualLinkConnector = 1; 896 } 897 break; 898 case 3: 899 args.v3.ucAction = action; 900 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 901 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 902 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 903 args.v3.asMode.ucLaneSel = lane_num; 904 args.v3.asMode.ucLaneSet = lane_set; 905 } else { 906 if (is_dp) 907 args.v3.usPixelClock = 908 cpu_to_le16(dp_clock / 10); 909 else if (radeon_encoder->pixel_clock > 165000) 910 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 911 else 912 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 913 } 914 915 if (is_dp) 916 args.v3.ucLaneNum = dp_lane_count; 917 else if (radeon_encoder->pixel_clock > 165000) 918 args.v3.ucLaneNum = 8; 919 else 920 args.v3.ucLaneNum = 4; 921 922 if (dig->linkb) 923 args.v3.acConfig.ucLinkSel = 1; 924 if (dig_encoder & 1) 925 args.v3.acConfig.ucEncoderSel = 1; 926 927 /* Select the PLL for the PHY 928 * DP PHY should be clocked from external src if there is 929 * one. 930 */ 931 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 932 if (is_dp && rdev->clock.dp_extclk) 933 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 934 else 935 args.v3.acConfig.ucRefClkSource = pll_id; 936 937 switch (radeon_encoder->encoder_id) { 938 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 939 args.v3.acConfig.ucTransmitterSel = 0; 940 break; 941 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 942 args.v3.acConfig.ucTransmitterSel = 1; 943 break; 944 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 945 args.v3.acConfig.ucTransmitterSel = 2; 946 break; 947 } 948 949 if (is_dp) 950 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 951 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 952 if (dig->coherent_mode) 953 args.v3.acConfig.fCoherentMode = 1; 954 if (radeon_encoder->pixel_clock > 165000) 955 args.v3.acConfig.fDualLinkConnector = 1; 956 } 957 break; 958 case 4: 959 args.v4.ucAction = action; 960 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 961 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 962 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 963 args.v4.asMode.ucLaneSel = lane_num; 964 args.v4.asMode.ucLaneSet = lane_set; 965 } else { 966 if (is_dp) 967 args.v4.usPixelClock = 968 cpu_to_le16(dp_clock / 10); 969 else if (radeon_encoder->pixel_clock > 165000) 970 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 971 else 972 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 973 } 974 975 if (is_dp) 976 args.v4.ucLaneNum = dp_lane_count; 977 else if (radeon_encoder->pixel_clock > 165000) 978 args.v4.ucLaneNum = 8; 979 else 980 args.v4.ucLaneNum = 4; 981 982 if (dig->linkb) 983 args.v4.acConfig.ucLinkSel = 1; 984 if (dig_encoder & 1) 985 args.v4.acConfig.ucEncoderSel = 1; 986 987 /* Select the PLL for the PHY 988 * DP PHY should be clocked from external src if there is 989 * one. 990 */ 991 /* On DCE5 DCPLL usually generates the DP ref clock */ 992 if (is_dp) { 993 if (rdev->clock.dp_extclk) 994 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 995 else 996 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 997 } else 998 args.v4.acConfig.ucRefClkSource = pll_id; 999 1000 switch (radeon_encoder->encoder_id) { 1001 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1002 args.v4.acConfig.ucTransmitterSel = 0; 1003 break; 1004 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1005 args.v4.acConfig.ucTransmitterSel = 1; 1006 break; 1007 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1008 args.v4.acConfig.ucTransmitterSel = 2; 1009 break; 1010 } 1011 1012 if (is_dp) 1013 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1014 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1015 if (dig->coherent_mode) 1016 args.v4.acConfig.fCoherentMode = 1; 1017 if (radeon_encoder->pixel_clock > 165000) 1018 args.v4.acConfig.fDualLinkConnector = 1; 1019 } 1020 break; 1021 default: 1022 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1023 break; 1024 } 1025 break; 1026 default: 1027 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1028 break; 1029 } 1030 1031 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1032 } 1033 1034 bool 1035 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1036 { 1037 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1038 struct drm_device *dev = radeon_connector->base.dev; 1039 struct radeon_device *rdev = dev->dev_private; 1040 union dig_transmitter_control args; 1041 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1042 uint8_t frev, crev; 1043 1044 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1045 goto done; 1046 1047 if (!ASIC_IS_DCE4(rdev)) 1048 goto done; 1049 1050 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1051 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1052 goto done; 1053 1054 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1055 goto done; 1056 1057 memset(&args, 0, sizeof(args)); 1058 1059 args.v1.ucAction = action; 1060 1061 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1062 1063 /* wait for the panel to power up */ 1064 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1065 int i; 1066 1067 for (i = 0; i < 300; i++) { 1068 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1069 return true; 1070 mdelay(1); 1071 } 1072 return false; 1073 } 1074 done: 1075 return true; 1076 } 1077 1078 union external_encoder_control { 1079 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1080 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1081 }; 1082 1083 static void 1084 atombios_external_encoder_setup(struct drm_encoder *encoder, 1085 struct drm_encoder *ext_encoder, 1086 int action) 1087 { 1088 struct drm_device *dev = encoder->dev; 1089 struct radeon_device *rdev = dev->dev_private; 1090 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1091 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1092 union external_encoder_control args; 1093 struct drm_connector *connector; 1094 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1095 u8 frev, crev; 1096 int dp_clock = 0; 1097 int dp_lane_count = 0; 1098 int connector_object_id = 0; 1099 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1100 int bpc = 8; 1101 1102 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1103 connector = radeon_get_connector_for_encoder_init(encoder); 1104 else 1105 connector = radeon_get_connector_for_encoder(encoder); 1106 1107 if (connector) { 1108 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1109 struct radeon_connector_atom_dig *dig_connector = 1110 radeon_connector->con_priv; 1111 1112 dp_clock = dig_connector->dp_clock; 1113 dp_lane_count = dig_connector->dp_lane_count; 1114 connector_object_id = 1115 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1116 bpc = connector->display_info.bpc; 1117 } 1118 1119 memset(&args, 0, sizeof(args)); 1120 1121 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1122 return; 1123 1124 switch (frev) { 1125 case 1: 1126 /* no params on frev 1 */ 1127 break; 1128 case 2: 1129 switch (crev) { 1130 case 1: 1131 case 2: 1132 args.v1.sDigEncoder.ucAction = action; 1133 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1134 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1135 1136 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1137 if (dp_clock == 270000) 1138 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1139 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1140 } else if (radeon_encoder->pixel_clock > 165000) 1141 args.v1.sDigEncoder.ucLaneNum = 8; 1142 else 1143 args.v1.sDigEncoder.ucLaneNum = 4; 1144 break; 1145 case 3: 1146 args.v3.sExtEncoder.ucAction = action; 1147 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1148 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1149 else 1150 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1151 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1152 1153 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1154 if (dp_clock == 270000) 1155 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1156 else if (dp_clock == 540000) 1157 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1158 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1159 } else if (radeon_encoder->pixel_clock > 165000) 1160 args.v3.sExtEncoder.ucLaneNum = 8; 1161 else 1162 args.v3.sExtEncoder.ucLaneNum = 4; 1163 switch (ext_enum) { 1164 case GRAPH_OBJECT_ENUM_ID1: 1165 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1166 break; 1167 case GRAPH_OBJECT_ENUM_ID2: 1168 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1169 break; 1170 case GRAPH_OBJECT_ENUM_ID3: 1171 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1172 break; 1173 } 1174 switch (bpc) { 1175 case 0: 1176 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE; 1177 break; 1178 case 6: 1179 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR; 1180 break; 1181 case 8: 1182 default: 1183 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR; 1184 break; 1185 case 10: 1186 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR; 1187 break; 1188 case 12: 1189 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR; 1190 break; 1191 case 16: 1192 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR; 1193 break; 1194 } 1195 break; 1196 default: 1197 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1198 return; 1199 } 1200 break; 1201 default: 1202 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1203 return; 1204 } 1205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1206 } 1207 1208 static void 1209 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1210 { 1211 struct drm_device *dev = encoder->dev; 1212 struct radeon_device *rdev = dev->dev_private; 1213 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1215 ENABLE_YUV_PS_ALLOCATION args; 1216 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1217 uint32_t temp, reg; 1218 1219 memset(&args, 0, sizeof(args)); 1220 1221 if (rdev->family >= CHIP_R600) 1222 reg = R600_BIOS_3_SCRATCH; 1223 else 1224 reg = RADEON_BIOS_3_SCRATCH; 1225 1226 /* XXX: fix up scratch reg handling */ 1227 temp = RREG32(reg); 1228 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1229 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1230 (radeon_crtc->crtc_id << 18))); 1231 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1232 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1233 else 1234 WREG32(reg, 0); 1235 1236 if (enable) 1237 args.ucEnable = ATOM_ENABLE; 1238 args.ucCRTC = radeon_crtc->crtc_id; 1239 1240 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1241 1242 WREG32(reg, temp); 1243 } 1244 1245 static void 1246 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1247 { 1248 struct drm_device *dev = encoder->dev; 1249 struct radeon_device *rdev = dev->dev_private; 1250 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1251 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1252 int index = 0; 1253 1254 memset(&args, 0, sizeof(args)); 1255 1256 switch (radeon_encoder->encoder_id) { 1257 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1258 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1259 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1260 break; 1261 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1262 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1263 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1264 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1265 break; 1266 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1267 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1268 break; 1269 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1270 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1271 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1272 else 1273 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1274 break; 1275 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1276 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1277 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1278 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1279 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1280 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1281 else 1282 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1283 break; 1284 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1285 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1286 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1287 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1288 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1289 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1290 else 1291 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1292 break; 1293 default: 1294 return; 1295 } 1296 1297 switch (mode) { 1298 case DRM_MODE_DPMS_ON: 1299 args.ucAction = ATOM_ENABLE; 1300 /* workaround for DVOOutputControl on some RS690 systems */ 1301 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1302 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1303 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1304 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1305 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1306 } else 1307 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1308 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1309 args.ucAction = ATOM_LCD_BLON; 1310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1311 } 1312 break; 1313 case DRM_MODE_DPMS_STANDBY: 1314 case DRM_MODE_DPMS_SUSPEND: 1315 case DRM_MODE_DPMS_OFF: 1316 args.ucAction = ATOM_DISABLE; 1317 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1318 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1319 args.ucAction = ATOM_LCD_BLOFF; 1320 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1321 } 1322 break; 1323 } 1324 } 1325 1326 static void 1327 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1328 { 1329 struct drm_device *dev = encoder->dev; 1330 struct radeon_device *rdev = dev->dev_private; 1331 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1332 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1333 struct radeon_connector *radeon_connector = NULL; 1334 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1335 1336 if (connector) { 1337 radeon_connector = to_radeon_connector(connector); 1338 radeon_dig_connector = radeon_connector->con_priv; 1339 } 1340 1341 switch (mode) { 1342 case DRM_MODE_DPMS_ON: 1343 /* some early dce3.2 boards have a bug in their transmitter control table */ 1344 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730)) 1345 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1346 else 1347 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1348 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1349 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1350 atombios_set_edp_panel_power(connector, 1351 ATOM_TRANSMITTER_ACTION_POWER_ON); 1352 radeon_dig_connector->edp_on = true; 1353 } 1354 if (ASIC_IS_DCE4(rdev)) 1355 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1356 radeon_dp_link_train(encoder, connector); 1357 if (ASIC_IS_DCE4(rdev)) 1358 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1359 } 1360 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1361 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1362 break; 1363 case DRM_MODE_DPMS_STANDBY: 1364 case DRM_MODE_DPMS_SUSPEND: 1365 case DRM_MODE_DPMS_OFF: 1366 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1367 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1368 if (ASIC_IS_DCE4(rdev)) 1369 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1370 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1371 atombios_set_edp_panel_power(connector, 1372 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1373 radeon_dig_connector->edp_on = false; 1374 } 1375 } 1376 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1377 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1378 break; 1379 } 1380 } 1381 1382 static void 1383 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, 1384 struct drm_encoder *ext_encoder, 1385 int mode) 1386 { 1387 struct drm_device *dev = encoder->dev; 1388 struct radeon_device *rdev = dev->dev_private; 1389 1390 switch (mode) { 1391 case DRM_MODE_DPMS_ON: 1392 default: 1393 if (ASIC_IS_DCE41(rdev)) { 1394 atombios_external_encoder_setup(encoder, ext_encoder, 1395 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); 1396 atombios_external_encoder_setup(encoder, ext_encoder, 1397 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); 1398 } else 1399 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1400 break; 1401 case DRM_MODE_DPMS_STANDBY: 1402 case DRM_MODE_DPMS_SUSPEND: 1403 case DRM_MODE_DPMS_OFF: 1404 if (ASIC_IS_DCE41(rdev)) { 1405 atombios_external_encoder_setup(encoder, ext_encoder, 1406 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); 1407 atombios_external_encoder_setup(encoder, ext_encoder, 1408 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); 1409 } else 1410 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1411 break; 1412 } 1413 } 1414 1415 static void 1416 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1417 { 1418 struct drm_device *dev = encoder->dev; 1419 struct radeon_device *rdev = dev->dev_private; 1420 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1421 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1422 1423 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1424 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1425 radeon_encoder->active_device); 1426 switch (radeon_encoder->encoder_id) { 1427 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1428 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1429 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1430 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1431 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1432 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1433 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1434 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1435 radeon_atom_encoder_dpms_avivo(encoder, mode); 1436 break; 1437 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1438 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1439 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1440 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1441 radeon_atom_encoder_dpms_dig(encoder, mode); 1442 break; 1443 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1444 if (ASIC_IS_DCE5(rdev)) { 1445 switch (mode) { 1446 case DRM_MODE_DPMS_ON: 1447 atombios_dvo_setup(encoder, ATOM_ENABLE); 1448 break; 1449 case DRM_MODE_DPMS_STANDBY: 1450 case DRM_MODE_DPMS_SUSPEND: 1451 case DRM_MODE_DPMS_OFF: 1452 atombios_dvo_setup(encoder, ATOM_DISABLE); 1453 break; 1454 } 1455 } else if (ASIC_IS_DCE3(rdev)) 1456 radeon_atom_encoder_dpms_dig(encoder, mode); 1457 else 1458 radeon_atom_encoder_dpms_avivo(encoder, mode); 1459 break; 1460 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1461 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1462 if (ASIC_IS_DCE5(rdev)) { 1463 switch (mode) { 1464 case DRM_MODE_DPMS_ON: 1465 atombios_dac_setup(encoder, ATOM_ENABLE); 1466 break; 1467 case DRM_MODE_DPMS_STANDBY: 1468 case DRM_MODE_DPMS_SUSPEND: 1469 case DRM_MODE_DPMS_OFF: 1470 atombios_dac_setup(encoder, ATOM_DISABLE); 1471 break; 1472 } 1473 } else 1474 radeon_atom_encoder_dpms_avivo(encoder, mode); 1475 break; 1476 default: 1477 return; 1478 } 1479 1480 if (ext_encoder) 1481 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode); 1482 1483 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1484 1485 } 1486 1487 union crtc_source_param { 1488 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1489 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1490 }; 1491 1492 static void 1493 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1494 { 1495 struct drm_device *dev = encoder->dev; 1496 struct radeon_device *rdev = dev->dev_private; 1497 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1498 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1499 union crtc_source_param args; 1500 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1501 uint8_t frev, crev; 1502 struct radeon_encoder_atom_dig *dig; 1503 1504 memset(&args, 0, sizeof(args)); 1505 1506 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1507 return; 1508 1509 switch (frev) { 1510 case 1: 1511 switch (crev) { 1512 case 1: 1513 default: 1514 if (ASIC_IS_AVIVO(rdev)) 1515 args.v1.ucCRTC = radeon_crtc->crtc_id; 1516 else { 1517 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1518 args.v1.ucCRTC = radeon_crtc->crtc_id; 1519 } else { 1520 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1521 } 1522 } 1523 switch (radeon_encoder->encoder_id) { 1524 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1525 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1526 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1527 break; 1528 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1529 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1530 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1531 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1532 else 1533 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1534 break; 1535 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1536 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1537 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1538 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1539 break; 1540 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1541 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1542 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1543 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1544 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1545 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1546 else 1547 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1548 break; 1549 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1550 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1551 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1552 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1553 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1554 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1555 else 1556 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1557 break; 1558 } 1559 break; 1560 case 2: 1561 args.v2.ucCRTC = radeon_crtc->crtc_id; 1562 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1563 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1564 1565 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1566 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1567 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1568 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1569 else 1570 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1571 } else 1572 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1573 switch (radeon_encoder->encoder_id) { 1574 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1575 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1576 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1577 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1578 dig = radeon_encoder->enc_priv; 1579 switch (dig->dig_encoder) { 1580 case 0: 1581 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1582 break; 1583 case 1: 1584 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1585 break; 1586 case 2: 1587 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1588 break; 1589 case 3: 1590 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1591 break; 1592 case 4: 1593 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1594 break; 1595 case 5: 1596 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1597 break; 1598 } 1599 break; 1600 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1601 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1602 break; 1603 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1604 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1605 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1606 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1607 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1608 else 1609 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1610 break; 1611 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1612 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1613 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1614 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1615 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1616 else 1617 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1618 break; 1619 } 1620 break; 1621 } 1622 break; 1623 default: 1624 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1625 return; 1626 } 1627 1628 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1629 1630 /* update scratch regs with new routing */ 1631 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1632 } 1633 1634 static void 1635 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 1636 struct drm_display_mode *mode) 1637 { 1638 struct drm_device *dev = encoder->dev; 1639 struct radeon_device *rdev = dev->dev_private; 1640 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1641 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1642 1643 /* Funky macbooks */ 1644 if ((dev->pdev->device == 0x71C5) && 1645 (dev->pdev->subsystem_vendor == 0x106b) && 1646 (dev->pdev->subsystem_device == 0x0080)) { 1647 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1648 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1649 1650 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1651 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1652 1653 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 1654 } 1655 } 1656 1657 /* set scaler clears this on some chips */ 1658 if (ASIC_IS_AVIVO(rdev) && 1659 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 1660 if (ASIC_IS_DCE4(rdev)) { 1661 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1662 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 1663 EVERGREEN_INTERLEAVE_EN); 1664 else 1665 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1666 } else { 1667 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1668 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1669 AVIVO_D1MODE_INTERLEAVE_EN); 1670 else 1671 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1672 } 1673 } 1674 } 1675 1676 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 1677 { 1678 struct drm_device *dev = encoder->dev; 1679 struct radeon_device *rdev = dev->dev_private; 1680 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1681 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1682 struct drm_encoder *test_encoder; 1683 struct radeon_encoder_atom_dig *dig; 1684 uint32_t dig_enc_in_use = 0; 1685 1686 /* DCE4/5 */ 1687 if (ASIC_IS_DCE4(rdev)) { 1688 dig = radeon_encoder->enc_priv; 1689 if (ASIC_IS_DCE41(rdev)) { 1690 /* ontario follows DCE4 */ 1691 if (rdev->family == CHIP_PALM) { 1692 if (dig->linkb) 1693 return 1; 1694 else 1695 return 0; 1696 } else 1697 /* llano follows DCE3.2 */ 1698 return radeon_crtc->crtc_id; 1699 } else { 1700 switch (radeon_encoder->encoder_id) { 1701 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1702 if (dig->linkb) 1703 return 1; 1704 else 1705 return 0; 1706 break; 1707 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1708 if (dig->linkb) 1709 return 3; 1710 else 1711 return 2; 1712 break; 1713 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1714 if (dig->linkb) 1715 return 5; 1716 else 1717 return 4; 1718 break; 1719 } 1720 } 1721 } 1722 1723 /* on DCE32 and encoder can driver any block so just crtc id */ 1724 if (ASIC_IS_DCE32(rdev)) { 1725 return radeon_crtc->crtc_id; 1726 } 1727 1728 /* on DCE3 - LVTMA can only be driven by DIGB */ 1729 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1730 struct radeon_encoder *radeon_test_encoder; 1731 1732 if (encoder == test_encoder) 1733 continue; 1734 1735 if (!radeon_encoder_is_digital(test_encoder)) 1736 continue; 1737 1738 radeon_test_encoder = to_radeon_encoder(test_encoder); 1739 dig = radeon_test_encoder->enc_priv; 1740 1741 if (dig->dig_encoder >= 0) 1742 dig_enc_in_use |= (1 << dig->dig_encoder); 1743 } 1744 1745 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 1746 if (dig_enc_in_use & 0x2) 1747 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 1748 return 1; 1749 } 1750 if (!(dig_enc_in_use & 1)) 1751 return 0; 1752 return 1; 1753 } 1754 1755 /* This only needs to be called once at startup */ 1756 void 1757 radeon_atom_encoder_init(struct radeon_device *rdev) 1758 { 1759 struct drm_device *dev = rdev->ddev; 1760 struct drm_encoder *encoder; 1761 1762 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1763 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1764 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1765 1766 switch (radeon_encoder->encoder_id) { 1767 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1768 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1769 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1770 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1771 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 1772 break; 1773 default: 1774 break; 1775 } 1776 1777 if (ext_encoder && ASIC_IS_DCE41(rdev)) 1778 atombios_external_encoder_setup(encoder, ext_encoder, 1779 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 1780 } 1781 } 1782 1783 static void 1784 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 1785 struct drm_display_mode *mode, 1786 struct drm_display_mode *adjusted_mode) 1787 { 1788 struct drm_device *dev = encoder->dev; 1789 struct radeon_device *rdev = dev->dev_private; 1790 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1791 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1792 1793 radeon_encoder->pixel_clock = adjusted_mode->clock; 1794 1795 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 1796 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 1797 atombios_yuv_setup(encoder, true); 1798 else 1799 atombios_yuv_setup(encoder, false); 1800 } 1801 1802 switch (radeon_encoder->encoder_id) { 1803 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1804 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1805 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1806 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1807 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 1808 break; 1809 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1810 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1811 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1812 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1813 if (ASIC_IS_DCE4(rdev)) { 1814 /* disable the transmitter */ 1815 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1816 /* setup and enable the encoder */ 1817 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1818 1819 /* enable the transmitter */ 1820 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1821 } else { 1822 /* disable the encoder and transmitter */ 1823 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1824 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1825 1826 /* setup and enable the encoder and transmitter */ 1827 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1828 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1829 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1830 } 1831 break; 1832 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1833 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1834 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1835 atombios_dvo_setup(encoder, ATOM_ENABLE); 1836 break; 1837 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1838 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1839 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1840 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1841 atombios_dac_setup(encoder, ATOM_ENABLE); 1842 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 1843 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1844 atombios_tv_setup(encoder, ATOM_ENABLE); 1845 else 1846 atombios_tv_setup(encoder, ATOM_DISABLE); 1847 } 1848 break; 1849 } 1850 1851 if (ext_encoder) { 1852 if (ASIC_IS_DCE41(rdev)) 1853 atombios_external_encoder_setup(encoder, ext_encoder, 1854 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1855 else 1856 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1857 } 1858 1859 atombios_apply_encoder_quirks(encoder, adjusted_mode); 1860 1861 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 1862 r600_hdmi_enable(encoder); 1863 r600_hdmi_setmode(encoder, adjusted_mode); 1864 } 1865 } 1866 1867 static bool 1868 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1869 { 1870 struct drm_device *dev = encoder->dev; 1871 struct radeon_device *rdev = dev->dev_private; 1872 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1873 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1874 1875 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 1876 ATOM_DEVICE_CV_SUPPORT | 1877 ATOM_DEVICE_CRT_SUPPORT)) { 1878 DAC_LOAD_DETECTION_PS_ALLOCATION args; 1879 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 1880 uint8_t frev, crev; 1881 1882 memset(&args, 0, sizeof(args)); 1883 1884 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1885 return false; 1886 1887 args.sDacload.ucMisc = 0; 1888 1889 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 1890 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 1891 args.sDacload.ucDacType = ATOM_DAC_A; 1892 else 1893 args.sDacload.ucDacType = ATOM_DAC_B; 1894 1895 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 1896 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 1897 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 1898 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 1899 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1900 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 1901 if (crev >= 3) 1902 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1903 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1904 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 1905 if (crev >= 3) 1906 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 1907 } 1908 1909 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1910 1911 return true; 1912 } else 1913 return false; 1914 } 1915 1916 static enum drm_connector_status 1917 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1918 { 1919 struct drm_device *dev = encoder->dev; 1920 struct radeon_device *rdev = dev->dev_private; 1921 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1922 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1923 uint32_t bios_0_scratch; 1924 1925 if (!atombios_dac_load_detect(encoder, connector)) { 1926 DRM_DEBUG_KMS("detect returned false \n"); 1927 return connector_status_unknown; 1928 } 1929 1930 if (rdev->family >= CHIP_R600) 1931 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 1932 else 1933 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 1934 1935 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 1936 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1937 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 1938 return connector_status_connected; 1939 } 1940 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1941 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 1942 return connector_status_connected; 1943 } 1944 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1945 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 1946 return connector_status_connected; 1947 } 1948 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1949 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 1950 return connector_status_connected; /* CTV */ 1951 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 1952 return connector_status_connected; /* STV */ 1953 } 1954 return connector_status_disconnected; 1955 } 1956 1957 static enum drm_connector_status 1958 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 1959 { 1960 struct drm_device *dev = encoder->dev; 1961 struct radeon_device *rdev = dev->dev_private; 1962 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1963 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1964 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1965 u32 bios_0_scratch; 1966 1967 if (!ASIC_IS_DCE4(rdev)) 1968 return connector_status_unknown; 1969 1970 if (!ext_encoder) 1971 return connector_status_unknown; 1972 1973 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 1974 return connector_status_unknown; 1975 1976 /* load detect on the dp bridge */ 1977 atombios_external_encoder_setup(encoder, ext_encoder, 1978 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 1979 1980 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 1981 1982 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 1983 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 1984 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 1985 return connector_status_connected; 1986 } 1987 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 1988 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 1989 return connector_status_connected; 1990 } 1991 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 1992 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 1993 return connector_status_connected; 1994 } 1995 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 1996 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 1997 return connector_status_connected; /* CTV */ 1998 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 1999 return connector_status_connected; /* STV */ 2000 } 2001 return connector_status_disconnected; 2002 } 2003 2004 void 2005 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2006 { 2007 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2008 2009 if (ext_encoder) 2010 /* ddc_setup on the dp bridge */ 2011 atombios_external_encoder_setup(encoder, ext_encoder, 2012 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2013 2014 } 2015 2016 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2017 { 2018 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2019 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2020 2021 if ((radeon_encoder->active_device & 2022 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2023 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2024 ENCODER_OBJECT_ID_NONE)) { 2025 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2026 if (dig) 2027 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 2028 } 2029 2030 radeon_atom_output_lock(encoder, true); 2031 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2032 2033 if (connector) { 2034 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2035 2036 /* select the clock/data port if it uses a router */ 2037 if (radeon_connector->router.cd_valid) 2038 radeon_router_select_cd_port(radeon_connector); 2039 2040 /* turn eDP panel on for mode set */ 2041 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2042 atombios_set_edp_panel_power(connector, 2043 ATOM_TRANSMITTER_ACTION_POWER_ON); 2044 } 2045 2046 /* this is needed for the pll/ss setup to work correctly in some cases */ 2047 atombios_set_encoder_crtc_source(encoder); 2048 } 2049 2050 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2051 { 2052 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2053 radeon_atom_output_lock(encoder, false); 2054 } 2055 2056 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2057 { 2058 struct drm_device *dev = encoder->dev; 2059 struct radeon_device *rdev = dev->dev_private; 2060 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2061 struct radeon_encoder_atom_dig *dig; 2062 2063 /* check for pre-DCE3 cards with shared encoders; 2064 * can't really use the links individually, so don't disable 2065 * the encoder if it's in use by another connector 2066 */ 2067 if (!ASIC_IS_DCE3(rdev)) { 2068 struct drm_encoder *other_encoder; 2069 struct radeon_encoder *other_radeon_encoder; 2070 2071 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2072 other_radeon_encoder = to_radeon_encoder(other_encoder); 2073 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2074 drm_helper_encoder_in_use(other_encoder)) 2075 goto disable_done; 2076 } 2077 } 2078 2079 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2080 2081 switch (radeon_encoder->encoder_id) { 2082 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2083 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2084 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2085 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2086 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2087 break; 2088 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2089 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2090 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2091 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2092 if (ASIC_IS_DCE4(rdev)) 2093 /* disable the transmitter */ 2094 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 2095 else { 2096 /* disable the encoder and transmitter */ 2097 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 2098 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 2099 } 2100 break; 2101 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2102 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2103 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2104 atombios_dvo_setup(encoder, ATOM_DISABLE); 2105 break; 2106 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2107 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2108 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2109 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2110 atombios_dac_setup(encoder, ATOM_DISABLE); 2111 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2112 atombios_tv_setup(encoder, ATOM_DISABLE); 2113 break; 2114 } 2115 2116 disable_done: 2117 if (radeon_encoder_is_digital(encoder)) { 2118 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 2119 r600_hdmi_disable(encoder); 2120 dig = radeon_encoder->enc_priv; 2121 dig->dig_encoder = -1; 2122 } 2123 radeon_encoder->active_device = 0; 2124 } 2125 2126 /* these are handled by the primary encoders */ 2127 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2128 { 2129 2130 } 2131 2132 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2133 { 2134 2135 } 2136 2137 static void 2138 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2139 struct drm_display_mode *mode, 2140 struct drm_display_mode *adjusted_mode) 2141 { 2142 2143 } 2144 2145 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2146 { 2147 2148 } 2149 2150 static void 2151 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2152 { 2153 2154 } 2155 2156 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 2157 struct drm_display_mode *mode, 2158 struct drm_display_mode *adjusted_mode) 2159 { 2160 return true; 2161 } 2162 2163 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2164 .dpms = radeon_atom_ext_dpms, 2165 .mode_fixup = radeon_atom_ext_mode_fixup, 2166 .prepare = radeon_atom_ext_prepare, 2167 .mode_set = radeon_atom_ext_mode_set, 2168 .commit = radeon_atom_ext_commit, 2169 .disable = radeon_atom_ext_disable, 2170 /* no detect for TMDS/LVDS yet */ 2171 }; 2172 2173 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2174 .dpms = radeon_atom_encoder_dpms, 2175 .mode_fixup = radeon_atom_mode_fixup, 2176 .prepare = radeon_atom_encoder_prepare, 2177 .mode_set = radeon_atom_encoder_mode_set, 2178 .commit = radeon_atom_encoder_commit, 2179 .disable = radeon_atom_encoder_disable, 2180 .detect = radeon_atom_dig_detect, 2181 }; 2182 2183 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2184 .dpms = radeon_atom_encoder_dpms, 2185 .mode_fixup = radeon_atom_mode_fixup, 2186 .prepare = radeon_atom_encoder_prepare, 2187 .mode_set = radeon_atom_encoder_mode_set, 2188 .commit = radeon_atom_encoder_commit, 2189 .detect = radeon_atom_dac_detect, 2190 }; 2191 2192 void radeon_enc_destroy(struct drm_encoder *encoder) 2193 { 2194 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2195 kfree(radeon_encoder->enc_priv); 2196 drm_encoder_cleanup(encoder); 2197 kfree(radeon_encoder); 2198 } 2199 2200 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2201 .destroy = radeon_enc_destroy, 2202 }; 2203 2204 struct radeon_encoder_atom_dac * 2205 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2206 { 2207 struct drm_device *dev = radeon_encoder->base.dev; 2208 struct radeon_device *rdev = dev->dev_private; 2209 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2210 2211 if (!dac) 2212 return NULL; 2213 2214 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2215 return dac; 2216 } 2217 2218 struct radeon_encoder_atom_dig * 2219 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2220 { 2221 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2222 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2223 2224 if (!dig) 2225 return NULL; 2226 2227 /* coherent mode by default */ 2228 dig->coherent_mode = true; 2229 dig->dig_encoder = -1; 2230 2231 if (encoder_enum == 2) 2232 dig->linkb = true; 2233 else 2234 dig->linkb = false; 2235 2236 return dig; 2237 } 2238 2239 void 2240 radeon_add_atom_encoder(struct drm_device *dev, 2241 uint32_t encoder_enum, 2242 uint32_t supported_device, 2243 u16 caps) 2244 { 2245 struct radeon_device *rdev = dev->dev_private; 2246 struct drm_encoder *encoder; 2247 struct radeon_encoder *radeon_encoder; 2248 2249 /* see if we already added it */ 2250 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2251 radeon_encoder = to_radeon_encoder(encoder); 2252 if (radeon_encoder->encoder_enum == encoder_enum) { 2253 radeon_encoder->devices |= supported_device; 2254 return; 2255 } 2256 2257 } 2258 2259 /* add a new one */ 2260 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2261 if (!radeon_encoder) 2262 return; 2263 2264 encoder = &radeon_encoder->base; 2265 switch (rdev->num_crtc) { 2266 case 1: 2267 encoder->possible_crtcs = 0x1; 2268 break; 2269 case 2: 2270 default: 2271 encoder->possible_crtcs = 0x3; 2272 break; 2273 case 4: 2274 encoder->possible_crtcs = 0xf; 2275 break; 2276 case 6: 2277 encoder->possible_crtcs = 0x3f; 2278 break; 2279 } 2280 2281 radeon_encoder->enc_priv = NULL; 2282 2283 radeon_encoder->encoder_enum = encoder_enum; 2284 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2285 radeon_encoder->devices = supported_device; 2286 radeon_encoder->rmx_type = RMX_OFF; 2287 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2288 radeon_encoder->is_ext_encoder = false; 2289 radeon_encoder->caps = caps; 2290 2291 switch (radeon_encoder->encoder_id) { 2292 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2293 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2294 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2295 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2296 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2297 radeon_encoder->rmx_type = RMX_FULL; 2298 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2299 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2300 } else { 2301 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2302 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2303 } 2304 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2305 break; 2306 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2307 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2308 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2309 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2310 break; 2311 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2312 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2313 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2314 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 2315 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2316 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2317 break; 2318 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2319 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2320 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2321 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2322 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2323 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2324 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2325 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2326 radeon_encoder->rmx_type = RMX_FULL; 2327 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2328 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2329 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2330 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2331 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2332 } else { 2333 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2334 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2335 } 2336 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2337 break; 2338 case ENCODER_OBJECT_ID_SI170B: 2339 case ENCODER_OBJECT_ID_CH7303: 2340 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2341 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2342 case ENCODER_OBJECT_ID_TITFP513: 2343 case ENCODER_OBJECT_ID_VT1623: 2344 case ENCODER_OBJECT_ID_HDMI_SI1930: 2345 case ENCODER_OBJECT_ID_TRAVIS: 2346 case ENCODER_OBJECT_ID_NUTMEG: 2347 /* these are handled by the primary encoders */ 2348 radeon_encoder->is_ext_encoder = true; 2349 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2350 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2351 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2352 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2353 else 2354 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2355 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2356 break; 2357 } 2358 } 2359