1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #include "drmP.h" 28 #include "radeon_drm.h" 29 #include "radeon.h" 30 31 #include "atom.h" 32 #include "atom-bits.h" 33 #include "drm_dp_helper.h" 34 35 /* move these to drm_dp_helper.c/h */ 36 #define DP_LINK_CONFIGURATION_SIZE 9 37 #define DP_LINK_STATUS_SIZE 6 38 #define DP_DPCD_SIZE 8 39 40 static char *voltage_names[] = { 41 "0.4V", "0.6V", "0.8V", "1.2V" 42 }; 43 static char *pre_emph_names[] = { 44 "0dB", "3.5dB", "6dB", "9.5dB" 45 }; 46 47 /***** radeon AUX functions *****/ 48 union aux_channel_transaction { 49 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 50 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 51 }; 52 53 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, 54 u8 *send, int send_bytes, 55 u8 *recv, int recv_size, 56 u8 delay, u8 *ack) 57 { 58 struct drm_device *dev = chan->dev; 59 struct radeon_device *rdev = dev->dev_private; 60 union aux_channel_transaction args; 61 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 62 unsigned char *base; 63 int recv_bytes; 64 65 memset(&args, 0, sizeof(args)); 66 67 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); 68 69 memcpy(base, send, send_bytes); 70 71 args.v1.lpAuxRequest = 0 + 4; 72 args.v1.lpDataOut = 16 + 4; 73 args.v1.ucDataOutLen = 0; 74 args.v1.ucChannelID = chan->rec.i2c_id; 75 args.v1.ucDelay = delay / 10; 76 if (ASIC_IS_DCE4(rdev)) 77 args.v2.ucHPD_ID = chan->rec.hpd; 78 79 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 80 81 *ack = args.v1.ucReplyStatus; 82 83 /* timeout */ 84 if (args.v1.ucReplyStatus == 1) { 85 DRM_DEBUG_KMS("dp_aux_ch timeout\n"); 86 return -ETIMEDOUT; 87 } 88 89 /* flags not zero */ 90 if (args.v1.ucReplyStatus == 2) { 91 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); 92 return -EBUSY; 93 } 94 95 /* error */ 96 if (args.v1.ucReplyStatus == 3) { 97 DRM_DEBUG_KMS("dp_aux_ch error\n"); 98 return -EIO; 99 } 100 101 recv_bytes = args.v1.ucDataOutLen; 102 if (recv_bytes > recv_size) 103 recv_bytes = recv_size; 104 105 if (recv && recv_size) 106 memcpy(recv, base + 16, recv_bytes); 107 108 return recv_bytes; 109 } 110 111 static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, 112 u16 address, u8 *send, u8 send_bytes, u8 delay) 113 { 114 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 115 int ret; 116 u8 msg[20]; 117 int msg_bytes = send_bytes + 4; 118 u8 ack; 119 unsigned retry; 120 121 if (send_bytes > 16) 122 return -1; 123 124 msg[0] = address; 125 msg[1] = address >> 8; 126 msg[2] = AUX_NATIVE_WRITE << 4; 127 msg[3] = (msg_bytes << 4) | (send_bytes - 1); 128 memcpy(&msg[4], send, send_bytes); 129 130 for (retry = 0; retry < 4; retry++) { 131 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 132 msg, msg_bytes, NULL, 0, delay, &ack); 133 if (ret == -EBUSY) 134 continue; 135 else if (ret < 0) 136 return ret; 137 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 138 return send_bytes; 139 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 140 udelay(400); 141 else 142 return -EIO; 143 } 144 145 return -EIO; 146 } 147 148 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, 149 u16 address, u8 *recv, int recv_bytes, u8 delay) 150 { 151 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 152 u8 msg[4]; 153 int msg_bytes = 4; 154 u8 ack; 155 int ret; 156 unsigned retry; 157 158 msg[0] = address; 159 msg[1] = address >> 8; 160 msg[2] = AUX_NATIVE_READ << 4; 161 msg[3] = (msg_bytes << 4) | (recv_bytes - 1); 162 163 for (retry = 0; retry < 4; retry++) { 164 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 165 msg, msg_bytes, recv, recv_bytes, delay, &ack); 166 if (ret == -EBUSY) 167 continue; 168 else if (ret < 0) 169 return ret; 170 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 171 return ret; 172 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 173 udelay(400); 174 else if (ret == 0) 175 return -EPROTO; 176 else 177 return -EIO; 178 } 179 180 return -EIO; 181 } 182 183 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector, 184 u16 reg, u8 val) 185 { 186 radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0); 187 } 188 189 static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector, 190 u16 reg) 191 { 192 u8 val = 0; 193 194 radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0); 195 196 return val; 197 } 198 199 int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 200 u8 write_byte, u8 *read_byte) 201 { 202 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 203 struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter; 204 u16 address = algo_data->address; 205 u8 msg[5]; 206 u8 reply[2]; 207 unsigned retry; 208 int msg_bytes; 209 int reply_bytes = 1; 210 int ret; 211 u8 ack; 212 213 /* Set up the command byte */ 214 if (mode & MODE_I2C_READ) 215 msg[2] = AUX_I2C_READ << 4; 216 else 217 msg[2] = AUX_I2C_WRITE << 4; 218 219 if (!(mode & MODE_I2C_STOP)) 220 msg[2] |= AUX_I2C_MOT << 4; 221 222 msg[0] = address; 223 msg[1] = address >> 8; 224 225 switch (mode) { 226 case MODE_I2C_WRITE: 227 msg_bytes = 5; 228 msg[3] = msg_bytes << 4; 229 msg[4] = write_byte; 230 break; 231 case MODE_I2C_READ: 232 msg_bytes = 4; 233 msg[3] = msg_bytes << 4; 234 break; 235 default: 236 msg_bytes = 4; 237 msg[3] = 3 << 4; 238 break; 239 } 240 241 for (retry = 0; retry < 4; retry++) { 242 ret = radeon_process_aux_ch(auxch, 243 msg, msg_bytes, reply, reply_bytes, 0, &ack); 244 if (ret == -EBUSY) 245 continue; 246 else if (ret < 0) { 247 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 248 return ret; 249 } 250 251 switch (ack & AUX_NATIVE_REPLY_MASK) { 252 case AUX_NATIVE_REPLY_ACK: 253 /* I2C-over-AUX Reply field is only valid 254 * when paired with AUX ACK. 255 */ 256 break; 257 case AUX_NATIVE_REPLY_NACK: 258 DRM_DEBUG_KMS("aux_ch native nack\n"); 259 return -EREMOTEIO; 260 case AUX_NATIVE_REPLY_DEFER: 261 DRM_DEBUG_KMS("aux_ch native defer\n"); 262 udelay(400); 263 continue; 264 default: 265 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack); 266 return -EREMOTEIO; 267 } 268 269 switch (ack & AUX_I2C_REPLY_MASK) { 270 case AUX_I2C_REPLY_ACK: 271 if (mode == MODE_I2C_READ) 272 *read_byte = reply[0]; 273 return ret; 274 case AUX_I2C_REPLY_NACK: 275 DRM_DEBUG_KMS("aux_i2c nack\n"); 276 return -EREMOTEIO; 277 case AUX_I2C_REPLY_DEFER: 278 DRM_DEBUG_KMS("aux_i2c defer\n"); 279 udelay(400); 280 break; 281 default: 282 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); 283 return -EREMOTEIO; 284 } 285 } 286 287 DRM_DEBUG_KMS("aux i2c too many retries, giving up\n"); 288 return -EREMOTEIO; 289 } 290 291 /***** general DP utility functions *****/ 292 293 static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r) 294 { 295 return link_status[r - DP_LANE0_1_STATUS]; 296 } 297 298 static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE], 299 int lane) 300 { 301 int i = DP_LANE0_1_STATUS + (lane >> 1); 302 int s = (lane & 1) * 4; 303 u8 l = dp_link_status(link_status, i); 304 return (l >> s) & 0xf; 305 } 306 307 static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], 308 int lane_count) 309 { 310 int lane; 311 u8 lane_status; 312 313 for (lane = 0; lane < lane_count; lane++) { 314 lane_status = dp_get_lane_status(link_status, lane); 315 if ((lane_status & DP_LANE_CR_DONE) == 0) 316 return false; 317 } 318 return true; 319 } 320 321 static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], 322 int lane_count) 323 { 324 u8 lane_align; 325 u8 lane_status; 326 int lane; 327 328 lane_align = dp_link_status(link_status, 329 DP_LANE_ALIGN_STATUS_UPDATED); 330 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 331 return false; 332 for (lane = 0; lane < lane_count; lane++) { 333 lane_status = dp_get_lane_status(link_status, lane); 334 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) 335 return false; 336 } 337 return true; 338 } 339 340 static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], 341 int lane) 342 343 { 344 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 345 int s = ((lane & 1) ? 346 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 347 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 348 u8 l = dp_link_status(link_status, i); 349 350 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 351 } 352 353 static u8 dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], 354 int lane) 355 { 356 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 357 int s = ((lane & 1) ? 358 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 359 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 360 u8 l = dp_link_status(link_status, i); 361 362 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 363 } 364 365 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 366 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 367 368 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], 369 int lane_count, 370 u8 train_set[4]) 371 { 372 u8 v = 0; 373 u8 p = 0; 374 int lane; 375 376 for (lane = 0; lane < lane_count; lane++) { 377 u8 this_v = dp_get_adjust_request_voltage(link_status, lane); 378 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane); 379 380 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", 381 lane, 382 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 383 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 384 385 if (this_v > v) 386 v = this_v; 387 if (this_p > p) 388 p = this_p; 389 } 390 391 if (v >= DP_VOLTAGE_MAX) 392 v |= DP_TRAIN_MAX_SWING_REACHED; 393 394 if (p >= DP_PRE_EMPHASIS_MAX) 395 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 396 397 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", 398 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 399 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 400 401 for (lane = 0; lane < 4; lane++) 402 train_set[lane] = v | p; 403 } 404 405 /* convert bits per color to bits per pixel */ 406 /* get bpc from the EDID */ 407 static int convert_bpc_to_bpp(int bpc) 408 { 409 if (bpc == 0) 410 return 24; 411 else 412 return bpc * 3; 413 } 414 415 /* get the max pix clock supported by the link rate and lane num */ 416 static int dp_get_max_dp_pix_clock(int link_rate, 417 int lane_num, 418 int bpp) 419 { 420 return (link_rate * lane_num * 8) / bpp; 421 } 422 423 static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE]) 424 { 425 switch (dpcd[DP_MAX_LINK_RATE]) { 426 case DP_LINK_BW_1_62: 427 default: 428 return 162000; 429 case DP_LINK_BW_2_7: 430 return 270000; 431 case DP_LINK_BW_5_4: 432 return 540000; 433 } 434 } 435 436 static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE]) 437 { 438 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 439 } 440 441 static u8 dp_get_dp_link_rate_coded(int link_rate) 442 { 443 switch (link_rate) { 444 case 162000: 445 default: 446 return DP_LINK_BW_1_62; 447 case 270000: 448 return DP_LINK_BW_2_7; 449 case 540000: 450 return DP_LINK_BW_5_4; 451 } 452 } 453 454 /***** radeon specific DP functions *****/ 455 456 /* First get the min lane# when low rate is used according to pixel clock 457 * (prefer low rate), second check max lane# supported by DP panel, 458 * if the max lane# < low rate lane# then use max lane# instead. 459 */ 460 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, 461 u8 dpcd[DP_DPCD_SIZE], 462 int pix_clock) 463 { 464 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 465 int max_link_rate = dp_get_max_link_rate(dpcd); 466 int max_lane_num = dp_get_max_lane_number(dpcd); 467 int lane_num; 468 int max_dp_pix_clock; 469 470 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { 471 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); 472 if (pix_clock <= max_dp_pix_clock) 473 break; 474 } 475 476 return lane_num; 477 } 478 479 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, 480 u8 dpcd[DP_DPCD_SIZE], 481 int pix_clock) 482 { 483 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 484 int lane_num, max_pix_clock; 485 486 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 487 ENCODER_OBJECT_ID_NUTMEG) 488 return 270000; 489 490 lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); 491 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); 492 if (pix_clock <= max_pix_clock) 493 return 162000; 494 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); 495 if (pix_clock <= max_pix_clock) 496 return 270000; 497 if (radeon_connector_is_dp12_capable(connector)) { 498 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); 499 if (pix_clock <= max_pix_clock) 500 return 540000; 501 } 502 503 return dp_get_max_link_rate(dpcd); 504 } 505 506 static u8 radeon_dp_encoder_service(struct radeon_device *rdev, 507 int action, int dp_clock, 508 u8 ucconfig, u8 lane_num) 509 { 510 DP_ENCODER_SERVICE_PARAMETERS args; 511 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 512 513 memset(&args, 0, sizeof(args)); 514 args.ucLinkClock = dp_clock / 10; 515 args.ucConfig = ucconfig; 516 args.ucAction = action; 517 args.ucLaneNum = lane_num; 518 args.ucStatus = 0; 519 520 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 521 return args.ucStatus; 522 } 523 524 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) 525 { 526 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 527 struct drm_device *dev = radeon_connector->base.dev; 528 struct radeon_device *rdev = dev->dev_private; 529 530 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, 531 dig_connector->dp_i2c_bus->rec.i2c_id, 0); 532 } 533 534 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) 535 { 536 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 537 u8 buf[3]; 538 539 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 540 return; 541 542 if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0)) 543 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 544 buf[0], buf[1], buf[2]); 545 546 if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0)) 547 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 548 buf[0], buf[1], buf[2]); 549 } 550 551 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) 552 { 553 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 554 u8 msg[25]; 555 int ret, i; 556 557 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8, 0); 558 if (ret > 0) { 559 memcpy(dig_connector->dpcd, msg, 8); 560 DRM_DEBUG_KMS("DPCD: "); 561 for (i = 0; i < 8; i++) 562 DRM_DEBUG_KMS("%02x ", msg[i]); 563 DRM_DEBUG_KMS("\n"); 564 565 radeon_dp_probe_oui(radeon_connector); 566 567 return true; 568 } 569 dig_connector->dpcd[0] = 0; 570 return false; 571 } 572 573 int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 574 struct drm_connector *connector) 575 { 576 struct drm_device *dev = encoder->dev; 577 struct radeon_device *rdev = dev->dev_private; 578 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 579 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 580 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); 581 u8 tmp; 582 583 if (!ASIC_IS_DCE4(rdev)) 584 return panel_mode; 585 586 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 587 /* DP bridge chips */ 588 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); 589 if (tmp & 1) 590 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 591 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 592 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 593 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 594 else 595 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 596 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 597 /* eDP */ 598 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); 599 if (tmp & 1) 600 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 601 } 602 603 return panel_mode; 604 } 605 606 void radeon_dp_set_link_config(struct drm_connector *connector, 607 const struct drm_display_mode *mode) 608 { 609 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 610 struct radeon_connector_atom_dig *dig_connector; 611 612 if (!radeon_connector->con_priv) 613 return; 614 dig_connector = radeon_connector->con_priv; 615 616 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 617 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 618 dig_connector->dp_clock = 619 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 620 dig_connector->dp_lane_count = 621 radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); 622 } 623 } 624 625 int radeon_dp_mode_valid_helper(struct drm_connector *connector, 626 struct drm_display_mode *mode) 627 { 628 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 629 struct radeon_connector_atom_dig *dig_connector; 630 int dp_clock; 631 632 if (!radeon_connector->con_priv) 633 return MODE_CLOCK_HIGH; 634 dig_connector = radeon_connector->con_priv; 635 636 dp_clock = 637 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); 638 639 if ((dp_clock == 540000) && 640 (!radeon_connector_is_dp12_capable(connector))) 641 return MODE_CLOCK_HIGH; 642 643 return MODE_OK; 644 } 645 646 static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector, 647 u8 link_status[DP_LINK_STATUS_SIZE]) 648 { 649 int ret; 650 ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 651 link_status, DP_LINK_STATUS_SIZE, 100); 652 if (ret <= 0) { 653 return false; 654 } 655 656 DRM_DEBUG_KMS("link status %02x %02x %02x %02x %02x %02x\n", 657 link_status[0], link_status[1], link_status[2], 658 link_status[3], link_status[4], link_status[5]); 659 return true; 660 } 661 662 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) 663 { 664 u8 link_status[DP_LINK_STATUS_SIZE]; 665 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 666 667 if (!radeon_dp_get_link_status(radeon_connector, link_status)) 668 return false; 669 if (dp_channel_eq_ok(link_status, dig->dp_lane_count)) 670 return false; 671 return true; 672 } 673 674 struct radeon_dp_link_train_info { 675 struct radeon_device *rdev; 676 struct drm_encoder *encoder; 677 struct drm_connector *connector; 678 struct radeon_connector *radeon_connector; 679 int enc_id; 680 int dp_clock; 681 int dp_lane_count; 682 int rd_interval; 683 bool tp3_supported; 684 u8 dpcd[8]; 685 u8 train_set[4]; 686 u8 link_status[DP_LINK_STATUS_SIZE]; 687 u8 tries; 688 bool use_dpencoder; 689 }; 690 691 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) 692 { 693 /* set the initial vs/emph on the source */ 694 atombios_dig_transmitter_setup(dp_info->encoder, 695 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, 696 0, dp_info->train_set[0]); /* sets all lanes at once */ 697 698 /* set the vs/emph on the sink */ 699 radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET, 700 dp_info->train_set, dp_info->dp_lane_count, 0); 701 } 702 703 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) 704 { 705 int rtp = 0; 706 707 /* set training pattern on the source */ 708 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { 709 switch (tp) { 710 case DP_TRAINING_PATTERN_1: 711 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; 712 break; 713 case DP_TRAINING_PATTERN_2: 714 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; 715 break; 716 case DP_TRAINING_PATTERN_3: 717 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; 718 break; 719 } 720 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); 721 } else { 722 switch (tp) { 723 case DP_TRAINING_PATTERN_1: 724 rtp = 0; 725 break; 726 case DP_TRAINING_PATTERN_2: 727 rtp = 1; 728 break; 729 } 730 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, 731 dp_info->dp_clock, dp_info->enc_id, rtp); 732 } 733 734 /* enable training pattern on the sink */ 735 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp); 736 } 737 738 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 739 { 740 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); 741 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 742 u8 tmp; 743 744 /* power up the sink */ 745 if (dp_info->dpcd[0] >= 0x11) 746 radeon_write_dpcd_reg(dp_info->radeon_connector, 747 DP_SET_POWER, DP_SET_POWER_D0); 748 749 /* possibly enable downspread on the sink */ 750 if (dp_info->dpcd[3] & 0x1) 751 radeon_write_dpcd_reg(dp_info->radeon_connector, 752 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); 753 else 754 radeon_write_dpcd_reg(dp_info->radeon_connector, 755 DP_DOWNSPREAD_CTRL, 0); 756 757 if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && 758 (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { 759 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1); 760 } 761 762 /* set the lane count on the sink */ 763 tmp = dp_info->dp_lane_count; 764 if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 && 765 dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP) 766 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 767 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); 768 769 /* set the link rate on the sink */ 770 tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock); 771 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp); 772 773 /* start training on the source */ 774 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 775 atombios_dig_encoder_setup(dp_info->encoder, 776 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); 777 else 778 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, 779 dp_info->dp_clock, dp_info->enc_id, 0); 780 781 /* disable the training pattern on the sink */ 782 radeon_write_dpcd_reg(dp_info->radeon_connector, 783 DP_TRAINING_PATTERN_SET, 784 DP_TRAINING_PATTERN_DISABLE); 785 786 return 0; 787 } 788 789 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) 790 { 791 udelay(400); 792 793 /* disable the training pattern on the sink */ 794 radeon_write_dpcd_reg(dp_info->radeon_connector, 795 DP_TRAINING_PATTERN_SET, 796 DP_TRAINING_PATTERN_DISABLE); 797 798 /* disable the training pattern on the source */ 799 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 800 atombios_dig_encoder_setup(dp_info->encoder, 801 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); 802 else 803 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, 804 dp_info->dp_clock, dp_info->enc_id, 0); 805 806 return 0; 807 } 808 809 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) 810 { 811 bool clock_recovery; 812 u8 voltage; 813 int i; 814 815 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); 816 memset(dp_info->train_set, 0, 4); 817 radeon_dp_update_vs_emph(dp_info); 818 819 udelay(400); 820 821 /* clock recovery loop */ 822 clock_recovery = false; 823 dp_info->tries = 0; 824 voltage = 0xff; 825 while (1) { 826 if (dp_info->rd_interval == 0) 827 udelay(100); 828 else 829 mdelay(dp_info->rd_interval * 4); 830 831 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { 832 DRM_ERROR("displayport link status failed\n"); 833 break; 834 } 835 836 if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { 837 clock_recovery = true; 838 break; 839 } 840 841 for (i = 0; i < dp_info->dp_lane_count; i++) { 842 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 843 break; 844 } 845 if (i == dp_info->dp_lane_count) { 846 DRM_ERROR("clock recovery reached max voltage\n"); 847 break; 848 } 849 850 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 851 ++dp_info->tries; 852 if (dp_info->tries == 5) { 853 DRM_ERROR("clock recovery tried 5 times\n"); 854 break; 855 } 856 } else 857 dp_info->tries = 0; 858 859 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 860 861 /* Compute new train_set as requested by sink */ 862 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 863 864 radeon_dp_update_vs_emph(dp_info); 865 } 866 if (!clock_recovery) { 867 DRM_ERROR("clock recovery failed\n"); 868 return -1; 869 } else { 870 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", 871 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 872 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 873 DP_TRAIN_PRE_EMPHASIS_SHIFT); 874 return 0; 875 } 876 } 877 878 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) 879 { 880 bool channel_eq; 881 882 if (dp_info->tp3_supported) 883 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); 884 else 885 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); 886 887 /* channel equalization loop */ 888 dp_info->tries = 0; 889 channel_eq = false; 890 while (1) { 891 if (dp_info->rd_interval == 0) 892 udelay(400); 893 else 894 mdelay(dp_info->rd_interval * 4); 895 896 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { 897 DRM_ERROR("displayport link status failed\n"); 898 break; 899 } 900 901 if (dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { 902 channel_eq = true; 903 break; 904 } 905 906 /* Try 5 times */ 907 if (dp_info->tries > 5) { 908 DRM_ERROR("channel eq failed: 5 tries\n"); 909 break; 910 } 911 912 /* Compute new train_set as requested by sink */ 913 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 914 915 radeon_dp_update_vs_emph(dp_info); 916 dp_info->tries++; 917 } 918 919 if (!channel_eq) { 920 DRM_ERROR("channel eq failed\n"); 921 return -1; 922 } else { 923 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", 924 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 925 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 926 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 927 return 0; 928 } 929 } 930 931 void radeon_dp_link_train(struct drm_encoder *encoder, 932 struct drm_connector *connector) 933 { 934 struct drm_device *dev = encoder->dev; 935 struct radeon_device *rdev = dev->dev_private; 936 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 937 struct radeon_encoder_atom_dig *dig; 938 struct radeon_connector *radeon_connector; 939 struct radeon_connector_atom_dig *dig_connector; 940 struct radeon_dp_link_train_info dp_info; 941 int index; 942 u8 tmp, frev, crev; 943 944 if (!radeon_encoder->enc_priv) 945 return; 946 dig = radeon_encoder->enc_priv; 947 948 radeon_connector = to_radeon_connector(connector); 949 if (!radeon_connector->con_priv) 950 return; 951 dig_connector = radeon_connector->con_priv; 952 953 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && 954 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) 955 return; 956 957 /* DPEncoderService newer than 1.1 can't program properly the 958 * training pattern. When facing such version use the 959 * DIGXEncoderControl (X== 1 | 2) 960 */ 961 dp_info.use_dpencoder = true; 962 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 963 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { 964 if (crev > 1) { 965 dp_info.use_dpencoder = false; 966 } 967 } 968 969 dp_info.enc_id = 0; 970 if (dig->dig_encoder) 971 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 972 else 973 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 974 if (dig->linkb) 975 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; 976 else 977 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; 978 979 dp_info.rd_interval = radeon_read_dpcd_reg(radeon_connector, DP_TRAINING_AUX_RD_INTERVAL); 980 tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT); 981 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 982 dp_info.tp3_supported = true; 983 else 984 dp_info.tp3_supported = false; 985 986 memcpy(dp_info.dpcd, dig_connector->dpcd, 8); 987 dp_info.rdev = rdev; 988 dp_info.encoder = encoder; 989 dp_info.connector = connector; 990 dp_info.radeon_connector = radeon_connector; 991 dp_info.dp_lane_count = dig_connector->dp_lane_count; 992 dp_info.dp_clock = dig_connector->dp_clock; 993 994 if (radeon_dp_link_train_init(&dp_info)) 995 goto done; 996 if (radeon_dp_link_train_cr(&dp_info)) 997 goto done; 998 if (radeon_dp_link_train_ce(&dp_info)) 999 goto done; 1000 done: 1001 if (radeon_dp_link_train_finish(&dp_info)) 1002 return; 1003 } 1004