1 /* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Dave Airlie 23 * Alon Levy 24 */ 25 26 #include <linux/io-mapping.h> 27 #include <linux/pci.h> 28 29 #include <drm/drm_drv.h> 30 #include <drm/drm_managed.h> 31 #include <drm/drm_print.h> 32 #include <drm/drm_probe_helper.h> 33 34 #include "qxl_drv.h" 35 #include "qxl_object.h" 36 37 static bool qxl_check_device(struct qxl_device *qdev) 38 { 39 struct qxl_rom *rom = qdev->rom; 40 41 if (rom->magic != 0x4f525851) { 42 DRM_ERROR("bad rom signature %x\n", rom->magic); 43 return false; 44 } 45 46 DRM_INFO("Device Version %d.%d\n", rom->id, rom->update_id); 47 DRM_INFO("Compression level %d log level %d\n", rom->compression_level, 48 rom->log_level); 49 DRM_INFO("%d io pages at offset 0x%x\n", 50 rom->num_io_pages, rom->pages_offset); 51 DRM_INFO("%d byte draw area at offset 0x%x\n", 52 rom->surface0_area_size, rom->draw_area_offset); 53 54 qdev->vram_size = rom->surface0_area_size; 55 DRM_INFO("RAM header offset: 0x%x\n", rom->ram_header_offset); 56 return true; 57 } 58 59 static void setup_hw_slot(struct qxl_device *qdev, struct qxl_memslot *slot) 60 { 61 qdev->ram_header->mem_slot.mem_start = slot->start_phys_addr; 62 qdev->ram_header->mem_slot.mem_end = slot->start_phys_addr + slot->size; 63 qxl_io_memslot_add(qdev, qdev->rom->slots_start + slot->index); 64 } 65 66 static void setup_slot(struct qxl_device *qdev, 67 struct qxl_memslot *slot, 68 unsigned int slot_index, 69 const char *slot_name, 70 unsigned long start_phys_addr, 71 unsigned long size) 72 { 73 uint64_t high_bits; 74 75 slot->index = slot_index; 76 slot->name = slot_name; 77 slot->start_phys_addr = start_phys_addr; 78 slot->size = size; 79 80 setup_hw_slot(qdev, slot); 81 82 slot->generation = qdev->rom->slot_generation; 83 high_bits = (qdev->rom->slots_start + slot->index) 84 << qdev->rom->slot_gen_bits; 85 high_bits |= slot->generation; 86 high_bits <<= (64 - (qdev->rom->slot_gen_bits + qdev->rom->slot_id_bits)); 87 slot->high_bits = high_bits; 88 89 DRM_INFO("slot %d (%s): base 0x%08lx, size 0x%08lx\n", 90 slot->index, slot->name, 91 (unsigned long)slot->start_phys_addr, 92 (unsigned long)slot->size); 93 } 94 95 void qxl_reinit_memslots(struct qxl_device *qdev) 96 { 97 setup_hw_slot(qdev, &qdev->main_slot); 98 setup_hw_slot(qdev, &qdev->surfaces_slot); 99 } 100 101 static void qxl_gc_work(struct work_struct *work) 102 { 103 struct qxl_device *qdev = container_of(work, struct qxl_device, gc_work); 104 105 qxl_garbage_collect(qdev); 106 } 107 108 int qxl_device_init(struct qxl_device *qdev, 109 struct pci_dev *pdev) 110 { 111 int r, sb; 112 113 pci_set_drvdata(pdev, &qdev->ddev); 114 115 mutex_init(&qdev->gem.mutex); 116 mutex_init(&qdev->update_area_mutex); 117 mutex_init(&qdev->release_mutex); 118 mutex_init(&qdev->surf_evict_mutex); 119 qxl_gem_init(qdev); 120 121 qdev->rom_base = pci_resource_start(pdev, 2); 122 qdev->rom_size = pci_resource_len(pdev, 2); 123 qdev->vram_base = pci_resource_start(pdev, 0); 124 qdev->io_base = pci_resource_start(pdev, 3); 125 126 qdev->vram_mapping = io_mapping_create_wc(qdev->vram_base, pci_resource_len(pdev, 0)); 127 if (!qdev->vram_mapping) { 128 pr_err("Unable to create vram_mapping"); 129 return -ENOMEM; 130 } 131 132 if (pci_resource_len(pdev, 4) > 0) { 133 /* 64bit surface bar present */ 134 sb = 4; 135 qdev->surfaceram_base = pci_resource_start(pdev, sb); 136 qdev->surfaceram_size = pci_resource_len(pdev, sb); 137 qdev->surface_mapping = 138 io_mapping_create_wc(qdev->surfaceram_base, 139 qdev->surfaceram_size); 140 } 141 if (qdev->surface_mapping == NULL) { 142 /* 64bit surface bar not present (or mapping failed) */ 143 sb = 1; 144 qdev->surfaceram_base = pci_resource_start(pdev, sb); 145 qdev->surfaceram_size = pci_resource_len(pdev, sb); 146 qdev->surface_mapping = 147 io_mapping_create_wc(qdev->surfaceram_base, 148 qdev->surfaceram_size); 149 if (!qdev->surface_mapping) { 150 pr_err("Unable to create surface_mapping"); 151 r = -ENOMEM; 152 goto vram_mapping_free; 153 } 154 } 155 156 DRM_DEBUG_KMS("qxl: vram %llx-%llx(%dM %dk), surface %llx-%llx(%dM %dk, %s)\n", 157 (unsigned long long)qdev->vram_base, 158 (unsigned long long)pci_resource_end(pdev, 0), 159 (int)pci_resource_len(pdev, 0) / 1024 / 1024, 160 (int)pci_resource_len(pdev, 0) / 1024, 161 (unsigned long long)qdev->surfaceram_base, 162 (unsigned long long)pci_resource_end(pdev, sb), 163 (int)qdev->surfaceram_size / 1024 / 1024, 164 (int)qdev->surfaceram_size / 1024, 165 (sb == 4) ? "64bit" : "32bit"); 166 167 qdev->rom = ioremap_wc(qdev->rom_base, qdev->rom_size); 168 if (!qdev->rom) { 169 pr_err("Unable to ioremap ROM\n"); 170 r = -ENOMEM; 171 goto surface_mapping_free; 172 } 173 174 if (!qxl_check_device(qdev)) { 175 r = -ENODEV; 176 goto rom_unmap; 177 } 178 179 r = qxl_bo_init(qdev); 180 if (r) { 181 DRM_ERROR("bo init failed %d\n", r); 182 goto rom_unmap; 183 } 184 185 qdev->ram_header = ioremap_wc(qdev->vram_base + 186 qdev->rom->ram_header_offset, 187 sizeof(*qdev->ram_header)); 188 if (!qdev->ram_header) { 189 DRM_ERROR("Unable to ioremap RAM header\n"); 190 r = -ENOMEM; 191 goto bo_fini; 192 } 193 194 qdev->command_ring = qxl_ring_create(&(qdev->ram_header->cmd_ring_hdr), 195 sizeof(struct qxl_command), 196 QXL_COMMAND_RING_SIZE, 197 qdev->io_base + QXL_IO_NOTIFY_CMD, 198 &qdev->display_event); 199 if (!qdev->command_ring) { 200 DRM_ERROR("Unable to create command ring\n"); 201 r = -ENOMEM; 202 goto ram_header_unmap; 203 } 204 205 qdev->cursor_ring = qxl_ring_create( 206 &(qdev->ram_header->cursor_ring_hdr), 207 sizeof(struct qxl_command), 208 QXL_CURSOR_RING_SIZE, 209 qdev->io_base + QXL_IO_NOTIFY_CURSOR, 210 &qdev->cursor_event); 211 212 if (!qdev->cursor_ring) { 213 DRM_ERROR("Unable to create cursor ring\n"); 214 r = -ENOMEM; 215 goto command_ring_free; 216 } 217 218 qdev->release_ring = qxl_ring_create( 219 &(qdev->ram_header->release_ring_hdr), 220 sizeof(uint64_t), 221 QXL_RELEASE_RING_SIZE, 0, 222 NULL); 223 224 if (!qdev->release_ring) { 225 DRM_ERROR("Unable to create release ring\n"); 226 r = -ENOMEM; 227 goto cursor_ring_free; 228 } 229 230 idr_init_base(&qdev->release_idr, 1); 231 spin_lock_init(&qdev->release_idr_lock); 232 spin_lock_init(&qdev->release_lock); 233 234 idr_init_base(&qdev->surf_id_idr, 1); 235 spin_lock_init(&qdev->surf_id_idr_lock); 236 237 mutex_init(&qdev->async_io_mutex); 238 239 /* reset the device into a known state - no memslots, no primary 240 * created, no surfaces. */ 241 qxl_io_reset(qdev); 242 243 /* must initialize irq before first async io - slot creation */ 244 r = qxl_irq_init(qdev); 245 if (r) { 246 DRM_ERROR("Unable to init qxl irq\n"); 247 goto release_ring_free; 248 } 249 250 /* 251 * Note that virtual is surface0. We rely on the single ioremap done 252 * before. 253 */ 254 setup_slot(qdev, &qdev->main_slot, 0, "main", 255 (unsigned long)qdev->vram_base, 256 (unsigned long)qdev->rom->ram_header_offset); 257 setup_slot(qdev, &qdev->surfaces_slot, 1, "surfaces", 258 (unsigned long)qdev->surfaceram_base, 259 (unsigned long)qdev->surfaceram_size); 260 261 INIT_WORK(&qdev->gc_work, qxl_gc_work); 262 263 return 0; 264 265 release_ring_free: 266 qxl_ring_free(qdev->release_ring); 267 cursor_ring_free: 268 qxl_ring_free(qdev->cursor_ring); 269 command_ring_free: 270 qxl_ring_free(qdev->command_ring); 271 ram_header_unmap: 272 iounmap(qdev->ram_header); 273 bo_fini: 274 qxl_bo_fini(qdev); 275 rom_unmap: 276 iounmap(qdev->rom); 277 surface_mapping_free: 278 io_mapping_free(qdev->surface_mapping); 279 vram_mapping_free: 280 io_mapping_free(qdev->vram_mapping); 281 return r; 282 } 283 284 void qxl_device_fini(struct qxl_device *qdev) 285 { 286 int cur_idx; 287 288 /* check if qxl_device_init() was successful (gc_work is initialized last) */ 289 if (!qdev->gc_work.func) 290 return; 291 292 for (cur_idx = 0; cur_idx < 3; cur_idx++) { 293 if (!qdev->current_release_bo[cur_idx]) 294 continue; 295 qxl_bo_unpin(qdev->current_release_bo[cur_idx]); 296 qxl_bo_unref(&qdev->current_release_bo[cur_idx]); 297 qdev->current_release_bo_offset[cur_idx] = 0; 298 qdev->current_release_bo[cur_idx] = NULL; 299 } 300 301 /* 302 * Ask host to release resources (+fill release ring), 303 * then wait for the release actually happening. 304 */ 305 qxl_io_notify_oom(qdev); 306 wait_event_timeout(qdev->release_event, 307 atomic_read(&qdev->release_count) == 0, 308 HZ); 309 flush_work(&qdev->gc_work); 310 qxl_surf_evict(qdev); 311 qxl_vram_evict(qdev); 312 313 qxl_gem_fini(qdev); 314 qxl_bo_fini(qdev); 315 qxl_ring_free(qdev->command_ring); 316 qxl_ring_free(qdev->cursor_ring); 317 qxl_ring_free(qdev->release_ring); 318 io_mapping_free(qdev->surface_mapping); 319 io_mapping_free(qdev->vram_mapping); 320 iounmap(qdev->ram_header); 321 iounmap(qdev->rom); 322 qdev->rom = NULL; 323 } 324