xref: /linux/drivers/gpu/drm/pl111/pl111_drm.h (revision 001485d5255cb17e99aa9e3712e43865b92d6adc)
1bed41005STom Cooksey /*
2bed41005STom Cooksey  *
3bed41005STom Cooksey  * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
4bed41005STom Cooksey  *
5bed41005STom Cooksey  *
6bed41005STom Cooksey  * Parts of this file were based on sources as follows:
7bed41005STom Cooksey  *
8bed41005STom Cooksey  * Copyright (c) 2006-2008 Intel Corporation
9bed41005STom Cooksey  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
10bed41005STom Cooksey  * Copyright (C) 2011 Texas Instruments
11bed41005STom Cooksey  *
12bed41005STom Cooksey  * This program is free software and is provided to you under the terms of the
13bed41005STom Cooksey  * GNU General Public License version 2 as published by the Free Software
14bed41005STom Cooksey  * Foundation, and any use by you of this program is subject to the terms of
15bed41005STom Cooksey  * such GNU licence.
16bed41005STom Cooksey  *
17bed41005STom Cooksey  */
18bed41005STom Cooksey 
19bed41005STom Cooksey #ifndef _PL111_DRM_H_
20bed41005STom Cooksey #define _PL111_DRM_H_
21bed41005STom Cooksey 
22bed41005STom Cooksey #include <drm/drm_gem.h>
23bed41005STom Cooksey #include <drm/drm_simple_kms_helper.h>
24*001485d5SLinus Walleij #include <drm/drm_connector.h>
25*001485d5SLinus Walleij #include <drm/drm_encoder.h>
26*001485d5SLinus Walleij #include <drm/drm_panel.h>
27*001485d5SLinus Walleij #include <drm/drm_bridge.h>
28032838f9SEric Anholt #include <linux/clk-provider.h>
29bed41005STom Cooksey 
30bed41005STom Cooksey #define CLCD_IRQ_NEXTBASE_UPDATE BIT(2)
31bed41005STom Cooksey 
32141518d2SEric Anholt struct drm_minor;
33141518d2SEric Anholt 
34bed41005STom Cooksey struct pl111_drm_dev_private {
35bed41005STom Cooksey 	struct drm_device *drm;
36bed41005STom Cooksey 
37*001485d5SLinus Walleij 	struct drm_connector *connector;
38*001485d5SLinus Walleij 	struct drm_panel *panel;
39*001485d5SLinus Walleij 	struct drm_bridge *bridge;
40bed41005STom Cooksey 	struct drm_simple_display_pipe pipe;
41bed41005STom Cooksey 	struct drm_fbdev_cma *fbdev;
42bed41005STom Cooksey 
43bed41005STom Cooksey 	void *regs;
44032838f9SEric Anholt 	/* The pixel clock (a reference to our clock divider off of CLCDCLK). */
45bed41005STom Cooksey 	struct clk *clk;
46032838f9SEric Anholt 	/* pl111's internal clock divider. */
47032838f9SEric Anholt 	struct clk_hw clk_div;
48032838f9SEric Anholt 	/* Lock to sync access to CLCD_TIM2 between the common clock
49032838f9SEric Anholt 	 * subsystem and pl111_display_enable().
50032838f9SEric Anholt 	 */
51032838f9SEric Anholt 	spinlock_t tim2_lock;
52bed41005STom Cooksey };
53bed41005STom Cooksey 
54bed41005STom Cooksey int pl111_display_init(struct drm_device *dev);
55bed41005STom Cooksey int pl111_enable_vblank(struct drm_device *drm, unsigned int crtc);
56bed41005STom Cooksey void pl111_disable_vblank(struct drm_device *drm, unsigned int crtc);
57bed41005STom Cooksey irqreturn_t pl111_irq(int irq, void *data);
58141518d2SEric Anholt int pl111_debugfs_init(struct drm_minor *minor);
59bed41005STom Cooksey 
60bed41005STom Cooksey #endif /* _PL111_DRM_H_ */
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