1 /* SPDX-License-Identifier: GPL-2.0 or MIT */ 2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */ 3 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */ 4 /* Copyright 2023 Collabora ltd. */ 5 /* 6 * Register definitions based on mali_kbase_gpu_regmap.h and 7 * mali_kbase_gpu_regmap_csf.h 8 * (C) COPYRIGHT 2010-2022 ARM Limited. All rights reserved. 9 */ 10 #ifndef __PANTHOR_REGS_H__ 11 #define __PANTHOR_REGS_H__ 12 13 #define GPU_ID 0x0 14 #define GPU_ARCH_MAJOR(x) ((x) >> 28) 15 #define GPU_ARCH_MINOR(x) (((x) & GENMASK(27, 24)) >> 24) 16 #define GPU_ARCH_REV(x) (((x) & GENMASK(23, 20)) >> 20) 17 #define GPU_PROD_MAJOR(x) (((x) & GENMASK(19, 16)) >> 16) 18 #define GPU_VER_MAJOR(x) (((x) & GENMASK(15, 12)) >> 12) 19 #define GPU_VER_MINOR(x) (((x) & GENMASK(11, 4)) >> 4) 20 #define GPU_VER_STATUS(x) ((x) & GENMASK(3, 0)) 21 22 #define GPU_L2_FEATURES 0x4 23 #define GPU_L2_FEATURES_LINE_SIZE(x) (1 << ((x) & GENMASK(7, 0))) 24 25 #define GPU_CORE_FEATURES 0x8 26 27 #define GPU_TILER_FEATURES 0xC 28 #define GPU_MEM_FEATURES 0x10 29 #define GROUPS_L2_COHERENT BIT(0) 30 31 #define GPU_MMU_FEATURES 0x14 32 #define GPU_MMU_FEATURES_VA_BITS(x) ((x) & GENMASK(7, 0)) 33 #define GPU_MMU_FEATURES_PA_BITS(x) (((x) >> 8) & GENMASK(7, 0)) 34 #define GPU_AS_PRESENT 0x18 35 #define GPU_CSF_ID 0x1C 36 37 #define GPU_INT_RAWSTAT 0x20 38 #define GPU_INT_CLEAR 0x24 39 #define GPU_INT_MASK 0x28 40 #define GPU_INT_STAT 0x2c 41 #define GPU_IRQ_FAULT BIT(0) 42 #define GPU_IRQ_PROTM_FAULT BIT(1) 43 #define GPU_IRQ_RESET_COMPLETED BIT(8) 44 #define GPU_IRQ_POWER_CHANGED BIT(9) 45 #define GPU_IRQ_POWER_CHANGED_ALL BIT(10) 46 #define GPU_IRQ_CLEAN_CACHES_COMPLETED BIT(17) 47 #define GPU_IRQ_DOORBELL_MIRROR BIT(18) 48 #define GPU_IRQ_MCU_STATUS_CHANGED BIT(19) 49 #define GPU_CMD 0x30 50 #define GPU_CMD_DEF(type, payload) ((type) | ((payload) << 8)) 51 #define GPU_SOFT_RESET GPU_CMD_DEF(1, 1) 52 #define GPU_HARD_RESET GPU_CMD_DEF(1, 2) 53 #define CACHE_CLEAN BIT(0) 54 #define CACHE_INV BIT(1) 55 #define GPU_FLUSH_CACHES(l2, lsc, oth) \ 56 GPU_CMD_DEF(4, ((l2) << 0) | ((lsc) << 4) | ((oth) << 8)) 57 58 #define GPU_STATUS 0x34 59 #define GPU_STATUS_ACTIVE BIT(0) 60 #define GPU_STATUS_PWR_ACTIVE BIT(1) 61 #define GPU_STATUS_PAGE_FAULT BIT(4) 62 #define GPU_STATUS_PROTM_ACTIVE BIT(7) 63 #define GPU_STATUS_DBG_ENABLED BIT(8) 64 65 #define GPU_FAULT_STATUS 0x3C 66 #define GPU_FAULT_ADDR 0x40 67 #define GPU_L2_CONFIG 0x48 68 #define GPU_L2_CONFIG_ASN_HASH_ENABLE BIT(24) 69 70 #define GPU_PWR_KEY 0x50 71 #define GPU_PWR_KEY_UNLOCK 0x2968A819 72 #define GPU_PWR_OVERRIDE0 0x54 73 #define GPU_PWR_OVERRIDE1 0x58 74 75 #define GPU_FEATURES 0x60 76 #define GPU_FEATURES_RAY_INTERSECTION BIT(2) 77 78 #define GPU_TIMESTAMP_OFFSET 0x88 79 #define GPU_CYCLE_COUNT 0x90 80 #define GPU_TIMESTAMP 0x98 81 82 #define GPU_THREAD_MAX_THREADS 0xA0 83 #define GPU_THREAD_MAX_WORKGROUP_SIZE 0xA4 84 #define GPU_THREAD_MAX_BARRIER_SIZE 0xA8 85 #define GPU_THREAD_FEATURES 0xAC 86 87 #define GPU_TEXTURE_FEATURES(n) (0xB0 + ((n) * 4)) 88 89 #define GPU_SHADER_PRESENT 0x100 90 #define GPU_TILER_PRESENT 0x110 91 #define GPU_L2_PRESENT 0x120 92 93 #define SHADER_READY 0x140 94 #define TILER_READY 0x150 95 #define L2_READY 0x160 96 97 #define SHADER_PWRON 0x180 98 #define TILER_PWRON 0x190 99 #define L2_PWRON 0x1A0 100 101 #define SHADER_PWROFF 0x1C0 102 #define TILER_PWROFF 0x1D0 103 #define L2_PWROFF 0x1E0 104 105 #define SHADER_PWRTRANS 0x200 106 #define TILER_PWRTRANS 0x210 107 #define L2_PWRTRANS 0x220 108 109 #define SHADER_PWRACTIVE 0x240 110 #define TILER_PWRACTIVE 0x250 111 #define L2_PWRACTIVE 0x260 112 113 #define GPU_REVID 0x280 114 115 #define GPU_ASN_HASH(n) (0x2C0 + ((n) * 4)) 116 117 #define GPU_COHERENCY_FEATURES 0x300 118 #define GPU_COHERENCY_PROT_BIT(name) BIT(GPU_COHERENCY_ ## name) 119 120 #define GPU_COHERENCY_PROTOCOL 0x304 121 #define GPU_COHERENCY_ACE_LITE 0 122 #define GPU_COHERENCY_ACE 1 123 #define GPU_COHERENCY_NONE 31 124 125 #define MCU_CONTROL 0x700 126 #define MCU_CONTROL_ENABLE 1 127 #define MCU_CONTROL_AUTO 2 128 #define MCU_CONTROL_DISABLE 0 129 130 #define MCU_STATUS 0x704 131 #define MCU_STATUS_DISABLED 0 132 #define MCU_STATUS_ENABLED 1 133 #define MCU_STATUS_HALT 2 134 #define MCU_STATUS_FATAL 3 135 136 /* Job Control regs */ 137 #define JOB_INT_RAWSTAT 0x1000 138 #define JOB_INT_CLEAR 0x1004 139 #define JOB_INT_MASK 0x1008 140 #define JOB_INT_STAT 0x100c 141 #define JOB_INT_GLOBAL_IF BIT(31) 142 #define JOB_INT_CSG_IF(x) BIT(x) 143 144 /* MMU regs */ 145 #define MMU_INT_RAWSTAT 0x2000 146 #define MMU_INT_CLEAR 0x2004 147 #define MMU_INT_MASK 0x2008 148 #define MMU_INT_STAT 0x200c 149 150 /* AS_COMMAND register commands */ 151 152 #define MMU_BASE 0x2400 153 #define MMU_AS_SHIFT 6 154 #define MMU_AS(as) (MMU_BASE + ((as) << MMU_AS_SHIFT)) 155 156 #define AS_TRANSTAB(as) (MMU_AS(as) + 0x0) 157 #define AS_MEMATTR(as) (MMU_AS(as) + 0x8) 158 #define AS_MEMATTR_AARCH64_INNER_ALLOC_IMPL (2 << 2) 159 #define AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(w, r) ((3 << 2) | \ 160 ((w) ? BIT(0) : 0) | \ 161 ((r) ? BIT(1) : 0)) 162 #define AS_MEMATTR_AARCH64_SH_MIDGARD_INNER (0 << 4) 163 #define AS_MEMATTR_AARCH64_SH_CPU_INNER (1 << 4) 164 #define AS_MEMATTR_AARCH64_SH_CPU_INNER_SHADER_COH (2 << 4) 165 #define AS_MEMATTR_AARCH64_SHARED (0 << 6) 166 #define AS_MEMATTR_AARCH64_INNER_OUTER_NC (1 << 6) 167 #define AS_MEMATTR_AARCH64_INNER_OUTER_WB (2 << 6) 168 #define AS_MEMATTR_AARCH64_FAULT (3 << 6) 169 #define AS_LOCKADDR(as) (MMU_AS(as) + 0x10) 170 #define AS_COMMAND(as) (MMU_AS(as) + 0x18) 171 #define AS_COMMAND_NOP 0 172 #define AS_COMMAND_UPDATE 1 173 #define AS_COMMAND_LOCK 2 174 #define AS_COMMAND_UNLOCK 3 175 #define AS_COMMAND_FLUSH_PT 4 176 #define AS_COMMAND_FLUSH_MEM 5 177 #define AS_LOCK_REGION_MIN_SIZE (1ULL << 15) 178 #define AS_FAULTSTATUS(as) (MMU_AS(as) + 0x1C) 179 #define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << 8) 180 #define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC (0x0 << 8) 181 #define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1 << 8) 182 #define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2 << 8) 183 #define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3 << 8) 184 #define AS_FAULTADDRESS(as) (MMU_AS(as) + 0x20) 185 #define AS_STATUS(as) (MMU_AS(as) + 0x28) 186 #define AS_STATUS_AS_ACTIVE BIT(0) 187 #define AS_TRANSCFG(as) (MMU_AS(as) + 0x30) 188 #define AS_TRANSCFG_ADRMODE_UNMAPPED (1 << 0) 189 #define AS_TRANSCFG_ADRMODE_IDENTITY (2 << 0) 190 #define AS_TRANSCFG_ADRMODE_AARCH64_4K (6 << 0) 191 #define AS_TRANSCFG_ADRMODE_AARCH64_64K (8 << 0) 192 #define AS_TRANSCFG_INA_BITS(x) ((x) << 6) 193 #define AS_TRANSCFG_OUTA_BITS(x) ((x) << 14) 194 #define AS_TRANSCFG_SL_CONCAT BIT(22) 195 #define AS_TRANSCFG_PTW_MEMATTR_NC (1 << 24) 196 #define AS_TRANSCFG_PTW_MEMATTR_WB (2 << 24) 197 #define AS_TRANSCFG_PTW_SH_NS (0 << 28) 198 #define AS_TRANSCFG_PTW_SH_OS (2 << 28) 199 #define AS_TRANSCFG_PTW_SH_IS (3 << 28) 200 #define AS_TRANSCFG_PTW_RA BIT(30) 201 #define AS_TRANSCFG_DISABLE_HIER_AP BIT(33) 202 #define AS_TRANSCFG_DISABLE_AF_FAULT BIT(34) 203 #define AS_TRANSCFG_WXN BIT(35) 204 #define AS_TRANSCFG_XREADABLE BIT(36) 205 #define AS_FAULTEXTRA(as) (MMU_AS(as) + 0x38) 206 207 #define CSF_GPU_LATEST_FLUSH_ID 0x10000 208 209 #define CSF_DOORBELL(i) (0x80000 + ((i) * 0x10000)) 210 #define CSF_GLB_DOORBELL_ID 0 211 212 #endif 213