1 // SPDX-License-Identifier: GPL-2.0 or MIT 2 /* Copyright 2025 ARM Limited. All rights reserved. */ 3 4 #include <linux/nvmem-consumer.h> 5 #include <linux/platform_device.h> 6 7 #include <drm/drm_print.h> 8 9 #include "panthor_device.h" 10 #include "panthor_gpu.h" 11 #include "panthor_gpu_regs.h" 12 #include "panthor_hw.h" 13 #include "panthor_pwr.h" 14 #include "panthor_pwr_regs.h" 15 16 #define GPU_PROD_ID_MAKE(arch_major, prod_major) \ 17 (((arch_major) << 24) | (prod_major)) 18 19 /** struct panthor_hw_entry - HW arch major to panthor_hw binding entry */ 20 struct panthor_hw_entry { 21 /** @arch_min: Minimum supported architecture major value (inclusive) */ 22 u8 arch_min; 23 24 /** @arch_max: Maximum supported architecture major value (inclusive) */ 25 u8 arch_max; 26 27 /** @hwdev: Pointer to panthor_hw structure */ 28 struct panthor_hw *hwdev; 29 }; 30 31 static struct panthor_hw panthor_hw_arch_v10 = { 32 .ops = { 33 .soft_reset = panthor_gpu_soft_reset, 34 .l2_power_off = panthor_gpu_l2_power_off, 35 .l2_power_on = panthor_gpu_l2_power_on, 36 .power_changed_off = panthor_gpu_power_changed_off, 37 .power_changed_on = panthor_gpu_power_changed_on, 38 }, 39 }; 40 41 static struct panthor_hw panthor_hw_arch_v14 = { 42 .ops = { 43 .soft_reset = panthor_pwr_reset_soft, 44 .l2_power_off = panthor_pwr_l2_power_off, 45 .l2_power_on = panthor_pwr_l2_power_on, 46 }, 47 }; 48 49 static struct panthor_hw_entry panthor_hw_match[] = { 50 { 51 .arch_min = 10, 52 .arch_max = 13, 53 .hwdev = &panthor_hw_arch_v10, 54 }, 55 { 56 .arch_min = 14, 57 .arch_max = 14, 58 .hwdev = &panthor_hw_arch_v14, 59 }, 60 }; 61 62 static int panthor_hw_set_power_tracing(struct device *dev, void *data) 63 { 64 struct panthor_device *ptdev = dev_get_drvdata(dev); 65 66 if (!ptdev) 67 return -ENODEV; 68 69 if (!ptdev->hw) 70 return 0; 71 72 if (data) { 73 if (ptdev->hw->ops.power_changed_on) 74 return ptdev->hw->ops.power_changed_on(ptdev); 75 } else { 76 if (ptdev->hw->ops.power_changed_off) 77 ptdev->hw->ops.power_changed_off(ptdev); 78 } 79 80 return 0; 81 } 82 83 int panthor_hw_power_status_register(void) 84 { 85 struct device_driver *drv; 86 int ret; 87 88 drv = driver_find("panthor", &platform_bus_type); 89 if (!drv) 90 return -ENODEV; 91 92 ret = driver_for_each_device(drv, NULL, (void *)true, 93 panthor_hw_set_power_tracing); 94 95 return ret; 96 } 97 98 void panthor_hw_power_status_unregister(void) 99 { 100 struct device_driver *drv; 101 int ret; 102 103 drv = driver_find("panthor", &platform_bus_type); 104 if (!drv) 105 return; 106 107 ret = driver_for_each_device(drv, NULL, NULL, panthor_hw_set_power_tracing); 108 109 /* 110 * Ideally, it'd be possible to ask driver_for_each_device to hand us 111 * another "start" to keep going after the failing device, but it 112 * doesn't do that. Minor inconvenience in what is probably a bad day 113 * on the computer already though. 114 */ 115 if (ret) 116 pr_warn("Couldn't mask power IRQ for at least one device: %pe\n", 117 ERR_PTR(ret)); 118 } 119 120 static char *get_gpu_model_name(struct panthor_device *ptdev) 121 { 122 const u32 gpu_id = ptdev->gpu_info.gpu_id; 123 const u32 product_id = GPU_PROD_ID_MAKE(GPU_ARCH_MAJOR(gpu_id), 124 GPU_PROD_MAJOR(gpu_id)); 125 const bool ray_intersection = !!(ptdev->gpu_info.gpu_features & 126 GPU_FEATURES_RAY_INTERSECTION); 127 const u8 shader_core_count = hweight64(ptdev->gpu_info.shader_present); 128 129 switch (product_id) { 130 case GPU_PROD_ID_MAKE(10, 2): 131 return "Mali-G710"; 132 case GPU_PROD_ID_MAKE(10, 3): 133 return "Mali-G510"; 134 case GPU_PROD_ID_MAKE(10, 4): 135 return "Mali-G310"; 136 case GPU_PROD_ID_MAKE(10, 7): 137 return "Mali-G610"; 138 case GPU_PROD_ID_MAKE(11, 2): 139 if (shader_core_count > 10 && ray_intersection) 140 return "Mali-G715-Immortalis"; 141 else if (shader_core_count >= 7) 142 return "Mali-G715"; 143 144 fallthrough; 145 case GPU_PROD_ID_MAKE(11, 3): 146 return "Mali-G615"; 147 case GPU_PROD_ID_MAKE(12, 0): 148 if (shader_core_count >= 10 && ray_intersection) 149 return "Mali-G720-Immortalis"; 150 else if (shader_core_count >= 6) 151 return "Mali-G720"; 152 153 fallthrough; 154 case GPU_PROD_ID_MAKE(12, 1): 155 return "Mali-G620"; 156 case GPU_PROD_ID_MAKE(13, 0): 157 if (shader_core_count >= 10 && ray_intersection) 158 return "Mali-G925-Immortalis"; 159 else if (shader_core_count >= 6) 160 return "Mali-G725"; 161 162 fallthrough; 163 case GPU_PROD_ID_MAKE(13, 1): 164 return "Mali-G625"; 165 case GPU_PROD_ID_MAKE(14, 0): 166 return "Mali-G1-Ultra"; 167 case GPU_PROD_ID_MAKE(14, 1): 168 return "Mali-G1-Premium"; 169 case GPU_PROD_ID_MAKE(14, 3): 170 return "Mali-G1-Pro"; 171 } 172 173 return "(Unknown Mali GPU)"; 174 } 175 176 static int overload_shader_present(struct panthor_device *ptdev) 177 { 178 u64 contents; 179 int ret; 180 181 ret = nvmem_cell_read_variable_le_u64(ptdev->base.dev, "shader-present", 182 &contents); 183 if (!ret) 184 ptdev->gpu_info.shader_present = contents; 185 else if (ret == -ENOENT) 186 return 0; 187 else 188 return dev_err_probe(ptdev->base.dev, ret, 189 "Failed to read shader-present nvmem cell\n"); 190 191 return 0; 192 } 193 194 static int panthor_gpu_info_init(struct panthor_device *ptdev) 195 { 196 unsigned int i; 197 198 void __iomem *gpu_iomem = ptdev->iomem + GPU_CONTROL_BASE; 199 200 ptdev->gpu_info.csf_id = gpu_read(gpu_iomem, GPU_CSF_ID); 201 ptdev->gpu_info.gpu_rev = gpu_read(gpu_iomem, GPU_REVID); 202 ptdev->gpu_info.core_features = gpu_read(gpu_iomem, GPU_CORE_FEATURES); 203 ptdev->gpu_info.l2_features = gpu_read(gpu_iomem, GPU_L2_FEATURES); 204 ptdev->gpu_info.tiler_features = gpu_read(gpu_iomem, GPU_TILER_FEATURES); 205 ptdev->gpu_info.mem_features = gpu_read(gpu_iomem, GPU_MEM_FEATURES); 206 ptdev->gpu_info.mmu_features = gpu_read(gpu_iomem, GPU_MMU_FEATURES); 207 ptdev->gpu_info.thread_features = gpu_read(gpu_iomem, GPU_THREAD_FEATURES); 208 ptdev->gpu_info.max_threads = gpu_read(gpu_iomem, GPU_THREAD_MAX_THREADS); 209 ptdev->gpu_info.thread_max_workgroup_size = 210 gpu_read(gpu_iomem, GPU_THREAD_MAX_WORKGROUP_SIZE); 211 ptdev->gpu_info.thread_max_barrier_size = 212 gpu_read(gpu_iomem, GPU_THREAD_MAX_BARRIER_SIZE); 213 ptdev->gpu_info.coherency_features = gpu_read(gpu_iomem, GPU_COHERENCY_FEATURES); 214 for (i = 0; i < 4; i++) 215 ptdev->gpu_info.texture_features[i] = 216 gpu_read(gpu_iomem, GPU_TEXTURE_FEATURES(i)); 217 218 ptdev->gpu_info.as_present = gpu_read(gpu_iomem, GPU_AS_PRESENT); 219 220 /* Introduced in arch 11.x */ 221 ptdev->gpu_info.gpu_features = gpu_read64(gpu_iomem, GPU_FEATURES); 222 223 if (panthor_hw_has_pwr_ctrl(ptdev)) { 224 void __iomem *pwr_iomem = gpu_iomem + PWR_CONTROL_BASE; 225 226 /* Introduced in arch 14.x */ 227 ptdev->gpu_info.l2_present = gpu_read64(pwr_iomem, PWR_L2_PRESENT); 228 ptdev->gpu_info.tiler_present = gpu_read64(pwr_iomem, PWR_TILER_PRESENT); 229 ptdev->gpu_info.shader_present = gpu_read64(pwr_iomem, PWR_SHADER_PRESENT); 230 } else { 231 ptdev->gpu_info.shader_present = gpu_read64(gpu_iomem, GPU_SHADER_PRESENT); 232 ptdev->gpu_info.tiler_present = gpu_read64(gpu_iomem, GPU_TILER_PRESENT); 233 ptdev->gpu_info.l2_present = gpu_read64(gpu_iomem, GPU_L2_PRESENT); 234 } 235 236 return overload_shader_present(ptdev); 237 } 238 239 static int panthor_hw_info_init(struct panthor_device *ptdev) 240 { 241 u32 major, minor, status; 242 int ret; 243 244 ret = panthor_gpu_info_init(ptdev); 245 if (ret) 246 return ret; 247 248 major = GPU_VER_MAJOR(ptdev->gpu_info.gpu_id); 249 minor = GPU_VER_MINOR(ptdev->gpu_info.gpu_id); 250 status = GPU_VER_STATUS(ptdev->gpu_info.gpu_id); 251 252 drm_info(&ptdev->base, 253 "%s id 0x%x major 0x%x minor 0x%x status 0x%x", 254 get_gpu_model_name(ptdev), ptdev->gpu_info.gpu_id >> 16, 255 major, minor, status); 256 257 drm_info(&ptdev->base, 258 "Features: L2:%#x Tiler:%#x Mem:%#x MMU:%#x AS:%#x", 259 ptdev->gpu_info.l2_features, 260 ptdev->gpu_info.tiler_features, 261 ptdev->gpu_info.mem_features, 262 ptdev->gpu_info.mmu_features, 263 ptdev->gpu_info.as_present); 264 265 drm_info(&ptdev->base, 266 "shader_present=0x%0llx l2_present=0x%0llx tiler_present=0x%0llx", 267 ptdev->gpu_info.shader_present, ptdev->gpu_info.l2_present, 268 ptdev->gpu_info.tiler_present); 269 270 return 0; 271 } 272 273 static int panthor_hw_bind_device(struct panthor_device *ptdev) 274 { 275 struct panthor_hw *hdev = NULL; 276 const u32 arch_major = GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id); 277 int i = 0; 278 279 for (i = 0; i < ARRAY_SIZE(panthor_hw_match); i++) { 280 struct panthor_hw_entry *entry = &panthor_hw_match[i]; 281 282 if (arch_major >= entry->arch_min && arch_major <= entry->arch_max) { 283 hdev = entry->hwdev; 284 break; 285 } 286 } 287 288 if (!hdev) 289 return -EOPNOTSUPP; 290 291 ptdev->hw = hdev; 292 293 return 0; 294 } 295 296 static int panthor_hw_gpu_id_init(struct panthor_device *ptdev) 297 { 298 ptdev->gpu_info.gpu_id = gpu_read(ptdev->iomem, GPU_ID); 299 if (!ptdev->gpu_info.gpu_id) 300 return -ENXIO; 301 302 return 0; 303 } 304 305 int panthor_hw_init(struct panthor_device *ptdev) 306 { 307 int ret = 0; 308 309 ret = panthor_hw_gpu_id_init(ptdev); 310 if (ret) 311 return ret; 312 313 ret = panthor_hw_bind_device(ptdev); 314 if (ret) 315 return ret; 316 317 return panthor_hw_info_init(ptdev); 318 } 319