1 /* SPDX-License-Identifier: GPL-2.0 or MIT */ 2 /* Copyright 2026 ARM Limited. All rights reserved. */ 3 4 #ifndef __PANTHOR_GPU_REGS_H__ 5 #define __PANTHOR_GPU_REGS_H__ 6 7 #define GPU_CONTROL_BASE 0x0 8 9 #define GPU_ID 0x0 10 #define GPU_ARCH_MAJOR(x) ((x) >> 28) 11 #define GPU_ARCH_MINOR(x) (((x) & GENMASK(27, 24)) >> 24) 12 #define GPU_ARCH_REV(x) (((x) & GENMASK(23, 20)) >> 20) 13 #define GPU_PROD_MAJOR(x) (((x) & GENMASK(19, 16)) >> 16) 14 #define GPU_VER_MAJOR(x) (((x) & GENMASK(15, 12)) >> 12) 15 #define GPU_VER_MINOR(x) (((x) & GENMASK(11, 4)) >> 4) 16 #define GPU_VER_STATUS(x) ((x) & GENMASK(3, 0)) 17 18 #define GPU_L2_FEATURES 0x4 19 #define GPU_L2_FEATURES_LINE_SIZE(x) (1 << ((x) & GENMASK(7, 0))) 20 21 #define GPU_CORE_FEATURES 0x8 22 23 #define GPU_TILER_FEATURES 0xC 24 #define GPU_MEM_FEATURES 0x10 25 #define GROUPS_L2_COHERENT BIT(0) 26 27 #define GPU_MMU_FEATURES 0x14 28 #define GPU_MMU_FEATURES_VA_BITS(x) ((x) & GENMASK(7, 0)) 29 #define GPU_MMU_FEATURES_PA_BITS(x) (((x) >> 8) & GENMASK(7, 0)) 30 #define GPU_AS_PRESENT 0x18 31 #define GPU_CSF_ID 0x1C 32 33 #define GPU_INT_BASE 0x20 34 #define GPU_IRQ_FAULT BIT(0) 35 #define GPU_IRQ_PROTM_FAULT BIT(1) 36 #define GPU_IRQ_RESET_COMPLETED BIT(8) 37 #define GPU_IRQ_POWER_CHANGED BIT(9) 38 #define GPU_IRQ_POWER_CHANGED_ALL BIT(10) 39 #define GPU_IRQ_CLEAN_CACHES_COMPLETED BIT(17) 40 #define GPU_IRQ_DOORBELL_MIRROR BIT(18) 41 #define GPU_IRQ_MCU_STATUS_CHANGED BIT(19) 42 #define GPU_CMD 0x30 43 #define GPU_CMD_DEF(type, payload) ((type) | ((payload) << 8)) 44 #define GPU_SOFT_RESET GPU_CMD_DEF(1, 1) 45 #define GPU_HARD_RESET GPU_CMD_DEF(1, 2) 46 #define CACHE_CLEAN BIT(0) 47 #define CACHE_INV BIT(1) 48 #define GPU_FLUSH_CACHES(l2, lsc, oth) \ 49 GPU_CMD_DEF(4, ((l2) << 0) | ((lsc) << 4) | ((oth) << 8)) 50 51 #define GPU_STATUS 0x34 52 #define GPU_STATUS_ACTIVE BIT(0) 53 #define GPU_STATUS_PWR_ACTIVE BIT(1) 54 #define GPU_STATUS_PAGE_FAULT BIT(4) 55 #define GPU_STATUS_PROTM_ACTIVE BIT(7) 56 #define GPU_STATUS_DBG_ENABLED BIT(8) 57 58 #define GPU_FAULT_STATUS 0x3C 59 #define GPU_FAULT_ADDR 0x40 60 #define GPU_L2_CONFIG 0x48 61 #define GPU_L2_CONFIG_ASN_HASH_ENABLE BIT(24) 62 63 #define GPU_PWR_KEY 0x50 64 #define GPU_PWR_KEY_UNLOCK 0x2968A819 65 #define GPU_PWR_OVERRIDE0 0x54 66 #define GPU_PWR_OVERRIDE1 0x58 67 68 #define GPU_FEATURES 0x60 69 #define GPU_FEATURES_RAY_INTERSECTION BIT(2) 70 #define GPU_FEATURES_RAY_TRAVERSAL BIT(5) 71 72 #define GPU_TIMESTAMP_OFFSET 0x88 73 #define GPU_CYCLE_COUNT 0x90 74 #define GPU_TIMESTAMP 0x98 75 76 #define GPU_THREAD_MAX_THREADS 0xA0 77 #define GPU_THREAD_MAX_WORKGROUP_SIZE 0xA4 78 #define GPU_THREAD_MAX_BARRIER_SIZE 0xA8 79 #define GPU_THREAD_FEATURES 0xAC 80 81 #define GPU_TEXTURE_FEATURES(n) (0xB0 + ((n) * 4)) 82 83 #define GPU_SHADER_PRESENT 0x100 84 #define GPU_TILER_PRESENT 0x110 85 #define GPU_L2_PRESENT 0x120 86 87 #define SHADER_READY 0x140 88 #define TILER_READY 0x150 89 #define L2_READY 0x160 90 91 #define SHADER_PWRON 0x180 92 #define TILER_PWRON 0x190 93 #define L2_PWRON 0x1A0 94 95 #define SHADER_PWROFF 0x1C0 96 #define TILER_PWROFF 0x1D0 97 #define L2_PWROFF 0x1E0 98 99 #define SHADER_PWRTRANS 0x200 100 #define TILER_PWRTRANS 0x210 101 #define L2_PWRTRANS 0x220 102 103 #define SHADER_PWRACTIVE 0x240 104 #define TILER_PWRACTIVE 0x250 105 #define L2_PWRACTIVE 0x260 106 107 #define GPU_REVID 0x280 108 109 #define GPU_ASN_HASH(n) (0x2C0 + ((n) * 4)) 110 111 #define GPU_COHERENCY_FEATURES 0x300 112 #define GPU_COHERENCY_PROT_BIT(name) BIT(GPU_COHERENCY_ ## name) 113 114 #define GPU_COHERENCY_PROTOCOL 0x304 115 #define GPU_COHERENCY_ACE_LITE 0 116 #define GPU_COHERENCY_ACE 1 117 #define GPU_COHERENCY_NONE 31 118 119 #endif /* __PANTHOR_GPU_REGS_H__ */ 120