1 // SPDX-License-Identifier: GPL-2.0 or MIT 2 /* Copyright 2023 Collabora ltd. */ 3 4 #ifdef CONFIG_ARM_ARCH_TIMER 5 #include <asm/arch_timer.h> 6 #endif 7 8 #include <linux/clk.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/iosys-map.h> 13 #include <linux/mutex.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 17 #include <drm/drm_drv.h> 18 #include <drm/drm_managed.h> 19 20 #include "panthor_device.h" 21 #include "panthor_fw.h" 22 #include "panthor_gem.h" 23 #include "panthor_gpu.h" 24 #include "panthor_mmu.h" 25 #include "panthor_regs.h" 26 #include "panthor_sched.h" 27 28 #define CSF_FW_NAME "mali_csffw.bin" 29 30 #define PING_INTERVAL_MS 12000 31 #define PROGRESS_TIMEOUT_CYCLES (5ull * 500 * 1024 * 1024) 32 #define PROGRESS_TIMEOUT_SCALE_SHIFT 10 33 #define IDLE_HYSTERESIS_US 800 34 #define PWROFF_HYSTERESIS_US 10000 35 36 /** 37 * struct panthor_fw_binary_hdr - Firmware binary header. 38 */ 39 struct panthor_fw_binary_hdr { 40 /** @magic: Magic value to check binary validity. */ 41 u32 magic; 42 #define CSF_FW_BINARY_HEADER_MAGIC 0xc3f13a6e 43 44 /** @minor: Minor FW version. */ 45 u8 minor; 46 47 /** @major: Major FW version. */ 48 u8 major; 49 #define CSF_FW_BINARY_HEADER_MAJOR_MAX 0 50 51 /** @padding1: MBZ. */ 52 u16 padding1; 53 54 /** @version_hash: FW version hash. */ 55 u32 version_hash; 56 57 /** @padding2: MBZ. */ 58 u32 padding2; 59 60 /** @size: FW binary size. */ 61 u32 size; 62 }; 63 64 /** 65 * enum panthor_fw_binary_entry_type - Firmware binary entry type 66 */ 67 enum panthor_fw_binary_entry_type { 68 /** @CSF_FW_BINARY_ENTRY_TYPE_IFACE: Host <-> FW interface. */ 69 CSF_FW_BINARY_ENTRY_TYPE_IFACE = 0, 70 71 /** @CSF_FW_BINARY_ENTRY_TYPE_CONFIG: FW config. */ 72 CSF_FW_BINARY_ENTRY_TYPE_CONFIG = 1, 73 74 /** @CSF_FW_BINARY_ENTRY_TYPE_FUTF_TEST: Unit-tests. */ 75 CSF_FW_BINARY_ENTRY_TYPE_FUTF_TEST = 2, 76 77 /** @CSF_FW_BINARY_ENTRY_TYPE_TRACE_BUFFER: Trace buffer interface. */ 78 CSF_FW_BINARY_ENTRY_TYPE_TRACE_BUFFER = 3, 79 80 /** @CSF_FW_BINARY_ENTRY_TYPE_TIMELINE_METADATA: Timeline metadata interface. */ 81 CSF_FW_BINARY_ENTRY_TYPE_TIMELINE_METADATA = 4, 82 83 /** 84 * @CSF_FW_BINARY_ENTRY_TYPE_BUILD_INFO_METADATA: Metadata about how 85 * the FW binary was built. 86 */ 87 CSF_FW_BINARY_ENTRY_TYPE_BUILD_INFO_METADATA = 6 88 }; 89 90 #define CSF_FW_BINARY_ENTRY_TYPE(ehdr) ((ehdr) & 0xff) 91 #define CSF_FW_BINARY_ENTRY_SIZE(ehdr) (((ehdr) >> 8) & 0xff) 92 #define CSF_FW_BINARY_ENTRY_UPDATE BIT(30) 93 #define CSF_FW_BINARY_ENTRY_OPTIONAL BIT(31) 94 95 #define CSF_FW_BINARY_IFACE_ENTRY_RD BIT(0) 96 #define CSF_FW_BINARY_IFACE_ENTRY_WR BIT(1) 97 #define CSF_FW_BINARY_IFACE_ENTRY_EX BIT(2) 98 #define CSF_FW_BINARY_IFACE_ENTRY_CACHE_MODE_NONE (0 << 3) 99 #define CSF_FW_BINARY_IFACE_ENTRY_CACHE_MODE_CACHED (1 << 3) 100 #define CSF_FW_BINARY_IFACE_ENTRY_CACHE_MODE_UNCACHED_COHERENT (2 << 3) 101 #define CSF_FW_BINARY_IFACE_ENTRY_CACHE_MODE_CACHED_COHERENT (3 << 3) 102 #define CSF_FW_BINARY_IFACE_ENTRY_CACHE_MODE_MASK GENMASK(4, 3) 103 #define CSF_FW_BINARY_IFACE_ENTRY_PROT BIT(5) 104 #define CSF_FW_BINARY_IFACE_ENTRY_SHARED BIT(30) 105 #define CSF_FW_BINARY_IFACE_ENTRY_ZERO BIT(31) 106 107 #define CSF_FW_BINARY_IFACE_ENTRY_SUPPORTED_FLAGS \ 108 (CSF_FW_BINARY_IFACE_ENTRY_RD | \ 109 CSF_FW_BINARY_IFACE_ENTRY_WR | \ 110 CSF_FW_BINARY_IFACE_ENTRY_EX | \ 111 CSF_FW_BINARY_IFACE_ENTRY_CACHE_MODE_MASK | \ 112 CSF_FW_BINARY_IFACE_ENTRY_PROT | \ 113 CSF_FW_BINARY_IFACE_ENTRY_SHARED | \ 114 CSF_FW_BINARY_IFACE_ENTRY_ZERO) 115 116 /** 117 * struct panthor_fw_binary_section_entry_hdr - Describes a section of FW binary 118 */ 119 struct panthor_fw_binary_section_entry_hdr { 120 /** @flags: Section flags. */ 121 u32 flags; 122 123 /** @va: MCU virtual range to map this binary section to. */ 124 struct { 125 /** @start: Start address. */ 126 u32 start; 127 128 /** @end: End address. */ 129 u32 end; 130 } va; 131 132 /** @data: Data to initialize the FW section with. */ 133 struct { 134 /** @start: Start offset in the FW binary. */ 135 u32 start; 136 137 /** @end: End offset in the FW binary. */ 138 u32 end; 139 } data; 140 }; 141 142 struct panthor_fw_build_info_hdr { 143 /** @meta_start: Offset of the build info data in the FW binary */ 144 u32 meta_start; 145 /** @meta_size: Size of the build info data in the FW binary */ 146 u32 meta_size; 147 }; 148 149 /** 150 * struct panthor_fw_binary_iter - Firmware binary iterator 151 * 152 * Used to parse a firmware binary. 153 */ 154 struct panthor_fw_binary_iter { 155 /** @data: FW binary data. */ 156 const void *data; 157 158 /** @size: FW binary size. */ 159 size_t size; 160 161 /** @offset: Iterator offset. */ 162 size_t offset; 163 }; 164 165 /** 166 * struct panthor_fw_section - FW section 167 */ 168 struct panthor_fw_section { 169 /** @node: Used to keep track of FW sections. */ 170 struct list_head node; 171 172 /** @flags: Section flags, as encoded in the FW binary. */ 173 u32 flags; 174 175 /** @mem: Section memory. */ 176 struct panthor_kernel_bo *mem; 177 178 /** 179 * @name: Name of the section, as specified in the binary. 180 * 181 * Can be NULL. 182 */ 183 const char *name; 184 185 /** 186 * @data: Initial data copied to the FW memory. 187 * 188 * We keep data around so we can reload sections after a reset. 189 */ 190 struct { 191 /** @buf: Buffed used to store init data. */ 192 const void *buf; 193 194 /** @size: Size of @buf in bytes. */ 195 size_t size; 196 } data; 197 }; 198 199 #define CSF_MCU_SHARED_REGION_START 0x04000000ULL 200 #define CSF_MCU_SHARED_REGION_SIZE 0x04000000ULL 201 202 #define MIN_CS_PER_CSG 8 203 #define MIN_CSGS 3 204 205 #define CSF_IFACE_VERSION(major, minor, patch) \ 206 (((major) << 24) | ((minor) << 16) | (patch)) 207 #define CSF_IFACE_VERSION_MAJOR(v) ((v) >> 24) 208 #define CSF_IFACE_VERSION_MINOR(v) (((v) >> 16) & 0xff) 209 #define CSF_IFACE_VERSION_PATCH(v) ((v) & 0xffff) 210 211 #define CSF_GROUP_CONTROL_OFFSET 0x1000 212 #define CSF_STREAM_CONTROL_OFFSET 0x40 213 #define CSF_UNPRESERVED_REG_COUNT 4 214 215 /** 216 * struct panthor_fw_iface - FW interfaces 217 */ 218 struct panthor_fw_iface { 219 /** @global: Global interface. */ 220 struct panthor_fw_global_iface global; 221 222 /** @groups: Group slot interfaces. */ 223 struct panthor_fw_csg_iface groups[MAX_CSGS]; 224 225 /** @streams: Command stream slot interfaces. */ 226 struct panthor_fw_cs_iface streams[MAX_CSGS][MAX_CS_PER_CSG]; 227 }; 228 229 /** 230 * struct panthor_fw - Firmware management 231 */ 232 struct panthor_fw { 233 /** @vm: MCU VM. */ 234 struct panthor_vm *vm; 235 236 /** @sections: List of FW sections. */ 237 struct list_head sections; 238 239 /** @shared_section: The section containing the FW interfaces. */ 240 struct panthor_fw_section *shared_section; 241 242 /** @iface: FW interfaces. */ 243 struct panthor_fw_iface iface; 244 245 /** @watchdog: Collection of fields relating to the FW watchdog. */ 246 struct { 247 /** @ping_work: Delayed work used to ping the FW. */ 248 struct delayed_work ping_work; 249 } watchdog; 250 251 /** 252 * @req_waitqueue: FW request waitqueue. 253 * 254 * Everytime a request is sent to a command stream group or the global 255 * interface, the caller will first busy wait for the request to be 256 * acknowledged, and then fallback to a sleeping wait. 257 * 258 * This wait queue is here to support the sleeping wait flavor. 259 */ 260 wait_queue_head_t req_waitqueue; 261 262 /** @booted: True is the FW is booted */ 263 bool booted; 264 265 /** @irq: Job irq data. */ 266 struct panthor_irq irq; 267 }; 268 269 struct panthor_vm *panthor_fw_vm(struct panthor_device *ptdev) 270 { 271 return ptdev->fw->vm; 272 } 273 274 /** 275 * panthor_fw_get_glb_iface() - Get the global interface 276 * @ptdev: Device. 277 * 278 * Return: The global interface. 279 */ 280 struct panthor_fw_global_iface * 281 panthor_fw_get_glb_iface(struct panthor_device *ptdev) 282 { 283 return &ptdev->fw->iface.global; 284 } 285 286 /** 287 * panthor_fw_get_csg_iface() - Get a command stream group slot interface 288 * @ptdev: Device. 289 * @csg_slot: Index of the command stream group slot. 290 * 291 * Return: The command stream group slot interface. 292 */ 293 struct panthor_fw_csg_iface * 294 panthor_fw_get_csg_iface(struct panthor_device *ptdev, u32 csg_slot) 295 { 296 if (drm_WARN_ON(&ptdev->base, csg_slot >= MAX_CSGS)) 297 return NULL; 298 299 return &ptdev->fw->iface.groups[csg_slot]; 300 } 301 302 /** 303 * panthor_fw_get_cs_iface() - Get a command stream slot interface 304 * @ptdev: Device. 305 * @csg_slot: Index of the command stream group slot. 306 * @cs_slot: Index of the command stream slot. 307 * 308 * Return: The command stream slot interface. 309 */ 310 struct panthor_fw_cs_iface * 311 panthor_fw_get_cs_iface(struct panthor_device *ptdev, u32 csg_slot, u32 cs_slot) 312 { 313 if (drm_WARN_ON(&ptdev->base, csg_slot >= MAX_CSGS || cs_slot >= MAX_CS_PER_CSG)) 314 return NULL; 315 316 return &ptdev->fw->iface.streams[csg_slot][cs_slot]; 317 } 318 319 /** 320 * panthor_fw_conv_timeout() - Convert a timeout into a cycle-count 321 * @ptdev: Device. 322 * @timeout_us: Timeout expressed in micro-seconds. 323 * 324 * The FW has two timer sources: the GPU counter or arch-timer. We need 325 * to express timeouts in term of number of cycles and specify which 326 * timer source should be used. 327 * 328 * Return: A value suitable for timeout fields in the global interface. 329 */ 330 static u32 panthor_fw_conv_timeout(struct panthor_device *ptdev, u32 timeout_us) 331 { 332 bool use_cycle_counter = false; 333 u32 timer_rate = 0; 334 u64 mod_cycles; 335 336 #ifdef CONFIG_ARM_ARCH_TIMER 337 timer_rate = arch_timer_get_cntfrq(); 338 #endif 339 340 if (!timer_rate) { 341 use_cycle_counter = true; 342 timer_rate = clk_get_rate(ptdev->clks.core); 343 } 344 345 if (drm_WARN_ON(&ptdev->base, !timer_rate)) { 346 /* We couldn't get a valid clock rate, let's just pick the 347 * maximum value so the FW still handles the core 348 * power on/off requests. 349 */ 350 return GLB_TIMER_VAL(~0) | 351 GLB_TIMER_SOURCE_GPU_COUNTER; 352 } 353 354 mod_cycles = DIV_ROUND_UP_ULL((u64)timeout_us * timer_rate, 355 1000000ull << 10); 356 if (drm_WARN_ON(&ptdev->base, mod_cycles > GLB_TIMER_VAL(~0))) 357 mod_cycles = GLB_TIMER_VAL(~0); 358 359 return GLB_TIMER_VAL(mod_cycles) | 360 (use_cycle_counter ? GLB_TIMER_SOURCE_GPU_COUNTER : 0); 361 } 362 363 static int panthor_fw_binary_iter_read(struct panthor_device *ptdev, 364 struct panthor_fw_binary_iter *iter, 365 void *out, size_t size) 366 { 367 size_t new_offset = iter->offset + size; 368 369 if (new_offset > iter->size || new_offset < iter->offset) { 370 drm_err(&ptdev->base, "Firmware too small\n"); 371 return -EINVAL; 372 } 373 374 memcpy(out, iter->data + iter->offset, size); 375 iter->offset = new_offset; 376 return 0; 377 } 378 379 static int panthor_fw_binary_sub_iter_init(struct panthor_device *ptdev, 380 struct panthor_fw_binary_iter *iter, 381 struct panthor_fw_binary_iter *sub_iter, 382 size_t size) 383 { 384 size_t new_offset = iter->offset + size; 385 386 if (new_offset > iter->size || new_offset < iter->offset) { 387 drm_err(&ptdev->base, "Firmware entry too long\n"); 388 return -EINVAL; 389 } 390 391 sub_iter->offset = 0; 392 sub_iter->data = iter->data + iter->offset; 393 sub_iter->size = size; 394 iter->offset = new_offset; 395 return 0; 396 } 397 398 static void panthor_fw_init_section_mem(struct panthor_device *ptdev, 399 struct panthor_fw_section *section) 400 { 401 bool was_mapped = !!section->mem->kmap; 402 int ret; 403 404 if (!section->data.size && 405 !(section->flags & CSF_FW_BINARY_IFACE_ENTRY_ZERO)) 406 return; 407 408 ret = panthor_kernel_bo_vmap(section->mem); 409 if (drm_WARN_ON(&ptdev->base, ret)) 410 return; 411 412 memcpy(section->mem->kmap, section->data.buf, section->data.size); 413 if (section->flags & CSF_FW_BINARY_IFACE_ENTRY_ZERO) { 414 memset(section->mem->kmap + section->data.size, 0, 415 panthor_kernel_bo_size(section->mem) - section->data.size); 416 } 417 418 if (!was_mapped) 419 panthor_kernel_bo_vunmap(section->mem); 420 } 421 422 /** 423 * panthor_fw_alloc_queue_iface_mem() - Allocate a ring-buffer interfaces. 424 * @ptdev: Device. 425 * @input: Pointer holding the input interface on success. 426 * Should be ignored on failure. 427 * @output: Pointer holding the output interface on success. 428 * Should be ignored on failure. 429 * @input_fw_va: Pointer holding the input interface FW VA on success. 430 * Should be ignored on failure. 431 * @output_fw_va: Pointer holding the output interface FW VA on success. 432 * Should be ignored on failure. 433 * 434 * Allocates panthor_fw_ringbuf_{input,out}_iface interfaces. The input 435 * interface is at offset 0, and the output interface at offset 4096. 436 * 437 * Return: A valid pointer in case of success, an ERR_PTR() otherwise. 438 */ 439 struct panthor_kernel_bo * 440 panthor_fw_alloc_queue_iface_mem(struct panthor_device *ptdev, 441 struct panthor_fw_ringbuf_input_iface **input, 442 const struct panthor_fw_ringbuf_output_iface **output, 443 u32 *input_fw_va, u32 *output_fw_va) 444 { 445 struct panthor_kernel_bo *mem; 446 int ret; 447 448 mem = panthor_kernel_bo_create(ptdev, ptdev->fw->vm, SZ_8K, 449 DRM_PANTHOR_BO_NO_MMAP, 450 DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC | 451 DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED, 452 PANTHOR_VM_KERNEL_AUTO_VA); 453 if (IS_ERR(mem)) 454 return mem; 455 456 ret = panthor_kernel_bo_vmap(mem); 457 if (ret) { 458 panthor_kernel_bo_destroy(mem); 459 return ERR_PTR(ret); 460 } 461 462 memset(mem->kmap, 0, panthor_kernel_bo_size(mem)); 463 *input = mem->kmap; 464 *output = mem->kmap + SZ_4K; 465 *input_fw_va = panthor_kernel_bo_gpuva(mem); 466 *output_fw_va = *input_fw_va + SZ_4K; 467 468 return mem; 469 } 470 471 /** 472 * panthor_fw_alloc_suspend_buf_mem() - Allocate a suspend buffer for a command stream group. 473 * @ptdev: Device. 474 * @size: Size of the suspend buffer. 475 * 476 * Return: A valid pointer in case of success, an ERR_PTR() otherwise. 477 */ 478 struct panthor_kernel_bo * 479 panthor_fw_alloc_suspend_buf_mem(struct panthor_device *ptdev, size_t size) 480 { 481 return panthor_kernel_bo_create(ptdev, panthor_fw_vm(ptdev), size, 482 DRM_PANTHOR_BO_NO_MMAP, 483 DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC, 484 PANTHOR_VM_KERNEL_AUTO_VA); 485 } 486 487 static int panthor_fw_load_section_entry(struct panthor_device *ptdev, 488 const struct firmware *fw, 489 struct panthor_fw_binary_iter *iter, 490 u32 ehdr) 491 { 492 ssize_t vm_pgsz = panthor_vm_page_size(ptdev->fw->vm); 493 struct panthor_fw_binary_section_entry_hdr hdr; 494 struct panthor_fw_section *section; 495 u32 section_size; 496 u32 name_len; 497 int ret; 498 499 ret = panthor_fw_binary_iter_read(ptdev, iter, &hdr, sizeof(hdr)); 500 if (ret) 501 return ret; 502 503 if (hdr.data.end < hdr.data.start) { 504 drm_err(&ptdev->base, "Firmware corrupted, data.end < data.start (0x%x < 0x%x)\n", 505 hdr.data.end, hdr.data.start); 506 return -EINVAL; 507 } 508 509 if (hdr.va.end < hdr.va.start) { 510 drm_err(&ptdev->base, "Firmware corrupted, hdr.va.end < hdr.va.start (0x%x < 0x%x)\n", 511 hdr.va.end, hdr.va.start); 512 return -EINVAL; 513 } 514 515 if (hdr.data.end > fw->size) { 516 drm_err(&ptdev->base, "Firmware corrupted, file truncated? data_end=0x%x > fw size=0x%zx\n", 517 hdr.data.end, fw->size); 518 return -EINVAL; 519 } 520 521 if (!IS_ALIGNED(hdr.va.start, vm_pgsz) || !IS_ALIGNED(hdr.va.end, vm_pgsz)) { 522 drm_err(&ptdev->base, "Firmware corrupted, virtual addresses not page aligned: 0x%x-0x%x\n", 523 hdr.va.start, hdr.va.end); 524 return -EINVAL; 525 } 526 527 if (hdr.flags & ~CSF_FW_BINARY_IFACE_ENTRY_SUPPORTED_FLAGS) { 528 drm_err(&ptdev->base, "Firmware contains interface with unsupported flags (0x%x)\n", 529 hdr.flags); 530 return -EINVAL; 531 } 532 533 if (hdr.flags & CSF_FW_BINARY_IFACE_ENTRY_PROT) { 534 drm_warn(&ptdev->base, 535 "Firmware protected mode entry not be supported, ignoring"); 536 return 0; 537 } 538 539 if (hdr.va.start == CSF_MCU_SHARED_REGION_START && 540 !(hdr.flags & CSF_FW_BINARY_IFACE_ENTRY_SHARED)) { 541 drm_err(&ptdev->base, 542 "Interface at 0x%llx must be shared", CSF_MCU_SHARED_REGION_START); 543 return -EINVAL; 544 } 545 546 name_len = iter->size - iter->offset; 547 548 section = drmm_kzalloc(&ptdev->base, sizeof(*section), GFP_KERNEL); 549 if (!section) 550 return -ENOMEM; 551 552 list_add_tail(§ion->node, &ptdev->fw->sections); 553 section->flags = hdr.flags; 554 section->data.size = hdr.data.end - hdr.data.start; 555 556 if (section->data.size > 0) { 557 void *data = drmm_kmalloc(&ptdev->base, section->data.size, GFP_KERNEL); 558 559 if (!data) 560 return -ENOMEM; 561 562 memcpy(data, fw->data + hdr.data.start, section->data.size); 563 section->data.buf = data; 564 } 565 566 if (name_len > 0) { 567 char *name = drmm_kmalloc(&ptdev->base, name_len + 1, GFP_KERNEL); 568 569 if (!name) 570 return -ENOMEM; 571 572 memcpy(name, iter->data + iter->offset, name_len); 573 name[name_len] = '\0'; 574 section->name = name; 575 } 576 577 section_size = hdr.va.end - hdr.va.start; 578 if (section_size) { 579 u32 cache_mode = hdr.flags & CSF_FW_BINARY_IFACE_ENTRY_CACHE_MODE_MASK; 580 struct panthor_gem_object *bo; 581 u32 vm_map_flags = 0; 582 struct sg_table *sgt; 583 u64 va = hdr.va.start; 584 585 if (!(hdr.flags & CSF_FW_BINARY_IFACE_ENTRY_WR)) 586 vm_map_flags |= DRM_PANTHOR_VM_BIND_OP_MAP_READONLY; 587 588 if (!(hdr.flags & CSF_FW_BINARY_IFACE_ENTRY_EX)) 589 vm_map_flags |= DRM_PANTHOR_VM_BIND_OP_MAP_NOEXEC; 590 591 /* TODO: CSF_FW_BINARY_IFACE_ENTRY_CACHE_MODE_*_COHERENT are mapped to 592 * non-cacheable for now. We might want to introduce a new 593 * IOMMU_xxx flag (or abuse IOMMU_MMIO, which maps to device 594 * memory and is currently not used by our driver) for 595 * AS_MEMATTR_AARCH64_SHARED memory, so we can take benefit 596 * of IO-coherent systems. 597 */ 598 if (cache_mode != CSF_FW_BINARY_IFACE_ENTRY_CACHE_MODE_CACHED) 599 vm_map_flags |= DRM_PANTHOR_VM_BIND_OP_MAP_UNCACHED; 600 601 section->mem = panthor_kernel_bo_create(ptdev, panthor_fw_vm(ptdev), 602 section_size, 603 DRM_PANTHOR_BO_NO_MMAP, 604 vm_map_flags, va); 605 if (IS_ERR(section->mem)) 606 return PTR_ERR(section->mem); 607 608 if (drm_WARN_ON(&ptdev->base, section->mem->va_node.start != hdr.va.start)) 609 return -EINVAL; 610 611 if (section->flags & CSF_FW_BINARY_IFACE_ENTRY_SHARED) { 612 ret = panthor_kernel_bo_vmap(section->mem); 613 if (ret) 614 return ret; 615 } 616 617 panthor_fw_init_section_mem(ptdev, section); 618 619 bo = to_panthor_bo(section->mem->obj); 620 sgt = drm_gem_shmem_get_pages_sgt(&bo->base); 621 if (IS_ERR(sgt)) 622 return PTR_ERR(sgt); 623 624 dma_sync_sgtable_for_device(ptdev->base.dev, sgt, DMA_TO_DEVICE); 625 } 626 627 if (hdr.va.start == CSF_MCU_SHARED_REGION_START) 628 ptdev->fw->shared_section = section; 629 630 return 0; 631 } 632 633 static int panthor_fw_read_build_info(struct panthor_device *ptdev, 634 const struct firmware *fw, 635 struct panthor_fw_binary_iter *iter, 636 u32 ehdr) 637 { 638 struct panthor_fw_build_info_hdr hdr; 639 char header[9]; 640 const char git_sha_header[sizeof(header)] = "git_sha: "; 641 int ret; 642 643 ret = panthor_fw_binary_iter_read(ptdev, iter, &hdr, sizeof(hdr)); 644 if (ret) 645 return ret; 646 647 if (hdr.meta_start > fw->size || 648 hdr.meta_start + hdr.meta_size > fw->size) { 649 drm_err(&ptdev->base, "Firmware build info corrupt\n"); 650 /* We don't need the build info, so continue */ 651 return 0; 652 } 653 654 if (memcmp(git_sha_header, fw->data + hdr.meta_start, 655 sizeof(git_sha_header))) { 656 /* Not the expected header, this isn't metadata we understand */ 657 return 0; 658 } 659 660 /* Check that the git SHA is NULL terminated as expected */ 661 if (fw->data[hdr.meta_start + hdr.meta_size - 1] != '\0') { 662 drm_warn(&ptdev->base, "Firmware's git sha is not NULL terminated\n"); 663 /* Don't treat as fatal */ 664 return 0; 665 } 666 667 drm_info(&ptdev->base, "Firmware git sha: %s\n", 668 fw->data + hdr.meta_start + sizeof(git_sha_header)); 669 670 return 0; 671 } 672 673 static void 674 panthor_reload_fw_sections(struct panthor_device *ptdev, bool full_reload) 675 { 676 struct panthor_fw_section *section; 677 678 list_for_each_entry(section, &ptdev->fw->sections, node) { 679 struct sg_table *sgt; 680 681 if (!full_reload && !(section->flags & CSF_FW_BINARY_IFACE_ENTRY_WR)) 682 continue; 683 684 panthor_fw_init_section_mem(ptdev, section); 685 sgt = drm_gem_shmem_get_pages_sgt(&to_panthor_bo(section->mem->obj)->base); 686 if (!drm_WARN_ON(&ptdev->base, IS_ERR_OR_NULL(sgt))) 687 dma_sync_sgtable_for_device(ptdev->base.dev, sgt, DMA_TO_DEVICE); 688 } 689 } 690 691 static int panthor_fw_load_entry(struct panthor_device *ptdev, 692 const struct firmware *fw, 693 struct panthor_fw_binary_iter *iter) 694 { 695 struct panthor_fw_binary_iter eiter; 696 u32 ehdr; 697 int ret; 698 699 ret = panthor_fw_binary_iter_read(ptdev, iter, &ehdr, sizeof(ehdr)); 700 if (ret) 701 return ret; 702 703 if ((iter->offset % sizeof(u32)) || 704 (CSF_FW_BINARY_ENTRY_SIZE(ehdr) % sizeof(u32))) { 705 drm_err(&ptdev->base, "Firmware entry isn't 32 bit aligned, offset=0x%x size=0x%x\n", 706 (u32)(iter->offset - sizeof(u32)), CSF_FW_BINARY_ENTRY_SIZE(ehdr)); 707 return -EINVAL; 708 } 709 710 if (panthor_fw_binary_sub_iter_init(ptdev, iter, &eiter, 711 CSF_FW_BINARY_ENTRY_SIZE(ehdr) - sizeof(ehdr))) 712 return -EINVAL; 713 714 switch (CSF_FW_BINARY_ENTRY_TYPE(ehdr)) { 715 case CSF_FW_BINARY_ENTRY_TYPE_IFACE: 716 return panthor_fw_load_section_entry(ptdev, fw, &eiter, ehdr); 717 case CSF_FW_BINARY_ENTRY_TYPE_BUILD_INFO_METADATA: 718 return panthor_fw_read_build_info(ptdev, fw, &eiter, ehdr); 719 720 /* FIXME: handle those entry types? */ 721 case CSF_FW_BINARY_ENTRY_TYPE_CONFIG: 722 case CSF_FW_BINARY_ENTRY_TYPE_FUTF_TEST: 723 case CSF_FW_BINARY_ENTRY_TYPE_TRACE_BUFFER: 724 case CSF_FW_BINARY_ENTRY_TYPE_TIMELINE_METADATA: 725 return 0; 726 default: 727 break; 728 } 729 730 if (ehdr & CSF_FW_BINARY_ENTRY_OPTIONAL) 731 return 0; 732 733 drm_err(&ptdev->base, 734 "Unsupported non-optional entry type %u in firmware\n", 735 CSF_FW_BINARY_ENTRY_TYPE(ehdr)); 736 return -EINVAL; 737 } 738 739 static int panthor_fw_load(struct panthor_device *ptdev) 740 { 741 const struct firmware *fw = NULL; 742 struct panthor_fw_binary_iter iter = {}; 743 struct panthor_fw_binary_hdr hdr; 744 char fw_path[128]; 745 int ret; 746 747 snprintf(fw_path, sizeof(fw_path), "arm/mali/arch%d.%d/%s", 748 (u32)GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id), 749 (u32)GPU_ARCH_MINOR(ptdev->gpu_info.gpu_id), 750 CSF_FW_NAME); 751 752 ret = request_firmware(&fw, fw_path, ptdev->base.dev); 753 if (ret) { 754 drm_err(&ptdev->base, "Failed to load firmware image '%s'\n", 755 CSF_FW_NAME); 756 return ret; 757 } 758 759 iter.data = fw->data; 760 iter.size = fw->size; 761 ret = panthor_fw_binary_iter_read(ptdev, &iter, &hdr, sizeof(hdr)); 762 if (ret) 763 goto out; 764 765 if (hdr.magic != CSF_FW_BINARY_HEADER_MAGIC) { 766 ret = -EINVAL; 767 drm_err(&ptdev->base, "Invalid firmware magic\n"); 768 goto out; 769 } 770 771 if (hdr.major != CSF_FW_BINARY_HEADER_MAJOR_MAX) { 772 ret = -EINVAL; 773 drm_err(&ptdev->base, "Unsupported firmware binary header version %d.%d (expected %d.x)\n", 774 hdr.major, hdr.minor, CSF_FW_BINARY_HEADER_MAJOR_MAX); 775 goto out; 776 } 777 778 if (hdr.size > iter.size) { 779 drm_err(&ptdev->base, "Firmware image is truncated\n"); 780 goto out; 781 } 782 783 iter.size = hdr.size; 784 785 while (iter.offset < hdr.size) { 786 ret = panthor_fw_load_entry(ptdev, fw, &iter); 787 if (ret) 788 goto out; 789 } 790 791 if (!ptdev->fw->shared_section) { 792 drm_err(&ptdev->base, "Shared interface region not found\n"); 793 ret = -EINVAL; 794 goto out; 795 } 796 797 out: 798 release_firmware(fw); 799 return ret; 800 } 801 802 /** 803 * iface_fw_to_cpu_addr() - Turn an MCU address into a CPU address 804 * @ptdev: Device. 805 * @mcu_va: MCU address. 806 * 807 * Return: NULL if the address is not part of the shared section, non-NULL otherwise. 808 */ 809 static void *iface_fw_to_cpu_addr(struct panthor_device *ptdev, u32 mcu_va) 810 { 811 u64 shared_mem_start = panthor_kernel_bo_gpuva(ptdev->fw->shared_section->mem); 812 u64 shared_mem_end = shared_mem_start + 813 panthor_kernel_bo_size(ptdev->fw->shared_section->mem); 814 if (mcu_va < shared_mem_start || mcu_va >= shared_mem_end) 815 return NULL; 816 817 return ptdev->fw->shared_section->mem->kmap + (mcu_va - shared_mem_start); 818 } 819 820 static int panthor_init_cs_iface(struct panthor_device *ptdev, 821 unsigned int csg_idx, unsigned int cs_idx) 822 { 823 struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev); 824 struct panthor_fw_csg_iface *csg_iface = panthor_fw_get_csg_iface(ptdev, csg_idx); 825 struct panthor_fw_cs_iface *cs_iface = &ptdev->fw->iface.streams[csg_idx][cs_idx]; 826 u64 shared_section_sz = panthor_kernel_bo_size(ptdev->fw->shared_section->mem); 827 u32 iface_offset = CSF_GROUP_CONTROL_OFFSET + 828 (csg_idx * glb_iface->control->group_stride) + 829 CSF_STREAM_CONTROL_OFFSET + 830 (cs_idx * csg_iface->control->stream_stride); 831 struct panthor_fw_cs_iface *first_cs_iface = 832 panthor_fw_get_cs_iface(ptdev, 0, 0); 833 834 if (iface_offset + sizeof(*cs_iface) >= shared_section_sz) 835 return -EINVAL; 836 837 spin_lock_init(&cs_iface->lock); 838 cs_iface->control = ptdev->fw->shared_section->mem->kmap + iface_offset; 839 cs_iface->input = iface_fw_to_cpu_addr(ptdev, cs_iface->control->input_va); 840 cs_iface->output = iface_fw_to_cpu_addr(ptdev, cs_iface->control->output_va); 841 842 if (!cs_iface->input || !cs_iface->output) { 843 drm_err(&ptdev->base, "Invalid stream control interface input/output VA"); 844 return -EINVAL; 845 } 846 847 if (cs_iface != first_cs_iface) { 848 if (cs_iface->control->features != first_cs_iface->control->features) { 849 drm_err(&ptdev->base, "Expecting identical CS slots"); 850 return -EINVAL; 851 } 852 } else { 853 u32 reg_count = CS_FEATURES_WORK_REGS(cs_iface->control->features); 854 855 ptdev->csif_info.cs_reg_count = reg_count; 856 ptdev->csif_info.unpreserved_cs_reg_count = CSF_UNPRESERVED_REG_COUNT; 857 } 858 859 return 0; 860 } 861 862 static bool compare_csg(const struct panthor_fw_csg_control_iface *a, 863 const struct panthor_fw_csg_control_iface *b) 864 { 865 if (a->features != b->features) 866 return false; 867 if (a->suspend_size != b->suspend_size) 868 return false; 869 if (a->protm_suspend_size != b->protm_suspend_size) 870 return false; 871 if (a->stream_num != b->stream_num) 872 return false; 873 return true; 874 } 875 876 static int panthor_init_csg_iface(struct panthor_device *ptdev, 877 unsigned int csg_idx) 878 { 879 struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev); 880 struct panthor_fw_csg_iface *csg_iface = &ptdev->fw->iface.groups[csg_idx]; 881 u64 shared_section_sz = panthor_kernel_bo_size(ptdev->fw->shared_section->mem); 882 u32 iface_offset = CSF_GROUP_CONTROL_OFFSET + (csg_idx * glb_iface->control->group_stride); 883 unsigned int i; 884 885 if (iface_offset + sizeof(*csg_iface) >= shared_section_sz) 886 return -EINVAL; 887 888 spin_lock_init(&csg_iface->lock); 889 csg_iface->control = ptdev->fw->shared_section->mem->kmap + iface_offset; 890 csg_iface->input = iface_fw_to_cpu_addr(ptdev, csg_iface->control->input_va); 891 csg_iface->output = iface_fw_to_cpu_addr(ptdev, csg_iface->control->output_va); 892 893 if (csg_iface->control->stream_num < MIN_CS_PER_CSG || 894 csg_iface->control->stream_num > MAX_CS_PER_CSG) 895 return -EINVAL; 896 897 if (!csg_iface->input || !csg_iface->output) { 898 drm_err(&ptdev->base, "Invalid group control interface input/output VA"); 899 return -EINVAL; 900 } 901 902 if (csg_idx > 0) { 903 struct panthor_fw_csg_iface *first_csg_iface = 904 panthor_fw_get_csg_iface(ptdev, 0); 905 906 if (!compare_csg(first_csg_iface->control, csg_iface->control)) { 907 drm_err(&ptdev->base, "Expecting identical CSG slots"); 908 return -EINVAL; 909 } 910 } 911 912 for (i = 0; i < csg_iface->control->stream_num; i++) { 913 int ret = panthor_init_cs_iface(ptdev, csg_idx, i); 914 915 if (ret) 916 return ret; 917 } 918 919 return 0; 920 } 921 922 static u32 panthor_get_instr_features(struct panthor_device *ptdev) 923 { 924 struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev); 925 926 if (glb_iface->control->version < CSF_IFACE_VERSION(1, 1, 0)) 927 return 0; 928 929 return glb_iface->control->instr_features; 930 } 931 932 static int panthor_fw_init_ifaces(struct panthor_device *ptdev) 933 { 934 struct panthor_fw_global_iface *glb_iface = &ptdev->fw->iface.global; 935 unsigned int i; 936 937 if (!ptdev->fw->shared_section->mem->kmap) 938 return -EINVAL; 939 940 spin_lock_init(&glb_iface->lock); 941 glb_iface->control = ptdev->fw->shared_section->mem->kmap; 942 943 if (!glb_iface->control->version) { 944 drm_err(&ptdev->base, "Firmware version is 0. Firmware may have failed to boot"); 945 return -EINVAL; 946 } 947 948 glb_iface->input = iface_fw_to_cpu_addr(ptdev, glb_iface->control->input_va); 949 glb_iface->output = iface_fw_to_cpu_addr(ptdev, glb_iface->control->output_va); 950 if (!glb_iface->input || !glb_iface->output) { 951 drm_err(&ptdev->base, "Invalid global control interface input/output VA"); 952 return -EINVAL; 953 } 954 955 if (glb_iface->control->group_num > MAX_CSGS || 956 glb_iface->control->group_num < MIN_CSGS) { 957 drm_err(&ptdev->base, "Invalid number of control groups"); 958 return -EINVAL; 959 } 960 961 for (i = 0; i < glb_iface->control->group_num; i++) { 962 int ret = panthor_init_csg_iface(ptdev, i); 963 964 if (ret) 965 return ret; 966 } 967 968 drm_info(&ptdev->base, "CSF FW using interface v%d.%d.%d, Features %#x Instrumentation features %#x", 969 CSF_IFACE_VERSION_MAJOR(glb_iface->control->version), 970 CSF_IFACE_VERSION_MINOR(glb_iface->control->version), 971 CSF_IFACE_VERSION_PATCH(glb_iface->control->version), 972 glb_iface->control->features, 973 panthor_get_instr_features(ptdev)); 974 return 0; 975 } 976 977 static void panthor_fw_init_global_iface(struct panthor_device *ptdev) 978 { 979 struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev); 980 981 /* Enable all cores. */ 982 glb_iface->input->core_en_mask = ptdev->gpu_info.shader_present; 983 984 /* Setup timers. */ 985 glb_iface->input->poweroff_timer = panthor_fw_conv_timeout(ptdev, PWROFF_HYSTERESIS_US); 986 glb_iface->input->progress_timer = PROGRESS_TIMEOUT_CYCLES >> PROGRESS_TIMEOUT_SCALE_SHIFT; 987 glb_iface->input->idle_timer = panthor_fw_conv_timeout(ptdev, IDLE_HYSTERESIS_US); 988 989 /* Enable interrupts we care about. */ 990 glb_iface->input->ack_irq_mask = GLB_CFG_ALLOC_EN | 991 GLB_PING | 992 GLB_CFG_PROGRESS_TIMER | 993 GLB_CFG_POWEROFF_TIMER | 994 GLB_IDLE_EN | 995 GLB_IDLE; 996 997 panthor_fw_update_reqs(glb_iface, req, GLB_IDLE_EN, GLB_IDLE_EN); 998 panthor_fw_toggle_reqs(glb_iface, req, ack, 999 GLB_CFG_ALLOC_EN | 1000 GLB_CFG_POWEROFF_TIMER | 1001 GLB_CFG_PROGRESS_TIMER); 1002 1003 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); 1004 1005 /* Kick the watchdog. */ 1006 mod_delayed_work(ptdev->reset.wq, &ptdev->fw->watchdog.ping_work, 1007 msecs_to_jiffies(PING_INTERVAL_MS)); 1008 } 1009 1010 static void panthor_job_irq_handler(struct panthor_device *ptdev, u32 status) 1011 { 1012 if (!ptdev->fw->booted && (status & JOB_INT_GLOBAL_IF)) 1013 ptdev->fw->booted = true; 1014 1015 wake_up_all(&ptdev->fw->req_waitqueue); 1016 1017 /* If the FW is not booted, don't process IRQs, just flag the FW as booted. */ 1018 if (!ptdev->fw->booted) 1019 return; 1020 1021 panthor_sched_report_fw_events(ptdev, status); 1022 } 1023 PANTHOR_IRQ_HANDLER(job, JOB, panthor_job_irq_handler); 1024 1025 static int panthor_fw_start(struct panthor_device *ptdev) 1026 { 1027 bool timedout = false; 1028 1029 ptdev->fw->booted = false; 1030 panthor_job_irq_resume(&ptdev->fw->irq, ~0); 1031 gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_AUTO); 1032 1033 if (!wait_event_timeout(ptdev->fw->req_waitqueue, 1034 ptdev->fw->booted, 1035 msecs_to_jiffies(1000))) { 1036 if (!ptdev->fw->booted && 1037 !(gpu_read(ptdev, JOB_INT_STAT) & JOB_INT_GLOBAL_IF)) 1038 timedout = true; 1039 } 1040 1041 if (timedout) { 1042 static const char * const status_str[] = { 1043 [MCU_STATUS_DISABLED] = "disabled", 1044 [MCU_STATUS_ENABLED] = "enabled", 1045 [MCU_STATUS_HALT] = "halt", 1046 [MCU_STATUS_FATAL] = "fatal", 1047 }; 1048 u32 status = gpu_read(ptdev, MCU_STATUS); 1049 1050 drm_err(&ptdev->base, "Failed to boot MCU (status=%s)", 1051 status < ARRAY_SIZE(status_str) ? status_str[status] : "unknown"); 1052 return -ETIMEDOUT; 1053 } 1054 1055 return 0; 1056 } 1057 1058 static void panthor_fw_stop(struct panthor_device *ptdev) 1059 { 1060 u32 status; 1061 1062 gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_DISABLE); 1063 if (readl_poll_timeout(ptdev->iomem + MCU_STATUS, status, 1064 status == MCU_STATUS_DISABLED, 10, 100000)) 1065 drm_err(&ptdev->base, "Failed to stop MCU"); 1066 } 1067 1068 /** 1069 * panthor_fw_pre_reset() - Call before a reset. 1070 * @ptdev: Device. 1071 * @on_hang: true if the reset was triggered on a GPU hang. 1072 * 1073 * If the reset is not triggered on a hang, we try to gracefully halt the 1074 * MCU, so we can do a fast-reset when panthor_fw_post_reset() is called. 1075 */ 1076 void panthor_fw_pre_reset(struct panthor_device *ptdev, bool on_hang) 1077 { 1078 /* Make sure we won't be woken up by a ping. */ 1079 cancel_delayed_work_sync(&ptdev->fw->watchdog.ping_work); 1080 1081 ptdev->reset.fast = false; 1082 1083 if (!on_hang) { 1084 struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev); 1085 u32 status; 1086 1087 panthor_fw_update_reqs(glb_iface, req, GLB_HALT, GLB_HALT); 1088 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); 1089 if (!readl_poll_timeout(ptdev->iomem + MCU_STATUS, status, 1090 status == MCU_STATUS_HALT, 10, 100000)) { 1091 ptdev->reset.fast = true; 1092 } else { 1093 drm_warn(&ptdev->base, "Failed to cleanly suspend MCU"); 1094 } 1095 } 1096 1097 panthor_job_irq_suspend(&ptdev->fw->irq); 1098 } 1099 1100 /** 1101 * panthor_fw_post_reset() - Call after a reset. 1102 * @ptdev: Device. 1103 * 1104 * Start the FW. If this is not a fast reset, all FW sections are reloaded to 1105 * make sure we can recover from a memory corruption. 1106 */ 1107 int panthor_fw_post_reset(struct panthor_device *ptdev) 1108 { 1109 int ret; 1110 1111 /* Make the MCU VM active. */ 1112 ret = panthor_vm_active(ptdev->fw->vm); 1113 if (ret) 1114 return ret; 1115 1116 if (!ptdev->reset.fast) { 1117 /* On a slow reset, reload all sections, including RO ones. 1118 * We're not supposed to end up here anyway, let's just assume 1119 * the overhead of reloading everything is acceptable. 1120 */ 1121 panthor_reload_fw_sections(ptdev, true); 1122 } else { 1123 /* The FW detects 0 -> 1 transitions. Make sure we reset 1124 * the HALT bit before the FW is rebooted. 1125 * This is not needed on a slow reset because FW sections are 1126 * re-initialized. 1127 */ 1128 struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev); 1129 1130 panthor_fw_update_reqs(glb_iface, req, 0, GLB_HALT); 1131 } 1132 1133 ret = panthor_fw_start(ptdev); 1134 if (ret) { 1135 drm_err(&ptdev->base, "FW %s reset failed", 1136 ptdev->reset.fast ? "fast" : "slow"); 1137 return ret; 1138 } 1139 1140 /* We must re-initialize the global interface even on fast-reset. */ 1141 panthor_fw_init_global_iface(ptdev); 1142 return 0; 1143 } 1144 1145 /** 1146 * panthor_fw_unplug() - Called when the device is unplugged. 1147 * @ptdev: Device. 1148 * 1149 * This function must make sure all pending operations are flushed before 1150 * will release device resources, thus preventing any interaction with 1151 * the HW. 1152 * 1153 * If there is still FW-related work running after this function returns, 1154 * they must use drm_dev_{enter,exit}() and skip any HW access when 1155 * drm_dev_enter() returns false. 1156 */ 1157 void panthor_fw_unplug(struct panthor_device *ptdev) 1158 { 1159 struct panthor_fw_section *section; 1160 1161 cancel_delayed_work_sync(&ptdev->fw->watchdog.ping_work); 1162 1163 if (!IS_ENABLED(CONFIG_PM) || pm_runtime_active(ptdev->base.dev)) { 1164 /* Make sure the IRQ handler cannot be called after that point. */ 1165 if (ptdev->fw->irq.irq) 1166 panthor_job_irq_suspend(&ptdev->fw->irq); 1167 1168 panthor_fw_stop(ptdev); 1169 } 1170 1171 list_for_each_entry(section, &ptdev->fw->sections, node) 1172 panthor_kernel_bo_destroy(section->mem); 1173 1174 /* We intentionally don't call panthor_vm_idle() and let 1175 * panthor_mmu_unplug() release the AS we acquired with 1176 * panthor_vm_active() so we don't have to track the VM active/idle 1177 * state to keep the active_refcnt balanced. 1178 */ 1179 panthor_vm_put(ptdev->fw->vm); 1180 ptdev->fw->vm = NULL; 1181 1182 if (!IS_ENABLED(CONFIG_PM) || pm_runtime_active(ptdev->base.dev)) 1183 panthor_gpu_power_off(ptdev, L2, ptdev->gpu_info.l2_present, 20000); 1184 } 1185 1186 /** 1187 * panthor_fw_wait_acks() - Wait for requests to be acknowledged by the FW. 1188 * @req_ptr: Pointer to the req register. 1189 * @ack_ptr: Pointer to the ack register. 1190 * @wq: Wait queue to use for the sleeping wait. 1191 * @req_mask: Mask of requests to wait for. 1192 * @acked: Pointer to field that's updated with the acked requests. 1193 * If the function returns 0, *acked == req_mask. 1194 * @timeout_ms: Timeout expressed in milliseconds. 1195 * 1196 * Return: 0 on success, -ETIMEDOUT otherwise. 1197 */ 1198 static int panthor_fw_wait_acks(const u32 *req_ptr, const u32 *ack_ptr, 1199 wait_queue_head_t *wq, 1200 u32 req_mask, u32 *acked, 1201 u32 timeout_ms) 1202 { 1203 u32 ack, req = READ_ONCE(*req_ptr) & req_mask; 1204 int ret; 1205 1206 /* Busy wait for a few µsecs before falling back to a sleeping wait. */ 1207 *acked = req_mask; 1208 ret = read_poll_timeout_atomic(READ_ONCE, ack, 1209 (ack & req_mask) == req, 1210 0, 10, 0, 1211 *ack_ptr); 1212 if (!ret) 1213 return 0; 1214 1215 if (wait_event_timeout(*wq, (READ_ONCE(*ack_ptr) & req_mask) == req, 1216 msecs_to_jiffies(timeout_ms))) 1217 return 0; 1218 1219 /* Check one last time, in case we were not woken up for some reason. */ 1220 ack = READ_ONCE(*ack_ptr); 1221 if ((ack & req_mask) == req) 1222 return 0; 1223 1224 *acked = ~(req ^ ack) & req_mask; 1225 return -ETIMEDOUT; 1226 } 1227 1228 /** 1229 * panthor_fw_glb_wait_acks() - Wait for global requests to be acknowledged. 1230 * @ptdev: Device. 1231 * @req_mask: Mask of requests to wait for. 1232 * @acked: Pointer to field that's updated with the acked requests. 1233 * If the function returns 0, *acked == req_mask. 1234 * @timeout_ms: Timeout expressed in milliseconds. 1235 * 1236 * Return: 0 on success, -ETIMEDOUT otherwise. 1237 */ 1238 int panthor_fw_glb_wait_acks(struct panthor_device *ptdev, 1239 u32 req_mask, u32 *acked, 1240 u32 timeout_ms) 1241 { 1242 struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev); 1243 1244 /* GLB_HALT doesn't get acked through the FW interface. */ 1245 if (drm_WARN_ON(&ptdev->base, req_mask & (~GLB_REQ_MASK | GLB_HALT))) 1246 return -EINVAL; 1247 1248 return panthor_fw_wait_acks(&glb_iface->input->req, 1249 &glb_iface->output->ack, 1250 &ptdev->fw->req_waitqueue, 1251 req_mask, acked, timeout_ms); 1252 } 1253 1254 /** 1255 * panthor_fw_csg_wait_acks() - Wait for command stream group requests to be acknowledged. 1256 * @ptdev: Device. 1257 * @csg_slot: CSG slot ID. 1258 * @req_mask: Mask of requests to wait for. 1259 * @acked: Pointer to field that's updated with the acked requests. 1260 * If the function returns 0, *acked == req_mask. 1261 * @timeout_ms: Timeout expressed in milliseconds. 1262 * 1263 * Return: 0 on success, -ETIMEDOUT otherwise. 1264 */ 1265 int panthor_fw_csg_wait_acks(struct panthor_device *ptdev, u32 csg_slot, 1266 u32 req_mask, u32 *acked, u32 timeout_ms) 1267 { 1268 struct panthor_fw_csg_iface *csg_iface = panthor_fw_get_csg_iface(ptdev, csg_slot); 1269 int ret; 1270 1271 if (drm_WARN_ON(&ptdev->base, req_mask & ~CSG_REQ_MASK)) 1272 return -EINVAL; 1273 1274 ret = panthor_fw_wait_acks(&csg_iface->input->req, 1275 &csg_iface->output->ack, 1276 &ptdev->fw->req_waitqueue, 1277 req_mask, acked, timeout_ms); 1278 1279 /* 1280 * Check that all bits in the state field were updated, if any mismatch 1281 * then clear all bits in the state field. This allows code to do 1282 * (acked & CSG_STATE_MASK) and get the right value. 1283 */ 1284 1285 if ((*acked & CSG_STATE_MASK) != CSG_STATE_MASK) 1286 *acked &= ~CSG_STATE_MASK; 1287 1288 return ret; 1289 } 1290 1291 /** 1292 * panthor_fw_ring_csg_doorbells() - Ring command stream group doorbells. 1293 * @ptdev: Device. 1294 * @csg_mask: Bitmask encoding the command stream group doorbells to ring. 1295 * 1296 * This function is toggling bits in the doorbell_req and ringing the 1297 * global doorbell. It doesn't require a user doorbell to be attached to 1298 * the group. 1299 */ 1300 void panthor_fw_ring_csg_doorbells(struct panthor_device *ptdev, u32 csg_mask) 1301 { 1302 struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev); 1303 1304 panthor_fw_toggle_reqs(glb_iface, doorbell_req, doorbell_ack, csg_mask); 1305 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); 1306 } 1307 1308 static void panthor_fw_ping_work(struct work_struct *work) 1309 { 1310 struct panthor_fw *fw = container_of(work, struct panthor_fw, watchdog.ping_work.work); 1311 struct panthor_device *ptdev = fw->irq.ptdev; 1312 struct panthor_fw_global_iface *glb_iface = panthor_fw_get_glb_iface(ptdev); 1313 u32 acked; 1314 int ret; 1315 1316 if (panthor_device_reset_is_pending(ptdev)) 1317 return; 1318 1319 panthor_fw_toggle_reqs(glb_iface, req, ack, GLB_PING); 1320 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); 1321 1322 ret = panthor_fw_glb_wait_acks(ptdev, GLB_PING, &acked, 100); 1323 if (ret) { 1324 panthor_device_schedule_reset(ptdev); 1325 drm_err(&ptdev->base, "FW ping timeout, scheduling a reset"); 1326 } else { 1327 mod_delayed_work(ptdev->reset.wq, &fw->watchdog.ping_work, 1328 msecs_to_jiffies(PING_INTERVAL_MS)); 1329 } 1330 } 1331 1332 /** 1333 * panthor_fw_init() - Initialize FW related data. 1334 * @ptdev: Device. 1335 * 1336 * Return: 0 on success, a negative error code otherwise. 1337 */ 1338 int panthor_fw_init(struct panthor_device *ptdev) 1339 { 1340 struct panthor_fw *fw; 1341 int ret, irq; 1342 1343 fw = drmm_kzalloc(&ptdev->base, sizeof(*fw), GFP_KERNEL); 1344 if (!fw) 1345 return -ENOMEM; 1346 1347 ptdev->fw = fw; 1348 init_waitqueue_head(&fw->req_waitqueue); 1349 INIT_LIST_HEAD(&fw->sections); 1350 INIT_DELAYED_WORK(&fw->watchdog.ping_work, panthor_fw_ping_work); 1351 1352 irq = platform_get_irq_byname(to_platform_device(ptdev->base.dev), "job"); 1353 if (irq <= 0) 1354 return -ENODEV; 1355 1356 ret = panthor_request_job_irq(ptdev, &fw->irq, irq, 0); 1357 if (ret) { 1358 drm_err(&ptdev->base, "failed to request job irq"); 1359 return ret; 1360 } 1361 1362 ret = panthor_gpu_l2_power_on(ptdev); 1363 if (ret) 1364 return ret; 1365 1366 fw->vm = panthor_vm_create(ptdev, true, 1367 0, SZ_4G, 1368 CSF_MCU_SHARED_REGION_START, 1369 CSF_MCU_SHARED_REGION_SIZE); 1370 if (IS_ERR(fw->vm)) { 1371 ret = PTR_ERR(fw->vm); 1372 fw->vm = NULL; 1373 goto err_unplug_fw; 1374 } 1375 1376 ret = panthor_fw_load(ptdev); 1377 if (ret) 1378 goto err_unplug_fw; 1379 1380 ret = panthor_vm_active(fw->vm); 1381 if (ret) 1382 goto err_unplug_fw; 1383 1384 ret = panthor_fw_start(ptdev); 1385 if (ret) 1386 goto err_unplug_fw; 1387 1388 ret = panthor_fw_init_ifaces(ptdev); 1389 if (ret) 1390 goto err_unplug_fw; 1391 1392 panthor_fw_init_global_iface(ptdev); 1393 return 0; 1394 1395 err_unplug_fw: 1396 panthor_fw_unplug(ptdev); 1397 return ret; 1398 } 1399 1400 MODULE_FIRMWARE("arm/mali/arch10.8/mali_csffw.bin"); 1401