1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */ 3 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */ 4 /* 5 * Register definitions based on mali_midg_regmap.h 6 * (C) COPYRIGHT 2010-2018 ARM Limited. All rights reserved. 7 */ 8 #ifndef __PANFROST_REGS_H__ 9 #define __PANFROST_REGS_H__ 10 11 #define GPU_ID 0x00 12 #define GPU_L2_FEATURES 0x004 /* (RO) Level 2 cache features */ 13 #define GPU_CORE_FEATURES 0x008 /* (RO) Shader Core Features */ 14 #define GPU_TILER_FEATURES 0x00C /* (RO) Tiler Features */ 15 #define GPU_MEM_FEATURES 0x010 /* (RO) Memory system features */ 16 #define GROUPS_L2_COHERENT BIT(0) /* Cores groups are l2 coherent */ 17 18 #define GPU_MMU_FEATURES 0x014 /* (RO) MMU features */ 19 #define GPU_AS_PRESENT 0x018 /* (RO) Address space slots present */ 20 #define GPU_JS_PRESENT 0x01C /* (RO) Job slots present */ 21 22 #define GPU_INT_RAWSTAT 0x20 23 #define GPU_INT_CLEAR 0x24 24 #define GPU_INT_MASK 0x28 25 #define GPU_INT_STAT 0x2c 26 #define GPU_IRQ_FAULT BIT(0) 27 #define GPU_IRQ_MULTIPLE_FAULT BIT(7) 28 #define GPU_IRQ_RESET_COMPLETED BIT(8) 29 #define GPU_IRQ_POWER_CHANGED BIT(9) 30 #define GPU_IRQ_POWER_CHANGED_ALL BIT(10) 31 #define GPU_IRQ_PERFCNT_SAMPLE_COMPLETED BIT(16) 32 #define GPU_IRQ_CLEAN_CACHES_COMPLETED BIT(17) 33 #define GPU_IRQ_MASK_ALL \ 34 (GPU_IRQ_FAULT |\ 35 GPU_IRQ_MULTIPLE_FAULT |\ 36 GPU_IRQ_RESET_COMPLETED |\ 37 GPU_IRQ_POWER_CHANGED |\ 38 GPU_IRQ_POWER_CHANGED_ALL |\ 39 GPU_IRQ_PERFCNT_SAMPLE_COMPLETED |\ 40 GPU_IRQ_CLEAN_CACHES_COMPLETED) 41 #define GPU_IRQ_MASK_ERROR \ 42 ( \ 43 GPU_IRQ_FAULT |\ 44 GPU_IRQ_MULTIPLE_FAULT) 45 #define GPU_CMD 0x30 46 #define GPU_CMD_SOFT_RESET 0x01 47 #define GPU_CMD_HARD_RESET 0x02 48 #define GPU_CMD_PERFCNT_CLEAR 0x03 49 #define GPU_CMD_PERFCNT_SAMPLE 0x04 50 #define GPU_CMD_CYCLE_COUNT_START 0x05 51 #define GPU_CMD_CYCLE_COUNT_STOP 0x06 52 #define GPU_CMD_CLEAN_CACHES 0x07 53 #define GPU_CMD_CLEAN_INV_CACHES 0x08 54 #define GPU_STATUS 0x34 55 #define GPU_STATUS_PRFCNT_ACTIVE BIT(2) 56 #define GPU_LATEST_FLUSH_ID 0x38 57 #define GPU_PWR_KEY 0x50 /* (WO) Power manager key register */ 58 #define GPU_PWR_KEY_UNLOCK 0x2968A819 59 #define GPU_PWR_OVERRIDE0 0x54 /* (RW) Power manager override settings */ 60 #define GPU_PWR_OVERRIDE1 0x58 /* (RW) Power manager override settings */ 61 #define GPU_FAULT_STATUS 0x3C 62 #define GPU_FAULT_ADDRESS_LO 0x40 63 #define GPU_FAULT_ADDRESS_HI 0x44 64 65 #define GPU_PERFCNT_BASE_LO 0x60 66 #define GPU_PERFCNT_BASE_HI 0x64 67 #define GPU_PERFCNT_CFG 0x68 68 #define GPU_PERFCNT_CFG_MODE(x) (x) 69 #define GPU_PERFCNT_CFG_MODE_OFF 0 70 #define GPU_PERFCNT_CFG_MODE_MANUAL 1 71 #define GPU_PERFCNT_CFG_MODE_TILE 2 72 #define GPU_PERFCNT_CFG_AS(x) ((x) << 4) 73 #define GPU_PERFCNT_CFG_SETSEL(x) ((x) << 8) 74 #define GPU_PRFCNT_JM_EN 0x6c 75 #define GPU_PRFCNT_SHADER_EN 0x70 76 #define GPU_PRFCNT_TILER_EN 0x74 77 #define GPU_PRFCNT_MMU_L2_EN 0x7c 78 79 #define GPU_CYCLE_COUNT_LO 0x90 80 #define GPU_CYCLE_COUNT_HI 0x94 81 82 #define GPU_THREAD_MAX_THREADS 0x0A0 /* (RO) Maximum number of threads per core */ 83 #define GPU_THREAD_MAX_WORKGROUP_SIZE 0x0A4 /* (RO) Maximum workgroup size */ 84 #define GPU_THREAD_MAX_BARRIER_SIZE 0x0A8 /* (RO) Maximum threads waiting at a barrier */ 85 #define GPU_THREAD_FEATURES 0x0AC /* (RO) Thread features */ 86 #define GPU_THREAD_TLS_ALLOC 0x310 /* (RO) Number of threads per core that 87 * TLS must be allocated for */ 88 89 #define GPU_TEXTURE_FEATURES(n) (0x0B0 + ((n) * 4)) 90 #define GPU_JS_FEATURES(n) (0x0C0 + ((n) * 4)) 91 #define GPU_AFBC_FEATURES (0x4C) /* (RO) AFBC support on Bifrost */ 92 93 #define GPU_SHADER_PRESENT_LO 0x100 /* (RO) Shader core present bitmap, low word */ 94 #define GPU_SHADER_PRESENT_HI 0x104 /* (RO) Shader core present bitmap, high word */ 95 #define GPU_TILER_PRESENT_LO 0x110 /* (RO) Tiler core present bitmap, low word */ 96 #define GPU_TILER_PRESENT_HI 0x114 /* (RO) Tiler core present bitmap, high word */ 97 98 #define GPU_L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */ 99 #define GPU_L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */ 100 101 #define GPU_COHERENCY_FEATURES 0x300 /* (RO) Coherency features present */ 102 #define COHERENCY_ACE_LITE BIT(0) 103 #define COHERENCY_ACE BIT(1) 104 105 #define GPU_STACK_PRESENT_LO 0xE00 /* (RO) Core stack present bitmap, low word */ 106 #define GPU_STACK_PRESENT_HI 0xE04 /* (RO) Core stack present bitmap, high word */ 107 108 #define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */ 109 #define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */ 110 111 #define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */ 112 #define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */ 113 114 #define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */ 115 #define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */ 116 117 #define STACK_READY_LO 0xE10 /* (RO) Core stack ready bitmap, low word */ 118 #define STACK_READY_HI 0xE14 /* (RO) Core stack ready bitmap, high word */ 119 120 121 #define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */ 122 #define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */ 123 124 #define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */ 125 #define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */ 126 127 #define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */ 128 #define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */ 129 130 #define STACK_PWRON_LO 0xE20 /* (RO) Core stack power on bitmap, low word */ 131 #define STACK_PWRON_HI 0xE24 /* (RO) Core stack power on bitmap, high word */ 132 133 134 #define SHADER_PWROFF_LO 0x1C0 /* (WO) Shader core power off bitmap, low word */ 135 #define SHADER_PWROFF_HI 0x1C4 /* (WO) Shader core power off bitmap, high word */ 136 137 #define TILER_PWROFF_LO 0x1D0 /* (WO) Tiler core power off bitmap, low word */ 138 #define TILER_PWROFF_HI 0x1D4 /* (WO) Tiler core power off bitmap, high word */ 139 140 #define L2_PWROFF_LO 0x1E0 /* (WO) Level 2 cache power off bitmap, low word */ 141 #define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */ 142 143 #define STACK_PWROFF_LO 0xE30 /* (RO) Core stack power off bitmap, low word */ 144 #define STACK_PWROFF_HI 0xE34 /* (RO) Core stack power off bitmap, high word */ 145 146 147 #define SHADER_PWRTRANS_LO 0x200 /* (RO) Shader core power transition bitmap, low word */ 148 #define SHADER_PWRTRANS_HI 0x204 /* (RO) Shader core power transition bitmap, high word */ 149 150 #define TILER_PWRTRANS_LO 0x210 /* (RO) Tiler core power transition bitmap, low word */ 151 #define TILER_PWRTRANS_HI 0x214 /* (RO) Tiler core power transition bitmap, high word */ 152 153 #define L2_PWRTRANS_LO 0x220 /* (RO) Level 2 cache power transition bitmap, low word */ 154 #define L2_PWRTRANS_HI 0x224 /* (RO) Level 2 cache power transition bitmap, high word */ 155 156 #define STACK_PWRTRANS_LO 0xE40 /* (RO) Core stack power transition bitmap, low word */ 157 #define STACK_PWRTRANS_HI 0xE44 /* (RO) Core stack power transition bitmap, high word */ 158 159 160 #define SHADER_PWRACTIVE_LO 0x240 /* (RO) Shader core active bitmap, low word */ 161 #define SHADER_PWRACTIVE_HI 0x244 /* (RO) Shader core active bitmap, high word */ 162 163 #define TILER_PWRACTIVE_LO 0x250 /* (RO) Tiler core active bitmap, low word */ 164 #define TILER_PWRACTIVE_HI 0x254 /* (RO) Tiler core active bitmap, high word */ 165 166 #define L2_PWRACTIVE_LO 0x260 /* (RO) Level 2 cache active bitmap, low word */ 167 #define L2_PWRACTIVE_HI 0x264 /* (RO) Level 2 cache active bitmap, high word */ 168 169 #define GPU_JM_CONFIG 0xF00 /* (RW) Job Manager configuration register (Implementation specific register) */ 170 #define GPU_SHADER_CONFIG 0xF04 /* (RW) Shader core configuration settings (Implementation specific register) */ 171 #define GPU_TILER_CONFIG 0xF08 /* (RW) Tiler core configuration settings (Implementation specific register) */ 172 #define GPU_L2_MMU_CONFIG 0xF0C /* (RW) Configuration of the L2 cache and MMU (Implementation specific register) */ 173 174 /* L2_MMU_CONFIG register */ 175 #define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT 23 176 #define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY (0x1 << L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT) 177 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT 24 178 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 179 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 180 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 181 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 182 183 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT 26 184 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 185 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 186 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 187 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 188 189 #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS_SHIFT 12 190 #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS (0x7 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 191 192 #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES_SHIFT 15 193 #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES (0x7 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 194 195 /* SHADER_CONFIG register */ 196 #define SC_ALT_COUNTERS BIT(3) 197 #define SC_OVERRIDE_FWD_PIXEL_KILL BIT(4) 198 #define SC_SDC_DISABLE_OQ_DISCARD BIT(6) 199 #define SC_LS_ALLOW_ATTR_TYPES BIT(16) 200 #define SC_LS_PAUSEBUFFER_DISABLE BIT(16) 201 #define SC_TLS_HASH_ENABLE BIT(17) 202 #define SC_LS_ATTR_CHECK_DISABLE BIT(18) 203 #define SC_ENABLE_TEXGRD_FLAGS BIT(25) 204 #define SC_VAR_ALGORITHM BIT(29) 205 /* End SHADER_CONFIG register */ 206 207 /* TILER_CONFIG register */ 208 #define TC_CLOCK_GATE_OVERRIDE BIT(0) 209 210 /* JM_CONFIG register */ 211 #define JM_TIMESTAMP_OVERRIDE BIT(0) 212 #define JM_CLOCK_GATE_OVERRIDE BIT(1) 213 #define JM_JOB_THROTTLE_ENABLE BIT(2) 214 #define JM_JOB_THROTTLE_LIMIT_SHIFT 3 215 #define JM_MAX_JOB_THROTTLE_LIMIT 0x3F 216 #define JM_FORCE_COHERENCY_FEATURES_SHIFT 2 217 #define JM_IDVS_GROUP_SIZE_SHIFT 16 218 #define JM_DEFAULT_IDVS_GROUP_SIZE 0xF 219 #define JM_MAX_IDVS_GROUP_SIZE 0x3F 220 221 222 /* Job Control regs */ 223 #define JOB_INT_RAWSTAT 0x1000 224 #define JOB_INT_CLEAR 0x1004 225 #define JOB_INT_MASK 0x1008 226 #define JOB_INT_STAT 0x100c 227 #define JOB_INT_JS_STATE 0x1010 228 #define JOB_INT_THROTTLE 0x1014 229 230 #define MK_JS_MASK(j) (0x10001 << (j)) 231 #define JOB_INT_MASK_ERR(j) BIT((j) + 16) 232 #define JOB_INT_MASK_DONE(j) BIT(j) 233 234 #define JS_BASE 0x1800 235 #define JS_SLOT_STRIDE 0x80 236 237 #define JS_HEAD_LO(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x00) 238 #define JS_HEAD_HI(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x04) 239 #define JS_TAIL_LO(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x08) 240 #define JS_TAIL_HI(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x0c) 241 #define JS_AFFINITY_LO(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x10) 242 #define JS_AFFINITY_HI(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x14) 243 #define JS_CONFIG(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x18) 244 #define JS_XAFFINITY(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x1c) 245 #define JS_COMMAND(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x20) 246 #define JS_STATUS(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x24) 247 #define JS_HEAD_NEXT_LO(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x40) 248 #define JS_HEAD_NEXT_HI(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x44) 249 #define JS_AFFINITY_NEXT_LO(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x50) 250 #define JS_AFFINITY_NEXT_HI(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x54) 251 #define JS_CONFIG_NEXT(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x58) 252 #define JS_COMMAND_NEXT(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x60) 253 #define JS_FLUSH_ID_NEXT(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x70) 254 255 /* Possible values of JS_CONFIG and JS_CONFIG_NEXT registers */ 256 #define JS_CONFIG_START_FLUSH_CLEAN BIT(8) 257 #define JS_CONFIG_START_FLUSH_CLEAN_INVALIDATE (3u << 8) 258 #define JS_CONFIG_START_MMU BIT(10) 259 #define JS_CONFIG_JOB_CHAIN_FLAG BIT(11) 260 #define JS_CONFIG_END_FLUSH_CLEAN BIT(12) 261 #define JS_CONFIG_END_FLUSH_CLEAN_INVALIDATE (3u << 12) 262 #define JS_CONFIG_ENABLE_FLUSH_REDUCTION BIT(14) 263 #define JS_CONFIG_DISABLE_DESCRIPTOR_WR_BK BIT(15) 264 #define JS_CONFIG_THREAD_PRI(n) ((n) << 16) 265 266 #define JS_COMMAND_NOP 0x00 267 #define JS_COMMAND_START 0x01 268 #define JS_COMMAND_SOFT_STOP 0x02 /* Gently stop processing a job chain */ 269 #define JS_COMMAND_HARD_STOP 0x03 /* Rudely stop processing a job chain */ 270 #define JS_COMMAND_SOFT_STOP_0 0x04 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 0 */ 271 #define JS_COMMAND_HARD_STOP_0 0x05 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 0 */ 272 #define JS_COMMAND_SOFT_STOP_1 0x06 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 1 */ 273 #define JS_COMMAND_HARD_STOP_1 0x07 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 1 */ 274 275 /* MMU regs */ 276 #define MMU_INT_RAWSTAT 0x2000 277 #define MMU_INT_CLEAR 0x2004 278 #define MMU_INT_MASK 0x2008 279 #define MMU_INT_STAT 0x200c 280 281 /* AS_COMMAND register commands */ 282 #define AS_COMMAND_NOP 0x00 /* NOP Operation */ 283 #define AS_COMMAND_UPDATE 0x01 /* Broadcasts the values in AS_TRANSTAB and ASn_MEMATTR to all MMUs */ 284 #define AS_COMMAND_LOCK 0x02 /* Issue a lock region command to all MMUs */ 285 #define AS_COMMAND_UNLOCK 0x03 /* Issue a flush region command to all MMUs */ 286 #define AS_COMMAND_FLUSH 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs 287 (deprecated - only for use with T60x) */ 288 #define AS_COMMAND_FLUSH_PT 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs */ 289 #define AS_COMMAND_FLUSH_MEM 0x05 /* Wait for memory accesses to complete, flush all the L1s cache then 290 flush all L2 caches then issue a flush region command to all MMUs */ 291 292 #define MMU_BASE 0x2400 293 #define MMU_AS_SHIFT 0x06 294 #define MMU_AS(as) (MMU_BASE + ((as) << MMU_AS_SHIFT)) 295 296 #define AS_TRANSTAB_LO(as) (MMU_AS(as) + 0x00) /* (RW) Translation Table Base Address for address space n, low word */ 297 #define AS_TRANSTAB_HI(as) (MMU_AS(as) + 0x04) /* (RW) Translation Table Base Address for address space n, high word */ 298 #define AS_MEMATTR_LO(as) (MMU_AS(as) + 0x08) /* (RW) Memory attributes for address space n, low word. */ 299 #define AS_MEMATTR_HI(as) (MMU_AS(as) + 0x0C) /* (RW) Memory attributes for address space n, high word. */ 300 #define AS_LOCKADDR_LO(as) (MMU_AS(as) + 0x10) /* (RW) Lock region address for address space n, low word */ 301 #define AS_LOCKADDR_HI(as) (MMU_AS(as) + 0x14) /* (RW) Lock region address for address space n, high word */ 302 #define AS_COMMAND(as) (MMU_AS(as) + 0x18) /* (WO) MMU command register for address space n */ 303 #define AS_FAULTSTATUS(as) (MMU_AS(as) + 0x1C) /* (RO) MMU fault status register for address space n */ 304 #define AS_FAULTADDRESS_LO(as) (MMU_AS(as) + 0x20) /* (RO) Fault Address for address space n, low word */ 305 #define AS_FAULTADDRESS_HI(as) (MMU_AS(as) + 0x24) /* (RO) Fault Address for address space n, high word */ 306 #define AS_STATUS(as) (MMU_AS(as) + 0x28) /* (RO) Status flags for address space n */ 307 /* Additional Bifrost AS registers */ 308 #define AS_TRANSCFG_LO(as) (MMU_AS(as) + 0x30) /* (RW) Translation table configuration for address space n, low word */ 309 #define AS_TRANSCFG_HI(as) (MMU_AS(as) + 0x34) /* (RW) Translation table configuration for address space n, high word */ 310 #define AS_FAULTEXTRA_LO(as) (MMU_AS(as) + 0x38) /* (RO) Secondary fault address for address space n, low word */ 311 #define AS_FAULTEXTRA_HI(as) (MMU_AS(as) + 0x3C) /* (RO) Secondary fault address for address space n, high word */ 312 313 #define MMU_AS_STRIDE (1 << MMU_AS_SHIFT) 314 315 /* 316 * Begin LPAE MMU TRANSTAB register values 317 */ 318 #define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK 0xfffffffffffff000 319 #define AS_TRANSTAB_LPAE_ADRMODE_IDENTITY 0x2 320 #define AS_TRANSTAB_LPAE_ADRMODE_TABLE 0x3 321 #define AS_TRANSTAB_LPAE_ADRMODE_MASK 0x3 322 #define AS_TRANSTAB_LPAE_READ_INNER BIT(2) 323 #define AS_TRANSTAB_LPAE_SHARE_OUTER BIT(4) 324 325 #define AS_STATUS_AS_ACTIVE 0x01 326 327 #define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << 8) 328 #define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC (0x0 << 8) 329 #define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1 << 8) 330 #define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2 << 8) 331 #define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3 << 8) 332 333 #define AS_LOCK_REGION_MIN_SIZE (1ULL << 15) 334 335 #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg) 336 #define gpu_read(dev, reg) readl(dev->iomem + reg) 337 338 #endif 339