xref: /linux/drivers/gpu/drm/panfrost/panfrost_regs.h (revision 4e95bc268b915c3a19ec8b9110f61e4ea41a1ed0)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
3 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
4 /*
5  * Register definitions based on mali_midg_regmap.h
6  * (C) COPYRIGHT 2010-2018 ARM Limited. All rights reserved.
7  */
8 #ifndef __PANFROST_REGS_H__
9 #define __PANFROST_REGS_H__
10 
11 #define GPU_ID				0x00
12 #define GPU_L2_FEATURES			0x004	/* (RO) Level 2 cache features */
13 #define GPU_CORE_FEATURES		0x008	/* (RO) Shader Core Features */
14 #define GPU_TILER_FEATURES		0x00C	/* (RO) Tiler Features */
15 #define GPU_MEM_FEATURES		0x010	/* (RO) Memory system features */
16 #define   GROUPS_L2_COHERENT		BIT(0)	/* Cores groups are l2 coherent */
17 
18 #define GPU_MMU_FEATURES		0x014	/* (RO) MMU features */
19 #define GPU_AS_PRESENT			0x018	/* (RO) Address space slots present */
20 #define GPU_JS_PRESENT			0x01C	/* (RO) Job slots present */
21 
22 #define GPU_INT_RAWSTAT			0x20
23 #define GPU_INT_CLEAR			0x24
24 #define GPU_INT_MASK			0x28
25 #define GPU_INT_STAT			0x2c
26 #define   GPU_IRQ_FAULT			BIT(0)
27 #define   GPU_IRQ_MULTIPLE_FAULT	BIT(7)
28 #define   GPU_IRQ_RESET_COMPLETED	BIT(8)
29 #define   GPU_IRQ_POWER_CHANGED		BIT(9)
30 #define   GPU_IRQ_POWER_CHANGED_ALL	BIT(10)
31 #define   GPU_IRQ_PERFCNT_SAMPLE_COMPLETED BIT(16)
32 #define   GPU_IRQ_CLEAN_CACHES_COMPLETED BIT(17)
33 #define   GPU_IRQ_MASK_ALL			 \
34 	  (GPU_IRQ_FAULT			|\
35 	   GPU_IRQ_MULTIPLE_FAULT		|\
36 	   GPU_IRQ_RESET_COMPLETED		|\
37 	   GPU_IRQ_POWER_CHANGED		|\
38 	   GPU_IRQ_POWER_CHANGED_ALL		|\
39 	   GPU_IRQ_PERFCNT_SAMPLE_COMPLETED	|\
40 	   GPU_IRQ_CLEAN_CACHES_COMPLETED)
41 #define GPU_IRQ_MASK_ERROR	   		\
42 	(					\
43 	 GPU_IRQ_FAULT				|\
44 	 GPU_IRQ_MULTIPLE_FAULT)
45 #define GPU_CMD				0x30
46 #define   GPU_CMD_SOFT_RESET		0x01
47 #define GPU_STATUS			0x34
48 #define GPU_LATEST_FLUSH_ID		0x38
49 #define GPU_FAULT_STATUS		0x3C
50 #define GPU_FAULT_ADDRESS_LO		0x40
51 #define GPU_FAULT_ADDRESS_HI		0x44
52 
53 #define GPU_THREAD_MAX_THREADS		0x0A0	/* (RO) Maximum number of threads per core */
54 #define GPU_THREAD_MAX_WORKGROUP_SIZE	0x0A4	/* (RO) Maximum workgroup size */
55 #define GPU_THREAD_MAX_BARRIER_SIZE	0x0A8	/* (RO) Maximum threads waiting at a barrier */
56 #define GPU_THREAD_FEATURES		0x0AC	/* (RO) Thread features */
57 #define GPU_THREAD_TLS_ALLOC		0x310   /* (RO) Number of threads per core that
58 						 * TLS must be allocated for */
59 
60 #define GPU_TEXTURE_FEATURES(n)		(0x0B0 + ((n) * 4))
61 #define GPU_JS_FEATURES(n)		(0x0C0 + ((n) * 4))
62 
63 #define GPU_SHADER_PRESENT_LO		0x100	/* (RO) Shader core present bitmap, low word */
64 #define GPU_SHADER_PRESENT_HI		0x104	/* (RO) Shader core present bitmap, high word */
65 #define GPU_TILER_PRESENT_LO		0x110	/* (RO) Tiler core present bitmap, low word */
66 #define GPU_TILER_PRESENT_HI		0x114	/* (RO) Tiler core present bitmap, high word */
67 
68 #define GPU_L2_PRESENT_LO		0x120	/* (RO) Level 2 cache present bitmap, low word */
69 #define GPU_L2_PRESENT_HI		0x124	/* (RO) Level 2 cache present bitmap, high word */
70 
71 #define GPU_COHERENCY_FEATURES		0x300	/* (RO) Coherency features present */
72 #define   COHERENCY_ACE_LITE		BIT(0)
73 #define   COHERENCY_ACE			BIT(1)
74 
75 #define GPU_STACK_PRESENT_LO		0xE00   /* (RO) Core stack present bitmap, low word */
76 #define GPU_STACK_PRESENT_HI		0xE04   /* (RO) Core stack present bitmap, high word */
77 
78 #define SHADER_READY_LO			0x140	/* (RO) Shader core ready bitmap, low word */
79 #define SHADER_READY_HI			0x144	/* (RO) Shader core ready bitmap, high word */
80 
81 #define TILER_READY_LO			0x150	/* (RO) Tiler core ready bitmap, low word */
82 #define TILER_READY_HI			0x154	/* (RO) Tiler core ready bitmap, high word */
83 
84 #define L2_READY_LO			0x160	/* (RO) Level 2 cache ready bitmap, low word */
85 #define L2_READY_HI			0x164	/* (RO) Level 2 cache ready bitmap, high word */
86 
87 #define STACK_READY_LO			0xE10   /* (RO) Core stack ready bitmap, low word */
88 #define STACK_READY_HI			0xE14   /* (RO) Core stack ready bitmap, high word */
89 
90 
91 #define SHADER_PWRON_LO			0x180	/* (WO) Shader core power on bitmap, low word */
92 #define SHADER_PWRON_HI			0x184	/* (WO) Shader core power on bitmap, high word */
93 
94 #define TILER_PWRON_LO			0x190	/* (WO) Tiler core power on bitmap, low word */
95 #define TILER_PWRON_HI			0x194	/* (WO) Tiler core power on bitmap, high word */
96 
97 #define L2_PWRON_LO			0x1A0	/* (WO) Level 2 cache power on bitmap, low word */
98 #define L2_PWRON_HI			0x1A4	/* (WO) Level 2 cache power on bitmap, high word */
99 
100 #define STACK_PWRON_LO			0xE20   /* (RO) Core stack power on bitmap, low word */
101 #define STACK_PWRON_HI			0xE24   /* (RO) Core stack power on bitmap, high word */
102 
103 
104 #define SHADER_PWROFF_LO		0x1C0	/* (WO) Shader core power off bitmap, low word */
105 #define SHADER_PWROFF_HI		0x1C4	/* (WO) Shader core power off bitmap, high word */
106 
107 #define TILER_PWROFF_LO			0x1D0	/* (WO) Tiler core power off bitmap, low word */
108 #define TILER_PWROFF_HI			0x1D4	/* (WO) Tiler core power off bitmap, high word */
109 
110 #define L2_PWROFF_LO			0x1E0	/* (WO) Level 2 cache power off bitmap, low word */
111 #define L2_PWROFF_HI			0x1E4	/* (WO) Level 2 cache power off bitmap, high word */
112 
113 #define STACK_PWROFF_LO			0xE30   /* (RO) Core stack power off bitmap, low word */
114 #define STACK_PWROFF_HI			0xE34   /* (RO) Core stack power off bitmap, high word */
115 
116 
117 #define SHADER_PWRTRANS_LO		0x200	/* (RO) Shader core power transition bitmap, low word */
118 #define SHADER_PWRTRANS_HI		0x204	/* (RO) Shader core power transition bitmap, high word */
119 
120 #define TILER_PWRTRANS_LO		0x210	/* (RO) Tiler core power transition bitmap, low word */
121 #define TILER_PWRTRANS_HI		0x214	/* (RO) Tiler core power transition bitmap, high word */
122 
123 #define L2_PWRTRANS_LO			0x220	/* (RO) Level 2 cache power transition bitmap, low word */
124 #define L2_PWRTRANS_HI			0x224	/* (RO) Level 2 cache power transition bitmap, high word */
125 
126 #define STACK_PWRTRANS_LO		0xE40   /* (RO) Core stack power transition bitmap, low word */
127 #define STACK_PWRTRANS_HI		0xE44   /* (RO) Core stack power transition bitmap, high word */
128 
129 
130 #define SHADER_PWRACTIVE_LO		0x240	/* (RO) Shader core active bitmap, low word */
131 #define SHADER_PWRACTIVE_HI		0x244	/* (RO) Shader core active bitmap, high word */
132 
133 #define TILER_PWRACTIVE_LO		0x250	/* (RO) Tiler core active bitmap, low word */
134 #define TILER_PWRACTIVE_HI		0x254	/* (RO) Tiler core active bitmap, high word */
135 
136 #define L2_PWRACTIVE_LO			0x260	/* (RO) Level 2 cache active bitmap, low word */
137 #define L2_PWRACTIVE_HI			0x264	/* (RO) Level 2 cache active bitmap, high word */
138 
139 #define GPU_JM_CONFIG			0xF00   /* (RW) Job Manager configuration register (Implementation specific register) */
140 #define GPU_SHADER_CONFIG		0xF04	/* (RW) Shader core configuration settings (Implementation specific register) */
141 #define GPU_TILER_CONFIG		0xF08   /* (RW) Tiler core configuration settings (Implementation specific register) */
142 #define GPU_L2_MMU_CONFIG		0xF0C	/* (RW) Configuration of the L2 cache and MMU (Implementation specific register) */
143 
144 /* L2_MMU_CONFIG register */
145 #define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT	23
146 #define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY		(0x1 << L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT)
147 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT	24
148 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS		(0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
149 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_OCTANT	(0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
150 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_QUARTER	(0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
151 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_HALF		(0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
152 
153 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT	26
154 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES		(0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
155 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_OCTANT	(0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
156 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_QUARTER	(0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
157 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_HALF	(0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
158 
159 #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS_SHIFT	12
160 #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS		(0x7 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
161 
162 #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES_SHIFT	15
163 #define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES	(0x7 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
164 
165 /* SHADER_CONFIG register */
166 #define SC_ALT_COUNTERS			BIT(3)
167 #define SC_OVERRIDE_FWD_PIXEL_KILL	BIT(4)
168 #define SC_SDC_DISABLE_OQ_DISCARD	BIT(6)
169 #define SC_LS_ALLOW_ATTR_TYPES		BIT(16)
170 #define SC_LS_PAUSEBUFFER_DISABLE	BIT(16)
171 #define SC_TLS_HASH_ENABLE		BIT(17)
172 #define SC_LS_ATTR_CHECK_DISABLE	BIT(18)
173 #define SC_ENABLE_TEXGRD_FLAGS		BIT(25)
174 /* End SHADER_CONFIG register */
175 
176 /* TILER_CONFIG register */
177 #define TC_CLOCK_GATE_OVERRIDE		BIT(0)
178 
179 /* JM_CONFIG register */
180 #define JM_TIMESTAMP_OVERRIDE		BIT(0)
181 #define JM_CLOCK_GATE_OVERRIDE		BIT(1)
182 #define JM_JOB_THROTTLE_ENABLE		BIT(2)
183 #define JM_JOB_THROTTLE_LIMIT_SHIFT	3
184 #define JM_MAX_JOB_THROTTLE_LIMIT	0x3F
185 #define JM_FORCE_COHERENCY_FEATURES_SHIFT 2
186 #define JM_IDVS_GROUP_SIZE_SHIFT	16
187 #define JM_MAX_IDVS_GROUP_SIZE		0x3F
188 
189 
190 /* Job Control regs */
191 #define JOB_INT_RAWSTAT			0x1000
192 #define JOB_INT_CLEAR			0x1004
193 #define JOB_INT_MASK			0x1008
194 #define JOB_INT_STAT			0x100c
195 #define JOB_INT_JS_STATE		0x1010
196 #define JOB_INT_THROTTLE		0x1014
197 
198 #define MK_JS_MASK(j)			(0x10001 << (j))
199 #define JOB_INT_MASK_ERR(j)		BIT((j) + 16)
200 #define JOB_INT_MASK_DONE(j)		BIT(j)
201 
202 #define JS_BASE				0x1800
203 #define JS_HEAD_LO(n)			(JS_BASE + ((n) * 0x80) + 0x00)
204 #define JS_HEAD_HI(n)			(JS_BASE + ((n) * 0x80) + 0x04)
205 #define JS_TAIL_LO(n)			(JS_BASE + ((n) * 0x80) + 0x08)
206 #define JS_TAIL_HI(n)			(JS_BASE + ((n) * 0x80) + 0x0c)
207 #define JS_AFFINITY_LO(n)		(JS_BASE + ((n) * 0x80) + 0x10)
208 #define JS_AFFINITY_HI(n)		(JS_BASE + ((n) * 0x80) + 0x14)
209 #define JS_CONFIG(n)			(JS_BASE + ((n) * 0x80) + 0x18)
210 #define JS_XAFFINITY(n)			(JS_BASE + ((n) * 0x80) + 0x1c)
211 #define JS_COMMAND(n)			(JS_BASE + ((n) * 0x80) + 0x20)
212 #define JS_STATUS(n)			(JS_BASE + ((n) * 0x80) + 0x24)
213 #define JS_HEAD_NEXT_LO(n)		(JS_BASE + ((n) * 0x80) + 0x40)
214 #define JS_HEAD_NEXT_HI(n)		(JS_BASE + ((n) * 0x80) + 0x44)
215 #define JS_AFFINITY_NEXT_LO(n)		(JS_BASE + ((n) * 0x80) + 0x50)
216 #define JS_AFFINITY_NEXT_HI(n)		(JS_BASE + ((n) * 0x80) + 0x54)
217 #define JS_CONFIG_NEXT(n)		(JS_BASE + ((n) * 0x80) + 0x58)
218 #define JS_COMMAND_NEXT(n)		(JS_BASE + ((n) * 0x80) + 0x60)
219 #define JS_FLUSH_ID_NEXT(n)		(JS_BASE + ((n) * 0x80) + 0x70)
220 
221 /* Possible values of JS_CONFIG and JS_CONFIG_NEXT registers */
222 #define JS_CONFIG_START_FLUSH_CLEAN		BIT(8)
223 #define JS_CONFIG_START_FLUSH_CLEAN_INVALIDATE	(3u << 8)
224 #define JS_CONFIG_START_MMU			BIT(10)
225 #define JS_CONFIG_JOB_CHAIN_FLAG		BIT(11)
226 #define JS_CONFIG_END_FLUSH_CLEAN		BIT(12)
227 #define JS_CONFIG_END_FLUSH_CLEAN_INVALIDATE	(3u << 12)
228 #define JS_CONFIG_ENABLE_FLUSH_REDUCTION	BIT(14)
229 #define JS_CONFIG_DISABLE_DESCRIPTOR_WR_BK	BIT(15)
230 #define JS_CONFIG_THREAD_PRI(n)			((n) << 16)
231 
232 #define JS_COMMAND_NOP			0x00
233 #define JS_COMMAND_START		0x01
234 #define JS_COMMAND_SOFT_STOP		0x02	/* Gently stop processing a job chain */
235 #define JS_COMMAND_HARD_STOP		0x03	/* Rudely stop processing a job chain */
236 #define JS_COMMAND_SOFT_STOP_0		0x04	/* Execute SOFT_STOP if JOB_CHAIN_FLAG is 0 */
237 #define JS_COMMAND_HARD_STOP_0		0x05	/* Execute HARD_STOP if JOB_CHAIN_FLAG is 0 */
238 #define JS_COMMAND_SOFT_STOP_1		0x06	/* Execute SOFT_STOP if JOB_CHAIN_FLAG is 1 */
239 #define JS_COMMAND_HARD_STOP_1		0x07	/* Execute HARD_STOP if JOB_CHAIN_FLAG is 1 */
240 
241 #define JS_STATUS_EVENT_ACTIVE		0x08
242 
243 
244 /* MMU regs */
245 #define MMU_INT_RAWSTAT			0x2000
246 #define MMU_INT_CLEAR			0x2004
247 #define MMU_INT_MASK			0x2008
248 #define MMU_INT_STAT			0x200c
249 
250 /* AS_COMMAND register commands */
251 #define AS_COMMAND_NOP			0x00	/* NOP Operation */
252 #define AS_COMMAND_UPDATE		0x01	/* Broadcasts the values in AS_TRANSTAB and ASn_MEMATTR to all MMUs */
253 #define AS_COMMAND_LOCK			0x02	/* Issue a lock region command to all MMUs */
254 #define AS_COMMAND_UNLOCK		0x03	/* Issue a flush region command to all MMUs */
255 #define AS_COMMAND_FLUSH		0x04	/* Flush all L2 caches then issue a flush region command to all MMUs
256 						   (deprecated - only for use with T60x) */
257 #define AS_COMMAND_FLUSH_PT		0x04	/* Flush all L2 caches then issue a flush region command to all MMUs */
258 #define AS_COMMAND_FLUSH_MEM		0x05	/* Wait for memory accesses to complete, flush all the L1s cache then
259 						   flush all L2 caches then issue a flush region command to all MMUs */
260 
261 #define MMU_AS(as)			(0x2400 + ((as) << 6))
262 
263 #define AS_TRANSTAB_LO(as)		(MMU_AS(as) + 0x00) /* (RW) Translation Table Base Address for address space n, low word */
264 #define AS_TRANSTAB_HI(as)		(MMU_AS(as) + 0x04) /* (RW) Translation Table Base Address for address space n, high word */
265 #define AS_MEMATTR_LO(as)		(MMU_AS(as) + 0x08) /* (RW) Memory attributes for address space n, low word. */
266 #define AS_MEMATTR_HI(as)		(MMU_AS(as) + 0x0C) /* (RW) Memory attributes for address space n, high word. */
267 #define AS_LOCKADDR_LO(as)		(MMU_AS(as) + 0x10) /* (RW) Lock region address for address space n, low word */
268 #define AS_LOCKADDR_HI(as)		(MMU_AS(as) + 0x14) /* (RW) Lock region address for address space n, high word */
269 #define AS_COMMAND(as)			(MMU_AS(as) + 0x18) /* (WO) MMU command register for address space n */
270 #define AS_FAULTSTATUS(as)		(MMU_AS(as) + 0x1C) /* (RO) MMU fault status register for address space n */
271 #define AS_FAULTADDRESS_LO(as)		(MMU_AS(as) + 0x20) /* (RO) Fault Address for address space n, low word */
272 #define AS_FAULTADDRESS_HI(as)		(MMU_AS(as) + 0x24) /* (RO) Fault Address for address space n, high word */
273 #define AS_STATUS(as)			(MMU_AS(as) + 0x28) /* (RO) Status flags for address space n */
274 /* Additional Bifrost AS regsiters */
275 #define AS_TRANSCFG_LO(as)		(MMU_AS(as) + 0x30) /* (RW) Translation table configuration for address space n, low word */
276 #define AS_TRANSCFG_HI(as)		(MMU_AS(as) + 0x34) /* (RW) Translation table configuration for address space n, high word */
277 #define AS_FAULTEXTRA_LO(as)		(MMU_AS(as) + 0x38) /* (RO) Secondary fault address for address space n, low word */
278 #define AS_FAULTEXTRA_HI(as)		(MMU_AS(as) + 0x3C) /* (RO) Secondary fault address for address space n, high word */
279 
280 /*
281  * Begin LPAE MMU TRANSTAB register values
282  */
283 #define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK	0xfffffffffffff000
284 #define AS_TRANSTAB_LPAE_ADRMODE_IDENTITY	0x2
285 #define AS_TRANSTAB_LPAE_ADRMODE_TABLE		0x3
286 #define AS_TRANSTAB_LPAE_ADRMODE_MASK		0x3
287 #define AS_TRANSTAB_LPAE_READ_INNER		BIT(2)
288 #define AS_TRANSTAB_LPAE_SHARE_OUTER		BIT(4)
289 
290 #define AS_STATUS_AS_ACTIVE			0x01
291 
292 #define AS_FAULTSTATUS_ACCESS_TYPE_MASK		(0x3 << 8)
293 #define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC	(0x0 << 8)
294 #define AS_FAULTSTATUS_ACCESS_TYPE_EX		(0x1 << 8)
295 #define AS_FAULTSTATUS_ACCESS_TYPE_READ		(0x2 << 8)
296 #define AS_FAULTSTATUS_ACCESS_TYPE_WRITE	(0x3 << 8)
297 
298 #endif
299