1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */ 3 /* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */ 4 /* Copyright 2019 Collabora ltd. */ 5 #include <linux/bitfield.h> 6 #include <linux/bitmap.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 15 #include "panfrost_device.h" 16 #include "panfrost_features.h" 17 #include "panfrost_issues.h" 18 #include "panfrost_gpu.h" 19 #include "panfrost_perfcnt.h" 20 #include "panfrost_regs.h" 21 22 static irqreturn_t panfrost_gpu_irq_handler(int irq, void *data) 23 { 24 struct panfrost_device *pfdev = data; 25 u32 state = gpu_read(pfdev, GPU_INT_STAT); 26 u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS); 27 28 if (!state) 29 return IRQ_NONE; 30 31 if (state & GPU_IRQ_MASK_ERROR) { 32 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32; 33 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO); 34 35 dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n", 36 fault_status, panfrost_exception_name(fault_status & 0xFF), 37 address); 38 39 if (state & GPU_IRQ_MULTIPLE_FAULT) 40 dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n"); 41 42 gpu_write(pfdev, GPU_INT_MASK, 0); 43 } 44 45 if (state & GPU_IRQ_PERFCNT_SAMPLE_COMPLETED) 46 panfrost_perfcnt_sample_done(pfdev); 47 48 if (state & GPU_IRQ_CLEAN_CACHES_COMPLETED) 49 panfrost_perfcnt_clean_cache_done(pfdev); 50 51 gpu_write(pfdev, GPU_INT_CLEAR, state); 52 53 return IRQ_HANDLED; 54 } 55 56 int panfrost_gpu_soft_reset(struct panfrost_device *pfdev) 57 { 58 int ret; 59 u32 val; 60 61 gpu_write(pfdev, GPU_INT_MASK, 0); 62 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); 63 64 gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); 65 ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, 66 val, val & GPU_IRQ_RESET_COMPLETED, 10, 10000); 67 68 if (ret) { 69 dev_err(pfdev->dev, "gpu soft reset timed out, attempting hard reset\n"); 70 71 gpu_write(pfdev, GPU_CMD, GPU_CMD_HARD_RESET); 72 ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, val, 73 val & GPU_IRQ_RESET_COMPLETED, 100, 10000); 74 if (ret) { 75 dev_err(pfdev->dev, "gpu hard reset timed out\n"); 76 return ret; 77 } 78 } 79 80 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL); 81 gpu_write(pfdev, GPU_INT_MASK, GPU_IRQ_MASK_ALL); 82 83 /* 84 * All in-flight jobs should have released their cycle 85 * counter references upon reset, but let us make sure 86 */ 87 if (drm_WARN_ON(pfdev->ddev, atomic_read(&pfdev->cycle_counter.use_count) != 0)) 88 atomic_set(&pfdev->cycle_counter.use_count, 0); 89 90 return 0; 91 } 92 93 void panfrost_gpu_amlogic_quirk(struct panfrost_device *pfdev) 94 { 95 /* 96 * The Amlogic integrated Mali-T820, Mali-G31 & Mali-G52 needs 97 * these undocumented bits in GPU_PWR_OVERRIDE1 to be set in order 98 * to operate correctly. 99 */ 100 gpu_write(pfdev, GPU_PWR_KEY, GPU_PWR_KEY_UNLOCK); 101 gpu_write(pfdev, GPU_PWR_OVERRIDE1, 0xfff | (0x20 << 16)); 102 } 103 104 static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev) 105 { 106 u32 quirks = 0; 107 108 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_8443) || 109 panfrost_has_hw_issue(pfdev, HW_ISSUE_11035)) 110 quirks |= SC_LS_PAUSEBUFFER_DISABLE; 111 112 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10327)) 113 quirks |= SC_SDC_DISABLE_OQ_DISCARD; 114 115 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_10797)) 116 quirks |= SC_ENABLE_TEXGRD_FLAGS; 117 118 if (!panfrost_has_hw_issue(pfdev, GPUCORE_1619)) { 119 if (panfrost_model_cmp(pfdev, 0x750) < 0) /* T60x, T62x, T72x */ 120 quirks |= SC_LS_ATTR_CHECK_DISABLE; 121 else if (panfrost_model_cmp(pfdev, 0x880) <= 0) /* T76x, T8xx */ 122 quirks |= SC_LS_ALLOW_ATTR_TYPES; 123 } 124 125 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_TTRX_2968_TTRX_3162)) 126 quirks |= SC_VAR_ALGORITHM; 127 128 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_TLS_HASHING)) 129 quirks |= SC_TLS_HASH_ENABLE; 130 131 if (quirks) 132 gpu_write(pfdev, GPU_SHADER_CONFIG, quirks); 133 134 135 quirks = gpu_read(pfdev, GPU_TILER_CONFIG); 136 137 /* Set tiler clock gate override if required */ 138 if (panfrost_has_hw_issue(pfdev, HW_ISSUE_T76X_3953)) 139 quirks |= TC_CLOCK_GATE_OVERRIDE; 140 141 gpu_write(pfdev, GPU_TILER_CONFIG, quirks); 142 143 144 quirks = 0; 145 if ((panfrost_model_eq(pfdev, 0x860) || panfrost_model_eq(pfdev, 0x880)) && 146 pfdev->features.revision >= 0x2000) 147 quirks |= JM_MAX_JOB_THROTTLE_LIMIT << JM_JOB_THROTTLE_LIMIT_SHIFT; 148 else if (panfrost_model_eq(pfdev, 0x6000) && 149 pfdev->features.coherency_features == COHERENCY_ACE) 150 quirks |= (COHERENCY_ACE_LITE | COHERENCY_ACE) << 151 JM_FORCE_COHERENCY_FEATURES_SHIFT; 152 153 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_IDVS_GROUP_SIZE)) 154 quirks |= JM_DEFAULT_IDVS_GROUP_SIZE << JM_IDVS_GROUP_SIZE_SHIFT; 155 156 if (quirks) 157 gpu_write(pfdev, GPU_JM_CONFIG, quirks); 158 159 /* Here goes platform specific quirks */ 160 if (pfdev->comp->vendor_quirk) 161 pfdev->comp->vendor_quirk(pfdev); 162 } 163 164 #define MAX_HW_REVS 6 165 166 struct panfrost_model { 167 const char *name; 168 u32 id; 169 u32 id_mask; 170 u64 features; 171 u64 issues; 172 struct { 173 u32 revision; 174 u64 issues; 175 } revs[MAX_HW_REVS]; 176 }; 177 178 #define GPU_MODEL(_name, _id, ...) \ 179 {\ 180 .name = __stringify(_name), \ 181 .id = _id, \ 182 .features = hw_features_##_name, \ 183 .issues = hw_issues_##_name, \ 184 .revs = { __VA_ARGS__ }, \ 185 } 186 187 #define GPU_REV_EXT(name, _rev, _p, _s, stat) \ 188 {\ 189 .revision = (_rev) << 12 | (_p) << 4 | (_s), \ 190 .issues = hw_issues_##name##_r##_rev##p##_p##stat, \ 191 } 192 #define GPU_REV(name, r, p) GPU_REV_EXT(name, r, p, 0, ) 193 194 static const struct panfrost_model gpu_models[] = { 195 /* T60x has an oddball version */ 196 GPU_MODEL(t600, 0x600, 197 GPU_REV_EXT(t600, 0, 0, 1, _15dev0)), 198 GPU_MODEL(t620, 0x620, 199 GPU_REV(t620, 0, 1), GPU_REV(t620, 1, 0)), 200 GPU_MODEL(t720, 0x720), 201 GPU_MODEL(t760, 0x750, 202 GPU_REV(t760, 0, 0), GPU_REV(t760, 0, 1), 203 GPU_REV_EXT(t760, 0, 1, 0, _50rel0), 204 GPU_REV(t760, 0, 2), GPU_REV(t760, 0, 3)), 205 GPU_MODEL(t820, 0x820), 206 GPU_MODEL(t830, 0x830), 207 GPU_MODEL(t860, 0x860), 208 GPU_MODEL(t880, 0x880), 209 210 GPU_MODEL(g71, 0x6000, 211 GPU_REV_EXT(g71, 0, 0, 1, _05dev0)), 212 GPU_MODEL(g72, 0x6001), 213 GPU_MODEL(g51, 0x7000), 214 GPU_MODEL(g76, 0x7001), 215 GPU_MODEL(g52, 0x7002), 216 GPU_MODEL(g31, 0x7003, 217 GPU_REV(g31, 1, 0)), 218 219 GPU_MODEL(g57, 0x9001, 220 GPU_REV(g57, 0, 0)), 221 222 /* MediaTek MT8192 has a Mali-G57 with a different GPU ID from the 223 * standard. Arm's driver does not appear to handle this model. 224 * ChromeOS has a hack downstream for it. Treat it as equivalent to 225 * standard Mali-G57 for now. 226 */ 227 GPU_MODEL(g57, 0x9003, 228 GPU_REV(g57, 0, 0)), 229 }; 230 231 static void panfrost_gpu_init_features(struct panfrost_device *pfdev) 232 { 233 u32 gpu_id, num_js, major, minor, status, rev; 234 const char *name = "unknown"; 235 u64 hw_feat = 0; 236 u64 hw_issues = hw_issues_all; 237 const struct panfrost_model *model; 238 int i; 239 240 pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES); 241 pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES); 242 pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES); 243 pfdev->features.mem_features = gpu_read(pfdev, GPU_MEM_FEATURES); 244 pfdev->features.mmu_features = gpu_read(pfdev, GPU_MMU_FEATURES); 245 pfdev->features.thread_features = gpu_read(pfdev, GPU_THREAD_FEATURES); 246 pfdev->features.max_threads = gpu_read(pfdev, GPU_THREAD_MAX_THREADS); 247 pfdev->features.thread_max_workgroup_sz = gpu_read(pfdev, GPU_THREAD_MAX_WORKGROUP_SIZE); 248 pfdev->features.thread_max_barrier_sz = gpu_read(pfdev, GPU_THREAD_MAX_BARRIER_SIZE); 249 pfdev->features.coherency_features = gpu_read(pfdev, GPU_COHERENCY_FEATURES); 250 pfdev->features.afbc_features = gpu_read(pfdev, GPU_AFBC_FEATURES); 251 for (i = 0; i < 4; i++) 252 pfdev->features.texture_features[i] = gpu_read(pfdev, GPU_TEXTURE_FEATURES(i)); 253 254 pfdev->features.as_present = gpu_read(pfdev, GPU_AS_PRESENT); 255 256 pfdev->features.js_present = gpu_read(pfdev, GPU_JS_PRESENT); 257 num_js = hweight32(pfdev->features.js_present); 258 for (i = 0; i < num_js; i++) 259 pfdev->features.js_features[i] = gpu_read(pfdev, GPU_JS_FEATURES(i)); 260 261 pfdev->features.shader_present = gpu_read(pfdev, GPU_SHADER_PRESENT_LO); 262 pfdev->features.shader_present |= (u64)gpu_read(pfdev, GPU_SHADER_PRESENT_HI) << 32; 263 264 pfdev->features.tiler_present = gpu_read(pfdev, GPU_TILER_PRESENT_LO); 265 pfdev->features.tiler_present |= (u64)gpu_read(pfdev, GPU_TILER_PRESENT_HI) << 32; 266 267 pfdev->features.l2_present = gpu_read(pfdev, GPU_L2_PRESENT_LO); 268 pfdev->features.l2_present |= (u64)gpu_read(pfdev, GPU_L2_PRESENT_HI) << 32; 269 pfdev->features.nr_core_groups = hweight64(pfdev->features.l2_present); 270 271 pfdev->features.stack_present = gpu_read(pfdev, GPU_STACK_PRESENT_LO); 272 pfdev->features.stack_present |= (u64)gpu_read(pfdev, GPU_STACK_PRESENT_HI) << 32; 273 274 pfdev->features.thread_tls_alloc = gpu_read(pfdev, GPU_THREAD_TLS_ALLOC); 275 276 gpu_id = gpu_read(pfdev, GPU_ID); 277 pfdev->features.revision = gpu_id & 0xffff; 278 pfdev->features.id = gpu_id >> 16; 279 280 /* The T60x has an oddball ID value. Fix it up to the standard Midgard 281 * format so we (and userspace) don't have to special case it. 282 */ 283 if (pfdev->features.id == 0x6956) 284 pfdev->features.id = 0x0600; 285 286 major = (pfdev->features.revision >> 12) & 0xf; 287 minor = (pfdev->features.revision >> 4) & 0xff; 288 status = pfdev->features.revision & 0xf; 289 rev = pfdev->features.revision; 290 291 gpu_id = pfdev->features.id; 292 293 for (model = gpu_models; model->name; model++) { 294 int best = -1; 295 296 if (!panfrost_model_eq(pfdev, model->id)) 297 continue; 298 299 name = model->name; 300 hw_feat = model->features; 301 hw_issues |= model->issues; 302 for (i = 0; i < MAX_HW_REVS; i++) { 303 if (model->revs[i].revision == rev) { 304 best = i; 305 break; 306 } else if (model->revs[i].revision == (rev & ~0xf)) 307 best = i; 308 } 309 310 if (best >= 0) 311 hw_issues |= model->revs[best].issues; 312 313 break; 314 } 315 316 bitmap_from_u64(pfdev->features.hw_features, hw_feat); 317 bitmap_from_u64(pfdev->features.hw_issues, hw_issues); 318 319 dev_info(pfdev->dev, "mali-%s id 0x%x major 0x%x minor 0x%x status 0x%x", 320 name, gpu_id, major, minor, status); 321 dev_info(pfdev->dev, "features: %64pb, issues: %64pb", 322 pfdev->features.hw_features, 323 pfdev->features.hw_issues); 324 325 dev_info(pfdev->dev, "Features: L2:0x%08x Shader:0x%08x Tiler:0x%08x Mem:0x%0x MMU:0x%08x AS:0x%x JS:0x%x", 326 pfdev->features.l2_features, 327 pfdev->features.core_features, 328 pfdev->features.tiler_features, 329 pfdev->features.mem_features, 330 pfdev->features.mmu_features, 331 pfdev->features.as_present, 332 pfdev->features.js_present); 333 334 dev_info(pfdev->dev, "shader_present=0x%0llx l2_present=0x%0llx", 335 pfdev->features.shader_present, pfdev->features.l2_present); 336 } 337 338 void panfrost_cycle_counter_get(struct panfrost_device *pfdev) 339 { 340 if (atomic_inc_not_zero(&pfdev->cycle_counter.use_count)) 341 return; 342 343 spin_lock(&pfdev->cycle_counter.lock); 344 if (atomic_inc_return(&pfdev->cycle_counter.use_count) == 1) 345 gpu_write(pfdev, GPU_CMD, GPU_CMD_CYCLE_COUNT_START); 346 spin_unlock(&pfdev->cycle_counter.lock); 347 } 348 349 void panfrost_cycle_counter_put(struct panfrost_device *pfdev) 350 { 351 if (atomic_add_unless(&pfdev->cycle_counter.use_count, -1, 1)) 352 return; 353 354 spin_lock(&pfdev->cycle_counter.lock); 355 if (atomic_dec_return(&pfdev->cycle_counter.use_count) == 0) 356 gpu_write(pfdev, GPU_CMD, GPU_CMD_CYCLE_COUNT_STOP); 357 spin_unlock(&pfdev->cycle_counter.lock); 358 } 359 360 unsigned long long panfrost_cycle_counter_read(struct panfrost_device *pfdev) 361 { 362 u32 hi, lo; 363 364 do { 365 hi = gpu_read(pfdev, GPU_CYCLE_COUNT_HI); 366 lo = gpu_read(pfdev, GPU_CYCLE_COUNT_LO); 367 } while (hi != gpu_read(pfdev, GPU_CYCLE_COUNT_HI)); 368 369 return ((u64)hi << 32) | lo; 370 } 371 372 static u64 panfrost_get_core_mask(struct panfrost_device *pfdev) 373 { 374 u64 core_mask; 375 376 if (pfdev->features.l2_present == 1) 377 return U64_MAX; 378 379 /* 380 * Only support one core group now. 381 * ~(l2_present - 1) unsets all bits in l2_present except 382 * the bottom bit. (l2_present - 2) has all the bits in 383 * the first core group set. AND them together to generate 384 * a mask of cores in the first core group. 385 */ 386 core_mask = ~(pfdev->features.l2_present - 1) & 387 (pfdev->features.l2_present - 2); 388 dev_info_once(pfdev->dev, "using only 1st core group (%lu cores from %lu)\n", 389 hweight64(core_mask), 390 hweight64(pfdev->features.shader_present)); 391 392 return core_mask; 393 } 394 395 void panfrost_gpu_power_on(struct panfrost_device *pfdev) 396 { 397 int ret; 398 u32 val; 399 u64 core_mask; 400 401 panfrost_gpu_init_quirks(pfdev); 402 core_mask = panfrost_get_core_mask(pfdev); 403 404 gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present & core_mask); 405 ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO, 406 val, val == (pfdev->features.l2_present & core_mask), 407 10, 20000); 408 if (ret) 409 dev_err(pfdev->dev, "error powering up gpu L2"); 410 411 gpu_write(pfdev, SHADER_PWRON_LO, 412 pfdev->features.shader_present & core_mask); 413 ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO, 414 val, val == (pfdev->features.shader_present & core_mask), 415 10, 20000); 416 if (ret) 417 dev_err(pfdev->dev, "error powering up gpu shader"); 418 419 gpu_write(pfdev, TILER_PWRON_LO, pfdev->features.tiler_present); 420 ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO, 421 val, val == pfdev->features.tiler_present, 10, 1000); 422 if (ret) 423 dev_err(pfdev->dev, "error powering up gpu tiler"); 424 } 425 426 void panfrost_gpu_power_off(struct panfrost_device *pfdev) 427 { 428 u64 core_mask = panfrost_get_core_mask(pfdev); 429 int ret; 430 u32 val; 431 432 gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present & core_mask); 433 ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_PWRTRANS_LO, 434 val, !val, 1, 1000); 435 if (ret) 436 dev_err(pfdev->dev, "shader power transition timeout"); 437 438 gpu_write(pfdev, TILER_PWROFF_LO, pfdev->features.tiler_present); 439 ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_PWRTRANS_LO, 440 val, !val, 1, 1000); 441 if (ret) 442 dev_err(pfdev->dev, "tiler power transition timeout"); 443 444 gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present & core_mask); 445 ret = readl_poll_timeout(pfdev->iomem + L2_PWRTRANS_LO, 446 val, !val, 0, 1000); 447 if (ret) 448 dev_err(pfdev->dev, "l2 power transition timeout"); 449 } 450 451 int panfrost_gpu_init(struct panfrost_device *pfdev) 452 { 453 int err, irq; 454 455 err = panfrost_gpu_soft_reset(pfdev); 456 if (err) 457 return err; 458 459 panfrost_gpu_init_features(pfdev); 460 461 err = dma_set_mask_and_coherent(pfdev->dev, 462 DMA_BIT_MASK(FIELD_GET(0xff00, pfdev->features.mmu_features))); 463 if (err) 464 return err; 465 466 dma_set_max_seg_size(pfdev->dev, UINT_MAX); 467 468 irq = platform_get_irq_byname(to_platform_device(pfdev->dev), "gpu"); 469 if (irq < 0) 470 return irq; 471 472 err = devm_request_irq(pfdev->dev, irq, panfrost_gpu_irq_handler, 473 IRQF_SHARED, KBUILD_MODNAME "-gpu", pfdev); 474 if (err) { 475 dev_err(pfdev->dev, "failed to request gpu irq"); 476 return err; 477 } 478 479 panfrost_gpu_power_on(pfdev); 480 481 return 0; 482 } 483 484 void panfrost_gpu_fini(struct panfrost_device *pfdev) 485 { 486 panfrost_gpu_power_off(pfdev); 487 } 488 489 u32 panfrost_gpu_get_latest_flush_id(struct panfrost_device *pfdev) 490 { 491 u32 flush_id; 492 493 if (panfrost_has_hw_feature(pfdev, HW_FEATURE_FLUSH_REDUCTION)) { 494 /* Flush reduction only makes sense when the GPU is kept powered on between jobs */ 495 if (pm_runtime_get_if_in_use(pfdev->dev)) { 496 flush_id = gpu_read(pfdev, GPU_LATEST_FLUSH_ID); 497 pm_runtime_put(pfdev->dev); 498 return flush_id; 499 } 500 } 501 502 return 0; 503 } 504