1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */ 3 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */ 4 5 #ifndef __PANFROST_DEVICE_H__ 6 #define __PANFROST_DEVICE_H__ 7 8 #include <linux/atomic.h> 9 #include <linux/io-pgtable.h> 10 #include <linux/pm.h> 11 #include <linux/regulator/consumer.h> 12 #include <linux/spinlock.h> 13 #include <drm/drm_auth.h> 14 #include <drm/drm_device.h> 15 #include <drm/drm_mm.h> 16 #include <drm/gpu_scheduler.h> 17 18 #include "panfrost_devfreq.h" 19 #include "panfrost_job.h" 20 21 struct panfrost_device; 22 struct panfrost_mmu; 23 struct panfrost_job_slot; 24 struct panfrost_job; 25 struct panfrost_perfcnt; 26 27 #define MAX_PM_DOMAINS 5 28 29 #define ALL_JS_INT_MASK \ 30 (GENMASK(16 + NUM_JOB_SLOTS - 1, 16) | \ 31 GENMASK(NUM_JOB_SLOTS - 1, 0)) 32 33 enum panfrost_drv_comp_bits { 34 PANFROST_COMP_BIT_GPU, 35 PANFROST_COMP_BIT_JOB, 36 PANFROST_COMP_BIT_MMU, 37 PANFROST_COMP_BIT_MAX 38 }; 39 40 /** 41 * enum panfrost_gpu_pm - Supported kernel power management features 42 * @GPU_PM_CLK_DIS: Allow disabling clocks during system suspend 43 * @GPU_PM_VREG_OFF: Allow turning off regulators during system suspend 44 * @GPU_PM_RT: Allow disabling clocks and asserting the reset control during 45 * system runtime suspend 46 */ 47 enum panfrost_gpu_pm { 48 GPU_PM_CLK_DIS, 49 GPU_PM_VREG_OFF, 50 GPU_PM_RT 51 }; 52 53 /** 54 * enum panfrost_gpu_quirks - GPU optional quirks 55 * @GPU_QUIRK_FORCE_AARCH64_PGTABLE: Use AARCH64_4K page table format 56 */ 57 enum panfrost_gpu_quirks { 58 GPU_QUIRK_FORCE_AARCH64_PGTABLE, 59 }; 60 61 struct panfrost_features { 62 u16 id; 63 u16 revision; 64 65 u64 shader_present; 66 u64 tiler_present; 67 u64 l2_present; 68 u64 stack_present; 69 u32 as_present; 70 u32 js_present; 71 72 u32 l2_features; 73 u32 core_features; 74 u32 tiler_features; 75 u32 mem_features; 76 u32 mmu_features; 77 u32 thread_features; 78 u32 max_threads; 79 u32 thread_max_workgroup_sz; 80 u32 thread_max_barrier_sz; 81 u32 coherency_features; 82 u32 selected_coherency; 83 u32 afbc_features; 84 u32 texture_features[4]; 85 u32 js_features[16]; 86 87 u32 nr_core_groups; 88 u32 thread_tls_alloc; 89 90 unsigned long hw_features[64 / BITS_PER_LONG]; 91 unsigned long hw_issues[64 / BITS_PER_LONG]; 92 }; 93 94 /* 95 * Features that cannot be automatically detected and need matching using the 96 * compatible string, typically SoC-specific. 97 */ 98 struct panfrost_compatible { 99 /* Supplies count and names. */ 100 int num_supplies; 101 const char * const *supply_names; 102 /* 103 * Number of power domains required, note that values 0 and 1 are 104 * handled identically, as only values > 1 need special handling. 105 */ 106 int num_pm_domains; 107 /* Only required if num_pm_domains > 1. */ 108 const char * const *pm_domain_names; 109 110 /* Vendor implementation quirks callback */ 111 void (*vendor_quirk)(struct panfrost_device *pfdev); 112 113 /* Allowed PM features */ 114 u8 pm_features; 115 116 /* GPU configuration quirks */ 117 u8 gpu_quirks; 118 }; 119 120 /** 121 * struct panfrost_device_debugfs - Device-wide DebugFS tracking structures 122 */ 123 struct panfrost_device_debugfs { 124 /** @gems_list: Device-wide list of GEM objects owned by at least one file. */ 125 struct list_head gems_list; 126 127 /** @gems_lock: Serializes access to the device-wide list of GEM objects. */ 128 struct mutex gems_lock; 129 }; 130 131 struct panfrost_device { 132 struct drm_device base; 133 int gpu_irq; 134 int mmu_irq; 135 136 void __iomem *iomem; 137 struct clk *clock; 138 struct clk *bus_clock; 139 struct regulator_bulk_data *regulators; 140 struct reset_control *rstc; 141 /* pm_domains for devices with more than one. */ 142 struct device *pm_domain_devs[MAX_PM_DOMAINS]; 143 struct device_link *pm_domain_links[MAX_PM_DOMAINS]; 144 bool coherent; 145 146 struct panfrost_features features; 147 const struct panfrost_compatible *comp; 148 DECLARE_BITMAP(is_suspended, PANFROST_COMP_BIT_MAX); 149 150 spinlock_t as_lock; 151 unsigned long as_alloc_mask; 152 unsigned long as_faulty_mask; 153 struct list_head as_lru_list; 154 155 struct panfrost_job_slot *js; 156 157 struct panfrost_job *jobs[NUM_JOB_SLOTS][2]; 158 struct list_head scheduled_jobs; 159 160 struct panfrost_perfcnt *perfcnt; 161 bool profile_mode; 162 163 struct mutex sched_lock; 164 165 struct { 166 struct workqueue_struct *wq; 167 struct work_struct work; 168 atomic_t pending; 169 } reset; 170 171 struct mutex shrinker_lock; 172 struct list_head shrinker_list; 173 struct shrinker *shrinker; 174 175 struct panfrost_devfreq pfdevfreq; 176 177 struct { 178 atomic_t use_count; 179 spinlock_t lock; 180 } cycle_counter; 181 182 #ifdef CONFIG_DEBUG_FS 183 struct panfrost_device_debugfs debugfs; 184 #endif 185 }; 186 187 struct panfrost_mmu { 188 struct panfrost_device *pfdev; 189 struct kref refcount; 190 struct io_pgtable_cfg pgtbl_cfg; 191 struct io_pgtable_ops *pgtbl_ops; 192 struct drm_mm mm; 193 spinlock_t mm_lock; 194 int as; 195 atomic_t as_count; 196 struct list_head list; 197 struct { 198 u64 transtab; 199 u64 memattr; 200 u64 transcfg; 201 } cfg; 202 }; 203 204 struct panfrost_engine_usage { 205 unsigned long long elapsed_ns[NUM_JOB_SLOTS]; 206 unsigned long long cycles[NUM_JOB_SLOTS]; 207 }; 208 209 struct panfrost_file_priv { 210 struct panfrost_device *pfdev; 211 212 struct xarray jm_ctxs; 213 214 struct panfrost_mmu *mmu; 215 216 struct panfrost_engine_usage engine_usage; 217 }; 218 219 static inline bool panfrost_high_prio_allowed(struct drm_file *file) 220 { 221 /* Higher priorities require CAP_SYS_NICE or DRM_MASTER */ 222 return (capable(CAP_SYS_NICE) || drm_is_current_master(file)); 223 } 224 225 static inline struct panfrost_device *to_panfrost_device(struct drm_device *ddev) 226 { 227 return container_of(ddev, struct panfrost_device, base); 228 } 229 230 static inline int panfrost_model_cmp(struct panfrost_device *pfdev, s32 id) 231 { 232 s32 match_id = pfdev->features.id; 233 234 if (match_id & 0xf000) 235 match_id &= 0xf00f; 236 return match_id - id; 237 } 238 239 static inline bool panfrost_model_is_bifrost(struct panfrost_device *pfdev) 240 { 241 return panfrost_model_cmp(pfdev, 0x1000) >= 0; 242 } 243 244 static inline bool panfrost_model_eq(struct panfrost_device *pfdev, s32 id) 245 { 246 return !panfrost_model_cmp(pfdev, id); 247 } 248 249 int panfrost_unstable_ioctl_check(void); 250 251 int panfrost_device_init(struct panfrost_device *pfdev); 252 void panfrost_device_fini(struct panfrost_device *pfdev); 253 void panfrost_device_reset(struct panfrost_device *pfdev, bool enable_job_int); 254 255 extern const struct dev_pm_ops panfrost_pm_ops; 256 257 enum drm_panfrost_exception_type { 258 DRM_PANFROST_EXCEPTION_OK = 0x00, 259 DRM_PANFROST_EXCEPTION_DONE = 0x01, 260 DRM_PANFROST_EXCEPTION_INTERRUPTED = 0x02, 261 DRM_PANFROST_EXCEPTION_STOPPED = 0x03, 262 DRM_PANFROST_EXCEPTION_TERMINATED = 0x04, 263 DRM_PANFROST_EXCEPTION_KABOOM = 0x05, 264 DRM_PANFROST_EXCEPTION_EUREKA = 0x06, 265 DRM_PANFROST_EXCEPTION_ACTIVE = 0x08, 266 DRM_PANFROST_EXCEPTION_MAX_NON_FAULT = 0x3f, 267 DRM_PANFROST_EXCEPTION_JOB_CONFIG_FAULT = 0x40, 268 DRM_PANFROST_EXCEPTION_JOB_POWER_FAULT = 0x41, 269 DRM_PANFROST_EXCEPTION_JOB_READ_FAULT = 0x42, 270 DRM_PANFROST_EXCEPTION_JOB_WRITE_FAULT = 0x43, 271 DRM_PANFROST_EXCEPTION_JOB_AFFINITY_FAULT = 0x44, 272 DRM_PANFROST_EXCEPTION_JOB_BUS_FAULT = 0x48, 273 DRM_PANFROST_EXCEPTION_INSTR_INVALID_PC = 0x50, 274 DRM_PANFROST_EXCEPTION_INSTR_INVALID_ENC = 0x51, 275 DRM_PANFROST_EXCEPTION_INSTR_TYPE_MISMATCH = 0x52, 276 DRM_PANFROST_EXCEPTION_INSTR_OPERAND_FAULT = 0x53, 277 DRM_PANFROST_EXCEPTION_INSTR_TLS_FAULT = 0x54, 278 DRM_PANFROST_EXCEPTION_INSTR_BARRIER_FAULT = 0x55, 279 DRM_PANFROST_EXCEPTION_INSTR_ALIGN_FAULT = 0x56, 280 DRM_PANFROST_EXCEPTION_DATA_INVALID_FAULT = 0x58, 281 DRM_PANFROST_EXCEPTION_TILE_RANGE_FAULT = 0x59, 282 DRM_PANFROST_EXCEPTION_ADDR_RANGE_FAULT = 0x5a, 283 DRM_PANFROST_EXCEPTION_IMPRECISE_FAULT = 0x5b, 284 DRM_PANFROST_EXCEPTION_OOM = 0x60, 285 DRM_PANFROST_EXCEPTION_OOM_AFBC = 0x61, 286 DRM_PANFROST_EXCEPTION_UNKNOWN = 0x7f, 287 DRM_PANFROST_EXCEPTION_DELAYED_BUS_FAULT = 0x80, 288 DRM_PANFROST_EXCEPTION_GPU_SHAREABILITY_FAULT = 0x88, 289 DRM_PANFROST_EXCEPTION_SYS_SHAREABILITY_FAULT = 0x89, 290 DRM_PANFROST_EXCEPTION_GPU_CACHEABILITY_FAULT = 0x8a, 291 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_0 = 0xc0, 292 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_1 = 0xc1, 293 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_2 = 0xc2, 294 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_3 = 0xc3, 295 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_4 = 0xc4, 296 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_IDENTITY = 0xc7, 297 DRM_PANFROST_EXCEPTION_PERM_FAULT_0 = 0xc8, 298 DRM_PANFROST_EXCEPTION_PERM_FAULT_1 = 0xc9, 299 DRM_PANFROST_EXCEPTION_PERM_FAULT_2 = 0xca, 300 DRM_PANFROST_EXCEPTION_PERM_FAULT_3 = 0xcb, 301 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_0 = 0xd0, 302 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_1 = 0xd1, 303 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_2 = 0xd2, 304 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_3 = 0xd3, 305 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_0 = 0xd8, 306 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_1 = 0xd9, 307 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_2 = 0xda, 308 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_3 = 0xdb, 309 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN0 = 0xe0, 310 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN1 = 0xe1, 311 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN2 = 0xe2, 312 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN3 = 0xe3, 313 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT0 = 0xe4, 314 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT1 = 0xe5, 315 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT2 = 0xe6, 316 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT3 = 0xe7, 317 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_0 = 0xe8, 318 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_1 = 0xe9, 319 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_2 = 0xea, 320 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_3 = 0xeb, 321 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_0 = 0xec, 322 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_1 = 0xed, 323 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_2 = 0xee, 324 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_3 = 0xef, 325 }; 326 327 static inline bool 328 panfrost_exception_is_fault(u32 exception_code) 329 { 330 return exception_code > DRM_PANFROST_EXCEPTION_MAX_NON_FAULT; 331 } 332 333 const char *panfrost_exception_name(u32 exception_code); 334 bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev, 335 u32 exception_code); 336 337 static inline void 338 panfrost_device_schedule_reset(struct panfrost_device *pfdev) 339 { 340 atomic_set(&pfdev->reset.pending, 1); 341 queue_work(pfdev->reset.wq, &pfdev->reset.work); 342 } 343 344 #endif 345