1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */ 3 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */ 4 5 #ifndef __PANFROST_DEVICE_H__ 6 #define __PANFROST_DEVICE_H__ 7 8 #include <linux/atomic.h> 9 #include <linux/io-pgtable.h> 10 #include <linux/pm.h> 11 #include <linux/regulator/consumer.h> 12 #include <linux/spinlock.h> 13 #include <drm/drm_device.h> 14 #include <drm/drm_mm.h> 15 #include <drm/gpu_scheduler.h> 16 17 #include "panfrost_devfreq.h" 18 19 struct panfrost_device; 20 struct panfrost_mmu; 21 struct panfrost_job_slot; 22 struct panfrost_job; 23 struct panfrost_perfcnt; 24 25 #define NUM_JOB_SLOTS 3 26 #define MAX_PM_DOMAINS 5 27 28 /** 29 * enum panfrost_gpu_pm - Supported kernel power management features 30 * @GPU_PM_CLK_DIS: Allow disabling clocks during system suspend 31 * @GPU_PM_VREG_OFF: Allow turning off regulators during system suspend 32 */ 33 enum panfrost_gpu_pm { 34 GPU_PM_CLK_DIS, 35 GPU_PM_VREG_OFF, 36 }; 37 38 struct panfrost_features { 39 u16 id; 40 u16 revision; 41 42 u64 shader_present; 43 u64 tiler_present; 44 u64 l2_present; 45 u64 stack_present; 46 u32 as_present; 47 u32 js_present; 48 49 u32 l2_features; 50 u32 core_features; 51 u32 tiler_features; 52 u32 mem_features; 53 u32 mmu_features; 54 u32 thread_features; 55 u32 max_threads; 56 u32 thread_max_workgroup_sz; 57 u32 thread_max_barrier_sz; 58 u32 coherency_features; 59 u32 afbc_features; 60 u32 texture_features[4]; 61 u32 js_features[16]; 62 63 u32 nr_core_groups; 64 u32 thread_tls_alloc; 65 66 unsigned long hw_features[64 / BITS_PER_LONG]; 67 unsigned long hw_issues[64 / BITS_PER_LONG]; 68 }; 69 70 /* 71 * Features that cannot be automatically detected and need matching using the 72 * compatible string, typically SoC-specific. 73 */ 74 struct panfrost_compatible { 75 /* Supplies count and names. */ 76 int num_supplies; 77 const char * const *supply_names; 78 /* 79 * Number of power domains required, note that values 0 and 1 are 80 * handled identically, as only values > 1 need special handling. 81 */ 82 int num_pm_domains; 83 /* Only required if num_pm_domains > 1. */ 84 const char * const *pm_domain_names; 85 86 /* Vendor implementation quirks callback */ 87 void (*vendor_quirk)(struct panfrost_device *pfdev); 88 89 /* Allowed PM features */ 90 u8 pm_features; 91 }; 92 93 struct panfrost_device { 94 struct device *dev; 95 struct drm_device *ddev; 96 struct platform_device *pdev; 97 98 void __iomem *iomem; 99 struct clk *clock; 100 struct clk *bus_clock; 101 struct regulator_bulk_data *regulators; 102 struct reset_control *rstc; 103 /* pm_domains for devices with more than one. */ 104 struct device *pm_domain_devs[MAX_PM_DOMAINS]; 105 struct device_link *pm_domain_links[MAX_PM_DOMAINS]; 106 bool coherent; 107 108 struct panfrost_features features; 109 const struct panfrost_compatible *comp; 110 111 spinlock_t as_lock; 112 unsigned long as_in_use_mask; 113 unsigned long as_alloc_mask; 114 unsigned long as_faulty_mask; 115 struct list_head as_lru_list; 116 117 struct panfrost_job_slot *js; 118 119 struct panfrost_job *jobs[NUM_JOB_SLOTS][2]; 120 struct list_head scheduled_jobs; 121 122 struct panfrost_perfcnt *perfcnt; 123 atomic_t profile_mode; 124 125 struct mutex sched_lock; 126 127 struct { 128 struct workqueue_struct *wq; 129 struct work_struct work; 130 atomic_t pending; 131 } reset; 132 133 struct mutex shrinker_lock; 134 struct list_head shrinker_list; 135 struct shrinker *shrinker; 136 137 struct panfrost_devfreq pfdevfreq; 138 139 struct { 140 atomic_t use_count; 141 spinlock_t lock; 142 } cycle_counter; 143 }; 144 145 struct panfrost_mmu { 146 struct panfrost_device *pfdev; 147 struct kref refcount; 148 struct io_pgtable_cfg pgtbl_cfg; 149 struct io_pgtable_ops *pgtbl_ops; 150 struct drm_mm mm; 151 spinlock_t mm_lock; 152 int as; 153 atomic_t as_count; 154 struct list_head list; 155 }; 156 157 struct panfrost_engine_usage { 158 unsigned long long elapsed_ns[NUM_JOB_SLOTS]; 159 unsigned long long cycles[NUM_JOB_SLOTS]; 160 }; 161 162 struct panfrost_file_priv { 163 struct panfrost_device *pfdev; 164 165 struct drm_sched_entity sched_entity[NUM_JOB_SLOTS]; 166 167 struct panfrost_mmu *mmu; 168 169 struct panfrost_engine_usage engine_usage; 170 }; 171 172 static inline struct panfrost_device *to_panfrost_device(struct drm_device *ddev) 173 { 174 return ddev->dev_private; 175 } 176 177 static inline int panfrost_model_cmp(struct panfrost_device *pfdev, s32 id) 178 { 179 s32 match_id = pfdev->features.id; 180 181 if (match_id & 0xf000) 182 match_id &= 0xf00f; 183 return match_id - id; 184 } 185 186 static inline bool panfrost_model_is_bifrost(struct panfrost_device *pfdev) 187 { 188 return panfrost_model_cmp(pfdev, 0x1000) >= 0; 189 } 190 191 static inline bool panfrost_model_eq(struct panfrost_device *pfdev, s32 id) 192 { 193 return !panfrost_model_cmp(pfdev, id); 194 } 195 196 int panfrost_unstable_ioctl_check(void); 197 198 int panfrost_device_init(struct panfrost_device *pfdev); 199 void panfrost_device_fini(struct panfrost_device *pfdev); 200 void panfrost_device_reset(struct panfrost_device *pfdev); 201 202 extern const struct dev_pm_ops panfrost_pm_ops; 203 204 enum drm_panfrost_exception_type { 205 DRM_PANFROST_EXCEPTION_OK = 0x00, 206 DRM_PANFROST_EXCEPTION_DONE = 0x01, 207 DRM_PANFROST_EXCEPTION_INTERRUPTED = 0x02, 208 DRM_PANFROST_EXCEPTION_STOPPED = 0x03, 209 DRM_PANFROST_EXCEPTION_TERMINATED = 0x04, 210 DRM_PANFROST_EXCEPTION_KABOOM = 0x05, 211 DRM_PANFROST_EXCEPTION_EUREKA = 0x06, 212 DRM_PANFROST_EXCEPTION_ACTIVE = 0x08, 213 DRM_PANFROST_EXCEPTION_MAX_NON_FAULT = 0x3f, 214 DRM_PANFROST_EXCEPTION_JOB_CONFIG_FAULT = 0x40, 215 DRM_PANFROST_EXCEPTION_JOB_POWER_FAULT = 0x41, 216 DRM_PANFROST_EXCEPTION_JOB_READ_FAULT = 0x42, 217 DRM_PANFROST_EXCEPTION_JOB_WRITE_FAULT = 0x43, 218 DRM_PANFROST_EXCEPTION_JOB_AFFINITY_FAULT = 0x44, 219 DRM_PANFROST_EXCEPTION_JOB_BUS_FAULT = 0x48, 220 DRM_PANFROST_EXCEPTION_INSTR_INVALID_PC = 0x50, 221 DRM_PANFROST_EXCEPTION_INSTR_INVALID_ENC = 0x51, 222 DRM_PANFROST_EXCEPTION_INSTR_TYPE_MISMATCH = 0x52, 223 DRM_PANFROST_EXCEPTION_INSTR_OPERAND_FAULT = 0x53, 224 DRM_PANFROST_EXCEPTION_INSTR_TLS_FAULT = 0x54, 225 DRM_PANFROST_EXCEPTION_INSTR_BARRIER_FAULT = 0x55, 226 DRM_PANFROST_EXCEPTION_INSTR_ALIGN_FAULT = 0x56, 227 DRM_PANFROST_EXCEPTION_DATA_INVALID_FAULT = 0x58, 228 DRM_PANFROST_EXCEPTION_TILE_RANGE_FAULT = 0x59, 229 DRM_PANFROST_EXCEPTION_ADDR_RANGE_FAULT = 0x5a, 230 DRM_PANFROST_EXCEPTION_IMPRECISE_FAULT = 0x5b, 231 DRM_PANFROST_EXCEPTION_OOM = 0x60, 232 DRM_PANFROST_EXCEPTION_OOM_AFBC = 0x61, 233 DRM_PANFROST_EXCEPTION_UNKNOWN = 0x7f, 234 DRM_PANFROST_EXCEPTION_DELAYED_BUS_FAULT = 0x80, 235 DRM_PANFROST_EXCEPTION_GPU_SHAREABILITY_FAULT = 0x88, 236 DRM_PANFROST_EXCEPTION_SYS_SHAREABILITY_FAULT = 0x89, 237 DRM_PANFROST_EXCEPTION_GPU_CACHEABILITY_FAULT = 0x8a, 238 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_0 = 0xc0, 239 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_1 = 0xc1, 240 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_2 = 0xc2, 241 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_3 = 0xc3, 242 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_4 = 0xc4, 243 DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_IDENTITY = 0xc7, 244 DRM_PANFROST_EXCEPTION_PERM_FAULT_0 = 0xc8, 245 DRM_PANFROST_EXCEPTION_PERM_FAULT_1 = 0xc9, 246 DRM_PANFROST_EXCEPTION_PERM_FAULT_2 = 0xca, 247 DRM_PANFROST_EXCEPTION_PERM_FAULT_3 = 0xcb, 248 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_0 = 0xd0, 249 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_1 = 0xd1, 250 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_2 = 0xd2, 251 DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_3 = 0xd3, 252 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_0 = 0xd8, 253 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_1 = 0xd9, 254 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_2 = 0xda, 255 DRM_PANFROST_EXCEPTION_ACCESS_FLAG_3 = 0xdb, 256 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN0 = 0xe0, 257 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN1 = 0xe1, 258 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN2 = 0xe2, 259 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN3 = 0xe3, 260 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT0 = 0xe4, 261 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT1 = 0xe5, 262 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT2 = 0xe6, 263 DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT3 = 0xe7, 264 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_0 = 0xe8, 265 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_1 = 0xe9, 266 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_2 = 0xea, 267 DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_3 = 0xeb, 268 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_0 = 0xec, 269 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_1 = 0xed, 270 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_2 = 0xee, 271 DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_3 = 0xef, 272 }; 273 274 static inline bool 275 panfrost_exception_is_fault(u32 exception_code) 276 { 277 return exception_code > DRM_PANFROST_EXCEPTION_MAX_NON_FAULT; 278 } 279 280 const char *panfrost_exception_name(u32 exception_code); 281 bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev, 282 u32 exception_code); 283 284 static inline void 285 panfrost_device_schedule_reset(struct panfrost_device *pfdev) 286 { 287 atomic_set(&pfdev->reset.pending, 1); 288 queue_work(pfdev->reset.wq, &pfdev->reset.work); 289 } 290 291 #endif 292