xref: /linux/drivers/gpu/drm/panfrost/panfrost_device.c (revision 570f7e331f5febb30f1384817463c7e42b65ca7d) 
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
3 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
4 
5 #include <linux/clk.h>
6 #include <linux/reset.h>
7 #include <linux/platform_device.h>
8 #include <linux/pm_domain.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/regulator/consumer.h>
11 
12 #include "panfrost_device.h"
13 #include "panfrost_devfreq.h"
14 #include "panfrost_features.h"
15 #include "panfrost_gem.h"
16 #include "panfrost_issues.h"
17 #include "panfrost_gpu.h"
18 #include "panfrost_job.h"
19 #include "panfrost_mmu.h"
20 #include "panfrost_perfcnt.h"
21 
22 static int panfrost_reset_init(struct panfrost_device *pfdev)
23 {
24 	pfdev->rstc = devm_reset_control_array_get_optional_exclusive(pfdev->base.dev);
25 	if (IS_ERR(pfdev->rstc)) {
26 		dev_err(pfdev->base.dev, "get reset failed %ld\n", PTR_ERR(pfdev->rstc));
27 		return PTR_ERR(pfdev->rstc);
28 	}
29 
30 	return reset_control_deassert(pfdev->rstc);
31 }
32 
33 static void panfrost_reset_fini(struct panfrost_device *pfdev)
34 {
35 	reset_control_assert(pfdev->rstc);
36 }
37 
38 static int panfrost_clk_init(struct panfrost_device *pfdev)
39 {
40 	int err;
41 	unsigned long rate;
42 
43 	pfdev->clock = devm_clk_get(pfdev->base.dev, NULL);
44 	if (IS_ERR(pfdev->clock)) {
45 		dev_err(pfdev->base.dev, "get clock failed %ld\n", PTR_ERR(pfdev->clock));
46 		return PTR_ERR(pfdev->clock);
47 	}
48 
49 	rate = clk_get_rate(pfdev->clock);
50 	dev_info(pfdev->base.dev, "clock rate = %lu\n", rate);
51 
52 	err = clk_prepare_enable(pfdev->clock);
53 	if (err)
54 		return err;
55 
56 	pfdev->bus_clock = devm_clk_get_optional(pfdev->base.dev, "bus");
57 	if (IS_ERR(pfdev->bus_clock)) {
58 		dev_err(pfdev->base.dev, "get bus_clock failed %ld\n",
59 			PTR_ERR(pfdev->bus_clock));
60 		err = PTR_ERR(pfdev->bus_clock);
61 		goto disable_clock;
62 	}
63 
64 	if (pfdev->bus_clock) {
65 		rate = clk_get_rate(pfdev->bus_clock);
66 		dev_info(pfdev->base.dev, "bus_clock rate = %lu\n", rate);
67 
68 		err = clk_prepare_enable(pfdev->bus_clock);
69 		if (err)
70 			goto disable_clock;
71 	}
72 
73 	pfdev->bus_ace_clock = devm_clk_get_optional(pfdev->base.dev, "bus_ace");
74 	if (IS_ERR(pfdev->bus_ace_clock)) {
75 		err = PTR_ERR(pfdev->bus_ace_clock);
76 		dev_err(pfdev->base.dev, "get bus_ace_clock failed %d\n", err);
77 		goto disable_bus_clock;
78 	}
79 
80 	err = clk_prepare_enable(pfdev->bus_ace_clock);
81 	if (err)
82 		goto disable_bus_clock;
83 
84 	return 0;
85 
86 disable_bus_clock:
87 	clk_disable_unprepare(pfdev->bus_clock);
88 disable_clock:
89 	clk_disable_unprepare(pfdev->clock);
90 
91 	return err;
92 }
93 
94 static void panfrost_clk_fini(struct panfrost_device *pfdev)
95 {
96 	clk_disable_unprepare(pfdev->bus_ace_clock);
97 	clk_disable_unprepare(pfdev->bus_clock);
98 	clk_disable_unprepare(pfdev->clock);
99 }
100 
101 static int panfrost_regulator_init(struct panfrost_device *pfdev)
102 {
103 	int ret, i;
104 
105 	pfdev->regulators = devm_kcalloc(pfdev->base.dev, pfdev->comp->num_supplies,
106 					 sizeof(*pfdev->regulators),
107 					 GFP_KERNEL);
108 	if (!pfdev->regulators)
109 		return -ENOMEM;
110 
111 	for (i = 0; i < pfdev->comp->num_supplies; i++)
112 		pfdev->regulators[i].supply = pfdev->comp->supply_names[i];
113 
114 	ret = devm_regulator_bulk_get(pfdev->base.dev,
115 				      pfdev->comp->num_supplies,
116 				      pfdev->regulators);
117 	if (ret < 0) {
118 		if (ret != -EPROBE_DEFER)
119 			dev_err(pfdev->base.dev, "failed to get regulators: %d\n",
120 				ret);
121 		return ret;
122 	}
123 
124 	ret = regulator_bulk_enable(pfdev->comp->num_supplies,
125 				    pfdev->regulators);
126 	if (ret < 0) {
127 		dev_err(pfdev->base.dev, "failed to enable regulators: %d\n", ret);
128 		return ret;
129 	}
130 
131 	return 0;
132 }
133 
134 static void panfrost_regulator_fini(struct panfrost_device *pfdev)
135 {
136 	if (!pfdev->regulators)
137 		return;
138 
139 	regulator_bulk_disable(pfdev->comp->num_supplies, pfdev->regulators);
140 }
141 
142 static void panfrost_pm_domain_fini(struct panfrost_device *pfdev)
143 {
144 	int i;
145 
146 	for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
147 		if (!pfdev->pm_domain_devs[i])
148 			break;
149 
150 		if (pfdev->pm_domain_links[i])
151 			device_link_del(pfdev->pm_domain_links[i]);
152 
153 		dev_pm_domain_detach(pfdev->pm_domain_devs[i], true);
154 	}
155 }
156 
157 static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
158 {
159 	int err;
160 	int i, num_domains;
161 
162 	num_domains = of_count_phandle_with_args(pfdev->base.dev->of_node,
163 						 "power-domains",
164 						 "#power-domain-cells");
165 
166 	/*
167 	 * Single domain is handled by the core, and, if only a single power
168 	 * the power domain is requested, the property is optional.
169 	 */
170 	if (num_domains < 2 && pfdev->comp->num_pm_domains < 2)
171 		return 0;
172 
173 	if (num_domains != pfdev->comp->num_pm_domains) {
174 		dev_err(pfdev->base.dev,
175 			"Incorrect number of power domains: %d provided, %d needed\n",
176 			num_domains, pfdev->comp->num_pm_domains);
177 		return -EINVAL;
178 	}
179 
180 	if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
181 			"Too many supplies in compatible structure.\n"))
182 		return -EINVAL;
183 
184 	for (i = 0; i < num_domains; i++) {
185 		pfdev->pm_domain_devs[i] =
186 			dev_pm_domain_attach_by_name(pfdev->base.dev,
187 						     pfdev->comp->pm_domain_names[i]);
188 		if (IS_ERR_OR_NULL(pfdev->pm_domain_devs[i])) {
189 			err = PTR_ERR(pfdev->pm_domain_devs[i]) ? : -ENODATA;
190 			pfdev->pm_domain_devs[i] = NULL;
191 			dev_err(pfdev->base.dev,
192 				"failed to get pm-domain %s(%d): %d\n",
193 				pfdev->comp->pm_domain_names[i], i, err);
194 			goto err;
195 		}
196 
197 		pfdev->pm_domain_links[i] =
198 			device_link_add(pfdev->base.dev,
199 					pfdev->pm_domain_devs[i], DL_FLAG_PM_RUNTIME |
200 					DL_FLAG_STATELESS | DL_FLAG_RPM_ACTIVE);
201 		if (!pfdev->pm_domain_links[i]) {
202 			dev_err(pfdev->pm_domain_devs[i],
203 				"adding device link failed!\n");
204 			err = -ENODEV;
205 			goto err;
206 		}
207 	}
208 
209 	return 0;
210 
211 err:
212 	panfrost_pm_domain_fini(pfdev);
213 	return err;
214 }
215 
216 int panfrost_device_init(struct panfrost_device *pfdev)
217 {
218 	int err;
219 
220 	mutex_init(&pfdev->sched_lock);
221 	INIT_LIST_HEAD(&pfdev->as_lru_list);
222 
223 	spin_lock_init(&pfdev->as_lock);
224 
225 	spin_lock_init(&pfdev->cycle_counter.lock);
226 
227 #ifdef CONFIG_DEBUG_FS
228 	mutex_init(&pfdev->debugfs.gems_lock);
229 	INIT_LIST_HEAD(&pfdev->debugfs.gems_list);
230 #endif
231 
232 	err = panfrost_pm_domain_init(pfdev);
233 	if (err)
234 		return err;
235 
236 	err = panfrost_reset_init(pfdev);
237 	if (err) {
238 		dev_err(pfdev->base.dev, "reset init failed %d\n", err);
239 		goto out_pm_domain;
240 	}
241 
242 	err = panfrost_clk_init(pfdev);
243 	if (err) {
244 		dev_err(pfdev->base.dev, "clk init failed %d\n", err);
245 		goto out_reset;
246 	}
247 
248 	err = panfrost_devfreq_init(pfdev);
249 	if (err) {
250 		if (err != -EPROBE_DEFER)
251 			dev_err(pfdev->base.dev, "devfreq init failed %d\n", err);
252 		goto out_clk;
253 	}
254 
255 	/* OPP will handle regulators */
256 	if (!pfdev->pfdevfreq.opp_of_table_added) {
257 		err = panfrost_regulator_init(pfdev);
258 		if (err)
259 			goto out_devfreq;
260 	}
261 
262 	pfdev->iomem = devm_platform_ioremap_resource(to_platform_device(pfdev->base.dev), 0);
263 	if (IS_ERR(pfdev->iomem)) {
264 		err = PTR_ERR(pfdev->iomem);
265 		goto out_regulator;
266 	}
267 
268 	err = panfrost_gpu_init(pfdev);
269 	if (err)
270 		goto out_regulator;
271 
272 	err = panfrost_mmu_init(pfdev);
273 	if (err)
274 		goto out_gpu;
275 
276 	err = panfrost_jm_init(pfdev);
277 	if (err)
278 		goto out_mmu;
279 
280 	err = panfrost_perfcnt_init(pfdev);
281 	if (err)
282 		goto out_job;
283 
284 	panfrost_gem_init(pfdev);
285 
286 	return 0;
287 out_job:
288 	panfrost_jm_fini(pfdev);
289 out_mmu:
290 	panfrost_mmu_fini(pfdev);
291 out_gpu:
292 	panfrost_gpu_fini(pfdev);
293 out_regulator:
294 	panfrost_regulator_fini(pfdev);
295 out_devfreq:
296 	panfrost_devfreq_fini(pfdev);
297 out_clk:
298 	panfrost_clk_fini(pfdev);
299 out_reset:
300 	panfrost_reset_fini(pfdev);
301 out_pm_domain:
302 	panfrost_pm_domain_fini(pfdev);
303 	return err;
304 }
305 
306 void panfrost_device_fini(struct panfrost_device *pfdev)
307 {
308 	panfrost_perfcnt_fini(pfdev);
309 	panfrost_jm_fini(pfdev);
310 	panfrost_mmu_fini(pfdev);
311 	panfrost_gpu_fini(pfdev);
312 	panfrost_devfreq_fini(pfdev);
313 	panfrost_regulator_fini(pfdev);
314 	panfrost_clk_fini(pfdev);
315 	panfrost_reset_fini(pfdev);
316 	panfrost_pm_domain_fini(pfdev);
317 }
318 
319 #define PANFROST_EXCEPTION(id) \
320 	[DRM_PANFROST_EXCEPTION_ ## id] = { \
321 		.name = #id, \
322 	}
323 
324 struct panfrost_exception_info {
325 	const char *name;
326 };
327 
328 static const struct panfrost_exception_info panfrost_exception_infos[] = {
329 	PANFROST_EXCEPTION(OK),
330 	PANFROST_EXCEPTION(DONE),
331 	PANFROST_EXCEPTION(INTERRUPTED),
332 	PANFROST_EXCEPTION(STOPPED),
333 	PANFROST_EXCEPTION(TERMINATED),
334 	PANFROST_EXCEPTION(KABOOM),
335 	PANFROST_EXCEPTION(EUREKA),
336 	PANFROST_EXCEPTION(ACTIVE),
337 	PANFROST_EXCEPTION(JOB_CONFIG_FAULT),
338 	PANFROST_EXCEPTION(JOB_POWER_FAULT),
339 	PANFROST_EXCEPTION(JOB_READ_FAULT),
340 	PANFROST_EXCEPTION(JOB_WRITE_FAULT),
341 	PANFROST_EXCEPTION(JOB_AFFINITY_FAULT),
342 	PANFROST_EXCEPTION(JOB_BUS_FAULT),
343 	PANFROST_EXCEPTION(INSTR_INVALID_PC),
344 	PANFROST_EXCEPTION(INSTR_INVALID_ENC),
345 	PANFROST_EXCEPTION(INSTR_TYPE_MISMATCH),
346 	PANFROST_EXCEPTION(INSTR_OPERAND_FAULT),
347 	PANFROST_EXCEPTION(INSTR_TLS_FAULT),
348 	PANFROST_EXCEPTION(INSTR_BARRIER_FAULT),
349 	PANFROST_EXCEPTION(INSTR_ALIGN_FAULT),
350 	PANFROST_EXCEPTION(DATA_INVALID_FAULT),
351 	PANFROST_EXCEPTION(TILE_RANGE_FAULT),
352 	PANFROST_EXCEPTION(ADDR_RANGE_FAULT),
353 	PANFROST_EXCEPTION(IMPRECISE_FAULT),
354 	PANFROST_EXCEPTION(OOM),
355 	PANFROST_EXCEPTION(OOM_AFBC),
356 	PANFROST_EXCEPTION(UNKNOWN),
357 	PANFROST_EXCEPTION(DELAYED_BUS_FAULT),
358 	PANFROST_EXCEPTION(GPU_SHAREABILITY_FAULT),
359 	PANFROST_EXCEPTION(SYS_SHAREABILITY_FAULT),
360 	PANFROST_EXCEPTION(GPU_CACHEABILITY_FAULT),
361 	PANFROST_EXCEPTION(TRANSLATION_FAULT_0),
362 	PANFROST_EXCEPTION(TRANSLATION_FAULT_1),
363 	PANFROST_EXCEPTION(TRANSLATION_FAULT_2),
364 	PANFROST_EXCEPTION(TRANSLATION_FAULT_3),
365 	PANFROST_EXCEPTION(TRANSLATION_FAULT_4),
366 	PANFROST_EXCEPTION(TRANSLATION_FAULT_IDENTITY),
367 	PANFROST_EXCEPTION(PERM_FAULT_0),
368 	PANFROST_EXCEPTION(PERM_FAULT_1),
369 	PANFROST_EXCEPTION(PERM_FAULT_2),
370 	PANFROST_EXCEPTION(PERM_FAULT_3),
371 	PANFROST_EXCEPTION(TRANSTAB_BUS_FAULT_0),
372 	PANFROST_EXCEPTION(TRANSTAB_BUS_FAULT_1),
373 	PANFROST_EXCEPTION(TRANSTAB_BUS_FAULT_2),
374 	PANFROST_EXCEPTION(TRANSTAB_BUS_FAULT_3),
375 	PANFROST_EXCEPTION(ACCESS_FLAG_0),
376 	PANFROST_EXCEPTION(ACCESS_FLAG_1),
377 	PANFROST_EXCEPTION(ACCESS_FLAG_2),
378 	PANFROST_EXCEPTION(ACCESS_FLAG_3),
379 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_IN0),
380 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_IN1),
381 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_IN2),
382 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_IN3),
383 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_OUT0),
384 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_OUT1),
385 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_OUT2),
386 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_OUT3),
387 	PANFROST_EXCEPTION(MEM_ATTR_FAULT_0),
388 	PANFROST_EXCEPTION(MEM_ATTR_FAULT_1),
389 	PANFROST_EXCEPTION(MEM_ATTR_FAULT_2),
390 	PANFROST_EXCEPTION(MEM_ATTR_FAULT_3),
391 	PANFROST_EXCEPTION(MEM_ATTR_NONCACHE_0),
392 	PANFROST_EXCEPTION(MEM_ATTR_NONCACHE_1),
393 	PANFROST_EXCEPTION(MEM_ATTR_NONCACHE_2),
394 	PANFROST_EXCEPTION(MEM_ATTR_NONCACHE_3),
395 };
396 
397 const char *panfrost_exception_name(u32 exception_code)
398 {
399 	if (WARN_ON(exception_code >= ARRAY_SIZE(panfrost_exception_infos) ||
400 		    !panfrost_exception_infos[exception_code].name))
401 		return "Unknown exception type";
402 
403 	return panfrost_exception_infos[exception_code].name;
404 }
405 
406 bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev,
407 				    u32 exception_code)
408 {
409 	/* If an occlusion query write causes a bus fault on affected GPUs,
410 	 * future fragment jobs may hang. Reset to workaround.
411 	 */
412 	if (exception_code == DRM_PANFROST_EXCEPTION_JOB_BUS_FAULT)
413 		return panfrost_has_hw_issue(pfdev, HW_ISSUE_TTRX_3076);
414 
415 	/* No other GPUs we support need a reset */
416 	return false;
417 }
418 
419 void panfrost_device_reset(struct panfrost_device *pfdev, bool enable_job_int)
420 {
421 	panfrost_gpu_soft_reset(pfdev);
422 
423 	panfrost_gpu_power_on(pfdev);
424 	panfrost_mmu_reset(pfdev);
425 
426 	panfrost_jm_reset_interrupts(pfdev);
427 	if (enable_job_int)
428 		panfrost_jm_enable_interrupts(pfdev);
429 }
430 
431 static int panfrost_device_runtime_resume(struct device *dev)
432 {
433 	struct panfrost_device *pfdev = dev_get_drvdata(dev);
434 	int ret;
435 
436 	if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) {
437 		ret = reset_control_deassert(pfdev->rstc);
438 		if (ret)
439 			return ret;
440 
441 		ret = clk_enable(pfdev->clock);
442 		if (ret)
443 			goto err_clk;
444 
445 		ret = clk_enable(pfdev->bus_clock);
446 		if (ret)
447 			goto err_bus_clk;
448 
449 		ret = clk_enable(pfdev->bus_ace_clock);
450 		if (ret)
451 			goto err_bus_ace_clk;
452 	}
453 
454 	panfrost_device_reset(pfdev, true);
455 	panfrost_devfreq_resume(pfdev);
456 
457 	return 0;
458 
459 err_bus_ace_clk:
460 	if (pfdev->comp->pm_features & BIT(GPU_PM_RT))
461 		clk_disable(pfdev->bus_clock);
462 err_bus_clk:
463 	if (pfdev->comp->pm_features & BIT(GPU_PM_RT))
464 		clk_disable(pfdev->clock);
465 err_clk:
466 	if (pfdev->comp->pm_features & BIT(GPU_PM_RT))
467 		reset_control_assert(pfdev->rstc);
468 	return ret;
469 }
470 
471 static int panfrost_device_runtime_suspend(struct device *dev)
472 {
473 	struct panfrost_device *pfdev = dev_get_drvdata(dev);
474 
475 	if (!panfrost_jm_is_idle(pfdev))
476 		return -EBUSY;
477 
478 	panfrost_devfreq_suspend(pfdev);
479 	panfrost_jm_suspend_irq(pfdev);
480 	panfrost_mmu_suspend_irq(pfdev);
481 	panfrost_gpu_suspend_irq(pfdev);
482 	panfrost_gpu_power_off(pfdev);
483 
484 	if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) {
485 		clk_disable(pfdev->bus_ace_clock);
486 		clk_disable(pfdev->bus_clock);
487 		clk_disable(pfdev->clock);
488 		reset_control_assert(pfdev->rstc);
489 	}
490 
491 	return 0;
492 }
493 
494 static int panfrost_device_resume(struct device *dev)
495 {
496 	struct panfrost_device *pfdev = dev_get_drvdata(dev);
497 	int ret;
498 
499 	if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF)) {
500 		unsigned long freq = pfdev->pfdevfreq.fast_rate;
501 		struct dev_pm_opp *opp;
502 
503 		opp = dev_pm_opp_find_freq_ceil(dev, &freq);
504 		if (IS_ERR(opp))
505 			return PTR_ERR(opp);
506 		dev_pm_opp_set_opp(dev, opp);
507 		dev_pm_opp_put(opp);
508 	}
509 
510 	if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) {
511 		ret = clk_enable(pfdev->clock);
512 		if (ret)
513 			goto err_clk;
514 
515 		if (pfdev->bus_clock) {
516 			ret = clk_enable(pfdev->bus_clock);
517 			if (ret)
518 				goto err_bus_clk;
519 		}
520 	}
521 
522 	ret = pm_runtime_force_resume(dev);
523 	if (ret)
524 		goto err_resume;
525 
526 	return 0;
527 
528 err_resume:
529 	if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS) && pfdev->bus_clock)
530 		clk_disable(pfdev->bus_clock);
531 err_bus_clk:
532 	if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS))
533 		clk_disable(pfdev->clock);
534 err_clk:
535 	if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF))
536 		dev_pm_opp_set_opp(dev, NULL);
537 	return ret;
538 }
539 
540 static int panfrost_device_suspend(struct device *dev)
541 {
542 	struct panfrost_device *pfdev = dev_get_drvdata(dev);
543 	int ret;
544 
545 	ret = pm_runtime_force_suspend(dev);
546 	if (ret)
547 		return ret;
548 
549 	if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) {
550 		if (pfdev->bus_clock)
551 			clk_disable(pfdev->bus_clock);
552 
553 		clk_disable(pfdev->clock);
554 	}
555 
556 	if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF))
557 		dev_pm_opp_set_opp(dev, NULL);
558 
559 	return 0;
560 }
561 
562 EXPORT_GPL_DEV_PM_OPS(panfrost_pm_ops) = {
563 	RUNTIME_PM_OPS(panfrost_device_runtime_suspend, panfrost_device_runtime_resume, NULL)
564 	SYSTEM_SLEEP_PM_OPS(panfrost_device_suspend, panfrost_device_resume)
565 };
566