xref: /linux/drivers/gpu/drm/panfrost/panfrost_device.c (revision 4b99990cdf9560e8a071640baf19f312e6ae02f4) 
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
3 /* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
4 
5 #include <linux/clk.h>
6 #include <linux/reset.h>
7 #include <linux/platform_device.h>
8 #include <linux/pm_domain.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/regulator/consumer.h>
11 
12 #include "panfrost_device.h"
13 #include "panfrost_devfreq.h"
14 #include "panfrost_features.h"
15 #include "panfrost_gem.h"
16 #include "panfrost_issues.h"
17 #include "panfrost_gpu.h"
18 #include "panfrost_job.h"
19 #include "panfrost_mmu.h"
20 #include "panfrost_perfcnt.h"
21 
22 static int panfrost_reset_init(struct panfrost_device *pfdev)
23 {
24 	pfdev->rstc = devm_reset_control_array_get_optional_exclusive(pfdev->base.dev);
25 	if (IS_ERR(pfdev->rstc)) {
26 		dev_err(pfdev->base.dev, "get reset failed %ld\n", PTR_ERR(pfdev->rstc));
27 		return PTR_ERR(pfdev->rstc);
28 	}
29 
30 	return reset_control_deassert(pfdev->rstc);
31 }
32 
33 static void panfrost_reset_fini(struct panfrost_device *pfdev)
34 {
35 	reset_control_assert(pfdev->rstc);
36 }
37 
38 static int panfrost_clk_init(struct panfrost_device *pfdev)
39 {
40 	int err;
41 	unsigned long rate;
42 
43 	pfdev->clock = devm_clk_get(pfdev->base.dev, NULL);
44 	if (IS_ERR(pfdev->clock)) {
45 		dev_err(pfdev->base.dev, "get clock failed %ld\n", PTR_ERR(pfdev->clock));
46 		return PTR_ERR(pfdev->clock);
47 	}
48 
49 	rate = clk_get_rate(pfdev->clock);
50 	dev_info(pfdev->base.dev, "clock rate = %lu\n", rate);
51 
52 	err = clk_prepare_enable(pfdev->clock);
53 	if (err)
54 		return err;
55 
56 	pfdev->bus_clock = devm_clk_get_optional(pfdev->base.dev, "bus");
57 	if (IS_ERR(pfdev->bus_clock)) {
58 		dev_err(pfdev->base.dev, "get bus_clock failed %ld\n",
59 			PTR_ERR(pfdev->bus_clock));
60 		err = PTR_ERR(pfdev->bus_clock);
61 		goto disable_clock;
62 	}
63 
64 	if (pfdev->bus_clock) {
65 		rate = clk_get_rate(pfdev->bus_clock);
66 		dev_info(pfdev->base.dev, "bus_clock rate = %lu\n", rate);
67 
68 		err = clk_prepare_enable(pfdev->bus_clock);
69 		if (err)
70 			goto disable_clock;
71 	}
72 
73 	pfdev->bus_ace_clock = devm_clk_get_optional(pfdev->base.dev, "bus_ace");
74 	if (IS_ERR(pfdev->bus_ace_clock)) {
75 		err = PTR_ERR(pfdev->bus_ace_clock);
76 		dev_err(pfdev->base.dev, "get bus_ace_clock failed %d\n", err);
77 		goto disable_bus_clock;
78 	}
79 
80 	err = clk_prepare_enable(pfdev->bus_ace_clock);
81 	if (err)
82 		goto disable_bus_clock;
83 
84 	return 0;
85 
86 disable_bus_clock:
87 	clk_disable_unprepare(pfdev->bus_clock);
88 disable_clock:
89 	clk_disable_unprepare(pfdev->clock);
90 
91 	return err;
92 }
93 
94 static void panfrost_clk_fini(struct panfrost_device *pfdev)
95 {
96 	clk_disable_unprepare(pfdev->bus_ace_clock);
97 	clk_disable_unprepare(pfdev->bus_clock);
98 	clk_disable_unprepare(pfdev->clock);
99 }
100 
101 static int panfrost_regulator_init(struct panfrost_device *pfdev)
102 {
103 	int ret, i;
104 
105 	pfdev->regulators = devm_kcalloc(pfdev->base.dev, pfdev->comp->num_supplies,
106 					 sizeof(*pfdev->regulators),
107 					 GFP_KERNEL);
108 	if (!pfdev->regulators)
109 		return -ENOMEM;
110 
111 	for (i = 0; i < pfdev->comp->num_supplies; i++)
112 		pfdev->regulators[i].supply = pfdev->comp->supply_names[i];
113 
114 	ret = devm_regulator_bulk_get(pfdev->base.dev,
115 				      pfdev->comp->num_supplies,
116 				      pfdev->regulators);
117 	if (ret < 0) {
118 		if (ret != -EPROBE_DEFER)
119 			dev_err(pfdev->base.dev, "failed to get regulators: %d\n",
120 				ret);
121 		return ret;
122 	}
123 
124 	ret = regulator_bulk_enable(pfdev->comp->num_supplies,
125 				    pfdev->regulators);
126 	if (ret < 0) {
127 		dev_err(pfdev->base.dev, "failed to enable regulators: %d\n", ret);
128 		return ret;
129 	}
130 
131 	return 0;
132 }
133 
134 static void panfrost_regulator_fini(struct panfrost_device *pfdev)
135 {
136 	if (!pfdev->regulators)
137 		return;
138 
139 	regulator_bulk_disable(pfdev->comp->num_supplies, pfdev->regulators);
140 }
141 
142 static void panfrost_pm_domain_fini(struct panfrost_device *pfdev)
143 {
144 	int i;
145 
146 	for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
147 		if (!pfdev->pm_domain_devs[i])
148 			break;
149 
150 		if (pfdev->pm_domain_links[i])
151 			device_link_del(pfdev->pm_domain_links[i]);
152 
153 		dev_pm_domain_detach(pfdev->pm_domain_devs[i], true);
154 	}
155 }
156 
157 static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
158 {
159 	int err;
160 	int i, num_domains;
161 
162 	num_domains = of_count_phandle_with_args(pfdev->base.dev->of_node,
163 						 "power-domains",
164 						 "#power-domain-cells");
165 
166 	/*
167 	 * Single domain is handled by the core, and, if only a single power
168 	 * the power domain is requested, the property is optional.
169 	 */
170 	if (num_domains < 2 && pfdev->comp->num_pm_domains < 2)
171 		return 0;
172 
173 	if (num_domains != pfdev->comp->num_pm_domains) {
174 		dev_err(pfdev->base.dev,
175 			"Incorrect number of power domains: %d provided, %d needed\n",
176 			num_domains, pfdev->comp->num_pm_domains);
177 		return -EINVAL;
178 	}
179 
180 	if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
181 			"Too many supplies in compatible structure.\n"))
182 		return -EINVAL;
183 
184 	for (i = 0; i < num_domains; i++) {
185 		pfdev->pm_domain_devs[i] =
186 			dev_pm_domain_attach_by_name(pfdev->base.dev,
187 						     pfdev->comp->pm_domain_names[i]);
188 		if (IS_ERR_OR_NULL(pfdev->pm_domain_devs[i])) {
189 			err = PTR_ERR(pfdev->pm_domain_devs[i]) ? : -ENODATA;
190 			pfdev->pm_domain_devs[i] = NULL;
191 			dev_err(pfdev->base.dev,
192 				"failed to get pm-domain %s(%d): %d\n",
193 				pfdev->comp->pm_domain_names[i], i, err);
194 			goto err;
195 		}
196 
197 		pfdev->pm_domain_links[i] =
198 			device_link_add(pfdev->base.dev,
199 					pfdev->pm_domain_devs[i], DL_FLAG_PM_RUNTIME |
200 					DL_FLAG_STATELESS | DL_FLAG_RPM_ACTIVE);
201 		if (!pfdev->pm_domain_links[i]) {
202 			dev_err(pfdev->pm_domain_devs[i],
203 				"adding device link failed!\n");
204 			err = -ENODEV;
205 			goto err;
206 		}
207 	}
208 
209 	return 0;
210 
211 err:
212 	panfrost_pm_domain_fini(pfdev);
213 	return err;
214 }
215 
216 int panfrost_device_init(struct panfrost_device *pfdev)
217 {
218 	int err;
219 
220 	mutex_init(&pfdev->sched_lock);
221 	INIT_LIST_HEAD(&pfdev->scheduled_jobs);
222 	INIT_LIST_HEAD(&pfdev->as_lru_list);
223 
224 	spin_lock_init(&pfdev->as_lock);
225 
226 	spin_lock_init(&pfdev->cycle_counter.lock);
227 
228 #ifdef CONFIG_DEBUG_FS
229 	mutex_init(&pfdev->debugfs.gems_lock);
230 	INIT_LIST_HEAD(&pfdev->debugfs.gems_list);
231 #endif
232 
233 	err = panfrost_pm_domain_init(pfdev);
234 	if (err)
235 		return err;
236 
237 	err = panfrost_reset_init(pfdev);
238 	if (err) {
239 		dev_err(pfdev->base.dev, "reset init failed %d\n", err);
240 		goto out_pm_domain;
241 	}
242 
243 	err = panfrost_clk_init(pfdev);
244 	if (err) {
245 		dev_err(pfdev->base.dev, "clk init failed %d\n", err);
246 		goto out_reset;
247 	}
248 
249 	err = panfrost_devfreq_init(pfdev);
250 	if (err) {
251 		if (err != -EPROBE_DEFER)
252 			dev_err(pfdev->base.dev, "devfreq init failed %d\n", err);
253 		goto out_clk;
254 	}
255 
256 	/* OPP will handle regulators */
257 	if (!pfdev->pfdevfreq.opp_of_table_added) {
258 		err = panfrost_regulator_init(pfdev);
259 		if (err)
260 			goto out_devfreq;
261 	}
262 
263 	pfdev->iomem = devm_platform_ioremap_resource(to_platform_device(pfdev->base.dev), 0);
264 	if (IS_ERR(pfdev->iomem)) {
265 		err = PTR_ERR(pfdev->iomem);
266 		goto out_regulator;
267 	}
268 
269 	err = panfrost_gpu_init(pfdev);
270 	if (err)
271 		goto out_regulator;
272 
273 	err = panfrost_mmu_init(pfdev);
274 	if (err)
275 		goto out_gpu;
276 
277 	err = panfrost_jm_init(pfdev);
278 	if (err)
279 		goto out_mmu;
280 
281 	err = panfrost_perfcnt_init(pfdev);
282 	if (err)
283 		goto out_job;
284 
285 	panfrost_gem_init(pfdev);
286 
287 	return 0;
288 out_job:
289 	panfrost_jm_fini(pfdev);
290 out_mmu:
291 	panfrost_mmu_fini(pfdev);
292 out_gpu:
293 	panfrost_gpu_fini(pfdev);
294 out_regulator:
295 	panfrost_regulator_fini(pfdev);
296 out_devfreq:
297 	panfrost_devfreq_fini(pfdev);
298 out_clk:
299 	panfrost_clk_fini(pfdev);
300 out_reset:
301 	panfrost_reset_fini(pfdev);
302 out_pm_domain:
303 	panfrost_pm_domain_fini(pfdev);
304 	return err;
305 }
306 
307 void panfrost_device_fini(struct panfrost_device *pfdev)
308 {
309 	panfrost_perfcnt_fini(pfdev);
310 	panfrost_jm_fini(pfdev);
311 	panfrost_mmu_fini(pfdev);
312 	panfrost_gpu_fini(pfdev);
313 	panfrost_devfreq_fini(pfdev);
314 	panfrost_regulator_fini(pfdev);
315 	panfrost_clk_fini(pfdev);
316 	panfrost_reset_fini(pfdev);
317 	panfrost_pm_domain_fini(pfdev);
318 }
319 
320 #define PANFROST_EXCEPTION(id) \
321 	[DRM_PANFROST_EXCEPTION_ ## id] = { \
322 		.name = #id, \
323 	}
324 
325 struct panfrost_exception_info {
326 	const char *name;
327 };
328 
329 static const struct panfrost_exception_info panfrost_exception_infos[] = {
330 	PANFROST_EXCEPTION(OK),
331 	PANFROST_EXCEPTION(DONE),
332 	PANFROST_EXCEPTION(INTERRUPTED),
333 	PANFROST_EXCEPTION(STOPPED),
334 	PANFROST_EXCEPTION(TERMINATED),
335 	PANFROST_EXCEPTION(KABOOM),
336 	PANFROST_EXCEPTION(EUREKA),
337 	PANFROST_EXCEPTION(ACTIVE),
338 	PANFROST_EXCEPTION(JOB_CONFIG_FAULT),
339 	PANFROST_EXCEPTION(JOB_POWER_FAULT),
340 	PANFROST_EXCEPTION(JOB_READ_FAULT),
341 	PANFROST_EXCEPTION(JOB_WRITE_FAULT),
342 	PANFROST_EXCEPTION(JOB_AFFINITY_FAULT),
343 	PANFROST_EXCEPTION(JOB_BUS_FAULT),
344 	PANFROST_EXCEPTION(INSTR_INVALID_PC),
345 	PANFROST_EXCEPTION(INSTR_INVALID_ENC),
346 	PANFROST_EXCEPTION(INSTR_TYPE_MISMATCH),
347 	PANFROST_EXCEPTION(INSTR_OPERAND_FAULT),
348 	PANFROST_EXCEPTION(INSTR_TLS_FAULT),
349 	PANFROST_EXCEPTION(INSTR_BARRIER_FAULT),
350 	PANFROST_EXCEPTION(INSTR_ALIGN_FAULT),
351 	PANFROST_EXCEPTION(DATA_INVALID_FAULT),
352 	PANFROST_EXCEPTION(TILE_RANGE_FAULT),
353 	PANFROST_EXCEPTION(ADDR_RANGE_FAULT),
354 	PANFROST_EXCEPTION(IMPRECISE_FAULT),
355 	PANFROST_EXCEPTION(OOM),
356 	PANFROST_EXCEPTION(OOM_AFBC),
357 	PANFROST_EXCEPTION(UNKNOWN),
358 	PANFROST_EXCEPTION(DELAYED_BUS_FAULT),
359 	PANFROST_EXCEPTION(GPU_SHAREABILITY_FAULT),
360 	PANFROST_EXCEPTION(SYS_SHAREABILITY_FAULT),
361 	PANFROST_EXCEPTION(GPU_CACHEABILITY_FAULT),
362 	PANFROST_EXCEPTION(TRANSLATION_FAULT_0),
363 	PANFROST_EXCEPTION(TRANSLATION_FAULT_1),
364 	PANFROST_EXCEPTION(TRANSLATION_FAULT_2),
365 	PANFROST_EXCEPTION(TRANSLATION_FAULT_3),
366 	PANFROST_EXCEPTION(TRANSLATION_FAULT_4),
367 	PANFROST_EXCEPTION(TRANSLATION_FAULT_IDENTITY),
368 	PANFROST_EXCEPTION(PERM_FAULT_0),
369 	PANFROST_EXCEPTION(PERM_FAULT_1),
370 	PANFROST_EXCEPTION(PERM_FAULT_2),
371 	PANFROST_EXCEPTION(PERM_FAULT_3),
372 	PANFROST_EXCEPTION(TRANSTAB_BUS_FAULT_0),
373 	PANFROST_EXCEPTION(TRANSTAB_BUS_FAULT_1),
374 	PANFROST_EXCEPTION(TRANSTAB_BUS_FAULT_2),
375 	PANFROST_EXCEPTION(TRANSTAB_BUS_FAULT_3),
376 	PANFROST_EXCEPTION(ACCESS_FLAG_0),
377 	PANFROST_EXCEPTION(ACCESS_FLAG_1),
378 	PANFROST_EXCEPTION(ACCESS_FLAG_2),
379 	PANFROST_EXCEPTION(ACCESS_FLAG_3),
380 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_IN0),
381 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_IN1),
382 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_IN2),
383 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_IN3),
384 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_OUT0),
385 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_OUT1),
386 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_OUT2),
387 	PANFROST_EXCEPTION(ADDR_SIZE_FAULT_OUT3),
388 	PANFROST_EXCEPTION(MEM_ATTR_FAULT_0),
389 	PANFROST_EXCEPTION(MEM_ATTR_FAULT_1),
390 	PANFROST_EXCEPTION(MEM_ATTR_FAULT_2),
391 	PANFROST_EXCEPTION(MEM_ATTR_FAULT_3),
392 	PANFROST_EXCEPTION(MEM_ATTR_NONCACHE_0),
393 	PANFROST_EXCEPTION(MEM_ATTR_NONCACHE_1),
394 	PANFROST_EXCEPTION(MEM_ATTR_NONCACHE_2),
395 	PANFROST_EXCEPTION(MEM_ATTR_NONCACHE_3),
396 };
397 
398 const char *panfrost_exception_name(u32 exception_code)
399 {
400 	if (WARN_ON(exception_code >= ARRAY_SIZE(panfrost_exception_infos) ||
401 		    !panfrost_exception_infos[exception_code].name))
402 		return "Unknown exception type";
403 
404 	return panfrost_exception_infos[exception_code].name;
405 }
406 
407 bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev,
408 				    u32 exception_code)
409 {
410 	/* If an occlusion query write causes a bus fault on affected GPUs,
411 	 * future fragment jobs may hang. Reset to workaround.
412 	 */
413 	if (exception_code == DRM_PANFROST_EXCEPTION_JOB_BUS_FAULT)
414 		return panfrost_has_hw_issue(pfdev, HW_ISSUE_TTRX_3076);
415 
416 	/* No other GPUs we support need a reset */
417 	return false;
418 }
419 
420 void panfrost_device_reset(struct panfrost_device *pfdev, bool enable_job_int)
421 {
422 	panfrost_gpu_soft_reset(pfdev);
423 
424 	panfrost_gpu_power_on(pfdev);
425 	panfrost_mmu_reset(pfdev);
426 
427 	panfrost_jm_reset_interrupts(pfdev);
428 	if (enable_job_int)
429 		panfrost_jm_enable_interrupts(pfdev);
430 }
431 
432 static int panfrost_device_runtime_resume(struct device *dev)
433 {
434 	struct panfrost_device *pfdev = dev_get_drvdata(dev);
435 	int ret;
436 
437 	if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) {
438 		ret = reset_control_deassert(pfdev->rstc);
439 		if (ret)
440 			return ret;
441 
442 		ret = clk_enable(pfdev->clock);
443 		if (ret)
444 			goto err_clk;
445 
446 		ret = clk_enable(pfdev->bus_clock);
447 		if (ret)
448 			goto err_bus_clk;
449 
450 		ret = clk_enable(pfdev->bus_ace_clock);
451 		if (ret)
452 			goto err_bus_ace_clk;
453 	}
454 
455 	panfrost_device_reset(pfdev, true);
456 	panfrost_devfreq_resume(pfdev);
457 
458 	return 0;
459 
460 err_bus_ace_clk:
461 	if (pfdev->comp->pm_features & BIT(GPU_PM_RT))
462 		clk_disable(pfdev->bus_clock);
463 err_bus_clk:
464 	if (pfdev->comp->pm_features & BIT(GPU_PM_RT))
465 		clk_disable(pfdev->clock);
466 err_clk:
467 	if (pfdev->comp->pm_features & BIT(GPU_PM_RT))
468 		reset_control_assert(pfdev->rstc);
469 	return ret;
470 }
471 
472 static int panfrost_device_runtime_suspend(struct device *dev)
473 {
474 	struct panfrost_device *pfdev = dev_get_drvdata(dev);
475 
476 	if (!panfrost_jm_is_idle(pfdev))
477 		return -EBUSY;
478 
479 	panfrost_devfreq_suspend(pfdev);
480 	panfrost_jm_suspend_irq(pfdev);
481 	panfrost_mmu_suspend_irq(pfdev);
482 	panfrost_gpu_suspend_irq(pfdev);
483 	panfrost_gpu_power_off(pfdev);
484 
485 	if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) {
486 		clk_disable(pfdev->bus_ace_clock);
487 		clk_disable(pfdev->bus_clock);
488 		clk_disable(pfdev->clock);
489 		reset_control_assert(pfdev->rstc);
490 	}
491 
492 	return 0;
493 }
494 
495 static int panfrost_device_resume(struct device *dev)
496 {
497 	struct panfrost_device *pfdev = dev_get_drvdata(dev);
498 	int ret;
499 
500 	if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF)) {
501 		unsigned long freq = pfdev->pfdevfreq.fast_rate;
502 		struct dev_pm_opp *opp;
503 
504 		opp = dev_pm_opp_find_freq_ceil(dev, &freq);
505 		if (IS_ERR(opp))
506 			return PTR_ERR(opp);
507 		dev_pm_opp_set_opp(dev, opp);
508 		dev_pm_opp_put(opp);
509 	}
510 
511 	if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) {
512 		ret = clk_enable(pfdev->clock);
513 		if (ret)
514 			goto err_clk;
515 
516 		if (pfdev->bus_clock) {
517 			ret = clk_enable(pfdev->bus_clock);
518 			if (ret)
519 				goto err_bus_clk;
520 		}
521 	}
522 
523 	ret = pm_runtime_force_resume(dev);
524 	if (ret)
525 		goto err_resume;
526 
527 	return 0;
528 
529 err_resume:
530 	if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS) && pfdev->bus_clock)
531 		clk_disable(pfdev->bus_clock);
532 err_bus_clk:
533 	if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS))
534 		clk_disable(pfdev->clock);
535 err_clk:
536 	if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF))
537 		dev_pm_opp_set_opp(dev, NULL);
538 	return ret;
539 }
540 
541 static int panfrost_device_suspend(struct device *dev)
542 {
543 	struct panfrost_device *pfdev = dev_get_drvdata(dev);
544 	int ret;
545 
546 	ret = pm_runtime_force_suspend(dev);
547 	if (ret)
548 		return ret;
549 
550 	if (pfdev->comp->pm_features & BIT(GPU_PM_CLK_DIS)) {
551 		if (pfdev->bus_clock)
552 			clk_disable(pfdev->bus_clock);
553 
554 		clk_disable(pfdev->clock);
555 	}
556 
557 	if (pfdev->comp->pm_features & BIT(GPU_PM_VREG_OFF))
558 		dev_pm_opp_set_opp(dev, NULL);
559 
560 	return 0;
561 }
562 
563 EXPORT_GPL_DEV_PM_OPS(panfrost_pm_ops) = {
564 	RUNTIME_PM_OPS(panfrost_device_runtime_suspend, panfrost_device_runtime_resume, NULL)
565 	SYSTEM_SLEEP_PM_OPS(panfrost_device_suspend, panfrost_device_resume)
566 };
567