1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 31 #include <video/display_timing.h> 32 #include <video/of_display_timing.h> 33 #include <video/videomode.h> 34 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_device.h> 37 #include <drm/drm_mipi_dsi.h> 38 #include <drm/drm_panel.h> 39 40 /** 41 * @modes: Pointer to array of fixed modes appropriate for this panel. If 42 * only one mode then this can just be the address of this the mode. 43 * NOTE: cannot be used with "timings" and also if this is specified 44 * then you cannot override the mode in the device tree. 45 * @num_modes: Number of elements in modes array. 46 * @timings: Pointer to array of display timings. NOTE: cannot be used with 47 * "modes" and also these will be used to validate a device tree 48 * override if one is present. 49 * @num_timings: Number of elements in timings array. 50 * @bpc: Bits per color. 51 * @size: Structure containing the physical size of this panel. 52 * @delay: Structure containing various delay values for this panel. 53 * @bus_format: See MEDIA_BUS_FMT_... defines. 54 * @bus_flags: See DRM_BUS_FLAG_... defines. 55 */ 56 struct panel_desc { 57 const struct drm_display_mode *modes; 58 unsigned int num_modes; 59 const struct display_timing *timings; 60 unsigned int num_timings; 61 62 unsigned int bpc; 63 64 /** 65 * @width: width (in millimeters) of the panel's active display area 66 * @height: height (in millimeters) of the panel's active display area 67 */ 68 struct { 69 unsigned int width; 70 unsigned int height; 71 } size; 72 73 /** 74 * @prepare: the time (in milliseconds) that it takes for the panel to 75 * become ready and start receiving video data 76 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 77 * Plug Detect isn't used. 78 * @enable: the time (in milliseconds) that it takes for the panel to 79 * display the first valid frame after starting to receive 80 * video data 81 * @disable: the time (in milliseconds) that it takes for the panel to 82 * turn the display off (no content is visible) 83 * @unprepare: the time (in milliseconds) that it takes for the panel 84 * to power itself down completely 85 */ 86 struct { 87 unsigned int prepare; 88 unsigned int hpd_absent_delay; 89 unsigned int enable; 90 unsigned int disable; 91 unsigned int unprepare; 92 } delay; 93 94 u32 bus_format; 95 u32 bus_flags; 96 int connector_type; 97 }; 98 99 struct panel_simple { 100 struct drm_panel base; 101 bool prepared; 102 bool enabled; 103 bool no_hpd; 104 105 const struct panel_desc *desc; 106 107 struct regulator *supply; 108 struct i2c_adapter *ddc; 109 110 struct gpio_desc *enable_gpio; 111 112 struct drm_display_mode override_mode; 113 }; 114 115 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 116 { 117 return container_of(panel, struct panel_simple, base); 118 } 119 120 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 121 struct drm_connector *connector) 122 { 123 struct drm_display_mode *mode; 124 unsigned int i, num = 0; 125 126 for (i = 0; i < panel->desc->num_timings; i++) { 127 const struct display_timing *dt = &panel->desc->timings[i]; 128 struct videomode vm; 129 130 videomode_from_timing(dt, &vm); 131 mode = drm_mode_create(connector->dev); 132 if (!mode) { 133 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 134 dt->hactive.typ, dt->vactive.typ); 135 continue; 136 } 137 138 drm_display_mode_from_videomode(&vm, mode); 139 140 mode->type |= DRM_MODE_TYPE_DRIVER; 141 142 if (panel->desc->num_timings == 1) 143 mode->type |= DRM_MODE_TYPE_PREFERRED; 144 145 drm_mode_probed_add(connector, mode); 146 num++; 147 } 148 149 return num; 150 } 151 152 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 153 struct drm_connector *connector) 154 { 155 struct drm_display_mode *mode; 156 unsigned int i, num = 0; 157 158 for (i = 0; i < panel->desc->num_modes; i++) { 159 const struct drm_display_mode *m = &panel->desc->modes[i]; 160 161 mode = drm_mode_duplicate(connector->dev, m); 162 if (!mode) { 163 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 164 m->hdisplay, m->vdisplay, m->vrefresh); 165 continue; 166 } 167 168 mode->type |= DRM_MODE_TYPE_DRIVER; 169 170 if (panel->desc->num_modes == 1) 171 mode->type |= DRM_MODE_TYPE_PREFERRED; 172 173 drm_mode_set_name(mode); 174 175 drm_mode_probed_add(connector, mode); 176 num++; 177 } 178 179 return num; 180 } 181 182 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 183 struct drm_connector *connector) 184 { 185 struct drm_display_mode *mode; 186 bool has_override = panel->override_mode.type; 187 unsigned int num = 0; 188 189 if (!panel->desc) 190 return 0; 191 192 if (has_override) { 193 mode = drm_mode_duplicate(connector->dev, 194 &panel->override_mode); 195 if (mode) { 196 drm_mode_probed_add(connector, mode); 197 num = 1; 198 } else { 199 dev_err(panel->base.dev, "failed to add override mode\n"); 200 } 201 } 202 203 /* Only add timings if override was not there or failed to validate */ 204 if (num == 0 && panel->desc->num_timings) 205 num = panel_simple_get_timings_modes(panel, connector); 206 207 /* 208 * Only add fixed modes if timings/override added no mode. 209 * 210 * We should only ever have either the display timings specified 211 * or a fixed mode. Anything else is rather bogus. 212 */ 213 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 214 if (num == 0) 215 num = panel_simple_get_display_modes(panel, connector); 216 217 connector->display_info.bpc = panel->desc->bpc; 218 connector->display_info.width_mm = panel->desc->size.width; 219 connector->display_info.height_mm = panel->desc->size.height; 220 if (panel->desc->bus_format) 221 drm_display_info_set_bus_formats(&connector->display_info, 222 &panel->desc->bus_format, 1); 223 connector->display_info.bus_flags = panel->desc->bus_flags; 224 225 return num; 226 } 227 228 static int panel_simple_disable(struct drm_panel *panel) 229 { 230 struct panel_simple *p = to_panel_simple(panel); 231 232 if (!p->enabled) 233 return 0; 234 235 if (p->desc->delay.disable) 236 msleep(p->desc->delay.disable); 237 238 p->enabled = false; 239 240 return 0; 241 } 242 243 static int panel_simple_unprepare(struct drm_panel *panel) 244 { 245 struct panel_simple *p = to_panel_simple(panel); 246 247 if (!p->prepared) 248 return 0; 249 250 gpiod_set_value_cansleep(p->enable_gpio, 0); 251 252 regulator_disable(p->supply); 253 254 if (p->desc->delay.unprepare) 255 msleep(p->desc->delay.unprepare); 256 257 p->prepared = false; 258 259 return 0; 260 } 261 262 static int panel_simple_prepare(struct drm_panel *panel) 263 { 264 struct panel_simple *p = to_panel_simple(panel); 265 unsigned int delay; 266 int err; 267 268 if (p->prepared) 269 return 0; 270 271 err = regulator_enable(p->supply); 272 if (err < 0) { 273 dev_err(panel->dev, "failed to enable supply: %d\n", err); 274 return err; 275 } 276 277 gpiod_set_value_cansleep(p->enable_gpio, 1); 278 279 delay = p->desc->delay.prepare; 280 if (p->no_hpd) 281 delay += p->desc->delay.hpd_absent_delay; 282 if (delay) 283 msleep(delay); 284 285 p->prepared = true; 286 287 return 0; 288 } 289 290 static int panel_simple_enable(struct drm_panel *panel) 291 { 292 struct panel_simple *p = to_panel_simple(panel); 293 294 if (p->enabled) 295 return 0; 296 297 if (p->desc->delay.enable) 298 msleep(p->desc->delay.enable); 299 300 p->enabled = true; 301 302 return 0; 303 } 304 305 static int panel_simple_get_modes(struct drm_panel *panel, 306 struct drm_connector *connector) 307 { 308 struct panel_simple *p = to_panel_simple(panel); 309 int num = 0; 310 311 /* probe EDID if a DDC bus is available */ 312 if (p->ddc) { 313 struct edid *edid = drm_get_edid(connector, p->ddc); 314 315 drm_connector_update_edid_property(connector, edid); 316 if (edid) { 317 num += drm_add_edid_modes(connector, edid); 318 kfree(edid); 319 } 320 } 321 322 /* add hard-coded panel modes */ 323 num += panel_simple_get_non_edid_modes(p, connector); 324 325 return num; 326 } 327 328 static int panel_simple_get_timings(struct drm_panel *panel, 329 unsigned int num_timings, 330 struct display_timing *timings) 331 { 332 struct panel_simple *p = to_panel_simple(panel); 333 unsigned int i; 334 335 if (p->desc->num_timings < num_timings) 336 num_timings = p->desc->num_timings; 337 338 if (timings) 339 for (i = 0; i < num_timings; i++) 340 timings[i] = p->desc->timings[i]; 341 342 return p->desc->num_timings; 343 } 344 345 static const struct drm_panel_funcs panel_simple_funcs = { 346 .disable = panel_simple_disable, 347 .unprepare = panel_simple_unprepare, 348 .prepare = panel_simple_prepare, 349 .enable = panel_simple_enable, 350 .get_modes = panel_simple_get_modes, 351 .get_timings = panel_simple_get_timings, 352 }; 353 354 static struct panel_desc panel_dpi; 355 356 static int panel_dpi_probe(struct device *dev, 357 struct panel_simple *panel) 358 { 359 struct display_timing *timing; 360 const struct device_node *np; 361 struct panel_desc *desc; 362 unsigned int bus_flags; 363 struct videomode vm; 364 const char *mapping; 365 int ret; 366 367 np = dev->of_node; 368 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 369 if (!desc) 370 return -ENOMEM; 371 372 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 373 if (!timing) 374 return -ENOMEM; 375 376 ret = of_get_display_timing(np, "panel-timing", timing); 377 if (ret < 0) { 378 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 379 np); 380 return ret; 381 } 382 383 desc->timings = timing; 384 desc->num_timings = 1; 385 386 of_property_read_u32(np, "width-mm", &desc->size.width); 387 of_property_read_u32(np, "height-mm", &desc->size.height); 388 389 of_property_read_string(np, "data-mapping", &mapping); 390 if (!strcmp(mapping, "rgb24")) 391 desc->bus_format = MEDIA_BUS_FMT_RGB888_1X24; 392 else if (!strcmp(mapping, "rgb565")) 393 desc->bus_format = MEDIA_BUS_FMT_RGB565_1X16; 394 else if (!strcmp(mapping, "bgr666")) 395 desc->bus_format = MEDIA_BUS_FMT_RGB666_1X18; 396 else if (!strcmp(mapping, "lvds666")) 397 desc->bus_format = MEDIA_BUS_FMT_RGB666_1X24_CPADHI; 398 399 /* Extract bus_flags from display_timing */ 400 bus_flags = 0; 401 vm.flags = timing->flags; 402 drm_bus_flags_from_videomode(&vm, &bus_flags); 403 desc->bus_flags = bus_flags; 404 405 /* We do not know the connector for the DT node, so guess it */ 406 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 407 408 panel->desc = desc; 409 410 return 0; 411 } 412 413 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 414 (to_check->field.typ >= bounds->field.min && \ 415 to_check->field.typ <= bounds->field.max) 416 static void panel_simple_parse_panel_timing_node(struct device *dev, 417 struct panel_simple *panel, 418 const struct display_timing *ot) 419 { 420 const struct panel_desc *desc = panel->desc; 421 struct videomode vm; 422 unsigned int i; 423 424 if (WARN_ON(desc->num_modes)) { 425 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 426 return; 427 } 428 if (WARN_ON(!desc->num_timings)) { 429 dev_err(dev, "Reject override mode: no timings specified\n"); 430 return; 431 } 432 433 for (i = 0; i < panel->desc->num_timings; i++) { 434 const struct display_timing *dt = &panel->desc->timings[i]; 435 436 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 437 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 438 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 439 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 440 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 441 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 442 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 443 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 444 continue; 445 446 if (ot->flags != dt->flags) 447 continue; 448 449 videomode_from_timing(ot, &vm); 450 drm_display_mode_from_videomode(&vm, &panel->override_mode); 451 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 452 DRM_MODE_TYPE_PREFERRED; 453 break; 454 } 455 456 if (WARN_ON(!panel->override_mode.type)) 457 dev_err(dev, "Reject override mode: No display_timing found\n"); 458 } 459 460 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 461 { 462 struct panel_simple *panel; 463 struct display_timing dt; 464 struct device_node *ddc; 465 int err; 466 467 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 468 if (!panel) 469 return -ENOMEM; 470 471 panel->enabled = false; 472 panel->prepared = false; 473 panel->desc = desc; 474 475 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 476 477 panel->supply = devm_regulator_get(dev, "power"); 478 if (IS_ERR(panel->supply)) 479 return PTR_ERR(panel->supply); 480 481 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 482 GPIOD_OUT_LOW); 483 if (IS_ERR(panel->enable_gpio)) { 484 err = PTR_ERR(panel->enable_gpio); 485 if (err != -EPROBE_DEFER) 486 dev_err(dev, "failed to request GPIO: %d\n", err); 487 return err; 488 } 489 490 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 491 if (ddc) { 492 panel->ddc = of_find_i2c_adapter_by_node(ddc); 493 of_node_put(ddc); 494 495 if (!panel->ddc) 496 return -EPROBE_DEFER; 497 } 498 499 if (desc == &panel_dpi) { 500 /* Handle the generic panel-dpi binding */ 501 err = panel_dpi_probe(dev, panel); 502 if (err) 503 goto free_ddc; 504 } else { 505 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 506 panel_simple_parse_panel_timing_node(dev, panel, &dt); 507 } 508 509 drm_panel_init(&panel->base, dev, &panel_simple_funcs, 510 desc->connector_type); 511 512 err = drm_panel_of_backlight(&panel->base); 513 if (err) 514 goto free_ddc; 515 516 err = drm_panel_add(&panel->base); 517 if (err < 0) 518 goto free_ddc; 519 520 dev_set_drvdata(dev, panel); 521 522 return 0; 523 524 free_ddc: 525 if (panel->ddc) 526 put_device(&panel->ddc->dev); 527 528 return err; 529 } 530 531 static int panel_simple_remove(struct device *dev) 532 { 533 struct panel_simple *panel = dev_get_drvdata(dev); 534 535 drm_panel_remove(&panel->base); 536 drm_panel_disable(&panel->base); 537 drm_panel_unprepare(&panel->base); 538 539 if (panel->ddc) 540 put_device(&panel->ddc->dev); 541 542 return 0; 543 } 544 545 static void panel_simple_shutdown(struct device *dev) 546 { 547 struct panel_simple *panel = dev_get_drvdata(dev); 548 549 drm_panel_disable(&panel->base); 550 drm_panel_unprepare(&panel->base); 551 } 552 553 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 554 .clock = 9000, 555 .hdisplay = 480, 556 .hsync_start = 480 + 2, 557 .hsync_end = 480 + 2 + 41, 558 .htotal = 480 + 2 + 41 + 2, 559 .vdisplay = 272, 560 .vsync_start = 272 + 2, 561 .vsync_end = 272 + 2 + 10, 562 .vtotal = 272 + 2 + 10 + 2, 563 .vrefresh = 60, 564 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 565 }; 566 567 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 568 .modes = &ire_am_480272h3tmqw_t01h_mode, 569 .num_modes = 1, 570 .bpc = 8, 571 .size = { 572 .width = 105, 573 .height = 67, 574 }, 575 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 576 }; 577 578 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 579 .clock = 33333, 580 .hdisplay = 800, 581 .hsync_start = 800 + 0, 582 .hsync_end = 800 + 0 + 255, 583 .htotal = 800 + 0 + 255 + 0, 584 .vdisplay = 480, 585 .vsync_start = 480 + 2, 586 .vsync_end = 480 + 2 + 45, 587 .vtotal = 480 + 2 + 45 + 0, 588 .vrefresh = 60, 589 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 590 }; 591 592 static const struct panel_desc ampire_am800480r3tmqwa1h = { 593 .modes = &ire_am800480r3tmqwa1h_mode, 594 .num_modes = 1, 595 .bpc = 6, 596 .size = { 597 .width = 152, 598 .height = 91, 599 }, 600 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 601 }; 602 603 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 604 .pixelclock = { 26400000, 33300000, 46800000 }, 605 .hactive = { 800, 800, 800 }, 606 .hfront_porch = { 16, 210, 354 }, 607 .hback_porch = { 45, 36, 6 }, 608 .hsync_len = { 1, 10, 40 }, 609 .vactive = { 480, 480, 480 }, 610 .vfront_porch = { 7, 22, 147 }, 611 .vback_porch = { 22, 13, 3 }, 612 .vsync_len = { 1, 10, 20 }, 613 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 614 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 615 }; 616 617 static const struct panel_desc armadeus_st0700_adapt = { 618 .timings = &santek_st0700i5y_rbslw_f_timing, 619 .num_timings = 1, 620 .bpc = 6, 621 .size = { 622 .width = 154, 623 .height = 86, 624 }, 625 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 626 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 627 }; 628 629 static const struct drm_display_mode auo_b101aw03_mode = { 630 .clock = 51450, 631 .hdisplay = 1024, 632 .hsync_start = 1024 + 156, 633 .hsync_end = 1024 + 156 + 8, 634 .htotal = 1024 + 156 + 8 + 156, 635 .vdisplay = 600, 636 .vsync_start = 600 + 16, 637 .vsync_end = 600 + 16 + 6, 638 .vtotal = 600 + 16 + 6 + 16, 639 .vrefresh = 60, 640 }; 641 642 static const struct panel_desc auo_b101aw03 = { 643 .modes = &auo_b101aw03_mode, 644 .num_modes = 1, 645 .bpc = 6, 646 .size = { 647 .width = 223, 648 .height = 125, 649 }, 650 }; 651 652 static const struct display_timing auo_b101ean01_timing = { 653 .pixelclock = { 65300000, 72500000, 75000000 }, 654 .hactive = { 1280, 1280, 1280 }, 655 .hfront_porch = { 18, 119, 119 }, 656 .hback_porch = { 21, 21, 21 }, 657 .hsync_len = { 32, 32, 32 }, 658 .vactive = { 800, 800, 800 }, 659 .vfront_porch = { 4, 4, 4 }, 660 .vback_porch = { 8, 8, 8 }, 661 .vsync_len = { 18, 20, 20 }, 662 }; 663 664 static const struct panel_desc auo_b101ean01 = { 665 .timings = &auo_b101ean01_timing, 666 .num_timings = 1, 667 .bpc = 6, 668 .size = { 669 .width = 217, 670 .height = 136, 671 }, 672 }; 673 674 static const struct drm_display_mode auo_b101xtn01_mode = { 675 .clock = 72000, 676 .hdisplay = 1366, 677 .hsync_start = 1366 + 20, 678 .hsync_end = 1366 + 20 + 70, 679 .htotal = 1366 + 20 + 70, 680 .vdisplay = 768, 681 .vsync_start = 768 + 14, 682 .vsync_end = 768 + 14 + 42, 683 .vtotal = 768 + 14 + 42, 684 .vrefresh = 60, 685 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 686 }; 687 688 static const struct panel_desc auo_b101xtn01 = { 689 .modes = &auo_b101xtn01_mode, 690 .num_modes = 1, 691 .bpc = 6, 692 .size = { 693 .width = 223, 694 .height = 125, 695 }, 696 }; 697 698 static const struct drm_display_mode auo_b116xak01_mode = { 699 .clock = 69300, 700 .hdisplay = 1366, 701 .hsync_start = 1366 + 48, 702 .hsync_end = 1366 + 48 + 32, 703 .htotal = 1366 + 48 + 32 + 10, 704 .vdisplay = 768, 705 .vsync_start = 768 + 4, 706 .vsync_end = 768 + 4 + 6, 707 .vtotal = 768 + 4 + 6 + 15, 708 .vrefresh = 60, 709 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 710 }; 711 712 static const struct panel_desc auo_b116xak01 = { 713 .modes = &auo_b116xak01_mode, 714 .num_modes = 1, 715 .bpc = 6, 716 .size = { 717 .width = 256, 718 .height = 144, 719 }, 720 .delay = { 721 .hpd_absent_delay = 200, 722 }, 723 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 724 .connector_type = DRM_MODE_CONNECTOR_eDP, 725 }; 726 727 static const struct drm_display_mode auo_b116xw03_mode = { 728 .clock = 70589, 729 .hdisplay = 1366, 730 .hsync_start = 1366 + 40, 731 .hsync_end = 1366 + 40 + 40, 732 .htotal = 1366 + 40 + 40 + 32, 733 .vdisplay = 768, 734 .vsync_start = 768 + 10, 735 .vsync_end = 768 + 10 + 12, 736 .vtotal = 768 + 10 + 12 + 6, 737 .vrefresh = 60, 738 }; 739 740 static const struct panel_desc auo_b116xw03 = { 741 .modes = &auo_b116xw03_mode, 742 .num_modes = 1, 743 .bpc = 6, 744 .size = { 745 .width = 256, 746 .height = 144, 747 }, 748 }; 749 750 static const struct drm_display_mode auo_b133xtn01_mode = { 751 .clock = 69500, 752 .hdisplay = 1366, 753 .hsync_start = 1366 + 48, 754 .hsync_end = 1366 + 48 + 32, 755 .htotal = 1366 + 48 + 32 + 20, 756 .vdisplay = 768, 757 .vsync_start = 768 + 3, 758 .vsync_end = 768 + 3 + 6, 759 .vtotal = 768 + 3 + 6 + 13, 760 .vrefresh = 60, 761 }; 762 763 static const struct panel_desc auo_b133xtn01 = { 764 .modes = &auo_b133xtn01_mode, 765 .num_modes = 1, 766 .bpc = 6, 767 .size = { 768 .width = 293, 769 .height = 165, 770 }, 771 }; 772 773 static const struct drm_display_mode auo_b133htn01_mode = { 774 .clock = 150660, 775 .hdisplay = 1920, 776 .hsync_start = 1920 + 172, 777 .hsync_end = 1920 + 172 + 80, 778 .htotal = 1920 + 172 + 80 + 60, 779 .vdisplay = 1080, 780 .vsync_start = 1080 + 25, 781 .vsync_end = 1080 + 25 + 10, 782 .vtotal = 1080 + 25 + 10 + 10, 783 .vrefresh = 60, 784 }; 785 786 static const struct panel_desc auo_b133htn01 = { 787 .modes = &auo_b133htn01_mode, 788 .num_modes = 1, 789 .bpc = 6, 790 .size = { 791 .width = 293, 792 .height = 165, 793 }, 794 .delay = { 795 .prepare = 105, 796 .enable = 20, 797 .unprepare = 50, 798 }, 799 }; 800 801 static const struct display_timing auo_g070vvn01_timings = { 802 .pixelclock = { 33300000, 34209000, 45000000 }, 803 .hactive = { 800, 800, 800 }, 804 .hfront_porch = { 20, 40, 200 }, 805 .hback_porch = { 87, 40, 1 }, 806 .hsync_len = { 1, 48, 87 }, 807 .vactive = { 480, 480, 480 }, 808 .vfront_porch = { 5, 13, 200 }, 809 .vback_porch = { 31, 31, 29 }, 810 .vsync_len = { 1, 1, 3 }, 811 }; 812 813 static const struct panel_desc auo_g070vvn01 = { 814 .timings = &auo_g070vvn01_timings, 815 .num_timings = 1, 816 .bpc = 8, 817 .size = { 818 .width = 152, 819 .height = 91, 820 }, 821 .delay = { 822 .prepare = 200, 823 .enable = 50, 824 .disable = 50, 825 .unprepare = 1000, 826 }, 827 }; 828 829 static const struct drm_display_mode auo_g101evn010_mode = { 830 .clock = 68930, 831 .hdisplay = 1280, 832 .hsync_start = 1280 + 82, 833 .hsync_end = 1280 + 82 + 2, 834 .htotal = 1280 + 82 + 2 + 84, 835 .vdisplay = 800, 836 .vsync_start = 800 + 8, 837 .vsync_end = 800 + 8 + 2, 838 .vtotal = 800 + 8 + 2 + 6, 839 .vrefresh = 60, 840 }; 841 842 static const struct panel_desc auo_g101evn010 = { 843 .modes = &auo_g101evn010_mode, 844 .num_modes = 1, 845 .bpc = 6, 846 .size = { 847 .width = 216, 848 .height = 135, 849 }, 850 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 851 }; 852 853 static const struct drm_display_mode auo_g104sn02_mode = { 854 .clock = 40000, 855 .hdisplay = 800, 856 .hsync_start = 800 + 40, 857 .hsync_end = 800 + 40 + 216, 858 .htotal = 800 + 40 + 216 + 128, 859 .vdisplay = 600, 860 .vsync_start = 600 + 10, 861 .vsync_end = 600 + 10 + 35, 862 .vtotal = 600 + 10 + 35 + 2, 863 .vrefresh = 60, 864 }; 865 866 static const struct panel_desc auo_g104sn02 = { 867 .modes = &auo_g104sn02_mode, 868 .num_modes = 1, 869 .bpc = 8, 870 .size = { 871 .width = 211, 872 .height = 158, 873 }, 874 }; 875 876 static const struct display_timing auo_g133han01_timings = { 877 .pixelclock = { 134000000, 141200000, 149000000 }, 878 .hactive = { 1920, 1920, 1920 }, 879 .hfront_porch = { 39, 58, 77 }, 880 .hback_porch = { 59, 88, 117 }, 881 .hsync_len = { 28, 42, 56 }, 882 .vactive = { 1080, 1080, 1080 }, 883 .vfront_porch = { 3, 8, 11 }, 884 .vback_porch = { 5, 14, 19 }, 885 .vsync_len = { 4, 14, 19 }, 886 }; 887 888 static const struct panel_desc auo_g133han01 = { 889 .timings = &auo_g133han01_timings, 890 .num_timings = 1, 891 .bpc = 8, 892 .size = { 893 .width = 293, 894 .height = 165, 895 }, 896 .delay = { 897 .prepare = 200, 898 .enable = 50, 899 .disable = 50, 900 .unprepare = 1000, 901 }, 902 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 903 .connector_type = DRM_MODE_CONNECTOR_LVDS, 904 }; 905 906 static const struct display_timing auo_g185han01_timings = { 907 .pixelclock = { 120000000, 144000000, 175000000 }, 908 .hactive = { 1920, 1920, 1920 }, 909 .hfront_porch = { 36, 120, 148 }, 910 .hback_porch = { 24, 88, 108 }, 911 .hsync_len = { 20, 48, 64 }, 912 .vactive = { 1080, 1080, 1080 }, 913 .vfront_porch = { 6, 10, 40 }, 914 .vback_porch = { 2, 5, 20 }, 915 .vsync_len = { 2, 5, 20 }, 916 }; 917 918 static const struct panel_desc auo_g185han01 = { 919 .timings = &auo_g185han01_timings, 920 .num_timings = 1, 921 .bpc = 8, 922 .size = { 923 .width = 409, 924 .height = 230, 925 }, 926 .delay = { 927 .prepare = 50, 928 .enable = 200, 929 .disable = 110, 930 .unprepare = 1000, 931 }, 932 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 933 .connector_type = DRM_MODE_CONNECTOR_LVDS, 934 }; 935 936 static const struct display_timing auo_p320hvn03_timings = { 937 .pixelclock = { 106000000, 148500000, 164000000 }, 938 .hactive = { 1920, 1920, 1920 }, 939 .hfront_porch = { 25, 50, 130 }, 940 .hback_porch = { 25, 50, 130 }, 941 .hsync_len = { 20, 40, 105 }, 942 .vactive = { 1080, 1080, 1080 }, 943 .vfront_porch = { 8, 17, 150 }, 944 .vback_porch = { 8, 17, 150 }, 945 .vsync_len = { 4, 11, 100 }, 946 }; 947 948 static const struct panel_desc auo_p320hvn03 = { 949 .timings = &auo_p320hvn03_timings, 950 .num_timings = 1, 951 .bpc = 8, 952 .size = { 953 .width = 698, 954 .height = 393, 955 }, 956 .delay = { 957 .prepare = 1, 958 .enable = 450, 959 .unprepare = 500, 960 }, 961 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 962 .connector_type = DRM_MODE_CONNECTOR_LVDS, 963 }; 964 965 static const struct drm_display_mode auo_t215hvn01_mode = { 966 .clock = 148800, 967 .hdisplay = 1920, 968 .hsync_start = 1920 + 88, 969 .hsync_end = 1920 + 88 + 44, 970 .htotal = 1920 + 88 + 44 + 148, 971 .vdisplay = 1080, 972 .vsync_start = 1080 + 4, 973 .vsync_end = 1080 + 4 + 5, 974 .vtotal = 1080 + 4 + 5 + 36, 975 .vrefresh = 60, 976 }; 977 978 static const struct panel_desc auo_t215hvn01 = { 979 .modes = &auo_t215hvn01_mode, 980 .num_modes = 1, 981 .bpc = 8, 982 .size = { 983 .width = 430, 984 .height = 270, 985 }, 986 .delay = { 987 .disable = 5, 988 .unprepare = 1000, 989 } 990 }; 991 992 static const struct drm_display_mode avic_tm070ddh03_mode = { 993 .clock = 51200, 994 .hdisplay = 1024, 995 .hsync_start = 1024 + 160, 996 .hsync_end = 1024 + 160 + 4, 997 .htotal = 1024 + 160 + 4 + 156, 998 .vdisplay = 600, 999 .vsync_start = 600 + 17, 1000 .vsync_end = 600 + 17 + 1, 1001 .vtotal = 600 + 17 + 1 + 17, 1002 .vrefresh = 60, 1003 }; 1004 1005 static const struct panel_desc avic_tm070ddh03 = { 1006 .modes = &avic_tm070ddh03_mode, 1007 .num_modes = 1, 1008 .bpc = 8, 1009 .size = { 1010 .width = 154, 1011 .height = 90, 1012 }, 1013 .delay = { 1014 .prepare = 20, 1015 .enable = 200, 1016 .disable = 200, 1017 }, 1018 }; 1019 1020 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1021 .clock = 30000, 1022 .hdisplay = 800, 1023 .hsync_start = 800 + 40, 1024 .hsync_end = 800 + 40 + 48, 1025 .htotal = 800 + 40 + 48 + 40, 1026 .vdisplay = 480, 1027 .vsync_start = 480 + 13, 1028 .vsync_end = 480 + 13 + 3, 1029 .vtotal = 480 + 13 + 3 + 29, 1030 }; 1031 1032 static const struct panel_desc bananapi_s070wv20_ct16 = { 1033 .modes = &bananapi_s070wv20_ct16_mode, 1034 .num_modes = 1, 1035 .bpc = 6, 1036 .size = { 1037 .width = 154, 1038 .height = 86, 1039 }, 1040 }; 1041 1042 static const struct drm_display_mode boe_hv070wsa_mode = { 1043 .clock = 42105, 1044 .hdisplay = 1024, 1045 .hsync_start = 1024 + 30, 1046 .hsync_end = 1024 + 30 + 30, 1047 .htotal = 1024 + 30 + 30 + 30, 1048 .vdisplay = 600, 1049 .vsync_start = 600 + 10, 1050 .vsync_end = 600 + 10 + 10, 1051 .vtotal = 600 + 10 + 10 + 10, 1052 .vrefresh = 60, 1053 }; 1054 1055 static const struct panel_desc boe_hv070wsa = { 1056 .modes = &boe_hv070wsa_mode, 1057 .num_modes = 1, 1058 .size = { 1059 .width = 154, 1060 .height = 90, 1061 }, 1062 }; 1063 1064 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1065 { 1066 .clock = 71900, 1067 .hdisplay = 1280, 1068 .hsync_start = 1280 + 48, 1069 .hsync_end = 1280 + 48 + 32, 1070 .htotal = 1280 + 48 + 32 + 80, 1071 .vdisplay = 800, 1072 .vsync_start = 800 + 3, 1073 .vsync_end = 800 + 3 + 5, 1074 .vtotal = 800 + 3 + 5 + 24, 1075 .vrefresh = 60, 1076 }, 1077 { 1078 .clock = 57500, 1079 .hdisplay = 1280, 1080 .hsync_start = 1280 + 48, 1081 .hsync_end = 1280 + 48 + 32, 1082 .htotal = 1280 + 48 + 32 + 80, 1083 .vdisplay = 800, 1084 .vsync_start = 800 + 3, 1085 .vsync_end = 800 + 3 + 5, 1086 .vtotal = 800 + 3 + 5 + 24, 1087 .vrefresh = 48, 1088 }, 1089 }; 1090 1091 static const struct panel_desc boe_nv101wxmn51 = { 1092 .modes = boe_nv101wxmn51_modes, 1093 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1094 .bpc = 8, 1095 .size = { 1096 .width = 217, 1097 .height = 136, 1098 }, 1099 .delay = { 1100 .prepare = 210, 1101 .enable = 50, 1102 .unprepare = 160, 1103 }, 1104 }; 1105 1106 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1107 { 1108 .clock = 148500, 1109 .hdisplay = 1920, 1110 .hsync_start = 1920 + 48, 1111 .hsync_end = 1920 + 48 + 32, 1112 .htotal = 2200, 1113 .vdisplay = 1080, 1114 .vsync_start = 1080 + 3, 1115 .vsync_end = 1080 + 3 + 5, 1116 .vtotal = 1125, 1117 .vrefresh = 60, 1118 }, 1119 }; 1120 1121 static const struct panel_desc boe_nv140fhmn49 = { 1122 .modes = boe_nv140fhmn49_modes, 1123 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1124 .bpc = 6, 1125 .size = { 1126 .width = 309, 1127 .height = 174, 1128 }, 1129 .delay = { 1130 .prepare = 210, 1131 .enable = 50, 1132 .unprepare = 160, 1133 }, 1134 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1135 .connector_type = DRM_MODE_CONNECTOR_eDP, 1136 }; 1137 1138 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1139 .clock = 9000, 1140 .hdisplay = 480, 1141 .hsync_start = 480 + 5, 1142 .hsync_end = 480 + 5 + 5, 1143 .htotal = 480 + 5 + 5 + 40, 1144 .vdisplay = 272, 1145 .vsync_start = 272 + 8, 1146 .vsync_end = 272 + 8 + 8, 1147 .vtotal = 272 + 8 + 8 + 8, 1148 .vrefresh = 60, 1149 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1150 }; 1151 1152 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1153 .modes = &cdtech_s043wq26h_ct7_mode, 1154 .num_modes = 1, 1155 .bpc = 8, 1156 .size = { 1157 .width = 95, 1158 .height = 54, 1159 }, 1160 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1161 }; 1162 1163 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1164 .clock = 35000, 1165 .hdisplay = 800, 1166 .hsync_start = 800 + 40, 1167 .hsync_end = 800 + 40 + 40, 1168 .htotal = 800 + 40 + 40 + 48, 1169 .vdisplay = 480, 1170 .vsync_start = 480 + 29, 1171 .vsync_end = 480 + 29 + 13, 1172 .vtotal = 480 + 29 + 13 + 3, 1173 .vrefresh = 60, 1174 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1175 }; 1176 1177 static const struct panel_desc cdtech_s070wv95_ct16 = { 1178 .modes = &cdtech_s070wv95_ct16_mode, 1179 .num_modes = 1, 1180 .bpc = 8, 1181 .size = { 1182 .width = 154, 1183 .height = 85, 1184 }, 1185 }; 1186 1187 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1188 .clock = 66770, 1189 .hdisplay = 800, 1190 .hsync_start = 800 + 49, 1191 .hsync_end = 800 + 49 + 33, 1192 .htotal = 800 + 49 + 33 + 17, 1193 .vdisplay = 1280, 1194 .vsync_start = 1280 + 1, 1195 .vsync_end = 1280 + 1 + 7, 1196 .vtotal = 1280 + 1 + 7 + 15, 1197 .vrefresh = 60, 1198 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1199 }; 1200 1201 static const struct panel_desc chunghwa_claa070wp03xg = { 1202 .modes = &chunghwa_claa070wp03xg_mode, 1203 .num_modes = 1, 1204 .bpc = 6, 1205 .size = { 1206 .width = 94, 1207 .height = 150, 1208 }, 1209 }; 1210 1211 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1212 .clock = 72070, 1213 .hdisplay = 1366, 1214 .hsync_start = 1366 + 58, 1215 .hsync_end = 1366 + 58 + 58, 1216 .htotal = 1366 + 58 + 58 + 58, 1217 .vdisplay = 768, 1218 .vsync_start = 768 + 4, 1219 .vsync_end = 768 + 4 + 4, 1220 .vtotal = 768 + 4 + 4 + 4, 1221 .vrefresh = 60, 1222 }; 1223 1224 static const struct panel_desc chunghwa_claa101wa01a = { 1225 .modes = &chunghwa_claa101wa01a_mode, 1226 .num_modes = 1, 1227 .bpc = 6, 1228 .size = { 1229 .width = 220, 1230 .height = 120, 1231 }, 1232 }; 1233 1234 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1235 .clock = 69300, 1236 .hdisplay = 1366, 1237 .hsync_start = 1366 + 48, 1238 .hsync_end = 1366 + 48 + 32, 1239 .htotal = 1366 + 48 + 32 + 20, 1240 .vdisplay = 768, 1241 .vsync_start = 768 + 16, 1242 .vsync_end = 768 + 16 + 8, 1243 .vtotal = 768 + 16 + 8 + 16, 1244 .vrefresh = 60, 1245 }; 1246 1247 static const struct panel_desc chunghwa_claa101wb01 = { 1248 .modes = &chunghwa_claa101wb01_mode, 1249 .num_modes = 1, 1250 .bpc = 6, 1251 .size = { 1252 .width = 223, 1253 .height = 125, 1254 }, 1255 }; 1256 1257 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1258 .clock = 33260, 1259 .hdisplay = 800, 1260 .hsync_start = 800 + 40, 1261 .hsync_end = 800 + 40 + 128, 1262 .htotal = 800 + 40 + 128 + 88, 1263 .vdisplay = 480, 1264 .vsync_start = 480 + 10, 1265 .vsync_end = 480 + 10 + 2, 1266 .vtotal = 480 + 10 + 2 + 33, 1267 .vrefresh = 60, 1268 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1269 }; 1270 1271 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1272 .modes = &dataimage_scf0700c48ggu18_mode, 1273 .num_modes = 1, 1274 .bpc = 8, 1275 .size = { 1276 .width = 152, 1277 .height = 91, 1278 }, 1279 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1280 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1281 }; 1282 1283 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1284 .pixelclock = { 45000000, 51200000, 57000000 }, 1285 .hactive = { 1024, 1024, 1024 }, 1286 .hfront_porch = { 100, 106, 113 }, 1287 .hback_porch = { 100, 106, 113 }, 1288 .hsync_len = { 100, 108, 114 }, 1289 .vactive = { 600, 600, 600 }, 1290 .vfront_porch = { 8, 11, 15 }, 1291 .vback_porch = { 8, 11, 15 }, 1292 .vsync_len = { 9, 13, 15 }, 1293 .flags = DISPLAY_FLAGS_DE_HIGH, 1294 }; 1295 1296 static const struct panel_desc dlc_dlc0700yzg_1 = { 1297 .timings = &dlc_dlc0700yzg_1_timing, 1298 .num_timings = 1, 1299 .bpc = 6, 1300 .size = { 1301 .width = 154, 1302 .height = 86, 1303 }, 1304 .delay = { 1305 .prepare = 30, 1306 .enable = 200, 1307 .disable = 200, 1308 }, 1309 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1310 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1311 }; 1312 1313 static const struct display_timing dlc_dlc1010gig_timing = { 1314 .pixelclock = { 68900000, 71100000, 73400000 }, 1315 .hactive = { 1280, 1280, 1280 }, 1316 .hfront_porch = { 43, 53, 63 }, 1317 .hback_porch = { 43, 53, 63 }, 1318 .hsync_len = { 44, 54, 64 }, 1319 .vactive = { 800, 800, 800 }, 1320 .vfront_porch = { 5, 8, 11 }, 1321 .vback_porch = { 5, 8, 11 }, 1322 .vsync_len = { 5, 7, 11 }, 1323 .flags = DISPLAY_FLAGS_DE_HIGH, 1324 }; 1325 1326 static const struct panel_desc dlc_dlc1010gig = { 1327 .timings = &dlc_dlc1010gig_timing, 1328 .num_timings = 1, 1329 .bpc = 8, 1330 .size = { 1331 .width = 216, 1332 .height = 135, 1333 }, 1334 .delay = { 1335 .prepare = 60, 1336 .enable = 150, 1337 .disable = 100, 1338 .unprepare = 60, 1339 }, 1340 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1341 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1342 }; 1343 1344 static const struct drm_display_mode edt_et035012dm6_mode = { 1345 .clock = 6500, 1346 .hdisplay = 320, 1347 .hsync_start = 320 + 20, 1348 .hsync_end = 320 + 20 + 30, 1349 .htotal = 320 + 20 + 68, 1350 .vdisplay = 240, 1351 .vsync_start = 240 + 4, 1352 .vsync_end = 240 + 4 + 4, 1353 .vtotal = 240 + 4 + 4 + 14, 1354 .vrefresh = 60, 1355 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1356 }; 1357 1358 static const struct panel_desc edt_et035012dm6 = { 1359 .modes = &edt_et035012dm6_mode, 1360 .num_modes = 1, 1361 .bpc = 8, 1362 .size = { 1363 .width = 70, 1364 .height = 52, 1365 }, 1366 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1367 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1368 }; 1369 1370 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1371 .clock = 10870, 1372 .hdisplay = 480, 1373 .hsync_start = 480 + 8, 1374 .hsync_end = 480 + 8 + 4, 1375 .htotal = 480 + 8 + 4 + 41, 1376 1377 /* 1378 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1379 * fb_align 1380 */ 1381 1382 .vdisplay = 288, 1383 .vsync_start = 288 + 2, 1384 .vsync_end = 288 + 2 + 4, 1385 .vtotal = 288 + 2 + 4 + 10, 1386 .vrefresh = 60, 1387 }; 1388 1389 static const struct panel_desc edt_etm043080dh6gp = { 1390 .modes = &edt_etm043080dh6gp_mode, 1391 .num_modes = 1, 1392 .bpc = 8, 1393 .size = { 1394 .width = 100, 1395 .height = 65, 1396 }, 1397 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1398 .connector_type = DRM_MODE_CONNECTOR_DPI, 1399 }; 1400 1401 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1402 .clock = 9000, 1403 .hdisplay = 480, 1404 .hsync_start = 480 + 2, 1405 .hsync_end = 480 + 2 + 41, 1406 .htotal = 480 + 2 + 41 + 2, 1407 .vdisplay = 272, 1408 .vsync_start = 272 + 2, 1409 .vsync_end = 272 + 2 + 10, 1410 .vtotal = 272 + 2 + 10 + 2, 1411 .vrefresh = 60, 1412 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1413 }; 1414 1415 static const struct panel_desc edt_etm0430g0dh6 = { 1416 .modes = &edt_etm0430g0dh6_mode, 1417 .num_modes = 1, 1418 .bpc = 6, 1419 .size = { 1420 .width = 95, 1421 .height = 54, 1422 }, 1423 }; 1424 1425 static const struct drm_display_mode edt_et057090dhu_mode = { 1426 .clock = 25175, 1427 .hdisplay = 640, 1428 .hsync_start = 640 + 16, 1429 .hsync_end = 640 + 16 + 30, 1430 .htotal = 640 + 16 + 30 + 114, 1431 .vdisplay = 480, 1432 .vsync_start = 480 + 10, 1433 .vsync_end = 480 + 10 + 3, 1434 .vtotal = 480 + 10 + 3 + 32, 1435 .vrefresh = 60, 1436 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1437 }; 1438 1439 static const struct panel_desc edt_et057090dhu = { 1440 .modes = &edt_et057090dhu_mode, 1441 .num_modes = 1, 1442 .bpc = 6, 1443 .size = { 1444 .width = 115, 1445 .height = 86, 1446 }, 1447 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1448 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1449 }; 1450 1451 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1452 .clock = 33260, 1453 .hdisplay = 800, 1454 .hsync_start = 800 + 40, 1455 .hsync_end = 800 + 40 + 128, 1456 .htotal = 800 + 40 + 128 + 88, 1457 .vdisplay = 480, 1458 .vsync_start = 480 + 10, 1459 .vsync_end = 480 + 10 + 2, 1460 .vtotal = 480 + 10 + 2 + 33, 1461 .vrefresh = 60, 1462 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1463 }; 1464 1465 static const struct panel_desc edt_etm0700g0dh6 = { 1466 .modes = &edt_etm0700g0dh6_mode, 1467 .num_modes = 1, 1468 .bpc = 6, 1469 .size = { 1470 .width = 152, 1471 .height = 91, 1472 }, 1473 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1474 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1475 }; 1476 1477 static const struct panel_desc edt_etm0700g0bdh6 = { 1478 .modes = &edt_etm0700g0dh6_mode, 1479 .num_modes = 1, 1480 .bpc = 6, 1481 .size = { 1482 .width = 152, 1483 .height = 91, 1484 }, 1485 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1486 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1487 }; 1488 1489 static const struct display_timing evervision_vgg804821_timing = { 1490 .pixelclock = { 27600000, 33300000, 50000000 }, 1491 .hactive = { 800, 800, 800 }, 1492 .hfront_porch = { 40, 66, 70 }, 1493 .hback_porch = { 40, 67, 70 }, 1494 .hsync_len = { 40, 67, 70 }, 1495 .vactive = { 480, 480, 480 }, 1496 .vfront_porch = { 6, 10, 10 }, 1497 .vback_porch = { 7, 11, 11 }, 1498 .vsync_len = { 7, 11, 11 }, 1499 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1500 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1501 DISPLAY_FLAGS_SYNC_NEGEDGE, 1502 }; 1503 1504 static const struct panel_desc evervision_vgg804821 = { 1505 .timings = &evervision_vgg804821_timing, 1506 .num_timings = 1, 1507 .bpc = 8, 1508 .size = { 1509 .width = 108, 1510 .height = 64, 1511 }, 1512 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1513 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1514 }; 1515 1516 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1517 .clock = 32260, 1518 .hdisplay = 800, 1519 .hsync_start = 800 + 168, 1520 .hsync_end = 800 + 168 + 64, 1521 .htotal = 800 + 168 + 64 + 88, 1522 .vdisplay = 480, 1523 .vsync_start = 480 + 37, 1524 .vsync_end = 480 + 37 + 2, 1525 .vtotal = 480 + 37 + 2 + 8, 1526 .vrefresh = 60, 1527 }; 1528 1529 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1530 .modes = &foxlink_fl500wvr00_a0t_mode, 1531 .num_modes = 1, 1532 .bpc = 8, 1533 .size = { 1534 .width = 108, 1535 .height = 65, 1536 }, 1537 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1538 }; 1539 1540 static const struct drm_display_mode frida_frd350h54004_mode = { 1541 .clock = 6000, 1542 .hdisplay = 320, 1543 .hsync_start = 320 + 44, 1544 .hsync_end = 320 + 44 + 16, 1545 .htotal = 320 + 44 + 16 + 20, 1546 .vdisplay = 240, 1547 .vsync_start = 240 + 2, 1548 .vsync_end = 240 + 2 + 6, 1549 .vtotal = 240 + 2 + 6 + 2, 1550 .vrefresh = 60, 1551 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1552 }; 1553 1554 static const struct panel_desc frida_frd350h54004 = { 1555 .modes = &frida_frd350h54004_mode, 1556 .num_modes = 1, 1557 .bpc = 8, 1558 .size = { 1559 .width = 77, 1560 .height = 64, 1561 }, 1562 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1563 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1564 .connector_type = DRM_MODE_CONNECTOR_DPI, 1565 }; 1566 1567 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1568 .clock = 67185, 1569 .hdisplay = 800, 1570 .hsync_start = 800 + 20, 1571 .hsync_end = 800 + 20 + 24, 1572 .htotal = 800 + 20 + 24 + 20, 1573 .vdisplay = 1280, 1574 .vsync_start = 1280 + 4, 1575 .vsync_end = 1280 + 4 + 8, 1576 .vtotal = 1280 + 4 + 8 + 4, 1577 .vrefresh = 60, 1578 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1579 }; 1580 1581 static const struct panel_desc friendlyarm_hd702e = { 1582 .modes = &friendlyarm_hd702e_mode, 1583 .num_modes = 1, 1584 .size = { 1585 .width = 94, 1586 .height = 151, 1587 }, 1588 }; 1589 1590 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1591 .clock = 9000, 1592 .hdisplay = 480, 1593 .hsync_start = 480 + 5, 1594 .hsync_end = 480 + 5 + 1, 1595 .htotal = 480 + 5 + 1 + 40, 1596 .vdisplay = 272, 1597 .vsync_start = 272 + 8, 1598 .vsync_end = 272 + 8 + 1, 1599 .vtotal = 272 + 8 + 1 + 8, 1600 .vrefresh = 60, 1601 }; 1602 1603 static const struct panel_desc giantplus_gpg482739qs5 = { 1604 .modes = &giantplus_gpg482739qs5_mode, 1605 .num_modes = 1, 1606 .bpc = 8, 1607 .size = { 1608 .width = 95, 1609 .height = 54, 1610 }, 1611 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1612 }; 1613 1614 static const struct display_timing giantplus_gpm940b0_timing = { 1615 .pixelclock = { 13500000, 27000000, 27500000 }, 1616 .hactive = { 320, 320, 320 }, 1617 .hfront_porch = { 14, 686, 718 }, 1618 .hback_porch = { 50, 70, 255 }, 1619 .hsync_len = { 1, 1, 1 }, 1620 .vactive = { 240, 240, 240 }, 1621 .vfront_porch = { 1, 1, 179 }, 1622 .vback_porch = { 1, 21, 31 }, 1623 .vsync_len = { 1, 1, 6 }, 1624 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1625 }; 1626 1627 static const struct panel_desc giantplus_gpm940b0 = { 1628 .timings = &giantplus_gpm940b0_timing, 1629 .num_timings = 1, 1630 .bpc = 8, 1631 .size = { 1632 .width = 60, 1633 .height = 45, 1634 }, 1635 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1636 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1637 }; 1638 1639 static const struct display_timing hannstar_hsd070pww1_timing = { 1640 .pixelclock = { 64300000, 71100000, 82000000 }, 1641 .hactive = { 1280, 1280, 1280 }, 1642 .hfront_porch = { 1, 1, 10 }, 1643 .hback_porch = { 1, 1, 10 }, 1644 /* 1645 * According to the data sheet, the minimum horizontal blanking interval 1646 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1647 * minimum working horizontal blanking interval to be 60 clocks. 1648 */ 1649 .hsync_len = { 58, 158, 661 }, 1650 .vactive = { 800, 800, 800 }, 1651 .vfront_porch = { 1, 1, 10 }, 1652 .vback_porch = { 1, 1, 10 }, 1653 .vsync_len = { 1, 21, 203 }, 1654 .flags = DISPLAY_FLAGS_DE_HIGH, 1655 }; 1656 1657 static const struct panel_desc hannstar_hsd070pww1 = { 1658 .timings = &hannstar_hsd070pww1_timing, 1659 .num_timings = 1, 1660 .bpc = 6, 1661 .size = { 1662 .width = 151, 1663 .height = 94, 1664 }, 1665 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1666 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1667 }; 1668 1669 static const struct display_timing hannstar_hsd100pxn1_timing = { 1670 .pixelclock = { 55000000, 65000000, 75000000 }, 1671 .hactive = { 1024, 1024, 1024 }, 1672 .hfront_porch = { 40, 40, 40 }, 1673 .hback_porch = { 220, 220, 220 }, 1674 .hsync_len = { 20, 60, 100 }, 1675 .vactive = { 768, 768, 768 }, 1676 .vfront_porch = { 7, 7, 7 }, 1677 .vback_porch = { 21, 21, 21 }, 1678 .vsync_len = { 10, 10, 10 }, 1679 .flags = DISPLAY_FLAGS_DE_HIGH, 1680 }; 1681 1682 static const struct panel_desc hannstar_hsd100pxn1 = { 1683 .timings = &hannstar_hsd100pxn1_timing, 1684 .num_timings = 1, 1685 .bpc = 6, 1686 .size = { 1687 .width = 203, 1688 .height = 152, 1689 }, 1690 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1691 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1692 }; 1693 1694 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1695 .clock = 33333, 1696 .hdisplay = 800, 1697 .hsync_start = 800 + 85, 1698 .hsync_end = 800 + 85 + 86, 1699 .htotal = 800 + 85 + 86 + 85, 1700 .vdisplay = 480, 1701 .vsync_start = 480 + 16, 1702 .vsync_end = 480 + 16 + 13, 1703 .vtotal = 480 + 16 + 13 + 16, 1704 .vrefresh = 60, 1705 }; 1706 1707 static const struct panel_desc hitachi_tx23d38vm0caa = { 1708 .modes = &hitachi_tx23d38vm0caa_mode, 1709 .num_modes = 1, 1710 .bpc = 6, 1711 .size = { 1712 .width = 195, 1713 .height = 117, 1714 }, 1715 .delay = { 1716 .enable = 160, 1717 .disable = 160, 1718 }, 1719 }; 1720 1721 static const struct drm_display_mode innolux_at043tn24_mode = { 1722 .clock = 9000, 1723 .hdisplay = 480, 1724 .hsync_start = 480 + 2, 1725 .hsync_end = 480 + 2 + 41, 1726 .htotal = 480 + 2 + 41 + 2, 1727 .vdisplay = 272, 1728 .vsync_start = 272 + 2, 1729 .vsync_end = 272 + 2 + 10, 1730 .vtotal = 272 + 2 + 10 + 2, 1731 .vrefresh = 60, 1732 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1733 }; 1734 1735 static const struct panel_desc innolux_at043tn24 = { 1736 .modes = &innolux_at043tn24_mode, 1737 .num_modes = 1, 1738 .bpc = 8, 1739 .size = { 1740 .width = 95, 1741 .height = 54, 1742 }, 1743 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1744 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1745 }; 1746 1747 static const struct drm_display_mode innolux_at070tn92_mode = { 1748 .clock = 33333, 1749 .hdisplay = 800, 1750 .hsync_start = 800 + 210, 1751 .hsync_end = 800 + 210 + 20, 1752 .htotal = 800 + 210 + 20 + 46, 1753 .vdisplay = 480, 1754 .vsync_start = 480 + 22, 1755 .vsync_end = 480 + 22 + 10, 1756 .vtotal = 480 + 22 + 23 + 10, 1757 .vrefresh = 60, 1758 }; 1759 1760 static const struct panel_desc innolux_at070tn92 = { 1761 .modes = &innolux_at070tn92_mode, 1762 .num_modes = 1, 1763 .size = { 1764 .width = 154, 1765 .height = 86, 1766 }, 1767 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1768 }; 1769 1770 static const struct display_timing innolux_g070y2_l01_timing = { 1771 .pixelclock = { 28000000, 29500000, 32000000 }, 1772 .hactive = { 800, 800, 800 }, 1773 .hfront_porch = { 61, 91, 141 }, 1774 .hback_porch = { 60, 90, 140 }, 1775 .hsync_len = { 12, 12, 12 }, 1776 .vactive = { 480, 480, 480 }, 1777 .vfront_porch = { 4, 9, 30 }, 1778 .vback_porch = { 4, 8, 28 }, 1779 .vsync_len = { 2, 2, 2 }, 1780 .flags = DISPLAY_FLAGS_DE_HIGH, 1781 }; 1782 1783 static const struct panel_desc innolux_g070y2_l01 = { 1784 .timings = &innolux_g070y2_l01_timing, 1785 .num_timings = 1, 1786 .bpc = 6, 1787 .size = { 1788 .width = 152, 1789 .height = 91, 1790 }, 1791 .delay = { 1792 .prepare = 10, 1793 .enable = 100, 1794 .disable = 100, 1795 .unprepare = 800, 1796 }, 1797 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1798 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1799 }; 1800 1801 static const struct display_timing innolux_g101ice_l01_timing = { 1802 .pixelclock = { 60400000, 71100000, 74700000 }, 1803 .hactive = { 1280, 1280, 1280 }, 1804 .hfront_porch = { 41, 80, 100 }, 1805 .hback_porch = { 40, 79, 99 }, 1806 .hsync_len = { 1, 1, 1 }, 1807 .vactive = { 800, 800, 800 }, 1808 .vfront_porch = { 5, 11, 14 }, 1809 .vback_porch = { 4, 11, 14 }, 1810 .vsync_len = { 1, 1, 1 }, 1811 .flags = DISPLAY_FLAGS_DE_HIGH, 1812 }; 1813 1814 static const struct panel_desc innolux_g101ice_l01 = { 1815 .timings = &innolux_g101ice_l01_timing, 1816 .num_timings = 1, 1817 .bpc = 8, 1818 .size = { 1819 .width = 217, 1820 .height = 135, 1821 }, 1822 .delay = { 1823 .enable = 200, 1824 .disable = 200, 1825 }, 1826 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1827 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1828 }; 1829 1830 static const struct display_timing innolux_g121i1_l01_timing = { 1831 .pixelclock = { 67450000, 71000000, 74550000 }, 1832 .hactive = { 1280, 1280, 1280 }, 1833 .hfront_porch = { 40, 80, 160 }, 1834 .hback_porch = { 39, 79, 159 }, 1835 .hsync_len = { 1, 1, 1 }, 1836 .vactive = { 800, 800, 800 }, 1837 .vfront_porch = { 5, 11, 100 }, 1838 .vback_porch = { 4, 11, 99 }, 1839 .vsync_len = { 1, 1, 1 }, 1840 }; 1841 1842 static const struct panel_desc innolux_g121i1_l01 = { 1843 .timings = &innolux_g121i1_l01_timing, 1844 .num_timings = 1, 1845 .bpc = 6, 1846 .size = { 1847 .width = 261, 1848 .height = 163, 1849 }, 1850 .delay = { 1851 .enable = 200, 1852 .disable = 20, 1853 }, 1854 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1855 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1856 }; 1857 1858 static const struct drm_display_mode innolux_g121x1_l03_mode = { 1859 .clock = 65000, 1860 .hdisplay = 1024, 1861 .hsync_start = 1024 + 0, 1862 .hsync_end = 1024 + 1, 1863 .htotal = 1024 + 0 + 1 + 320, 1864 .vdisplay = 768, 1865 .vsync_start = 768 + 38, 1866 .vsync_end = 768 + 38 + 1, 1867 .vtotal = 768 + 38 + 1 + 0, 1868 .vrefresh = 60, 1869 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1870 }; 1871 1872 static const struct panel_desc innolux_g121x1_l03 = { 1873 .modes = &innolux_g121x1_l03_mode, 1874 .num_modes = 1, 1875 .bpc = 6, 1876 .size = { 1877 .width = 246, 1878 .height = 185, 1879 }, 1880 .delay = { 1881 .enable = 200, 1882 .unprepare = 200, 1883 .disable = 400, 1884 }, 1885 }; 1886 1887 /* 1888 * Datasheet specifies that at 60 Hz refresh rate: 1889 * - total horizontal time: { 1506, 1592, 1716 } 1890 * - total vertical time: { 788, 800, 868 } 1891 * 1892 * ...but doesn't go into exactly how that should be split into a front 1893 * porch, back porch, or sync length. For now we'll leave a single setting 1894 * here which allows a bit of tweaking of the pixel clock at the expense of 1895 * refresh rate. 1896 */ 1897 static const struct display_timing innolux_n116bge_timing = { 1898 .pixelclock = { 72600000, 76420000, 80240000 }, 1899 .hactive = { 1366, 1366, 1366 }, 1900 .hfront_porch = { 136, 136, 136 }, 1901 .hback_porch = { 60, 60, 60 }, 1902 .hsync_len = { 30, 30, 30 }, 1903 .vactive = { 768, 768, 768 }, 1904 .vfront_porch = { 8, 8, 8 }, 1905 .vback_porch = { 12, 12, 12 }, 1906 .vsync_len = { 12, 12, 12 }, 1907 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 1908 }; 1909 1910 static const struct panel_desc innolux_n116bge = { 1911 .timings = &innolux_n116bge_timing, 1912 .num_timings = 1, 1913 .bpc = 6, 1914 .size = { 1915 .width = 256, 1916 .height = 144, 1917 }, 1918 }; 1919 1920 static const struct drm_display_mode innolux_n156bge_l21_mode = { 1921 .clock = 69300, 1922 .hdisplay = 1366, 1923 .hsync_start = 1366 + 16, 1924 .hsync_end = 1366 + 16 + 34, 1925 .htotal = 1366 + 16 + 34 + 50, 1926 .vdisplay = 768, 1927 .vsync_start = 768 + 2, 1928 .vsync_end = 768 + 2 + 6, 1929 .vtotal = 768 + 2 + 6 + 12, 1930 .vrefresh = 60, 1931 }; 1932 1933 static const struct panel_desc innolux_n156bge_l21 = { 1934 .modes = &innolux_n156bge_l21_mode, 1935 .num_modes = 1, 1936 .bpc = 6, 1937 .size = { 1938 .width = 344, 1939 .height = 193, 1940 }, 1941 }; 1942 1943 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 1944 .clock = 206016, 1945 .hdisplay = 2160, 1946 .hsync_start = 2160 + 48, 1947 .hsync_end = 2160 + 48 + 32, 1948 .htotal = 2160 + 48 + 32 + 80, 1949 .vdisplay = 1440, 1950 .vsync_start = 1440 + 3, 1951 .vsync_end = 1440 + 3 + 10, 1952 .vtotal = 1440 + 3 + 10 + 27, 1953 .vrefresh = 60, 1954 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1955 }; 1956 1957 static const struct panel_desc innolux_p120zdg_bf1 = { 1958 .modes = &innolux_p120zdg_bf1_mode, 1959 .num_modes = 1, 1960 .bpc = 8, 1961 .size = { 1962 .width = 254, 1963 .height = 169, 1964 }, 1965 .delay = { 1966 .hpd_absent_delay = 200, 1967 .unprepare = 500, 1968 }, 1969 }; 1970 1971 static const struct drm_display_mode innolux_zj070na_01p_mode = { 1972 .clock = 51501, 1973 .hdisplay = 1024, 1974 .hsync_start = 1024 + 128, 1975 .hsync_end = 1024 + 128 + 64, 1976 .htotal = 1024 + 128 + 64 + 128, 1977 .vdisplay = 600, 1978 .vsync_start = 600 + 16, 1979 .vsync_end = 600 + 16 + 4, 1980 .vtotal = 600 + 16 + 4 + 16, 1981 .vrefresh = 60, 1982 }; 1983 1984 static const struct panel_desc innolux_zj070na_01p = { 1985 .modes = &innolux_zj070na_01p_mode, 1986 .num_modes = 1, 1987 .bpc = 6, 1988 .size = { 1989 .width = 154, 1990 .height = 90, 1991 }, 1992 }; 1993 1994 static const struct display_timing koe_tx14d24vm1bpa_timing = { 1995 .pixelclock = { 5580000, 5850000, 6200000 }, 1996 .hactive = { 320, 320, 320 }, 1997 .hfront_porch = { 30, 30, 30 }, 1998 .hback_porch = { 30, 30, 30 }, 1999 .hsync_len = { 1, 5, 17 }, 2000 .vactive = { 240, 240, 240 }, 2001 .vfront_porch = { 6, 6, 6 }, 2002 .vback_porch = { 5, 5, 5 }, 2003 .vsync_len = { 1, 2, 11 }, 2004 .flags = DISPLAY_FLAGS_DE_HIGH, 2005 }; 2006 2007 static const struct panel_desc koe_tx14d24vm1bpa = { 2008 .timings = &koe_tx14d24vm1bpa_timing, 2009 .num_timings = 1, 2010 .bpc = 6, 2011 .size = { 2012 .width = 115, 2013 .height = 86, 2014 }, 2015 }; 2016 2017 static const struct display_timing koe_tx31d200vm0baa_timing = { 2018 .pixelclock = { 39600000, 43200000, 48000000 }, 2019 .hactive = { 1280, 1280, 1280 }, 2020 .hfront_porch = { 16, 36, 56 }, 2021 .hback_porch = { 16, 36, 56 }, 2022 .hsync_len = { 8, 8, 8 }, 2023 .vactive = { 480, 480, 480 }, 2024 .vfront_porch = { 6, 21, 33 }, 2025 .vback_porch = { 6, 21, 33 }, 2026 .vsync_len = { 8, 8, 8 }, 2027 .flags = DISPLAY_FLAGS_DE_HIGH, 2028 }; 2029 2030 static const struct panel_desc koe_tx31d200vm0baa = { 2031 .timings = &koe_tx31d200vm0baa_timing, 2032 .num_timings = 1, 2033 .bpc = 6, 2034 .size = { 2035 .width = 292, 2036 .height = 109, 2037 }, 2038 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2039 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2040 }; 2041 2042 static const struct display_timing kyo_tcg121xglp_timing = { 2043 .pixelclock = { 52000000, 65000000, 71000000 }, 2044 .hactive = { 1024, 1024, 1024 }, 2045 .hfront_porch = { 2, 2, 2 }, 2046 .hback_porch = { 2, 2, 2 }, 2047 .hsync_len = { 86, 124, 244 }, 2048 .vactive = { 768, 768, 768 }, 2049 .vfront_porch = { 2, 2, 2 }, 2050 .vback_porch = { 2, 2, 2 }, 2051 .vsync_len = { 6, 34, 73 }, 2052 .flags = DISPLAY_FLAGS_DE_HIGH, 2053 }; 2054 2055 static const struct panel_desc kyo_tcg121xglp = { 2056 .timings = &kyo_tcg121xglp_timing, 2057 .num_timings = 1, 2058 .bpc = 8, 2059 .size = { 2060 .width = 246, 2061 .height = 184, 2062 }, 2063 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2064 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2065 }; 2066 2067 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2068 .clock = 7000, 2069 .hdisplay = 320, 2070 .hsync_start = 320 + 20, 2071 .hsync_end = 320 + 20 + 30, 2072 .htotal = 320 + 20 + 30 + 38, 2073 .vdisplay = 240, 2074 .vsync_start = 240 + 4, 2075 .vsync_end = 240 + 4 + 3, 2076 .vtotal = 240 + 4 + 3 + 15, 2077 .vrefresh = 60, 2078 }; 2079 2080 static const struct panel_desc lemaker_bl035_rgb_002 = { 2081 .modes = &lemaker_bl035_rgb_002_mode, 2082 .num_modes = 1, 2083 .size = { 2084 .width = 70, 2085 .height = 52, 2086 }, 2087 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2088 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2089 }; 2090 2091 static const struct drm_display_mode lg_lb070wv8_mode = { 2092 .clock = 33246, 2093 .hdisplay = 800, 2094 .hsync_start = 800 + 88, 2095 .hsync_end = 800 + 88 + 80, 2096 .htotal = 800 + 88 + 80 + 88, 2097 .vdisplay = 480, 2098 .vsync_start = 480 + 10, 2099 .vsync_end = 480 + 10 + 25, 2100 .vtotal = 480 + 10 + 25 + 10, 2101 .vrefresh = 60, 2102 }; 2103 2104 static const struct panel_desc lg_lb070wv8 = { 2105 .modes = &lg_lb070wv8_mode, 2106 .num_modes = 1, 2107 .bpc = 16, 2108 .size = { 2109 .width = 151, 2110 .height = 91, 2111 }, 2112 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2113 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2114 }; 2115 2116 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2117 .clock = 200000, 2118 .hdisplay = 1536, 2119 .hsync_start = 1536 + 12, 2120 .hsync_end = 1536 + 12 + 16, 2121 .htotal = 1536 + 12 + 16 + 48, 2122 .vdisplay = 2048, 2123 .vsync_start = 2048 + 8, 2124 .vsync_end = 2048 + 8 + 4, 2125 .vtotal = 2048 + 8 + 4 + 8, 2126 .vrefresh = 60, 2127 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2128 }; 2129 2130 static const struct panel_desc lg_lp079qx1_sp0v = { 2131 .modes = &lg_lp079qx1_sp0v_mode, 2132 .num_modes = 1, 2133 .size = { 2134 .width = 129, 2135 .height = 171, 2136 }, 2137 }; 2138 2139 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2140 .clock = 205210, 2141 .hdisplay = 2048, 2142 .hsync_start = 2048 + 150, 2143 .hsync_end = 2048 + 150 + 5, 2144 .htotal = 2048 + 150 + 5 + 5, 2145 .vdisplay = 1536, 2146 .vsync_start = 1536 + 3, 2147 .vsync_end = 1536 + 3 + 1, 2148 .vtotal = 1536 + 3 + 1 + 9, 2149 .vrefresh = 60, 2150 }; 2151 2152 static const struct panel_desc lg_lp097qx1_spa1 = { 2153 .modes = &lg_lp097qx1_spa1_mode, 2154 .num_modes = 1, 2155 .size = { 2156 .width = 208, 2157 .height = 147, 2158 }, 2159 }; 2160 2161 static const struct drm_display_mode lg_lp120up1_mode = { 2162 .clock = 162300, 2163 .hdisplay = 1920, 2164 .hsync_start = 1920 + 40, 2165 .hsync_end = 1920 + 40 + 40, 2166 .htotal = 1920 + 40 + 40+ 80, 2167 .vdisplay = 1280, 2168 .vsync_start = 1280 + 4, 2169 .vsync_end = 1280 + 4 + 4, 2170 .vtotal = 1280 + 4 + 4 + 12, 2171 .vrefresh = 60, 2172 }; 2173 2174 static const struct panel_desc lg_lp120up1 = { 2175 .modes = &lg_lp120up1_mode, 2176 .num_modes = 1, 2177 .bpc = 8, 2178 .size = { 2179 .width = 267, 2180 .height = 183, 2181 }, 2182 }; 2183 2184 static const struct drm_display_mode lg_lp129qe_mode = { 2185 .clock = 285250, 2186 .hdisplay = 2560, 2187 .hsync_start = 2560 + 48, 2188 .hsync_end = 2560 + 48 + 32, 2189 .htotal = 2560 + 48 + 32 + 80, 2190 .vdisplay = 1700, 2191 .vsync_start = 1700 + 3, 2192 .vsync_end = 1700 + 3 + 10, 2193 .vtotal = 1700 + 3 + 10 + 36, 2194 .vrefresh = 60, 2195 }; 2196 2197 static const struct panel_desc lg_lp129qe = { 2198 .modes = &lg_lp129qe_mode, 2199 .num_modes = 1, 2200 .bpc = 8, 2201 .size = { 2202 .width = 272, 2203 .height = 181, 2204 }, 2205 }; 2206 2207 static const struct display_timing logictechno_lt161010_2nh_timing = { 2208 .pixelclock = { 26400000, 33300000, 46800000 }, 2209 .hactive = { 800, 800, 800 }, 2210 .hfront_porch = { 16, 210, 354 }, 2211 .hback_porch = { 46, 46, 46 }, 2212 .hsync_len = { 1, 20, 40 }, 2213 .vactive = { 480, 480, 480 }, 2214 .vfront_porch = { 7, 22, 147 }, 2215 .vback_porch = { 23, 23, 23 }, 2216 .vsync_len = { 1, 10, 20 }, 2217 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2218 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2219 DISPLAY_FLAGS_SYNC_POSEDGE, 2220 }; 2221 2222 static const struct panel_desc logictechno_lt161010_2nh = { 2223 .timings = &logictechno_lt161010_2nh_timing, 2224 .num_timings = 1, 2225 .size = { 2226 .width = 154, 2227 .height = 86, 2228 }, 2229 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2230 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2231 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2232 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2233 .connector_type = DRM_MODE_CONNECTOR_DPI, 2234 }; 2235 2236 static const struct display_timing logictechno_lt170410_2whc_timing = { 2237 .pixelclock = { 68900000, 71100000, 73400000 }, 2238 .hactive = { 1280, 1280, 1280 }, 2239 .hfront_porch = { 23, 60, 71 }, 2240 .hback_porch = { 23, 60, 71 }, 2241 .hsync_len = { 15, 40, 47 }, 2242 .vactive = { 800, 800, 800 }, 2243 .vfront_porch = { 5, 7, 10 }, 2244 .vback_porch = { 5, 7, 10 }, 2245 .vsync_len = { 6, 9, 12 }, 2246 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2247 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2248 DISPLAY_FLAGS_SYNC_POSEDGE, 2249 }; 2250 2251 static const struct panel_desc logictechno_lt170410_2whc = { 2252 .timings = &logictechno_lt170410_2whc_timing, 2253 .num_timings = 1, 2254 .size = { 2255 .width = 217, 2256 .height = 136, 2257 }, 2258 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2259 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2260 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2261 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2262 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2263 }; 2264 2265 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2266 .clock = 30400, 2267 .hdisplay = 800, 2268 .hsync_start = 800 + 0, 2269 .hsync_end = 800 + 1, 2270 .htotal = 800 + 0 + 1 + 160, 2271 .vdisplay = 480, 2272 .vsync_start = 480 + 0, 2273 .vsync_end = 480 + 48 + 1, 2274 .vtotal = 480 + 48 + 1 + 0, 2275 .vrefresh = 60, 2276 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2277 }; 2278 2279 static const struct drm_display_mode logicpd_type_28_mode = { 2280 .clock = 9107, 2281 .hdisplay = 480, 2282 .hsync_start = 480 + 3, 2283 .hsync_end = 480 + 3 + 42, 2284 .htotal = 480 + 3 + 42 + 2, 2285 2286 .vdisplay = 272, 2287 .vsync_start = 272 + 2, 2288 .vsync_end = 272 + 2 + 11, 2289 .vtotal = 272 + 2 + 11 + 3, 2290 .vrefresh = 60, 2291 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2292 }; 2293 2294 static const struct panel_desc logicpd_type_28 = { 2295 .modes = &logicpd_type_28_mode, 2296 .num_modes = 1, 2297 .bpc = 8, 2298 .size = { 2299 .width = 105, 2300 .height = 67, 2301 }, 2302 .delay = { 2303 .prepare = 200, 2304 .enable = 200, 2305 .unprepare = 200, 2306 .disable = 200, 2307 }, 2308 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2309 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2310 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2311 }; 2312 2313 static const struct panel_desc mitsubishi_aa070mc01 = { 2314 .modes = &mitsubishi_aa070mc01_mode, 2315 .num_modes = 1, 2316 .bpc = 8, 2317 .size = { 2318 .width = 152, 2319 .height = 91, 2320 }, 2321 2322 .delay = { 2323 .enable = 200, 2324 .unprepare = 200, 2325 .disable = 400, 2326 }, 2327 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2328 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2329 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2330 }; 2331 2332 static const struct display_timing nec_nl12880bc20_05_timing = { 2333 .pixelclock = { 67000000, 71000000, 75000000 }, 2334 .hactive = { 1280, 1280, 1280 }, 2335 .hfront_porch = { 2, 30, 30 }, 2336 .hback_porch = { 6, 100, 100 }, 2337 .hsync_len = { 2, 30, 30 }, 2338 .vactive = { 800, 800, 800 }, 2339 .vfront_porch = { 5, 5, 5 }, 2340 .vback_porch = { 11, 11, 11 }, 2341 .vsync_len = { 7, 7, 7 }, 2342 }; 2343 2344 static const struct panel_desc nec_nl12880bc20_05 = { 2345 .timings = &nec_nl12880bc20_05_timing, 2346 .num_timings = 1, 2347 .bpc = 8, 2348 .size = { 2349 .width = 261, 2350 .height = 163, 2351 }, 2352 .delay = { 2353 .enable = 50, 2354 .disable = 50, 2355 }, 2356 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2357 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2358 }; 2359 2360 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2361 .clock = 10870, 2362 .hdisplay = 480, 2363 .hsync_start = 480 + 2, 2364 .hsync_end = 480 + 2 + 41, 2365 .htotal = 480 + 2 + 41 + 2, 2366 .vdisplay = 272, 2367 .vsync_start = 272 + 2, 2368 .vsync_end = 272 + 2 + 4, 2369 .vtotal = 272 + 2 + 4 + 2, 2370 .vrefresh = 74, 2371 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2372 }; 2373 2374 static const struct panel_desc nec_nl4827hc19_05b = { 2375 .modes = &nec_nl4827hc19_05b_mode, 2376 .num_modes = 1, 2377 .bpc = 8, 2378 .size = { 2379 .width = 95, 2380 .height = 54, 2381 }, 2382 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2383 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2384 }; 2385 2386 static const struct drm_display_mode netron_dy_e231732_mode = { 2387 .clock = 66000, 2388 .hdisplay = 1024, 2389 .hsync_start = 1024 + 160, 2390 .hsync_end = 1024 + 160 + 70, 2391 .htotal = 1024 + 160 + 70 + 90, 2392 .vdisplay = 600, 2393 .vsync_start = 600 + 127, 2394 .vsync_end = 600 + 127 + 20, 2395 .vtotal = 600 + 127 + 20 + 3, 2396 .vrefresh = 60, 2397 }; 2398 2399 static const struct panel_desc netron_dy_e231732 = { 2400 .modes = &netron_dy_e231732_mode, 2401 .num_modes = 1, 2402 .size = { 2403 .width = 154, 2404 .height = 87, 2405 }, 2406 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2407 }; 2408 2409 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 2410 { 2411 .clock = 138500, 2412 .hdisplay = 1920, 2413 .hsync_start = 1920 + 48, 2414 .hsync_end = 1920 + 48 + 32, 2415 .htotal = 1920 + 48 + 32 + 80, 2416 .vdisplay = 1080, 2417 .vsync_start = 1080 + 3, 2418 .vsync_end = 1080 + 3 + 5, 2419 .vtotal = 1080 + 3 + 5 + 23, 2420 .vrefresh = 60, 2421 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2422 }, { 2423 .clock = 110920, 2424 .hdisplay = 1920, 2425 .hsync_start = 1920 + 48, 2426 .hsync_end = 1920 + 48 + 32, 2427 .htotal = 1920 + 48 + 32 + 80, 2428 .vdisplay = 1080, 2429 .vsync_start = 1080 + 3, 2430 .vsync_end = 1080 + 3 + 5, 2431 .vtotal = 1080 + 3 + 5 + 23, 2432 .vrefresh = 48, 2433 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2434 } 2435 }; 2436 2437 static const struct panel_desc neweast_wjfh116008a = { 2438 .modes = neweast_wjfh116008a_modes, 2439 .num_modes = 2, 2440 .bpc = 6, 2441 .size = { 2442 .width = 260, 2443 .height = 150, 2444 }, 2445 .delay = { 2446 .prepare = 110, 2447 .enable = 20, 2448 .unprepare = 500, 2449 }, 2450 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2451 .connector_type = DRM_MODE_CONNECTOR_eDP, 2452 }; 2453 2454 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2455 .clock = 9000, 2456 .hdisplay = 480, 2457 .hsync_start = 480 + 2, 2458 .hsync_end = 480 + 2 + 41, 2459 .htotal = 480 + 2 + 41 + 2, 2460 .vdisplay = 272, 2461 .vsync_start = 272 + 2, 2462 .vsync_end = 272 + 2 + 10, 2463 .vtotal = 272 + 2 + 10 + 2, 2464 .vrefresh = 60, 2465 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2466 }; 2467 2468 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2469 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2470 .num_modes = 1, 2471 .bpc = 8, 2472 .size = { 2473 .width = 95, 2474 .height = 54, 2475 }, 2476 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2477 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2478 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2479 }; 2480 2481 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2482 .pixelclock = { 130000000, 148350000, 163000000 }, 2483 .hactive = { 1920, 1920, 1920 }, 2484 .hfront_porch = { 80, 100, 100 }, 2485 .hback_porch = { 100, 120, 120 }, 2486 .hsync_len = { 50, 60, 60 }, 2487 .vactive = { 1080, 1080, 1080 }, 2488 .vfront_porch = { 12, 30, 30 }, 2489 .vback_porch = { 4, 10, 10 }, 2490 .vsync_len = { 4, 5, 5 }, 2491 }; 2492 2493 static const struct panel_desc nlt_nl192108ac18_02d = { 2494 .timings = &nlt_nl192108ac18_02d_timing, 2495 .num_timings = 1, 2496 .bpc = 8, 2497 .size = { 2498 .width = 344, 2499 .height = 194, 2500 }, 2501 .delay = { 2502 .unprepare = 500, 2503 }, 2504 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2505 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2506 }; 2507 2508 static const struct drm_display_mode nvd_9128_mode = { 2509 .clock = 29500, 2510 .hdisplay = 800, 2511 .hsync_start = 800 + 130, 2512 .hsync_end = 800 + 130 + 98, 2513 .htotal = 800 + 0 + 130 + 98, 2514 .vdisplay = 480, 2515 .vsync_start = 480 + 10, 2516 .vsync_end = 480 + 10 + 50, 2517 .vtotal = 480 + 0 + 10 + 50, 2518 }; 2519 2520 static const struct panel_desc nvd_9128 = { 2521 .modes = &nvd_9128_mode, 2522 .num_modes = 1, 2523 .bpc = 8, 2524 .size = { 2525 .width = 156, 2526 .height = 88, 2527 }, 2528 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2529 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2530 }; 2531 2532 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2533 .pixelclock = { 30000000, 30000000, 40000000 }, 2534 .hactive = { 800, 800, 800 }, 2535 .hfront_porch = { 40, 40, 40 }, 2536 .hback_porch = { 40, 40, 40 }, 2537 .hsync_len = { 1, 48, 48 }, 2538 .vactive = { 480, 480, 480 }, 2539 .vfront_porch = { 13, 13, 13 }, 2540 .vback_porch = { 29, 29, 29 }, 2541 .vsync_len = { 3, 3, 3 }, 2542 .flags = DISPLAY_FLAGS_DE_HIGH, 2543 }; 2544 2545 static const struct panel_desc okaya_rs800480t_7x0gp = { 2546 .timings = &okaya_rs800480t_7x0gp_timing, 2547 .num_timings = 1, 2548 .bpc = 6, 2549 .size = { 2550 .width = 154, 2551 .height = 87, 2552 }, 2553 .delay = { 2554 .prepare = 41, 2555 .enable = 50, 2556 .unprepare = 41, 2557 .disable = 50, 2558 }, 2559 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2560 }; 2561 2562 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2563 .clock = 9000, 2564 .hdisplay = 480, 2565 .hsync_start = 480 + 5, 2566 .hsync_end = 480 + 5 + 30, 2567 .htotal = 480 + 5 + 30 + 10, 2568 .vdisplay = 272, 2569 .vsync_start = 272 + 8, 2570 .vsync_end = 272 + 8 + 5, 2571 .vtotal = 272 + 8 + 5 + 3, 2572 .vrefresh = 60, 2573 }; 2574 2575 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2576 .modes = &olimex_lcd_olinuxino_43ts_mode, 2577 .num_modes = 1, 2578 .size = { 2579 .width = 95, 2580 .height = 54, 2581 }, 2582 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2583 }; 2584 2585 /* 2586 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2587 * pixel clocks, but this is the timing that was being used in the Adafruit 2588 * installation instructions. 2589 */ 2590 static const struct drm_display_mode ontat_yx700wv03_mode = { 2591 .clock = 29500, 2592 .hdisplay = 800, 2593 .hsync_start = 824, 2594 .hsync_end = 896, 2595 .htotal = 992, 2596 .vdisplay = 480, 2597 .vsync_start = 483, 2598 .vsync_end = 493, 2599 .vtotal = 500, 2600 .vrefresh = 60, 2601 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2602 }; 2603 2604 /* 2605 * Specification at: 2606 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2607 */ 2608 static const struct panel_desc ontat_yx700wv03 = { 2609 .modes = &ontat_yx700wv03_mode, 2610 .num_modes = 1, 2611 .bpc = 8, 2612 .size = { 2613 .width = 154, 2614 .height = 83, 2615 }, 2616 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2617 }; 2618 2619 static const struct drm_display_mode ortustech_com37h3m_mode = { 2620 .clock = 22230, 2621 .hdisplay = 480, 2622 .hsync_start = 480 + 40, 2623 .hsync_end = 480 + 40 + 10, 2624 .htotal = 480 + 40 + 10 + 40, 2625 .vdisplay = 640, 2626 .vsync_start = 640 + 4, 2627 .vsync_end = 640 + 4 + 2, 2628 .vtotal = 640 + 4 + 2 + 4, 2629 .vrefresh = 60, 2630 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2631 }; 2632 2633 static const struct panel_desc ortustech_com37h3m = { 2634 .modes = &ortustech_com37h3m_mode, 2635 .num_modes = 1, 2636 .bpc = 8, 2637 .size = { 2638 .width = 56, /* 56.16mm */ 2639 .height = 75, /* 74.88mm */ 2640 }, 2641 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2642 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 2643 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2644 }; 2645 2646 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 2647 .clock = 25000, 2648 .hdisplay = 480, 2649 .hsync_start = 480 + 10, 2650 .hsync_end = 480 + 10 + 10, 2651 .htotal = 480 + 10 + 10 + 15, 2652 .vdisplay = 800, 2653 .vsync_start = 800 + 3, 2654 .vsync_end = 800 + 3 + 3, 2655 .vtotal = 800 + 3 + 3 + 3, 2656 .vrefresh = 60, 2657 }; 2658 2659 static const struct panel_desc ortustech_com43h4m85ulc = { 2660 .modes = &ortustech_com43h4m85ulc_mode, 2661 .num_modes = 1, 2662 .bpc = 8, 2663 .size = { 2664 .width = 56, 2665 .height = 93, 2666 }, 2667 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2668 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2669 .connector_type = DRM_MODE_CONNECTOR_DPI, 2670 }; 2671 2672 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 2673 .clock = 33000, 2674 .hdisplay = 800, 2675 .hsync_start = 800 + 210, 2676 .hsync_end = 800 + 210 + 30, 2677 .htotal = 800 + 210 + 30 + 16, 2678 .vdisplay = 480, 2679 .vsync_start = 480 + 22, 2680 .vsync_end = 480 + 22 + 13, 2681 .vtotal = 480 + 22 + 13 + 10, 2682 .vrefresh = 60, 2683 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2684 }; 2685 2686 static const struct panel_desc osddisplays_osd070t1718_19ts = { 2687 .modes = &osddisplays_osd070t1718_19ts_mode, 2688 .num_modes = 1, 2689 .bpc = 8, 2690 .size = { 2691 .width = 152, 2692 .height = 91, 2693 }, 2694 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2695 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2696 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2697 .connector_type = DRM_MODE_CONNECTOR_DPI, 2698 }; 2699 2700 static const struct drm_display_mode pda_91_00156_a0_mode = { 2701 .clock = 33300, 2702 .hdisplay = 800, 2703 .hsync_start = 800 + 1, 2704 .hsync_end = 800 + 1 + 64, 2705 .htotal = 800 + 1 + 64 + 64, 2706 .vdisplay = 480, 2707 .vsync_start = 480 + 1, 2708 .vsync_end = 480 + 1 + 23, 2709 .vtotal = 480 + 1 + 23 + 22, 2710 .vrefresh = 60, 2711 }; 2712 2713 static const struct panel_desc pda_91_00156_a0 = { 2714 .modes = &pda_91_00156_a0_mode, 2715 .num_modes = 1, 2716 .size = { 2717 .width = 152, 2718 .height = 91, 2719 }, 2720 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2721 }; 2722 2723 2724 static const struct drm_display_mode qd43003c0_40_mode = { 2725 .clock = 9000, 2726 .hdisplay = 480, 2727 .hsync_start = 480 + 8, 2728 .hsync_end = 480 + 8 + 4, 2729 .htotal = 480 + 8 + 4 + 39, 2730 .vdisplay = 272, 2731 .vsync_start = 272 + 4, 2732 .vsync_end = 272 + 4 + 10, 2733 .vtotal = 272 + 4 + 10 + 2, 2734 .vrefresh = 60, 2735 }; 2736 2737 static const struct panel_desc qd43003c0_40 = { 2738 .modes = &qd43003c0_40_mode, 2739 .num_modes = 1, 2740 .bpc = 8, 2741 .size = { 2742 .width = 95, 2743 .height = 53, 2744 }, 2745 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2746 }; 2747 2748 static const struct display_timing rocktech_rk070er9427_timing = { 2749 .pixelclock = { 26400000, 33300000, 46800000 }, 2750 .hactive = { 800, 800, 800 }, 2751 .hfront_porch = { 16, 210, 354 }, 2752 .hback_porch = { 46, 46, 46 }, 2753 .hsync_len = { 1, 1, 1 }, 2754 .vactive = { 480, 480, 480 }, 2755 .vfront_porch = { 7, 22, 147 }, 2756 .vback_porch = { 23, 23, 23 }, 2757 .vsync_len = { 1, 1, 1 }, 2758 .flags = DISPLAY_FLAGS_DE_HIGH, 2759 }; 2760 2761 static const struct panel_desc rocktech_rk070er9427 = { 2762 .timings = &rocktech_rk070er9427_timing, 2763 .num_timings = 1, 2764 .bpc = 6, 2765 .size = { 2766 .width = 154, 2767 .height = 86, 2768 }, 2769 .delay = { 2770 .prepare = 41, 2771 .enable = 50, 2772 .unprepare = 41, 2773 .disable = 50, 2774 }, 2775 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2776 }; 2777 2778 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 2779 .clock = 71100, 2780 .hdisplay = 1280, 2781 .hsync_start = 1280 + 48, 2782 .hsync_end = 1280 + 48 + 32, 2783 .htotal = 1280 + 48 + 32 + 80, 2784 .vdisplay = 800, 2785 .vsync_start = 800 + 2, 2786 .vsync_end = 800 + 2 + 5, 2787 .vtotal = 800 + 2 + 5 + 16, 2788 .vrefresh = 60, 2789 }; 2790 2791 static const struct panel_desc rocktech_rk101ii01d_ct = { 2792 .modes = &rocktech_rk101ii01d_ct_mode, 2793 .num_modes = 1, 2794 .size = { 2795 .width = 217, 2796 .height = 136, 2797 }, 2798 .delay = { 2799 .prepare = 50, 2800 .disable = 50, 2801 }, 2802 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2803 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2804 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2805 }; 2806 2807 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 2808 .clock = 271560, 2809 .hdisplay = 2560, 2810 .hsync_start = 2560 + 48, 2811 .hsync_end = 2560 + 48 + 32, 2812 .htotal = 2560 + 48 + 32 + 80, 2813 .vdisplay = 1600, 2814 .vsync_start = 1600 + 2, 2815 .vsync_end = 1600 + 2 + 5, 2816 .vtotal = 1600 + 2 + 5 + 57, 2817 .vrefresh = 60, 2818 }; 2819 2820 static const struct panel_desc samsung_lsn122dl01_c01 = { 2821 .modes = &samsung_lsn122dl01_c01_mode, 2822 .num_modes = 1, 2823 .size = { 2824 .width = 263, 2825 .height = 164, 2826 }, 2827 }; 2828 2829 static const struct drm_display_mode samsung_ltn101nt05_mode = { 2830 .clock = 54030, 2831 .hdisplay = 1024, 2832 .hsync_start = 1024 + 24, 2833 .hsync_end = 1024 + 24 + 136, 2834 .htotal = 1024 + 24 + 136 + 160, 2835 .vdisplay = 600, 2836 .vsync_start = 600 + 3, 2837 .vsync_end = 600 + 3 + 6, 2838 .vtotal = 600 + 3 + 6 + 61, 2839 .vrefresh = 60, 2840 }; 2841 2842 static const struct panel_desc samsung_ltn101nt05 = { 2843 .modes = &samsung_ltn101nt05_mode, 2844 .num_modes = 1, 2845 .bpc = 6, 2846 .size = { 2847 .width = 223, 2848 .height = 125, 2849 }, 2850 }; 2851 2852 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 2853 .clock = 76300, 2854 .hdisplay = 1366, 2855 .hsync_start = 1366 + 64, 2856 .hsync_end = 1366 + 64 + 48, 2857 .htotal = 1366 + 64 + 48 + 128, 2858 .vdisplay = 768, 2859 .vsync_start = 768 + 2, 2860 .vsync_end = 768 + 2 + 5, 2861 .vtotal = 768 + 2 + 5 + 17, 2862 .vrefresh = 60, 2863 }; 2864 2865 static const struct panel_desc samsung_ltn140at29_301 = { 2866 .modes = &samsung_ltn140at29_301_mode, 2867 .num_modes = 1, 2868 .bpc = 6, 2869 .size = { 2870 .width = 320, 2871 .height = 187, 2872 }, 2873 }; 2874 2875 static const struct display_timing satoz_sat050at40h12r2_timing = { 2876 .pixelclock = {33300000, 33300000, 50000000}, 2877 .hactive = {800, 800, 800}, 2878 .hfront_porch = {16, 210, 354}, 2879 .hback_porch = {46, 46, 46}, 2880 .hsync_len = {1, 1, 40}, 2881 .vactive = {480, 480, 480}, 2882 .vfront_porch = {7, 22, 147}, 2883 .vback_porch = {23, 23, 23}, 2884 .vsync_len = {1, 1, 20}, 2885 }; 2886 2887 static const struct panel_desc satoz_sat050at40h12r2 = { 2888 .timings = &satoz_sat050at40h12r2_timing, 2889 .num_timings = 1, 2890 .bpc = 8, 2891 .size = { 2892 .width = 108, 2893 .height = 65, 2894 }, 2895 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2896 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2897 }; 2898 2899 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 2900 .clock = 168480, 2901 .hdisplay = 1920, 2902 .hsync_start = 1920 + 48, 2903 .hsync_end = 1920 + 48 + 32, 2904 .htotal = 1920 + 48 + 32 + 80, 2905 .vdisplay = 1280, 2906 .vsync_start = 1280 + 3, 2907 .vsync_end = 1280 + 3 + 10, 2908 .vtotal = 1280 + 3 + 10 + 57, 2909 .vrefresh = 60, 2910 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2911 }; 2912 2913 static const struct panel_desc sharp_ld_d5116z01b = { 2914 .modes = &sharp_ld_d5116z01b_mode, 2915 .num_modes = 1, 2916 .bpc = 8, 2917 .size = { 2918 .width = 260, 2919 .height = 120, 2920 }, 2921 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2922 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2923 }; 2924 2925 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 2926 .clock = 33260, 2927 .hdisplay = 800, 2928 .hsync_start = 800 + 64, 2929 .hsync_end = 800 + 64 + 128, 2930 .htotal = 800 + 64 + 128 + 64, 2931 .vdisplay = 480, 2932 .vsync_start = 480 + 8, 2933 .vsync_end = 480 + 8 + 2, 2934 .vtotal = 480 + 8 + 2 + 35, 2935 .vrefresh = 60, 2936 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 2937 }; 2938 2939 static const struct panel_desc sharp_lq070y3dg3b = { 2940 .modes = &sharp_lq070y3dg3b_mode, 2941 .num_modes = 1, 2942 .bpc = 8, 2943 .size = { 2944 .width = 152, /* 152.4mm */ 2945 .height = 91, /* 91.4mm */ 2946 }, 2947 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2948 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 2949 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2950 }; 2951 2952 static const struct drm_display_mode sharp_lq035q7db03_mode = { 2953 .clock = 5500, 2954 .hdisplay = 240, 2955 .hsync_start = 240 + 16, 2956 .hsync_end = 240 + 16 + 7, 2957 .htotal = 240 + 16 + 7 + 5, 2958 .vdisplay = 320, 2959 .vsync_start = 320 + 9, 2960 .vsync_end = 320 + 9 + 1, 2961 .vtotal = 320 + 9 + 1 + 7, 2962 .vrefresh = 60, 2963 }; 2964 2965 static const struct panel_desc sharp_lq035q7db03 = { 2966 .modes = &sharp_lq035q7db03_mode, 2967 .num_modes = 1, 2968 .bpc = 6, 2969 .size = { 2970 .width = 54, 2971 .height = 72, 2972 }, 2973 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2974 }; 2975 2976 static const struct display_timing sharp_lq101k1ly04_timing = { 2977 .pixelclock = { 60000000, 65000000, 80000000 }, 2978 .hactive = { 1280, 1280, 1280 }, 2979 .hfront_porch = { 20, 20, 20 }, 2980 .hback_porch = { 20, 20, 20 }, 2981 .hsync_len = { 10, 10, 10 }, 2982 .vactive = { 800, 800, 800 }, 2983 .vfront_porch = { 4, 4, 4 }, 2984 .vback_porch = { 4, 4, 4 }, 2985 .vsync_len = { 4, 4, 4 }, 2986 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 2987 }; 2988 2989 static const struct panel_desc sharp_lq101k1ly04 = { 2990 .timings = &sharp_lq101k1ly04_timing, 2991 .num_timings = 1, 2992 .bpc = 8, 2993 .size = { 2994 .width = 217, 2995 .height = 136, 2996 }, 2997 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 2998 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2999 }; 3000 3001 static const struct display_timing sharp_lq123p1jx31_timing = { 3002 .pixelclock = { 252750000, 252750000, 266604720 }, 3003 .hactive = { 2400, 2400, 2400 }, 3004 .hfront_porch = { 48, 48, 48 }, 3005 .hback_porch = { 80, 80, 84 }, 3006 .hsync_len = { 32, 32, 32 }, 3007 .vactive = { 1600, 1600, 1600 }, 3008 .vfront_porch = { 3, 3, 3 }, 3009 .vback_porch = { 33, 33, 120 }, 3010 .vsync_len = { 10, 10, 10 }, 3011 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3012 }; 3013 3014 static const struct panel_desc sharp_lq123p1jx31 = { 3015 .timings = &sharp_lq123p1jx31_timing, 3016 .num_timings = 1, 3017 .bpc = 8, 3018 .size = { 3019 .width = 259, 3020 .height = 173, 3021 }, 3022 .delay = { 3023 .prepare = 110, 3024 .enable = 50, 3025 .unprepare = 550, 3026 }, 3027 }; 3028 3029 static const struct display_timing sharp_ls020b1dd01d_timing = { 3030 .pixelclock = { 2000000, 4200000, 5000000 }, 3031 .hactive = { 240, 240, 240 }, 3032 .hfront_porch = { 66, 66, 66 }, 3033 .hback_porch = { 1, 1, 1 }, 3034 .hsync_len = { 1, 1, 1 }, 3035 .vactive = { 160, 160, 160 }, 3036 .vfront_porch = { 52, 52, 52 }, 3037 .vback_porch = { 6, 6, 6 }, 3038 .vsync_len = { 10, 10, 10 }, 3039 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW, 3040 }; 3041 3042 static const struct panel_desc sharp_ls020b1dd01d = { 3043 .timings = &sharp_ls020b1dd01d_timing, 3044 .num_timings = 1, 3045 .bpc = 6, 3046 .size = { 3047 .width = 42, 3048 .height = 28, 3049 }, 3050 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3051 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3052 | DRM_BUS_FLAG_PIXDATA_NEGEDGE 3053 | DRM_BUS_FLAG_SHARP_SIGNALS, 3054 }; 3055 3056 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3057 .clock = 33300, 3058 .hdisplay = 800, 3059 .hsync_start = 800 + 1, 3060 .hsync_end = 800 + 1 + 64, 3061 .htotal = 800 + 1 + 64 + 64, 3062 .vdisplay = 480, 3063 .vsync_start = 480 + 1, 3064 .vsync_end = 480 + 1 + 23, 3065 .vtotal = 480 + 1 + 23 + 22, 3066 .vrefresh = 60, 3067 }; 3068 3069 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3070 .modes = &shelly_sca07010_bfn_lnn_mode, 3071 .num_modes = 1, 3072 .size = { 3073 .width = 152, 3074 .height = 91, 3075 }, 3076 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3077 }; 3078 3079 static const struct drm_display_mode starry_kr122ea0sra_mode = { 3080 .clock = 147000, 3081 .hdisplay = 1920, 3082 .hsync_start = 1920 + 16, 3083 .hsync_end = 1920 + 16 + 16, 3084 .htotal = 1920 + 16 + 16 + 32, 3085 .vdisplay = 1200, 3086 .vsync_start = 1200 + 15, 3087 .vsync_end = 1200 + 15 + 2, 3088 .vtotal = 1200 + 15 + 2 + 18, 3089 .vrefresh = 60, 3090 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3091 }; 3092 3093 static const struct panel_desc starry_kr122ea0sra = { 3094 .modes = &starry_kr122ea0sra_mode, 3095 .num_modes = 1, 3096 .size = { 3097 .width = 263, 3098 .height = 164, 3099 }, 3100 .delay = { 3101 .prepare = 10 + 200, 3102 .enable = 50, 3103 .unprepare = 10 + 500, 3104 }, 3105 }; 3106 3107 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3108 .clock = 30000, 3109 .hdisplay = 800, 3110 .hsync_start = 800 + 39, 3111 .hsync_end = 800 + 39 + 47, 3112 .htotal = 800 + 39 + 47 + 39, 3113 .vdisplay = 480, 3114 .vsync_start = 480 + 13, 3115 .vsync_end = 480 + 13 + 2, 3116 .vtotal = 480 + 13 + 2 + 29, 3117 .vrefresh = 62, 3118 }; 3119 3120 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3121 .modes = &tfc_s9700rtwv43tr_01b_mode, 3122 .num_modes = 1, 3123 .bpc = 8, 3124 .size = { 3125 .width = 155, 3126 .height = 90, 3127 }, 3128 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3129 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3130 }; 3131 3132 static const struct display_timing tianma_tm070jdhg30_timing = { 3133 .pixelclock = { 62600000, 68200000, 78100000 }, 3134 .hactive = { 1280, 1280, 1280 }, 3135 .hfront_porch = { 15, 64, 159 }, 3136 .hback_porch = { 5, 5, 5 }, 3137 .hsync_len = { 1, 1, 256 }, 3138 .vactive = { 800, 800, 800 }, 3139 .vfront_porch = { 3, 40, 99 }, 3140 .vback_porch = { 2, 2, 2 }, 3141 .vsync_len = { 1, 1, 128 }, 3142 .flags = DISPLAY_FLAGS_DE_HIGH, 3143 }; 3144 3145 static const struct panel_desc tianma_tm070jdhg30 = { 3146 .timings = &tianma_tm070jdhg30_timing, 3147 .num_timings = 1, 3148 .bpc = 8, 3149 .size = { 3150 .width = 151, 3151 .height = 95, 3152 }, 3153 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3154 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3155 }; 3156 3157 static const struct display_timing tianma_tm070rvhg71_timing = { 3158 .pixelclock = { 27700000, 29200000, 39600000 }, 3159 .hactive = { 800, 800, 800 }, 3160 .hfront_porch = { 12, 40, 212 }, 3161 .hback_porch = { 88, 88, 88 }, 3162 .hsync_len = { 1, 1, 40 }, 3163 .vactive = { 480, 480, 480 }, 3164 .vfront_porch = { 1, 13, 88 }, 3165 .vback_porch = { 32, 32, 32 }, 3166 .vsync_len = { 1, 1, 3 }, 3167 .flags = DISPLAY_FLAGS_DE_HIGH, 3168 }; 3169 3170 static const struct panel_desc tianma_tm070rvhg71 = { 3171 .timings = &tianma_tm070rvhg71_timing, 3172 .num_timings = 1, 3173 .bpc = 8, 3174 .size = { 3175 .width = 154, 3176 .height = 86, 3177 }, 3178 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3179 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3180 }; 3181 3182 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3183 { 3184 .clock = 10000, 3185 .hdisplay = 320, 3186 .hsync_start = 320 + 50, 3187 .hsync_end = 320 + 50 + 6, 3188 .htotal = 320 + 50 + 6 + 38, 3189 .vdisplay = 240, 3190 .vsync_start = 240 + 3, 3191 .vsync_end = 240 + 3 + 1, 3192 .vtotal = 240 + 3 + 1 + 17, 3193 .vrefresh = 60, 3194 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3195 }, 3196 }; 3197 3198 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3199 .modes = ti_nspire_cx_lcd_mode, 3200 .num_modes = 1, 3201 .bpc = 8, 3202 .size = { 3203 .width = 65, 3204 .height = 49, 3205 }, 3206 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3207 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE, 3208 }; 3209 3210 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3211 { 3212 .clock = 10000, 3213 .hdisplay = 320, 3214 .hsync_start = 320 + 6, 3215 .hsync_end = 320 + 6 + 6, 3216 .htotal = 320 + 6 + 6 + 6, 3217 .vdisplay = 240, 3218 .vsync_start = 240 + 0, 3219 .vsync_end = 240 + 0 + 1, 3220 .vtotal = 240 + 0 + 1 + 0, 3221 .vrefresh = 60, 3222 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3223 }, 3224 }; 3225 3226 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3227 .modes = ti_nspire_classic_lcd_mode, 3228 .num_modes = 1, 3229 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3230 .bpc = 8, 3231 .size = { 3232 .width = 71, 3233 .height = 53, 3234 }, 3235 /* This is the grayscale bus format */ 3236 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3237 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 3238 }; 3239 3240 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3241 .clock = 79500, 3242 .hdisplay = 1280, 3243 .hsync_start = 1280 + 192, 3244 .hsync_end = 1280 + 192 + 128, 3245 .htotal = 1280 + 192 + 128 + 64, 3246 .vdisplay = 768, 3247 .vsync_start = 768 + 20, 3248 .vsync_end = 768 + 20 + 7, 3249 .vtotal = 768 + 20 + 7 + 3, 3250 .vrefresh = 60, 3251 }; 3252 3253 static const struct panel_desc toshiba_lt089ac29000 = { 3254 .modes = &toshiba_lt089ac29000_mode, 3255 .num_modes = 1, 3256 .size = { 3257 .width = 194, 3258 .height = 116, 3259 }, 3260 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3261 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3262 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3263 }; 3264 3265 static const struct drm_display_mode tpk_f07a_0102_mode = { 3266 .clock = 33260, 3267 .hdisplay = 800, 3268 .hsync_start = 800 + 40, 3269 .hsync_end = 800 + 40 + 128, 3270 .htotal = 800 + 40 + 128 + 88, 3271 .vdisplay = 480, 3272 .vsync_start = 480 + 10, 3273 .vsync_end = 480 + 10 + 2, 3274 .vtotal = 480 + 10 + 2 + 33, 3275 .vrefresh = 60, 3276 }; 3277 3278 static const struct panel_desc tpk_f07a_0102 = { 3279 .modes = &tpk_f07a_0102_mode, 3280 .num_modes = 1, 3281 .size = { 3282 .width = 152, 3283 .height = 91, 3284 }, 3285 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3286 }; 3287 3288 static const struct drm_display_mode tpk_f10a_0102_mode = { 3289 .clock = 45000, 3290 .hdisplay = 1024, 3291 .hsync_start = 1024 + 176, 3292 .hsync_end = 1024 + 176 + 5, 3293 .htotal = 1024 + 176 + 5 + 88, 3294 .vdisplay = 600, 3295 .vsync_start = 600 + 20, 3296 .vsync_end = 600 + 20 + 5, 3297 .vtotal = 600 + 20 + 5 + 25, 3298 .vrefresh = 60, 3299 }; 3300 3301 static const struct panel_desc tpk_f10a_0102 = { 3302 .modes = &tpk_f10a_0102_mode, 3303 .num_modes = 1, 3304 .size = { 3305 .width = 223, 3306 .height = 125, 3307 }, 3308 }; 3309 3310 static const struct display_timing urt_umsh_8596md_timing = { 3311 .pixelclock = { 33260000, 33260000, 33260000 }, 3312 .hactive = { 800, 800, 800 }, 3313 .hfront_porch = { 41, 41, 41 }, 3314 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3315 .hsync_len = { 71, 128, 128 }, 3316 .vactive = { 480, 480, 480 }, 3317 .vfront_porch = { 10, 10, 10 }, 3318 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3319 .vsync_len = { 2, 2, 2 }, 3320 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3321 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3322 }; 3323 3324 static const struct panel_desc urt_umsh_8596md_lvds = { 3325 .timings = &urt_umsh_8596md_timing, 3326 .num_timings = 1, 3327 .bpc = 6, 3328 .size = { 3329 .width = 152, 3330 .height = 91, 3331 }, 3332 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3333 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3334 }; 3335 3336 static const struct panel_desc urt_umsh_8596md_parallel = { 3337 .timings = &urt_umsh_8596md_timing, 3338 .num_timings = 1, 3339 .bpc = 6, 3340 .size = { 3341 .width = 152, 3342 .height = 91, 3343 }, 3344 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3345 }; 3346 3347 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3348 .clock = 33333, 3349 .hdisplay = 800, 3350 .hsync_start = 800 + 210, 3351 .hsync_end = 800 + 210 + 20, 3352 .htotal = 800 + 210 + 20 + 46, 3353 .vdisplay = 480, 3354 .vsync_start = 480 + 22, 3355 .vsync_end = 480 + 22 + 10, 3356 .vtotal = 480 + 22 + 10 + 23, 3357 .vrefresh = 60, 3358 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3359 }; 3360 3361 static const struct panel_desc vl050_8048nt_c01 = { 3362 .modes = &vl050_8048nt_c01_mode, 3363 .num_modes = 1, 3364 .bpc = 8, 3365 .size = { 3366 .width = 120, 3367 .height = 76, 3368 }, 3369 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3370 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 3371 }; 3372 3373 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3374 .clock = 6410, 3375 .hdisplay = 320, 3376 .hsync_start = 320 + 20, 3377 .hsync_end = 320 + 20 + 30, 3378 .htotal = 320 + 20 + 30 + 38, 3379 .vdisplay = 240, 3380 .vsync_start = 240 + 4, 3381 .vsync_end = 240 + 4 + 3, 3382 .vtotal = 240 + 4 + 3 + 15, 3383 .vrefresh = 60, 3384 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3385 }; 3386 3387 static const struct panel_desc winstar_wf35ltiacd = { 3388 .modes = &winstar_wf35ltiacd_mode, 3389 .num_modes = 1, 3390 .bpc = 8, 3391 .size = { 3392 .width = 70, 3393 .height = 53, 3394 }, 3395 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3396 }; 3397 3398 static const struct drm_display_mode arm_rtsm_mode[] = { 3399 { 3400 .clock = 65000, 3401 .hdisplay = 1024, 3402 .hsync_start = 1024 + 24, 3403 .hsync_end = 1024 + 24 + 136, 3404 .htotal = 1024 + 24 + 136 + 160, 3405 .vdisplay = 768, 3406 .vsync_start = 768 + 3, 3407 .vsync_end = 768 + 3 + 6, 3408 .vtotal = 768 + 3 + 6 + 29, 3409 .vrefresh = 60, 3410 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3411 }, 3412 }; 3413 3414 static const struct panel_desc arm_rtsm = { 3415 .modes = arm_rtsm_mode, 3416 .num_modes = 1, 3417 .bpc = 8, 3418 .size = { 3419 .width = 400, 3420 .height = 300, 3421 }, 3422 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3423 }; 3424 3425 static const struct of_device_id platform_of_match[] = { 3426 { 3427 .compatible = "ampire,am-480272h3tmqw-t01h", 3428 .data = &ire_am_480272h3tmqw_t01h, 3429 }, { 3430 .compatible = "ampire,am800480r3tmqwa1h", 3431 .data = &ire_am800480r3tmqwa1h, 3432 }, { 3433 .compatible = "arm,rtsm-display", 3434 .data = &arm_rtsm, 3435 }, { 3436 .compatible = "armadeus,st0700-adapt", 3437 .data = &armadeus_st0700_adapt, 3438 }, { 3439 .compatible = "auo,b101aw03", 3440 .data = &auo_b101aw03, 3441 }, { 3442 .compatible = "auo,b101ean01", 3443 .data = &auo_b101ean01, 3444 }, { 3445 .compatible = "auo,b101xtn01", 3446 .data = &auo_b101xtn01, 3447 }, { 3448 .compatible = "auo,b116xa01", 3449 .data = &auo_b116xak01, 3450 }, { 3451 .compatible = "auo,b116xw03", 3452 .data = &auo_b116xw03, 3453 }, { 3454 .compatible = "auo,b133htn01", 3455 .data = &auo_b133htn01, 3456 }, { 3457 .compatible = "auo,b133xtn01", 3458 .data = &auo_b133xtn01, 3459 }, { 3460 .compatible = "auo,g070vvn01", 3461 .data = &auo_g070vvn01, 3462 }, { 3463 .compatible = "auo,g101evn010", 3464 .data = &auo_g101evn010, 3465 }, { 3466 .compatible = "auo,g104sn02", 3467 .data = &auo_g104sn02, 3468 }, { 3469 .compatible = "auo,g133han01", 3470 .data = &auo_g133han01, 3471 }, { 3472 .compatible = "auo,g185han01", 3473 .data = &auo_g185han01, 3474 }, { 3475 .compatible = "auo,p320hvn03", 3476 .data = &auo_p320hvn03, 3477 }, { 3478 .compatible = "auo,t215hvn01", 3479 .data = &auo_t215hvn01, 3480 }, { 3481 .compatible = "avic,tm070ddh03", 3482 .data = &avic_tm070ddh03, 3483 }, { 3484 .compatible = "bananapi,s070wv20-ct16", 3485 .data = &bananapi_s070wv20_ct16, 3486 }, { 3487 .compatible = "boe,hv070wsa-100", 3488 .data = &boe_hv070wsa 3489 }, { 3490 .compatible = "boe,nv101wxmn51", 3491 .data = &boe_nv101wxmn51, 3492 }, { 3493 .compatible = "boe,nv140fhmn49", 3494 .data = &boe_nv140fhmn49, 3495 }, { 3496 .compatible = "cdtech,s043wq26h-ct7", 3497 .data = &cdtech_s043wq26h_ct7, 3498 }, { 3499 .compatible = "cdtech,s070wv95-ct16", 3500 .data = &cdtech_s070wv95_ct16, 3501 }, { 3502 .compatible = "chunghwa,claa070wp03xg", 3503 .data = &chunghwa_claa070wp03xg, 3504 }, { 3505 .compatible = "chunghwa,claa101wa01a", 3506 .data = &chunghwa_claa101wa01a 3507 }, { 3508 .compatible = "chunghwa,claa101wb01", 3509 .data = &chunghwa_claa101wb01 3510 }, { 3511 .compatible = "dataimage,scf0700c48ggu18", 3512 .data = &dataimage_scf0700c48ggu18, 3513 }, { 3514 .compatible = "dlc,dlc0700yzg-1", 3515 .data = &dlc_dlc0700yzg_1, 3516 }, { 3517 .compatible = "dlc,dlc1010gig", 3518 .data = &dlc_dlc1010gig, 3519 }, { 3520 .compatible = "edt,et035012dm6", 3521 .data = &edt_et035012dm6, 3522 }, { 3523 .compatible = "edt,etm043080dh6gp", 3524 .data = &edt_etm043080dh6gp, 3525 }, { 3526 .compatible = "edt,etm0430g0dh6", 3527 .data = &edt_etm0430g0dh6, 3528 }, { 3529 .compatible = "edt,et057090dhu", 3530 .data = &edt_et057090dhu, 3531 }, { 3532 .compatible = "edt,et070080dh6", 3533 .data = &edt_etm0700g0dh6, 3534 }, { 3535 .compatible = "edt,etm0700g0dh6", 3536 .data = &edt_etm0700g0dh6, 3537 }, { 3538 .compatible = "edt,etm0700g0bdh6", 3539 .data = &edt_etm0700g0bdh6, 3540 }, { 3541 .compatible = "edt,etm0700g0edh6", 3542 .data = &edt_etm0700g0bdh6, 3543 }, { 3544 .compatible = "evervision,vgg804821", 3545 .data = &evervision_vgg804821, 3546 }, { 3547 .compatible = "foxlink,fl500wvr00-a0t", 3548 .data = &foxlink_fl500wvr00_a0t, 3549 }, { 3550 .compatible = "frida,frd350h54004", 3551 .data = &frida_frd350h54004, 3552 }, { 3553 .compatible = "friendlyarm,hd702e", 3554 .data = &friendlyarm_hd702e, 3555 }, { 3556 .compatible = "giantplus,gpg482739qs5", 3557 .data = &giantplus_gpg482739qs5 3558 }, { 3559 .compatible = "giantplus,gpm940b0", 3560 .data = &giantplus_gpm940b0, 3561 }, { 3562 .compatible = "hannstar,hsd070pww1", 3563 .data = &hannstar_hsd070pww1, 3564 }, { 3565 .compatible = "hannstar,hsd100pxn1", 3566 .data = &hannstar_hsd100pxn1, 3567 }, { 3568 .compatible = "hit,tx23d38vm0caa", 3569 .data = &hitachi_tx23d38vm0caa 3570 }, { 3571 .compatible = "innolux,at043tn24", 3572 .data = &innolux_at043tn24, 3573 }, { 3574 .compatible = "innolux,at070tn92", 3575 .data = &innolux_at070tn92, 3576 }, { 3577 .compatible = "innolux,g070y2-l01", 3578 .data = &innolux_g070y2_l01, 3579 }, { 3580 .compatible = "innolux,g101ice-l01", 3581 .data = &innolux_g101ice_l01 3582 }, { 3583 .compatible = "innolux,g121i1-l01", 3584 .data = &innolux_g121i1_l01 3585 }, { 3586 .compatible = "innolux,g121x1-l03", 3587 .data = &innolux_g121x1_l03, 3588 }, { 3589 .compatible = "innolux,n116bge", 3590 .data = &innolux_n116bge, 3591 }, { 3592 .compatible = "innolux,n156bge-l21", 3593 .data = &innolux_n156bge_l21, 3594 }, { 3595 .compatible = "innolux,p120zdg-bf1", 3596 .data = &innolux_p120zdg_bf1, 3597 }, { 3598 .compatible = "innolux,zj070na-01p", 3599 .data = &innolux_zj070na_01p, 3600 }, { 3601 .compatible = "koe,tx14d24vm1bpa", 3602 .data = &koe_tx14d24vm1bpa, 3603 }, { 3604 .compatible = "koe,tx31d200vm0baa", 3605 .data = &koe_tx31d200vm0baa, 3606 }, { 3607 .compatible = "kyo,tcg121xglp", 3608 .data = &kyo_tcg121xglp, 3609 }, { 3610 .compatible = "lemaker,bl035-rgb-002", 3611 .data = &lemaker_bl035_rgb_002, 3612 }, { 3613 .compatible = "lg,lb070wv8", 3614 .data = &lg_lb070wv8, 3615 }, { 3616 .compatible = "lg,lp079qx1-sp0v", 3617 .data = &lg_lp079qx1_sp0v, 3618 }, { 3619 .compatible = "lg,lp097qx1-spa1", 3620 .data = &lg_lp097qx1_spa1, 3621 }, { 3622 .compatible = "lg,lp120up1", 3623 .data = &lg_lp120up1, 3624 }, { 3625 .compatible = "lg,lp129qe", 3626 .data = &lg_lp129qe, 3627 }, { 3628 .compatible = "logicpd,type28", 3629 .data = &logicpd_type_28, 3630 }, { 3631 .compatible = "logictechno,lt161010-2nhc", 3632 .data = &logictechno_lt161010_2nh, 3633 }, { 3634 .compatible = "logictechno,lt161010-2nhr", 3635 .data = &logictechno_lt161010_2nh, 3636 }, { 3637 .compatible = "logictechno,lt170410-2whc", 3638 .data = &logictechno_lt170410_2whc, 3639 }, { 3640 .compatible = "mitsubishi,aa070mc01-ca1", 3641 .data = &mitsubishi_aa070mc01, 3642 }, { 3643 .compatible = "nec,nl12880bc20-05", 3644 .data = &nec_nl12880bc20_05, 3645 }, { 3646 .compatible = "nec,nl4827hc19-05b", 3647 .data = &nec_nl4827hc19_05b, 3648 }, { 3649 .compatible = "netron-dy,e231732", 3650 .data = &netron_dy_e231732, 3651 }, { 3652 .compatible = "neweast,wjfh116008a", 3653 .data = &neweast_wjfh116008a, 3654 }, { 3655 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 3656 .data = &newhaven_nhd_43_480272ef_atxl, 3657 }, { 3658 .compatible = "nlt,nl192108ac18-02d", 3659 .data = &nlt_nl192108ac18_02d, 3660 }, { 3661 .compatible = "nvd,9128", 3662 .data = &nvd_9128, 3663 }, { 3664 .compatible = "okaya,rs800480t-7x0gp", 3665 .data = &okaya_rs800480t_7x0gp, 3666 }, { 3667 .compatible = "olimex,lcd-olinuxino-43-ts", 3668 .data = &olimex_lcd_olinuxino_43ts, 3669 }, { 3670 .compatible = "ontat,yx700wv03", 3671 .data = &ontat_yx700wv03, 3672 }, { 3673 .compatible = "ortustech,com37h3m05dtc", 3674 .data = &ortustech_com37h3m, 3675 }, { 3676 .compatible = "ortustech,com37h3m99dtc", 3677 .data = &ortustech_com37h3m, 3678 }, { 3679 .compatible = "ortustech,com43h4m85ulc", 3680 .data = &ortustech_com43h4m85ulc, 3681 }, { 3682 .compatible = "osddisplays,osd070t1718-19ts", 3683 .data = &osddisplays_osd070t1718_19ts, 3684 }, { 3685 .compatible = "pda,91-00156-a0", 3686 .data = &pda_91_00156_a0, 3687 }, { 3688 .compatible = "qiaodian,qd43003c0-40", 3689 .data = &qd43003c0_40, 3690 }, { 3691 .compatible = "rocktech,rk070er9427", 3692 .data = &rocktech_rk070er9427, 3693 }, { 3694 .compatible = "rocktech,rk101ii01d-ct", 3695 .data = &rocktech_rk101ii01d_ct, 3696 }, { 3697 .compatible = "samsung,lsn122dl01-c01", 3698 .data = &samsung_lsn122dl01_c01, 3699 }, { 3700 .compatible = "samsung,ltn101nt05", 3701 .data = &samsung_ltn101nt05, 3702 }, { 3703 .compatible = "samsung,ltn140at29-301", 3704 .data = &samsung_ltn140at29_301, 3705 }, { 3706 .compatible = "satoz,sat050at40h12r2", 3707 .data = &satoz_sat050at40h12r2, 3708 }, { 3709 .compatible = "sharp,ld-d5116z01b", 3710 .data = &sharp_ld_d5116z01b, 3711 }, { 3712 .compatible = "sharp,lq035q7db03", 3713 .data = &sharp_lq035q7db03, 3714 }, { 3715 .compatible = "sharp,lq070y3dg3b", 3716 .data = &sharp_lq070y3dg3b, 3717 }, { 3718 .compatible = "sharp,lq101k1ly04", 3719 .data = &sharp_lq101k1ly04, 3720 }, { 3721 .compatible = "sharp,lq123p1jx31", 3722 .data = &sharp_lq123p1jx31, 3723 }, { 3724 .compatible = "sharp,ls020b1dd01d", 3725 .data = &sharp_ls020b1dd01d, 3726 }, { 3727 .compatible = "shelly,sca07010-bfn-lnn", 3728 .data = &shelly_sca07010_bfn_lnn, 3729 }, { 3730 .compatible = "starry,kr122ea0sra", 3731 .data = &starry_kr122ea0sra, 3732 }, { 3733 .compatible = "tfc,s9700rtwv43tr-01b", 3734 .data = &tfc_s9700rtwv43tr_01b, 3735 }, { 3736 .compatible = "tianma,tm070jdhg30", 3737 .data = &tianma_tm070jdhg30, 3738 }, { 3739 .compatible = "tianma,tm070rvhg71", 3740 .data = &tianma_tm070rvhg71, 3741 }, { 3742 .compatible = "ti,nspire-cx-lcd-panel", 3743 .data = &ti_nspire_cx_lcd_panel, 3744 }, { 3745 .compatible = "ti,nspire-classic-lcd-panel", 3746 .data = &ti_nspire_classic_lcd_panel, 3747 }, { 3748 .compatible = "toshiba,lt089ac29000", 3749 .data = &toshiba_lt089ac29000, 3750 }, { 3751 .compatible = "tpk,f07a-0102", 3752 .data = &tpk_f07a_0102, 3753 }, { 3754 .compatible = "tpk,f10a-0102", 3755 .data = &tpk_f10a_0102, 3756 }, { 3757 .compatible = "urt,umsh-8596md-t", 3758 .data = &urt_umsh_8596md_parallel, 3759 }, { 3760 .compatible = "urt,umsh-8596md-1t", 3761 .data = &urt_umsh_8596md_parallel, 3762 }, { 3763 .compatible = "urt,umsh-8596md-7t", 3764 .data = &urt_umsh_8596md_parallel, 3765 }, { 3766 .compatible = "urt,umsh-8596md-11t", 3767 .data = &urt_umsh_8596md_lvds, 3768 }, { 3769 .compatible = "urt,umsh-8596md-19t", 3770 .data = &urt_umsh_8596md_lvds, 3771 }, { 3772 .compatible = "urt,umsh-8596md-20t", 3773 .data = &urt_umsh_8596md_parallel, 3774 }, { 3775 .compatible = "vxt,vl050-8048nt-c01", 3776 .data = &vl050_8048nt_c01, 3777 }, { 3778 .compatible = "winstar,wf35ltiacd", 3779 .data = &winstar_wf35ltiacd, 3780 }, { 3781 /* Must be the last entry */ 3782 .compatible = "panel-dpi", 3783 .data = &panel_dpi, 3784 }, { 3785 /* sentinel */ 3786 } 3787 }; 3788 MODULE_DEVICE_TABLE(of, platform_of_match); 3789 3790 static int panel_simple_platform_probe(struct platform_device *pdev) 3791 { 3792 const struct of_device_id *id; 3793 3794 id = of_match_node(platform_of_match, pdev->dev.of_node); 3795 if (!id) 3796 return -ENODEV; 3797 3798 return panel_simple_probe(&pdev->dev, id->data); 3799 } 3800 3801 static int panel_simple_platform_remove(struct platform_device *pdev) 3802 { 3803 return panel_simple_remove(&pdev->dev); 3804 } 3805 3806 static void panel_simple_platform_shutdown(struct platform_device *pdev) 3807 { 3808 panel_simple_shutdown(&pdev->dev); 3809 } 3810 3811 static struct platform_driver panel_simple_platform_driver = { 3812 .driver = { 3813 .name = "panel-simple", 3814 .of_match_table = platform_of_match, 3815 }, 3816 .probe = panel_simple_platform_probe, 3817 .remove = panel_simple_platform_remove, 3818 .shutdown = panel_simple_platform_shutdown, 3819 }; 3820 3821 struct panel_desc_dsi { 3822 struct panel_desc desc; 3823 3824 unsigned long flags; 3825 enum mipi_dsi_pixel_format format; 3826 unsigned int lanes; 3827 }; 3828 3829 static const struct drm_display_mode auo_b080uan01_mode = { 3830 .clock = 154500, 3831 .hdisplay = 1200, 3832 .hsync_start = 1200 + 62, 3833 .hsync_end = 1200 + 62 + 4, 3834 .htotal = 1200 + 62 + 4 + 62, 3835 .vdisplay = 1920, 3836 .vsync_start = 1920 + 9, 3837 .vsync_end = 1920 + 9 + 2, 3838 .vtotal = 1920 + 9 + 2 + 8, 3839 .vrefresh = 60, 3840 }; 3841 3842 static const struct panel_desc_dsi auo_b080uan01 = { 3843 .desc = { 3844 .modes = &auo_b080uan01_mode, 3845 .num_modes = 1, 3846 .bpc = 8, 3847 .size = { 3848 .width = 108, 3849 .height = 272, 3850 }, 3851 }, 3852 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 3853 .format = MIPI_DSI_FMT_RGB888, 3854 .lanes = 4, 3855 }; 3856 3857 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 3858 .clock = 160000, 3859 .hdisplay = 1200, 3860 .hsync_start = 1200 + 120, 3861 .hsync_end = 1200 + 120 + 20, 3862 .htotal = 1200 + 120 + 20 + 21, 3863 .vdisplay = 1920, 3864 .vsync_start = 1920 + 21, 3865 .vsync_end = 1920 + 21 + 3, 3866 .vtotal = 1920 + 21 + 3 + 18, 3867 .vrefresh = 60, 3868 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3869 }; 3870 3871 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 3872 .desc = { 3873 .modes = &boe_tv080wum_nl0_mode, 3874 .num_modes = 1, 3875 .size = { 3876 .width = 107, 3877 .height = 172, 3878 }, 3879 }, 3880 .flags = MIPI_DSI_MODE_VIDEO | 3881 MIPI_DSI_MODE_VIDEO_BURST | 3882 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 3883 .format = MIPI_DSI_FMT_RGB888, 3884 .lanes = 4, 3885 }; 3886 3887 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 3888 .clock = 71000, 3889 .hdisplay = 800, 3890 .hsync_start = 800 + 32, 3891 .hsync_end = 800 + 32 + 1, 3892 .htotal = 800 + 32 + 1 + 57, 3893 .vdisplay = 1280, 3894 .vsync_start = 1280 + 28, 3895 .vsync_end = 1280 + 28 + 1, 3896 .vtotal = 1280 + 28 + 1 + 14, 3897 .vrefresh = 60, 3898 }; 3899 3900 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 3901 .desc = { 3902 .modes = &lg_ld070wx3_sl01_mode, 3903 .num_modes = 1, 3904 .bpc = 8, 3905 .size = { 3906 .width = 94, 3907 .height = 151, 3908 }, 3909 }, 3910 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 3911 .format = MIPI_DSI_FMT_RGB888, 3912 .lanes = 4, 3913 }; 3914 3915 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 3916 .clock = 67000, 3917 .hdisplay = 720, 3918 .hsync_start = 720 + 12, 3919 .hsync_end = 720 + 12 + 4, 3920 .htotal = 720 + 12 + 4 + 112, 3921 .vdisplay = 1280, 3922 .vsync_start = 1280 + 8, 3923 .vsync_end = 1280 + 8 + 4, 3924 .vtotal = 1280 + 8 + 4 + 12, 3925 .vrefresh = 60, 3926 }; 3927 3928 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 3929 .desc = { 3930 .modes = &lg_lh500wx1_sd03_mode, 3931 .num_modes = 1, 3932 .bpc = 8, 3933 .size = { 3934 .width = 62, 3935 .height = 110, 3936 }, 3937 }, 3938 .flags = MIPI_DSI_MODE_VIDEO, 3939 .format = MIPI_DSI_FMT_RGB888, 3940 .lanes = 4, 3941 }; 3942 3943 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 3944 .clock = 157200, 3945 .hdisplay = 1920, 3946 .hsync_start = 1920 + 154, 3947 .hsync_end = 1920 + 154 + 16, 3948 .htotal = 1920 + 154 + 16 + 32, 3949 .vdisplay = 1200, 3950 .vsync_start = 1200 + 17, 3951 .vsync_end = 1200 + 17 + 2, 3952 .vtotal = 1200 + 17 + 2 + 16, 3953 .vrefresh = 60, 3954 }; 3955 3956 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 3957 .desc = { 3958 .modes = &panasonic_vvx10f004b00_mode, 3959 .num_modes = 1, 3960 .bpc = 8, 3961 .size = { 3962 .width = 217, 3963 .height = 136, 3964 }, 3965 }, 3966 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 3967 MIPI_DSI_CLOCK_NON_CONTINUOUS, 3968 .format = MIPI_DSI_FMT_RGB888, 3969 .lanes = 4, 3970 }; 3971 3972 static const struct drm_display_mode lg_acx467akm_7_mode = { 3973 .clock = 150000, 3974 .hdisplay = 1080, 3975 .hsync_start = 1080 + 2, 3976 .hsync_end = 1080 + 2 + 2, 3977 .htotal = 1080 + 2 + 2 + 2, 3978 .vdisplay = 1920, 3979 .vsync_start = 1920 + 2, 3980 .vsync_end = 1920 + 2 + 2, 3981 .vtotal = 1920 + 2 + 2 + 2, 3982 .vrefresh = 60, 3983 }; 3984 3985 static const struct panel_desc_dsi lg_acx467akm_7 = { 3986 .desc = { 3987 .modes = &lg_acx467akm_7_mode, 3988 .num_modes = 1, 3989 .bpc = 8, 3990 .size = { 3991 .width = 62, 3992 .height = 110, 3993 }, 3994 }, 3995 .flags = 0, 3996 .format = MIPI_DSI_FMT_RGB888, 3997 .lanes = 4, 3998 }; 3999 4000 static const struct drm_display_mode osd101t2045_53ts_mode = { 4001 .clock = 154500, 4002 .hdisplay = 1920, 4003 .hsync_start = 1920 + 112, 4004 .hsync_end = 1920 + 112 + 16, 4005 .htotal = 1920 + 112 + 16 + 32, 4006 .vdisplay = 1200, 4007 .vsync_start = 1200 + 16, 4008 .vsync_end = 1200 + 16 + 2, 4009 .vtotal = 1200 + 16 + 2 + 16, 4010 .vrefresh = 60, 4011 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4012 }; 4013 4014 static const struct panel_desc_dsi osd101t2045_53ts = { 4015 .desc = { 4016 .modes = &osd101t2045_53ts_mode, 4017 .num_modes = 1, 4018 .bpc = 8, 4019 .size = { 4020 .width = 217, 4021 .height = 136, 4022 }, 4023 }, 4024 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4025 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4026 MIPI_DSI_MODE_EOT_PACKET, 4027 .format = MIPI_DSI_FMT_RGB888, 4028 .lanes = 4, 4029 }; 4030 4031 static const struct of_device_id dsi_of_match[] = { 4032 { 4033 .compatible = "auo,b080uan01", 4034 .data = &auo_b080uan01 4035 }, { 4036 .compatible = "boe,tv080wum-nl0", 4037 .data = &boe_tv080wum_nl0 4038 }, { 4039 .compatible = "lg,ld070wx3-sl01", 4040 .data = &lg_ld070wx3_sl01 4041 }, { 4042 .compatible = "lg,lh500wx1-sd03", 4043 .data = &lg_lh500wx1_sd03 4044 }, { 4045 .compatible = "panasonic,vvx10f004b00", 4046 .data = &panasonic_vvx10f004b00 4047 }, { 4048 .compatible = "lg,acx467akm-7", 4049 .data = &lg_acx467akm_7 4050 }, { 4051 .compatible = "osddisplays,osd101t2045-53ts", 4052 .data = &osd101t2045_53ts 4053 }, { 4054 /* sentinel */ 4055 } 4056 }; 4057 MODULE_DEVICE_TABLE(of, dsi_of_match); 4058 4059 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4060 { 4061 const struct panel_desc_dsi *desc; 4062 const struct of_device_id *id; 4063 int err; 4064 4065 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4066 if (!id) 4067 return -ENODEV; 4068 4069 desc = id->data; 4070 4071 err = panel_simple_probe(&dsi->dev, &desc->desc); 4072 if (err < 0) 4073 return err; 4074 4075 dsi->mode_flags = desc->flags; 4076 dsi->format = desc->format; 4077 dsi->lanes = desc->lanes; 4078 4079 err = mipi_dsi_attach(dsi); 4080 if (err) { 4081 struct panel_simple *panel = dev_get_drvdata(&dsi->dev); 4082 4083 drm_panel_remove(&panel->base); 4084 } 4085 4086 return err; 4087 } 4088 4089 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4090 { 4091 int err; 4092 4093 err = mipi_dsi_detach(dsi); 4094 if (err < 0) 4095 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4096 4097 return panel_simple_remove(&dsi->dev); 4098 } 4099 4100 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4101 { 4102 panel_simple_shutdown(&dsi->dev); 4103 } 4104 4105 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4106 .driver = { 4107 .name = "panel-simple-dsi", 4108 .of_match_table = dsi_of_match, 4109 }, 4110 .probe = panel_simple_dsi_probe, 4111 .remove = panel_simple_dsi_remove, 4112 .shutdown = panel_simple_dsi_shutdown, 4113 }; 4114 4115 static int __init panel_simple_init(void) 4116 { 4117 int err; 4118 4119 err = platform_driver_register(&panel_simple_platform_driver); 4120 if (err < 0) 4121 return err; 4122 4123 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4124 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4125 if (err < 0) 4126 return err; 4127 } 4128 4129 return 0; 4130 } 4131 module_init(panel_simple_init); 4132 4133 static void __exit panel_simple_exit(void) 4134 { 4135 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4136 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4137 4138 platform_driver_unregister(&panel_simple_platform_driver); 4139 } 4140 module_exit(panel_simple_exit); 4141 4142 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4143 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4144 MODULE_LICENSE("GPL and additional rights"); 4145