1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 142 ktime_t unprepared_time; 143 144 const struct panel_desc *desc; 145 146 struct regulator *supply; 147 struct i2c_adapter *ddc; 148 149 struct gpio_desc *enable_gpio; 150 151 const struct drm_edid *drm_edid; 152 153 struct drm_display_mode override_mode; 154 155 enum drm_panel_orientation orientation; 156 }; 157 158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 159 { 160 return container_of(panel, struct panel_simple, base); 161 } 162 163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 164 struct drm_connector *connector) 165 { 166 struct drm_display_mode *mode; 167 unsigned int i, num = 0; 168 169 for (i = 0; i < panel->desc->num_timings; i++) { 170 const struct display_timing *dt = &panel->desc->timings[i]; 171 struct videomode vm; 172 173 videomode_from_timing(dt, &vm); 174 mode = drm_mode_create(connector->dev); 175 if (!mode) { 176 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 177 dt->hactive.typ, dt->vactive.typ); 178 continue; 179 } 180 181 drm_display_mode_from_videomode(&vm, mode); 182 183 mode->type |= DRM_MODE_TYPE_DRIVER; 184 185 if (panel->desc->num_timings == 1) 186 mode->type |= DRM_MODE_TYPE_PREFERRED; 187 188 drm_mode_probed_add(connector, mode); 189 num++; 190 } 191 192 return num; 193 } 194 195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 196 struct drm_connector *connector) 197 { 198 struct drm_display_mode *mode; 199 unsigned int i, num = 0; 200 201 for (i = 0; i < panel->desc->num_modes; i++) { 202 const struct drm_display_mode *m = &panel->desc->modes[i]; 203 204 mode = drm_mode_duplicate(connector->dev, m); 205 if (!mode) { 206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 207 m->hdisplay, m->vdisplay, 208 drm_mode_vrefresh(m)); 209 continue; 210 } 211 212 mode->type |= DRM_MODE_TYPE_DRIVER; 213 214 if (panel->desc->num_modes == 1) 215 mode->type |= DRM_MODE_TYPE_PREFERRED; 216 217 drm_mode_set_name(mode); 218 219 drm_mode_probed_add(connector, mode); 220 num++; 221 } 222 223 return num; 224 } 225 226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 227 struct drm_connector *connector) 228 { 229 struct drm_display_mode *mode; 230 bool has_override = panel->override_mode.type; 231 unsigned int num = 0; 232 233 if (!panel->desc) 234 return 0; 235 236 if (has_override) { 237 mode = drm_mode_duplicate(connector->dev, 238 &panel->override_mode); 239 if (mode) { 240 drm_mode_probed_add(connector, mode); 241 num = 1; 242 } else { 243 dev_err(panel->base.dev, "failed to add override mode\n"); 244 } 245 } 246 247 /* Only add timings if override was not there or failed to validate */ 248 if (num == 0 && panel->desc->num_timings) 249 num = panel_simple_get_timings_modes(panel, connector); 250 251 /* 252 * Only add fixed modes if timings/override added no mode. 253 * 254 * We should only ever have either the display timings specified 255 * or a fixed mode. Anything else is rather bogus. 256 */ 257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 258 if (num == 0) 259 num = panel_simple_get_display_modes(panel, connector); 260 261 connector->display_info.bpc = panel->desc->bpc; 262 connector->display_info.width_mm = panel->desc->size.width; 263 connector->display_info.height_mm = panel->desc->size.height; 264 if (panel->desc->bus_format) 265 drm_display_info_set_bus_formats(&connector->display_info, 266 &panel->desc->bus_format, 1); 267 connector->display_info.bus_flags = panel->desc->bus_flags; 268 269 return num; 270 } 271 272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 273 { 274 ktime_t now_ktime, min_ktime; 275 276 if (!min_ms) 277 return; 278 279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 280 now_ktime = ktime_get_boottime(); 281 282 if (ktime_before(now_ktime, min_ktime)) 283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 284 } 285 286 static int panel_simple_disable(struct drm_panel *panel) 287 { 288 struct panel_simple *p = to_panel_simple(panel); 289 290 if (p->desc->delay.disable) 291 msleep(p->desc->delay.disable); 292 293 return 0; 294 } 295 296 static int panel_simple_suspend(struct device *dev) 297 { 298 struct panel_simple *p = dev_get_drvdata(dev); 299 300 gpiod_set_value_cansleep(p->enable_gpio, 0); 301 regulator_disable(p->supply); 302 p->unprepared_time = ktime_get_boottime(); 303 304 drm_edid_free(p->drm_edid); 305 p->drm_edid = NULL; 306 307 return 0; 308 } 309 310 static int panel_simple_unprepare(struct drm_panel *panel) 311 { 312 int ret; 313 314 pm_runtime_mark_last_busy(panel->dev); 315 ret = pm_runtime_put_autosuspend(panel->dev); 316 if (ret < 0) 317 return ret; 318 319 return 0; 320 } 321 322 static int panel_simple_resume(struct device *dev) 323 { 324 struct panel_simple *p = dev_get_drvdata(dev); 325 int err; 326 327 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 328 329 err = regulator_enable(p->supply); 330 if (err < 0) { 331 dev_err(dev, "failed to enable supply: %d\n", err); 332 return err; 333 } 334 335 gpiod_set_value_cansleep(p->enable_gpio, 1); 336 337 if (p->desc->delay.prepare) 338 msleep(p->desc->delay.prepare); 339 340 return 0; 341 } 342 343 static int panel_simple_prepare(struct drm_panel *panel) 344 { 345 int ret; 346 347 ret = pm_runtime_get_sync(panel->dev); 348 if (ret < 0) { 349 pm_runtime_put_autosuspend(panel->dev); 350 return ret; 351 } 352 353 return 0; 354 } 355 356 static int panel_simple_enable(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 360 if (p->desc->delay.enable) 361 msleep(p->desc->delay.enable); 362 363 return 0; 364 } 365 366 static int panel_simple_get_modes(struct drm_panel *panel, 367 struct drm_connector *connector) 368 { 369 struct panel_simple *p = to_panel_simple(panel); 370 int num = 0; 371 372 /* probe EDID if a DDC bus is available */ 373 if (p->ddc) { 374 pm_runtime_get_sync(panel->dev); 375 376 if (!p->drm_edid) 377 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 378 379 drm_edid_connector_update(connector, p->drm_edid); 380 381 num += drm_edid_connector_add_modes(connector); 382 383 pm_runtime_mark_last_busy(panel->dev); 384 pm_runtime_put_autosuspend(panel->dev); 385 } 386 387 /* add hard-coded panel modes */ 388 num += panel_simple_get_non_edid_modes(p, connector); 389 390 /* 391 * TODO: Remove once all drm drivers call 392 * drm_connector_set_orientation_from_panel() 393 */ 394 drm_connector_set_panel_orientation(connector, p->orientation); 395 396 return num; 397 } 398 399 static int panel_simple_get_timings(struct drm_panel *panel, 400 unsigned int num_timings, 401 struct display_timing *timings) 402 { 403 struct panel_simple *p = to_panel_simple(panel); 404 unsigned int i; 405 406 if (p->desc->num_timings < num_timings) 407 num_timings = p->desc->num_timings; 408 409 if (timings) 410 for (i = 0; i < num_timings; i++) 411 timings[i] = p->desc->timings[i]; 412 413 return p->desc->num_timings; 414 } 415 416 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 417 { 418 struct panel_simple *p = to_panel_simple(panel); 419 420 return p->orientation; 421 } 422 423 static const struct drm_panel_funcs panel_simple_funcs = { 424 .disable = panel_simple_disable, 425 .unprepare = panel_simple_unprepare, 426 .prepare = panel_simple_prepare, 427 .enable = panel_simple_enable, 428 .get_modes = panel_simple_get_modes, 429 .get_orientation = panel_simple_get_orientation, 430 .get_timings = panel_simple_get_timings, 431 }; 432 433 static struct panel_desc panel_dpi; 434 435 static int panel_dpi_probe(struct device *dev, 436 struct panel_simple *panel) 437 { 438 struct display_timing *timing; 439 const struct device_node *np; 440 struct panel_desc *desc; 441 unsigned int bus_flags; 442 struct videomode vm; 443 int ret; 444 445 np = dev->of_node; 446 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 447 if (!desc) 448 return -ENOMEM; 449 450 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 451 if (!timing) 452 return -ENOMEM; 453 454 ret = of_get_display_timing(np, "panel-timing", timing); 455 if (ret < 0) { 456 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 457 np); 458 return ret; 459 } 460 461 desc->timings = timing; 462 desc->num_timings = 1; 463 464 of_property_read_u32(np, "width-mm", &desc->size.width); 465 of_property_read_u32(np, "height-mm", &desc->size.height); 466 467 /* Extract bus_flags from display_timing */ 468 bus_flags = 0; 469 vm.flags = timing->flags; 470 drm_bus_flags_from_videomode(&vm, &bus_flags); 471 desc->bus_flags = bus_flags; 472 473 /* We do not know the connector for the DT node, so guess it */ 474 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 475 476 panel->desc = desc; 477 478 return 0; 479 } 480 481 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 482 (to_check->field.typ >= bounds->field.min && \ 483 to_check->field.typ <= bounds->field.max) 484 static void panel_simple_parse_panel_timing_node(struct device *dev, 485 struct panel_simple *panel, 486 const struct display_timing *ot) 487 { 488 const struct panel_desc *desc = panel->desc; 489 struct videomode vm; 490 unsigned int i; 491 492 if (WARN_ON(desc->num_modes)) { 493 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 494 return; 495 } 496 if (WARN_ON(!desc->num_timings)) { 497 dev_err(dev, "Reject override mode: no timings specified\n"); 498 return; 499 } 500 501 for (i = 0; i < panel->desc->num_timings; i++) { 502 const struct display_timing *dt = &panel->desc->timings[i]; 503 504 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 505 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 506 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 507 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 508 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 512 continue; 513 514 if (ot->flags != dt->flags) 515 continue; 516 517 videomode_from_timing(ot, &vm); 518 drm_display_mode_from_videomode(&vm, &panel->override_mode); 519 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 520 DRM_MODE_TYPE_PREFERRED; 521 break; 522 } 523 524 if (WARN_ON(!panel->override_mode.type)) 525 dev_err(dev, "Reject override mode: No display_timing found\n"); 526 } 527 528 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 529 struct panel_simple *panel) 530 { 531 int ret, bpc; 532 533 ret = drm_of_lvds_get_data_mapping(dev->of_node); 534 if (ret < 0) { 535 if (ret == -EINVAL) 536 dev_warn(dev, "Ignore invalid data-mapping property\n"); 537 538 /* 539 * Ignore non-existing or malformatted property, fallback to 540 * default data-mapping, and return 0. 541 */ 542 return 0; 543 } 544 545 switch (ret) { 546 default: 547 WARN_ON(1); 548 fallthrough; 549 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 550 fallthrough; 551 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 552 bpc = 8; 553 break; 554 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 555 bpc = 6; 556 } 557 558 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 559 struct panel_desc *override_desc; 560 561 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 562 if (!override_desc) 563 return -ENOMEM; 564 565 override_desc->bus_format = ret; 566 override_desc->bpc = bpc; 567 panel->desc = override_desc; 568 } 569 570 return 0; 571 } 572 573 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 574 { 575 struct panel_simple *panel; 576 struct display_timing dt; 577 struct device_node *ddc; 578 int connector_type; 579 u32 bus_flags; 580 int err; 581 582 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 583 if (!panel) 584 return -ENOMEM; 585 586 panel->desc = desc; 587 588 panel->supply = devm_regulator_get(dev, "power"); 589 if (IS_ERR(panel->supply)) 590 return PTR_ERR(panel->supply); 591 592 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 593 GPIOD_OUT_LOW); 594 if (IS_ERR(panel->enable_gpio)) 595 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 596 "failed to request GPIO\n"); 597 598 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 599 if (err) { 600 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 601 return err; 602 } 603 604 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 605 if (ddc) { 606 panel->ddc = of_find_i2c_adapter_by_node(ddc); 607 of_node_put(ddc); 608 609 if (!panel->ddc) 610 return -EPROBE_DEFER; 611 } 612 613 if (desc == &panel_dpi) { 614 /* Handle the generic panel-dpi binding */ 615 err = panel_dpi_probe(dev, panel); 616 if (err) 617 goto free_ddc; 618 desc = panel->desc; 619 } else { 620 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 621 panel_simple_parse_panel_timing_node(dev, panel, &dt); 622 } 623 624 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 625 /* Optional data-mapping property for overriding bus format */ 626 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 627 if (err) 628 goto free_ddc; 629 } 630 631 connector_type = desc->connector_type; 632 /* Catch common mistakes for panels. */ 633 switch (connector_type) { 634 case 0: 635 dev_warn(dev, "Specify missing connector_type\n"); 636 connector_type = DRM_MODE_CONNECTOR_DPI; 637 break; 638 case DRM_MODE_CONNECTOR_LVDS: 639 WARN_ON(desc->bus_flags & 640 ~(DRM_BUS_FLAG_DE_LOW | 641 DRM_BUS_FLAG_DE_HIGH | 642 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 643 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 644 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 645 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 646 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 647 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 648 desc->bpc != 6); 649 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 650 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 651 desc->bpc != 8); 652 break; 653 case DRM_MODE_CONNECTOR_eDP: 654 dev_warn(dev, "eDP panels moved to panel-edp\n"); 655 err = -EINVAL; 656 goto free_ddc; 657 case DRM_MODE_CONNECTOR_DSI: 658 if (desc->bpc != 6 && desc->bpc != 8) 659 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 660 break; 661 case DRM_MODE_CONNECTOR_DPI: 662 bus_flags = DRM_BUS_FLAG_DE_LOW | 663 DRM_BUS_FLAG_DE_HIGH | 664 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 665 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 666 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 667 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 668 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 669 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 670 if (desc->bus_flags & ~bus_flags) 671 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 672 if (!(desc->bus_flags & bus_flags)) 673 dev_warn(dev, "Specify missing bus_flags\n"); 674 if (desc->bus_format == 0) 675 dev_warn(dev, "Specify missing bus_format\n"); 676 if (desc->bpc != 6 && desc->bpc != 8) 677 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 678 break; 679 default: 680 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 681 connector_type = DRM_MODE_CONNECTOR_DPI; 682 break; 683 } 684 685 dev_set_drvdata(dev, panel); 686 687 /* 688 * We use runtime PM for prepare / unprepare since those power the panel 689 * on and off and those can be very slow operations. This is important 690 * to optimize powering the panel on briefly to read the EDID before 691 * fully enabling the panel. 692 */ 693 pm_runtime_enable(dev); 694 pm_runtime_set_autosuspend_delay(dev, 1000); 695 pm_runtime_use_autosuspend(dev); 696 697 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 698 699 err = drm_panel_of_backlight(&panel->base); 700 if (err) { 701 dev_err_probe(dev, err, "Could not find backlight\n"); 702 goto disable_pm_runtime; 703 } 704 705 drm_panel_add(&panel->base); 706 707 return 0; 708 709 disable_pm_runtime: 710 pm_runtime_dont_use_autosuspend(dev); 711 pm_runtime_disable(dev); 712 free_ddc: 713 if (panel->ddc) 714 put_device(&panel->ddc->dev); 715 716 return err; 717 } 718 719 static void panel_simple_shutdown(struct device *dev) 720 { 721 struct panel_simple *panel = dev_get_drvdata(dev); 722 723 /* 724 * NOTE: the following two calls don't really belong here. It is the 725 * responsibility of a correctly written DRM modeset driver to call 726 * drm_atomic_helper_shutdown() at shutdown time and that should 727 * cause the panel to be disabled / unprepared if needed. For now, 728 * however, we'll keep these calls due to the sheer number of 729 * different DRM modeset drivers used with panel-simple. Once we've 730 * confirmed that all DRM modeset drivers using this panel properly 731 * call drm_atomic_helper_shutdown() we can simply delete the two 732 * calls below. 733 * 734 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 735 * PANEL DRIVERS. 736 * 737 * FIXME: If we're still haven't figured out if all DRM modeset 738 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 739 * managed to make sure that DRM modeset drivers get their shutdown() 740 * callback before the panel's shutdown() callback (perhaps using 741 * device link), we could add a WARN_ON here to help move forward. 742 */ 743 if (panel->base.enabled) 744 drm_panel_disable(&panel->base); 745 if (panel->base.prepared) 746 drm_panel_unprepare(&panel->base); 747 } 748 749 static void panel_simple_remove(struct device *dev) 750 { 751 struct panel_simple *panel = dev_get_drvdata(dev); 752 753 drm_panel_remove(&panel->base); 754 panel_simple_shutdown(dev); 755 756 pm_runtime_dont_use_autosuspend(dev); 757 pm_runtime_disable(dev); 758 if (panel->ddc) 759 put_device(&panel->ddc->dev); 760 } 761 762 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 763 .clock = 71100, 764 .hdisplay = 1280, 765 .hsync_start = 1280 + 40, 766 .hsync_end = 1280 + 40 + 80, 767 .htotal = 1280 + 40 + 80 + 40, 768 .vdisplay = 800, 769 .vsync_start = 800 + 3, 770 .vsync_end = 800 + 3 + 10, 771 .vtotal = 800 + 3 + 10 + 10, 772 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 773 }; 774 775 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 776 .modes = &ire_am_1280800n3tzqw_t00h_mode, 777 .num_modes = 1, 778 .bpc = 8, 779 .size = { 780 .width = 217, 781 .height = 136, 782 }, 783 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 784 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 785 .connector_type = DRM_MODE_CONNECTOR_LVDS, 786 }; 787 788 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 789 .clock = 9000, 790 .hdisplay = 480, 791 .hsync_start = 480 + 2, 792 .hsync_end = 480 + 2 + 41, 793 .htotal = 480 + 2 + 41 + 2, 794 .vdisplay = 272, 795 .vsync_start = 272 + 2, 796 .vsync_end = 272 + 2 + 10, 797 .vtotal = 272 + 2 + 10 + 2, 798 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 799 }; 800 801 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 802 .modes = &ire_am_480272h3tmqw_t01h_mode, 803 .num_modes = 1, 804 .bpc = 8, 805 .size = { 806 .width = 99, 807 .height = 58, 808 }, 809 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 810 }; 811 812 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 813 .clock = 33333, 814 .hdisplay = 800, 815 .hsync_start = 800 + 0, 816 .hsync_end = 800 + 0 + 255, 817 .htotal = 800 + 0 + 255 + 0, 818 .vdisplay = 480, 819 .vsync_start = 480 + 2, 820 .vsync_end = 480 + 2 + 45, 821 .vtotal = 480 + 2 + 45 + 0, 822 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 823 }; 824 825 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 826 .pixelclock = { 29930000, 33260000, 36590000 }, 827 .hactive = { 800, 800, 800 }, 828 .hfront_porch = { 1, 40, 168 }, 829 .hback_porch = { 88, 88, 88 }, 830 .hsync_len = { 1, 128, 128 }, 831 .vactive = { 480, 480, 480 }, 832 .vfront_porch = { 1, 35, 37 }, 833 .vback_porch = { 8, 8, 8 }, 834 .vsync_len = { 1, 2, 2 }, 835 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 836 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 837 DISPLAY_FLAGS_SYNC_POSEDGE, 838 }; 839 840 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 841 .timings = &ire_am_800480l1tmqw_t00h_timing, 842 .num_timings = 1, 843 .bpc = 8, 844 .size = { 845 .width = 111, 846 .height = 67, 847 }, 848 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 849 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 850 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 851 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 852 .connector_type = DRM_MODE_CONNECTOR_DPI, 853 }; 854 855 static const struct panel_desc ampire_am800480r3tmqwa1h = { 856 .modes = &ire_am800480r3tmqwa1h_mode, 857 .num_modes = 1, 858 .bpc = 6, 859 .size = { 860 .width = 152, 861 .height = 91, 862 }, 863 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 864 }; 865 866 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 867 .pixelclock = { 34500000, 39600000, 50400000 }, 868 .hactive = { 800, 800, 800 }, 869 .hfront_porch = { 12, 112, 312 }, 870 .hback_porch = { 87, 87, 48 }, 871 .hsync_len = { 1, 1, 40 }, 872 .vactive = { 600, 600, 600 }, 873 .vfront_porch = { 1, 21, 61 }, 874 .vback_porch = { 38, 38, 19 }, 875 .vsync_len = { 1, 1, 20 }, 876 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 877 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 878 DISPLAY_FLAGS_SYNC_POSEDGE, 879 }; 880 881 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 882 .timings = &ire_am800600p5tmqw_tb8h_timing, 883 .num_timings = 1, 884 .bpc = 6, 885 .size = { 886 .width = 162, 887 .height = 122, 888 }, 889 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 890 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 891 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 892 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 893 .connector_type = DRM_MODE_CONNECTOR_DPI, 894 }; 895 896 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 897 .pixelclock = { 26400000, 33300000, 46800000 }, 898 .hactive = { 800, 800, 800 }, 899 .hfront_porch = { 16, 210, 354 }, 900 .hback_porch = { 45, 36, 6 }, 901 .hsync_len = { 1, 10, 40 }, 902 .vactive = { 480, 480, 480 }, 903 .vfront_porch = { 7, 22, 147 }, 904 .vback_porch = { 22, 13, 3 }, 905 .vsync_len = { 1, 10, 20 }, 906 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 907 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 908 }; 909 910 static const struct panel_desc armadeus_st0700_adapt = { 911 .timings = &santek_st0700i5y_rbslw_f_timing, 912 .num_timings = 1, 913 .bpc = 6, 914 .size = { 915 .width = 154, 916 .height = 86, 917 }, 918 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 919 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 920 }; 921 922 static const struct drm_display_mode auo_b101aw03_mode = { 923 .clock = 51450, 924 .hdisplay = 1024, 925 .hsync_start = 1024 + 156, 926 .hsync_end = 1024 + 156 + 8, 927 .htotal = 1024 + 156 + 8 + 156, 928 .vdisplay = 600, 929 .vsync_start = 600 + 16, 930 .vsync_end = 600 + 16 + 6, 931 .vtotal = 600 + 16 + 6 + 16, 932 }; 933 934 static const struct panel_desc auo_b101aw03 = { 935 .modes = &auo_b101aw03_mode, 936 .num_modes = 1, 937 .bpc = 6, 938 .size = { 939 .width = 223, 940 .height = 125, 941 }, 942 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 943 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 944 .connector_type = DRM_MODE_CONNECTOR_LVDS, 945 }; 946 947 static const struct drm_display_mode auo_b101xtn01_mode = { 948 .clock = 72000, 949 .hdisplay = 1366, 950 .hsync_start = 1366 + 20, 951 .hsync_end = 1366 + 20 + 70, 952 .htotal = 1366 + 20 + 70, 953 .vdisplay = 768, 954 .vsync_start = 768 + 14, 955 .vsync_end = 768 + 14 + 42, 956 .vtotal = 768 + 14 + 42, 957 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 958 }; 959 960 static const struct panel_desc auo_b101xtn01 = { 961 .modes = &auo_b101xtn01_mode, 962 .num_modes = 1, 963 .bpc = 6, 964 .size = { 965 .width = 223, 966 .height = 125, 967 }, 968 }; 969 970 static const struct drm_display_mode auo_b116xw03_mode = { 971 .clock = 70589, 972 .hdisplay = 1366, 973 .hsync_start = 1366 + 40, 974 .hsync_end = 1366 + 40 + 40, 975 .htotal = 1366 + 40 + 40 + 32, 976 .vdisplay = 768, 977 .vsync_start = 768 + 10, 978 .vsync_end = 768 + 10 + 12, 979 .vtotal = 768 + 10 + 12 + 6, 980 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 981 }; 982 983 static const struct panel_desc auo_b116xw03 = { 984 .modes = &auo_b116xw03_mode, 985 .num_modes = 1, 986 .bpc = 6, 987 .size = { 988 .width = 256, 989 .height = 144, 990 }, 991 .delay = { 992 .prepare = 1, 993 .enable = 200, 994 .disable = 200, 995 .unprepare = 500, 996 }, 997 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 998 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 999 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1000 }; 1001 1002 static const struct display_timing auo_g070vvn01_timings = { 1003 .pixelclock = { 33300000, 34209000, 45000000 }, 1004 .hactive = { 800, 800, 800 }, 1005 .hfront_porch = { 20, 40, 200 }, 1006 .hback_porch = { 87, 40, 1 }, 1007 .hsync_len = { 1, 48, 87 }, 1008 .vactive = { 480, 480, 480 }, 1009 .vfront_porch = { 5, 13, 200 }, 1010 .vback_porch = { 31, 31, 29 }, 1011 .vsync_len = { 1, 1, 3 }, 1012 }; 1013 1014 static const struct panel_desc auo_g070vvn01 = { 1015 .timings = &auo_g070vvn01_timings, 1016 .num_timings = 1, 1017 .bpc = 8, 1018 .size = { 1019 .width = 152, 1020 .height = 91, 1021 }, 1022 .delay = { 1023 .prepare = 200, 1024 .enable = 50, 1025 .disable = 50, 1026 .unprepare = 1000, 1027 }, 1028 }; 1029 1030 static const struct drm_display_mode auo_g101evn010_mode = { 1031 .clock = 68930, 1032 .hdisplay = 1280, 1033 .hsync_start = 1280 + 82, 1034 .hsync_end = 1280 + 82 + 2, 1035 .htotal = 1280 + 82 + 2 + 84, 1036 .vdisplay = 800, 1037 .vsync_start = 800 + 8, 1038 .vsync_end = 800 + 8 + 2, 1039 .vtotal = 800 + 8 + 2 + 6, 1040 }; 1041 1042 static const struct panel_desc auo_g101evn010 = { 1043 .modes = &auo_g101evn010_mode, 1044 .num_modes = 1, 1045 .bpc = 6, 1046 .size = { 1047 .width = 216, 1048 .height = 135, 1049 }, 1050 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1051 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1052 }; 1053 1054 static const struct drm_display_mode auo_g104sn02_mode = { 1055 .clock = 40000, 1056 .hdisplay = 800, 1057 .hsync_start = 800 + 40, 1058 .hsync_end = 800 + 40 + 216, 1059 .htotal = 800 + 40 + 216 + 128, 1060 .vdisplay = 600, 1061 .vsync_start = 600 + 10, 1062 .vsync_end = 600 + 10 + 35, 1063 .vtotal = 600 + 10 + 35 + 2, 1064 }; 1065 1066 static const struct panel_desc auo_g104sn02 = { 1067 .modes = &auo_g104sn02_mode, 1068 .num_modes = 1, 1069 .bpc = 8, 1070 .size = { 1071 .width = 211, 1072 .height = 158, 1073 }, 1074 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1075 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1076 }; 1077 1078 static const struct drm_display_mode auo_g104stn01_mode = { 1079 .clock = 40000, 1080 .hdisplay = 800, 1081 .hsync_start = 800 + 40, 1082 .hsync_end = 800 + 40 + 88, 1083 .htotal = 800 + 40 + 88 + 128, 1084 .vdisplay = 600, 1085 .vsync_start = 600 + 1, 1086 .vsync_end = 600 + 1 + 23, 1087 .vtotal = 600 + 1 + 23 + 4, 1088 }; 1089 1090 static const struct panel_desc auo_g104stn01 = { 1091 .modes = &auo_g104stn01_mode, 1092 .num_modes = 1, 1093 .bpc = 8, 1094 .size = { 1095 .width = 211, 1096 .height = 158, 1097 }, 1098 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1099 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1100 }; 1101 1102 static const struct display_timing auo_g121ean01_timing = { 1103 .pixelclock = { 60000000, 74400000, 90000000 }, 1104 .hactive = { 1280, 1280, 1280 }, 1105 .hfront_porch = { 20, 50, 100 }, 1106 .hback_porch = { 20, 50, 100 }, 1107 .hsync_len = { 30, 100, 200 }, 1108 .vactive = { 800, 800, 800 }, 1109 .vfront_porch = { 2, 10, 25 }, 1110 .vback_porch = { 2, 10, 25 }, 1111 .vsync_len = { 4, 18, 50 }, 1112 }; 1113 1114 static const struct panel_desc auo_g121ean01 = { 1115 .timings = &auo_g121ean01_timing, 1116 .num_timings = 1, 1117 .bpc = 8, 1118 .size = { 1119 .width = 261, 1120 .height = 163, 1121 }, 1122 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1123 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1124 }; 1125 1126 static const struct display_timing auo_g133han01_timings = { 1127 .pixelclock = { 134000000, 141200000, 149000000 }, 1128 .hactive = { 1920, 1920, 1920 }, 1129 .hfront_porch = { 39, 58, 77 }, 1130 .hback_porch = { 59, 88, 117 }, 1131 .hsync_len = { 28, 42, 56 }, 1132 .vactive = { 1080, 1080, 1080 }, 1133 .vfront_porch = { 3, 8, 11 }, 1134 .vback_porch = { 5, 14, 19 }, 1135 .vsync_len = { 4, 14, 19 }, 1136 }; 1137 1138 static const struct panel_desc auo_g133han01 = { 1139 .timings = &auo_g133han01_timings, 1140 .num_timings = 1, 1141 .bpc = 8, 1142 .size = { 1143 .width = 293, 1144 .height = 165, 1145 }, 1146 .delay = { 1147 .prepare = 200, 1148 .enable = 50, 1149 .disable = 50, 1150 .unprepare = 1000, 1151 }, 1152 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1153 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1154 }; 1155 1156 static const struct display_timing auo_g156han04_timings = { 1157 .pixelclock = { 137000000, 141000000, 146000000 }, 1158 .hactive = { 1920, 1920, 1920 }, 1159 .hfront_porch = { 60, 60, 60 }, 1160 .hback_porch = { 90, 92, 111 }, 1161 .hsync_len = { 32, 32, 32 }, 1162 .vactive = { 1080, 1080, 1080 }, 1163 .vfront_porch = { 12, 12, 12 }, 1164 .vback_porch = { 24, 36, 56 }, 1165 .vsync_len = { 8, 8, 8 }, 1166 }; 1167 1168 static const struct panel_desc auo_g156han04 = { 1169 .timings = &auo_g156han04_timings, 1170 .num_timings = 1, 1171 .bpc = 8, 1172 .size = { 1173 .width = 344, 1174 .height = 194, 1175 }, 1176 .delay = { 1177 .prepare = 50, /* T2 */ 1178 .enable = 200, /* T3 */ 1179 .disable = 110, /* T10 */ 1180 .unprepare = 1000, /* T13 */ 1181 }, 1182 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1183 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1184 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1185 }; 1186 1187 static const struct drm_display_mode auo_g156xtn01_mode = { 1188 .clock = 76000, 1189 .hdisplay = 1366, 1190 .hsync_start = 1366 + 33, 1191 .hsync_end = 1366 + 33 + 67, 1192 .htotal = 1560, 1193 .vdisplay = 768, 1194 .vsync_start = 768 + 4, 1195 .vsync_end = 768 + 4 + 4, 1196 .vtotal = 806, 1197 }; 1198 1199 static const struct panel_desc auo_g156xtn01 = { 1200 .modes = &auo_g156xtn01_mode, 1201 .num_modes = 1, 1202 .bpc = 8, 1203 .size = { 1204 .width = 344, 1205 .height = 194, 1206 }, 1207 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1208 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1209 }; 1210 1211 static const struct display_timing auo_g185han01_timings = { 1212 .pixelclock = { 120000000, 144000000, 175000000 }, 1213 .hactive = { 1920, 1920, 1920 }, 1214 .hfront_porch = { 36, 120, 148 }, 1215 .hback_porch = { 24, 88, 108 }, 1216 .hsync_len = { 20, 48, 64 }, 1217 .vactive = { 1080, 1080, 1080 }, 1218 .vfront_porch = { 6, 10, 40 }, 1219 .vback_porch = { 2, 5, 20 }, 1220 .vsync_len = { 2, 5, 20 }, 1221 }; 1222 1223 static const struct panel_desc auo_g185han01 = { 1224 .timings = &auo_g185han01_timings, 1225 .num_timings = 1, 1226 .bpc = 8, 1227 .size = { 1228 .width = 409, 1229 .height = 230, 1230 }, 1231 .delay = { 1232 .prepare = 50, 1233 .enable = 200, 1234 .disable = 110, 1235 .unprepare = 1000, 1236 }, 1237 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1238 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1239 }; 1240 1241 static const struct display_timing auo_g190ean01_timings = { 1242 .pixelclock = { 90000000, 108000000, 135000000 }, 1243 .hactive = { 1280, 1280, 1280 }, 1244 .hfront_porch = { 126, 184, 1266 }, 1245 .hback_porch = { 84, 122, 844 }, 1246 .hsync_len = { 70, 102, 704 }, 1247 .vactive = { 1024, 1024, 1024 }, 1248 .vfront_porch = { 4, 26, 76 }, 1249 .vback_porch = { 2, 8, 25 }, 1250 .vsync_len = { 2, 8, 25 }, 1251 }; 1252 1253 static const struct panel_desc auo_g190ean01 = { 1254 .timings = &auo_g190ean01_timings, 1255 .num_timings = 1, 1256 .bpc = 8, 1257 .size = { 1258 .width = 376, 1259 .height = 301, 1260 }, 1261 .delay = { 1262 .prepare = 50, 1263 .enable = 200, 1264 .disable = 110, 1265 .unprepare = 1000, 1266 }, 1267 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1268 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1269 }; 1270 1271 static const struct display_timing auo_p320hvn03_timings = { 1272 .pixelclock = { 106000000, 148500000, 164000000 }, 1273 .hactive = { 1920, 1920, 1920 }, 1274 .hfront_porch = { 25, 50, 130 }, 1275 .hback_porch = { 25, 50, 130 }, 1276 .hsync_len = { 20, 40, 105 }, 1277 .vactive = { 1080, 1080, 1080 }, 1278 .vfront_porch = { 8, 17, 150 }, 1279 .vback_porch = { 8, 17, 150 }, 1280 .vsync_len = { 4, 11, 100 }, 1281 }; 1282 1283 static const struct panel_desc auo_p320hvn03 = { 1284 .timings = &auo_p320hvn03_timings, 1285 .num_timings = 1, 1286 .bpc = 8, 1287 .size = { 1288 .width = 698, 1289 .height = 393, 1290 }, 1291 .delay = { 1292 .prepare = 1, 1293 .enable = 450, 1294 .unprepare = 500, 1295 }, 1296 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1297 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1298 }; 1299 1300 static const struct drm_display_mode auo_t215hvn01_mode = { 1301 .clock = 148800, 1302 .hdisplay = 1920, 1303 .hsync_start = 1920 + 88, 1304 .hsync_end = 1920 + 88 + 44, 1305 .htotal = 1920 + 88 + 44 + 148, 1306 .vdisplay = 1080, 1307 .vsync_start = 1080 + 4, 1308 .vsync_end = 1080 + 4 + 5, 1309 .vtotal = 1080 + 4 + 5 + 36, 1310 }; 1311 1312 static const struct panel_desc auo_t215hvn01 = { 1313 .modes = &auo_t215hvn01_mode, 1314 .num_modes = 1, 1315 .bpc = 8, 1316 .size = { 1317 .width = 430, 1318 .height = 270, 1319 }, 1320 .delay = { 1321 .disable = 5, 1322 .unprepare = 1000, 1323 }, 1324 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1325 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1326 }; 1327 1328 static const struct drm_display_mode avic_tm070ddh03_mode = { 1329 .clock = 51200, 1330 .hdisplay = 1024, 1331 .hsync_start = 1024 + 160, 1332 .hsync_end = 1024 + 160 + 4, 1333 .htotal = 1024 + 160 + 4 + 156, 1334 .vdisplay = 600, 1335 .vsync_start = 600 + 17, 1336 .vsync_end = 600 + 17 + 1, 1337 .vtotal = 600 + 17 + 1 + 17, 1338 }; 1339 1340 static const struct panel_desc avic_tm070ddh03 = { 1341 .modes = &avic_tm070ddh03_mode, 1342 .num_modes = 1, 1343 .bpc = 8, 1344 .size = { 1345 .width = 154, 1346 .height = 90, 1347 }, 1348 .delay = { 1349 .prepare = 20, 1350 .enable = 200, 1351 .disable = 200, 1352 }, 1353 }; 1354 1355 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1356 .clock = 30000, 1357 .hdisplay = 800, 1358 .hsync_start = 800 + 40, 1359 .hsync_end = 800 + 40 + 48, 1360 .htotal = 800 + 40 + 48 + 40, 1361 .vdisplay = 480, 1362 .vsync_start = 480 + 13, 1363 .vsync_end = 480 + 13 + 3, 1364 .vtotal = 480 + 13 + 3 + 29, 1365 }; 1366 1367 static const struct panel_desc bananapi_s070wv20_ct16 = { 1368 .modes = &bananapi_s070wv20_ct16_mode, 1369 .num_modes = 1, 1370 .bpc = 6, 1371 .size = { 1372 .width = 154, 1373 .height = 86, 1374 }, 1375 }; 1376 1377 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1378 .clock = 78945, 1379 .hdisplay = 1280, 1380 .hsync_start = 1280 + 0, 1381 .hsync_end = 1280 + 0 + 2, 1382 .htotal = 1280 + 62 + 0 + 2, 1383 .vdisplay = 800, 1384 .vsync_start = 800 + 8, 1385 .vsync_end = 800 + 8 + 2, 1386 .vtotal = 800 + 6 + 8 + 2, 1387 }; 1388 1389 static const struct panel_desc boe_bp082wx1_100 = { 1390 .modes = &boe_bp101wx1_100_mode, 1391 .num_modes = 1, 1392 .bpc = 8, 1393 .size = { 1394 .width = 177, 1395 .height = 110, 1396 }, 1397 .delay = { 1398 .enable = 50, 1399 .disable = 50, 1400 }, 1401 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1402 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1403 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1404 }; 1405 1406 static const struct panel_desc boe_bp101wx1_100 = { 1407 .modes = &boe_bp101wx1_100_mode, 1408 .num_modes = 1, 1409 .bpc = 8, 1410 .size = { 1411 .width = 217, 1412 .height = 136, 1413 }, 1414 .delay = { 1415 .enable = 50, 1416 .disable = 50, 1417 }, 1418 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1419 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1420 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1421 }; 1422 1423 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1424 .pixelclock = { 69922000, 71000000, 72293000 }, 1425 .hactive = { 1280, 1280, 1280 }, 1426 .hfront_porch = { 48, 48, 48 }, 1427 .hback_porch = { 80, 80, 80 }, 1428 .hsync_len = { 32, 32, 32 }, 1429 .vactive = { 800, 800, 800 }, 1430 .vfront_porch = { 3, 3, 3 }, 1431 .vback_porch = { 14, 14, 14 }, 1432 .vsync_len = { 6, 6, 6 }, 1433 }; 1434 1435 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1436 .timings = &boe_ev121wxm_n10_1850_timing, 1437 .num_timings = 1, 1438 .bpc = 8, 1439 .size = { 1440 .width = 261, 1441 .height = 163, 1442 }, 1443 .delay = { 1444 .prepare = 9, 1445 .enable = 300, 1446 .unprepare = 300, 1447 .disable = 560, 1448 }, 1449 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1450 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1451 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1452 }; 1453 1454 static const struct drm_display_mode boe_hv070wsa_mode = { 1455 .clock = 42105, 1456 .hdisplay = 1024, 1457 .hsync_start = 1024 + 30, 1458 .hsync_end = 1024 + 30 + 30, 1459 .htotal = 1024 + 30 + 30 + 30, 1460 .vdisplay = 600, 1461 .vsync_start = 600 + 10, 1462 .vsync_end = 600 + 10 + 10, 1463 .vtotal = 600 + 10 + 10 + 10, 1464 }; 1465 1466 static const struct panel_desc boe_hv070wsa = { 1467 .modes = &boe_hv070wsa_mode, 1468 .num_modes = 1, 1469 .bpc = 8, 1470 .size = { 1471 .width = 154, 1472 .height = 90, 1473 }, 1474 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1475 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1476 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1477 }; 1478 1479 static const struct display_timing cct_cmt430b19n00_timing = { 1480 .pixelclock = { 8000000, 9000000, 12000000 }, 1481 .hactive = { 480, 480, 480 }, 1482 .hfront_porch = { 2, 8, 75 }, 1483 .hback_porch = { 3, 43, 43 }, 1484 .hsync_len = { 2, 4, 75 }, 1485 .vactive = { 272, 272, 272 }, 1486 .vfront_porch = { 2, 8, 37 }, 1487 .vback_porch = { 2, 12, 12 }, 1488 .vsync_len = { 2, 4, 37 }, 1489 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1490 }; 1491 1492 static const struct panel_desc cct_cmt430b19n00 = { 1493 .timings = &cct_cmt430b19n00_timing, 1494 .num_timings = 1, 1495 .bpc = 8, 1496 .size = { 1497 .width = 95, 1498 .height = 53, 1499 }, 1500 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1501 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1502 .connector_type = DRM_MODE_CONNECTOR_DPI, 1503 }; 1504 1505 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1506 .clock = 9000, 1507 .hdisplay = 480, 1508 .hsync_start = 480 + 5, 1509 .hsync_end = 480 + 5 + 5, 1510 .htotal = 480 + 5 + 5 + 40, 1511 .vdisplay = 272, 1512 .vsync_start = 272 + 8, 1513 .vsync_end = 272 + 8 + 8, 1514 .vtotal = 272 + 8 + 8 + 8, 1515 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1516 }; 1517 1518 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1519 .modes = &cdtech_s043wq26h_ct7_mode, 1520 .num_modes = 1, 1521 .bpc = 8, 1522 .size = { 1523 .width = 95, 1524 .height = 54, 1525 }, 1526 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1527 }; 1528 1529 /* S070PWS19HP-FC21 2017/04/22 */ 1530 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1531 .clock = 51200, 1532 .hdisplay = 1024, 1533 .hsync_start = 1024 + 160, 1534 .hsync_end = 1024 + 160 + 20, 1535 .htotal = 1024 + 160 + 20 + 140, 1536 .vdisplay = 600, 1537 .vsync_start = 600 + 12, 1538 .vsync_end = 600 + 12 + 3, 1539 .vtotal = 600 + 12 + 3 + 20, 1540 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1541 }; 1542 1543 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1544 .modes = &cdtech_s070pws19hp_fc21_mode, 1545 .num_modes = 1, 1546 .bpc = 6, 1547 .size = { 1548 .width = 154, 1549 .height = 86, 1550 }, 1551 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1552 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1553 .connector_type = DRM_MODE_CONNECTOR_DPI, 1554 }; 1555 1556 /* S070SWV29HG-DC44 2017/09/21 */ 1557 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1558 .clock = 33300, 1559 .hdisplay = 800, 1560 .hsync_start = 800 + 210, 1561 .hsync_end = 800 + 210 + 2, 1562 .htotal = 800 + 210 + 2 + 44, 1563 .vdisplay = 480, 1564 .vsync_start = 480 + 22, 1565 .vsync_end = 480 + 22 + 2, 1566 .vtotal = 480 + 22 + 2 + 21, 1567 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1568 }; 1569 1570 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1571 .modes = &cdtech_s070swv29hg_dc44_mode, 1572 .num_modes = 1, 1573 .bpc = 6, 1574 .size = { 1575 .width = 154, 1576 .height = 86, 1577 }, 1578 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1579 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1580 .connector_type = DRM_MODE_CONNECTOR_DPI, 1581 }; 1582 1583 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1584 .clock = 35000, 1585 .hdisplay = 800, 1586 .hsync_start = 800 + 40, 1587 .hsync_end = 800 + 40 + 40, 1588 .htotal = 800 + 40 + 40 + 48, 1589 .vdisplay = 480, 1590 .vsync_start = 480 + 29, 1591 .vsync_end = 480 + 29 + 13, 1592 .vtotal = 480 + 29 + 13 + 3, 1593 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1594 }; 1595 1596 static const struct panel_desc cdtech_s070wv95_ct16 = { 1597 .modes = &cdtech_s070wv95_ct16_mode, 1598 .num_modes = 1, 1599 .bpc = 8, 1600 .size = { 1601 .width = 154, 1602 .height = 85, 1603 }, 1604 }; 1605 1606 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1607 .pixelclock = { 68900000, 71100000, 73400000 }, 1608 .hactive = { 1280, 1280, 1280 }, 1609 .hfront_porch = { 65, 80, 95 }, 1610 .hback_porch = { 64, 79, 94 }, 1611 .hsync_len = { 1, 1, 1 }, 1612 .vactive = { 800, 800, 800 }, 1613 .vfront_porch = { 7, 11, 14 }, 1614 .vback_porch = { 7, 11, 14 }, 1615 .vsync_len = { 1, 1, 1 }, 1616 .flags = DISPLAY_FLAGS_DE_HIGH, 1617 }; 1618 1619 static const struct panel_desc chefree_ch101olhlwh_002 = { 1620 .timings = &chefree_ch101olhlwh_002_timing, 1621 .num_timings = 1, 1622 .bpc = 8, 1623 .size = { 1624 .width = 217, 1625 .height = 135, 1626 }, 1627 .delay = { 1628 .enable = 200, 1629 .disable = 200, 1630 }, 1631 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1632 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1633 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1634 }; 1635 1636 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1637 .clock = 66770, 1638 .hdisplay = 800, 1639 .hsync_start = 800 + 49, 1640 .hsync_end = 800 + 49 + 33, 1641 .htotal = 800 + 49 + 33 + 17, 1642 .vdisplay = 1280, 1643 .vsync_start = 1280 + 1, 1644 .vsync_end = 1280 + 1 + 7, 1645 .vtotal = 1280 + 1 + 7 + 15, 1646 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1647 }; 1648 1649 static const struct panel_desc chunghwa_claa070wp03xg = { 1650 .modes = &chunghwa_claa070wp03xg_mode, 1651 .num_modes = 1, 1652 .bpc = 6, 1653 .size = { 1654 .width = 94, 1655 .height = 150, 1656 }, 1657 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1658 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1659 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1660 }; 1661 1662 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1663 .clock = 72070, 1664 .hdisplay = 1366, 1665 .hsync_start = 1366 + 58, 1666 .hsync_end = 1366 + 58 + 58, 1667 .htotal = 1366 + 58 + 58 + 58, 1668 .vdisplay = 768, 1669 .vsync_start = 768 + 4, 1670 .vsync_end = 768 + 4 + 4, 1671 .vtotal = 768 + 4 + 4 + 4, 1672 }; 1673 1674 static const struct panel_desc chunghwa_claa101wa01a = { 1675 .modes = &chunghwa_claa101wa01a_mode, 1676 .num_modes = 1, 1677 .bpc = 6, 1678 .size = { 1679 .width = 220, 1680 .height = 120, 1681 }, 1682 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1683 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1684 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1685 }; 1686 1687 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1688 .clock = 69300, 1689 .hdisplay = 1366, 1690 .hsync_start = 1366 + 48, 1691 .hsync_end = 1366 + 48 + 32, 1692 .htotal = 1366 + 48 + 32 + 20, 1693 .vdisplay = 768, 1694 .vsync_start = 768 + 16, 1695 .vsync_end = 768 + 16 + 8, 1696 .vtotal = 768 + 16 + 8 + 16, 1697 }; 1698 1699 static const struct panel_desc chunghwa_claa101wb01 = { 1700 .modes = &chunghwa_claa101wb01_mode, 1701 .num_modes = 1, 1702 .bpc = 6, 1703 .size = { 1704 .width = 223, 1705 .height = 125, 1706 }, 1707 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1708 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1709 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1710 }; 1711 1712 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1713 .pixelclock = { 5000000, 9000000, 12000000 }, 1714 .hactive = { 480, 480, 480 }, 1715 .hfront_porch = { 12, 12, 12 }, 1716 .hback_porch = { 12, 12, 12 }, 1717 .hsync_len = { 21, 21, 21 }, 1718 .vactive = { 272, 272, 272 }, 1719 .vfront_porch = { 4, 4, 4 }, 1720 .vback_porch = { 4, 4, 4 }, 1721 .vsync_len = { 8, 8, 8 }, 1722 }; 1723 1724 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1725 .timings = &dataimage_fg040346dsswbg04_timing, 1726 .num_timings = 1, 1727 .bpc = 8, 1728 .size = { 1729 .width = 95, 1730 .height = 54, 1731 }, 1732 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1733 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1734 .connector_type = DRM_MODE_CONNECTOR_DPI, 1735 }; 1736 1737 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1738 .pixelclock = { 68900000, 71110000, 73400000 }, 1739 .hactive = { 1280, 1280, 1280 }, 1740 .vactive = { 800, 800, 800 }, 1741 .hback_porch = { 100, 100, 100 }, 1742 .hfront_porch = { 100, 100, 100 }, 1743 .vback_porch = { 5, 5, 5 }, 1744 .vfront_porch = { 5, 5, 5 }, 1745 .hsync_len = { 24, 24, 24 }, 1746 .vsync_len = { 3, 3, 3 }, 1747 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1748 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1749 }; 1750 1751 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1752 .timings = &dataimage_fg1001l0dsswmg01_timing, 1753 .num_timings = 1, 1754 .bpc = 8, 1755 .size = { 1756 .width = 217, 1757 .height = 136, 1758 }, 1759 }; 1760 1761 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1762 .clock = 33260, 1763 .hdisplay = 800, 1764 .hsync_start = 800 + 40, 1765 .hsync_end = 800 + 40 + 128, 1766 .htotal = 800 + 40 + 128 + 88, 1767 .vdisplay = 480, 1768 .vsync_start = 480 + 10, 1769 .vsync_end = 480 + 10 + 2, 1770 .vtotal = 480 + 10 + 2 + 33, 1771 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1772 }; 1773 1774 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1775 .modes = &dataimage_scf0700c48ggu18_mode, 1776 .num_modes = 1, 1777 .bpc = 8, 1778 .size = { 1779 .width = 152, 1780 .height = 91, 1781 }, 1782 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1783 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1784 }; 1785 1786 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1787 .pixelclock = { 45000000, 51200000, 57000000 }, 1788 .hactive = { 1024, 1024, 1024 }, 1789 .hfront_porch = { 100, 106, 113 }, 1790 .hback_porch = { 100, 106, 113 }, 1791 .hsync_len = { 100, 108, 114 }, 1792 .vactive = { 600, 600, 600 }, 1793 .vfront_porch = { 8, 11, 15 }, 1794 .vback_porch = { 8, 11, 15 }, 1795 .vsync_len = { 9, 13, 15 }, 1796 .flags = DISPLAY_FLAGS_DE_HIGH, 1797 }; 1798 1799 static const struct panel_desc dlc_dlc0700yzg_1 = { 1800 .timings = &dlc_dlc0700yzg_1_timing, 1801 .num_timings = 1, 1802 .bpc = 6, 1803 .size = { 1804 .width = 154, 1805 .height = 86, 1806 }, 1807 .delay = { 1808 .prepare = 30, 1809 .enable = 200, 1810 .disable = 200, 1811 }, 1812 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1813 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1814 }; 1815 1816 static const struct display_timing dlc_dlc1010gig_timing = { 1817 .pixelclock = { 68900000, 71100000, 73400000 }, 1818 .hactive = { 1280, 1280, 1280 }, 1819 .hfront_porch = { 43, 53, 63 }, 1820 .hback_porch = { 43, 53, 63 }, 1821 .hsync_len = { 44, 54, 64 }, 1822 .vactive = { 800, 800, 800 }, 1823 .vfront_porch = { 5, 8, 11 }, 1824 .vback_porch = { 5, 8, 11 }, 1825 .vsync_len = { 5, 7, 11 }, 1826 .flags = DISPLAY_FLAGS_DE_HIGH, 1827 }; 1828 1829 static const struct panel_desc dlc_dlc1010gig = { 1830 .timings = &dlc_dlc1010gig_timing, 1831 .num_timings = 1, 1832 .bpc = 8, 1833 .size = { 1834 .width = 216, 1835 .height = 135, 1836 }, 1837 .delay = { 1838 .prepare = 60, 1839 .enable = 150, 1840 .disable = 100, 1841 .unprepare = 60, 1842 }, 1843 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1844 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1845 }; 1846 1847 static const struct drm_display_mode edt_et035012dm6_mode = { 1848 .clock = 6500, 1849 .hdisplay = 320, 1850 .hsync_start = 320 + 20, 1851 .hsync_end = 320 + 20 + 30, 1852 .htotal = 320 + 20 + 68, 1853 .vdisplay = 240, 1854 .vsync_start = 240 + 4, 1855 .vsync_end = 240 + 4 + 4, 1856 .vtotal = 240 + 4 + 4 + 14, 1857 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1858 }; 1859 1860 static const struct panel_desc edt_et035012dm6 = { 1861 .modes = &edt_et035012dm6_mode, 1862 .num_modes = 1, 1863 .bpc = 8, 1864 .size = { 1865 .width = 70, 1866 .height = 52, 1867 }, 1868 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1869 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1870 }; 1871 1872 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1873 .clock = 6520, 1874 .hdisplay = 320, 1875 .hsync_start = 320 + 20, 1876 .hsync_end = 320 + 20 + 68, 1877 .htotal = 320 + 20 + 68, 1878 .vdisplay = 240, 1879 .vsync_start = 240 + 4, 1880 .vsync_end = 240 + 4 + 18, 1881 .vtotal = 240 + 4 + 18, 1882 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1883 }; 1884 1885 static const struct panel_desc edt_etm0350g0dh6 = { 1886 .modes = &edt_etm0350g0dh6_mode, 1887 .num_modes = 1, 1888 .bpc = 6, 1889 .size = { 1890 .width = 70, 1891 .height = 53, 1892 }, 1893 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1894 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1895 .connector_type = DRM_MODE_CONNECTOR_DPI, 1896 }; 1897 1898 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1899 .clock = 10870, 1900 .hdisplay = 480, 1901 .hsync_start = 480 + 8, 1902 .hsync_end = 480 + 8 + 4, 1903 .htotal = 480 + 8 + 4 + 41, 1904 1905 /* 1906 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1907 * fb_align 1908 */ 1909 1910 .vdisplay = 288, 1911 .vsync_start = 288 + 2, 1912 .vsync_end = 288 + 2 + 4, 1913 .vtotal = 288 + 2 + 4 + 10, 1914 }; 1915 1916 static const struct panel_desc edt_etm043080dh6gp = { 1917 .modes = &edt_etm043080dh6gp_mode, 1918 .num_modes = 1, 1919 .bpc = 8, 1920 .size = { 1921 .width = 100, 1922 .height = 65, 1923 }, 1924 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1925 .connector_type = DRM_MODE_CONNECTOR_DPI, 1926 }; 1927 1928 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1929 .clock = 9000, 1930 .hdisplay = 480, 1931 .hsync_start = 480 + 2, 1932 .hsync_end = 480 + 2 + 41, 1933 .htotal = 480 + 2 + 41 + 2, 1934 .vdisplay = 272, 1935 .vsync_start = 272 + 2, 1936 .vsync_end = 272 + 2 + 10, 1937 .vtotal = 272 + 2 + 10 + 2, 1938 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1939 }; 1940 1941 static const struct panel_desc edt_etm0430g0dh6 = { 1942 .modes = &edt_etm0430g0dh6_mode, 1943 .num_modes = 1, 1944 .bpc = 6, 1945 .size = { 1946 .width = 95, 1947 .height = 54, 1948 }, 1949 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1950 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1951 .connector_type = DRM_MODE_CONNECTOR_DPI, 1952 }; 1953 1954 static const struct drm_display_mode edt_et057090dhu_mode = { 1955 .clock = 25175, 1956 .hdisplay = 640, 1957 .hsync_start = 640 + 16, 1958 .hsync_end = 640 + 16 + 30, 1959 .htotal = 640 + 16 + 30 + 114, 1960 .vdisplay = 480, 1961 .vsync_start = 480 + 10, 1962 .vsync_end = 480 + 10 + 3, 1963 .vtotal = 480 + 10 + 3 + 32, 1964 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1965 }; 1966 1967 static const struct panel_desc edt_et057090dhu = { 1968 .modes = &edt_et057090dhu_mode, 1969 .num_modes = 1, 1970 .bpc = 6, 1971 .size = { 1972 .width = 115, 1973 .height = 86, 1974 }, 1975 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1976 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1977 .connector_type = DRM_MODE_CONNECTOR_DPI, 1978 }; 1979 1980 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1981 .clock = 33260, 1982 .hdisplay = 800, 1983 .hsync_start = 800 + 40, 1984 .hsync_end = 800 + 40 + 128, 1985 .htotal = 800 + 40 + 128 + 88, 1986 .vdisplay = 480, 1987 .vsync_start = 480 + 10, 1988 .vsync_end = 480 + 10 + 2, 1989 .vtotal = 480 + 10 + 2 + 33, 1990 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1991 }; 1992 1993 static const struct panel_desc edt_etm0700g0dh6 = { 1994 .modes = &edt_etm0700g0dh6_mode, 1995 .num_modes = 1, 1996 .bpc = 6, 1997 .size = { 1998 .width = 152, 1999 .height = 91, 2000 }, 2001 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2002 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2003 .connector_type = DRM_MODE_CONNECTOR_DPI, 2004 }; 2005 2006 static const struct panel_desc edt_etm0700g0bdh6 = { 2007 .modes = &edt_etm0700g0dh6_mode, 2008 .num_modes = 1, 2009 .bpc = 6, 2010 .size = { 2011 .width = 152, 2012 .height = 91, 2013 }, 2014 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2015 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2016 .connector_type = DRM_MODE_CONNECTOR_DPI, 2017 }; 2018 2019 static const struct display_timing edt_etml0700y5dha_timing = { 2020 .pixelclock = { 40800000, 51200000, 67200000 }, 2021 .hactive = { 1024, 1024, 1024 }, 2022 .hfront_porch = { 30, 106, 125 }, 2023 .hback_porch = { 30, 106, 125 }, 2024 .hsync_len = { 30, 108, 126 }, 2025 .vactive = { 600, 600, 600 }, 2026 .vfront_porch = { 3, 12, 67}, 2027 .vback_porch = { 3, 12, 67 }, 2028 .vsync_len = { 4, 11, 66 }, 2029 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2030 DISPLAY_FLAGS_DE_HIGH, 2031 }; 2032 2033 static const struct panel_desc edt_etml0700y5dha = { 2034 .timings = &edt_etml0700y5dha_timing, 2035 .num_timings = 1, 2036 .bpc = 8, 2037 .size = { 2038 .width = 155, 2039 .height = 86, 2040 }, 2041 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2042 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2043 }; 2044 2045 static const struct display_timing edt_etml1010g3dra_timing = { 2046 .pixelclock = { 66300000, 72400000, 78900000 }, 2047 .hactive = { 1280, 1280, 1280 }, 2048 .hfront_porch = { 12, 72, 132 }, 2049 .hback_porch = { 86, 86, 86 }, 2050 .hsync_len = { 2, 2, 2 }, 2051 .vactive = { 800, 800, 800 }, 2052 .vfront_porch = { 1, 15, 49 }, 2053 .vback_porch = { 21, 21, 21 }, 2054 .vsync_len = { 2, 2, 2 }, 2055 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2056 DISPLAY_FLAGS_DE_HIGH, 2057 }; 2058 2059 static const struct panel_desc edt_etml1010g3dra = { 2060 .timings = &edt_etml1010g3dra_timing, 2061 .num_timings = 1, 2062 .bpc = 8, 2063 .size = { 2064 .width = 216, 2065 .height = 135, 2066 }, 2067 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2068 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2069 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2070 }; 2071 2072 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2073 .clock = 25175, 2074 .hdisplay = 640, 2075 .hsync_start = 640, 2076 .hsync_end = 640 + 16, 2077 .htotal = 640 + 16 + 30 + 114, 2078 .vdisplay = 480, 2079 .vsync_start = 480 + 10, 2080 .vsync_end = 480 + 10 + 3, 2081 .vtotal = 480 + 10 + 3 + 35, 2082 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2083 }; 2084 2085 static const struct panel_desc edt_etmv570g2dhu = { 2086 .modes = &edt_etmv570g2dhu_mode, 2087 .num_modes = 1, 2088 .bpc = 6, 2089 .size = { 2090 .width = 115, 2091 .height = 86, 2092 }, 2093 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2094 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2095 .connector_type = DRM_MODE_CONNECTOR_DPI, 2096 }; 2097 2098 static const struct display_timing eink_vb3300_kca_timing = { 2099 .pixelclock = { 40000000, 40000000, 40000000 }, 2100 .hactive = { 334, 334, 334 }, 2101 .hfront_porch = { 1, 1, 1 }, 2102 .hback_porch = { 1, 1, 1 }, 2103 .hsync_len = { 1, 1, 1 }, 2104 .vactive = { 1405, 1405, 1405 }, 2105 .vfront_porch = { 1, 1, 1 }, 2106 .vback_porch = { 1, 1, 1 }, 2107 .vsync_len = { 1, 1, 1 }, 2108 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2109 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2110 }; 2111 2112 static const struct panel_desc eink_vb3300_kca = { 2113 .timings = &eink_vb3300_kca_timing, 2114 .num_timings = 1, 2115 .bpc = 6, 2116 .size = { 2117 .width = 157, 2118 .height = 209, 2119 }, 2120 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2121 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2122 .connector_type = DRM_MODE_CONNECTOR_DPI, 2123 }; 2124 2125 static const struct display_timing evervision_vgg644804_timing = { 2126 .pixelclock = { 25175000, 25175000, 25175000 }, 2127 .hactive = { 640, 640, 640 }, 2128 .hfront_porch = { 16, 16, 16 }, 2129 .hback_porch = { 82, 114, 170 }, 2130 .hsync_len = { 5, 30, 30 }, 2131 .vactive = { 480, 480, 480 }, 2132 .vfront_porch = { 10, 10, 10 }, 2133 .vback_porch = { 30, 32, 34 }, 2134 .vsync_len = { 1, 3, 5 }, 2135 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2136 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2137 DISPLAY_FLAGS_SYNC_POSEDGE, 2138 }; 2139 2140 static const struct panel_desc evervision_vgg644804 = { 2141 .timings = &evervision_vgg644804_timing, 2142 .num_timings = 1, 2143 .bpc = 8, 2144 .size = { 2145 .width = 115, 2146 .height = 86, 2147 }, 2148 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2149 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2150 }; 2151 2152 static const struct display_timing evervision_vgg804821_timing = { 2153 .pixelclock = { 27600000, 33300000, 50000000 }, 2154 .hactive = { 800, 800, 800 }, 2155 .hfront_porch = { 40, 66, 70 }, 2156 .hback_porch = { 40, 67, 70 }, 2157 .hsync_len = { 40, 67, 70 }, 2158 .vactive = { 480, 480, 480 }, 2159 .vfront_porch = { 6, 10, 10 }, 2160 .vback_porch = { 7, 11, 11 }, 2161 .vsync_len = { 7, 11, 11 }, 2162 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2163 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2164 DISPLAY_FLAGS_SYNC_NEGEDGE, 2165 }; 2166 2167 static const struct panel_desc evervision_vgg804821 = { 2168 .timings = &evervision_vgg804821_timing, 2169 .num_timings = 1, 2170 .bpc = 8, 2171 .size = { 2172 .width = 108, 2173 .height = 64, 2174 }, 2175 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2176 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2177 }; 2178 2179 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2180 .clock = 32260, 2181 .hdisplay = 800, 2182 .hsync_start = 800 + 168, 2183 .hsync_end = 800 + 168 + 64, 2184 .htotal = 800 + 168 + 64 + 88, 2185 .vdisplay = 480, 2186 .vsync_start = 480 + 37, 2187 .vsync_end = 480 + 37 + 2, 2188 .vtotal = 480 + 37 + 2 + 8, 2189 }; 2190 2191 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2192 .modes = &foxlink_fl500wvr00_a0t_mode, 2193 .num_modes = 1, 2194 .bpc = 8, 2195 .size = { 2196 .width = 108, 2197 .height = 65, 2198 }, 2199 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2200 }; 2201 2202 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2203 { /* 60 Hz */ 2204 .clock = 6000, 2205 .hdisplay = 320, 2206 .hsync_start = 320 + 44, 2207 .hsync_end = 320 + 44 + 16, 2208 .htotal = 320 + 44 + 16 + 20, 2209 .vdisplay = 240, 2210 .vsync_start = 240 + 2, 2211 .vsync_end = 240 + 2 + 6, 2212 .vtotal = 240 + 2 + 6 + 2, 2213 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2214 }, 2215 { /* 50 Hz */ 2216 .clock = 5400, 2217 .hdisplay = 320, 2218 .hsync_start = 320 + 56, 2219 .hsync_end = 320 + 56 + 16, 2220 .htotal = 320 + 56 + 16 + 40, 2221 .vdisplay = 240, 2222 .vsync_start = 240 + 2, 2223 .vsync_end = 240 + 2 + 6, 2224 .vtotal = 240 + 2 + 6 + 2, 2225 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2226 }, 2227 }; 2228 2229 static const struct panel_desc frida_frd350h54004 = { 2230 .modes = frida_frd350h54004_modes, 2231 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2232 .bpc = 8, 2233 .size = { 2234 .width = 77, 2235 .height = 64, 2236 }, 2237 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2238 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2239 .connector_type = DRM_MODE_CONNECTOR_DPI, 2240 }; 2241 2242 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2243 .clock = 67185, 2244 .hdisplay = 800, 2245 .hsync_start = 800 + 20, 2246 .hsync_end = 800 + 20 + 24, 2247 .htotal = 800 + 20 + 24 + 20, 2248 .vdisplay = 1280, 2249 .vsync_start = 1280 + 4, 2250 .vsync_end = 1280 + 4 + 8, 2251 .vtotal = 1280 + 4 + 8 + 4, 2252 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2253 }; 2254 2255 static const struct panel_desc friendlyarm_hd702e = { 2256 .modes = &friendlyarm_hd702e_mode, 2257 .num_modes = 1, 2258 .size = { 2259 .width = 94, 2260 .height = 151, 2261 }, 2262 }; 2263 2264 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2265 .clock = 9000, 2266 .hdisplay = 480, 2267 .hsync_start = 480 + 5, 2268 .hsync_end = 480 + 5 + 1, 2269 .htotal = 480 + 5 + 1 + 40, 2270 .vdisplay = 272, 2271 .vsync_start = 272 + 8, 2272 .vsync_end = 272 + 8 + 1, 2273 .vtotal = 272 + 8 + 1 + 8, 2274 }; 2275 2276 static const struct panel_desc giantplus_gpg482739qs5 = { 2277 .modes = &giantplus_gpg482739qs5_mode, 2278 .num_modes = 1, 2279 .bpc = 8, 2280 .size = { 2281 .width = 95, 2282 .height = 54, 2283 }, 2284 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2285 }; 2286 2287 static const struct display_timing giantplus_gpm940b0_timing = { 2288 .pixelclock = { 13500000, 27000000, 27500000 }, 2289 .hactive = { 320, 320, 320 }, 2290 .hfront_porch = { 14, 686, 718 }, 2291 .hback_porch = { 50, 70, 255 }, 2292 .hsync_len = { 1, 1, 1 }, 2293 .vactive = { 240, 240, 240 }, 2294 .vfront_porch = { 1, 1, 179 }, 2295 .vback_porch = { 1, 21, 31 }, 2296 .vsync_len = { 1, 1, 6 }, 2297 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2298 }; 2299 2300 static const struct panel_desc giantplus_gpm940b0 = { 2301 .timings = &giantplus_gpm940b0_timing, 2302 .num_timings = 1, 2303 .bpc = 8, 2304 .size = { 2305 .width = 60, 2306 .height = 45, 2307 }, 2308 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2309 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2310 }; 2311 2312 static const struct display_timing hannstar_hsd070pww1_timing = { 2313 .pixelclock = { 64300000, 71100000, 82000000 }, 2314 .hactive = { 1280, 1280, 1280 }, 2315 .hfront_porch = { 1, 1, 10 }, 2316 .hback_porch = { 1, 1, 10 }, 2317 /* 2318 * According to the data sheet, the minimum horizontal blanking interval 2319 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2320 * minimum working horizontal blanking interval to be 60 clocks. 2321 */ 2322 .hsync_len = { 58, 158, 661 }, 2323 .vactive = { 800, 800, 800 }, 2324 .vfront_porch = { 1, 1, 10 }, 2325 .vback_porch = { 1, 1, 10 }, 2326 .vsync_len = { 1, 21, 203 }, 2327 .flags = DISPLAY_FLAGS_DE_HIGH, 2328 }; 2329 2330 static const struct panel_desc hannstar_hsd070pww1 = { 2331 .timings = &hannstar_hsd070pww1_timing, 2332 .num_timings = 1, 2333 .bpc = 6, 2334 .size = { 2335 .width = 151, 2336 .height = 94, 2337 }, 2338 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2339 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2340 }; 2341 2342 static const struct display_timing hannstar_hsd100pxn1_timing = { 2343 .pixelclock = { 55000000, 65000000, 75000000 }, 2344 .hactive = { 1024, 1024, 1024 }, 2345 .hfront_porch = { 40, 40, 40 }, 2346 .hback_porch = { 220, 220, 220 }, 2347 .hsync_len = { 20, 60, 100 }, 2348 .vactive = { 768, 768, 768 }, 2349 .vfront_porch = { 7, 7, 7 }, 2350 .vback_porch = { 21, 21, 21 }, 2351 .vsync_len = { 10, 10, 10 }, 2352 .flags = DISPLAY_FLAGS_DE_HIGH, 2353 }; 2354 2355 static const struct panel_desc hannstar_hsd100pxn1 = { 2356 .timings = &hannstar_hsd100pxn1_timing, 2357 .num_timings = 1, 2358 .bpc = 6, 2359 .size = { 2360 .width = 203, 2361 .height = 152, 2362 }, 2363 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2364 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2365 }; 2366 2367 static const struct display_timing hannstar_hsd101pww2_timing = { 2368 .pixelclock = { 64300000, 71100000, 82000000 }, 2369 .hactive = { 1280, 1280, 1280 }, 2370 .hfront_porch = { 1, 1, 10 }, 2371 .hback_porch = { 1, 1, 10 }, 2372 .hsync_len = { 58, 158, 661 }, 2373 .vactive = { 800, 800, 800 }, 2374 .vfront_porch = { 1, 1, 10 }, 2375 .vback_porch = { 1, 1, 10 }, 2376 .vsync_len = { 1, 21, 203 }, 2377 .flags = DISPLAY_FLAGS_DE_HIGH, 2378 }; 2379 2380 static const struct panel_desc hannstar_hsd101pww2 = { 2381 .timings = &hannstar_hsd101pww2_timing, 2382 .num_timings = 1, 2383 .bpc = 8, 2384 .size = { 2385 .width = 217, 2386 .height = 136, 2387 }, 2388 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2389 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2390 }; 2391 2392 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2393 .clock = 33333, 2394 .hdisplay = 800, 2395 .hsync_start = 800 + 85, 2396 .hsync_end = 800 + 85 + 86, 2397 .htotal = 800 + 85 + 86 + 85, 2398 .vdisplay = 480, 2399 .vsync_start = 480 + 16, 2400 .vsync_end = 480 + 16 + 13, 2401 .vtotal = 480 + 16 + 13 + 16, 2402 }; 2403 2404 static const struct panel_desc hitachi_tx23d38vm0caa = { 2405 .modes = &hitachi_tx23d38vm0caa_mode, 2406 .num_modes = 1, 2407 .bpc = 6, 2408 .size = { 2409 .width = 195, 2410 .height = 117, 2411 }, 2412 .delay = { 2413 .enable = 160, 2414 .disable = 160, 2415 }, 2416 }; 2417 2418 static const struct drm_display_mode innolux_at043tn24_mode = { 2419 .clock = 9000, 2420 .hdisplay = 480, 2421 .hsync_start = 480 + 2, 2422 .hsync_end = 480 + 2 + 41, 2423 .htotal = 480 + 2 + 41 + 2, 2424 .vdisplay = 272, 2425 .vsync_start = 272 + 2, 2426 .vsync_end = 272 + 2 + 10, 2427 .vtotal = 272 + 2 + 10 + 2, 2428 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2429 }; 2430 2431 static const struct panel_desc innolux_at043tn24 = { 2432 .modes = &innolux_at043tn24_mode, 2433 .num_modes = 1, 2434 .bpc = 8, 2435 .size = { 2436 .width = 95, 2437 .height = 54, 2438 }, 2439 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2440 .connector_type = DRM_MODE_CONNECTOR_DPI, 2441 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2442 }; 2443 2444 static const struct drm_display_mode innolux_at070tn92_mode = { 2445 .clock = 33333, 2446 .hdisplay = 800, 2447 .hsync_start = 800 + 210, 2448 .hsync_end = 800 + 210 + 20, 2449 .htotal = 800 + 210 + 20 + 46, 2450 .vdisplay = 480, 2451 .vsync_start = 480 + 22, 2452 .vsync_end = 480 + 22 + 10, 2453 .vtotal = 480 + 22 + 23 + 10, 2454 }; 2455 2456 static const struct panel_desc innolux_at070tn92 = { 2457 .modes = &innolux_at070tn92_mode, 2458 .num_modes = 1, 2459 .size = { 2460 .width = 154, 2461 .height = 86, 2462 }, 2463 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2464 }; 2465 2466 static const struct display_timing innolux_g070ace_l01_timing = { 2467 .pixelclock = { 25200000, 35000000, 35700000 }, 2468 .hactive = { 800, 800, 800 }, 2469 .hfront_porch = { 30, 32, 87 }, 2470 .hback_porch = { 30, 32, 87 }, 2471 .hsync_len = { 1, 1, 1 }, 2472 .vactive = { 480, 480, 480 }, 2473 .vfront_porch = { 3, 3, 3 }, 2474 .vback_porch = { 13, 13, 13 }, 2475 .vsync_len = { 1, 1, 4 }, 2476 .flags = DISPLAY_FLAGS_DE_HIGH, 2477 }; 2478 2479 static const struct panel_desc innolux_g070ace_l01 = { 2480 .timings = &innolux_g070ace_l01_timing, 2481 .num_timings = 1, 2482 .bpc = 8, 2483 .size = { 2484 .width = 152, 2485 .height = 91, 2486 }, 2487 .delay = { 2488 .prepare = 10, 2489 .enable = 50, 2490 .disable = 50, 2491 .unprepare = 500, 2492 }, 2493 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2494 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2495 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2496 }; 2497 2498 static const struct display_timing innolux_g070y2_l01_timing = { 2499 .pixelclock = { 28000000, 29500000, 32000000 }, 2500 .hactive = { 800, 800, 800 }, 2501 .hfront_porch = { 61, 91, 141 }, 2502 .hback_porch = { 60, 90, 140 }, 2503 .hsync_len = { 12, 12, 12 }, 2504 .vactive = { 480, 480, 480 }, 2505 .vfront_porch = { 4, 9, 30 }, 2506 .vback_porch = { 4, 8, 28 }, 2507 .vsync_len = { 2, 2, 2 }, 2508 .flags = DISPLAY_FLAGS_DE_HIGH, 2509 }; 2510 2511 static const struct panel_desc innolux_g070y2_l01 = { 2512 .timings = &innolux_g070y2_l01_timing, 2513 .num_timings = 1, 2514 .bpc = 8, 2515 .size = { 2516 .width = 152, 2517 .height = 91, 2518 }, 2519 .delay = { 2520 .prepare = 10, 2521 .enable = 100, 2522 .disable = 100, 2523 .unprepare = 800, 2524 }, 2525 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2526 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2527 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2528 }; 2529 2530 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2531 .clock = 33333, 2532 .hdisplay = 800, 2533 .hsync_start = 800 + 210, 2534 .hsync_end = 800 + 210 + 20, 2535 .htotal = 800 + 210 + 20 + 46, 2536 .vdisplay = 480, 2537 .vsync_start = 480 + 22, 2538 .vsync_end = 480 + 22 + 10, 2539 .vtotal = 480 + 22 + 23 + 10, 2540 }; 2541 2542 static const struct panel_desc innolux_g070y2_t02 = { 2543 .modes = &innolux_g070y2_t02_mode, 2544 .num_modes = 1, 2545 .bpc = 8, 2546 .size = { 2547 .width = 152, 2548 .height = 92, 2549 }, 2550 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2551 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2552 .connector_type = DRM_MODE_CONNECTOR_DPI, 2553 }; 2554 2555 static const struct display_timing innolux_g101ice_l01_timing = { 2556 .pixelclock = { 60400000, 71100000, 74700000 }, 2557 .hactive = { 1280, 1280, 1280 }, 2558 .hfront_porch = { 30, 60, 70 }, 2559 .hback_porch = { 30, 60, 70 }, 2560 .hsync_len = { 22, 40, 60 }, 2561 .vactive = { 800, 800, 800 }, 2562 .vfront_porch = { 3, 8, 14 }, 2563 .vback_porch = { 3, 8, 14 }, 2564 .vsync_len = { 4, 7, 12 }, 2565 .flags = DISPLAY_FLAGS_DE_HIGH, 2566 }; 2567 2568 static const struct panel_desc innolux_g101ice_l01 = { 2569 .timings = &innolux_g101ice_l01_timing, 2570 .num_timings = 1, 2571 .bpc = 8, 2572 .size = { 2573 .width = 217, 2574 .height = 135, 2575 }, 2576 .delay = { 2577 .enable = 200, 2578 .disable = 200, 2579 }, 2580 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2581 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2582 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2583 }; 2584 2585 static const struct display_timing innolux_g121i1_l01_timing = { 2586 .pixelclock = { 67450000, 71000000, 74550000 }, 2587 .hactive = { 1280, 1280, 1280 }, 2588 .hfront_porch = { 40, 80, 160 }, 2589 .hback_porch = { 39, 79, 159 }, 2590 .hsync_len = { 1, 1, 1 }, 2591 .vactive = { 800, 800, 800 }, 2592 .vfront_porch = { 5, 11, 100 }, 2593 .vback_porch = { 4, 11, 99 }, 2594 .vsync_len = { 1, 1, 1 }, 2595 }; 2596 2597 static const struct panel_desc innolux_g121i1_l01 = { 2598 .timings = &innolux_g121i1_l01_timing, 2599 .num_timings = 1, 2600 .bpc = 6, 2601 .size = { 2602 .width = 261, 2603 .height = 163, 2604 }, 2605 .delay = { 2606 .enable = 200, 2607 .disable = 20, 2608 }, 2609 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2610 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2611 }; 2612 2613 static const struct display_timing innolux_g121x1_l03_timings = { 2614 .pixelclock = { 57500000, 64900000, 74400000 }, 2615 .hactive = { 1024, 1024, 1024 }, 2616 .hfront_porch = { 90, 140, 190 }, 2617 .hback_porch = { 90, 140, 190 }, 2618 .hsync_len = { 36, 40, 60 }, 2619 .vactive = { 768, 768, 768 }, 2620 .vfront_porch = { 2, 15, 30 }, 2621 .vback_porch = { 2, 15, 30 }, 2622 .vsync_len = { 2, 8, 20 }, 2623 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2624 }; 2625 2626 static const struct panel_desc innolux_g121x1_l03 = { 2627 .timings = &innolux_g121x1_l03_timings, 2628 .num_timings = 1, 2629 .bpc = 6, 2630 .size = { 2631 .width = 246, 2632 .height = 185, 2633 }, 2634 .delay = { 2635 .enable = 200, 2636 .unprepare = 200, 2637 .disable = 400, 2638 }, 2639 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2640 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2641 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2642 }; 2643 2644 static const struct panel_desc innolux_g121xce_l01 = { 2645 .timings = &innolux_g121x1_l03_timings, 2646 .num_timings = 1, 2647 .bpc = 8, 2648 .size = { 2649 .width = 246, 2650 .height = 185, 2651 }, 2652 .delay = { 2653 .enable = 200, 2654 .unprepare = 200, 2655 .disable = 400, 2656 }, 2657 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2658 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2659 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2660 }; 2661 2662 static const struct display_timing innolux_g156hce_l01_timings = { 2663 .pixelclock = { 120000000, 141860000, 150000000 }, 2664 .hactive = { 1920, 1920, 1920 }, 2665 .hfront_porch = { 80, 90, 100 }, 2666 .hback_porch = { 80, 90, 100 }, 2667 .hsync_len = { 20, 30, 30 }, 2668 .vactive = { 1080, 1080, 1080 }, 2669 .vfront_porch = { 3, 10, 20 }, 2670 .vback_porch = { 3, 10, 20 }, 2671 .vsync_len = { 4, 10, 10 }, 2672 }; 2673 2674 static const struct panel_desc innolux_g156hce_l01 = { 2675 .timings = &innolux_g156hce_l01_timings, 2676 .num_timings = 1, 2677 .bpc = 8, 2678 .size = { 2679 .width = 344, 2680 .height = 194, 2681 }, 2682 .delay = { 2683 .prepare = 1, /* T1+T2 */ 2684 .enable = 450, /* T5 */ 2685 .disable = 200, /* T6 */ 2686 .unprepare = 10, /* T3+T7 */ 2687 }, 2688 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2689 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2690 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2691 }; 2692 2693 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2694 .clock = 69300, 2695 .hdisplay = 1366, 2696 .hsync_start = 1366 + 16, 2697 .hsync_end = 1366 + 16 + 34, 2698 .htotal = 1366 + 16 + 34 + 50, 2699 .vdisplay = 768, 2700 .vsync_start = 768 + 2, 2701 .vsync_end = 768 + 2 + 6, 2702 .vtotal = 768 + 2 + 6 + 12, 2703 }; 2704 2705 static const struct panel_desc innolux_n156bge_l21 = { 2706 .modes = &innolux_n156bge_l21_mode, 2707 .num_modes = 1, 2708 .bpc = 6, 2709 .size = { 2710 .width = 344, 2711 .height = 193, 2712 }, 2713 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2714 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2715 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2716 }; 2717 2718 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2719 .clock = 51501, 2720 .hdisplay = 1024, 2721 .hsync_start = 1024 + 128, 2722 .hsync_end = 1024 + 128 + 64, 2723 .htotal = 1024 + 128 + 64 + 128, 2724 .vdisplay = 600, 2725 .vsync_start = 600 + 16, 2726 .vsync_end = 600 + 16 + 4, 2727 .vtotal = 600 + 16 + 4 + 16, 2728 }; 2729 2730 static const struct panel_desc innolux_zj070na_01p = { 2731 .modes = &innolux_zj070na_01p_mode, 2732 .num_modes = 1, 2733 .bpc = 6, 2734 .size = { 2735 .width = 154, 2736 .height = 90, 2737 }, 2738 }; 2739 2740 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2741 .pixelclock = { 5580000, 5850000, 6200000 }, 2742 .hactive = { 320, 320, 320 }, 2743 .hfront_porch = { 30, 30, 30 }, 2744 .hback_porch = { 30, 30, 30 }, 2745 .hsync_len = { 1, 5, 17 }, 2746 .vactive = { 240, 240, 240 }, 2747 .vfront_porch = { 6, 6, 6 }, 2748 .vback_porch = { 5, 5, 5 }, 2749 .vsync_len = { 1, 2, 11 }, 2750 .flags = DISPLAY_FLAGS_DE_HIGH, 2751 }; 2752 2753 static const struct panel_desc koe_tx14d24vm1bpa = { 2754 .timings = &koe_tx14d24vm1bpa_timing, 2755 .num_timings = 1, 2756 .bpc = 6, 2757 .size = { 2758 .width = 115, 2759 .height = 86, 2760 }, 2761 }; 2762 2763 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2764 .pixelclock = { 151820000, 156720000, 159780000 }, 2765 .hactive = { 1920, 1920, 1920 }, 2766 .hfront_porch = { 105, 130, 142 }, 2767 .hback_porch = { 45, 70, 82 }, 2768 .hsync_len = { 30, 30, 30 }, 2769 .vactive = { 1200, 1200, 1200}, 2770 .vfront_porch = { 3, 5, 10 }, 2771 .vback_porch = { 2, 5, 10 }, 2772 .vsync_len = { 5, 5, 5 }, 2773 .flags = DISPLAY_FLAGS_DE_HIGH, 2774 }; 2775 2776 static const struct panel_desc koe_tx26d202vm0bwa = { 2777 .timings = &koe_tx26d202vm0bwa_timing, 2778 .num_timings = 1, 2779 .bpc = 8, 2780 .size = { 2781 .width = 217, 2782 .height = 136, 2783 }, 2784 .delay = { 2785 .prepare = 1000, 2786 .enable = 1000, 2787 .unprepare = 1000, 2788 .disable = 1000, 2789 }, 2790 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2791 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2792 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2793 }; 2794 2795 static const struct display_timing koe_tx31d200vm0baa_timing = { 2796 .pixelclock = { 39600000, 43200000, 48000000 }, 2797 .hactive = { 1280, 1280, 1280 }, 2798 .hfront_porch = { 16, 36, 56 }, 2799 .hback_porch = { 16, 36, 56 }, 2800 .hsync_len = { 8, 8, 8 }, 2801 .vactive = { 480, 480, 480 }, 2802 .vfront_porch = { 6, 21, 33 }, 2803 .vback_porch = { 6, 21, 33 }, 2804 .vsync_len = { 8, 8, 8 }, 2805 .flags = DISPLAY_FLAGS_DE_HIGH, 2806 }; 2807 2808 static const struct panel_desc koe_tx31d200vm0baa = { 2809 .timings = &koe_tx31d200vm0baa_timing, 2810 .num_timings = 1, 2811 .bpc = 6, 2812 .size = { 2813 .width = 292, 2814 .height = 109, 2815 }, 2816 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2817 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2818 }; 2819 2820 static const struct display_timing kyo_tcg121xglp_timing = { 2821 .pixelclock = { 52000000, 65000000, 71000000 }, 2822 .hactive = { 1024, 1024, 1024 }, 2823 .hfront_porch = { 2, 2, 2 }, 2824 .hback_porch = { 2, 2, 2 }, 2825 .hsync_len = { 86, 124, 244 }, 2826 .vactive = { 768, 768, 768 }, 2827 .vfront_porch = { 2, 2, 2 }, 2828 .vback_porch = { 2, 2, 2 }, 2829 .vsync_len = { 6, 34, 73 }, 2830 .flags = DISPLAY_FLAGS_DE_HIGH, 2831 }; 2832 2833 static const struct panel_desc kyo_tcg121xglp = { 2834 .timings = &kyo_tcg121xglp_timing, 2835 .num_timings = 1, 2836 .bpc = 8, 2837 .size = { 2838 .width = 246, 2839 .height = 184, 2840 }, 2841 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2842 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2843 }; 2844 2845 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2846 .clock = 7000, 2847 .hdisplay = 320, 2848 .hsync_start = 320 + 20, 2849 .hsync_end = 320 + 20 + 30, 2850 .htotal = 320 + 20 + 30 + 38, 2851 .vdisplay = 240, 2852 .vsync_start = 240 + 4, 2853 .vsync_end = 240 + 4 + 3, 2854 .vtotal = 240 + 4 + 3 + 15, 2855 }; 2856 2857 static const struct panel_desc lemaker_bl035_rgb_002 = { 2858 .modes = &lemaker_bl035_rgb_002_mode, 2859 .num_modes = 1, 2860 .size = { 2861 .width = 70, 2862 .height = 52, 2863 }, 2864 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2865 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2866 }; 2867 2868 static const struct display_timing lg_lb070wv8_timing = { 2869 .pixelclock = { 31950000, 33260000, 34600000 }, 2870 .hactive = { 800, 800, 800 }, 2871 .hfront_porch = { 88, 88, 88 }, 2872 .hback_porch = { 88, 88, 88 }, 2873 .hsync_len = { 80, 80, 80 }, 2874 .vactive = { 480, 480, 480 }, 2875 .vfront_porch = { 10, 10, 10 }, 2876 .vback_porch = { 10, 10, 10 }, 2877 .vsync_len = { 25, 25, 25 }, 2878 }; 2879 2880 static const struct panel_desc lg_lb070wv8 = { 2881 .timings = &lg_lb070wv8_timing, 2882 .num_timings = 1, 2883 .bpc = 8, 2884 .size = { 2885 .width = 151, 2886 .height = 91, 2887 }, 2888 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2889 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2890 }; 2891 2892 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 2893 .clock = 155127, 2894 .hdisplay = 1920, 2895 .hsync_start = 1920 + 128, 2896 .hsync_end = 1920 + 128 + 20, 2897 .htotal = 1920 + 128 + 20 + 12, 2898 .vdisplay = 1200, 2899 .vsync_start = 1200 + 19, 2900 .vsync_end = 1200 + 19 + 4, 2901 .vtotal = 1200 + 19 + 4 + 20, 2902 }; 2903 2904 static const struct panel_desc lincolntech_lcd185_101ct = { 2905 .modes = &lincolntech_lcd185_101ct_mode, 2906 .bpc = 8, 2907 .num_modes = 1, 2908 .size = { 2909 .width = 217, 2910 .height = 136, 2911 }, 2912 .delay = { 2913 .prepare = 50, 2914 .disable = 50, 2915 }, 2916 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2917 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2918 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2919 }; 2920 2921 static const struct display_timing logictechno_lt161010_2nh_timing = { 2922 .pixelclock = { 26400000, 33300000, 46800000 }, 2923 .hactive = { 800, 800, 800 }, 2924 .hfront_porch = { 16, 210, 354 }, 2925 .hback_porch = { 46, 46, 46 }, 2926 .hsync_len = { 1, 20, 40 }, 2927 .vactive = { 480, 480, 480 }, 2928 .vfront_porch = { 7, 22, 147 }, 2929 .vback_porch = { 23, 23, 23 }, 2930 .vsync_len = { 1, 10, 20 }, 2931 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2932 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2933 DISPLAY_FLAGS_SYNC_POSEDGE, 2934 }; 2935 2936 static const struct panel_desc logictechno_lt161010_2nh = { 2937 .timings = &logictechno_lt161010_2nh_timing, 2938 .num_timings = 1, 2939 .bpc = 6, 2940 .size = { 2941 .width = 154, 2942 .height = 86, 2943 }, 2944 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2945 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2946 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2947 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2948 .connector_type = DRM_MODE_CONNECTOR_DPI, 2949 }; 2950 2951 static const struct display_timing logictechno_lt170410_2whc_timing = { 2952 .pixelclock = { 68900000, 71100000, 73400000 }, 2953 .hactive = { 1280, 1280, 1280 }, 2954 .hfront_porch = { 23, 60, 71 }, 2955 .hback_porch = { 23, 60, 71 }, 2956 .hsync_len = { 15, 40, 47 }, 2957 .vactive = { 800, 800, 800 }, 2958 .vfront_porch = { 5, 7, 10 }, 2959 .vback_porch = { 5, 7, 10 }, 2960 .vsync_len = { 6, 9, 12 }, 2961 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2962 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2963 DISPLAY_FLAGS_SYNC_POSEDGE, 2964 }; 2965 2966 static const struct panel_desc logictechno_lt170410_2whc = { 2967 .timings = &logictechno_lt170410_2whc_timing, 2968 .num_timings = 1, 2969 .bpc = 8, 2970 .size = { 2971 .width = 217, 2972 .height = 136, 2973 }, 2974 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2975 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2976 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2977 }; 2978 2979 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2980 .clock = 33000, 2981 .hdisplay = 800, 2982 .hsync_start = 800 + 112, 2983 .hsync_end = 800 + 112 + 3, 2984 .htotal = 800 + 112 + 3 + 85, 2985 .vdisplay = 480, 2986 .vsync_start = 480 + 38, 2987 .vsync_end = 480 + 38 + 3, 2988 .vtotal = 480 + 38 + 3 + 29, 2989 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2990 }; 2991 2992 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2993 .modes = &logictechno_lttd800480070_l2rt_mode, 2994 .num_modes = 1, 2995 .bpc = 8, 2996 .size = { 2997 .width = 154, 2998 .height = 86, 2999 }, 3000 .delay = { 3001 .prepare = 45, 3002 .enable = 100, 3003 .disable = 100, 3004 .unprepare = 45 3005 }, 3006 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3007 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3008 .connector_type = DRM_MODE_CONNECTOR_DPI, 3009 }; 3010 3011 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3012 .clock = 33000, 3013 .hdisplay = 800, 3014 .hsync_start = 800 + 154, 3015 .hsync_end = 800 + 154 + 3, 3016 .htotal = 800 + 154 + 3 + 43, 3017 .vdisplay = 480, 3018 .vsync_start = 480 + 47, 3019 .vsync_end = 480 + 47 + 3, 3020 .vtotal = 480 + 47 + 3 + 20, 3021 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3022 }; 3023 3024 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3025 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3026 .num_modes = 1, 3027 .bpc = 8, 3028 .size = { 3029 .width = 154, 3030 .height = 86, 3031 }, 3032 .delay = { 3033 .prepare = 45, 3034 .enable = 100, 3035 .disable = 100, 3036 .unprepare = 45 3037 }, 3038 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3039 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3040 .connector_type = DRM_MODE_CONNECTOR_DPI, 3041 }; 3042 3043 static const struct drm_display_mode logicpd_type_28_mode = { 3044 .clock = 9107, 3045 .hdisplay = 480, 3046 .hsync_start = 480 + 3, 3047 .hsync_end = 480 + 3 + 42, 3048 .htotal = 480 + 3 + 42 + 2, 3049 3050 .vdisplay = 272, 3051 .vsync_start = 272 + 2, 3052 .vsync_end = 272 + 2 + 11, 3053 .vtotal = 272 + 2 + 11 + 3, 3054 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3055 }; 3056 3057 static const struct panel_desc logicpd_type_28 = { 3058 .modes = &logicpd_type_28_mode, 3059 .num_modes = 1, 3060 .bpc = 8, 3061 .size = { 3062 .width = 105, 3063 .height = 67, 3064 }, 3065 .delay = { 3066 .prepare = 200, 3067 .enable = 200, 3068 .unprepare = 200, 3069 .disable = 200, 3070 }, 3071 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3072 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3073 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3074 .connector_type = DRM_MODE_CONNECTOR_DPI, 3075 }; 3076 3077 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3078 .clock = 150275, 3079 .hdisplay = 1920, 3080 .hsync_start = 1920 + 32, 3081 .hsync_end = 1920 + 32 + 52, 3082 .htotal = 1920 + 32 + 52 + 24, 3083 .vdisplay = 1200, 3084 .vsync_start = 1200 + 24, 3085 .vsync_end = 1200 + 24 + 8, 3086 .vtotal = 1200 + 24 + 8 + 3, 3087 }; 3088 3089 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3090 .modes = µtips_mf_101hiebcaf0_c_mode, 3091 .bpc = 8, 3092 .num_modes = 1, 3093 .size = { 3094 .width = 217, 3095 .height = 136, 3096 }, 3097 .delay = { 3098 .prepare = 50, 3099 .disable = 50, 3100 }, 3101 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3102 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3103 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3104 }; 3105 3106 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3107 .clock = 93301, 3108 .hdisplay = 1920, 3109 .hsync_start = 1920 + 72, 3110 .hsync_end = 1920 + 72 + 72, 3111 .htotal = 1920 + 72 + 72 + 72, 3112 .vdisplay = 720, 3113 .vsync_start = 720 + 3, 3114 .vsync_end = 720 + 3 + 3, 3115 .vtotal = 720 + 3 + 3 + 2, 3116 }; 3117 3118 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3119 .modes = µtips_mf_103hieb0ga0_mode, 3120 .bpc = 8, 3121 .num_modes = 1, 3122 .size = { 3123 .width = 244, 3124 .height = 92, 3125 }, 3126 .delay = { 3127 .prepare = 50, 3128 .disable = 50, 3129 }, 3130 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3131 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3132 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3133 }; 3134 3135 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3136 .clock = 30400, 3137 .hdisplay = 800, 3138 .hsync_start = 800 + 0, 3139 .hsync_end = 800 + 1, 3140 .htotal = 800 + 0 + 1 + 160, 3141 .vdisplay = 480, 3142 .vsync_start = 480 + 0, 3143 .vsync_end = 480 + 48 + 1, 3144 .vtotal = 480 + 48 + 1 + 0, 3145 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3146 }; 3147 3148 static const struct panel_desc mitsubishi_aa070mc01 = { 3149 .modes = &mitsubishi_aa070mc01_mode, 3150 .num_modes = 1, 3151 .bpc = 8, 3152 .size = { 3153 .width = 152, 3154 .height = 91, 3155 }, 3156 3157 .delay = { 3158 .enable = 200, 3159 .unprepare = 200, 3160 .disable = 400, 3161 }, 3162 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3163 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3164 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3165 }; 3166 3167 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3168 .clock = 56234, 3169 .hdisplay = 1024, 3170 .hsync_start = 1024 + 24, 3171 .hsync_end = 1024 + 24 + 63, 3172 .htotal = 1024 + 24 + 63 + 1, 3173 .vdisplay = 768, 3174 .vsync_start = 768 + 3, 3175 .vsync_end = 768 + 3 + 6, 3176 .vtotal = 768 + 3 + 6 + 1, 3177 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3178 }; 3179 3180 static const struct panel_desc mitsubishi_aa084xe01 = { 3181 .modes = &mitsubishi_aa084xe01_mode, 3182 .num_modes = 1, 3183 .bpc = 8, 3184 .size = { 3185 .width = 1024, 3186 .height = 768, 3187 }, 3188 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3189 .connector_type = DRM_MODE_CONNECTOR_DPI, 3190 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3191 }; 3192 3193 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3194 .pixelclock = { 29000000, 33000000, 38000000 }, 3195 .hactive = { 800, 800, 800 }, 3196 .hfront_porch = { 180, 210, 240 }, 3197 .hback_porch = { 16, 16, 16 }, 3198 .hsync_len = { 30, 30, 30 }, 3199 .vactive = { 480, 480, 480 }, 3200 .vfront_porch = { 12, 22, 32 }, 3201 .vback_porch = { 10, 10, 10 }, 3202 .vsync_len = { 13, 13, 13 }, 3203 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3204 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3205 DISPLAY_FLAGS_SYNC_POSEDGE, 3206 }; 3207 3208 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3209 .timings = &multi_inno_mi0700s4t_6_timing, 3210 .num_timings = 1, 3211 .bpc = 8, 3212 .size = { 3213 .width = 154, 3214 .height = 86, 3215 }, 3216 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3217 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3218 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3219 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3220 .connector_type = DRM_MODE_CONNECTOR_DPI, 3221 }; 3222 3223 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3224 .pixelclock = { 32000000, 40000000, 50000000 }, 3225 .hactive = { 800, 800, 800 }, 3226 .hfront_porch = { 16, 210, 354 }, 3227 .hback_porch = { 6, 26, 45 }, 3228 .hsync_len = { 1, 20, 40 }, 3229 .vactive = { 600, 600, 600 }, 3230 .vfront_porch = { 1, 12, 77 }, 3231 .vback_porch = { 3, 13, 22 }, 3232 .vsync_len = { 1, 10, 20 }, 3233 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3234 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3235 DISPLAY_FLAGS_SYNC_POSEDGE, 3236 }; 3237 3238 static const struct panel_desc multi_inno_mi0800ft_9 = { 3239 .timings = &multi_inno_mi0800ft_9_timing, 3240 .num_timings = 1, 3241 .bpc = 8, 3242 .size = { 3243 .width = 162, 3244 .height = 122, 3245 }, 3246 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3247 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3248 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3249 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3250 .connector_type = DRM_MODE_CONNECTOR_DPI, 3251 }; 3252 3253 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3254 .pixelclock = { 68900000, 70000000, 73400000 }, 3255 .hactive = { 1280, 1280, 1280 }, 3256 .hfront_porch = { 30, 60, 71 }, 3257 .hback_porch = { 30, 60, 71 }, 3258 .hsync_len = { 10, 10, 48 }, 3259 .vactive = { 800, 800, 800 }, 3260 .vfront_porch = { 5, 10, 10 }, 3261 .vback_porch = { 5, 10, 10 }, 3262 .vsync_len = { 5, 6, 13 }, 3263 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3264 DISPLAY_FLAGS_DE_HIGH, 3265 }; 3266 3267 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3268 .timings = &multi_inno_mi1010ait_1cp_timing, 3269 .num_timings = 1, 3270 .bpc = 8, 3271 .size = { 3272 .width = 217, 3273 .height = 136, 3274 }, 3275 .delay = { 3276 .enable = 50, 3277 .disable = 50, 3278 }, 3279 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3280 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3281 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3282 }; 3283 3284 static const struct display_timing nec_nl12880bc20_05_timing = { 3285 .pixelclock = { 67000000, 71000000, 75000000 }, 3286 .hactive = { 1280, 1280, 1280 }, 3287 .hfront_porch = { 2, 30, 30 }, 3288 .hback_porch = { 6, 100, 100 }, 3289 .hsync_len = { 2, 30, 30 }, 3290 .vactive = { 800, 800, 800 }, 3291 .vfront_porch = { 5, 5, 5 }, 3292 .vback_porch = { 11, 11, 11 }, 3293 .vsync_len = { 7, 7, 7 }, 3294 }; 3295 3296 static const struct panel_desc nec_nl12880bc20_05 = { 3297 .timings = &nec_nl12880bc20_05_timing, 3298 .num_timings = 1, 3299 .bpc = 8, 3300 .size = { 3301 .width = 261, 3302 .height = 163, 3303 }, 3304 .delay = { 3305 .enable = 50, 3306 .disable = 50, 3307 }, 3308 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3309 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3310 }; 3311 3312 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3313 .clock = 10870, 3314 .hdisplay = 480, 3315 .hsync_start = 480 + 2, 3316 .hsync_end = 480 + 2 + 41, 3317 .htotal = 480 + 2 + 41 + 2, 3318 .vdisplay = 272, 3319 .vsync_start = 272 + 2, 3320 .vsync_end = 272 + 2 + 4, 3321 .vtotal = 272 + 2 + 4 + 2, 3322 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3323 }; 3324 3325 static const struct panel_desc nec_nl4827hc19_05b = { 3326 .modes = &nec_nl4827hc19_05b_mode, 3327 .num_modes = 1, 3328 .bpc = 8, 3329 .size = { 3330 .width = 95, 3331 .height = 54, 3332 }, 3333 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3334 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3335 }; 3336 3337 static const struct drm_display_mode netron_dy_e231732_mode = { 3338 .clock = 66000, 3339 .hdisplay = 1024, 3340 .hsync_start = 1024 + 160, 3341 .hsync_end = 1024 + 160 + 70, 3342 .htotal = 1024 + 160 + 70 + 90, 3343 .vdisplay = 600, 3344 .vsync_start = 600 + 127, 3345 .vsync_end = 600 + 127 + 20, 3346 .vtotal = 600 + 127 + 20 + 3, 3347 }; 3348 3349 static const struct panel_desc netron_dy_e231732 = { 3350 .modes = &netron_dy_e231732_mode, 3351 .num_modes = 1, 3352 .size = { 3353 .width = 154, 3354 .height = 87, 3355 }, 3356 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3357 }; 3358 3359 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3360 .clock = 9000, 3361 .hdisplay = 480, 3362 .hsync_start = 480 + 2, 3363 .hsync_end = 480 + 2 + 41, 3364 .htotal = 480 + 2 + 41 + 2, 3365 .vdisplay = 272, 3366 .vsync_start = 272 + 2, 3367 .vsync_end = 272 + 2 + 10, 3368 .vtotal = 272 + 2 + 10 + 2, 3369 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3370 }; 3371 3372 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3373 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3374 .num_modes = 1, 3375 .bpc = 8, 3376 .size = { 3377 .width = 95, 3378 .height = 54, 3379 }, 3380 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3381 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3382 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3383 .connector_type = DRM_MODE_CONNECTOR_DPI, 3384 }; 3385 3386 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3387 .pixelclock = { 130000000, 148350000, 163000000 }, 3388 .hactive = { 1920, 1920, 1920 }, 3389 .hfront_porch = { 80, 100, 100 }, 3390 .hback_porch = { 100, 120, 120 }, 3391 .hsync_len = { 50, 60, 60 }, 3392 .vactive = { 1080, 1080, 1080 }, 3393 .vfront_porch = { 12, 30, 30 }, 3394 .vback_porch = { 4, 10, 10 }, 3395 .vsync_len = { 4, 5, 5 }, 3396 }; 3397 3398 static const struct panel_desc nlt_nl192108ac18_02d = { 3399 .timings = &nlt_nl192108ac18_02d_timing, 3400 .num_timings = 1, 3401 .bpc = 8, 3402 .size = { 3403 .width = 344, 3404 .height = 194, 3405 }, 3406 .delay = { 3407 .unprepare = 500, 3408 }, 3409 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3410 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3411 }; 3412 3413 static const struct drm_display_mode nvd_9128_mode = { 3414 .clock = 29500, 3415 .hdisplay = 800, 3416 .hsync_start = 800 + 130, 3417 .hsync_end = 800 + 130 + 98, 3418 .htotal = 800 + 0 + 130 + 98, 3419 .vdisplay = 480, 3420 .vsync_start = 480 + 10, 3421 .vsync_end = 480 + 10 + 50, 3422 .vtotal = 480 + 0 + 10 + 50, 3423 }; 3424 3425 static const struct panel_desc nvd_9128 = { 3426 .modes = &nvd_9128_mode, 3427 .num_modes = 1, 3428 .bpc = 8, 3429 .size = { 3430 .width = 156, 3431 .height = 88, 3432 }, 3433 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3434 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3435 }; 3436 3437 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3438 .pixelclock = { 30000000, 30000000, 40000000 }, 3439 .hactive = { 800, 800, 800 }, 3440 .hfront_porch = { 40, 40, 40 }, 3441 .hback_porch = { 40, 40, 40 }, 3442 .hsync_len = { 1, 48, 48 }, 3443 .vactive = { 480, 480, 480 }, 3444 .vfront_porch = { 13, 13, 13 }, 3445 .vback_porch = { 29, 29, 29 }, 3446 .vsync_len = { 3, 3, 3 }, 3447 .flags = DISPLAY_FLAGS_DE_HIGH, 3448 }; 3449 3450 static const struct panel_desc okaya_rs800480t_7x0gp = { 3451 .timings = &okaya_rs800480t_7x0gp_timing, 3452 .num_timings = 1, 3453 .bpc = 6, 3454 .size = { 3455 .width = 154, 3456 .height = 87, 3457 }, 3458 .delay = { 3459 .prepare = 41, 3460 .enable = 50, 3461 .unprepare = 41, 3462 .disable = 50, 3463 }, 3464 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3465 }; 3466 3467 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3468 .clock = 9000, 3469 .hdisplay = 480, 3470 .hsync_start = 480 + 5, 3471 .hsync_end = 480 + 5 + 30, 3472 .htotal = 480 + 5 + 30 + 10, 3473 .vdisplay = 272, 3474 .vsync_start = 272 + 8, 3475 .vsync_end = 272 + 8 + 5, 3476 .vtotal = 272 + 8 + 5 + 3, 3477 }; 3478 3479 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3480 .modes = &olimex_lcd_olinuxino_43ts_mode, 3481 .num_modes = 1, 3482 .size = { 3483 .width = 95, 3484 .height = 54, 3485 }, 3486 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3487 }; 3488 3489 /* 3490 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3491 * pixel clocks, but this is the timing that was being used in the Adafruit 3492 * installation instructions. 3493 */ 3494 static const struct drm_display_mode ontat_yx700wv03_mode = { 3495 .clock = 29500, 3496 .hdisplay = 800, 3497 .hsync_start = 824, 3498 .hsync_end = 896, 3499 .htotal = 992, 3500 .vdisplay = 480, 3501 .vsync_start = 483, 3502 .vsync_end = 493, 3503 .vtotal = 500, 3504 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3505 }; 3506 3507 /* 3508 * Specification at: 3509 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3510 */ 3511 static const struct panel_desc ontat_yx700wv03 = { 3512 .modes = &ontat_yx700wv03_mode, 3513 .num_modes = 1, 3514 .bpc = 8, 3515 .size = { 3516 .width = 154, 3517 .height = 83, 3518 }, 3519 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3520 }; 3521 3522 static const struct drm_display_mode ortustech_com37h3m_mode = { 3523 .clock = 22230, 3524 .hdisplay = 480, 3525 .hsync_start = 480 + 40, 3526 .hsync_end = 480 + 40 + 10, 3527 .htotal = 480 + 40 + 10 + 40, 3528 .vdisplay = 640, 3529 .vsync_start = 640 + 4, 3530 .vsync_end = 640 + 4 + 2, 3531 .vtotal = 640 + 4 + 2 + 4, 3532 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3533 }; 3534 3535 static const struct panel_desc ortustech_com37h3m = { 3536 .modes = &ortustech_com37h3m_mode, 3537 .num_modes = 1, 3538 .bpc = 8, 3539 .size = { 3540 .width = 56, /* 56.16mm */ 3541 .height = 75, /* 74.88mm */ 3542 }, 3543 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3544 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3545 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3546 }; 3547 3548 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3549 .clock = 25000, 3550 .hdisplay = 480, 3551 .hsync_start = 480 + 10, 3552 .hsync_end = 480 + 10 + 10, 3553 .htotal = 480 + 10 + 10 + 15, 3554 .vdisplay = 800, 3555 .vsync_start = 800 + 3, 3556 .vsync_end = 800 + 3 + 3, 3557 .vtotal = 800 + 3 + 3 + 3, 3558 }; 3559 3560 static const struct panel_desc ortustech_com43h4m85ulc = { 3561 .modes = &ortustech_com43h4m85ulc_mode, 3562 .num_modes = 1, 3563 .bpc = 6, 3564 .size = { 3565 .width = 56, 3566 .height = 93, 3567 }, 3568 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3569 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3570 .connector_type = DRM_MODE_CONNECTOR_DPI, 3571 }; 3572 3573 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3574 .clock = 33000, 3575 .hdisplay = 800, 3576 .hsync_start = 800 + 210, 3577 .hsync_end = 800 + 210 + 30, 3578 .htotal = 800 + 210 + 30 + 16, 3579 .vdisplay = 480, 3580 .vsync_start = 480 + 22, 3581 .vsync_end = 480 + 22 + 13, 3582 .vtotal = 480 + 22 + 13 + 10, 3583 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3584 }; 3585 3586 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3587 .modes = &osddisplays_osd070t1718_19ts_mode, 3588 .num_modes = 1, 3589 .bpc = 8, 3590 .size = { 3591 .width = 152, 3592 .height = 91, 3593 }, 3594 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3595 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3596 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3597 .connector_type = DRM_MODE_CONNECTOR_DPI, 3598 }; 3599 3600 static const struct drm_display_mode pda_91_00156_a0_mode = { 3601 .clock = 33300, 3602 .hdisplay = 800, 3603 .hsync_start = 800 + 1, 3604 .hsync_end = 800 + 1 + 64, 3605 .htotal = 800 + 1 + 64 + 64, 3606 .vdisplay = 480, 3607 .vsync_start = 480 + 1, 3608 .vsync_end = 480 + 1 + 23, 3609 .vtotal = 480 + 1 + 23 + 22, 3610 }; 3611 3612 static const struct panel_desc pda_91_00156_a0 = { 3613 .modes = &pda_91_00156_a0_mode, 3614 .num_modes = 1, 3615 .size = { 3616 .width = 152, 3617 .height = 91, 3618 }, 3619 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3620 }; 3621 3622 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 3623 .clock = 66500, 3624 .hdisplay = 1280, 3625 .hsync_start = 1280 + 12, 3626 .hsync_end = 1280 + 12 + 20, 3627 .htotal = 1280 + 12 + 20 + 56, 3628 .vdisplay = 800, 3629 .vsync_start = 800 + 1, 3630 .vsync_end = 800 + 1 + 3, 3631 .vtotal = 800 + 1 + 3 + 20, 3632 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3633 }; 3634 3635 static const struct panel_desc powertip_ph128800t006_zhc01 = { 3636 .modes = &powertip_ph128800t006_zhc01_mode, 3637 .num_modes = 1, 3638 .bpc = 8, 3639 .size = { 3640 .width = 216, 3641 .height = 135, 3642 }, 3643 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3644 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3645 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3646 }; 3647 3648 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3649 .clock = 24750, 3650 .hdisplay = 800, 3651 .hsync_start = 800 + 54, 3652 .hsync_end = 800 + 54 + 2, 3653 .htotal = 800 + 54 + 2 + 44, 3654 .vdisplay = 480, 3655 .vsync_start = 480 + 49, 3656 .vsync_end = 480 + 49 + 2, 3657 .vtotal = 480 + 49 + 2 + 22, 3658 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3659 }; 3660 3661 static const struct panel_desc powertip_ph800480t013_idf02 = { 3662 .modes = &powertip_ph800480t013_idf02_mode, 3663 .num_modes = 1, 3664 .bpc = 8, 3665 .size = { 3666 .width = 152, 3667 .height = 91, 3668 }, 3669 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3670 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3671 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3672 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3673 .connector_type = DRM_MODE_CONNECTOR_DPI, 3674 }; 3675 3676 static const struct drm_display_mode primeview_pm070wl4_mode = { 3677 .clock = 32000, 3678 .hdisplay = 800, 3679 .hsync_start = 800 + 42, 3680 .hsync_end = 800 + 42 + 128, 3681 .htotal = 800 + 42 + 128 + 86, 3682 .vdisplay = 480, 3683 .vsync_start = 480 + 10, 3684 .vsync_end = 480 + 10 + 2, 3685 .vtotal = 480 + 10 + 2 + 33, 3686 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3687 }; 3688 3689 static const struct panel_desc primeview_pm070wl4 = { 3690 .modes = &primeview_pm070wl4_mode, 3691 .num_modes = 1, 3692 .bpc = 6, 3693 .size = { 3694 .width = 152, 3695 .height = 91, 3696 }, 3697 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3698 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3699 .connector_type = DRM_MODE_CONNECTOR_DPI, 3700 }; 3701 3702 static const struct drm_display_mode qd43003c0_40_mode = { 3703 .clock = 9000, 3704 .hdisplay = 480, 3705 .hsync_start = 480 + 8, 3706 .hsync_end = 480 + 8 + 4, 3707 .htotal = 480 + 8 + 4 + 39, 3708 .vdisplay = 272, 3709 .vsync_start = 272 + 4, 3710 .vsync_end = 272 + 4 + 10, 3711 .vtotal = 272 + 4 + 10 + 2, 3712 }; 3713 3714 static const struct panel_desc qd43003c0_40 = { 3715 .modes = &qd43003c0_40_mode, 3716 .num_modes = 1, 3717 .bpc = 8, 3718 .size = { 3719 .width = 95, 3720 .height = 53, 3721 }, 3722 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3723 }; 3724 3725 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3726 { /* 60 Hz */ 3727 .clock = 10800, 3728 .hdisplay = 480, 3729 .hsync_start = 480 + 77, 3730 .hsync_end = 480 + 77 + 41, 3731 .htotal = 480 + 77 + 41 + 2, 3732 .vdisplay = 272, 3733 .vsync_start = 272 + 16, 3734 .vsync_end = 272 + 16 + 10, 3735 .vtotal = 272 + 16 + 10 + 2, 3736 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3737 }, 3738 { /* 50 Hz */ 3739 .clock = 10800, 3740 .hdisplay = 480, 3741 .hsync_start = 480 + 17, 3742 .hsync_end = 480 + 17 + 41, 3743 .htotal = 480 + 17 + 41 + 2, 3744 .vdisplay = 272, 3745 .vsync_start = 272 + 116, 3746 .vsync_end = 272 + 116 + 10, 3747 .vtotal = 272 + 116 + 10 + 2, 3748 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3749 }, 3750 }; 3751 3752 static const struct panel_desc qishenglong_gopher2b_lcd = { 3753 .modes = qishenglong_gopher2b_lcd_modes, 3754 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3755 .bpc = 8, 3756 .size = { 3757 .width = 95, 3758 .height = 54, 3759 }, 3760 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3761 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3762 .connector_type = DRM_MODE_CONNECTOR_DPI, 3763 }; 3764 3765 static const struct display_timing rocktech_rk043fn48h_timing = { 3766 .pixelclock = { 6000000, 9000000, 12000000 }, 3767 .hactive = { 480, 480, 480 }, 3768 .hback_porch = { 8, 43, 43 }, 3769 .hfront_porch = { 2, 8, 10 }, 3770 .hsync_len = { 1, 1, 1 }, 3771 .vactive = { 272, 272, 272 }, 3772 .vback_porch = { 2, 12, 26 }, 3773 .vfront_porch = { 1, 4, 4 }, 3774 .vsync_len = { 1, 10, 10 }, 3775 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3776 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3777 DISPLAY_FLAGS_SYNC_POSEDGE, 3778 }; 3779 3780 static const struct panel_desc rocktech_rk043fn48h = { 3781 .timings = &rocktech_rk043fn48h_timing, 3782 .num_timings = 1, 3783 .bpc = 8, 3784 .size = { 3785 .width = 95, 3786 .height = 54, 3787 }, 3788 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3789 .connector_type = DRM_MODE_CONNECTOR_DPI, 3790 }; 3791 3792 static const struct display_timing rocktech_rk070er9427_timing = { 3793 .pixelclock = { 26400000, 33300000, 46800000 }, 3794 .hactive = { 800, 800, 800 }, 3795 .hfront_porch = { 16, 210, 354 }, 3796 .hback_porch = { 46, 46, 46 }, 3797 .hsync_len = { 1, 1, 1 }, 3798 .vactive = { 480, 480, 480 }, 3799 .vfront_porch = { 7, 22, 147 }, 3800 .vback_porch = { 23, 23, 23 }, 3801 .vsync_len = { 1, 1, 1 }, 3802 .flags = DISPLAY_FLAGS_DE_HIGH, 3803 }; 3804 3805 static const struct panel_desc rocktech_rk070er9427 = { 3806 .timings = &rocktech_rk070er9427_timing, 3807 .num_timings = 1, 3808 .bpc = 6, 3809 .size = { 3810 .width = 154, 3811 .height = 86, 3812 }, 3813 .delay = { 3814 .prepare = 41, 3815 .enable = 50, 3816 .unprepare = 41, 3817 .disable = 50, 3818 }, 3819 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3820 }; 3821 3822 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3823 .clock = 71100, 3824 .hdisplay = 1280, 3825 .hsync_start = 1280 + 48, 3826 .hsync_end = 1280 + 48 + 32, 3827 .htotal = 1280 + 48 + 32 + 80, 3828 .vdisplay = 800, 3829 .vsync_start = 800 + 2, 3830 .vsync_end = 800 + 2 + 5, 3831 .vtotal = 800 + 2 + 5 + 16, 3832 }; 3833 3834 static const struct panel_desc rocktech_rk101ii01d_ct = { 3835 .modes = &rocktech_rk101ii01d_ct_mode, 3836 .bpc = 8, 3837 .num_modes = 1, 3838 .size = { 3839 .width = 217, 3840 .height = 136, 3841 }, 3842 .delay = { 3843 .prepare = 50, 3844 .disable = 50, 3845 }, 3846 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3847 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3848 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3849 }; 3850 3851 static const struct display_timing samsung_ltl101al01_timing = { 3852 .pixelclock = { 66663000, 66663000, 66663000 }, 3853 .hactive = { 1280, 1280, 1280 }, 3854 .hfront_porch = { 18, 18, 18 }, 3855 .hback_porch = { 36, 36, 36 }, 3856 .hsync_len = { 16, 16, 16 }, 3857 .vactive = { 800, 800, 800 }, 3858 .vfront_porch = { 4, 4, 4 }, 3859 .vback_porch = { 16, 16, 16 }, 3860 .vsync_len = { 3, 3, 3 }, 3861 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3862 }; 3863 3864 static const struct panel_desc samsung_ltl101al01 = { 3865 .timings = &samsung_ltl101al01_timing, 3866 .num_timings = 1, 3867 .bpc = 8, 3868 .size = { 3869 .width = 217, 3870 .height = 135, 3871 }, 3872 .delay = { 3873 .prepare = 40, 3874 .enable = 300, 3875 .disable = 200, 3876 .unprepare = 600, 3877 }, 3878 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3879 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3880 }; 3881 3882 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3883 .clock = 54030, 3884 .hdisplay = 1024, 3885 .hsync_start = 1024 + 24, 3886 .hsync_end = 1024 + 24 + 136, 3887 .htotal = 1024 + 24 + 136 + 160, 3888 .vdisplay = 600, 3889 .vsync_start = 600 + 3, 3890 .vsync_end = 600 + 3 + 6, 3891 .vtotal = 600 + 3 + 6 + 61, 3892 }; 3893 3894 static const struct panel_desc samsung_ltn101nt05 = { 3895 .modes = &samsung_ltn101nt05_mode, 3896 .num_modes = 1, 3897 .bpc = 6, 3898 .size = { 3899 .width = 223, 3900 .height = 125, 3901 }, 3902 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3903 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3904 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3905 }; 3906 3907 static const struct display_timing satoz_sat050at40h12r2_timing = { 3908 .pixelclock = {33300000, 33300000, 50000000}, 3909 .hactive = {800, 800, 800}, 3910 .hfront_porch = {16, 210, 354}, 3911 .hback_porch = {46, 46, 46}, 3912 .hsync_len = {1, 1, 40}, 3913 .vactive = {480, 480, 480}, 3914 .vfront_porch = {7, 22, 147}, 3915 .vback_porch = {23, 23, 23}, 3916 .vsync_len = {1, 1, 20}, 3917 }; 3918 3919 static const struct panel_desc satoz_sat050at40h12r2 = { 3920 .timings = &satoz_sat050at40h12r2_timing, 3921 .num_timings = 1, 3922 .bpc = 8, 3923 .size = { 3924 .width = 108, 3925 .height = 65, 3926 }, 3927 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3928 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3929 }; 3930 3931 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3932 .clock = 33260, 3933 .hdisplay = 800, 3934 .hsync_start = 800 + 64, 3935 .hsync_end = 800 + 64 + 128, 3936 .htotal = 800 + 64 + 128 + 64, 3937 .vdisplay = 480, 3938 .vsync_start = 480 + 8, 3939 .vsync_end = 480 + 8 + 2, 3940 .vtotal = 480 + 8 + 2 + 35, 3941 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3942 }; 3943 3944 static const struct panel_desc sharp_lq070y3dg3b = { 3945 .modes = &sharp_lq070y3dg3b_mode, 3946 .num_modes = 1, 3947 .bpc = 8, 3948 .size = { 3949 .width = 152, /* 152.4mm */ 3950 .height = 91, /* 91.4mm */ 3951 }, 3952 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3953 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3954 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3955 }; 3956 3957 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3958 .clock = 5500, 3959 .hdisplay = 240, 3960 .hsync_start = 240 + 16, 3961 .hsync_end = 240 + 16 + 7, 3962 .htotal = 240 + 16 + 7 + 5, 3963 .vdisplay = 320, 3964 .vsync_start = 320 + 9, 3965 .vsync_end = 320 + 9 + 1, 3966 .vtotal = 320 + 9 + 1 + 7, 3967 }; 3968 3969 static const struct panel_desc sharp_lq035q7db03 = { 3970 .modes = &sharp_lq035q7db03_mode, 3971 .num_modes = 1, 3972 .bpc = 6, 3973 .size = { 3974 .width = 54, 3975 .height = 72, 3976 }, 3977 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3978 }; 3979 3980 static const struct display_timing sharp_lq101k1ly04_timing = { 3981 .pixelclock = { 60000000, 65000000, 80000000 }, 3982 .hactive = { 1280, 1280, 1280 }, 3983 .hfront_porch = { 20, 20, 20 }, 3984 .hback_porch = { 20, 20, 20 }, 3985 .hsync_len = { 10, 10, 10 }, 3986 .vactive = { 800, 800, 800 }, 3987 .vfront_porch = { 4, 4, 4 }, 3988 .vback_porch = { 4, 4, 4 }, 3989 .vsync_len = { 4, 4, 4 }, 3990 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3991 }; 3992 3993 static const struct panel_desc sharp_lq101k1ly04 = { 3994 .timings = &sharp_lq101k1ly04_timing, 3995 .num_timings = 1, 3996 .bpc = 8, 3997 .size = { 3998 .width = 217, 3999 .height = 136, 4000 }, 4001 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4002 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4003 }; 4004 4005 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4006 { /* 50 Hz */ 4007 .clock = 3000, 4008 .hdisplay = 240, 4009 .hsync_start = 240 + 58, 4010 .hsync_end = 240 + 58 + 1, 4011 .htotal = 240 + 58 + 1 + 1, 4012 .vdisplay = 160, 4013 .vsync_start = 160 + 24, 4014 .vsync_end = 160 + 24 + 10, 4015 .vtotal = 160 + 24 + 10 + 6, 4016 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4017 }, 4018 { /* 60 Hz */ 4019 .clock = 3000, 4020 .hdisplay = 240, 4021 .hsync_start = 240 + 8, 4022 .hsync_end = 240 + 8 + 1, 4023 .htotal = 240 + 8 + 1 + 1, 4024 .vdisplay = 160, 4025 .vsync_start = 160 + 24, 4026 .vsync_end = 160 + 24 + 10, 4027 .vtotal = 160 + 24 + 10 + 6, 4028 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4029 }, 4030 }; 4031 4032 static const struct panel_desc sharp_ls020b1dd01d = { 4033 .modes = sharp_ls020b1dd01d_modes, 4034 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4035 .bpc = 6, 4036 .size = { 4037 .width = 42, 4038 .height = 28, 4039 }, 4040 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4041 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4042 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4043 | DRM_BUS_FLAG_SHARP_SIGNALS, 4044 }; 4045 4046 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4047 .clock = 33300, 4048 .hdisplay = 800, 4049 .hsync_start = 800 + 1, 4050 .hsync_end = 800 + 1 + 64, 4051 .htotal = 800 + 1 + 64 + 64, 4052 .vdisplay = 480, 4053 .vsync_start = 480 + 1, 4054 .vsync_end = 480 + 1 + 23, 4055 .vtotal = 480 + 1 + 23 + 22, 4056 }; 4057 4058 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4059 .modes = &shelly_sca07010_bfn_lnn_mode, 4060 .num_modes = 1, 4061 .size = { 4062 .width = 152, 4063 .height = 91, 4064 }, 4065 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4066 }; 4067 4068 static const struct drm_display_mode starry_kr070pe2t_mode = { 4069 .clock = 33000, 4070 .hdisplay = 800, 4071 .hsync_start = 800 + 209, 4072 .hsync_end = 800 + 209 + 1, 4073 .htotal = 800 + 209 + 1 + 45, 4074 .vdisplay = 480, 4075 .vsync_start = 480 + 22, 4076 .vsync_end = 480 + 22 + 1, 4077 .vtotal = 480 + 22 + 1 + 22, 4078 }; 4079 4080 static const struct panel_desc starry_kr070pe2t = { 4081 .modes = &starry_kr070pe2t_mode, 4082 .num_modes = 1, 4083 .bpc = 8, 4084 .size = { 4085 .width = 152, 4086 .height = 86, 4087 }, 4088 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4089 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4090 .connector_type = DRM_MODE_CONNECTOR_DPI, 4091 }; 4092 4093 static const struct display_timing startek_kd070wvfpa_mode = { 4094 .pixelclock = { 25200000, 27200000, 30500000 }, 4095 .hactive = { 800, 800, 800 }, 4096 .hfront_porch = { 19, 44, 115 }, 4097 .hback_porch = { 5, 16, 101 }, 4098 .hsync_len = { 1, 2, 100 }, 4099 .vactive = { 480, 480, 480 }, 4100 .vfront_porch = { 5, 43, 67 }, 4101 .vback_porch = { 5, 5, 67 }, 4102 .vsync_len = { 1, 2, 66 }, 4103 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4104 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4105 DISPLAY_FLAGS_SYNC_POSEDGE, 4106 }; 4107 4108 static const struct panel_desc startek_kd070wvfpa = { 4109 .timings = &startek_kd070wvfpa_mode, 4110 .num_timings = 1, 4111 .bpc = 8, 4112 .size = { 4113 .width = 152, 4114 .height = 91, 4115 }, 4116 .delay = { 4117 .prepare = 20, 4118 .enable = 200, 4119 .disable = 200, 4120 }, 4121 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4122 .connector_type = DRM_MODE_CONNECTOR_DPI, 4123 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4124 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4125 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4126 }; 4127 4128 static const struct display_timing tsd_tst043015cmhx_timing = { 4129 .pixelclock = { 5000000, 9000000, 12000000 }, 4130 .hactive = { 480, 480, 480 }, 4131 .hfront_porch = { 4, 5, 65 }, 4132 .hback_porch = { 36, 40, 255 }, 4133 .hsync_len = { 1, 1, 1 }, 4134 .vactive = { 272, 272, 272 }, 4135 .vfront_porch = { 2, 8, 97 }, 4136 .vback_porch = { 3, 8, 31 }, 4137 .vsync_len = { 1, 1, 1 }, 4138 4139 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4140 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4141 }; 4142 4143 static const struct panel_desc tsd_tst043015cmhx = { 4144 .timings = &tsd_tst043015cmhx_timing, 4145 .num_timings = 1, 4146 .bpc = 8, 4147 .size = { 4148 .width = 105, 4149 .height = 67, 4150 }, 4151 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4152 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4153 }; 4154 4155 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4156 .clock = 30000, 4157 .hdisplay = 800, 4158 .hsync_start = 800 + 39, 4159 .hsync_end = 800 + 39 + 47, 4160 .htotal = 800 + 39 + 47 + 39, 4161 .vdisplay = 480, 4162 .vsync_start = 480 + 13, 4163 .vsync_end = 480 + 13 + 2, 4164 .vtotal = 480 + 13 + 2 + 29, 4165 }; 4166 4167 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4168 .modes = &tfc_s9700rtwv43tr_01b_mode, 4169 .num_modes = 1, 4170 .bpc = 8, 4171 .size = { 4172 .width = 155, 4173 .height = 90, 4174 }, 4175 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4176 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4177 }; 4178 4179 static const struct display_timing tianma_tm070jdhg30_timing = { 4180 .pixelclock = { 62600000, 68200000, 78100000 }, 4181 .hactive = { 1280, 1280, 1280 }, 4182 .hfront_porch = { 15, 64, 159 }, 4183 .hback_porch = { 5, 5, 5 }, 4184 .hsync_len = { 1, 1, 256 }, 4185 .vactive = { 800, 800, 800 }, 4186 .vfront_porch = { 3, 40, 99 }, 4187 .vback_porch = { 2, 2, 2 }, 4188 .vsync_len = { 1, 1, 128 }, 4189 .flags = DISPLAY_FLAGS_DE_HIGH, 4190 }; 4191 4192 static const struct panel_desc tianma_tm070jdhg30 = { 4193 .timings = &tianma_tm070jdhg30_timing, 4194 .num_timings = 1, 4195 .bpc = 8, 4196 .size = { 4197 .width = 151, 4198 .height = 95, 4199 }, 4200 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4201 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4202 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4203 }; 4204 4205 static const struct panel_desc tianma_tm070jvhg33 = { 4206 .timings = &tianma_tm070jdhg30_timing, 4207 .num_timings = 1, 4208 .bpc = 8, 4209 .size = { 4210 .width = 150, 4211 .height = 94, 4212 }, 4213 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4214 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4215 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4216 }; 4217 4218 static const struct display_timing tianma_tm070rvhg71_timing = { 4219 .pixelclock = { 27700000, 29200000, 39600000 }, 4220 .hactive = { 800, 800, 800 }, 4221 .hfront_porch = { 12, 40, 212 }, 4222 .hback_porch = { 88, 88, 88 }, 4223 .hsync_len = { 1, 1, 40 }, 4224 .vactive = { 480, 480, 480 }, 4225 .vfront_porch = { 1, 13, 88 }, 4226 .vback_porch = { 32, 32, 32 }, 4227 .vsync_len = { 1, 1, 3 }, 4228 .flags = DISPLAY_FLAGS_DE_HIGH, 4229 }; 4230 4231 static const struct panel_desc tianma_tm070rvhg71 = { 4232 .timings = &tianma_tm070rvhg71_timing, 4233 .num_timings = 1, 4234 .bpc = 8, 4235 .size = { 4236 .width = 154, 4237 .height = 86, 4238 }, 4239 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4240 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4241 }; 4242 4243 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4244 { 4245 .clock = 10000, 4246 .hdisplay = 320, 4247 .hsync_start = 320 + 50, 4248 .hsync_end = 320 + 50 + 6, 4249 .htotal = 320 + 50 + 6 + 38, 4250 .vdisplay = 240, 4251 .vsync_start = 240 + 3, 4252 .vsync_end = 240 + 3 + 1, 4253 .vtotal = 240 + 3 + 1 + 17, 4254 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4255 }, 4256 }; 4257 4258 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4259 .modes = ti_nspire_cx_lcd_mode, 4260 .num_modes = 1, 4261 .bpc = 8, 4262 .size = { 4263 .width = 65, 4264 .height = 49, 4265 }, 4266 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4267 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4268 }; 4269 4270 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4271 { 4272 .clock = 10000, 4273 .hdisplay = 320, 4274 .hsync_start = 320 + 6, 4275 .hsync_end = 320 + 6 + 6, 4276 .htotal = 320 + 6 + 6 + 6, 4277 .vdisplay = 240, 4278 .vsync_start = 240 + 0, 4279 .vsync_end = 240 + 0 + 1, 4280 .vtotal = 240 + 0 + 1 + 0, 4281 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4282 }, 4283 }; 4284 4285 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4286 .modes = ti_nspire_classic_lcd_mode, 4287 .num_modes = 1, 4288 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4289 .bpc = 8, 4290 .size = { 4291 .width = 71, 4292 .height = 53, 4293 }, 4294 /* This is the grayscale bus format */ 4295 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4296 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4297 }; 4298 4299 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4300 .clock = 79500, 4301 .hdisplay = 1280, 4302 .hsync_start = 1280 + 192, 4303 .hsync_end = 1280 + 192 + 128, 4304 .htotal = 1280 + 192 + 128 + 64, 4305 .vdisplay = 768, 4306 .vsync_start = 768 + 20, 4307 .vsync_end = 768 + 20 + 7, 4308 .vtotal = 768 + 20 + 7 + 3, 4309 }; 4310 4311 static const struct panel_desc toshiba_lt089ac29000 = { 4312 .modes = &toshiba_lt089ac29000_mode, 4313 .num_modes = 1, 4314 .size = { 4315 .width = 194, 4316 .height = 116, 4317 }, 4318 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4319 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4320 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4321 }; 4322 4323 static const struct drm_display_mode tpk_f07a_0102_mode = { 4324 .clock = 33260, 4325 .hdisplay = 800, 4326 .hsync_start = 800 + 40, 4327 .hsync_end = 800 + 40 + 128, 4328 .htotal = 800 + 40 + 128 + 88, 4329 .vdisplay = 480, 4330 .vsync_start = 480 + 10, 4331 .vsync_end = 480 + 10 + 2, 4332 .vtotal = 480 + 10 + 2 + 33, 4333 }; 4334 4335 static const struct panel_desc tpk_f07a_0102 = { 4336 .modes = &tpk_f07a_0102_mode, 4337 .num_modes = 1, 4338 .size = { 4339 .width = 152, 4340 .height = 91, 4341 }, 4342 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4343 }; 4344 4345 static const struct drm_display_mode tpk_f10a_0102_mode = { 4346 .clock = 45000, 4347 .hdisplay = 1024, 4348 .hsync_start = 1024 + 176, 4349 .hsync_end = 1024 + 176 + 5, 4350 .htotal = 1024 + 176 + 5 + 88, 4351 .vdisplay = 600, 4352 .vsync_start = 600 + 20, 4353 .vsync_end = 600 + 20 + 5, 4354 .vtotal = 600 + 20 + 5 + 25, 4355 }; 4356 4357 static const struct panel_desc tpk_f10a_0102 = { 4358 .modes = &tpk_f10a_0102_mode, 4359 .num_modes = 1, 4360 .size = { 4361 .width = 223, 4362 .height = 125, 4363 }, 4364 }; 4365 4366 static const struct display_timing urt_umsh_8596md_timing = { 4367 .pixelclock = { 33260000, 33260000, 33260000 }, 4368 .hactive = { 800, 800, 800 }, 4369 .hfront_porch = { 41, 41, 41 }, 4370 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4371 .hsync_len = { 71, 128, 128 }, 4372 .vactive = { 480, 480, 480 }, 4373 .vfront_porch = { 10, 10, 10 }, 4374 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4375 .vsync_len = { 2, 2, 2 }, 4376 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4377 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4378 }; 4379 4380 static const struct panel_desc urt_umsh_8596md_lvds = { 4381 .timings = &urt_umsh_8596md_timing, 4382 .num_timings = 1, 4383 .bpc = 6, 4384 .size = { 4385 .width = 152, 4386 .height = 91, 4387 }, 4388 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4389 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4390 }; 4391 4392 static const struct panel_desc urt_umsh_8596md_parallel = { 4393 .timings = &urt_umsh_8596md_timing, 4394 .num_timings = 1, 4395 .bpc = 6, 4396 .size = { 4397 .width = 152, 4398 .height = 91, 4399 }, 4400 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4401 }; 4402 4403 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4404 .clock = 60000, 4405 .hdisplay = 1024, 4406 .hsync_start = 1024 + 160, 4407 .hsync_end = 1024 + 160 + 100, 4408 .htotal = 1024 + 160 + 100 + 60, 4409 .vdisplay = 600, 4410 .vsync_start = 600 + 12, 4411 .vsync_end = 600 + 12 + 10, 4412 .vtotal = 600 + 12 + 10 + 13, 4413 }; 4414 4415 static const struct panel_desc vivax_tpc9150_panel = { 4416 .modes = &vivax_tpc9150_panel_mode, 4417 .num_modes = 1, 4418 .bpc = 6, 4419 .size = { 4420 .width = 200, 4421 .height = 115, 4422 }, 4423 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4424 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4425 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4426 }; 4427 4428 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4429 .clock = 33333, 4430 .hdisplay = 800, 4431 .hsync_start = 800 + 210, 4432 .hsync_end = 800 + 210 + 20, 4433 .htotal = 800 + 210 + 20 + 46, 4434 .vdisplay = 480, 4435 .vsync_start = 480 + 22, 4436 .vsync_end = 480 + 22 + 10, 4437 .vtotal = 480 + 22 + 10 + 23, 4438 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4439 }; 4440 4441 static const struct panel_desc vl050_8048nt_c01 = { 4442 .modes = &vl050_8048nt_c01_mode, 4443 .num_modes = 1, 4444 .bpc = 8, 4445 .size = { 4446 .width = 120, 4447 .height = 76, 4448 }, 4449 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4450 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4451 }; 4452 4453 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4454 .clock = 6410, 4455 .hdisplay = 320, 4456 .hsync_start = 320 + 20, 4457 .hsync_end = 320 + 20 + 30, 4458 .htotal = 320 + 20 + 30 + 38, 4459 .vdisplay = 240, 4460 .vsync_start = 240 + 4, 4461 .vsync_end = 240 + 4 + 3, 4462 .vtotal = 240 + 4 + 3 + 15, 4463 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4464 }; 4465 4466 static const struct panel_desc winstar_wf35ltiacd = { 4467 .modes = &winstar_wf35ltiacd_mode, 4468 .num_modes = 1, 4469 .bpc = 8, 4470 .size = { 4471 .width = 70, 4472 .height = 53, 4473 }, 4474 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4475 }; 4476 4477 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4478 .clock = 51200, 4479 .hdisplay = 1024, 4480 .hsync_start = 1024 + 100, 4481 .hsync_end = 1024 + 100 + 100, 4482 .htotal = 1024 + 100 + 100 + 120, 4483 .vdisplay = 600, 4484 .vsync_start = 600 + 10, 4485 .vsync_end = 600 + 10 + 10, 4486 .vtotal = 600 + 10 + 10 + 15, 4487 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4488 }; 4489 4490 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4491 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4492 .num_modes = 1, 4493 .bpc = 8, 4494 .size = { 4495 .width = 154, 4496 .height = 90, 4497 }, 4498 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4499 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4500 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4501 }; 4502 4503 static const struct drm_display_mode arm_rtsm_mode[] = { 4504 { 4505 .clock = 65000, 4506 .hdisplay = 1024, 4507 .hsync_start = 1024 + 24, 4508 .hsync_end = 1024 + 24 + 136, 4509 .htotal = 1024 + 24 + 136 + 160, 4510 .vdisplay = 768, 4511 .vsync_start = 768 + 3, 4512 .vsync_end = 768 + 3 + 6, 4513 .vtotal = 768 + 3 + 6 + 29, 4514 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4515 }, 4516 }; 4517 4518 static const struct panel_desc arm_rtsm = { 4519 .modes = arm_rtsm_mode, 4520 .num_modes = 1, 4521 .bpc = 8, 4522 .size = { 4523 .width = 400, 4524 .height = 300, 4525 }, 4526 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4527 }; 4528 4529 static const struct of_device_id platform_of_match[] = { 4530 { 4531 .compatible = "ampire,am-1280800n3tzqw-t00h", 4532 .data = &ire_am_1280800n3tzqw_t00h, 4533 }, { 4534 .compatible = "ampire,am-480272h3tmqw-t01h", 4535 .data = &ire_am_480272h3tmqw_t01h, 4536 }, { 4537 .compatible = "ampire,am-800480l1tmqw-t00h", 4538 .data = &ire_am_800480l1tmqw_t00h, 4539 }, { 4540 .compatible = "ampire,am800480r3tmqwa1h", 4541 .data = &ire_am800480r3tmqwa1h, 4542 }, { 4543 .compatible = "ampire,am800600p5tmqw-tb8h", 4544 .data = &ire_am800600p5tmqwtb8h, 4545 }, { 4546 .compatible = "arm,rtsm-display", 4547 .data = &arm_rtsm, 4548 }, { 4549 .compatible = "armadeus,st0700-adapt", 4550 .data = &armadeus_st0700_adapt, 4551 }, { 4552 .compatible = "auo,b101aw03", 4553 .data = &auo_b101aw03, 4554 }, { 4555 .compatible = "auo,b101xtn01", 4556 .data = &auo_b101xtn01, 4557 }, { 4558 .compatible = "auo,b116xw03", 4559 .data = &auo_b116xw03, 4560 }, { 4561 .compatible = "auo,g070vvn01", 4562 .data = &auo_g070vvn01, 4563 }, { 4564 .compatible = "auo,g101evn010", 4565 .data = &auo_g101evn010, 4566 }, { 4567 .compatible = "auo,g104sn02", 4568 .data = &auo_g104sn02, 4569 }, { 4570 .compatible = "auo,g104stn01", 4571 .data = &auo_g104stn01, 4572 }, { 4573 .compatible = "auo,g121ean01", 4574 .data = &auo_g121ean01, 4575 }, { 4576 .compatible = "auo,g133han01", 4577 .data = &auo_g133han01, 4578 }, { 4579 .compatible = "auo,g156han04", 4580 .data = &auo_g156han04, 4581 }, { 4582 .compatible = "auo,g156xtn01", 4583 .data = &auo_g156xtn01, 4584 }, { 4585 .compatible = "auo,g185han01", 4586 .data = &auo_g185han01, 4587 }, { 4588 .compatible = "auo,g190ean01", 4589 .data = &auo_g190ean01, 4590 }, { 4591 .compatible = "auo,p320hvn03", 4592 .data = &auo_p320hvn03, 4593 }, { 4594 .compatible = "auo,t215hvn01", 4595 .data = &auo_t215hvn01, 4596 }, { 4597 .compatible = "avic,tm070ddh03", 4598 .data = &avic_tm070ddh03, 4599 }, { 4600 .compatible = "bananapi,s070wv20-ct16", 4601 .data = &bananapi_s070wv20_ct16, 4602 }, { 4603 .compatible = "boe,bp082wx1-100", 4604 .data = &boe_bp082wx1_100, 4605 }, { 4606 .compatible = "boe,bp101wx1-100", 4607 .data = &boe_bp101wx1_100, 4608 }, { 4609 .compatible = "boe,ev121wxm-n10-1850", 4610 .data = &boe_ev121wxm_n10_1850, 4611 }, { 4612 .compatible = "boe,hv070wsa-100", 4613 .data = &boe_hv070wsa 4614 }, { 4615 .compatible = "cct,cmt430b19n00", 4616 .data = &cct_cmt430b19n00, 4617 }, { 4618 .compatible = "cdtech,s043wq26h-ct7", 4619 .data = &cdtech_s043wq26h_ct7, 4620 }, { 4621 .compatible = "cdtech,s070pws19hp-fc21", 4622 .data = &cdtech_s070pws19hp_fc21, 4623 }, { 4624 .compatible = "cdtech,s070swv29hg-dc44", 4625 .data = &cdtech_s070swv29hg_dc44, 4626 }, { 4627 .compatible = "cdtech,s070wv95-ct16", 4628 .data = &cdtech_s070wv95_ct16, 4629 }, { 4630 .compatible = "chefree,ch101olhlwh-002", 4631 .data = &chefree_ch101olhlwh_002, 4632 }, { 4633 .compatible = "chunghwa,claa070wp03xg", 4634 .data = &chunghwa_claa070wp03xg, 4635 }, { 4636 .compatible = "chunghwa,claa101wa01a", 4637 .data = &chunghwa_claa101wa01a 4638 }, { 4639 .compatible = "chunghwa,claa101wb01", 4640 .data = &chunghwa_claa101wb01 4641 }, { 4642 .compatible = "dataimage,fg040346dsswbg04", 4643 .data = &dataimage_fg040346dsswbg04, 4644 }, { 4645 .compatible = "dataimage,fg1001l0dsswmg01", 4646 .data = &dataimage_fg1001l0dsswmg01, 4647 }, { 4648 .compatible = "dataimage,scf0700c48ggu18", 4649 .data = &dataimage_scf0700c48ggu18, 4650 }, { 4651 .compatible = "dlc,dlc0700yzg-1", 4652 .data = &dlc_dlc0700yzg_1, 4653 }, { 4654 .compatible = "dlc,dlc1010gig", 4655 .data = &dlc_dlc1010gig, 4656 }, { 4657 .compatible = "edt,et035012dm6", 4658 .data = &edt_et035012dm6, 4659 }, { 4660 .compatible = "edt,etm0350g0dh6", 4661 .data = &edt_etm0350g0dh6, 4662 }, { 4663 .compatible = "edt,etm043080dh6gp", 4664 .data = &edt_etm043080dh6gp, 4665 }, { 4666 .compatible = "edt,etm0430g0dh6", 4667 .data = &edt_etm0430g0dh6, 4668 }, { 4669 .compatible = "edt,et057090dhu", 4670 .data = &edt_et057090dhu, 4671 }, { 4672 .compatible = "edt,et070080dh6", 4673 .data = &edt_etm0700g0dh6, 4674 }, { 4675 .compatible = "edt,etm0700g0dh6", 4676 .data = &edt_etm0700g0dh6, 4677 }, { 4678 .compatible = "edt,etm0700g0bdh6", 4679 .data = &edt_etm0700g0bdh6, 4680 }, { 4681 .compatible = "edt,etm0700g0edh6", 4682 .data = &edt_etm0700g0bdh6, 4683 }, { 4684 .compatible = "edt,etml0700y5dha", 4685 .data = &edt_etml0700y5dha, 4686 }, { 4687 .compatible = "edt,etml1010g3dra", 4688 .data = &edt_etml1010g3dra, 4689 }, { 4690 .compatible = "edt,etmv570g2dhu", 4691 .data = &edt_etmv570g2dhu, 4692 }, { 4693 .compatible = "eink,vb3300-kca", 4694 .data = &eink_vb3300_kca, 4695 }, { 4696 .compatible = "evervision,vgg644804", 4697 .data = &evervision_vgg644804, 4698 }, { 4699 .compatible = "evervision,vgg804821", 4700 .data = &evervision_vgg804821, 4701 }, { 4702 .compatible = "foxlink,fl500wvr00-a0t", 4703 .data = &foxlink_fl500wvr00_a0t, 4704 }, { 4705 .compatible = "frida,frd350h54004", 4706 .data = &frida_frd350h54004, 4707 }, { 4708 .compatible = "friendlyarm,hd702e", 4709 .data = &friendlyarm_hd702e, 4710 }, { 4711 .compatible = "giantplus,gpg482739qs5", 4712 .data = &giantplus_gpg482739qs5 4713 }, { 4714 .compatible = "giantplus,gpm940b0", 4715 .data = &giantplus_gpm940b0, 4716 }, { 4717 .compatible = "hannstar,hsd070pww1", 4718 .data = &hannstar_hsd070pww1, 4719 }, { 4720 .compatible = "hannstar,hsd100pxn1", 4721 .data = &hannstar_hsd100pxn1, 4722 }, { 4723 .compatible = "hannstar,hsd101pww2", 4724 .data = &hannstar_hsd101pww2, 4725 }, { 4726 .compatible = "hit,tx23d38vm0caa", 4727 .data = &hitachi_tx23d38vm0caa 4728 }, { 4729 .compatible = "innolux,at043tn24", 4730 .data = &innolux_at043tn24, 4731 }, { 4732 .compatible = "innolux,at070tn92", 4733 .data = &innolux_at070tn92, 4734 }, { 4735 .compatible = "innolux,g070ace-l01", 4736 .data = &innolux_g070ace_l01, 4737 }, { 4738 .compatible = "innolux,g070y2-l01", 4739 .data = &innolux_g070y2_l01, 4740 }, { 4741 .compatible = "innolux,g070y2-t02", 4742 .data = &innolux_g070y2_t02, 4743 }, { 4744 .compatible = "innolux,g101ice-l01", 4745 .data = &innolux_g101ice_l01 4746 }, { 4747 .compatible = "innolux,g121i1-l01", 4748 .data = &innolux_g121i1_l01 4749 }, { 4750 .compatible = "innolux,g121x1-l03", 4751 .data = &innolux_g121x1_l03, 4752 }, { 4753 .compatible = "innolux,g121xce-l01", 4754 .data = &innolux_g121xce_l01, 4755 }, { 4756 .compatible = "innolux,g156hce-l01", 4757 .data = &innolux_g156hce_l01, 4758 }, { 4759 .compatible = "innolux,n156bge-l21", 4760 .data = &innolux_n156bge_l21, 4761 }, { 4762 .compatible = "innolux,zj070na-01p", 4763 .data = &innolux_zj070na_01p, 4764 }, { 4765 .compatible = "koe,tx14d24vm1bpa", 4766 .data = &koe_tx14d24vm1bpa, 4767 }, { 4768 .compatible = "koe,tx26d202vm0bwa", 4769 .data = &koe_tx26d202vm0bwa, 4770 }, { 4771 .compatible = "koe,tx31d200vm0baa", 4772 .data = &koe_tx31d200vm0baa, 4773 }, { 4774 .compatible = "kyo,tcg121xglp", 4775 .data = &kyo_tcg121xglp, 4776 }, { 4777 .compatible = "lemaker,bl035-rgb-002", 4778 .data = &lemaker_bl035_rgb_002, 4779 }, { 4780 .compatible = "lg,lb070wv8", 4781 .data = &lg_lb070wv8, 4782 }, { 4783 .compatible = "lincolntech,lcd185-101ct", 4784 .data = &lincolntech_lcd185_101ct, 4785 }, { 4786 .compatible = "logicpd,type28", 4787 .data = &logicpd_type_28, 4788 }, { 4789 .compatible = "logictechno,lt161010-2nhc", 4790 .data = &logictechno_lt161010_2nh, 4791 }, { 4792 .compatible = "logictechno,lt161010-2nhr", 4793 .data = &logictechno_lt161010_2nh, 4794 }, { 4795 .compatible = "logictechno,lt170410-2whc", 4796 .data = &logictechno_lt170410_2whc, 4797 }, { 4798 .compatible = "logictechno,lttd800480070-l2rt", 4799 .data = &logictechno_lttd800480070_l2rt, 4800 }, { 4801 .compatible = "logictechno,lttd800480070-l6wh-rt", 4802 .data = &logictechno_lttd800480070_l6wh_rt, 4803 }, { 4804 .compatible = "microtips,mf-101hiebcaf0", 4805 .data = µtips_mf_101hiebcaf0_c, 4806 }, { 4807 .compatible = "microtips,mf-103hieb0ga0", 4808 .data = µtips_mf_103hieb0ga0, 4809 }, { 4810 .compatible = "mitsubishi,aa070mc01-ca1", 4811 .data = &mitsubishi_aa070mc01, 4812 }, { 4813 .compatible = "mitsubishi,aa084xe01", 4814 .data = &mitsubishi_aa084xe01, 4815 }, { 4816 .compatible = "multi-inno,mi0700s4t-6", 4817 .data = &multi_inno_mi0700s4t_6, 4818 }, { 4819 .compatible = "multi-inno,mi0800ft-9", 4820 .data = &multi_inno_mi0800ft_9, 4821 }, { 4822 .compatible = "multi-inno,mi1010ait-1cp", 4823 .data = &multi_inno_mi1010ait_1cp, 4824 }, { 4825 .compatible = "nec,nl12880bc20-05", 4826 .data = &nec_nl12880bc20_05, 4827 }, { 4828 .compatible = "nec,nl4827hc19-05b", 4829 .data = &nec_nl4827hc19_05b, 4830 }, { 4831 .compatible = "netron-dy,e231732", 4832 .data = &netron_dy_e231732, 4833 }, { 4834 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4835 .data = &newhaven_nhd_43_480272ef_atxl, 4836 }, { 4837 .compatible = "nlt,nl192108ac18-02d", 4838 .data = &nlt_nl192108ac18_02d, 4839 }, { 4840 .compatible = "nvd,9128", 4841 .data = &nvd_9128, 4842 }, { 4843 .compatible = "okaya,rs800480t-7x0gp", 4844 .data = &okaya_rs800480t_7x0gp, 4845 }, { 4846 .compatible = "olimex,lcd-olinuxino-43-ts", 4847 .data = &olimex_lcd_olinuxino_43ts, 4848 }, { 4849 .compatible = "ontat,yx700wv03", 4850 .data = &ontat_yx700wv03, 4851 }, { 4852 .compatible = "ortustech,com37h3m05dtc", 4853 .data = &ortustech_com37h3m, 4854 }, { 4855 .compatible = "ortustech,com37h3m99dtc", 4856 .data = &ortustech_com37h3m, 4857 }, { 4858 .compatible = "ortustech,com43h4m85ulc", 4859 .data = &ortustech_com43h4m85ulc, 4860 }, { 4861 .compatible = "osddisplays,osd070t1718-19ts", 4862 .data = &osddisplays_osd070t1718_19ts, 4863 }, { 4864 .compatible = "pda,91-00156-a0", 4865 .data = &pda_91_00156_a0, 4866 }, { 4867 .compatible = "powertip,ph128800t006-zhc01", 4868 .data = &powertip_ph128800t006_zhc01, 4869 }, { 4870 .compatible = "powertip,ph800480t013-idf02", 4871 .data = &powertip_ph800480t013_idf02, 4872 }, { 4873 .compatible = "primeview,pm070wl4", 4874 .data = &primeview_pm070wl4, 4875 }, { 4876 .compatible = "qiaodian,qd43003c0-40", 4877 .data = &qd43003c0_40, 4878 }, { 4879 .compatible = "qishenglong,gopher2b-lcd", 4880 .data = &qishenglong_gopher2b_lcd, 4881 }, { 4882 .compatible = "rocktech,rk043fn48h", 4883 .data = &rocktech_rk043fn48h, 4884 }, { 4885 .compatible = "rocktech,rk070er9427", 4886 .data = &rocktech_rk070er9427, 4887 }, { 4888 .compatible = "rocktech,rk101ii01d-ct", 4889 .data = &rocktech_rk101ii01d_ct, 4890 }, { 4891 .compatible = "samsung,ltl101al01", 4892 .data = &samsung_ltl101al01, 4893 }, { 4894 .compatible = "samsung,ltn101nt05", 4895 .data = &samsung_ltn101nt05, 4896 }, { 4897 .compatible = "satoz,sat050at40h12r2", 4898 .data = &satoz_sat050at40h12r2, 4899 }, { 4900 .compatible = "sharp,lq035q7db03", 4901 .data = &sharp_lq035q7db03, 4902 }, { 4903 .compatible = "sharp,lq070y3dg3b", 4904 .data = &sharp_lq070y3dg3b, 4905 }, { 4906 .compatible = "sharp,lq101k1ly04", 4907 .data = &sharp_lq101k1ly04, 4908 }, { 4909 .compatible = "sharp,ls020b1dd01d", 4910 .data = &sharp_ls020b1dd01d, 4911 }, { 4912 .compatible = "shelly,sca07010-bfn-lnn", 4913 .data = &shelly_sca07010_bfn_lnn, 4914 }, { 4915 .compatible = "starry,kr070pe2t", 4916 .data = &starry_kr070pe2t, 4917 }, { 4918 .compatible = "startek,kd070wvfpa", 4919 .data = &startek_kd070wvfpa, 4920 }, { 4921 .compatible = "team-source-display,tst043015cmhx", 4922 .data = &tsd_tst043015cmhx, 4923 }, { 4924 .compatible = "tfc,s9700rtwv43tr-01b", 4925 .data = &tfc_s9700rtwv43tr_01b, 4926 }, { 4927 .compatible = "tianma,tm070jdhg30", 4928 .data = &tianma_tm070jdhg30, 4929 }, { 4930 .compatible = "tianma,tm070jvhg33", 4931 .data = &tianma_tm070jvhg33, 4932 }, { 4933 .compatible = "tianma,tm070rvhg71", 4934 .data = &tianma_tm070rvhg71, 4935 }, { 4936 .compatible = "ti,nspire-cx-lcd-panel", 4937 .data = &ti_nspire_cx_lcd_panel, 4938 }, { 4939 .compatible = "ti,nspire-classic-lcd-panel", 4940 .data = &ti_nspire_classic_lcd_panel, 4941 }, { 4942 .compatible = "toshiba,lt089ac29000", 4943 .data = &toshiba_lt089ac29000, 4944 }, { 4945 .compatible = "tpk,f07a-0102", 4946 .data = &tpk_f07a_0102, 4947 }, { 4948 .compatible = "tpk,f10a-0102", 4949 .data = &tpk_f10a_0102, 4950 }, { 4951 .compatible = "urt,umsh-8596md-t", 4952 .data = &urt_umsh_8596md_parallel, 4953 }, { 4954 .compatible = "urt,umsh-8596md-1t", 4955 .data = &urt_umsh_8596md_parallel, 4956 }, { 4957 .compatible = "urt,umsh-8596md-7t", 4958 .data = &urt_umsh_8596md_parallel, 4959 }, { 4960 .compatible = "urt,umsh-8596md-11t", 4961 .data = &urt_umsh_8596md_lvds, 4962 }, { 4963 .compatible = "urt,umsh-8596md-19t", 4964 .data = &urt_umsh_8596md_lvds, 4965 }, { 4966 .compatible = "urt,umsh-8596md-20t", 4967 .data = &urt_umsh_8596md_parallel, 4968 }, { 4969 .compatible = "vivax,tpc9150-panel", 4970 .data = &vivax_tpc9150_panel, 4971 }, { 4972 .compatible = "vxt,vl050-8048nt-c01", 4973 .data = &vl050_8048nt_c01, 4974 }, { 4975 .compatible = "winstar,wf35ltiacd", 4976 .data = &winstar_wf35ltiacd, 4977 }, { 4978 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4979 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4980 }, { 4981 /* Must be the last entry */ 4982 .compatible = "panel-dpi", 4983 .data = &panel_dpi, 4984 }, { 4985 /* sentinel */ 4986 } 4987 }; 4988 MODULE_DEVICE_TABLE(of, platform_of_match); 4989 4990 static int panel_simple_platform_probe(struct platform_device *pdev) 4991 { 4992 const struct panel_desc *desc; 4993 4994 desc = of_device_get_match_data(&pdev->dev); 4995 if (!desc) 4996 return -ENODEV; 4997 4998 return panel_simple_probe(&pdev->dev, desc); 4999 } 5000 5001 static void panel_simple_platform_remove(struct platform_device *pdev) 5002 { 5003 panel_simple_remove(&pdev->dev); 5004 } 5005 5006 static void panel_simple_platform_shutdown(struct platform_device *pdev) 5007 { 5008 panel_simple_shutdown(&pdev->dev); 5009 } 5010 5011 static const struct dev_pm_ops panel_simple_pm_ops = { 5012 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 5013 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5014 pm_runtime_force_resume) 5015 }; 5016 5017 static struct platform_driver panel_simple_platform_driver = { 5018 .driver = { 5019 .name = "panel-simple", 5020 .of_match_table = platform_of_match, 5021 .pm = &panel_simple_pm_ops, 5022 }, 5023 .probe = panel_simple_platform_probe, 5024 .remove_new = panel_simple_platform_remove, 5025 .shutdown = panel_simple_platform_shutdown, 5026 }; 5027 5028 struct panel_desc_dsi { 5029 struct panel_desc desc; 5030 5031 unsigned long flags; 5032 enum mipi_dsi_pixel_format format; 5033 unsigned int lanes; 5034 }; 5035 5036 static const struct drm_display_mode auo_b080uan01_mode = { 5037 .clock = 154500, 5038 .hdisplay = 1200, 5039 .hsync_start = 1200 + 62, 5040 .hsync_end = 1200 + 62 + 4, 5041 .htotal = 1200 + 62 + 4 + 62, 5042 .vdisplay = 1920, 5043 .vsync_start = 1920 + 9, 5044 .vsync_end = 1920 + 9 + 2, 5045 .vtotal = 1920 + 9 + 2 + 8, 5046 }; 5047 5048 static const struct panel_desc_dsi auo_b080uan01 = { 5049 .desc = { 5050 .modes = &auo_b080uan01_mode, 5051 .num_modes = 1, 5052 .bpc = 8, 5053 .size = { 5054 .width = 108, 5055 .height = 272, 5056 }, 5057 .connector_type = DRM_MODE_CONNECTOR_DSI, 5058 }, 5059 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5060 .format = MIPI_DSI_FMT_RGB888, 5061 .lanes = 4, 5062 }; 5063 5064 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5065 .clock = 160000, 5066 .hdisplay = 1200, 5067 .hsync_start = 1200 + 120, 5068 .hsync_end = 1200 + 120 + 20, 5069 .htotal = 1200 + 120 + 20 + 21, 5070 .vdisplay = 1920, 5071 .vsync_start = 1920 + 21, 5072 .vsync_end = 1920 + 21 + 3, 5073 .vtotal = 1920 + 21 + 3 + 18, 5074 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5075 }; 5076 5077 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5078 .desc = { 5079 .modes = &boe_tv080wum_nl0_mode, 5080 .num_modes = 1, 5081 .size = { 5082 .width = 107, 5083 .height = 172, 5084 }, 5085 .connector_type = DRM_MODE_CONNECTOR_DSI, 5086 }, 5087 .flags = MIPI_DSI_MODE_VIDEO | 5088 MIPI_DSI_MODE_VIDEO_BURST | 5089 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5090 .format = MIPI_DSI_FMT_RGB888, 5091 .lanes = 4, 5092 }; 5093 5094 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 5095 .clock = 71000, 5096 .hdisplay = 800, 5097 .hsync_start = 800 + 32, 5098 .hsync_end = 800 + 32 + 1, 5099 .htotal = 800 + 32 + 1 + 57, 5100 .vdisplay = 1280, 5101 .vsync_start = 1280 + 28, 5102 .vsync_end = 1280 + 28 + 1, 5103 .vtotal = 1280 + 28 + 1 + 14, 5104 }; 5105 5106 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 5107 .desc = { 5108 .modes = &lg_ld070wx3_sl01_mode, 5109 .num_modes = 1, 5110 .bpc = 8, 5111 .size = { 5112 .width = 94, 5113 .height = 151, 5114 }, 5115 .connector_type = DRM_MODE_CONNECTOR_DSI, 5116 }, 5117 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5118 .format = MIPI_DSI_FMT_RGB888, 5119 .lanes = 4, 5120 }; 5121 5122 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5123 .clock = 67000, 5124 .hdisplay = 720, 5125 .hsync_start = 720 + 12, 5126 .hsync_end = 720 + 12 + 4, 5127 .htotal = 720 + 12 + 4 + 112, 5128 .vdisplay = 1280, 5129 .vsync_start = 1280 + 8, 5130 .vsync_end = 1280 + 8 + 4, 5131 .vtotal = 1280 + 8 + 4 + 12, 5132 }; 5133 5134 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5135 .desc = { 5136 .modes = &lg_lh500wx1_sd03_mode, 5137 .num_modes = 1, 5138 .bpc = 8, 5139 .size = { 5140 .width = 62, 5141 .height = 110, 5142 }, 5143 .connector_type = DRM_MODE_CONNECTOR_DSI, 5144 }, 5145 .flags = MIPI_DSI_MODE_VIDEO, 5146 .format = MIPI_DSI_FMT_RGB888, 5147 .lanes = 4, 5148 }; 5149 5150 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5151 .clock = 157200, 5152 .hdisplay = 1920, 5153 .hsync_start = 1920 + 154, 5154 .hsync_end = 1920 + 154 + 16, 5155 .htotal = 1920 + 154 + 16 + 32, 5156 .vdisplay = 1200, 5157 .vsync_start = 1200 + 17, 5158 .vsync_end = 1200 + 17 + 2, 5159 .vtotal = 1200 + 17 + 2 + 16, 5160 }; 5161 5162 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5163 .desc = { 5164 .modes = &panasonic_vvx10f004b00_mode, 5165 .num_modes = 1, 5166 .bpc = 8, 5167 .size = { 5168 .width = 217, 5169 .height = 136, 5170 }, 5171 .connector_type = DRM_MODE_CONNECTOR_DSI, 5172 }, 5173 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5174 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5175 .format = MIPI_DSI_FMT_RGB888, 5176 .lanes = 4, 5177 }; 5178 5179 static const struct drm_display_mode lg_acx467akm_7_mode = { 5180 .clock = 150000, 5181 .hdisplay = 1080, 5182 .hsync_start = 1080 + 2, 5183 .hsync_end = 1080 + 2 + 2, 5184 .htotal = 1080 + 2 + 2 + 2, 5185 .vdisplay = 1920, 5186 .vsync_start = 1920 + 2, 5187 .vsync_end = 1920 + 2 + 2, 5188 .vtotal = 1920 + 2 + 2 + 2, 5189 }; 5190 5191 static const struct panel_desc_dsi lg_acx467akm_7 = { 5192 .desc = { 5193 .modes = &lg_acx467akm_7_mode, 5194 .num_modes = 1, 5195 .bpc = 8, 5196 .size = { 5197 .width = 62, 5198 .height = 110, 5199 }, 5200 .connector_type = DRM_MODE_CONNECTOR_DSI, 5201 }, 5202 .flags = 0, 5203 .format = MIPI_DSI_FMT_RGB888, 5204 .lanes = 4, 5205 }; 5206 5207 static const struct drm_display_mode osd101t2045_53ts_mode = { 5208 .clock = 154500, 5209 .hdisplay = 1920, 5210 .hsync_start = 1920 + 112, 5211 .hsync_end = 1920 + 112 + 16, 5212 .htotal = 1920 + 112 + 16 + 32, 5213 .vdisplay = 1200, 5214 .vsync_start = 1200 + 16, 5215 .vsync_end = 1200 + 16 + 2, 5216 .vtotal = 1200 + 16 + 2 + 16, 5217 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5218 }; 5219 5220 static const struct panel_desc_dsi osd101t2045_53ts = { 5221 .desc = { 5222 .modes = &osd101t2045_53ts_mode, 5223 .num_modes = 1, 5224 .bpc = 8, 5225 .size = { 5226 .width = 217, 5227 .height = 136, 5228 }, 5229 .connector_type = DRM_MODE_CONNECTOR_DSI, 5230 }, 5231 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5232 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5233 MIPI_DSI_MODE_NO_EOT_PACKET, 5234 .format = MIPI_DSI_FMT_RGB888, 5235 .lanes = 4, 5236 }; 5237 5238 static const struct of_device_id dsi_of_match[] = { 5239 { 5240 .compatible = "auo,b080uan01", 5241 .data = &auo_b080uan01 5242 }, { 5243 .compatible = "boe,tv080wum-nl0", 5244 .data = &boe_tv080wum_nl0 5245 }, { 5246 .compatible = "lg,ld070wx3-sl01", 5247 .data = &lg_ld070wx3_sl01 5248 }, { 5249 .compatible = "lg,lh500wx1-sd03", 5250 .data = &lg_lh500wx1_sd03 5251 }, { 5252 .compatible = "panasonic,vvx10f004b00", 5253 .data = &panasonic_vvx10f004b00 5254 }, { 5255 .compatible = "lg,acx467akm-7", 5256 .data = &lg_acx467akm_7 5257 }, { 5258 .compatible = "osddisplays,osd101t2045-53ts", 5259 .data = &osd101t2045_53ts 5260 }, { 5261 /* sentinel */ 5262 } 5263 }; 5264 MODULE_DEVICE_TABLE(of, dsi_of_match); 5265 5266 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5267 { 5268 const struct panel_desc_dsi *desc; 5269 int err; 5270 5271 desc = of_device_get_match_data(&dsi->dev); 5272 if (!desc) 5273 return -ENODEV; 5274 5275 err = panel_simple_probe(&dsi->dev, &desc->desc); 5276 if (err < 0) 5277 return err; 5278 5279 dsi->mode_flags = desc->flags; 5280 dsi->format = desc->format; 5281 dsi->lanes = desc->lanes; 5282 5283 err = mipi_dsi_attach(dsi); 5284 if (err) { 5285 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5286 5287 drm_panel_remove(&panel->base); 5288 } 5289 5290 return err; 5291 } 5292 5293 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5294 { 5295 int err; 5296 5297 err = mipi_dsi_detach(dsi); 5298 if (err < 0) 5299 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5300 5301 panel_simple_remove(&dsi->dev); 5302 } 5303 5304 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5305 { 5306 panel_simple_shutdown(&dsi->dev); 5307 } 5308 5309 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5310 .driver = { 5311 .name = "panel-simple-dsi", 5312 .of_match_table = dsi_of_match, 5313 .pm = &panel_simple_pm_ops, 5314 }, 5315 .probe = panel_simple_dsi_probe, 5316 .remove = panel_simple_dsi_remove, 5317 .shutdown = panel_simple_dsi_shutdown, 5318 }; 5319 5320 static int __init panel_simple_init(void) 5321 { 5322 int err; 5323 5324 err = platform_driver_register(&panel_simple_platform_driver); 5325 if (err < 0) 5326 return err; 5327 5328 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5329 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5330 if (err < 0) 5331 goto err_did_platform_register; 5332 } 5333 5334 return 0; 5335 5336 err_did_platform_register: 5337 platform_driver_unregister(&panel_simple_platform_driver); 5338 5339 return err; 5340 } 5341 module_init(panel_simple_init); 5342 5343 static void __exit panel_simple_exit(void) 5344 { 5345 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5346 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5347 5348 platform_driver_unregister(&panel_simple_platform_driver); 5349 } 5350 module_exit(panel_simple_exit); 5351 5352 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5353 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5354 MODULE_LICENSE("GPL and additional rights"); 5355