1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 bool enabled; 142 143 bool prepared; 144 145 ktime_t unprepared_time; 146 147 const struct panel_desc *desc; 148 149 struct regulator *supply; 150 struct i2c_adapter *ddc; 151 152 struct gpio_desc *enable_gpio; 153 154 struct edid *edid; 155 156 struct drm_display_mode override_mode; 157 158 enum drm_panel_orientation orientation; 159 }; 160 161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 162 { 163 return container_of(panel, struct panel_simple, base); 164 } 165 166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 167 struct drm_connector *connector) 168 { 169 struct drm_display_mode *mode; 170 unsigned int i, num = 0; 171 172 for (i = 0; i < panel->desc->num_timings; i++) { 173 const struct display_timing *dt = &panel->desc->timings[i]; 174 struct videomode vm; 175 176 videomode_from_timing(dt, &vm); 177 mode = drm_mode_create(connector->dev); 178 if (!mode) { 179 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 180 dt->hactive.typ, dt->vactive.typ); 181 continue; 182 } 183 184 drm_display_mode_from_videomode(&vm, mode); 185 186 mode->type |= DRM_MODE_TYPE_DRIVER; 187 188 if (panel->desc->num_timings == 1) 189 mode->type |= DRM_MODE_TYPE_PREFERRED; 190 191 drm_mode_probed_add(connector, mode); 192 num++; 193 } 194 195 return num; 196 } 197 198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 199 struct drm_connector *connector) 200 { 201 struct drm_display_mode *mode; 202 unsigned int i, num = 0; 203 204 for (i = 0; i < panel->desc->num_modes; i++) { 205 const struct drm_display_mode *m = &panel->desc->modes[i]; 206 207 mode = drm_mode_duplicate(connector->dev, m); 208 if (!mode) { 209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 210 m->hdisplay, m->vdisplay, 211 drm_mode_vrefresh(m)); 212 continue; 213 } 214 215 mode->type |= DRM_MODE_TYPE_DRIVER; 216 217 if (panel->desc->num_modes == 1) 218 mode->type |= DRM_MODE_TYPE_PREFERRED; 219 220 drm_mode_set_name(mode); 221 222 drm_mode_probed_add(connector, mode); 223 num++; 224 } 225 226 return num; 227 } 228 229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 230 struct drm_connector *connector) 231 { 232 struct drm_display_mode *mode; 233 bool has_override = panel->override_mode.type; 234 unsigned int num = 0; 235 236 if (!panel->desc) 237 return 0; 238 239 if (has_override) { 240 mode = drm_mode_duplicate(connector->dev, 241 &panel->override_mode); 242 if (mode) { 243 drm_mode_probed_add(connector, mode); 244 num = 1; 245 } else { 246 dev_err(panel->base.dev, "failed to add override mode\n"); 247 } 248 } 249 250 /* Only add timings if override was not there or failed to validate */ 251 if (num == 0 && panel->desc->num_timings) 252 num = panel_simple_get_timings_modes(panel, connector); 253 254 /* 255 * Only add fixed modes if timings/override added no mode. 256 * 257 * We should only ever have either the display timings specified 258 * or a fixed mode. Anything else is rather bogus. 259 */ 260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 261 if (num == 0) 262 num = panel_simple_get_display_modes(panel, connector); 263 264 connector->display_info.bpc = panel->desc->bpc; 265 connector->display_info.width_mm = panel->desc->size.width; 266 connector->display_info.height_mm = panel->desc->size.height; 267 if (panel->desc->bus_format) 268 drm_display_info_set_bus_formats(&connector->display_info, 269 &panel->desc->bus_format, 1); 270 connector->display_info.bus_flags = panel->desc->bus_flags; 271 272 return num; 273 } 274 275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 276 { 277 ktime_t now_ktime, min_ktime; 278 279 if (!min_ms) 280 return; 281 282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 283 now_ktime = ktime_get_boottime(); 284 285 if (ktime_before(now_ktime, min_ktime)) 286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 287 } 288 289 static int panel_simple_disable(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 293 if (!p->enabled) 294 return 0; 295 296 if (p->desc->delay.disable) 297 msleep(p->desc->delay.disable); 298 299 p->enabled = false; 300 301 return 0; 302 } 303 304 static int panel_simple_suspend(struct device *dev) 305 { 306 struct panel_simple *p = dev_get_drvdata(dev); 307 308 gpiod_set_value_cansleep(p->enable_gpio, 0); 309 regulator_disable(p->supply); 310 p->unprepared_time = ktime_get_boottime(); 311 312 kfree(p->edid); 313 p->edid = NULL; 314 315 return 0; 316 } 317 318 static int panel_simple_unprepare(struct drm_panel *panel) 319 { 320 struct panel_simple *p = to_panel_simple(panel); 321 int ret; 322 323 /* Unpreparing when already unprepared is a no-op */ 324 if (!p->prepared) 325 return 0; 326 327 pm_runtime_mark_last_busy(panel->dev); 328 ret = pm_runtime_put_autosuspend(panel->dev); 329 if (ret < 0) 330 return ret; 331 p->prepared = false; 332 333 return 0; 334 } 335 336 static int panel_simple_resume(struct device *dev) 337 { 338 struct panel_simple *p = dev_get_drvdata(dev); 339 int err; 340 341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 342 343 err = regulator_enable(p->supply); 344 if (err < 0) { 345 dev_err(dev, "failed to enable supply: %d\n", err); 346 return err; 347 } 348 349 gpiod_set_value_cansleep(p->enable_gpio, 1); 350 351 if (p->desc->delay.prepare) 352 msleep(p->desc->delay.prepare); 353 354 return 0; 355 } 356 357 static int panel_simple_prepare(struct drm_panel *panel) 358 { 359 struct panel_simple *p = to_panel_simple(panel); 360 int ret; 361 362 /* Preparing when already prepared is a no-op */ 363 if (p->prepared) 364 return 0; 365 366 ret = pm_runtime_get_sync(panel->dev); 367 if (ret < 0) { 368 pm_runtime_put_autosuspend(panel->dev); 369 return ret; 370 } 371 372 p->prepared = true; 373 374 return 0; 375 } 376 377 static int panel_simple_enable(struct drm_panel *panel) 378 { 379 struct panel_simple *p = to_panel_simple(panel); 380 381 if (p->enabled) 382 return 0; 383 384 if (p->desc->delay.enable) 385 msleep(p->desc->delay.enable); 386 387 p->enabled = true; 388 389 return 0; 390 } 391 392 static int panel_simple_get_modes(struct drm_panel *panel, 393 struct drm_connector *connector) 394 { 395 struct panel_simple *p = to_panel_simple(panel); 396 int num = 0; 397 398 /* probe EDID if a DDC bus is available */ 399 if (p->ddc) { 400 pm_runtime_get_sync(panel->dev); 401 402 if (!p->edid) 403 p->edid = drm_get_edid(connector, p->ddc); 404 405 if (p->edid) 406 num += drm_add_edid_modes(connector, p->edid); 407 408 pm_runtime_mark_last_busy(panel->dev); 409 pm_runtime_put_autosuspend(panel->dev); 410 } 411 412 /* add hard-coded panel modes */ 413 num += panel_simple_get_non_edid_modes(p, connector); 414 415 /* 416 * TODO: Remove once all drm drivers call 417 * drm_connector_set_orientation_from_panel() 418 */ 419 drm_connector_set_panel_orientation(connector, p->orientation); 420 421 return num; 422 } 423 424 static int panel_simple_get_timings(struct drm_panel *panel, 425 unsigned int num_timings, 426 struct display_timing *timings) 427 { 428 struct panel_simple *p = to_panel_simple(panel); 429 unsigned int i; 430 431 if (p->desc->num_timings < num_timings) 432 num_timings = p->desc->num_timings; 433 434 if (timings) 435 for (i = 0; i < num_timings; i++) 436 timings[i] = p->desc->timings[i]; 437 438 return p->desc->num_timings; 439 } 440 441 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 442 { 443 struct panel_simple *p = to_panel_simple(panel); 444 445 return p->orientation; 446 } 447 448 static const struct drm_panel_funcs panel_simple_funcs = { 449 .disable = panel_simple_disable, 450 .unprepare = panel_simple_unprepare, 451 .prepare = panel_simple_prepare, 452 .enable = panel_simple_enable, 453 .get_modes = panel_simple_get_modes, 454 .get_orientation = panel_simple_get_orientation, 455 .get_timings = panel_simple_get_timings, 456 }; 457 458 static struct panel_desc panel_dpi; 459 460 static int panel_dpi_probe(struct device *dev, 461 struct panel_simple *panel) 462 { 463 struct display_timing *timing; 464 const struct device_node *np; 465 struct panel_desc *desc; 466 unsigned int bus_flags; 467 struct videomode vm; 468 int ret; 469 470 np = dev->of_node; 471 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 472 if (!desc) 473 return -ENOMEM; 474 475 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 476 if (!timing) 477 return -ENOMEM; 478 479 ret = of_get_display_timing(np, "panel-timing", timing); 480 if (ret < 0) { 481 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 482 np); 483 return ret; 484 } 485 486 desc->timings = timing; 487 desc->num_timings = 1; 488 489 of_property_read_u32(np, "width-mm", &desc->size.width); 490 of_property_read_u32(np, "height-mm", &desc->size.height); 491 492 /* Extract bus_flags from display_timing */ 493 bus_flags = 0; 494 vm.flags = timing->flags; 495 drm_bus_flags_from_videomode(&vm, &bus_flags); 496 desc->bus_flags = bus_flags; 497 498 /* We do not know the connector for the DT node, so guess it */ 499 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 500 501 panel->desc = desc; 502 503 return 0; 504 } 505 506 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 507 (to_check->field.typ >= bounds->field.min && \ 508 to_check->field.typ <= bounds->field.max) 509 static void panel_simple_parse_panel_timing_node(struct device *dev, 510 struct panel_simple *panel, 511 const struct display_timing *ot) 512 { 513 const struct panel_desc *desc = panel->desc; 514 struct videomode vm; 515 unsigned int i; 516 517 if (WARN_ON(desc->num_modes)) { 518 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 519 return; 520 } 521 if (WARN_ON(!desc->num_timings)) { 522 dev_err(dev, "Reject override mode: no timings specified\n"); 523 return; 524 } 525 526 for (i = 0; i < panel->desc->num_timings; i++) { 527 const struct display_timing *dt = &panel->desc->timings[i]; 528 529 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 537 continue; 538 539 if (ot->flags != dt->flags) 540 continue; 541 542 videomode_from_timing(ot, &vm); 543 drm_display_mode_from_videomode(&vm, &panel->override_mode); 544 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 545 DRM_MODE_TYPE_PREFERRED; 546 break; 547 } 548 549 if (WARN_ON(!panel->override_mode.type)) 550 dev_err(dev, "Reject override mode: No display_timing found\n"); 551 } 552 553 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 554 struct panel_simple *panel) 555 { 556 int ret, bpc; 557 558 ret = drm_of_lvds_get_data_mapping(dev->of_node); 559 if (ret < 0) { 560 if (ret == -EINVAL) 561 dev_warn(dev, "Ignore invalid data-mapping property\n"); 562 563 /* 564 * Ignore non-existing or malformatted property, fallback to 565 * default data-mapping, and return 0. 566 */ 567 return 0; 568 } 569 570 switch (ret) { 571 default: 572 WARN_ON(1); 573 fallthrough; 574 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 575 fallthrough; 576 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 577 bpc = 8; 578 break; 579 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 580 bpc = 6; 581 } 582 583 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 584 struct panel_desc *override_desc; 585 586 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 587 if (!override_desc) 588 return -ENOMEM; 589 590 override_desc->bus_format = ret; 591 override_desc->bpc = bpc; 592 panel->desc = override_desc; 593 } 594 595 return 0; 596 } 597 598 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 599 { 600 struct panel_simple *panel; 601 struct display_timing dt; 602 struct device_node *ddc; 603 int connector_type; 604 u32 bus_flags; 605 int err; 606 607 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 608 if (!panel) 609 return -ENOMEM; 610 611 panel->enabled = false; 612 panel->desc = desc; 613 614 panel->supply = devm_regulator_get(dev, "power"); 615 if (IS_ERR(panel->supply)) 616 return PTR_ERR(panel->supply); 617 618 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 619 GPIOD_OUT_LOW); 620 if (IS_ERR(panel->enable_gpio)) 621 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 622 "failed to request GPIO\n"); 623 624 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 625 if (err) { 626 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 627 return err; 628 } 629 630 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 631 if (ddc) { 632 panel->ddc = of_find_i2c_adapter_by_node(ddc); 633 of_node_put(ddc); 634 635 if (!panel->ddc) 636 return -EPROBE_DEFER; 637 } 638 639 if (desc == &panel_dpi) { 640 /* Handle the generic panel-dpi binding */ 641 err = panel_dpi_probe(dev, panel); 642 if (err) 643 goto free_ddc; 644 desc = panel->desc; 645 } else { 646 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 647 panel_simple_parse_panel_timing_node(dev, panel, &dt); 648 } 649 650 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 651 /* Optional data-mapping property for overriding bus format */ 652 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 653 if (err) 654 goto free_ddc; 655 } 656 657 connector_type = desc->connector_type; 658 /* Catch common mistakes for panels. */ 659 switch (connector_type) { 660 case 0: 661 dev_warn(dev, "Specify missing connector_type\n"); 662 connector_type = DRM_MODE_CONNECTOR_DPI; 663 break; 664 case DRM_MODE_CONNECTOR_LVDS: 665 WARN_ON(desc->bus_flags & 666 ~(DRM_BUS_FLAG_DE_LOW | 667 DRM_BUS_FLAG_DE_HIGH | 668 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 669 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 670 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 671 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 672 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 673 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 674 desc->bpc != 6); 675 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 676 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 677 desc->bpc != 8); 678 break; 679 case DRM_MODE_CONNECTOR_eDP: 680 dev_warn(dev, "eDP panels moved to panel-edp\n"); 681 err = -EINVAL; 682 goto free_ddc; 683 case DRM_MODE_CONNECTOR_DSI: 684 if (desc->bpc != 6 && desc->bpc != 8) 685 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 686 break; 687 case DRM_MODE_CONNECTOR_DPI: 688 bus_flags = DRM_BUS_FLAG_DE_LOW | 689 DRM_BUS_FLAG_DE_HIGH | 690 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 691 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 692 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 693 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 694 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 695 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 696 if (desc->bus_flags & ~bus_flags) 697 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 698 if (!(desc->bus_flags & bus_flags)) 699 dev_warn(dev, "Specify missing bus_flags\n"); 700 if (desc->bus_format == 0) 701 dev_warn(dev, "Specify missing bus_format\n"); 702 if (desc->bpc != 6 && desc->bpc != 8) 703 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 704 break; 705 default: 706 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 707 connector_type = DRM_MODE_CONNECTOR_DPI; 708 break; 709 } 710 711 dev_set_drvdata(dev, panel); 712 713 /* 714 * We use runtime PM for prepare / unprepare since those power the panel 715 * on and off and those can be very slow operations. This is important 716 * to optimize powering the panel on briefly to read the EDID before 717 * fully enabling the panel. 718 */ 719 pm_runtime_enable(dev); 720 pm_runtime_set_autosuspend_delay(dev, 1000); 721 pm_runtime_use_autosuspend(dev); 722 723 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 724 725 err = drm_panel_of_backlight(&panel->base); 726 if (err) { 727 dev_err_probe(dev, err, "Could not find backlight\n"); 728 goto disable_pm_runtime; 729 } 730 731 drm_panel_add(&panel->base); 732 733 return 0; 734 735 disable_pm_runtime: 736 pm_runtime_dont_use_autosuspend(dev); 737 pm_runtime_disable(dev); 738 free_ddc: 739 if (panel->ddc) 740 put_device(&panel->ddc->dev); 741 742 return err; 743 } 744 745 static void panel_simple_remove(struct device *dev) 746 { 747 struct panel_simple *panel = dev_get_drvdata(dev); 748 749 drm_panel_remove(&panel->base); 750 drm_panel_disable(&panel->base); 751 drm_panel_unprepare(&panel->base); 752 753 pm_runtime_dont_use_autosuspend(dev); 754 pm_runtime_disable(dev); 755 if (panel->ddc) 756 put_device(&panel->ddc->dev); 757 } 758 759 static void panel_simple_shutdown(struct device *dev) 760 { 761 struct panel_simple *panel = dev_get_drvdata(dev); 762 763 drm_panel_disable(&panel->base); 764 drm_panel_unprepare(&panel->base); 765 } 766 767 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 768 .clock = 71100, 769 .hdisplay = 1280, 770 .hsync_start = 1280 + 40, 771 .hsync_end = 1280 + 40 + 80, 772 .htotal = 1280 + 40 + 80 + 40, 773 .vdisplay = 800, 774 .vsync_start = 800 + 3, 775 .vsync_end = 800 + 3 + 10, 776 .vtotal = 800 + 3 + 10 + 10, 777 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 778 }; 779 780 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 781 .modes = &ire_am_1280800n3tzqw_t00h_mode, 782 .num_modes = 1, 783 .bpc = 8, 784 .size = { 785 .width = 217, 786 .height = 136, 787 }, 788 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 789 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 790 .connector_type = DRM_MODE_CONNECTOR_LVDS, 791 }; 792 793 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 794 .clock = 9000, 795 .hdisplay = 480, 796 .hsync_start = 480 + 2, 797 .hsync_end = 480 + 2 + 41, 798 .htotal = 480 + 2 + 41 + 2, 799 .vdisplay = 272, 800 .vsync_start = 272 + 2, 801 .vsync_end = 272 + 2 + 10, 802 .vtotal = 272 + 2 + 10 + 2, 803 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 804 }; 805 806 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 807 .modes = &ire_am_480272h3tmqw_t01h_mode, 808 .num_modes = 1, 809 .bpc = 8, 810 .size = { 811 .width = 99, 812 .height = 58, 813 }, 814 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 815 }; 816 817 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 818 .clock = 33333, 819 .hdisplay = 800, 820 .hsync_start = 800 + 0, 821 .hsync_end = 800 + 0 + 255, 822 .htotal = 800 + 0 + 255 + 0, 823 .vdisplay = 480, 824 .vsync_start = 480 + 2, 825 .vsync_end = 480 + 2 + 45, 826 .vtotal = 480 + 2 + 45 + 0, 827 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 828 }; 829 830 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 831 .pixelclock = { 29930000, 33260000, 36590000 }, 832 .hactive = { 800, 800, 800 }, 833 .hfront_porch = { 1, 40, 168 }, 834 .hback_porch = { 88, 88, 88 }, 835 .hsync_len = { 1, 128, 128 }, 836 .vactive = { 480, 480, 480 }, 837 .vfront_porch = { 1, 35, 37 }, 838 .vback_porch = { 8, 8, 8 }, 839 .vsync_len = { 1, 2, 2 }, 840 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 841 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 842 DISPLAY_FLAGS_SYNC_POSEDGE, 843 }; 844 845 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 846 .timings = &ire_am_800480l1tmqw_t00h_timing, 847 .num_timings = 1, 848 .bpc = 8, 849 .size = { 850 .width = 111, 851 .height = 67, 852 }, 853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 854 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 855 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 856 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 857 .connector_type = DRM_MODE_CONNECTOR_DPI, 858 }; 859 860 static const struct panel_desc ampire_am800480r3tmqwa1h = { 861 .modes = &ire_am800480r3tmqwa1h_mode, 862 .num_modes = 1, 863 .bpc = 6, 864 .size = { 865 .width = 152, 866 .height = 91, 867 }, 868 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 869 }; 870 871 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 872 .pixelclock = { 34500000, 39600000, 50400000 }, 873 .hactive = { 800, 800, 800 }, 874 .hfront_porch = { 12, 112, 312 }, 875 .hback_porch = { 87, 87, 48 }, 876 .hsync_len = { 1, 1, 40 }, 877 .vactive = { 600, 600, 600 }, 878 .vfront_porch = { 1, 21, 61 }, 879 .vback_porch = { 38, 38, 19 }, 880 .vsync_len = { 1, 1, 20 }, 881 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 882 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 883 DISPLAY_FLAGS_SYNC_POSEDGE, 884 }; 885 886 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 887 .timings = &ire_am800600p5tmqw_tb8h_timing, 888 .num_timings = 1, 889 .bpc = 6, 890 .size = { 891 .width = 162, 892 .height = 122, 893 }, 894 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 895 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 896 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 897 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 898 .connector_type = DRM_MODE_CONNECTOR_DPI, 899 }; 900 901 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 902 .pixelclock = { 26400000, 33300000, 46800000 }, 903 .hactive = { 800, 800, 800 }, 904 .hfront_porch = { 16, 210, 354 }, 905 .hback_porch = { 45, 36, 6 }, 906 .hsync_len = { 1, 10, 40 }, 907 .vactive = { 480, 480, 480 }, 908 .vfront_porch = { 7, 22, 147 }, 909 .vback_porch = { 22, 13, 3 }, 910 .vsync_len = { 1, 10, 20 }, 911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 913 }; 914 915 static const struct panel_desc armadeus_st0700_adapt = { 916 .timings = &santek_st0700i5y_rbslw_f_timing, 917 .num_timings = 1, 918 .bpc = 6, 919 .size = { 920 .width = 154, 921 .height = 86, 922 }, 923 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 924 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 925 }; 926 927 static const struct drm_display_mode auo_b101aw03_mode = { 928 .clock = 51450, 929 .hdisplay = 1024, 930 .hsync_start = 1024 + 156, 931 .hsync_end = 1024 + 156 + 8, 932 .htotal = 1024 + 156 + 8 + 156, 933 .vdisplay = 600, 934 .vsync_start = 600 + 16, 935 .vsync_end = 600 + 16 + 6, 936 .vtotal = 600 + 16 + 6 + 16, 937 }; 938 939 static const struct panel_desc auo_b101aw03 = { 940 .modes = &auo_b101aw03_mode, 941 .num_modes = 1, 942 .bpc = 6, 943 .size = { 944 .width = 223, 945 .height = 125, 946 }, 947 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 948 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 949 .connector_type = DRM_MODE_CONNECTOR_LVDS, 950 }; 951 952 static const struct drm_display_mode auo_b101xtn01_mode = { 953 .clock = 72000, 954 .hdisplay = 1366, 955 .hsync_start = 1366 + 20, 956 .hsync_end = 1366 + 20 + 70, 957 .htotal = 1366 + 20 + 70, 958 .vdisplay = 768, 959 .vsync_start = 768 + 14, 960 .vsync_end = 768 + 14 + 42, 961 .vtotal = 768 + 14 + 42, 962 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 963 }; 964 965 static const struct panel_desc auo_b101xtn01 = { 966 .modes = &auo_b101xtn01_mode, 967 .num_modes = 1, 968 .bpc = 6, 969 .size = { 970 .width = 223, 971 .height = 125, 972 }, 973 }; 974 975 static const struct drm_display_mode auo_b116xw03_mode = { 976 .clock = 70589, 977 .hdisplay = 1366, 978 .hsync_start = 1366 + 40, 979 .hsync_end = 1366 + 40 + 40, 980 .htotal = 1366 + 40 + 40 + 32, 981 .vdisplay = 768, 982 .vsync_start = 768 + 10, 983 .vsync_end = 768 + 10 + 12, 984 .vtotal = 768 + 10 + 12 + 6, 985 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 986 }; 987 988 static const struct panel_desc auo_b116xw03 = { 989 .modes = &auo_b116xw03_mode, 990 .num_modes = 1, 991 .bpc = 6, 992 .size = { 993 .width = 256, 994 .height = 144, 995 }, 996 .delay = { 997 .prepare = 1, 998 .enable = 200, 999 .disable = 200, 1000 .unprepare = 500, 1001 }, 1002 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1003 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1004 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1005 }; 1006 1007 static const struct display_timing auo_g070vvn01_timings = { 1008 .pixelclock = { 33300000, 34209000, 45000000 }, 1009 .hactive = { 800, 800, 800 }, 1010 .hfront_porch = { 20, 40, 200 }, 1011 .hback_porch = { 87, 40, 1 }, 1012 .hsync_len = { 1, 48, 87 }, 1013 .vactive = { 480, 480, 480 }, 1014 .vfront_porch = { 5, 13, 200 }, 1015 .vback_porch = { 31, 31, 29 }, 1016 .vsync_len = { 1, 1, 3 }, 1017 }; 1018 1019 static const struct panel_desc auo_g070vvn01 = { 1020 .timings = &auo_g070vvn01_timings, 1021 .num_timings = 1, 1022 .bpc = 8, 1023 .size = { 1024 .width = 152, 1025 .height = 91, 1026 }, 1027 .delay = { 1028 .prepare = 200, 1029 .enable = 50, 1030 .disable = 50, 1031 .unprepare = 1000, 1032 }, 1033 }; 1034 1035 static const struct drm_display_mode auo_g101evn010_mode = { 1036 .clock = 68930, 1037 .hdisplay = 1280, 1038 .hsync_start = 1280 + 82, 1039 .hsync_end = 1280 + 82 + 2, 1040 .htotal = 1280 + 82 + 2 + 84, 1041 .vdisplay = 800, 1042 .vsync_start = 800 + 8, 1043 .vsync_end = 800 + 8 + 2, 1044 .vtotal = 800 + 8 + 2 + 6, 1045 }; 1046 1047 static const struct panel_desc auo_g101evn010 = { 1048 .modes = &auo_g101evn010_mode, 1049 .num_modes = 1, 1050 .bpc = 6, 1051 .size = { 1052 .width = 216, 1053 .height = 135, 1054 }, 1055 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1056 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1057 }; 1058 1059 static const struct drm_display_mode auo_g104sn02_mode = { 1060 .clock = 40000, 1061 .hdisplay = 800, 1062 .hsync_start = 800 + 40, 1063 .hsync_end = 800 + 40 + 216, 1064 .htotal = 800 + 40 + 216 + 128, 1065 .vdisplay = 600, 1066 .vsync_start = 600 + 10, 1067 .vsync_end = 600 + 10 + 35, 1068 .vtotal = 600 + 10 + 35 + 2, 1069 }; 1070 1071 static const struct panel_desc auo_g104sn02 = { 1072 .modes = &auo_g104sn02_mode, 1073 .num_modes = 1, 1074 .bpc = 8, 1075 .size = { 1076 .width = 211, 1077 .height = 158, 1078 }, 1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1080 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1081 }; 1082 1083 static const struct display_timing auo_g121ean01_timing = { 1084 .pixelclock = { 60000000, 74400000, 90000000 }, 1085 .hactive = { 1280, 1280, 1280 }, 1086 .hfront_porch = { 20, 50, 100 }, 1087 .hback_porch = { 20, 50, 100 }, 1088 .hsync_len = { 30, 100, 200 }, 1089 .vactive = { 800, 800, 800 }, 1090 .vfront_porch = { 2, 10, 25 }, 1091 .vback_porch = { 2, 10, 25 }, 1092 .vsync_len = { 4, 18, 50 }, 1093 }; 1094 1095 static const struct panel_desc auo_g121ean01 = { 1096 .timings = &auo_g121ean01_timing, 1097 .num_timings = 1, 1098 .bpc = 8, 1099 .size = { 1100 .width = 261, 1101 .height = 163, 1102 }, 1103 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1104 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1105 }; 1106 1107 static const struct display_timing auo_g133han01_timings = { 1108 .pixelclock = { 134000000, 141200000, 149000000 }, 1109 .hactive = { 1920, 1920, 1920 }, 1110 .hfront_porch = { 39, 58, 77 }, 1111 .hback_porch = { 59, 88, 117 }, 1112 .hsync_len = { 28, 42, 56 }, 1113 .vactive = { 1080, 1080, 1080 }, 1114 .vfront_porch = { 3, 8, 11 }, 1115 .vback_porch = { 5, 14, 19 }, 1116 .vsync_len = { 4, 14, 19 }, 1117 }; 1118 1119 static const struct panel_desc auo_g133han01 = { 1120 .timings = &auo_g133han01_timings, 1121 .num_timings = 1, 1122 .bpc = 8, 1123 .size = { 1124 .width = 293, 1125 .height = 165, 1126 }, 1127 .delay = { 1128 .prepare = 200, 1129 .enable = 50, 1130 .disable = 50, 1131 .unprepare = 1000, 1132 }, 1133 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1134 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1135 }; 1136 1137 static const struct display_timing auo_g156han04_timings = { 1138 .pixelclock = { 137000000, 141000000, 146000000 }, 1139 .hactive = { 1920, 1920, 1920 }, 1140 .hfront_porch = { 60, 60, 60 }, 1141 .hback_porch = { 90, 92, 111 }, 1142 .hsync_len = { 32, 32, 32 }, 1143 .vactive = { 1080, 1080, 1080 }, 1144 .vfront_porch = { 12, 12, 12 }, 1145 .vback_porch = { 24, 36, 56 }, 1146 .vsync_len = { 8, 8, 8 }, 1147 }; 1148 1149 static const struct panel_desc auo_g156han04 = { 1150 .timings = &auo_g156han04_timings, 1151 .num_timings = 1, 1152 .bpc = 8, 1153 .size = { 1154 .width = 344, 1155 .height = 194, 1156 }, 1157 .delay = { 1158 .prepare = 50, /* T2 */ 1159 .enable = 200, /* T3 */ 1160 .disable = 110, /* T10 */ 1161 .unprepare = 1000, /* T13 */ 1162 }, 1163 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1164 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1165 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1166 }; 1167 1168 static const struct drm_display_mode auo_g156xtn01_mode = { 1169 .clock = 76000, 1170 .hdisplay = 1366, 1171 .hsync_start = 1366 + 33, 1172 .hsync_end = 1366 + 33 + 67, 1173 .htotal = 1560, 1174 .vdisplay = 768, 1175 .vsync_start = 768 + 4, 1176 .vsync_end = 768 + 4 + 4, 1177 .vtotal = 806, 1178 }; 1179 1180 static const struct panel_desc auo_g156xtn01 = { 1181 .modes = &auo_g156xtn01_mode, 1182 .num_modes = 1, 1183 .bpc = 8, 1184 .size = { 1185 .width = 344, 1186 .height = 194, 1187 }, 1188 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1189 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1190 }; 1191 1192 static const struct display_timing auo_g185han01_timings = { 1193 .pixelclock = { 120000000, 144000000, 175000000 }, 1194 .hactive = { 1920, 1920, 1920 }, 1195 .hfront_porch = { 36, 120, 148 }, 1196 .hback_porch = { 24, 88, 108 }, 1197 .hsync_len = { 20, 48, 64 }, 1198 .vactive = { 1080, 1080, 1080 }, 1199 .vfront_porch = { 6, 10, 40 }, 1200 .vback_porch = { 2, 5, 20 }, 1201 .vsync_len = { 2, 5, 20 }, 1202 }; 1203 1204 static const struct panel_desc auo_g185han01 = { 1205 .timings = &auo_g185han01_timings, 1206 .num_timings = 1, 1207 .bpc = 8, 1208 .size = { 1209 .width = 409, 1210 .height = 230, 1211 }, 1212 .delay = { 1213 .prepare = 50, 1214 .enable = 200, 1215 .disable = 110, 1216 .unprepare = 1000, 1217 }, 1218 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1219 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1220 }; 1221 1222 static const struct display_timing auo_g190ean01_timings = { 1223 .pixelclock = { 90000000, 108000000, 135000000 }, 1224 .hactive = { 1280, 1280, 1280 }, 1225 .hfront_porch = { 126, 184, 1266 }, 1226 .hback_porch = { 84, 122, 844 }, 1227 .hsync_len = { 70, 102, 704 }, 1228 .vactive = { 1024, 1024, 1024 }, 1229 .vfront_porch = { 4, 26, 76 }, 1230 .vback_porch = { 2, 8, 25 }, 1231 .vsync_len = { 2, 8, 25 }, 1232 }; 1233 1234 static const struct panel_desc auo_g190ean01 = { 1235 .timings = &auo_g190ean01_timings, 1236 .num_timings = 1, 1237 .bpc = 8, 1238 .size = { 1239 .width = 376, 1240 .height = 301, 1241 }, 1242 .delay = { 1243 .prepare = 50, 1244 .enable = 200, 1245 .disable = 110, 1246 .unprepare = 1000, 1247 }, 1248 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1249 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1250 }; 1251 1252 static const struct display_timing auo_p320hvn03_timings = { 1253 .pixelclock = { 106000000, 148500000, 164000000 }, 1254 .hactive = { 1920, 1920, 1920 }, 1255 .hfront_porch = { 25, 50, 130 }, 1256 .hback_porch = { 25, 50, 130 }, 1257 .hsync_len = { 20, 40, 105 }, 1258 .vactive = { 1080, 1080, 1080 }, 1259 .vfront_porch = { 8, 17, 150 }, 1260 .vback_porch = { 8, 17, 150 }, 1261 .vsync_len = { 4, 11, 100 }, 1262 }; 1263 1264 static const struct panel_desc auo_p320hvn03 = { 1265 .timings = &auo_p320hvn03_timings, 1266 .num_timings = 1, 1267 .bpc = 8, 1268 .size = { 1269 .width = 698, 1270 .height = 393, 1271 }, 1272 .delay = { 1273 .prepare = 1, 1274 .enable = 450, 1275 .unprepare = 500, 1276 }, 1277 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1278 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1279 }; 1280 1281 static const struct drm_display_mode auo_t215hvn01_mode = { 1282 .clock = 148800, 1283 .hdisplay = 1920, 1284 .hsync_start = 1920 + 88, 1285 .hsync_end = 1920 + 88 + 44, 1286 .htotal = 1920 + 88 + 44 + 148, 1287 .vdisplay = 1080, 1288 .vsync_start = 1080 + 4, 1289 .vsync_end = 1080 + 4 + 5, 1290 .vtotal = 1080 + 4 + 5 + 36, 1291 }; 1292 1293 static const struct panel_desc auo_t215hvn01 = { 1294 .modes = &auo_t215hvn01_mode, 1295 .num_modes = 1, 1296 .bpc = 8, 1297 .size = { 1298 .width = 430, 1299 .height = 270, 1300 }, 1301 .delay = { 1302 .disable = 5, 1303 .unprepare = 1000, 1304 }, 1305 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1306 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1307 }; 1308 1309 static const struct drm_display_mode avic_tm070ddh03_mode = { 1310 .clock = 51200, 1311 .hdisplay = 1024, 1312 .hsync_start = 1024 + 160, 1313 .hsync_end = 1024 + 160 + 4, 1314 .htotal = 1024 + 160 + 4 + 156, 1315 .vdisplay = 600, 1316 .vsync_start = 600 + 17, 1317 .vsync_end = 600 + 17 + 1, 1318 .vtotal = 600 + 17 + 1 + 17, 1319 }; 1320 1321 static const struct panel_desc avic_tm070ddh03 = { 1322 .modes = &avic_tm070ddh03_mode, 1323 .num_modes = 1, 1324 .bpc = 8, 1325 .size = { 1326 .width = 154, 1327 .height = 90, 1328 }, 1329 .delay = { 1330 .prepare = 20, 1331 .enable = 200, 1332 .disable = 200, 1333 }, 1334 }; 1335 1336 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1337 .clock = 30000, 1338 .hdisplay = 800, 1339 .hsync_start = 800 + 40, 1340 .hsync_end = 800 + 40 + 48, 1341 .htotal = 800 + 40 + 48 + 40, 1342 .vdisplay = 480, 1343 .vsync_start = 480 + 13, 1344 .vsync_end = 480 + 13 + 3, 1345 .vtotal = 480 + 13 + 3 + 29, 1346 }; 1347 1348 static const struct panel_desc bananapi_s070wv20_ct16 = { 1349 .modes = &bananapi_s070wv20_ct16_mode, 1350 .num_modes = 1, 1351 .bpc = 6, 1352 .size = { 1353 .width = 154, 1354 .height = 86, 1355 }, 1356 }; 1357 1358 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1359 .clock = 78945, 1360 .hdisplay = 1280, 1361 .hsync_start = 1280 + 0, 1362 .hsync_end = 1280 + 0 + 2, 1363 .htotal = 1280 + 62 + 0 + 2, 1364 .vdisplay = 800, 1365 .vsync_start = 800 + 8, 1366 .vsync_end = 800 + 8 + 2, 1367 .vtotal = 800 + 6 + 8 + 2, 1368 }; 1369 1370 static const struct panel_desc boe_bp082wx1_100 = { 1371 .modes = &boe_bp101wx1_100_mode, 1372 .num_modes = 1, 1373 .bpc = 8, 1374 .size = { 1375 .width = 177, 1376 .height = 110, 1377 }, 1378 .delay = { 1379 .enable = 50, 1380 .disable = 50, 1381 }, 1382 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1383 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1384 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1385 }; 1386 1387 static const struct panel_desc boe_bp101wx1_100 = { 1388 .modes = &boe_bp101wx1_100_mode, 1389 .num_modes = 1, 1390 .bpc = 8, 1391 .size = { 1392 .width = 217, 1393 .height = 136, 1394 }, 1395 .delay = { 1396 .enable = 50, 1397 .disable = 50, 1398 }, 1399 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1400 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1401 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1402 }; 1403 1404 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1405 .pixelclock = { 69922000, 71000000, 72293000 }, 1406 .hactive = { 1280, 1280, 1280 }, 1407 .hfront_porch = { 48, 48, 48 }, 1408 .hback_porch = { 80, 80, 80 }, 1409 .hsync_len = { 32, 32, 32 }, 1410 .vactive = { 800, 800, 800 }, 1411 .vfront_porch = { 3, 3, 3 }, 1412 .vback_porch = { 14, 14, 14 }, 1413 .vsync_len = { 6, 6, 6 }, 1414 }; 1415 1416 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1417 .timings = &boe_ev121wxm_n10_1850_timing, 1418 .num_timings = 1, 1419 .bpc = 8, 1420 .size = { 1421 .width = 261, 1422 .height = 163, 1423 }, 1424 .delay = { 1425 .prepare = 9, 1426 .enable = 300, 1427 .unprepare = 300, 1428 .disable = 560, 1429 }, 1430 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1431 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1432 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1433 }; 1434 1435 static const struct drm_display_mode boe_hv070wsa_mode = { 1436 .clock = 42105, 1437 .hdisplay = 1024, 1438 .hsync_start = 1024 + 30, 1439 .hsync_end = 1024 + 30 + 30, 1440 .htotal = 1024 + 30 + 30 + 30, 1441 .vdisplay = 600, 1442 .vsync_start = 600 + 10, 1443 .vsync_end = 600 + 10 + 10, 1444 .vtotal = 600 + 10 + 10 + 10, 1445 }; 1446 1447 static const struct panel_desc boe_hv070wsa = { 1448 .modes = &boe_hv070wsa_mode, 1449 .num_modes = 1, 1450 .bpc = 8, 1451 .size = { 1452 .width = 154, 1453 .height = 90, 1454 }, 1455 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1456 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1457 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1458 }; 1459 1460 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1461 .clock = 9000, 1462 .hdisplay = 480, 1463 .hsync_start = 480 + 5, 1464 .hsync_end = 480 + 5 + 5, 1465 .htotal = 480 + 5 + 5 + 40, 1466 .vdisplay = 272, 1467 .vsync_start = 272 + 8, 1468 .vsync_end = 272 + 8 + 8, 1469 .vtotal = 272 + 8 + 8 + 8, 1470 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1471 }; 1472 1473 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1474 .modes = &cdtech_s043wq26h_ct7_mode, 1475 .num_modes = 1, 1476 .bpc = 8, 1477 .size = { 1478 .width = 95, 1479 .height = 54, 1480 }, 1481 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1482 }; 1483 1484 /* S070PWS19HP-FC21 2017/04/22 */ 1485 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1486 .clock = 51200, 1487 .hdisplay = 1024, 1488 .hsync_start = 1024 + 160, 1489 .hsync_end = 1024 + 160 + 20, 1490 .htotal = 1024 + 160 + 20 + 140, 1491 .vdisplay = 600, 1492 .vsync_start = 600 + 12, 1493 .vsync_end = 600 + 12 + 3, 1494 .vtotal = 600 + 12 + 3 + 20, 1495 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1496 }; 1497 1498 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1499 .modes = &cdtech_s070pws19hp_fc21_mode, 1500 .num_modes = 1, 1501 .bpc = 6, 1502 .size = { 1503 .width = 154, 1504 .height = 86, 1505 }, 1506 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1507 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1508 .connector_type = DRM_MODE_CONNECTOR_DPI, 1509 }; 1510 1511 /* S070SWV29HG-DC44 2017/09/21 */ 1512 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1513 .clock = 33300, 1514 .hdisplay = 800, 1515 .hsync_start = 800 + 210, 1516 .hsync_end = 800 + 210 + 2, 1517 .htotal = 800 + 210 + 2 + 44, 1518 .vdisplay = 480, 1519 .vsync_start = 480 + 22, 1520 .vsync_end = 480 + 22 + 2, 1521 .vtotal = 480 + 22 + 2 + 21, 1522 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1523 }; 1524 1525 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1526 .modes = &cdtech_s070swv29hg_dc44_mode, 1527 .num_modes = 1, 1528 .bpc = 6, 1529 .size = { 1530 .width = 154, 1531 .height = 86, 1532 }, 1533 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1534 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1535 .connector_type = DRM_MODE_CONNECTOR_DPI, 1536 }; 1537 1538 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1539 .clock = 35000, 1540 .hdisplay = 800, 1541 .hsync_start = 800 + 40, 1542 .hsync_end = 800 + 40 + 40, 1543 .htotal = 800 + 40 + 40 + 48, 1544 .vdisplay = 480, 1545 .vsync_start = 480 + 29, 1546 .vsync_end = 480 + 29 + 13, 1547 .vtotal = 480 + 29 + 13 + 3, 1548 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1549 }; 1550 1551 static const struct panel_desc cdtech_s070wv95_ct16 = { 1552 .modes = &cdtech_s070wv95_ct16_mode, 1553 .num_modes = 1, 1554 .bpc = 8, 1555 .size = { 1556 .width = 154, 1557 .height = 85, 1558 }, 1559 }; 1560 1561 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1562 .pixelclock = { 68900000, 71100000, 73400000 }, 1563 .hactive = { 1280, 1280, 1280 }, 1564 .hfront_porch = { 65, 80, 95 }, 1565 .hback_porch = { 64, 79, 94 }, 1566 .hsync_len = { 1, 1, 1 }, 1567 .vactive = { 800, 800, 800 }, 1568 .vfront_porch = { 7, 11, 14 }, 1569 .vback_porch = { 7, 11, 14 }, 1570 .vsync_len = { 1, 1, 1 }, 1571 .flags = DISPLAY_FLAGS_DE_HIGH, 1572 }; 1573 1574 static const struct panel_desc chefree_ch101olhlwh_002 = { 1575 .timings = &chefree_ch101olhlwh_002_timing, 1576 .num_timings = 1, 1577 .bpc = 8, 1578 .size = { 1579 .width = 217, 1580 .height = 135, 1581 }, 1582 .delay = { 1583 .enable = 200, 1584 .disable = 200, 1585 }, 1586 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1587 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1588 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1589 }; 1590 1591 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1592 .clock = 66770, 1593 .hdisplay = 800, 1594 .hsync_start = 800 + 49, 1595 .hsync_end = 800 + 49 + 33, 1596 .htotal = 800 + 49 + 33 + 17, 1597 .vdisplay = 1280, 1598 .vsync_start = 1280 + 1, 1599 .vsync_end = 1280 + 1 + 7, 1600 .vtotal = 1280 + 1 + 7 + 15, 1601 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1602 }; 1603 1604 static const struct panel_desc chunghwa_claa070wp03xg = { 1605 .modes = &chunghwa_claa070wp03xg_mode, 1606 .num_modes = 1, 1607 .bpc = 6, 1608 .size = { 1609 .width = 94, 1610 .height = 150, 1611 }, 1612 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1613 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1614 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1615 }; 1616 1617 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1618 .clock = 72070, 1619 .hdisplay = 1366, 1620 .hsync_start = 1366 + 58, 1621 .hsync_end = 1366 + 58 + 58, 1622 .htotal = 1366 + 58 + 58 + 58, 1623 .vdisplay = 768, 1624 .vsync_start = 768 + 4, 1625 .vsync_end = 768 + 4 + 4, 1626 .vtotal = 768 + 4 + 4 + 4, 1627 }; 1628 1629 static const struct panel_desc chunghwa_claa101wa01a = { 1630 .modes = &chunghwa_claa101wa01a_mode, 1631 .num_modes = 1, 1632 .bpc = 6, 1633 .size = { 1634 .width = 220, 1635 .height = 120, 1636 }, 1637 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1638 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1639 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1640 }; 1641 1642 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1643 .clock = 69300, 1644 .hdisplay = 1366, 1645 .hsync_start = 1366 + 48, 1646 .hsync_end = 1366 + 48 + 32, 1647 .htotal = 1366 + 48 + 32 + 20, 1648 .vdisplay = 768, 1649 .vsync_start = 768 + 16, 1650 .vsync_end = 768 + 16 + 8, 1651 .vtotal = 768 + 16 + 8 + 16, 1652 }; 1653 1654 static const struct panel_desc chunghwa_claa101wb01 = { 1655 .modes = &chunghwa_claa101wb01_mode, 1656 .num_modes = 1, 1657 .bpc = 6, 1658 .size = { 1659 .width = 223, 1660 .height = 125, 1661 }, 1662 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1663 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1664 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1665 }; 1666 1667 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1668 .pixelclock = { 5000000, 9000000, 12000000 }, 1669 .hactive = { 480, 480, 480 }, 1670 .hfront_porch = { 12, 12, 12 }, 1671 .hback_porch = { 12, 12, 12 }, 1672 .hsync_len = { 21, 21, 21 }, 1673 .vactive = { 272, 272, 272 }, 1674 .vfront_porch = { 4, 4, 4 }, 1675 .vback_porch = { 4, 4, 4 }, 1676 .vsync_len = { 8, 8, 8 }, 1677 }; 1678 1679 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1680 .timings = &dataimage_fg040346dsswbg04_timing, 1681 .num_timings = 1, 1682 .bpc = 8, 1683 .size = { 1684 .width = 95, 1685 .height = 54, 1686 }, 1687 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1688 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1689 .connector_type = DRM_MODE_CONNECTOR_DPI, 1690 }; 1691 1692 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1693 .pixelclock = { 68900000, 71110000, 73400000 }, 1694 .hactive = { 1280, 1280, 1280 }, 1695 .vactive = { 800, 800, 800 }, 1696 .hback_porch = { 100, 100, 100 }, 1697 .hfront_porch = { 100, 100, 100 }, 1698 .vback_porch = { 5, 5, 5 }, 1699 .vfront_porch = { 5, 5, 5 }, 1700 .hsync_len = { 24, 24, 24 }, 1701 .vsync_len = { 3, 3, 3 }, 1702 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1703 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1704 }; 1705 1706 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1707 .timings = &dataimage_fg1001l0dsswmg01_timing, 1708 .num_timings = 1, 1709 .bpc = 8, 1710 .size = { 1711 .width = 217, 1712 .height = 136, 1713 }, 1714 }; 1715 1716 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1717 .clock = 33260, 1718 .hdisplay = 800, 1719 .hsync_start = 800 + 40, 1720 .hsync_end = 800 + 40 + 128, 1721 .htotal = 800 + 40 + 128 + 88, 1722 .vdisplay = 480, 1723 .vsync_start = 480 + 10, 1724 .vsync_end = 480 + 10 + 2, 1725 .vtotal = 480 + 10 + 2 + 33, 1726 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1727 }; 1728 1729 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1730 .modes = &dataimage_scf0700c48ggu18_mode, 1731 .num_modes = 1, 1732 .bpc = 8, 1733 .size = { 1734 .width = 152, 1735 .height = 91, 1736 }, 1737 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1738 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1739 }; 1740 1741 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1742 .pixelclock = { 45000000, 51200000, 57000000 }, 1743 .hactive = { 1024, 1024, 1024 }, 1744 .hfront_porch = { 100, 106, 113 }, 1745 .hback_porch = { 100, 106, 113 }, 1746 .hsync_len = { 100, 108, 114 }, 1747 .vactive = { 600, 600, 600 }, 1748 .vfront_porch = { 8, 11, 15 }, 1749 .vback_porch = { 8, 11, 15 }, 1750 .vsync_len = { 9, 13, 15 }, 1751 .flags = DISPLAY_FLAGS_DE_HIGH, 1752 }; 1753 1754 static const struct panel_desc dlc_dlc0700yzg_1 = { 1755 .timings = &dlc_dlc0700yzg_1_timing, 1756 .num_timings = 1, 1757 .bpc = 6, 1758 .size = { 1759 .width = 154, 1760 .height = 86, 1761 }, 1762 .delay = { 1763 .prepare = 30, 1764 .enable = 200, 1765 .disable = 200, 1766 }, 1767 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1768 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1769 }; 1770 1771 static const struct display_timing dlc_dlc1010gig_timing = { 1772 .pixelclock = { 68900000, 71100000, 73400000 }, 1773 .hactive = { 1280, 1280, 1280 }, 1774 .hfront_porch = { 43, 53, 63 }, 1775 .hback_porch = { 43, 53, 63 }, 1776 .hsync_len = { 44, 54, 64 }, 1777 .vactive = { 800, 800, 800 }, 1778 .vfront_porch = { 5, 8, 11 }, 1779 .vback_porch = { 5, 8, 11 }, 1780 .vsync_len = { 5, 7, 11 }, 1781 .flags = DISPLAY_FLAGS_DE_HIGH, 1782 }; 1783 1784 static const struct panel_desc dlc_dlc1010gig = { 1785 .timings = &dlc_dlc1010gig_timing, 1786 .num_timings = 1, 1787 .bpc = 8, 1788 .size = { 1789 .width = 216, 1790 .height = 135, 1791 }, 1792 .delay = { 1793 .prepare = 60, 1794 .enable = 150, 1795 .disable = 100, 1796 .unprepare = 60, 1797 }, 1798 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1799 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1800 }; 1801 1802 static const struct drm_display_mode edt_et035012dm6_mode = { 1803 .clock = 6500, 1804 .hdisplay = 320, 1805 .hsync_start = 320 + 20, 1806 .hsync_end = 320 + 20 + 30, 1807 .htotal = 320 + 20 + 68, 1808 .vdisplay = 240, 1809 .vsync_start = 240 + 4, 1810 .vsync_end = 240 + 4 + 4, 1811 .vtotal = 240 + 4 + 4 + 14, 1812 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1813 }; 1814 1815 static const struct panel_desc edt_et035012dm6 = { 1816 .modes = &edt_et035012dm6_mode, 1817 .num_modes = 1, 1818 .bpc = 8, 1819 .size = { 1820 .width = 70, 1821 .height = 52, 1822 }, 1823 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1824 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1825 }; 1826 1827 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1828 .clock = 6520, 1829 .hdisplay = 320, 1830 .hsync_start = 320 + 20, 1831 .hsync_end = 320 + 20 + 68, 1832 .htotal = 320 + 20 + 68, 1833 .vdisplay = 240, 1834 .vsync_start = 240 + 4, 1835 .vsync_end = 240 + 4 + 18, 1836 .vtotal = 240 + 4 + 18, 1837 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1838 }; 1839 1840 static const struct panel_desc edt_etm0350g0dh6 = { 1841 .modes = &edt_etm0350g0dh6_mode, 1842 .num_modes = 1, 1843 .bpc = 6, 1844 .size = { 1845 .width = 70, 1846 .height = 53, 1847 }, 1848 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1849 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1850 .connector_type = DRM_MODE_CONNECTOR_DPI, 1851 }; 1852 1853 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1854 .clock = 10870, 1855 .hdisplay = 480, 1856 .hsync_start = 480 + 8, 1857 .hsync_end = 480 + 8 + 4, 1858 .htotal = 480 + 8 + 4 + 41, 1859 1860 /* 1861 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1862 * fb_align 1863 */ 1864 1865 .vdisplay = 288, 1866 .vsync_start = 288 + 2, 1867 .vsync_end = 288 + 2 + 4, 1868 .vtotal = 288 + 2 + 4 + 10, 1869 }; 1870 1871 static const struct panel_desc edt_etm043080dh6gp = { 1872 .modes = &edt_etm043080dh6gp_mode, 1873 .num_modes = 1, 1874 .bpc = 8, 1875 .size = { 1876 .width = 100, 1877 .height = 65, 1878 }, 1879 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1880 .connector_type = DRM_MODE_CONNECTOR_DPI, 1881 }; 1882 1883 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1884 .clock = 9000, 1885 .hdisplay = 480, 1886 .hsync_start = 480 + 2, 1887 .hsync_end = 480 + 2 + 41, 1888 .htotal = 480 + 2 + 41 + 2, 1889 .vdisplay = 272, 1890 .vsync_start = 272 + 2, 1891 .vsync_end = 272 + 2 + 10, 1892 .vtotal = 272 + 2 + 10 + 2, 1893 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1894 }; 1895 1896 static const struct panel_desc edt_etm0430g0dh6 = { 1897 .modes = &edt_etm0430g0dh6_mode, 1898 .num_modes = 1, 1899 .bpc = 6, 1900 .size = { 1901 .width = 95, 1902 .height = 54, 1903 }, 1904 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1905 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1906 .connector_type = DRM_MODE_CONNECTOR_DPI, 1907 }; 1908 1909 static const struct drm_display_mode edt_et057090dhu_mode = { 1910 .clock = 25175, 1911 .hdisplay = 640, 1912 .hsync_start = 640 + 16, 1913 .hsync_end = 640 + 16 + 30, 1914 .htotal = 640 + 16 + 30 + 114, 1915 .vdisplay = 480, 1916 .vsync_start = 480 + 10, 1917 .vsync_end = 480 + 10 + 3, 1918 .vtotal = 480 + 10 + 3 + 32, 1919 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1920 }; 1921 1922 static const struct panel_desc edt_et057090dhu = { 1923 .modes = &edt_et057090dhu_mode, 1924 .num_modes = 1, 1925 .bpc = 6, 1926 .size = { 1927 .width = 115, 1928 .height = 86, 1929 }, 1930 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1931 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1932 .connector_type = DRM_MODE_CONNECTOR_DPI, 1933 }; 1934 1935 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1936 .clock = 33260, 1937 .hdisplay = 800, 1938 .hsync_start = 800 + 40, 1939 .hsync_end = 800 + 40 + 128, 1940 .htotal = 800 + 40 + 128 + 88, 1941 .vdisplay = 480, 1942 .vsync_start = 480 + 10, 1943 .vsync_end = 480 + 10 + 2, 1944 .vtotal = 480 + 10 + 2 + 33, 1945 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1946 }; 1947 1948 static const struct panel_desc edt_etm0700g0dh6 = { 1949 .modes = &edt_etm0700g0dh6_mode, 1950 .num_modes = 1, 1951 .bpc = 6, 1952 .size = { 1953 .width = 152, 1954 .height = 91, 1955 }, 1956 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1957 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1958 .connector_type = DRM_MODE_CONNECTOR_DPI, 1959 }; 1960 1961 static const struct panel_desc edt_etm0700g0bdh6 = { 1962 .modes = &edt_etm0700g0dh6_mode, 1963 .num_modes = 1, 1964 .bpc = 6, 1965 .size = { 1966 .width = 152, 1967 .height = 91, 1968 }, 1969 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1970 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1971 .connector_type = DRM_MODE_CONNECTOR_DPI, 1972 }; 1973 1974 static const struct display_timing edt_etml0700y5dha_timing = { 1975 .pixelclock = { 40800000, 51200000, 67200000 }, 1976 .hactive = { 1024, 1024, 1024 }, 1977 .hfront_porch = { 30, 106, 125 }, 1978 .hback_porch = { 30, 106, 125 }, 1979 .hsync_len = { 30, 108, 126 }, 1980 .vactive = { 600, 600, 600 }, 1981 .vfront_porch = { 3, 12, 67}, 1982 .vback_porch = { 3, 12, 67 }, 1983 .vsync_len = { 4, 11, 66 }, 1984 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1985 DISPLAY_FLAGS_DE_HIGH, 1986 }; 1987 1988 static const struct panel_desc edt_etml0700y5dha = { 1989 .timings = &edt_etml0700y5dha_timing, 1990 .num_timings = 1, 1991 .bpc = 8, 1992 .size = { 1993 .width = 155, 1994 .height = 86, 1995 }, 1996 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1997 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1998 }; 1999 2000 static const struct display_timing edt_etml1010g3dra_timing = { 2001 .pixelclock = { 66300000, 72400000, 78900000 }, 2002 .hactive = { 1280, 1280, 1280 }, 2003 .hfront_porch = { 12, 72, 132 }, 2004 .hback_porch = { 86, 86, 86 }, 2005 .hsync_len = { 2, 2, 2 }, 2006 .vactive = { 800, 800, 800 }, 2007 .vfront_porch = { 1, 15, 49 }, 2008 .vback_porch = { 21, 21, 21 }, 2009 .vsync_len = { 2, 2, 2 }, 2010 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2011 DISPLAY_FLAGS_DE_HIGH, 2012 }; 2013 2014 static const struct panel_desc edt_etml1010g3dra = { 2015 .timings = &edt_etml1010g3dra_timing, 2016 .num_timings = 1, 2017 .bpc = 8, 2018 .size = { 2019 .width = 216, 2020 .height = 135, 2021 }, 2022 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2023 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2024 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2025 }; 2026 2027 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2028 .clock = 25175, 2029 .hdisplay = 640, 2030 .hsync_start = 640, 2031 .hsync_end = 640 + 16, 2032 .htotal = 640 + 16 + 30 + 114, 2033 .vdisplay = 480, 2034 .vsync_start = 480 + 10, 2035 .vsync_end = 480 + 10 + 3, 2036 .vtotal = 480 + 10 + 3 + 35, 2037 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2038 }; 2039 2040 static const struct panel_desc edt_etmv570g2dhu = { 2041 .modes = &edt_etmv570g2dhu_mode, 2042 .num_modes = 1, 2043 .bpc = 6, 2044 .size = { 2045 .width = 115, 2046 .height = 86, 2047 }, 2048 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2049 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2050 .connector_type = DRM_MODE_CONNECTOR_DPI, 2051 }; 2052 2053 static const struct display_timing eink_vb3300_kca_timing = { 2054 .pixelclock = { 40000000, 40000000, 40000000 }, 2055 .hactive = { 334, 334, 334 }, 2056 .hfront_porch = { 1, 1, 1 }, 2057 .hback_porch = { 1, 1, 1 }, 2058 .hsync_len = { 1, 1, 1 }, 2059 .vactive = { 1405, 1405, 1405 }, 2060 .vfront_porch = { 1, 1, 1 }, 2061 .vback_porch = { 1, 1, 1 }, 2062 .vsync_len = { 1, 1, 1 }, 2063 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2064 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2065 }; 2066 2067 static const struct panel_desc eink_vb3300_kca = { 2068 .timings = &eink_vb3300_kca_timing, 2069 .num_timings = 1, 2070 .bpc = 6, 2071 .size = { 2072 .width = 157, 2073 .height = 209, 2074 }, 2075 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2076 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2077 .connector_type = DRM_MODE_CONNECTOR_DPI, 2078 }; 2079 2080 static const struct display_timing evervision_vgg644804_timing = { 2081 .pixelclock = { 25175000, 25175000, 25175000 }, 2082 .hactive = { 640, 640, 640 }, 2083 .hfront_porch = { 16, 16, 16 }, 2084 .hback_porch = { 82, 114, 170 }, 2085 .hsync_len = { 5, 30, 30 }, 2086 .vactive = { 480, 480, 480 }, 2087 .vfront_porch = { 10, 10, 10 }, 2088 .vback_porch = { 30, 32, 34 }, 2089 .vsync_len = { 1, 3, 5 }, 2090 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2091 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2092 DISPLAY_FLAGS_SYNC_POSEDGE, 2093 }; 2094 2095 static const struct panel_desc evervision_vgg644804 = { 2096 .timings = &evervision_vgg644804_timing, 2097 .num_timings = 1, 2098 .bpc = 8, 2099 .size = { 2100 .width = 115, 2101 .height = 86, 2102 }, 2103 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2104 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2105 }; 2106 2107 static const struct display_timing evervision_vgg804821_timing = { 2108 .pixelclock = { 27600000, 33300000, 50000000 }, 2109 .hactive = { 800, 800, 800 }, 2110 .hfront_porch = { 40, 66, 70 }, 2111 .hback_porch = { 40, 67, 70 }, 2112 .hsync_len = { 40, 67, 70 }, 2113 .vactive = { 480, 480, 480 }, 2114 .vfront_porch = { 6, 10, 10 }, 2115 .vback_porch = { 7, 11, 11 }, 2116 .vsync_len = { 7, 11, 11 }, 2117 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2118 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2119 DISPLAY_FLAGS_SYNC_NEGEDGE, 2120 }; 2121 2122 static const struct panel_desc evervision_vgg804821 = { 2123 .timings = &evervision_vgg804821_timing, 2124 .num_timings = 1, 2125 .bpc = 8, 2126 .size = { 2127 .width = 108, 2128 .height = 64, 2129 }, 2130 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2131 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2132 }; 2133 2134 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2135 .clock = 32260, 2136 .hdisplay = 800, 2137 .hsync_start = 800 + 168, 2138 .hsync_end = 800 + 168 + 64, 2139 .htotal = 800 + 168 + 64 + 88, 2140 .vdisplay = 480, 2141 .vsync_start = 480 + 37, 2142 .vsync_end = 480 + 37 + 2, 2143 .vtotal = 480 + 37 + 2 + 8, 2144 }; 2145 2146 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2147 .modes = &foxlink_fl500wvr00_a0t_mode, 2148 .num_modes = 1, 2149 .bpc = 8, 2150 .size = { 2151 .width = 108, 2152 .height = 65, 2153 }, 2154 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2155 }; 2156 2157 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2158 { /* 60 Hz */ 2159 .clock = 6000, 2160 .hdisplay = 320, 2161 .hsync_start = 320 + 44, 2162 .hsync_end = 320 + 44 + 16, 2163 .htotal = 320 + 44 + 16 + 20, 2164 .vdisplay = 240, 2165 .vsync_start = 240 + 2, 2166 .vsync_end = 240 + 2 + 6, 2167 .vtotal = 240 + 2 + 6 + 2, 2168 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2169 }, 2170 { /* 50 Hz */ 2171 .clock = 5400, 2172 .hdisplay = 320, 2173 .hsync_start = 320 + 56, 2174 .hsync_end = 320 + 56 + 16, 2175 .htotal = 320 + 56 + 16 + 40, 2176 .vdisplay = 240, 2177 .vsync_start = 240 + 2, 2178 .vsync_end = 240 + 2 + 6, 2179 .vtotal = 240 + 2 + 6 + 2, 2180 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2181 }, 2182 }; 2183 2184 static const struct panel_desc frida_frd350h54004 = { 2185 .modes = frida_frd350h54004_modes, 2186 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2187 .bpc = 8, 2188 .size = { 2189 .width = 77, 2190 .height = 64, 2191 }, 2192 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2193 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2194 .connector_type = DRM_MODE_CONNECTOR_DPI, 2195 }; 2196 2197 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2198 .clock = 67185, 2199 .hdisplay = 800, 2200 .hsync_start = 800 + 20, 2201 .hsync_end = 800 + 20 + 24, 2202 .htotal = 800 + 20 + 24 + 20, 2203 .vdisplay = 1280, 2204 .vsync_start = 1280 + 4, 2205 .vsync_end = 1280 + 4 + 8, 2206 .vtotal = 1280 + 4 + 8 + 4, 2207 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2208 }; 2209 2210 static const struct panel_desc friendlyarm_hd702e = { 2211 .modes = &friendlyarm_hd702e_mode, 2212 .num_modes = 1, 2213 .size = { 2214 .width = 94, 2215 .height = 151, 2216 }, 2217 }; 2218 2219 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2220 .clock = 9000, 2221 .hdisplay = 480, 2222 .hsync_start = 480 + 5, 2223 .hsync_end = 480 + 5 + 1, 2224 .htotal = 480 + 5 + 1 + 40, 2225 .vdisplay = 272, 2226 .vsync_start = 272 + 8, 2227 .vsync_end = 272 + 8 + 1, 2228 .vtotal = 272 + 8 + 1 + 8, 2229 }; 2230 2231 static const struct panel_desc giantplus_gpg482739qs5 = { 2232 .modes = &giantplus_gpg482739qs5_mode, 2233 .num_modes = 1, 2234 .bpc = 8, 2235 .size = { 2236 .width = 95, 2237 .height = 54, 2238 }, 2239 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2240 }; 2241 2242 static const struct display_timing giantplus_gpm940b0_timing = { 2243 .pixelclock = { 13500000, 27000000, 27500000 }, 2244 .hactive = { 320, 320, 320 }, 2245 .hfront_porch = { 14, 686, 718 }, 2246 .hback_porch = { 50, 70, 255 }, 2247 .hsync_len = { 1, 1, 1 }, 2248 .vactive = { 240, 240, 240 }, 2249 .vfront_porch = { 1, 1, 179 }, 2250 .vback_porch = { 1, 21, 31 }, 2251 .vsync_len = { 1, 1, 6 }, 2252 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2253 }; 2254 2255 static const struct panel_desc giantplus_gpm940b0 = { 2256 .timings = &giantplus_gpm940b0_timing, 2257 .num_timings = 1, 2258 .bpc = 8, 2259 .size = { 2260 .width = 60, 2261 .height = 45, 2262 }, 2263 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2264 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2265 }; 2266 2267 static const struct display_timing hannstar_hsd070pww1_timing = { 2268 .pixelclock = { 64300000, 71100000, 82000000 }, 2269 .hactive = { 1280, 1280, 1280 }, 2270 .hfront_porch = { 1, 1, 10 }, 2271 .hback_porch = { 1, 1, 10 }, 2272 /* 2273 * According to the data sheet, the minimum horizontal blanking interval 2274 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2275 * minimum working horizontal blanking interval to be 60 clocks. 2276 */ 2277 .hsync_len = { 58, 158, 661 }, 2278 .vactive = { 800, 800, 800 }, 2279 .vfront_porch = { 1, 1, 10 }, 2280 .vback_porch = { 1, 1, 10 }, 2281 .vsync_len = { 1, 21, 203 }, 2282 .flags = DISPLAY_FLAGS_DE_HIGH, 2283 }; 2284 2285 static const struct panel_desc hannstar_hsd070pww1 = { 2286 .timings = &hannstar_hsd070pww1_timing, 2287 .num_timings = 1, 2288 .bpc = 6, 2289 .size = { 2290 .width = 151, 2291 .height = 94, 2292 }, 2293 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2294 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2295 }; 2296 2297 static const struct display_timing hannstar_hsd100pxn1_timing = { 2298 .pixelclock = { 55000000, 65000000, 75000000 }, 2299 .hactive = { 1024, 1024, 1024 }, 2300 .hfront_porch = { 40, 40, 40 }, 2301 .hback_porch = { 220, 220, 220 }, 2302 .hsync_len = { 20, 60, 100 }, 2303 .vactive = { 768, 768, 768 }, 2304 .vfront_porch = { 7, 7, 7 }, 2305 .vback_porch = { 21, 21, 21 }, 2306 .vsync_len = { 10, 10, 10 }, 2307 .flags = DISPLAY_FLAGS_DE_HIGH, 2308 }; 2309 2310 static const struct panel_desc hannstar_hsd100pxn1 = { 2311 .timings = &hannstar_hsd100pxn1_timing, 2312 .num_timings = 1, 2313 .bpc = 6, 2314 .size = { 2315 .width = 203, 2316 .height = 152, 2317 }, 2318 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2319 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2320 }; 2321 2322 static const struct display_timing hannstar_hsd101pww2_timing = { 2323 .pixelclock = { 64300000, 71100000, 82000000 }, 2324 .hactive = { 1280, 1280, 1280 }, 2325 .hfront_porch = { 1, 1, 10 }, 2326 .hback_porch = { 1, 1, 10 }, 2327 .hsync_len = { 58, 158, 661 }, 2328 .vactive = { 800, 800, 800 }, 2329 .vfront_porch = { 1, 1, 10 }, 2330 .vback_porch = { 1, 1, 10 }, 2331 .vsync_len = { 1, 21, 203 }, 2332 .flags = DISPLAY_FLAGS_DE_HIGH, 2333 }; 2334 2335 static const struct panel_desc hannstar_hsd101pww2 = { 2336 .timings = &hannstar_hsd101pww2_timing, 2337 .num_timings = 1, 2338 .bpc = 8, 2339 .size = { 2340 .width = 217, 2341 .height = 136, 2342 }, 2343 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2344 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2345 }; 2346 2347 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2348 .clock = 33333, 2349 .hdisplay = 800, 2350 .hsync_start = 800 + 85, 2351 .hsync_end = 800 + 85 + 86, 2352 .htotal = 800 + 85 + 86 + 85, 2353 .vdisplay = 480, 2354 .vsync_start = 480 + 16, 2355 .vsync_end = 480 + 16 + 13, 2356 .vtotal = 480 + 16 + 13 + 16, 2357 }; 2358 2359 static const struct panel_desc hitachi_tx23d38vm0caa = { 2360 .modes = &hitachi_tx23d38vm0caa_mode, 2361 .num_modes = 1, 2362 .bpc = 6, 2363 .size = { 2364 .width = 195, 2365 .height = 117, 2366 }, 2367 .delay = { 2368 .enable = 160, 2369 .disable = 160, 2370 }, 2371 }; 2372 2373 static const struct drm_display_mode innolux_at043tn24_mode = { 2374 .clock = 9000, 2375 .hdisplay = 480, 2376 .hsync_start = 480 + 2, 2377 .hsync_end = 480 + 2 + 41, 2378 .htotal = 480 + 2 + 41 + 2, 2379 .vdisplay = 272, 2380 .vsync_start = 272 + 2, 2381 .vsync_end = 272 + 2 + 10, 2382 .vtotal = 272 + 2 + 10 + 2, 2383 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2384 }; 2385 2386 static const struct panel_desc innolux_at043tn24 = { 2387 .modes = &innolux_at043tn24_mode, 2388 .num_modes = 1, 2389 .bpc = 8, 2390 .size = { 2391 .width = 95, 2392 .height = 54, 2393 }, 2394 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2395 .connector_type = DRM_MODE_CONNECTOR_DPI, 2396 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2397 }; 2398 2399 static const struct drm_display_mode innolux_at070tn92_mode = { 2400 .clock = 33333, 2401 .hdisplay = 800, 2402 .hsync_start = 800 + 210, 2403 .hsync_end = 800 + 210 + 20, 2404 .htotal = 800 + 210 + 20 + 46, 2405 .vdisplay = 480, 2406 .vsync_start = 480 + 22, 2407 .vsync_end = 480 + 22 + 10, 2408 .vtotal = 480 + 22 + 23 + 10, 2409 }; 2410 2411 static const struct panel_desc innolux_at070tn92 = { 2412 .modes = &innolux_at070tn92_mode, 2413 .num_modes = 1, 2414 .size = { 2415 .width = 154, 2416 .height = 86, 2417 }, 2418 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2419 }; 2420 2421 static const struct display_timing innolux_g070ace_l01_timing = { 2422 .pixelclock = { 25200000, 35000000, 35700000 }, 2423 .hactive = { 800, 800, 800 }, 2424 .hfront_porch = { 30, 32, 87 }, 2425 .hback_porch = { 30, 32, 87 }, 2426 .hsync_len = { 1, 1, 1 }, 2427 .vactive = { 480, 480, 480 }, 2428 .vfront_porch = { 3, 3, 3 }, 2429 .vback_porch = { 13, 13, 13 }, 2430 .vsync_len = { 1, 1, 4 }, 2431 .flags = DISPLAY_FLAGS_DE_HIGH, 2432 }; 2433 2434 static const struct panel_desc innolux_g070ace_l01 = { 2435 .timings = &innolux_g070ace_l01_timing, 2436 .num_timings = 1, 2437 .bpc = 8, 2438 .size = { 2439 .width = 152, 2440 .height = 91, 2441 }, 2442 .delay = { 2443 .prepare = 10, 2444 .enable = 50, 2445 .disable = 50, 2446 .unprepare = 500, 2447 }, 2448 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2449 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2450 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2451 }; 2452 2453 static const struct display_timing innolux_g070y2_l01_timing = { 2454 .pixelclock = { 28000000, 29500000, 32000000 }, 2455 .hactive = { 800, 800, 800 }, 2456 .hfront_porch = { 61, 91, 141 }, 2457 .hback_porch = { 60, 90, 140 }, 2458 .hsync_len = { 12, 12, 12 }, 2459 .vactive = { 480, 480, 480 }, 2460 .vfront_porch = { 4, 9, 30 }, 2461 .vback_porch = { 4, 8, 28 }, 2462 .vsync_len = { 2, 2, 2 }, 2463 .flags = DISPLAY_FLAGS_DE_HIGH, 2464 }; 2465 2466 static const struct panel_desc innolux_g070y2_l01 = { 2467 .timings = &innolux_g070y2_l01_timing, 2468 .num_timings = 1, 2469 .bpc = 8, 2470 .size = { 2471 .width = 152, 2472 .height = 91, 2473 }, 2474 .delay = { 2475 .prepare = 10, 2476 .enable = 100, 2477 .disable = 100, 2478 .unprepare = 800, 2479 }, 2480 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2481 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2482 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2483 }; 2484 2485 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2486 .clock = 33333, 2487 .hdisplay = 800, 2488 .hsync_start = 800 + 210, 2489 .hsync_end = 800 + 210 + 20, 2490 .htotal = 800 + 210 + 20 + 46, 2491 .vdisplay = 480, 2492 .vsync_start = 480 + 22, 2493 .vsync_end = 480 + 22 + 10, 2494 .vtotal = 480 + 22 + 23 + 10, 2495 }; 2496 2497 static const struct panel_desc innolux_g070y2_t02 = { 2498 .modes = &innolux_g070y2_t02_mode, 2499 .num_modes = 1, 2500 .bpc = 8, 2501 .size = { 2502 .width = 152, 2503 .height = 92, 2504 }, 2505 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2506 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2507 .connector_type = DRM_MODE_CONNECTOR_DPI, 2508 }; 2509 2510 static const struct display_timing innolux_g101ice_l01_timing = { 2511 .pixelclock = { 60400000, 71100000, 74700000 }, 2512 .hactive = { 1280, 1280, 1280 }, 2513 .hfront_porch = { 30, 60, 70 }, 2514 .hback_porch = { 30, 60, 70 }, 2515 .hsync_len = { 22, 40, 60 }, 2516 .vactive = { 800, 800, 800 }, 2517 .vfront_porch = { 3, 8, 14 }, 2518 .vback_porch = { 3, 8, 14 }, 2519 .vsync_len = { 4, 7, 12 }, 2520 .flags = DISPLAY_FLAGS_DE_HIGH, 2521 }; 2522 2523 static const struct panel_desc innolux_g101ice_l01 = { 2524 .timings = &innolux_g101ice_l01_timing, 2525 .num_timings = 1, 2526 .bpc = 8, 2527 .size = { 2528 .width = 217, 2529 .height = 135, 2530 }, 2531 .delay = { 2532 .enable = 200, 2533 .disable = 200, 2534 }, 2535 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2536 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2537 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2538 }; 2539 2540 static const struct display_timing innolux_g121i1_l01_timing = { 2541 .pixelclock = { 67450000, 71000000, 74550000 }, 2542 .hactive = { 1280, 1280, 1280 }, 2543 .hfront_porch = { 40, 80, 160 }, 2544 .hback_porch = { 39, 79, 159 }, 2545 .hsync_len = { 1, 1, 1 }, 2546 .vactive = { 800, 800, 800 }, 2547 .vfront_porch = { 5, 11, 100 }, 2548 .vback_porch = { 4, 11, 99 }, 2549 .vsync_len = { 1, 1, 1 }, 2550 }; 2551 2552 static const struct panel_desc innolux_g121i1_l01 = { 2553 .timings = &innolux_g121i1_l01_timing, 2554 .num_timings = 1, 2555 .bpc = 6, 2556 .size = { 2557 .width = 261, 2558 .height = 163, 2559 }, 2560 .delay = { 2561 .enable = 200, 2562 .disable = 20, 2563 }, 2564 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2565 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2566 }; 2567 2568 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2569 .clock = 65000, 2570 .hdisplay = 1024, 2571 .hsync_start = 1024 + 0, 2572 .hsync_end = 1024 + 1, 2573 .htotal = 1024 + 0 + 1 + 320, 2574 .vdisplay = 768, 2575 .vsync_start = 768 + 38, 2576 .vsync_end = 768 + 38 + 1, 2577 .vtotal = 768 + 38 + 1 + 0, 2578 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2579 }; 2580 2581 static const struct panel_desc innolux_g121x1_l03 = { 2582 .modes = &innolux_g121x1_l03_mode, 2583 .num_modes = 1, 2584 .bpc = 6, 2585 .size = { 2586 .width = 246, 2587 .height = 185, 2588 }, 2589 .delay = { 2590 .enable = 200, 2591 .unprepare = 200, 2592 .disable = 400, 2593 }, 2594 }; 2595 2596 static const struct display_timing innolux_g156hce_l01_timings = { 2597 .pixelclock = { 120000000, 141860000, 150000000 }, 2598 .hactive = { 1920, 1920, 1920 }, 2599 .hfront_porch = { 80, 90, 100 }, 2600 .hback_porch = { 80, 90, 100 }, 2601 .hsync_len = { 20, 30, 30 }, 2602 .vactive = { 1080, 1080, 1080 }, 2603 .vfront_porch = { 3, 10, 20 }, 2604 .vback_porch = { 3, 10, 20 }, 2605 .vsync_len = { 4, 10, 10 }, 2606 }; 2607 2608 static const struct panel_desc innolux_g156hce_l01 = { 2609 .timings = &innolux_g156hce_l01_timings, 2610 .num_timings = 1, 2611 .bpc = 8, 2612 .size = { 2613 .width = 344, 2614 .height = 194, 2615 }, 2616 .delay = { 2617 .prepare = 1, /* T1+T2 */ 2618 .enable = 450, /* T5 */ 2619 .disable = 200, /* T6 */ 2620 .unprepare = 10, /* T3+T7 */ 2621 }, 2622 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2623 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2624 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2625 }; 2626 2627 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2628 .clock = 69300, 2629 .hdisplay = 1366, 2630 .hsync_start = 1366 + 16, 2631 .hsync_end = 1366 + 16 + 34, 2632 .htotal = 1366 + 16 + 34 + 50, 2633 .vdisplay = 768, 2634 .vsync_start = 768 + 2, 2635 .vsync_end = 768 + 2 + 6, 2636 .vtotal = 768 + 2 + 6 + 12, 2637 }; 2638 2639 static const struct panel_desc innolux_n156bge_l21 = { 2640 .modes = &innolux_n156bge_l21_mode, 2641 .num_modes = 1, 2642 .bpc = 6, 2643 .size = { 2644 .width = 344, 2645 .height = 193, 2646 }, 2647 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2648 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2649 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2650 }; 2651 2652 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2653 .clock = 51501, 2654 .hdisplay = 1024, 2655 .hsync_start = 1024 + 128, 2656 .hsync_end = 1024 + 128 + 64, 2657 .htotal = 1024 + 128 + 64 + 128, 2658 .vdisplay = 600, 2659 .vsync_start = 600 + 16, 2660 .vsync_end = 600 + 16 + 4, 2661 .vtotal = 600 + 16 + 4 + 16, 2662 }; 2663 2664 static const struct panel_desc innolux_zj070na_01p = { 2665 .modes = &innolux_zj070na_01p_mode, 2666 .num_modes = 1, 2667 .bpc = 6, 2668 .size = { 2669 .width = 154, 2670 .height = 90, 2671 }, 2672 }; 2673 2674 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2675 .pixelclock = { 5580000, 5850000, 6200000 }, 2676 .hactive = { 320, 320, 320 }, 2677 .hfront_porch = { 30, 30, 30 }, 2678 .hback_porch = { 30, 30, 30 }, 2679 .hsync_len = { 1, 5, 17 }, 2680 .vactive = { 240, 240, 240 }, 2681 .vfront_porch = { 6, 6, 6 }, 2682 .vback_porch = { 5, 5, 5 }, 2683 .vsync_len = { 1, 2, 11 }, 2684 .flags = DISPLAY_FLAGS_DE_HIGH, 2685 }; 2686 2687 static const struct panel_desc koe_tx14d24vm1bpa = { 2688 .timings = &koe_tx14d24vm1bpa_timing, 2689 .num_timings = 1, 2690 .bpc = 6, 2691 .size = { 2692 .width = 115, 2693 .height = 86, 2694 }, 2695 }; 2696 2697 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2698 .pixelclock = { 151820000, 156720000, 159780000 }, 2699 .hactive = { 1920, 1920, 1920 }, 2700 .hfront_porch = { 105, 130, 142 }, 2701 .hback_porch = { 45, 70, 82 }, 2702 .hsync_len = { 30, 30, 30 }, 2703 .vactive = { 1200, 1200, 1200}, 2704 .vfront_porch = { 3, 5, 10 }, 2705 .vback_porch = { 2, 5, 10 }, 2706 .vsync_len = { 5, 5, 5 }, 2707 }; 2708 2709 static const struct panel_desc koe_tx26d202vm0bwa = { 2710 .timings = &koe_tx26d202vm0bwa_timing, 2711 .num_timings = 1, 2712 .bpc = 8, 2713 .size = { 2714 .width = 217, 2715 .height = 136, 2716 }, 2717 .delay = { 2718 .prepare = 1000, 2719 .enable = 1000, 2720 .unprepare = 1000, 2721 .disable = 1000, 2722 }, 2723 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2724 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2725 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2726 }; 2727 2728 static const struct display_timing koe_tx31d200vm0baa_timing = { 2729 .pixelclock = { 39600000, 43200000, 48000000 }, 2730 .hactive = { 1280, 1280, 1280 }, 2731 .hfront_porch = { 16, 36, 56 }, 2732 .hback_porch = { 16, 36, 56 }, 2733 .hsync_len = { 8, 8, 8 }, 2734 .vactive = { 480, 480, 480 }, 2735 .vfront_porch = { 6, 21, 33 }, 2736 .vback_porch = { 6, 21, 33 }, 2737 .vsync_len = { 8, 8, 8 }, 2738 .flags = DISPLAY_FLAGS_DE_HIGH, 2739 }; 2740 2741 static const struct panel_desc koe_tx31d200vm0baa = { 2742 .timings = &koe_tx31d200vm0baa_timing, 2743 .num_timings = 1, 2744 .bpc = 6, 2745 .size = { 2746 .width = 292, 2747 .height = 109, 2748 }, 2749 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2750 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2751 }; 2752 2753 static const struct display_timing kyo_tcg121xglp_timing = { 2754 .pixelclock = { 52000000, 65000000, 71000000 }, 2755 .hactive = { 1024, 1024, 1024 }, 2756 .hfront_porch = { 2, 2, 2 }, 2757 .hback_porch = { 2, 2, 2 }, 2758 .hsync_len = { 86, 124, 244 }, 2759 .vactive = { 768, 768, 768 }, 2760 .vfront_porch = { 2, 2, 2 }, 2761 .vback_porch = { 2, 2, 2 }, 2762 .vsync_len = { 6, 34, 73 }, 2763 .flags = DISPLAY_FLAGS_DE_HIGH, 2764 }; 2765 2766 static const struct panel_desc kyo_tcg121xglp = { 2767 .timings = &kyo_tcg121xglp_timing, 2768 .num_timings = 1, 2769 .bpc = 8, 2770 .size = { 2771 .width = 246, 2772 .height = 184, 2773 }, 2774 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2775 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2776 }; 2777 2778 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2779 .clock = 7000, 2780 .hdisplay = 320, 2781 .hsync_start = 320 + 20, 2782 .hsync_end = 320 + 20 + 30, 2783 .htotal = 320 + 20 + 30 + 38, 2784 .vdisplay = 240, 2785 .vsync_start = 240 + 4, 2786 .vsync_end = 240 + 4 + 3, 2787 .vtotal = 240 + 4 + 3 + 15, 2788 }; 2789 2790 static const struct panel_desc lemaker_bl035_rgb_002 = { 2791 .modes = &lemaker_bl035_rgb_002_mode, 2792 .num_modes = 1, 2793 .size = { 2794 .width = 70, 2795 .height = 52, 2796 }, 2797 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2798 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2799 }; 2800 2801 static const struct display_timing lg_lb070wv8_timing = { 2802 .pixelclock = { 31950000, 33260000, 34600000 }, 2803 .hactive = { 800, 800, 800 }, 2804 .hfront_porch = { 88, 88, 88 }, 2805 .hback_porch = { 88, 88, 88 }, 2806 .hsync_len = { 80, 80, 80 }, 2807 .vactive = { 480, 480, 480 }, 2808 .vfront_porch = { 10, 10, 10 }, 2809 .vback_porch = { 10, 10, 10 }, 2810 .vsync_len = { 25, 25, 25 }, 2811 }; 2812 2813 static const struct panel_desc lg_lb070wv8 = { 2814 .timings = &lg_lb070wv8_timing, 2815 .num_timings = 1, 2816 .bpc = 8, 2817 .size = { 2818 .width = 151, 2819 .height = 91, 2820 }, 2821 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2822 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2823 }; 2824 2825 static const struct display_timing logictechno_lt161010_2nh_timing = { 2826 .pixelclock = { 26400000, 33300000, 46800000 }, 2827 .hactive = { 800, 800, 800 }, 2828 .hfront_porch = { 16, 210, 354 }, 2829 .hback_porch = { 46, 46, 46 }, 2830 .hsync_len = { 1, 20, 40 }, 2831 .vactive = { 480, 480, 480 }, 2832 .vfront_porch = { 7, 22, 147 }, 2833 .vback_porch = { 23, 23, 23 }, 2834 .vsync_len = { 1, 10, 20 }, 2835 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2836 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2837 DISPLAY_FLAGS_SYNC_POSEDGE, 2838 }; 2839 2840 static const struct panel_desc logictechno_lt161010_2nh = { 2841 .timings = &logictechno_lt161010_2nh_timing, 2842 .num_timings = 1, 2843 .bpc = 6, 2844 .size = { 2845 .width = 154, 2846 .height = 86, 2847 }, 2848 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2849 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2850 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2851 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2852 .connector_type = DRM_MODE_CONNECTOR_DPI, 2853 }; 2854 2855 static const struct display_timing logictechno_lt170410_2whc_timing = { 2856 .pixelclock = { 68900000, 71100000, 73400000 }, 2857 .hactive = { 1280, 1280, 1280 }, 2858 .hfront_porch = { 23, 60, 71 }, 2859 .hback_porch = { 23, 60, 71 }, 2860 .hsync_len = { 15, 40, 47 }, 2861 .vactive = { 800, 800, 800 }, 2862 .vfront_porch = { 5, 7, 10 }, 2863 .vback_porch = { 5, 7, 10 }, 2864 .vsync_len = { 6, 9, 12 }, 2865 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2866 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2867 DISPLAY_FLAGS_SYNC_POSEDGE, 2868 }; 2869 2870 static const struct panel_desc logictechno_lt170410_2whc = { 2871 .timings = &logictechno_lt170410_2whc_timing, 2872 .num_timings = 1, 2873 .bpc = 8, 2874 .size = { 2875 .width = 217, 2876 .height = 136, 2877 }, 2878 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2879 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2880 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2881 }; 2882 2883 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2884 .clock = 33000, 2885 .hdisplay = 800, 2886 .hsync_start = 800 + 112, 2887 .hsync_end = 800 + 112 + 3, 2888 .htotal = 800 + 112 + 3 + 85, 2889 .vdisplay = 480, 2890 .vsync_start = 480 + 38, 2891 .vsync_end = 480 + 38 + 3, 2892 .vtotal = 480 + 38 + 3 + 29, 2893 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2894 }; 2895 2896 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2897 .modes = &logictechno_lttd800480070_l2rt_mode, 2898 .num_modes = 1, 2899 .bpc = 8, 2900 .size = { 2901 .width = 154, 2902 .height = 86, 2903 }, 2904 .delay = { 2905 .prepare = 45, 2906 .enable = 100, 2907 .disable = 100, 2908 .unprepare = 45 2909 }, 2910 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2911 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2912 .connector_type = DRM_MODE_CONNECTOR_DPI, 2913 }; 2914 2915 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2916 .clock = 33000, 2917 .hdisplay = 800, 2918 .hsync_start = 800 + 154, 2919 .hsync_end = 800 + 154 + 3, 2920 .htotal = 800 + 154 + 3 + 43, 2921 .vdisplay = 480, 2922 .vsync_start = 480 + 47, 2923 .vsync_end = 480 + 47 + 3, 2924 .vtotal = 480 + 47 + 3 + 20, 2925 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2926 }; 2927 2928 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2929 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2930 .num_modes = 1, 2931 .bpc = 8, 2932 .size = { 2933 .width = 154, 2934 .height = 86, 2935 }, 2936 .delay = { 2937 .prepare = 45, 2938 .enable = 100, 2939 .disable = 100, 2940 .unprepare = 45 2941 }, 2942 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2943 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2944 .connector_type = DRM_MODE_CONNECTOR_DPI, 2945 }; 2946 2947 static const struct drm_display_mode logicpd_type_28_mode = { 2948 .clock = 9107, 2949 .hdisplay = 480, 2950 .hsync_start = 480 + 3, 2951 .hsync_end = 480 + 3 + 42, 2952 .htotal = 480 + 3 + 42 + 2, 2953 2954 .vdisplay = 272, 2955 .vsync_start = 272 + 2, 2956 .vsync_end = 272 + 2 + 11, 2957 .vtotal = 272 + 2 + 11 + 3, 2958 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2959 }; 2960 2961 static const struct panel_desc logicpd_type_28 = { 2962 .modes = &logicpd_type_28_mode, 2963 .num_modes = 1, 2964 .bpc = 8, 2965 .size = { 2966 .width = 105, 2967 .height = 67, 2968 }, 2969 .delay = { 2970 .prepare = 200, 2971 .enable = 200, 2972 .unprepare = 200, 2973 .disable = 200, 2974 }, 2975 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2976 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2977 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2978 .connector_type = DRM_MODE_CONNECTOR_DPI, 2979 }; 2980 2981 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2982 .clock = 30400, 2983 .hdisplay = 800, 2984 .hsync_start = 800 + 0, 2985 .hsync_end = 800 + 1, 2986 .htotal = 800 + 0 + 1 + 160, 2987 .vdisplay = 480, 2988 .vsync_start = 480 + 0, 2989 .vsync_end = 480 + 48 + 1, 2990 .vtotal = 480 + 48 + 1 + 0, 2991 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2992 }; 2993 2994 static const struct panel_desc mitsubishi_aa070mc01 = { 2995 .modes = &mitsubishi_aa070mc01_mode, 2996 .num_modes = 1, 2997 .bpc = 8, 2998 .size = { 2999 .width = 152, 3000 .height = 91, 3001 }, 3002 3003 .delay = { 3004 .enable = 200, 3005 .unprepare = 200, 3006 .disable = 400, 3007 }, 3008 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3009 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3010 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3011 }; 3012 3013 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3014 .clock = 56234, 3015 .hdisplay = 1024, 3016 .hsync_start = 1024 + 24, 3017 .hsync_end = 1024 + 24 + 63, 3018 .htotal = 1024 + 24 + 63 + 1, 3019 .vdisplay = 768, 3020 .vsync_start = 768 + 3, 3021 .vsync_end = 768 + 3 + 6, 3022 .vtotal = 768 + 3 + 6 + 1, 3023 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3024 }; 3025 3026 static const struct panel_desc mitsubishi_aa084xe01 = { 3027 .modes = &mitsubishi_aa084xe01_mode, 3028 .num_modes = 1, 3029 .bpc = 8, 3030 .size = { 3031 .width = 1024, 3032 .height = 768, 3033 }, 3034 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3035 .connector_type = DRM_MODE_CONNECTOR_DPI, 3036 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3037 }; 3038 3039 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3040 .pixelclock = { 29000000, 33000000, 38000000 }, 3041 .hactive = { 800, 800, 800 }, 3042 .hfront_porch = { 180, 210, 240 }, 3043 .hback_porch = { 16, 16, 16 }, 3044 .hsync_len = { 30, 30, 30 }, 3045 .vactive = { 480, 480, 480 }, 3046 .vfront_porch = { 12, 22, 32 }, 3047 .vback_porch = { 10, 10, 10 }, 3048 .vsync_len = { 13, 13, 13 }, 3049 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3050 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3051 DISPLAY_FLAGS_SYNC_POSEDGE, 3052 }; 3053 3054 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3055 .timings = &multi_inno_mi0700s4t_6_timing, 3056 .num_timings = 1, 3057 .bpc = 8, 3058 .size = { 3059 .width = 154, 3060 .height = 86, 3061 }, 3062 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3063 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3064 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3065 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3066 .connector_type = DRM_MODE_CONNECTOR_DPI, 3067 }; 3068 3069 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3070 .pixelclock = { 32000000, 40000000, 50000000 }, 3071 .hactive = { 800, 800, 800 }, 3072 .hfront_porch = { 16, 210, 354 }, 3073 .hback_porch = { 6, 26, 45 }, 3074 .hsync_len = { 1, 20, 40 }, 3075 .vactive = { 600, 600, 600 }, 3076 .vfront_porch = { 1, 12, 77 }, 3077 .vback_porch = { 3, 13, 22 }, 3078 .vsync_len = { 1, 10, 20 }, 3079 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3080 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3081 DISPLAY_FLAGS_SYNC_POSEDGE, 3082 }; 3083 3084 static const struct panel_desc multi_inno_mi0800ft_9 = { 3085 .timings = &multi_inno_mi0800ft_9_timing, 3086 .num_timings = 1, 3087 .bpc = 8, 3088 .size = { 3089 .width = 162, 3090 .height = 122, 3091 }, 3092 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3093 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3094 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3095 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3096 .connector_type = DRM_MODE_CONNECTOR_DPI, 3097 }; 3098 3099 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3100 .pixelclock = { 68900000, 70000000, 73400000 }, 3101 .hactive = { 1280, 1280, 1280 }, 3102 .hfront_porch = { 30, 60, 71 }, 3103 .hback_porch = { 30, 60, 71 }, 3104 .hsync_len = { 10, 10, 48 }, 3105 .vactive = { 800, 800, 800 }, 3106 .vfront_porch = { 5, 10, 10 }, 3107 .vback_porch = { 5, 10, 10 }, 3108 .vsync_len = { 5, 6, 13 }, 3109 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3110 DISPLAY_FLAGS_DE_HIGH, 3111 }; 3112 3113 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3114 .timings = &multi_inno_mi1010ait_1cp_timing, 3115 .num_timings = 1, 3116 .bpc = 8, 3117 .size = { 3118 .width = 217, 3119 .height = 136, 3120 }, 3121 .delay = { 3122 .enable = 50, 3123 .disable = 50, 3124 }, 3125 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3126 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3127 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3128 }; 3129 3130 static const struct display_timing nec_nl12880bc20_05_timing = { 3131 .pixelclock = { 67000000, 71000000, 75000000 }, 3132 .hactive = { 1280, 1280, 1280 }, 3133 .hfront_porch = { 2, 30, 30 }, 3134 .hback_porch = { 6, 100, 100 }, 3135 .hsync_len = { 2, 30, 30 }, 3136 .vactive = { 800, 800, 800 }, 3137 .vfront_porch = { 5, 5, 5 }, 3138 .vback_porch = { 11, 11, 11 }, 3139 .vsync_len = { 7, 7, 7 }, 3140 }; 3141 3142 static const struct panel_desc nec_nl12880bc20_05 = { 3143 .timings = &nec_nl12880bc20_05_timing, 3144 .num_timings = 1, 3145 .bpc = 8, 3146 .size = { 3147 .width = 261, 3148 .height = 163, 3149 }, 3150 .delay = { 3151 .enable = 50, 3152 .disable = 50, 3153 }, 3154 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3155 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3156 }; 3157 3158 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3159 .clock = 10870, 3160 .hdisplay = 480, 3161 .hsync_start = 480 + 2, 3162 .hsync_end = 480 + 2 + 41, 3163 .htotal = 480 + 2 + 41 + 2, 3164 .vdisplay = 272, 3165 .vsync_start = 272 + 2, 3166 .vsync_end = 272 + 2 + 4, 3167 .vtotal = 272 + 2 + 4 + 2, 3168 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3169 }; 3170 3171 static const struct panel_desc nec_nl4827hc19_05b = { 3172 .modes = &nec_nl4827hc19_05b_mode, 3173 .num_modes = 1, 3174 .bpc = 8, 3175 .size = { 3176 .width = 95, 3177 .height = 54, 3178 }, 3179 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3180 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3181 }; 3182 3183 static const struct drm_display_mode netron_dy_e231732_mode = { 3184 .clock = 66000, 3185 .hdisplay = 1024, 3186 .hsync_start = 1024 + 160, 3187 .hsync_end = 1024 + 160 + 70, 3188 .htotal = 1024 + 160 + 70 + 90, 3189 .vdisplay = 600, 3190 .vsync_start = 600 + 127, 3191 .vsync_end = 600 + 127 + 20, 3192 .vtotal = 600 + 127 + 20 + 3, 3193 }; 3194 3195 static const struct panel_desc netron_dy_e231732 = { 3196 .modes = &netron_dy_e231732_mode, 3197 .num_modes = 1, 3198 .size = { 3199 .width = 154, 3200 .height = 87, 3201 }, 3202 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3203 }; 3204 3205 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3206 .clock = 9000, 3207 .hdisplay = 480, 3208 .hsync_start = 480 + 2, 3209 .hsync_end = 480 + 2 + 41, 3210 .htotal = 480 + 2 + 41 + 2, 3211 .vdisplay = 272, 3212 .vsync_start = 272 + 2, 3213 .vsync_end = 272 + 2 + 10, 3214 .vtotal = 272 + 2 + 10 + 2, 3215 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3216 }; 3217 3218 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3219 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3220 .num_modes = 1, 3221 .bpc = 8, 3222 .size = { 3223 .width = 95, 3224 .height = 54, 3225 }, 3226 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3227 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3228 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3229 .connector_type = DRM_MODE_CONNECTOR_DPI, 3230 }; 3231 3232 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3233 .pixelclock = { 130000000, 148350000, 163000000 }, 3234 .hactive = { 1920, 1920, 1920 }, 3235 .hfront_porch = { 80, 100, 100 }, 3236 .hback_porch = { 100, 120, 120 }, 3237 .hsync_len = { 50, 60, 60 }, 3238 .vactive = { 1080, 1080, 1080 }, 3239 .vfront_porch = { 12, 30, 30 }, 3240 .vback_porch = { 4, 10, 10 }, 3241 .vsync_len = { 4, 5, 5 }, 3242 }; 3243 3244 static const struct panel_desc nlt_nl192108ac18_02d = { 3245 .timings = &nlt_nl192108ac18_02d_timing, 3246 .num_timings = 1, 3247 .bpc = 8, 3248 .size = { 3249 .width = 344, 3250 .height = 194, 3251 }, 3252 .delay = { 3253 .unprepare = 500, 3254 }, 3255 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3256 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3257 }; 3258 3259 static const struct drm_display_mode nvd_9128_mode = { 3260 .clock = 29500, 3261 .hdisplay = 800, 3262 .hsync_start = 800 + 130, 3263 .hsync_end = 800 + 130 + 98, 3264 .htotal = 800 + 0 + 130 + 98, 3265 .vdisplay = 480, 3266 .vsync_start = 480 + 10, 3267 .vsync_end = 480 + 10 + 50, 3268 .vtotal = 480 + 0 + 10 + 50, 3269 }; 3270 3271 static const struct panel_desc nvd_9128 = { 3272 .modes = &nvd_9128_mode, 3273 .num_modes = 1, 3274 .bpc = 8, 3275 .size = { 3276 .width = 156, 3277 .height = 88, 3278 }, 3279 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3280 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3281 }; 3282 3283 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3284 .pixelclock = { 30000000, 30000000, 40000000 }, 3285 .hactive = { 800, 800, 800 }, 3286 .hfront_porch = { 40, 40, 40 }, 3287 .hback_porch = { 40, 40, 40 }, 3288 .hsync_len = { 1, 48, 48 }, 3289 .vactive = { 480, 480, 480 }, 3290 .vfront_porch = { 13, 13, 13 }, 3291 .vback_porch = { 29, 29, 29 }, 3292 .vsync_len = { 3, 3, 3 }, 3293 .flags = DISPLAY_FLAGS_DE_HIGH, 3294 }; 3295 3296 static const struct panel_desc okaya_rs800480t_7x0gp = { 3297 .timings = &okaya_rs800480t_7x0gp_timing, 3298 .num_timings = 1, 3299 .bpc = 6, 3300 .size = { 3301 .width = 154, 3302 .height = 87, 3303 }, 3304 .delay = { 3305 .prepare = 41, 3306 .enable = 50, 3307 .unprepare = 41, 3308 .disable = 50, 3309 }, 3310 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3311 }; 3312 3313 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3314 .clock = 9000, 3315 .hdisplay = 480, 3316 .hsync_start = 480 + 5, 3317 .hsync_end = 480 + 5 + 30, 3318 .htotal = 480 + 5 + 30 + 10, 3319 .vdisplay = 272, 3320 .vsync_start = 272 + 8, 3321 .vsync_end = 272 + 8 + 5, 3322 .vtotal = 272 + 8 + 5 + 3, 3323 }; 3324 3325 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3326 .modes = &olimex_lcd_olinuxino_43ts_mode, 3327 .num_modes = 1, 3328 .size = { 3329 .width = 95, 3330 .height = 54, 3331 }, 3332 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3333 }; 3334 3335 /* 3336 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3337 * pixel clocks, but this is the timing that was being used in the Adafruit 3338 * installation instructions. 3339 */ 3340 static const struct drm_display_mode ontat_yx700wv03_mode = { 3341 .clock = 29500, 3342 .hdisplay = 800, 3343 .hsync_start = 824, 3344 .hsync_end = 896, 3345 .htotal = 992, 3346 .vdisplay = 480, 3347 .vsync_start = 483, 3348 .vsync_end = 493, 3349 .vtotal = 500, 3350 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3351 }; 3352 3353 /* 3354 * Specification at: 3355 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3356 */ 3357 static const struct panel_desc ontat_yx700wv03 = { 3358 .modes = &ontat_yx700wv03_mode, 3359 .num_modes = 1, 3360 .bpc = 8, 3361 .size = { 3362 .width = 154, 3363 .height = 83, 3364 }, 3365 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3366 }; 3367 3368 static const struct drm_display_mode ortustech_com37h3m_mode = { 3369 .clock = 22230, 3370 .hdisplay = 480, 3371 .hsync_start = 480 + 40, 3372 .hsync_end = 480 + 40 + 10, 3373 .htotal = 480 + 40 + 10 + 40, 3374 .vdisplay = 640, 3375 .vsync_start = 640 + 4, 3376 .vsync_end = 640 + 4 + 2, 3377 .vtotal = 640 + 4 + 2 + 4, 3378 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3379 }; 3380 3381 static const struct panel_desc ortustech_com37h3m = { 3382 .modes = &ortustech_com37h3m_mode, 3383 .num_modes = 1, 3384 .bpc = 8, 3385 .size = { 3386 .width = 56, /* 56.16mm */ 3387 .height = 75, /* 74.88mm */ 3388 }, 3389 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3390 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3391 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3392 }; 3393 3394 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3395 .clock = 25000, 3396 .hdisplay = 480, 3397 .hsync_start = 480 + 10, 3398 .hsync_end = 480 + 10 + 10, 3399 .htotal = 480 + 10 + 10 + 15, 3400 .vdisplay = 800, 3401 .vsync_start = 800 + 3, 3402 .vsync_end = 800 + 3 + 3, 3403 .vtotal = 800 + 3 + 3 + 3, 3404 }; 3405 3406 static const struct panel_desc ortustech_com43h4m85ulc = { 3407 .modes = &ortustech_com43h4m85ulc_mode, 3408 .num_modes = 1, 3409 .bpc = 6, 3410 .size = { 3411 .width = 56, 3412 .height = 93, 3413 }, 3414 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3415 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3416 .connector_type = DRM_MODE_CONNECTOR_DPI, 3417 }; 3418 3419 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3420 .clock = 33000, 3421 .hdisplay = 800, 3422 .hsync_start = 800 + 210, 3423 .hsync_end = 800 + 210 + 30, 3424 .htotal = 800 + 210 + 30 + 16, 3425 .vdisplay = 480, 3426 .vsync_start = 480 + 22, 3427 .vsync_end = 480 + 22 + 13, 3428 .vtotal = 480 + 22 + 13 + 10, 3429 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3430 }; 3431 3432 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3433 .modes = &osddisplays_osd070t1718_19ts_mode, 3434 .num_modes = 1, 3435 .bpc = 8, 3436 .size = { 3437 .width = 152, 3438 .height = 91, 3439 }, 3440 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3441 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3442 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3443 .connector_type = DRM_MODE_CONNECTOR_DPI, 3444 }; 3445 3446 static const struct drm_display_mode pda_91_00156_a0_mode = { 3447 .clock = 33300, 3448 .hdisplay = 800, 3449 .hsync_start = 800 + 1, 3450 .hsync_end = 800 + 1 + 64, 3451 .htotal = 800 + 1 + 64 + 64, 3452 .vdisplay = 480, 3453 .vsync_start = 480 + 1, 3454 .vsync_end = 480 + 1 + 23, 3455 .vtotal = 480 + 1 + 23 + 22, 3456 }; 3457 3458 static const struct panel_desc pda_91_00156_a0 = { 3459 .modes = &pda_91_00156_a0_mode, 3460 .num_modes = 1, 3461 .size = { 3462 .width = 152, 3463 .height = 91, 3464 }, 3465 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3466 }; 3467 3468 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3469 .clock = 24750, 3470 .hdisplay = 800, 3471 .hsync_start = 800 + 54, 3472 .hsync_end = 800 + 54 + 2, 3473 .htotal = 800 + 54 + 2 + 44, 3474 .vdisplay = 480, 3475 .vsync_start = 480 + 49, 3476 .vsync_end = 480 + 49 + 2, 3477 .vtotal = 480 + 49 + 2 + 22, 3478 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3479 }; 3480 3481 static const struct panel_desc powertip_ph800480t013_idf02 = { 3482 .modes = &powertip_ph800480t013_idf02_mode, 3483 .num_modes = 1, 3484 .bpc = 8, 3485 .size = { 3486 .width = 152, 3487 .height = 91, 3488 }, 3489 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3490 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3491 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3492 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3493 .connector_type = DRM_MODE_CONNECTOR_DPI, 3494 }; 3495 3496 static const struct drm_display_mode qd43003c0_40_mode = { 3497 .clock = 9000, 3498 .hdisplay = 480, 3499 .hsync_start = 480 + 8, 3500 .hsync_end = 480 + 8 + 4, 3501 .htotal = 480 + 8 + 4 + 39, 3502 .vdisplay = 272, 3503 .vsync_start = 272 + 4, 3504 .vsync_end = 272 + 4 + 10, 3505 .vtotal = 272 + 4 + 10 + 2, 3506 }; 3507 3508 static const struct panel_desc qd43003c0_40 = { 3509 .modes = &qd43003c0_40_mode, 3510 .num_modes = 1, 3511 .bpc = 8, 3512 .size = { 3513 .width = 95, 3514 .height = 53, 3515 }, 3516 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3517 }; 3518 3519 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3520 { /* 60 Hz */ 3521 .clock = 10800, 3522 .hdisplay = 480, 3523 .hsync_start = 480 + 77, 3524 .hsync_end = 480 + 77 + 41, 3525 .htotal = 480 + 77 + 41 + 2, 3526 .vdisplay = 272, 3527 .vsync_start = 272 + 16, 3528 .vsync_end = 272 + 16 + 10, 3529 .vtotal = 272 + 16 + 10 + 2, 3530 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3531 }, 3532 { /* 50 Hz */ 3533 .clock = 10800, 3534 .hdisplay = 480, 3535 .hsync_start = 480 + 17, 3536 .hsync_end = 480 + 17 + 41, 3537 .htotal = 480 + 17 + 41 + 2, 3538 .vdisplay = 272, 3539 .vsync_start = 272 + 116, 3540 .vsync_end = 272 + 116 + 10, 3541 .vtotal = 272 + 116 + 10 + 2, 3542 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3543 }, 3544 }; 3545 3546 static const struct panel_desc qishenglong_gopher2b_lcd = { 3547 .modes = qishenglong_gopher2b_lcd_modes, 3548 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3549 .bpc = 8, 3550 .size = { 3551 .width = 95, 3552 .height = 54, 3553 }, 3554 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3555 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3556 .connector_type = DRM_MODE_CONNECTOR_DPI, 3557 }; 3558 3559 static const struct display_timing rocktech_rk043fn48h_timing = { 3560 .pixelclock = { 6000000, 9000000, 12000000 }, 3561 .hactive = { 480, 480, 480 }, 3562 .hback_porch = { 8, 43, 43 }, 3563 .hfront_porch = { 2, 8, 10 }, 3564 .hsync_len = { 1, 1, 1 }, 3565 .vactive = { 272, 272, 272 }, 3566 .vback_porch = { 2, 12, 26 }, 3567 .vfront_porch = { 1, 4, 4 }, 3568 .vsync_len = { 1, 10, 10 }, 3569 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3570 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3571 DISPLAY_FLAGS_SYNC_POSEDGE, 3572 }; 3573 3574 static const struct panel_desc rocktech_rk043fn48h = { 3575 .timings = &rocktech_rk043fn48h_timing, 3576 .num_timings = 1, 3577 .bpc = 8, 3578 .size = { 3579 .width = 95, 3580 .height = 54, 3581 }, 3582 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3583 .connector_type = DRM_MODE_CONNECTOR_DPI, 3584 }; 3585 3586 static const struct display_timing rocktech_rk070er9427_timing = { 3587 .pixelclock = { 26400000, 33300000, 46800000 }, 3588 .hactive = { 800, 800, 800 }, 3589 .hfront_porch = { 16, 210, 354 }, 3590 .hback_porch = { 46, 46, 46 }, 3591 .hsync_len = { 1, 1, 1 }, 3592 .vactive = { 480, 480, 480 }, 3593 .vfront_porch = { 7, 22, 147 }, 3594 .vback_porch = { 23, 23, 23 }, 3595 .vsync_len = { 1, 1, 1 }, 3596 .flags = DISPLAY_FLAGS_DE_HIGH, 3597 }; 3598 3599 static const struct panel_desc rocktech_rk070er9427 = { 3600 .timings = &rocktech_rk070er9427_timing, 3601 .num_timings = 1, 3602 .bpc = 6, 3603 .size = { 3604 .width = 154, 3605 .height = 86, 3606 }, 3607 .delay = { 3608 .prepare = 41, 3609 .enable = 50, 3610 .unprepare = 41, 3611 .disable = 50, 3612 }, 3613 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3614 }; 3615 3616 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3617 .clock = 71100, 3618 .hdisplay = 1280, 3619 .hsync_start = 1280 + 48, 3620 .hsync_end = 1280 + 48 + 32, 3621 .htotal = 1280 + 48 + 32 + 80, 3622 .vdisplay = 800, 3623 .vsync_start = 800 + 2, 3624 .vsync_end = 800 + 2 + 5, 3625 .vtotal = 800 + 2 + 5 + 16, 3626 }; 3627 3628 static const struct panel_desc rocktech_rk101ii01d_ct = { 3629 .modes = &rocktech_rk101ii01d_ct_mode, 3630 .bpc = 8, 3631 .num_modes = 1, 3632 .size = { 3633 .width = 217, 3634 .height = 136, 3635 }, 3636 .delay = { 3637 .prepare = 50, 3638 .disable = 50, 3639 }, 3640 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3641 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3642 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3643 }; 3644 3645 static const struct display_timing samsung_ltl101al01_timing = { 3646 .pixelclock = { 66663000, 66663000, 66663000 }, 3647 .hactive = { 1280, 1280, 1280 }, 3648 .hfront_porch = { 18, 18, 18 }, 3649 .hback_porch = { 36, 36, 36 }, 3650 .hsync_len = { 16, 16, 16 }, 3651 .vactive = { 800, 800, 800 }, 3652 .vfront_porch = { 4, 4, 4 }, 3653 .vback_porch = { 16, 16, 16 }, 3654 .vsync_len = { 3, 3, 3 }, 3655 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3656 }; 3657 3658 static const struct panel_desc samsung_ltl101al01 = { 3659 .timings = &samsung_ltl101al01_timing, 3660 .num_timings = 1, 3661 .bpc = 8, 3662 .size = { 3663 .width = 217, 3664 .height = 135, 3665 }, 3666 .delay = { 3667 .prepare = 40, 3668 .enable = 300, 3669 .disable = 200, 3670 .unprepare = 600, 3671 }, 3672 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3673 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3674 }; 3675 3676 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3677 .clock = 54030, 3678 .hdisplay = 1024, 3679 .hsync_start = 1024 + 24, 3680 .hsync_end = 1024 + 24 + 136, 3681 .htotal = 1024 + 24 + 136 + 160, 3682 .vdisplay = 600, 3683 .vsync_start = 600 + 3, 3684 .vsync_end = 600 + 3 + 6, 3685 .vtotal = 600 + 3 + 6 + 61, 3686 }; 3687 3688 static const struct panel_desc samsung_ltn101nt05 = { 3689 .modes = &samsung_ltn101nt05_mode, 3690 .num_modes = 1, 3691 .bpc = 6, 3692 .size = { 3693 .width = 223, 3694 .height = 125, 3695 }, 3696 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3697 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3698 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3699 }; 3700 3701 static const struct display_timing satoz_sat050at40h12r2_timing = { 3702 .pixelclock = {33300000, 33300000, 50000000}, 3703 .hactive = {800, 800, 800}, 3704 .hfront_porch = {16, 210, 354}, 3705 .hback_porch = {46, 46, 46}, 3706 .hsync_len = {1, 1, 40}, 3707 .vactive = {480, 480, 480}, 3708 .vfront_porch = {7, 22, 147}, 3709 .vback_porch = {23, 23, 23}, 3710 .vsync_len = {1, 1, 20}, 3711 }; 3712 3713 static const struct panel_desc satoz_sat050at40h12r2 = { 3714 .timings = &satoz_sat050at40h12r2_timing, 3715 .num_timings = 1, 3716 .bpc = 8, 3717 .size = { 3718 .width = 108, 3719 .height = 65, 3720 }, 3721 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3722 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3723 }; 3724 3725 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3726 .clock = 33260, 3727 .hdisplay = 800, 3728 .hsync_start = 800 + 64, 3729 .hsync_end = 800 + 64 + 128, 3730 .htotal = 800 + 64 + 128 + 64, 3731 .vdisplay = 480, 3732 .vsync_start = 480 + 8, 3733 .vsync_end = 480 + 8 + 2, 3734 .vtotal = 480 + 8 + 2 + 35, 3735 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3736 }; 3737 3738 static const struct panel_desc sharp_lq070y3dg3b = { 3739 .modes = &sharp_lq070y3dg3b_mode, 3740 .num_modes = 1, 3741 .bpc = 8, 3742 .size = { 3743 .width = 152, /* 152.4mm */ 3744 .height = 91, /* 91.4mm */ 3745 }, 3746 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3747 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3748 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3749 }; 3750 3751 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3752 .clock = 5500, 3753 .hdisplay = 240, 3754 .hsync_start = 240 + 16, 3755 .hsync_end = 240 + 16 + 7, 3756 .htotal = 240 + 16 + 7 + 5, 3757 .vdisplay = 320, 3758 .vsync_start = 320 + 9, 3759 .vsync_end = 320 + 9 + 1, 3760 .vtotal = 320 + 9 + 1 + 7, 3761 }; 3762 3763 static const struct panel_desc sharp_lq035q7db03 = { 3764 .modes = &sharp_lq035q7db03_mode, 3765 .num_modes = 1, 3766 .bpc = 6, 3767 .size = { 3768 .width = 54, 3769 .height = 72, 3770 }, 3771 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3772 }; 3773 3774 static const struct display_timing sharp_lq101k1ly04_timing = { 3775 .pixelclock = { 60000000, 65000000, 80000000 }, 3776 .hactive = { 1280, 1280, 1280 }, 3777 .hfront_porch = { 20, 20, 20 }, 3778 .hback_porch = { 20, 20, 20 }, 3779 .hsync_len = { 10, 10, 10 }, 3780 .vactive = { 800, 800, 800 }, 3781 .vfront_porch = { 4, 4, 4 }, 3782 .vback_porch = { 4, 4, 4 }, 3783 .vsync_len = { 4, 4, 4 }, 3784 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3785 }; 3786 3787 static const struct panel_desc sharp_lq101k1ly04 = { 3788 .timings = &sharp_lq101k1ly04_timing, 3789 .num_timings = 1, 3790 .bpc = 8, 3791 .size = { 3792 .width = 217, 3793 .height = 136, 3794 }, 3795 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3796 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3797 }; 3798 3799 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3800 { /* 50 Hz */ 3801 .clock = 3000, 3802 .hdisplay = 240, 3803 .hsync_start = 240 + 58, 3804 .hsync_end = 240 + 58 + 1, 3805 .htotal = 240 + 58 + 1 + 1, 3806 .vdisplay = 160, 3807 .vsync_start = 160 + 24, 3808 .vsync_end = 160 + 24 + 10, 3809 .vtotal = 160 + 24 + 10 + 6, 3810 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3811 }, 3812 { /* 60 Hz */ 3813 .clock = 3000, 3814 .hdisplay = 240, 3815 .hsync_start = 240 + 8, 3816 .hsync_end = 240 + 8 + 1, 3817 .htotal = 240 + 8 + 1 + 1, 3818 .vdisplay = 160, 3819 .vsync_start = 160 + 24, 3820 .vsync_end = 160 + 24 + 10, 3821 .vtotal = 160 + 24 + 10 + 6, 3822 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3823 }, 3824 }; 3825 3826 static const struct panel_desc sharp_ls020b1dd01d = { 3827 .modes = sharp_ls020b1dd01d_modes, 3828 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3829 .bpc = 6, 3830 .size = { 3831 .width = 42, 3832 .height = 28, 3833 }, 3834 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3835 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3836 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3837 | DRM_BUS_FLAG_SHARP_SIGNALS, 3838 }; 3839 3840 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3841 .clock = 33300, 3842 .hdisplay = 800, 3843 .hsync_start = 800 + 1, 3844 .hsync_end = 800 + 1 + 64, 3845 .htotal = 800 + 1 + 64 + 64, 3846 .vdisplay = 480, 3847 .vsync_start = 480 + 1, 3848 .vsync_end = 480 + 1 + 23, 3849 .vtotal = 480 + 1 + 23 + 22, 3850 }; 3851 3852 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3853 .modes = &shelly_sca07010_bfn_lnn_mode, 3854 .num_modes = 1, 3855 .size = { 3856 .width = 152, 3857 .height = 91, 3858 }, 3859 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3860 }; 3861 3862 static const struct drm_display_mode starry_kr070pe2t_mode = { 3863 .clock = 33000, 3864 .hdisplay = 800, 3865 .hsync_start = 800 + 209, 3866 .hsync_end = 800 + 209 + 1, 3867 .htotal = 800 + 209 + 1 + 45, 3868 .vdisplay = 480, 3869 .vsync_start = 480 + 22, 3870 .vsync_end = 480 + 22 + 1, 3871 .vtotal = 480 + 22 + 1 + 22, 3872 }; 3873 3874 static const struct panel_desc starry_kr070pe2t = { 3875 .modes = &starry_kr070pe2t_mode, 3876 .num_modes = 1, 3877 .bpc = 8, 3878 .size = { 3879 .width = 152, 3880 .height = 86, 3881 }, 3882 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3883 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3884 .connector_type = DRM_MODE_CONNECTOR_DPI, 3885 }; 3886 3887 static const struct display_timing startek_kd070wvfpa_mode = { 3888 .pixelclock = { 25200000, 27200000, 30500000 }, 3889 .hactive = { 800, 800, 800 }, 3890 .hfront_porch = { 19, 44, 115 }, 3891 .hback_porch = { 5, 16, 101 }, 3892 .hsync_len = { 1, 2, 100 }, 3893 .vactive = { 480, 480, 480 }, 3894 .vfront_porch = { 5, 43, 67 }, 3895 .vback_porch = { 5, 5, 67 }, 3896 .vsync_len = { 1, 2, 66 }, 3897 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3898 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3899 DISPLAY_FLAGS_SYNC_POSEDGE, 3900 }; 3901 3902 static const struct panel_desc startek_kd070wvfpa = { 3903 .timings = &startek_kd070wvfpa_mode, 3904 .num_timings = 1, 3905 .bpc = 8, 3906 .size = { 3907 .width = 152, 3908 .height = 91, 3909 }, 3910 .delay = { 3911 .prepare = 20, 3912 .enable = 200, 3913 .disable = 200, 3914 }, 3915 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3916 .connector_type = DRM_MODE_CONNECTOR_DPI, 3917 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3918 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3919 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3920 }; 3921 3922 static const struct display_timing tsd_tst043015cmhx_timing = { 3923 .pixelclock = { 5000000, 9000000, 12000000 }, 3924 .hactive = { 480, 480, 480 }, 3925 .hfront_porch = { 4, 5, 65 }, 3926 .hback_porch = { 36, 40, 255 }, 3927 .hsync_len = { 1, 1, 1 }, 3928 .vactive = { 272, 272, 272 }, 3929 .vfront_porch = { 2, 8, 97 }, 3930 .vback_porch = { 3, 8, 31 }, 3931 .vsync_len = { 1, 1, 1 }, 3932 3933 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3934 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3935 }; 3936 3937 static const struct panel_desc tsd_tst043015cmhx = { 3938 .timings = &tsd_tst043015cmhx_timing, 3939 .num_timings = 1, 3940 .bpc = 8, 3941 .size = { 3942 .width = 105, 3943 .height = 67, 3944 }, 3945 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3946 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3947 }; 3948 3949 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3950 .clock = 30000, 3951 .hdisplay = 800, 3952 .hsync_start = 800 + 39, 3953 .hsync_end = 800 + 39 + 47, 3954 .htotal = 800 + 39 + 47 + 39, 3955 .vdisplay = 480, 3956 .vsync_start = 480 + 13, 3957 .vsync_end = 480 + 13 + 2, 3958 .vtotal = 480 + 13 + 2 + 29, 3959 }; 3960 3961 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3962 .modes = &tfc_s9700rtwv43tr_01b_mode, 3963 .num_modes = 1, 3964 .bpc = 8, 3965 .size = { 3966 .width = 155, 3967 .height = 90, 3968 }, 3969 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3970 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3971 }; 3972 3973 static const struct display_timing tianma_tm070jdhg30_timing = { 3974 .pixelclock = { 62600000, 68200000, 78100000 }, 3975 .hactive = { 1280, 1280, 1280 }, 3976 .hfront_porch = { 15, 64, 159 }, 3977 .hback_porch = { 5, 5, 5 }, 3978 .hsync_len = { 1, 1, 256 }, 3979 .vactive = { 800, 800, 800 }, 3980 .vfront_porch = { 3, 40, 99 }, 3981 .vback_porch = { 2, 2, 2 }, 3982 .vsync_len = { 1, 1, 128 }, 3983 .flags = DISPLAY_FLAGS_DE_HIGH, 3984 }; 3985 3986 static const struct panel_desc tianma_tm070jdhg30 = { 3987 .timings = &tianma_tm070jdhg30_timing, 3988 .num_timings = 1, 3989 .bpc = 8, 3990 .size = { 3991 .width = 151, 3992 .height = 95, 3993 }, 3994 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3995 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3996 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3997 }; 3998 3999 static const struct panel_desc tianma_tm070jvhg33 = { 4000 .timings = &tianma_tm070jdhg30_timing, 4001 .num_timings = 1, 4002 .bpc = 8, 4003 .size = { 4004 .width = 150, 4005 .height = 94, 4006 }, 4007 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4008 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4009 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4010 }; 4011 4012 static const struct display_timing tianma_tm070rvhg71_timing = { 4013 .pixelclock = { 27700000, 29200000, 39600000 }, 4014 .hactive = { 800, 800, 800 }, 4015 .hfront_porch = { 12, 40, 212 }, 4016 .hback_porch = { 88, 88, 88 }, 4017 .hsync_len = { 1, 1, 40 }, 4018 .vactive = { 480, 480, 480 }, 4019 .vfront_porch = { 1, 13, 88 }, 4020 .vback_porch = { 32, 32, 32 }, 4021 .vsync_len = { 1, 1, 3 }, 4022 .flags = DISPLAY_FLAGS_DE_HIGH, 4023 }; 4024 4025 static const struct panel_desc tianma_tm070rvhg71 = { 4026 .timings = &tianma_tm070rvhg71_timing, 4027 .num_timings = 1, 4028 .bpc = 8, 4029 .size = { 4030 .width = 154, 4031 .height = 86, 4032 }, 4033 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4034 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4035 }; 4036 4037 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4038 { 4039 .clock = 10000, 4040 .hdisplay = 320, 4041 .hsync_start = 320 + 50, 4042 .hsync_end = 320 + 50 + 6, 4043 .htotal = 320 + 50 + 6 + 38, 4044 .vdisplay = 240, 4045 .vsync_start = 240 + 3, 4046 .vsync_end = 240 + 3 + 1, 4047 .vtotal = 240 + 3 + 1 + 17, 4048 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4049 }, 4050 }; 4051 4052 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4053 .modes = ti_nspire_cx_lcd_mode, 4054 .num_modes = 1, 4055 .bpc = 8, 4056 .size = { 4057 .width = 65, 4058 .height = 49, 4059 }, 4060 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4061 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4062 }; 4063 4064 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4065 { 4066 .clock = 10000, 4067 .hdisplay = 320, 4068 .hsync_start = 320 + 6, 4069 .hsync_end = 320 + 6 + 6, 4070 .htotal = 320 + 6 + 6 + 6, 4071 .vdisplay = 240, 4072 .vsync_start = 240 + 0, 4073 .vsync_end = 240 + 0 + 1, 4074 .vtotal = 240 + 0 + 1 + 0, 4075 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4076 }, 4077 }; 4078 4079 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4080 .modes = ti_nspire_classic_lcd_mode, 4081 .num_modes = 1, 4082 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4083 .bpc = 8, 4084 .size = { 4085 .width = 71, 4086 .height = 53, 4087 }, 4088 /* This is the grayscale bus format */ 4089 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4090 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4091 }; 4092 4093 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4094 .clock = 79500, 4095 .hdisplay = 1280, 4096 .hsync_start = 1280 + 192, 4097 .hsync_end = 1280 + 192 + 128, 4098 .htotal = 1280 + 192 + 128 + 64, 4099 .vdisplay = 768, 4100 .vsync_start = 768 + 20, 4101 .vsync_end = 768 + 20 + 7, 4102 .vtotal = 768 + 20 + 7 + 3, 4103 }; 4104 4105 static const struct panel_desc toshiba_lt089ac29000 = { 4106 .modes = &toshiba_lt089ac29000_mode, 4107 .num_modes = 1, 4108 .size = { 4109 .width = 194, 4110 .height = 116, 4111 }, 4112 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4113 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4114 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4115 }; 4116 4117 static const struct drm_display_mode tpk_f07a_0102_mode = { 4118 .clock = 33260, 4119 .hdisplay = 800, 4120 .hsync_start = 800 + 40, 4121 .hsync_end = 800 + 40 + 128, 4122 .htotal = 800 + 40 + 128 + 88, 4123 .vdisplay = 480, 4124 .vsync_start = 480 + 10, 4125 .vsync_end = 480 + 10 + 2, 4126 .vtotal = 480 + 10 + 2 + 33, 4127 }; 4128 4129 static const struct panel_desc tpk_f07a_0102 = { 4130 .modes = &tpk_f07a_0102_mode, 4131 .num_modes = 1, 4132 .size = { 4133 .width = 152, 4134 .height = 91, 4135 }, 4136 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4137 }; 4138 4139 static const struct drm_display_mode tpk_f10a_0102_mode = { 4140 .clock = 45000, 4141 .hdisplay = 1024, 4142 .hsync_start = 1024 + 176, 4143 .hsync_end = 1024 + 176 + 5, 4144 .htotal = 1024 + 176 + 5 + 88, 4145 .vdisplay = 600, 4146 .vsync_start = 600 + 20, 4147 .vsync_end = 600 + 20 + 5, 4148 .vtotal = 600 + 20 + 5 + 25, 4149 }; 4150 4151 static const struct panel_desc tpk_f10a_0102 = { 4152 .modes = &tpk_f10a_0102_mode, 4153 .num_modes = 1, 4154 .size = { 4155 .width = 223, 4156 .height = 125, 4157 }, 4158 }; 4159 4160 static const struct display_timing urt_umsh_8596md_timing = { 4161 .pixelclock = { 33260000, 33260000, 33260000 }, 4162 .hactive = { 800, 800, 800 }, 4163 .hfront_porch = { 41, 41, 41 }, 4164 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4165 .hsync_len = { 71, 128, 128 }, 4166 .vactive = { 480, 480, 480 }, 4167 .vfront_porch = { 10, 10, 10 }, 4168 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4169 .vsync_len = { 2, 2, 2 }, 4170 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4171 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4172 }; 4173 4174 static const struct panel_desc urt_umsh_8596md_lvds = { 4175 .timings = &urt_umsh_8596md_timing, 4176 .num_timings = 1, 4177 .bpc = 6, 4178 .size = { 4179 .width = 152, 4180 .height = 91, 4181 }, 4182 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4183 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4184 }; 4185 4186 static const struct panel_desc urt_umsh_8596md_parallel = { 4187 .timings = &urt_umsh_8596md_timing, 4188 .num_timings = 1, 4189 .bpc = 6, 4190 .size = { 4191 .width = 152, 4192 .height = 91, 4193 }, 4194 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4195 }; 4196 4197 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4198 .clock = 60000, 4199 .hdisplay = 1024, 4200 .hsync_start = 1024 + 160, 4201 .hsync_end = 1024 + 160 + 100, 4202 .htotal = 1024 + 160 + 100 + 60, 4203 .vdisplay = 600, 4204 .vsync_start = 600 + 12, 4205 .vsync_end = 600 + 12 + 10, 4206 .vtotal = 600 + 12 + 10 + 13, 4207 }; 4208 4209 static const struct panel_desc vivax_tpc9150_panel = { 4210 .modes = &vivax_tpc9150_panel_mode, 4211 .num_modes = 1, 4212 .bpc = 6, 4213 .size = { 4214 .width = 200, 4215 .height = 115, 4216 }, 4217 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4218 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4219 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4220 }; 4221 4222 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4223 .clock = 33333, 4224 .hdisplay = 800, 4225 .hsync_start = 800 + 210, 4226 .hsync_end = 800 + 210 + 20, 4227 .htotal = 800 + 210 + 20 + 46, 4228 .vdisplay = 480, 4229 .vsync_start = 480 + 22, 4230 .vsync_end = 480 + 22 + 10, 4231 .vtotal = 480 + 22 + 10 + 23, 4232 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4233 }; 4234 4235 static const struct panel_desc vl050_8048nt_c01 = { 4236 .modes = &vl050_8048nt_c01_mode, 4237 .num_modes = 1, 4238 .bpc = 8, 4239 .size = { 4240 .width = 120, 4241 .height = 76, 4242 }, 4243 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4244 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4245 }; 4246 4247 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4248 .clock = 6410, 4249 .hdisplay = 320, 4250 .hsync_start = 320 + 20, 4251 .hsync_end = 320 + 20 + 30, 4252 .htotal = 320 + 20 + 30 + 38, 4253 .vdisplay = 240, 4254 .vsync_start = 240 + 4, 4255 .vsync_end = 240 + 4 + 3, 4256 .vtotal = 240 + 4 + 3 + 15, 4257 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4258 }; 4259 4260 static const struct panel_desc winstar_wf35ltiacd = { 4261 .modes = &winstar_wf35ltiacd_mode, 4262 .num_modes = 1, 4263 .bpc = 8, 4264 .size = { 4265 .width = 70, 4266 .height = 53, 4267 }, 4268 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4269 }; 4270 4271 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4272 .clock = 51200, 4273 .hdisplay = 1024, 4274 .hsync_start = 1024 + 100, 4275 .hsync_end = 1024 + 100 + 100, 4276 .htotal = 1024 + 100 + 100 + 120, 4277 .vdisplay = 600, 4278 .vsync_start = 600 + 10, 4279 .vsync_end = 600 + 10 + 10, 4280 .vtotal = 600 + 10 + 10 + 15, 4281 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4282 }; 4283 4284 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4285 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4286 .num_modes = 1, 4287 .bpc = 8, 4288 .size = { 4289 .width = 154, 4290 .height = 90, 4291 }, 4292 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4293 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4294 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4295 }; 4296 4297 static const struct drm_display_mode arm_rtsm_mode[] = { 4298 { 4299 .clock = 65000, 4300 .hdisplay = 1024, 4301 .hsync_start = 1024 + 24, 4302 .hsync_end = 1024 + 24 + 136, 4303 .htotal = 1024 + 24 + 136 + 160, 4304 .vdisplay = 768, 4305 .vsync_start = 768 + 3, 4306 .vsync_end = 768 + 3 + 6, 4307 .vtotal = 768 + 3 + 6 + 29, 4308 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4309 }, 4310 }; 4311 4312 static const struct panel_desc arm_rtsm = { 4313 .modes = arm_rtsm_mode, 4314 .num_modes = 1, 4315 .bpc = 8, 4316 .size = { 4317 .width = 400, 4318 .height = 300, 4319 }, 4320 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4321 }; 4322 4323 static const struct of_device_id platform_of_match[] = { 4324 { 4325 .compatible = "ampire,am-1280800n3tzqw-t00h", 4326 .data = &ire_am_1280800n3tzqw_t00h, 4327 }, { 4328 .compatible = "ampire,am-480272h3tmqw-t01h", 4329 .data = &ire_am_480272h3tmqw_t01h, 4330 }, { 4331 .compatible = "ampire,am-800480l1tmqw-t00h", 4332 .data = &ire_am_800480l1tmqw_t00h, 4333 }, { 4334 .compatible = "ampire,am800480r3tmqwa1h", 4335 .data = &ire_am800480r3tmqwa1h, 4336 }, { 4337 .compatible = "ampire,am800600p5tmqw-tb8h", 4338 .data = &ire_am800600p5tmqwtb8h, 4339 }, { 4340 .compatible = "arm,rtsm-display", 4341 .data = &arm_rtsm, 4342 }, { 4343 .compatible = "armadeus,st0700-adapt", 4344 .data = &armadeus_st0700_adapt, 4345 }, { 4346 .compatible = "auo,b101aw03", 4347 .data = &auo_b101aw03, 4348 }, { 4349 .compatible = "auo,b101xtn01", 4350 .data = &auo_b101xtn01, 4351 }, { 4352 .compatible = "auo,b116xw03", 4353 .data = &auo_b116xw03, 4354 }, { 4355 .compatible = "auo,g070vvn01", 4356 .data = &auo_g070vvn01, 4357 }, { 4358 .compatible = "auo,g101evn010", 4359 .data = &auo_g101evn010, 4360 }, { 4361 .compatible = "auo,g104sn02", 4362 .data = &auo_g104sn02, 4363 }, { 4364 .compatible = "auo,g121ean01", 4365 .data = &auo_g121ean01, 4366 }, { 4367 .compatible = "auo,g133han01", 4368 .data = &auo_g133han01, 4369 }, { 4370 .compatible = "auo,g156han04", 4371 .data = &auo_g156han04, 4372 }, { 4373 .compatible = "auo,g156xtn01", 4374 .data = &auo_g156xtn01, 4375 }, { 4376 .compatible = "auo,g185han01", 4377 .data = &auo_g185han01, 4378 }, { 4379 .compatible = "auo,g190ean01", 4380 .data = &auo_g190ean01, 4381 }, { 4382 .compatible = "auo,p320hvn03", 4383 .data = &auo_p320hvn03, 4384 }, { 4385 .compatible = "auo,t215hvn01", 4386 .data = &auo_t215hvn01, 4387 }, { 4388 .compatible = "avic,tm070ddh03", 4389 .data = &avic_tm070ddh03, 4390 }, { 4391 .compatible = "bananapi,s070wv20-ct16", 4392 .data = &bananapi_s070wv20_ct16, 4393 }, { 4394 .compatible = "boe,bp082wx1-100", 4395 .data = &boe_bp082wx1_100, 4396 }, { 4397 .compatible = "boe,bp101wx1-100", 4398 .data = &boe_bp101wx1_100, 4399 }, { 4400 .compatible = "boe,ev121wxm-n10-1850", 4401 .data = &boe_ev121wxm_n10_1850, 4402 }, { 4403 .compatible = "boe,hv070wsa-100", 4404 .data = &boe_hv070wsa 4405 }, { 4406 .compatible = "cdtech,s043wq26h-ct7", 4407 .data = &cdtech_s043wq26h_ct7, 4408 }, { 4409 .compatible = "cdtech,s070pws19hp-fc21", 4410 .data = &cdtech_s070pws19hp_fc21, 4411 }, { 4412 .compatible = "cdtech,s070swv29hg-dc44", 4413 .data = &cdtech_s070swv29hg_dc44, 4414 }, { 4415 .compatible = "cdtech,s070wv95-ct16", 4416 .data = &cdtech_s070wv95_ct16, 4417 }, { 4418 .compatible = "chefree,ch101olhlwh-002", 4419 .data = &chefree_ch101olhlwh_002, 4420 }, { 4421 .compatible = "chunghwa,claa070wp03xg", 4422 .data = &chunghwa_claa070wp03xg, 4423 }, { 4424 .compatible = "chunghwa,claa101wa01a", 4425 .data = &chunghwa_claa101wa01a 4426 }, { 4427 .compatible = "chunghwa,claa101wb01", 4428 .data = &chunghwa_claa101wb01 4429 }, { 4430 .compatible = "dataimage,fg040346dsswbg04", 4431 .data = &dataimage_fg040346dsswbg04, 4432 }, { 4433 .compatible = "dataimage,fg1001l0dsswmg01", 4434 .data = &dataimage_fg1001l0dsswmg01, 4435 }, { 4436 .compatible = "dataimage,scf0700c48ggu18", 4437 .data = &dataimage_scf0700c48ggu18, 4438 }, { 4439 .compatible = "dlc,dlc0700yzg-1", 4440 .data = &dlc_dlc0700yzg_1, 4441 }, { 4442 .compatible = "dlc,dlc1010gig", 4443 .data = &dlc_dlc1010gig, 4444 }, { 4445 .compatible = "edt,et035012dm6", 4446 .data = &edt_et035012dm6, 4447 }, { 4448 .compatible = "edt,etm0350g0dh6", 4449 .data = &edt_etm0350g0dh6, 4450 }, { 4451 .compatible = "edt,etm043080dh6gp", 4452 .data = &edt_etm043080dh6gp, 4453 }, { 4454 .compatible = "edt,etm0430g0dh6", 4455 .data = &edt_etm0430g0dh6, 4456 }, { 4457 .compatible = "edt,et057090dhu", 4458 .data = &edt_et057090dhu, 4459 }, { 4460 .compatible = "edt,et070080dh6", 4461 .data = &edt_etm0700g0dh6, 4462 }, { 4463 .compatible = "edt,etm0700g0dh6", 4464 .data = &edt_etm0700g0dh6, 4465 }, { 4466 .compatible = "edt,etm0700g0bdh6", 4467 .data = &edt_etm0700g0bdh6, 4468 }, { 4469 .compatible = "edt,etm0700g0edh6", 4470 .data = &edt_etm0700g0bdh6, 4471 }, { 4472 .compatible = "edt,etml0700y5dha", 4473 .data = &edt_etml0700y5dha, 4474 }, { 4475 .compatible = "edt,etml1010g3dra", 4476 .data = &edt_etml1010g3dra, 4477 }, { 4478 .compatible = "edt,etmv570g2dhu", 4479 .data = &edt_etmv570g2dhu, 4480 }, { 4481 .compatible = "eink,vb3300-kca", 4482 .data = &eink_vb3300_kca, 4483 }, { 4484 .compatible = "evervision,vgg644804", 4485 .data = &evervision_vgg644804, 4486 }, { 4487 .compatible = "evervision,vgg804821", 4488 .data = &evervision_vgg804821, 4489 }, { 4490 .compatible = "foxlink,fl500wvr00-a0t", 4491 .data = &foxlink_fl500wvr00_a0t, 4492 }, { 4493 .compatible = "frida,frd350h54004", 4494 .data = &frida_frd350h54004, 4495 }, { 4496 .compatible = "friendlyarm,hd702e", 4497 .data = &friendlyarm_hd702e, 4498 }, { 4499 .compatible = "giantplus,gpg482739qs5", 4500 .data = &giantplus_gpg482739qs5 4501 }, { 4502 .compatible = "giantplus,gpm940b0", 4503 .data = &giantplus_gpm940b0, 4504 }, { 4505 .compatible = "hannstar,hsd070pww1", 4506 .data = &hannstar_hsd070pww1, 4507 }, { 4508 .compatible = "hannstar,hsd100pxn1", 4509 .data = &hannstar_hsd100pxn1, 4510 }, { 4511 .compatible = "hannstar,hsd101pww2", 4512 .data = &hannstar_hsd101pww2, 4513 }, { 4514 .compatible = "hit,tx23d38vm0caa", 4515 .data = &hitachi_tx23d38vm0caa 4516 }, { 4517 .compatible = "innolux,at043tn24", 4518 .data = &innolux_at043tn24, 4519 }, { 4520 .compatible = "innolux,at070tn92", 4521 .data = &innolux_at070tn92, 4522 }, { 4523 .compatible = "innolux,g070ace-l01", 4524 .data = &innolux_g070ace_l01, 4525 }, { 4526 .compatible = "innolux,g070y2-l01", 4527 .data = &innolux_g070y2_l01, 4528 }, { 4529 .compatible = "innolux,g070y2-t02", 4530 .data = &innolux_g070y2_t02, 4531 }, { 4532 .compatible = "innolux,g101ice-l01", 4533 .data = &innolux_g101ice_l01 4534 }, { 4535 .compatible = "innolux,g121i1-l01", 4536 .data = &innolux_g121i1_l01 4537 }, { 4538 .compatible = "innolux,g121x1-l03", 4539 .data = &innolux_g121x1_l03, 4540 }, { 4541 .compatible = "innolux,g156hce-l01", 4542 .data = &innolux_g156hce_l01, 4543 }, { 4544 .compatible = "innolux,n156bge-l21", 4545 .data = &innolux_n156bge_l21, 4546 }, { 4547 .compatible = "innolux,zj070na-01p", 4548 .data = &innolux_zj070na_01p, 4549 }, { 4550 .compatible = "koe,tx14d24vm1bpa", 4551 .data = &koe_tx14d24vm1bpa, 4552 }, { 4553 .compatible = "koe,tx26d202vm0bwa", 4554 .data = &koe_tx26d202vm0bwa, 4555 }, { 4556 .compatible = "koe,tx31d200vm0baa", 4557 .data = &koe_tx31d200vm0baa, 4558 }, { 4559 .compatible = "kyo,tcg121xglp", 4560 .data = &kyo_tcg121xglp, 4561 }, { 4562 .compatible = "lemaker,bl035-rgb-002", 4563 .data = &lemaker_bl035_rgb_002, 4564 }, { 4565 .compatible = "lg,lb070wv8", 4566 .data = &lg_lb070wv8, 4567 }, { 4568 .compatible = "logicpd,type28", 4569 .data = &logicpd_type_28, 4570 }, { 4571 .compatible = "logictechno,lt161010-2nhc", 4572 .data = &logictechno_lt161010_2nh, 4573 }, { 4574 .compatible = "logictechno,lt161010-2nhr", 4575 .data = &logictechno_lt161010_2nh, 4576 }, { 4577 .compatible = "logictechno,lt170410-2whc", 4578 .data = &logictechno_lt170410_2whc, 4579 }, { 4580 .compatible = "logictechno,lttd800480070-l2rt", 4581 .data = &logictechno_lttd800480070_l2rt, 4582 }, { 4583 .compatible = "logictechno,lttd800480070-l6wh-rt", 4584 .data = &logictechno_lttd800480070_l6wh_rt, 4585 }, { 4586 .compatible = "mitsubishi,aa070mc01-ca1", 4587 .data = &mitsubishi_aa070mc01, 4588 }, { 4589 .compatible = "mitsubishi,aa084xe01", 4590 .data = &mitsubishi_aa084xe01, 4591 }, { 4592 .compatible = "multi-inno,mi0700s4t-6", 4593 .data = &multi_inno_mi0700s4t_6, 4594 }, { 4595 .compatible = "multi-inno,mi0800ft-9", 4596 .data = &multi_inno_mi0800ft_9, 4597 }, { 4598 .compatible = "multi-inno,mi1010ait-1cp", 4599 .data = &multi_inno_mi1010ait_1cp, 4600 }, { 4601 .compatible = "nec,nl12880bc20-05", 4602 .data = &nec_nl12880bc20_05, 4603 }, { 4604 .compatible = "nec,nl4827hc19-05b", 4605 .data = &nec_nl4827hc19_05b, 4606 }, { 4607 .compatible = "netron-dy,e231732", 4608 .data = &netron_dy_e231732, 4609 }, { 4610 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4611 .data = &newhaven_nhd_43_480272ef_atxl, 4612 }, { 4613 .compatible = "nlt,nl192108ac18-02d", 4614 .data = &nlt_nl192108ac18_02d, 4615 }, { 4616 .compatible = "nvd,9128", 4617 .data = &nvd_9128, 4618 }, { 4619 .compatible = "okaya,rs800480t-7x0gp", 4620 .data = &okaya_rs800480t_7x0gp, 4621 }, { 4622 .compatible = "olimex,lcd-olinuxino-43-ts", 4623 .data = &olimex_lcd_olinuxino_43ts, 4624 }, { 4625 .compatible = "ontat,yx700wv03", 4626 .data = &ontat_yx700wv03, 4627 }, { 4628 .compatible = "ortustech,com37h3m05dtc", 4629 .data = &ortustech_com37h3m, 4630 }, { 4631 .compatible = "ortustech,com37h3m99dtc", 4632 .data = &ortustech_com37h3m, 4633 }, { 4634 .compatible = "ortustech,com43h4m85ulc", 4635 .data = &ortustech_com43h4m85ulc, 4636 }, { 4637 .compatible = "osddisplays,osd070t1718-19ts", 4638 .data = &osddisplays_osd070t1718_19ts, 4639 }, { 4640 .compatible = "pda,91-00156-a0", 4641 .data = &pda_91_00156_a0, 4642 }, { 4643 .compatible = "powertip,ph800480t013-idf02", 4644 .data = &powertip_ph800480t013_idf02, 4645 }, { 4646 .compatible = "qiaodian,qd43003c0-40", 4647 .data = &qd43003c0_40, 4648 }, { 4649 .compatible = "qishenglong,gopher2b-lcd", 4650 .data = &qishenglong_gopher2b_lcd, 4651 }, { 4652 .compatible = "rocktech,rk043fn48h", 4653 .data = &rocktech_rk043fn48h, 4654 }, { 4655 .compatible = "rocktech,rk070er9427", 4656 .data = &rocktech_rk070er9427, 4657 }, { 4658 .compatible = "rocktech,rk101ii01d-ct", 4659 .data = &rocktech_rk101ii01d_ct, 4660 }, { 4661 .compatible = "samsung,ltl101al01", 4662 .data = &samsung_ltl101al01, 4663 }, { 4664 .compatible = "samsung,ltn101nt05", 4665 .data = &samsung_ltn101nt05, 4666 }, { 4667 .compatible = "satoz,sat050at40h12r2", 4668 .data = &satoz_sat050at40h12r2, 4669 }, { 4670 .compatible = "sharp,lq035q7db03", 4671 .data = &sharp_lq035q7db03, 4672 }, { 4673 .compatible = "sharp,lq070y3dg3b", 4674 .data = &sharp_lq070y3dg3b, 4675 }, { 4676 .compatible = "sharp,lq101k1ly04", 4677 .data = &sharp_lq101k1ly04, 4678 }, { 4679 .compatible = "sharp,ls020b1dd01d", 4680 .data = &sharp_ls020b1dd01d, 4681 }, { 4682 .compatible = "shelly,sca07010-bfn-lnn", 4683 .data = &shelly_sca07010_bfn_lnn, 4684 }, { 4685 .compatible = "starry,kr070pe2t", 4686 .data = &starry_kr070pe2t, 4687 }, { 4688 .compatible = "startek,kd070wvfpa", 4689 .data = &startek_kd070wvfpa, 4690 }, { 4691 .compatible = "team-source-display,tst043015cmhx", 4692 .data = &tsd_tst043015cmhx, 4693 }, { 4694 .compatible = "tfc,s9700rtwv43tr-01b", 4695 .data = &tfc_s9700rtwv43tr_01b, 4696 }, { 4697 .compatible = "tianma,tm070jdhg30", 4698 .data = &tianma_tm070jdhg30, 4699 }, { 4700 .compatible = "tianma,tm070jvhg33", 4701 .data = &tianma_tm070jvhg33, 4702 }, { 4703 .compatible = "tianma,tm070rvhg71", 4704 .data = &tianma_tm070rvhg71, 4705 }, { 4706 .compatible = "ti,nspire-cx-lcd-panel", 4707 .data = &ti_nspire_cx_lcd_panel, 4708 }, { 4709 .compatible = "ti,nspire-classic-lcd-panel", 4710 .data = &ti_nspire_classic_lcd_panel, 4711 }, { 4712 .compatible = "toshiba,lt089ac29000", 4713 .data = &toshiba_lt089ac29000, 4714 }, { 4715 .compatible = "tpk,f07a-0102", 4716 .data = &tpk_f07a_0102, 4717 }, { 4718 .compatible = "tpk,f10a-0102", 4719 .data = &tpk_f10a_0102, 4720 }, { 4721 .compatible = "urt,umsh-8596md-t", 4722 .data = &urt_umsh_8596md_parallel, 4723 }, { 4724 .compatible = "urt,umsh-8596md-1t", 4725 .data = &urt_umsh_8596md_parallel, 4726 }, { 4727 .compatible = "urt,umsh-8596md-7t", 4728 .data = &urt_umsh_8596md_parallel, 4729 }, { 4730 .compatible = "urt,umsh-8596md-11t", 4731 .data = &urt_umsh_8596md_lvds, 4732 }, { 4733 .compatible = "urt,umsh-8596md-19t", 4734 .data = &urt_umsh_8596md_lvds, 4735 }, { 4736 .compatible = "urt,umsh-8596md-20t", 4737 .data = &urt_umsh_8596md_parallel, 4738 }, { 4739 .compatible = "vivax,tpc9150-panel", 4740 .data = &vivax_tpc9150_panel, 4741 }, { 4742 .compatible = "vxt,vl050-8048nt-c01", 4743 .data = &vl050_8048nt_c01, 4744 }, { 4745 .compatible = "winstar,wf35ltiacd", 4746 .data = &winstar_wf35ltiacd, 4747 }, { 4748 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4749 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4750 }, { 4751 /* Must be the last entry */ 4752 .compatible = "panel-dpi", 4753 .data = &panel_dpi, 4754 }, { 4755 /* sentinel */ 4756 } 4757 }; 4758 MODULE_DEVICE_TABLE(of, platform_of_match); 4759 4760 static int panel_simple_platform_probe(struct platform_device *pdev) 4761 { 4762 const struct panel_desc *desc; 4763 4764 desc = of_device_get_match_data(&pdev->dev); 4765 if (!desc) 4766 return -ENODEV; 4767 4768 return panel_simple_probe(&pdev->dev, desc); 4769 } 4770 4771 static void panel_simple_platform_remove(struct platform_device *pdev) 4772 { 4773 panel_simple_remove(&pdev->dev); 4774 } 4775 4776 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4777 { 4778 panel_simple_shutdown(&pdev->dev); 4779 } 4780 4781 static const struct dev_pm_ops panel_simple_pm_ops = { 4782 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4783 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4784 pm_runtime_force_resume) 4785 }; 4786 4787 static struct platform_driver panel_simple_platform_driver = { 4788 .driver = { 4789 .name = "panel-simple", 4790 .of_match_table = platform_of_match, 4791 .pm = &panel_simple_pm_ops, 4792 }, 4793 .probe = panel_simple_platform_probe, 4794 .remove_new = panel_simple_platform_remove, 4795 .shutdown = panel_simple_platform_shutdown, 4796 }; 4797 4798 struct panel_desc_dsi { 4799 struct panel_desc desc; 4800 4801 unsigned long flags; 4802 enum mipi_dsi_pixel_format format; 4803 unsigned int lanes; 4804 }; 4805 4806 static const struct drm_display_mode auo_b080uan01_mode = { 4807 .clock = 154500, 4808 .hdisplay = 1200, 4809 .hsync_start = 1200 + 62, 4810 .hsync_end = 1200 + 62 + 4, 4811 .htotal = 1200 + 62 + 4 + 62, 4812 .vdisplay = 1920, 4813 .vsync_start = 1920 + 9, 4814 .vsync_end = 1920 + 9 + 2, 4815 .vtotal = 1920 + 9 + 2 + 8, 4816 }; 4817 4818 static const struct panel_desc_dsi auo_b080uan01 = { 4819 .desc = { 4820 .modes = &auo_b080uan01_mode, 4821 .num_modes = 1, 4822 .bpc = 8, 4823 .size = { 4824 .width = 108, 4825 .height = 272, 4826 }, 4827 .connector_type = DRM_MODE_CONNECTOR_DSI, 4828 }, 4829 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4830 .format = MIPI_DSI_FMT_RGB888, 4831 .lanes = 4, 4832 }; 4833 4834 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4835 .clock = 160000, 4836 .hdisplay = 1200, 4837 .hsync_start = 1200 + 120, 4838 .hsync_end = 1200 + 120 + 20, 4839 .htotal = 1200 + 120 + 20 + 21, 4840 .vdisplay = 1920, 4841 .vsync_start = 1920 + 21, 4842 .vsync_end = 1920 + 21 + 3, 4843 .vtotal = 1920 + 21 + 3 + 18, 4844 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4845 }; 4846 4847 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4848 .desc = { 4849 .modes = &boe_tv080wum_nl0_mode, 4850 .num_modes = 1, 4851 .size = { 4852 .width = 107, 4853 .height = 172, 4854 }, 4855 .connector_type = DRM_MODE_CONNECTOR_DSI, 4856 }, 4857 .flags = MIPI_DSI_MODE_VIDEO | 4858 MIPI_DSI_MODE_VIDEO_BURST | 4859 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4860 .format = MIPI_DSI_FMT_RGB888, 4861 .lanes = 4, 4862 }; 4863 4864 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4865 .clock = 71000, 4866 .hdisplay = 800, 4867 .hsync_start = 800 + 32, 4868 .hsync_end = 800 + 32 + 1, 4869 .htotal = 800 + 32 + 1 + 57, 4870 .vdisplay = 1280, 4871 .vsync_start = 1280 + 28, 4872 .vsync_end = 1280 + 28 + 1, 4873 .vtotal = 1280 + 28 + 1 + 14, 4874 }; 4875 4876 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4877 .desc = { 4878 .modes = &lg_ld070wx3_sl01_mode, 4879 .num_modes = 1, 4880 .bpc = 8, 4881 .size = { 4882 .width = 94, 4883 .height = 151, 4884 }, 4885 .connector_type = DRM_MODE_CONNECTOR_DSI, 4886 }, 4887 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4888 .format = MIPI_DSI_FMT_RGB888, 4889 .lanes = 4, 4890 }; 4891 4892 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4893 .clock = 67000, 4894 .hdisplay = 720, 4895 .hsync_start = 720 + 12, 4896 .hsync_end = 720 + 12 + 4, 4897 .htotal = 720 + 12 + 4 + 112, 4898 .vdisplay = 1280, 4899 .vsync_start = 1280 + 8, 4900 .vsync_end = 1280 + 8 + 4, 4901 .vtotal = 1280 + 8 + 4 + 12, 4902 }; 4903 4904 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4905 .desc = { 4906 .modes = &lg_lh500wx1_sd03_mode, 4907 .num_modes = 1, 4908 .bpc = 8, 4909 .size = { 4910 .width = 62, 4911 .height = 110, 4912 }, 4913 .connector_type = DRM_MODE_CONNECTOR_DSI, 4914 }, 4915 .flags = MIPI_DSI_MODE_VIDEO, 4916 .format = MIPI_DSI_FMT_RGB888, 4917 .lanes = 4, 4918 }; 4919 4920 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4921 .clock = 157200, 4922 .hdisplay = 1920, 4923 .hsync_start = 1920 + 154, 4924 .hsync_end = 1920 + 154 + 16, 4925 .htotal = 1920 + 154 + 16 + 32, 4926 .vdisplay = 1200, 4927 .vsync_start = 1200 + 17, 4928 .vsync_end = 1200 + 17 + 2, 4929 .vtotal = 1200 + 17 + 2 + 16, 4930 }; 4931 4932 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4933 .desc = { 4934 .modes = &panasonic_vvx10f004b00_mode, 4935 .num_modes = 1, 4936 .bpc = 8, 4937 .size = { 4938 .width = 217, 4939 .height = 136, 4940 }, 4941 .connector_type = DRM_MODE_CONNECTOR_DSI, 4942 }, 4943 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4944 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4945 .format = MIPI_DSI_FMT_RGB888, 4946 .lanes = 4, 4947 }; 4948 4949 static const struct drm_display_mode lg_acx467akm_7_mode = { 4950 .clock = 150000, 4951 .hdisplay = 1080, 4952 .hsync_start = 1080 + 2, 4953 .hsync_end = 1080 + 2 + 2, 4954 .htotal = 1080 + 2 + 2 + 2, 4955 .vdisplay = 1920, 4956 .vsync_start = 1920 + 2, 4957 .vsync_end = 1920 + 2 + 2, 4958 .vtotal = 1920 + 2 + 2 + 2, 4959 }; 4960 4961 static const struct panel_desc_dsi lg_acx467akm_7 = { 4962 .desc = { 4963 .modes = &lg_acx467akm_7_mode, 4964 .num_modes = 1, 4965 .bpc = 8, 4966 .size = { 4967 .width = 62, 4968 .height = 110, 4969 }, 4970 .connector_type = DRM_MODE_CONNECTOR_DSI, 4971 }, 4972 .flags = 0, 4973 .format = MIPI_DSI_FMT_RGB888, 4974 .lanes = 4, 4975 }; 4976 4977 static const struct drm_display_mode osd101t2045_53ts_mode = { 4978 .clock = 154500, 4979 .hdisplay = 1920, 4980 .hsync_start = 1920 + 112, 4981 .hsync_end = 1920 + 112 + 16, 4982 .htotal = 1920 + 112 + 16 + 32, 4983 .vdisplay = 1200, 4984 .vsync_start = 1200 + 16, 4985 .vsync_end = 1200 + 16 + 2, 4986 .vtotal = 1200 + 16 + 2 + 16, 4987 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4988 }; 4989 4990 static const struct panel_desc_dsi osd101t2045_53ts = { 4991 .desc = { 4992 .modes = &osd101t2045_53ts_mode, 4993 .num_modes = 1, 4994 .bpc = 8, 4995 .size = { 4996 .width = 217, 4997 .height = 136, 4998 }, 4999 .connector_type = DRM_MODE_CONNECTOR_DSI, 5000 }, 5001 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5002 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5003 MIPI_DSI_MODE_NO_EOT_PACKET, 5004 .format = MIPI_DSI_FMT_RGB888, 5005 .lanes = 4, 5006 }; 5007 5008 static const struct of_device_id dsi_of_match[] = { 5009 { 5010 .compatible = "auo,b080uan01", 5011 .data = &auo_b080uan01 5012 }, { 5013 .compatible = "boe,tv080wum-nl0", 5014 .data = &boe_tv080wum_nl0 5015 }, { 5016 .compatible = "lg,ld070wx3-sl01", 5017 .data = &lg_ld070wx3_sl01 5018 }, { 5019 .compatible = "lg,lh500wx1-sd03", 5020 .data = &lg_lh500wx1_sd03 5021 }, { 5022 .compatible = "panasonic,vvx10f004b00", 5023 .data = &panasonic_vvx10f004b00 5024 }, { 5025 .compatible = "lg,acx467akm-7", 5026 .data = &lg_acx467akm_7 5027 }, { 5028 .compatible = "osddisplays,osd101t2045-53ts", 5029 .data = &osd101t2045_53ts 5030 }, { 5031 /* sentinel */ 5032 } 5033 }; 5034 MODULE_DEVICE_TABLE(of, dsi_of_match); 5035 5036 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5037 { 5038 const struct panel_desc_dsi *desc; 5039 int err; 5040 5041 desc = of_device_get_match_data(&dsi->dev); 5042 if (!desc) 5043 return -ENODEV; 5044 5045 err = panel_simple_probe(&dsi->dev, &desc->desc); 5046 if (err < 0) 5047 return err; 5048 5049 dsi->mode_flags = desc->flags; 5050 dsi->format = desc->format; 5051 dsi->lanes = desc->lanes; 5052 5053 err = mipi_dsi_attach(dsi); 5054 if (err) { 5055 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5056 5057 drm_panel_remove(&panel->base); 5058 } 5059 5060 return err; 5061 } 5062 5063 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5064 { 5065 int err; 5066 5067 err = mipi_dsi_detach(dsi); 5068 if (err < 0) 5069 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5070 5071 panel_simple_remove(&dsi->dev); 5072 } 5073 5074 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5075 { 5076 panel_simple_shutdown(&dsi->dev); 5077 } 5078 5079 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5080 .driver = { 5081 .name = "panel-simple-dsi", 5082 .of_match_table = dsi_of_match, 5083 .pm = &panel_simple_pm_ops, 5084 }, 5085 .probe = panel_simple_dsi_probe, 5086 .remove = panel_simple_dsi_remove, 5087 .shutdown = panel_simple_dsi_shutdown, 5088 }; 5089 5090 static int __init panel_simple_init(void) 5091 { 5092 int err; 5093 5094 err = platform_driver_register(&panel_simple_platform_driver); 5095 if (err < 0) 5096 return err; 5097 5098 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5099 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5100 if (err < 0) 5101 goto err_did_platform_register; 5102 } 5103 5104 return 0; 5105 5106 err_did_platform_register: 5107 platform_driver_unregister(&panel_simple_platform_driver); 5108 5109 return err; 5110 } 5111 module_init(panel_simple_init); 5112 5113 static void __exit panel_simple_exit(void) 5114 { 5115 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5116 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5117 5118 platform_driver_unregister(&panel_simple_platform_driver); 5119 } 5120 module_exit(panel_simple_exit); 5121 5122 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5123 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5124 MODULE_LICENSE("GPL and additional rights"); 5125