1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 bool enabled; 142 143 bool prepared; 144 145 ktime_t unprepared_time; 146 147 const struct panel_desc *desc; 148 149 struct regulator *supply; 150 struct i2c_adapter *ddc; 151 152 struct gpio_desc *enable_gpio; 153 154 struct edid *edid; 155 156 struct drm_display_mode override_mode; 157 158 enum drm_panel_orientation orientation; 159 }; 160 161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 162 { 163 return container_of(panel, struct panel_simple, base); 164 } 165 166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 167 struct drm_connector *connector) 168 { 169 struct drm_display_mode *mode; 170 unsigned int i, num = 0; 171 172 for (i = 0; i < panel->desc->num_timings; i++) { 173 const struct display_timing *dt = &panel->desc->timings[i]; 174 struct videomode vm; 175 176 videomode_from_timing(dt, &vm); 177 mode = drm_mode_create(connector->dev); 178 if (!mode) { 179 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 180 dt->hactive.typ, dt->vactive.typ); 181 continue; 182 } 183 184 drm_display_mode_from_videomode(&vm, mode); 185 186 mode->type |= DRM_MODE_TYPE_DRIVER; 187 188 if (panel->desc->num_timings == 1) 189 mode->type |= DRM_MODE_TYPE_PREFERRED; 190 191 drm_mode_probed_add(connector, mode); 192 num++; 193 } 194 195 return num; 196 } 197 198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 199 struct drm_connector *connector) 200 { 201 struct drm_display_mode *mode; 202 unsigned int i, num = 0; 203 204 for (i = 0; i < panel->desc->num_modes; i++) { 205 const struct drm_display_mode *m = &panel->desc->modes[i]; 206 207 mode = drm_mode_duplicate(connector->dev, m); 208 if (!mode) { 209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 210 m->hdisplay, m->vdisplay, 211 drm_mode_vrefresh(m)); 212 continue; 213 } 214 215 mode->type |= DRM_MODE_TYPE_DRIVER; 216 217 if (panel->desc->num_modes == 1) 218 mode->type |= DRM_MODE_TYPE_PREFERRED; 219 220 drm_mode_set_name(mode); 221 222 drm_mode_probed_add(connector, mode); 223 num++; 224 } 225 226 return num; 227 } 228 229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 230 struct drm_connector *connector) 231 { 232 struct drm_display_mode *mode; 233 bool has_override = panel->override_mode.type; 234 unsigned int num = 0; 235 236 if (!panel->desc) 237 return 0; 238 239 if (has_override) { 240 mode = drm_mode_duplicate(connector->dev, 241 &panel->override_mode); 242 if (mode) { 243 drm_mode_probed_add(connector, mode); 244 num = 1; 245 } else { 246 dev_err(panel->base.dev, "failed to add override mode\n"); 247 } 248 } 249 250 /* Only add timings if override was not there or failed to validate */ 251 if (num == 0 && panel->desc->num_timings) 252 num = panel_simple_get_timings_modes(panel, connector); 253 254 /* 255 * Only add fixed modes if timings/override added no mode. 256 * 257 * We should only ever have either the display timings specified 258 * or a fixed mode. Anything else is rather bogus. 259 */ 260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 261 if (num == 0) 262 num = panel_simple_get_display_modes(panel, connector); 263 264 connector->display_info.bpc = panel->desc->bpc; 265 connector->display_info.width_mm = panel->desc->size.width; 266 connector->display_info.height_mm = panel->desc->size.height; 267 if (panel->desc->bus_format) 268 drm_display_info_set_bus_formats(&connector->display_info, 269 &panel->desc->bus_format, 1); 270 connector->display_info.bus_flags = panel->desc->bus_flags; 271 272 return num; 273 } 274 275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 276 { 277 ktime_t now_ktime, min_ktime; 278 279 if (!min_ms) 280 return; 281 282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 283 now_ktime = ktime_get_boottime(); 284 285 if (ktime_before(now_ktime, min_ktime)) 286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 287 } 288 289 static int panel_simple_disable(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 293 if (!p->enabled) 294 return 0; 295 296 if (p->desc->delay.disable) 297 msleep(p->desc->delay.disable); 298 299 p->enabled = false; 300 301 return 0; 302 } 303 304 static int panel_simple_suspend(struct device *dev) 305 { 306 struct panel_simple *p = dev_get_drvdata(dev); 307 308 gpiod_set_value_cansleep(p->enable_gpio, 0); 309 regulator_disable(p->supply); 310 p->unprepared_time = ktime_get_boottime(); 311 312 kfree(p->edid); 313 p->edid = NULL; 314 315 return 0; 316 } 317 318 static int panel_simple_unprepare(struct drm_panel *panel) 319 { 320 struct panel_simple *p = to_panel_simple(panel); 321 int ret; 322 323 /* Unpreparing when already unprepared is a no-op */ 324 if (!p->prepared) 325 return 0; 326 327 pm_runtime_mark_last_busy(panel->dev); 328 ret = pm_runtime_put_autosuspend(panel->dev); 329 if (ret < 0) 330 return ret; 331 p->prepared = false; 332 333 return 0; 334 } 335 336 static int panel_simple_resume(struct device *dev) 337 { 338 struct panel_simple *p = dev_get_drvdata(dev); 339 int err; 340 341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 342 343 err = regulator_enable(p->supply); 344 if (err < 0) { 345 dev_err(dev, "failed to enable supply: %d\n", err); 346 return err; 347 } 348 349 gpiod_set_value_cansleep(p->enable_gpio, 1); 350 351 if (p->desc->delay.prepare) 352 msleep(p->desc->delay.prepare); 353 354 return 0; 355 } 356 357 static int panel_simple_prepare(struct drm_panel *panel) 358 { 359 struct panel_simple *p = to_panel_simple(panel); 360 int ret; 361 362 /* Preparing when already prepared is a no-op */ 363 if (p->prepared) 364 return 0; 365 366 ret = pm_runtime_get_sync(panel->dev); 367 if (ret < 0) { 368 pm_runtime_put_autosuspend(panel->dev); 369 return ret; 370 } 371 372 p->prepared = true; 373 374 return 0; 375 } 376 377 static int panel_simple_enable(struct drm_panel *panel) 378 { 379 struct panel_simple *p = to_panel_simple(panel); 380 381 if (p->enabled) 382 return 0; 383 384 if (p->desc->delay.enable) 385 msleep(p->desc->delay.enable); 386 387 p->enabled = true; 388 389 return 0; 390 } 391 392 static int panel_simple_get_modes(struct drm_panel *panel, 393 struct drm_connector *connector) 394 { 395 struct panel_simple *p = to_panel_simple(panel); 396 int num = 0; 397 398 /* probe EDID if a DDC bus is available */ 399 if (p->ddc) { 400 pm_runtime_get_sync(panel->dev); 401 402 if (!p->edid) 403 p->edid = drm_get_edid(connector, p->ddc); 404 405 if (p->edid) 406 num += drm_add_edid_modes(connector, p->edid); 407 408 pm_runtime_mark_last_busy(panel->dev); 409 pm_runtime_put_autosuspend(panel->dev); 410 } 411 412 /* add hard-coded panel modes */ 413 num += panel_simple_get_non_edid_modes(p, connector); 414 415 /* 416 * TODO: Remove once all drm drivers call 417 * drm_connector_set_orientation_from_panel() 418 */ 419 drm_connector_set_panel_orientation(connector, p->orientation); 420 421 return num; 422 } 423 424 static int panel_simple_get_timings(struct drm_panel *panel, 425 unsigned int num_timings, 426 struct display_timing *timings) 427 { 428 struct panel_simple *p = to_panel_simple(panel); 429 unsigned int i; 430 431 if (p->desc->num_timings < num_timings) 432 num_timings = p->desc->num_timings; 433 434 if (timings) 435 for (i = 0; i < num_timings; i++) 436 timings[i] = p->desc->timings[i]; 437 438 return p->desc->num_timings; 439 } 440 441 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 442 { 443 struct panel_simple *p = to_panel_simple(panel); 444 445 return p->orientation; 446 } 447 448 static const struct drm_panel_funcs panel_simple_funcs = { 449 .disable = panel_simple_disable, 450 .unprepare = panel_simple_unprepare, 451 .prepare = panel_simple_prepare, 452 .enable = panel_simple_enable, 453 .get_modes = panel_simple_get_modes, 454 .get_orientation = panel_simple_get_orientation, 455 .get_timings = panel_simple_get_timings, 456 }; 457 458 static struct panel_desc panel_dpi; 459 460 static int panel_dpi_probe(struct device *dev, 461 struct panel_simple *panel) 462 { 463 struct display_timing *timing; 464 const struct device_node *np; 465 struct panel_desc *desc; 466 unsigned int bus_flags; 467 struct videomode vm; 468 int ret; 469 470 np = dev->of_node; 471 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 472 if (!desc) 473 return -ENOMEM; 474 475 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 476 if (!timing) 477 return -ENOMEM; 478 479 ret = of_get_display_timing(np, "panel-timing", timing); 480 if (ret < 0) { 481 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 482 np); 483 return ret; 484 } 485 486 desc->timings = timing; 487 desc->num_timings = 1; 488 489 of_property_read_u32(np, "width-mm", &desc->size.width); 490 of_property_read_u32(np, "height-mm", &desc->size.height); 491 492 /* Extract bus_flags from display_timing */ 493 bus_flags = 0; 494 vm.flags = timing->flags; 495 drm_bus_flags_from_videomode(&vm, &bus_flags); 496 desc->bus_flags = bus_flags; 497 498 /* We do not know the connector for the DT node, so guess it */ 499 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 500 501 panel->desc = desc; 502 503 return 0; 504 } 505 506 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 507 (to_check->field.typ >= bounds->field.min && \ 508 to_check->field.typ <= bounds->field.max) 509 static void panel_simple_parse_panel_timing_node(struct device *dev, 510 struct panel_simple *panel, 511 const struct display_timing *ot) 512 { 513 const struct panel_desc *desc = panel->desc; 514 struct videomode vm; 515 unsigned int i; 516 517 if (WARN_ON(desc->num_modes)) { 518 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 519 return; 520 } 521 if (WARN_ON(!desc->num_timings)) { 522 dev_err(dev, "Reject override mode: no timings specified\n"); 523 return; 524 } 525 526 for (i = 0; i < panel->desc->num_timings; i++) { 527 const struct display_timing *dt = &panel->desc->timings[i]; 528 529 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 537 continue; 538 539 if (ot->flags != dt->flags) 540 continue; 541 542 videomode_from_timing(ot, &vm); 543 drm_display_mode_from_videomode(&vm, &panel->override_mode); 544 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 545 DRM_MODE_TYPE_PREFERRED; 546 break; 547 } 548 549 if (WARN_ON(!panel->override_mode.type)) 550 dev_err(dev, "Reject override mode: No display_timing found\n"); 551 } 552 553 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 554 struct panel_simple *panel) 555 { 556 int ret, bpc; 557 558 ret = drm_of_lvds_get_data_mapping(dev->of_node); 559 if (ret < 0) { 560 if (ret == -EINVAL) 561 dev_warn(dev, "Ignore invalid data-mapping property\n"); 562 563 /* 564 * Ignore non-existing or malformatted property, fallback to 565 * default data-mapping, and return 0. 566 */ 567 return 0; 568 } 569 570 switch (ret) { 571 default: 572 WARN_ON(1); 573 fallthrough; 574 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 575 fallthrough; 576 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 577 bpc = 8; 578 break; 579 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 580 bpc = 6; 581 } 582 583 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 584 struct panel_desc *override_desc; 585 586 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 587 if (!override_desc) 588 return -ENOMEM; 589 590 override_desc->bus_format = ret; 591 override_desc->bpc = bpc; 592 panel->desc = override_desc; 593 } 594 595 return 0; 596 } 597 598 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 599 { 600 struct panel_simple *panel; 601 struct display_timing dt; 602 struct device_node *ddc; 603 int connector_type; 604 u32 bus_flags; 605 int err; 606 607 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 608 if (!panel) 609 return -ENOMEM; 610 611 panel->enabled = false; 612 panel->desc = desc; 613 614 panel->supply = devm_regulator_get(dev, "power"); 615 if (IS_ERR(panel->supply)) 616 return PTR_ERR(panel->supply); 617 618 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 619 GPIOD_OUT_LOW); 620 if (IS_ERR(panel->enable_gpio)) 621 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 622 "failed to request GPIO\n"); 623 624 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 625 if (err) { 626 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 627 return err; 628 } 629 630 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 631 if (ddc) { 632 panel->ddc = of_find_i2c_adapter_by_node(ddc); 633 of_node_put(ddc); 634 635 if (!panel->ddc) 636 return -EPROBE_DEFER; 637 } 638 639 if (desc == &panel_dpi) { 640 /* Handle the generic panel-dpi binding */ 641 err = panel_dpi_probe(dev, panel); 642 if (err) 643 goto free_ddc; 644 desc = panel->desc; 645 } else { 646 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 647 panel_simple_parse_panel_timing_node(dev, panel, &dt); 648 } 649 650 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 651 /* Optional data-mapping property for overriding bus format */ 652 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 653 if (err) 654 goto free_ddc; 655 } 656 657 connector_type = desc->connector_type; 658 /* Catch common mistakes for panels. */ 659 switch (connector_type) { 660 case 0: 661 dev_warn(dev, "Specify missing connector_type\n"); 662 connector_type = DRM_MODE_CONNECTOR_DPI; 663 break; 664 case DRM_MODE_CONNECTOR_LVDS: 665 WARN_ON(desc->bus_flags & 666 ~(DRM_BUS_FLAG_DE_LOW | 667 DRM_BUS_FLAG_DE_HIGH | 668 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 669 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 670 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 671 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 672 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 673 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 674 desc->bpc != 6); 675 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 676 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 677 desc->bpc != 8); 678 break; 679 case DRM_MODE_CONNECTOR_eDP: 680 dev_warn(dev, "eDP panels moved to panel-edp\n"); 681 err = -EINVAL; 682 goto free_ddc; 683 case DRM_MODE_CONNECTOR_DSI: 684 if (desc->bpc != 6 && desc->bpc != 8) 685 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 686 break; 687 case DRM_MODE_CONNECTOR_DPI: 688 bus_flags = DRM_BUS_FLAG_DE_LOW | 689 DRM_BUS_FLAG_DE_HIGH | 690 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 691 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 692 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 693 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 694 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 695 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 696 if (desc->bus_flags & ~bus_flags) 697 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 698 if (!(desc->bus_flags & bus_flags)) 699 dev_warn(dev, "Specify missing bus_flags\n"); 700 if (desc->bus_format == 0) 701 dev_warn(dev, "Specify missing bus_format\n"); 702 if (desc->bpc != 6 && desc->bpc != 8) 703 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 704 break; 705 default: 706 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 707 connector_type = DRM_MODE_CONNECTOR_DPI; 708 break; 709 } 710 711 dev_set_drvdata(dev, panel); 712 713 /* 714 * We use runtime PM for prepare / unprepare since those power the panel 715 * on and off and those can be very slow operations. This is important 716 * to optimize powering the panel on briefly to read the EDID before 717 * fully enabling the panel. 718 */ 719 pm_runtime_enable(dev); 720 pm_runtime_set_autosuspend_delay(dev, 1000); 721 pm_runtime_use_autosuspend(dev); 722 723 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 724 725 err = drm_panel_of_backlight(&panel->base); 726 if (err) { 727 dev_err_probe(dev, err, "Could not find backlight\n"); 728 goto disable_pm_runtime; 729 } 730 731 drm_panel_add(&panel->base); 732 733 return 0; 734 735 disable_pm_runtime: 736 pm_runtime_dont_use_autosuspend(dev); 737 pm_runtime_disable(dev); 738 free_ddc: 739 if (panel->ddc) 740 put_device(&panel->ddc->dev); 741 742 return err; 743 } 744 745 static void panel_simple_remove(struct device *dev) 746 { 747 struct panel_simple *panel = dev_get_drvdata(dev); 748 749 drm_panel_remove(&panel->base); 750 drm_panel_disable(&panel->base); 751 drm_panel_unprepare(&panel->base); 752 753 pm_runtime_dont_use_autosuspend(dev); 754 pm_runtime_disable(dev); 755 if (panel->ddc) 756 put_device(&panel->ddc->dev); 757 } 758 759 static void panel_simple_shutdown(struct device *dev) 760 { 761 struct panel_simple *panel = dev_get_drvdata(dev); 762 763 drm_panel_disable(&panel->base); 764 drm_panel_unprepare(&panel->base); 765 } 766 767 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 768 .clock = 71100, 769 .hdisplay = 1280, 770 .hsync_start = 1280 + 40, 771 .hsync_end = 1280 + 40 + 80, 772 .htotal = 1280 + 40 + 80 + 40, 773 .vdisplay = 800, 774 .vsync_start = 800 + 3, 775 .vsync_end = 800 + 3 + 10, 776 .vtotal = 800 + 3 + 10 + 10, 777 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 778 }; 779 780 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 781 .modes = &ire_am_1280800n3tzqw_t00h_mode, 782 .num_modes = 1, 783 .bpc = 8, 784 .size = { 785 .width = 217, 786 .height = 136, 787 }, 788 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 789 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 790 .connector_type = DRM_MODE_CONNECTOR_LVDS, 791 }; 792 793 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 794 .clock = 9000, 795 .hdisplay = 480, 796 .hsync_start = 480 + 2, 797 .hsync_end = 480 + 2 + 41, 798 .htotal = 480 + 2 + 41 + 2, 799 .vdisplay = 272, 800 .vsync_start = 272 + 2, 801 .vsync_end = 272 + 2 + 10, 802 .vtotal = 272 + 2 + 10 + 2, 803 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 804 }; 805 806 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 807 .modes = &ire_am_480272h3tmqw_t01h_mode, 808 .num_modes = 1, 809 .bpc = 8, 810 .size = { 811 .width = 99, 812 .height = 58, 813 }, 814 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 815 }; 816 817 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 818 .clock = 33333, 819 .hdisplay = 800, 820 .hsync_start = 800 + 0, 821 .hsync_end = 800 + 0 + 255, 822 .htotal = 800 + 0 + 255 + 0, 823 .vdisplay = 480, 824 .vsync_start = 480 + 2, 825 .vsync_end = 480 + 2 + 45, 826 .vtotal = 480 + 2 + 45 + 0, 827 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 828 }; 829 830 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 831 .pixelclock = { 29930000, 33260000, 36590000 }, 832 .hactive = { 800, 800, 800 }, 833 .hfront_porch = { 1, 40, 168 }, 834 .hback_porch = { 88, 88, 88 }, 835 .hsync_len = { 1, 128, 128 }, 836 .vactive = { 480, 480, 480 }, 837 .vfront_porch = { 1, 35, 37 }, 838 .vback_porch = { 8, 8, 8 }, 839 .vsync_len = { 1, 2, 2 }, 840 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 841 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 842 DISPLAY_FLAGS_SYNC_POSEDGE, 843 }; 844 845 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 846 .timings = &ire_am_800480l1tmqw_t00h_timing, 847 .num_timings = 1, 848 .bpc = 8, 849 .size = { 850 .width = 111, 851 .height = 67, 852 }, 853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 854 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 855 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 856 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 857 .connector_type = DRM_MODE_CONNECTOR_DPI, 858 }; 859 860 static const struct panel_desc ampire_am800480r3tmqwa1h = { 861 .modes = &ire_am800480r3tmqwa1h_mode, 862 .num_modes = 1, 863 .bpc = 6, 864 .size = { 865 .width = 152, 866 .height = 91, 867 }, 868 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 869 }; 870 871 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 872 .pixelclock = { 34500000, 39600000, 50400000 }, 873 .hactive = { 800, 800, 800 }, 874 .hfront_porch = { 12, 112, 312 }, 875 .hback_porch = { 87, 87, 48 }, 876 .hsync_len = { 1, 1, 40 }, 877 .vactive = { 600, 600, 600 }, 878 .vfront_porch = { 1, 21, 61 }, 879 .vback_porch = { 38, 38, 19 }, 880 .vsync_len = { 1, 1, 20 }, 881 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 882 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 883 DISPLAY_FLAGS_SYNC_POSEDGE, 884 }; 885 886 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 887 .timings = &ire_am800600p5tmqw_tb8h_timing, 888 .num_timings = 1, 889 .bpc = 6, 890 .size = { 891 .width = 162, 892 .height = 122, 893 }, 894 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 895 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 896 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 897 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 898 .connector_type = DRM_MODE_CONNECTOR_DPI, 899 }; 900 901 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 902 .pixelclock = { 26400000, 33300000, 46800000 }, 903 .hactive = { 800, 800, 800 }, 904 .hfront_porch = { 16, 210, 354 }, 905 .hback_porch = { 45, 36, 6 }, 906 .hsync_len = { 1, 10, 40 }, 907 .vactive = { 480, 480, 480 }, 908 .vfront_porch = { 7, 22, 147 }, 909 .vback_porch = { 22, 13, 3 }, 910 .vsync_len = { 1, 10, 20 }, 911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 913 }; 914 915 static const struct panel_desc armadeus_st0700_adapt = { 916 .timings = &santek_st0700i5y_rbslw_f_timing, 917 .num_timings = 1, 918 .bpc = 6, 919 .size = { 920 .width = 154, 921 .height = 86, 922 }, 923 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 924 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 925 }; 926 927 static const struct drm_display_mode auo_b101aw03_mode = { 928 .clock = 51450, 929 .hdisplay = 1024, 930 .hsync_start = 1024 + 156, 931 .hsync_end = 1024 + 156 + 8, 932 .htotal = 1024 + 156 + 8 + 156, 933 .vdisplay = 600, 934 .vsync_start = 600 + 16, 935 .vsync_end = 600 + 16 + 6, 936 .vtotal = 600 + 16 + 6 + 16, 937 }; 938 939 static const struct panel_desc auo_b101aw03 = { 940 .modes = &auo_b101aw03_mode, 941 .num_modes = 1, 942 .bpc = 6, 943 .size = { 944 .width = 223, 945 .height = 125, 946 }, 947 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 948 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 949 .connector_type = DRM_MODE_CONNECTOR_LVDS, 950 }; 951 952 static const struct drm_display_mode auo_b101xtn01_mode = { 953 .clock = 72000, 954 .hdisplay = 1366, 955 .hsync_start = 1366 + 20, 956 .hsync_end = 1366 + 20 + 70, 957 .htotal = 1366 + 20 + 70, 958 .vdisplay = 768, 959 .vsync_start = 768 + 14, 960 .vsync_end = 768 + 14 + 42, 961 .vtotal = 768 + 14 + 42, 962 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 963 }; 964 965 static const struct panel_desc auo_b101xtn01 = { 966 .modes = &auo_b101xtn01_mode, 967 .num_modes = 1, 968 .bpc = 6, 969 .size = { 970 .width = 223, 971 .height = 125, 972 }, 973 }; 974 975 static const struct drm_display_mode auo_b116xw03_mode = { 976 .clock = 70589, 977 .hdisplay = 1366, 978 .hsync_start = 1366 + 40, 979 .hsync_end = 1366 + 40 + 40, 980 .htotal = 1366 + 40 + 40 + 32, 981 .vdisplay = 768, 982 .vsync_start = 768 + 10, 983 .vsync_end = 768 + 10 + 12, 984 .vtotal = 768 + 10 + 12 + 6, 985 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 986 }; 987 988 static const struct panel_desc auo_b116xw03 = { 989 .modes = &auo_b116xw03_mode, 990 .num_modes = 1, 991 .bpc = 6, 992 .size = { 993 .width = 256, 994 .height = 144, 995 }, 996 .delay = { 997 .prepare = 1, 998 .enable = 200, 999 .disable = 200, 1000 .unprepare = 500, 1001 }, 1002 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1003 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1004 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1005 }; 1006 1007 static const struct display_timing auo_g070vvn01_timings = { 1008 .pixelclock = { 33300000, 34209000, 45000000 }, 1009 .hactive = { 800, 800, 800 }, 1010 .hfront_porch = { 20, 40, 200 }, 1011 .hback_porch = { 87, 40, 1 }, 1012 .hsync_len = { 1, 48, 87 }, 1013 .vactive = { 480, 480, 480 }, 1014 .vfront_porch = { 5, 13, 200 }, 1015 .vback_porch = { 31, 31, 29 }, 1016 .vsync_len = { 1, 1, 3 }, 1017 }; 1018 1019 static const struct panel_desc auo_g070vvn01 = { 1020 .timings = &auo_g070vvn01_timings, 1021 .num_timings = 1, 1022 .bpc = 8, 1023 .size = { 1024 .width = 152, 1025 .height = 91, 1026 }, 1027 .delay = { 1028 .prepare = 200, 1029 .enable = 50, 1030 .disable = 50, 1031 .unprepare = 1000, 1032 }, 1033 }; 1034 1035 static const struct drm_display_mode auo_g101evn010_mode = { 1036 .clock = 68930, 1037 .hdisplay = 1280, 1038 .hsync_start = 1280 + 82, 1039 .hsync_end = 1280 + 82 + 2, 1040 .htotal = 1280 + 82 + 2 + 84, 1041 .vdisplay = 800, 1042 .vsync_start = 800 + 8, 1043 .vsync_end = 800 + 8 + 2, 1044 .vtotal = 800 + 8 + 2 + 6, 1045 }; 1046 1047 static const struct panel_desc auo_g101evn010 = { 1048 .modes = &auo_g101evn010_mode, 1049 .num_modes = 1, 1050 .bpc = 6, 1051 .size = { 1052 .width = 216, 1053 .height = 135, 1054 }, 1055 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1056 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1057 }; 1058 1059 static const struct drm_display_mode auo_g104sn02_mode = { 1060 .clock = 40000, 1061 .hdisplay = 800, 1062 .hsync_start = 800 + 40, 1063 .hsync_end = 800 + 40 + 216, 1064 .htotal = 800 + 40 + 216 + 128, 1065 .vdisplay = 600, 1066 .vsync_start = 600 + 10, 1067 .vsync_end = 600 + 10 + 35, 1068 .vtotal = 600 + 10 + 35 + 2, 1069 }; 1070 1071 static const struct panel_desc auo_g104sn02 = { 1072 .modes = &auo_g104sn02_mode, 1073 .num_modes = 1, 1074 .bpc = 8, 1075 .size = { 1076 .width = 211, 1077 .height = 158, 1078 }, 1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1080 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1081 }; 1082 1083 static const struct display_timing auo_g121ean01_timing = { 1084 .pixelclock = { 60000000, 74400000, 90000000 }, 1085 .hactive = { 1280, 1280, 1280 }, 1086 .hfront_porch = { 20, 50, 100 }, 1087 .hback_porch = { 20, 50, 100 }, 1088 .hsync_len = { 30, 100, 200 }, 1089 .vactive = { 800, 800, 800 }, 1090 .vfront_porch = { 2, 10, 25 }, 1091 .vback_porch = { 2, 10, 25 }, 1092 .vsync_len = { 4, 18, 50 }, 1093 }; 1094 1095 static const struct panel_desc auo_g121ean01 = { 1096 .timings = &auo_g121ean01_timing, 1097 .num_timings = 1, 1098 .bpc = 8, 1099 .size = { 1100 .width = 261, 1101 .height = 163, 1102 }, 1103 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1104 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1105 }; 1106 1107 static const struct display_timing auo_g133han01_timings = { 1108 .pixelclock = { 134000000, 141200000, 149000000 }, 1109 .hactive = { 1920, 1920, 1920 }, 1110 .hfront_porch = { 39, 58, 77 }, 1111 .hback_porch = { 59, 88, 117 }, 1112 .hsync_len = { 28, 42, 56 }, 1113 .vactive = { 1080, 1080, 1080 }, 1114 .vfront_porch = { 3, 8, 11 }, 1115 .vback_porch = { 5, 14, 19 }, 1116 .vsync_len = { 4, 14, 19 }, 1117 }; 1118 1119 static const struct panel_desc auo_g133han01 = { 1120 .timings = &auo_g133han01_timings, 1121 .num_timings = 1, 1122 .bpc = 8, 1123 .size = { 1124 .width = 293, 1125 .height = 165, 1126 }, 1127 .delay = { 1128 .prepare = 200, 1129 .enable = 50, 1130 .disable = 50, 1131 .unprepare = 1000, 1132 }, 1133 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1134 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1135 }; 1136 1137 static const struct display_timing auo_g156han04_timings = { 1138 .pixelclock = { 137000000, 141000000, 146000000 }, 1139 .hactive = { 1920, 1920, 1920 }, 1140 .hfront_porch = { 60, 60, 60 }, 1141 .hback_porch = { 90, 92, 111 }, 1142 .hsync_len = { 32, 32, 32 }, 1143 .vactive = { 1080, 1080, 1080 }, 1144 .vfront_porch = { 12, 12, 12 }, 1145 .vback_porch = { 24, 36, 56 }, 1146 .vsync_len = { 8, 8, 8 }, 1147 }; 1148 1149 static const struct panel_desc auo_g156han04 = { 1150 .timings = &auo_g156han04_timings, 1151 .num_timings = 1, 1152 .bpc = 8, 1153 .size = { 1154 .width = 344, 1155 .height = 194, 1156 }, 1157 .delay = { 1158 .prepare = 50, /* T2 */ 1159 .enable = 200, /* T3 */ 1160 .disable = 110, /* T10 */ 1161 .unprepare = 1000, /* T13 */ 1162 }, 1163 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1164 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1165 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1166 }; 1167 1168 static const struct drm_display_mode auo_g156xtn01_mode = { 1169 .clock = 76000, 1170 .hdisplay = 1366, 1171 .hsync_start = 1366 + 33, 1172 .hsync_end = 1366 + 33 + 67, 1173 .htotal = 1560, 1174 .vdisplay = 768, 1175 .vsync_start = 768 + 4, 1176 .vsync_end = 768 + 4 + 4, 1177 .vtotal = 806, 1178 }; 1179 1180 static const struct panel_desc auo_g156xtn01 = { 1181 .modes = &auo_g156xtn01_mode, 1182 .num_modes = 1, 1183 .bpc = 8, 1184 .size = { 1185 .width = 344, 1186 .height = 194, 1187 }, 1188 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1189 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1190 }; 1191 1192 static const struct display_timing auo_g185han01_timings = { 1193 .pixelclock = { 120000000, 144000000, 175000000 }, 1194 .hactive = { 1920, 1920, 1920 }, 1195 .hfront_porch = { 36, 120, 148 }, 1196 .hback_porch = { 24, 88, 108 }, 1197 .hsync_len = { 20, 48, 64 }, 1198 .vactive = { 1080, 1080, 1080 }, 1199 .vfront_porch = { 6, 10, 40 }, 1200 .vback_porch = { 2, 5, 20 }, 1201 .vsync_len = { 2, 5, 20 }, 1202 }; 1203 1204 static const struct panel_desc auo_g185han01 = { 1205 .timings = &auo_g185han01_timings, 1206 .num_timings = 1, 1207 .bpc = 8, 1208 .size = { 1209 .width = 409, 1210 .height = 230, 1211 }, 1212 .delay = { 1213 .prepare = 50, 1214 .enable = 200, 1215 .disable = 110, 1216 .unprepare = 1000, 1217 }, 1218 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1219 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1220 }; 1221 1222 static const struct display_timing auo_g190ean01_timings = { 1223 .pixelclock = { 90000000, 108000000, 135000000 }, 1224 .hactive = { 1280, 1280, 1280 }, 1225 .hfront_porch = { 126, 184, 1266 }, 1226 .hback_porch = { 84, 122, 844 }, 1227 .hsync_len = { 70, 102, 704 }, 1228 .vactive = { 1024, 1024, 1024 }, 1229 .vfront_porch = { 4, 26, 76 }, 1230 .vback_porch = { 2, 8, 25 }, 1231 .vsync_len = { 2, 8, 25 }, 1232 }; 1233 1234 static const struct panel_desc auo_g190ean01 = { 1235 .timings = &auo_g190ean01_timings, 1236 .num_timings = 1, 1237 .bpc = 8, 1238 .size = { 1239 .width = 376, 1240 .height = 301, 1241 }, 1242 .delay = { 1243 .prepare = 50, 1244 .enable = 200, 1245 .disable = 110, 1246 .unprepare = 1000, 1247 }, 1248 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1249 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1250 }; 1251 1252 static const struct display_timing auo_p320hvn03_timings = { 1253 .pixelclock = { 106000000, 148500000, 164000000 }, 1254 .hactive = { 1920, 1920, 1920 }, 1255 .hfront_porch = { 25, 50, 130 }, 1256 .hback_porch = { 25, 50, 130 }, 1257 .hsync_len = { 20, 40, 105 }, 1258 .vactive = { 1080, 1080, 1080 }, 1259 .vfront_porch = { 8, 17, 150 }, 1260 .vback_porch = { 8, 17, 150 }, 1261 .vsync_len = { 4, 11, 100 }, 1262 }; 1263 1264 static const struct panel_desc auo_p320hvn03 = { 1265 .timings = &auo_p320hvn03_timings, 1266 .num_timings = 1, 1267 .bpc = 8, 1268 .size = { 1269 .width = 698, 1270 .height = 393, 1271 }, 1272 .delay = { 1273 .prepare = 1, 1274 .enable = 450, 1275 .unprepare = 500, 1276 }, 1277 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1278 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1279 }; 1280 1281 static const struct drm_display_mode auo_t215hvn01_mode = { 1282 .clock = 148800, 1283 .hdisplay = 1920, 1284 .hsync_start = 1920 + 88, 1285 .hsync_end = 1920 + 88 + 44, 1286 .htotal = 1920 + 88 + 44 + 148, 1287 .vdisplay = 1080, 1288 .vsync_start = 1080 + 4, 1289 .vsync_end = 1080 + 4 + 5, 1290 .vtotal = 1080 + 4 + 5 + 36, 1291 }; 1292 1293 static const struct panel_desc auo_t215hvn01 = { 1294 .modes = &auo_t215hvn01_mode, 1295 .num_modes = 1, 1296 .bpc = 8, 1297 .size = { 1298 .width = 430, 1299 .height = 270, 1300 }, 1301 .delay = { 1302 .disable = 5, 1303 .unprepare = 1000, 1304 }, 1305 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1306 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1307 }; 1308 1309 static const struct drm_display_mode avic_tm070ddh03_mode = { 1310 .clock = 51200, 1311 .hdisplay = 1024, 1312 .hsync_start = 1024 + 160, 1313 .hsync_end = 1024 + 160 + 4, 1314 .htotal = 1024 + 160 + 4 + 156, 1315 .vdisplay = 600, 1316 .vsync_start = 600 + 17, 1317 .vsync_end = 600 + 17 + 1, 1318 .vtotal = 600 + 17 + 1 + 17, 1319 }; 1320 1321 static const struct panel_desc avic_tm070ddh03 = { 1322 .modes = &avic_tm070ddh03_mode, 1323 .num_modes = 1, 1324 .bpc = 8, 1325 .size = { 1326 .width = 154, 1327 .height = 90, 1328 }, 1329 .delay = { 1330 .prepare = 20, 1331 .enable = 200, 1332 .disable = 200, 1333 }, 1334 }; 1335 1336 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1337 .clock = 30000, 1338 .hdisplay = 800, 1339 .hsync_start = 800 + 40, 1340 .hsync_end = 800 + 40 + 48, 1341 .htotal = 800 + 40 + 48 + 40, 1342 .vdisplay = 480, 1343 .vsync_start = 480 + 13, 1344 .vsync_end = 480 + 13 + 3, 1345 .vtotal = 480 + 13 + 3 + 29, 1346 }; 1347 1348 static const struct panel_desc bananapi_s070wv20_ct16 = { 1349 .modes = &bananapi_s070wv20_ct16_mode, 1350 .num_modes = 1, 1351 .bpc = 6, 1352 .size = { 1353 .width = 154, 1354 .height = 86, 1355 }, 1356 }; 1357 1358 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1359 .clock = 78945, 1360 .hdisplay = 1280, 1361 .hsync_start = 1280 + 0, 1362 .hsync_end = 1280 + 0 + 2, 1363 .htotal = 1280 + 62 + 0 + 2, 1364 .vdisplay = 800, 1365 .vsync_start = 800 + 8, 1366 .vsync_end = 800 + 8 + 2, 1367 .vtotal = 800 + 6 + 8 + 2, 1368 }; 1369 1370 static const struct panel_desc boe_bp082wx1_100 = { 1371 .modes = &boe_bp101wx1_100_mode, 1372 .num_modes = 1, 1373 .bpc = 8, 1374 .size = { 1375 .width = 177, 1376 .height = 110, 1377 }, 1378 .delay = { 1379 .enable = 50, 1380 .disable = 50, 1381 }, 1382 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1383 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1384 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1385 }; 1386 1387 static const struct panel_desc boe_bp101wx1_100 = { 1388 .modes = &boe_bp101wx1_100_mode, 1389 .num_modes = 1, 1390 .bpc = 8, 1391 .size = { 1392 .width = 217, 1393 .height = 136, 1394 }, 1395 .delay = { 1396 .enable = 50, 1397 .disable = 50, 1398 }, 1399 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1400 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1401 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1402 }; 1403 1404 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1405 .pixelclock = { 69922000, 71000000, 72293000 }, 1406 .hactive = { 1280, 1280, 1280 }, 1407 .hfront_porch = { 48, 48, 48 }, 1408 .hback_porch = { 80, 80, 80 }, 1409 .hsync_len = { 32, 32, 32 }, 1410 .vactive = { 800, 800, 800 }, 1411 .vfront_porch = { 3, 3, 3 }, 1412 .vback_porch = { 14, 14, 14 }, 1413 .vsync_len = { 6, 6, 6 }, 1414 }; 1415 1416 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1417 .timings = &boe_ev121wxm_n10_1850_timing, 1418 .num_timings = 1, 1419 .bpc = 8, 1420 .size = { 1421 .width = 261, 1422 .height = 163, 1423 }, 1424 .delay = { 1425 .prepare = 9, 1426 .enable = 300, 1427 .unprepare = 300, 1428 .disable = 560, 1429 }, 1430 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1431 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1432 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1433 }; 1434 1435 static const struct drm_display_mode boe_hv070wsa_mode = { 1436 .clock = 42105, 1437 .hdisplay = 1024, 1438 .hsync_start = 1024 + 30, 1439 .hsync_end = 1024 + 30 + 30, 1440 .htotal = 1024 + 30 + 30 + 30, 1441 .vdisplay = 600, 1442 .vsync_start = 600 + 10, 1443 .vsync_end = 600 + 10 + 10, 1444 .vtotal = 600 + 10 + 10 + 10, 1445 }; 1446 1447 static const struct panel_desc boe_hv070wsa = { 1448 .modes = &boe_hv070wsa_mode, 1449 .num_modes = 1, 1450 .bpc = 8, 1451 .size = { 1452 .width = 154, 1453 .height = 90, 1454 }, 1455 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1456 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1457 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1458 }; 1459 1460 static const struct display_timing cct_cmt430b19n00_timing = { 1461 .pixelclock = { 8000000, 9000000, 12000000 }, 1462 .hactive = { 480, 480, 480 }, 1463 .hfront_porch = { 2, 8, 75 }, 1464 .hback_porch = { 3, 43, 43 }, 1465 .hsync_len = { 2, 4, 75 }, 1466 .vactive = { 272, 272, 272 }, 1467 .vfront_porch = { 2, 8, 37 }, 1468 .vback_porch = { 2, 12, 12 }, 1469 .vsync_len = { 2, 4, 37 }, 1470 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1471 }; 1472 1473 static const struct panel_desc cct_cmt430b19n00 = { 1474 .timings = &cct_cmt430b19n00_timing, 1475 .num_timings = 1, 1476 .bpc = 8, 1477 .size = { 1478 .width = 95, 1479 .height = 53, 1480 }, 1481 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1482 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1483 .connector_type = DRM_MODE_CONNECTOR_DPI, 1484 }; 1485 1486 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1487 .clock = 9000, 1488 .hdisplay = 480, 1489 .hsync_start = 480 + 5, 1490 .hsync_end = 480 + 5 + 5, 1491 .htotal = 480 + 5 + 5 + 40, 1492 .vdisplay = 272, 1493 .vsync_start = 272 + 8, 1494 .vsync_end = 272 + 8 + 8, 1495 .vtotal = 272 + 8 + 8 + 8, 1496 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1497 }; 1498 1499 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1500 .modes = &cdtech_s043wq26h_ct7_mode, 1501 .num_modes = 1, 1502 .bpc = 8, 1503 .size = { 1504 .width = 95, 1505 .height = 54, 1506 }, 1507 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1508 }; 1509 1510 /* S070PWS19HP-FC21 2017/04/22 */ 1511 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1512 .clock = 51200, 1513 .hdisplay = 1024, 1514 .hsync_start = 1024 + 160, 1515 .hsync_end = 1024 + 160 + 20, 1516 .htotal = 1024 + 160 + 20 + 140, 1517 .vdisplay = 600, 1518 .vsync_start = 600 + 12, 1519 .vsync_end = 600 + 12 + 3, 1520 .vtotal = 600 + 12 + 3 + 20, 1521 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1522 }; 1523 1524 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1525 .modes = &cdtech_s070pws19hp_fc21_mode, 1526 .num_modes = 1, 1527 .bpc = 6, 1528 .size = { 1529 .width = 154, 1530 .height = 86, 1531 }, 1532 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1533 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1534 .connector_type = DRM_MODE_CONNECTOR_DPI, 1535 }; 1536 1537 /* S070SWV29HG-DC44 2017/09/21 */ 1538 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1539 .clock = 33300, 1540 .hdisplay = 800, 1541 .hsync_start = 800 + 210, 1542 .hsync_end = 800 + 210 + 2, 1543 .htotal = 800 + 210 + 2 + 44, 1544 .vdisplay = 480, 1545 .vsync_start = 480 + 22, 1546 .vsync_end = 480 + 22 + 2, 1547 .vtotal = 480 + 22 + 2 + 21, 1548 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1549 }; 1550 1551 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1552 .modes = &cdtech_s070swv29hg_dc44_mode, 1553 .num_modes = 1, 1554 .bpc = 6, 1555 .size = { 1556 .width = 154, 1557 .height = 86, 1558 }, 1559 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1560 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1561 .connector_type = DRM_MODE_CONNECTOR_DPI, 1562 }; 1563 1564 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1565 .clock = 35000, 1566 .hdisplay = 800, 1567 .hsync_start = 800 + 40, 1568 .hsync_end = 800 + 40 + 40, 1569 .htotal = 800 + 40 + 40 + 48, 1570 .vdisplay = 480, 1571 .vsync_start = 480 + 29, 1572 .vsync_end = 480 + 29 + 13, 1573 .vtotal = 480 + 29 + 13 + 3, 1574 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1575 }; 1576 1577 static const struct panel_desc cdtech_s070wv95_ct16 = { 1578 .modes = &cdtech_s070wv95_ct16_mode, 1579 .num_modes = 1, 1580 .bpc = 8, 1581 .size = { 1582 .width = 154, 1583 .height = 85, 1584 }, 1585 }; 1586 1587 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1588 .pixelclock = { 68900000, 71100000, 73400000 }, 1589 .hactive = { 1280, 1280, 1280 }, 1590 .hfront_porch = { 65, 80, 95 }, 1591 .hback_porch = { 64, 79, 94 }, 1592 .hsync_len = { 1, 1, 1 }, 1593 .vactive = { 800, 800, 800 }, 1594 .vfront_porch = { 7, 11, 14 }, 1595 .vback_porch = { 7, 11, 14 }, 1596 .vsync_len = { 1, 1, 1 }, 1597 .flags = DISPLAY_FLAGS_DE_HIGH, 1598 }; 1599 1600 static const struct panel_desc chefree_ch101olhlwh_002 = { 1601 .timings = &chefree_ch101olhlwh_002_timing, 1602 .num_timings = 1, 1603 .bpc = 8, 1604 .size = { 1605 .width = 217, 1606 .height = 135, 1607 }, 1608 .delay = { 1609 .enable = 200, 1610 .disable = 200, 1611 }, 1612 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1613 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1614 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1615 }; 1616 1617 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1618 .clock = 66770, 1619 .hdisplay = 800, 1620 .hsync_start = 800 + 49, 1621 .hsync_end = 800 + 49 + 33, 1622 .htotal = 800 + 49 + 33 + 17, 1623 .vdisplay = 1280, 1624 .vsync_start = 1280 + 1, 1625 .vsync_end = 1280 + 1 + 7, 1626 .vtotal = 1280 + 1 + 7 + 15, 1627 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1628 }; 1629 1630 static const struct panel_desc chunghwa_claa070wp03xg = { 1631 .modes = &chunghwa_claa070wp03xg_mode, 1632 .num_modes = 1, 1633 .bpc = 6, 1634 .size = { 1635 .width = 94, 1636 .height = 150, 1637 }, 1638 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1639 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1640 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1641 }; 1642 1643 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1644 .clock = 72070, 1645 .hdisplay = 1366, 1646 .hsync_start = 1366 + 58, 1647 .hsync_end = 1366 + 58 + 58, 1648 .htotal = 1366 + 58 + 58 + 58, 1649 .vdisplay = 768, 1650 .vsync_start = 768 + 4, 1651 .vsync_end = 768 + 4 + 4, 1652 .vtotal = 768 + 4 + 4 + 4, 1653 }; 1654 1655 static const struct panel_desc chunghwa_claa101wa01a = { 1656 .modes = &chunghwa_claa101wa01a_mode, 1657 .num_modes = 1, 1658 .bpc = 6, 1659 .size = { 1660 .width = 220, 1661 .height = 120, 1662 }, 1663 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1664 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1665 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1666 }; 1667 1668 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1669 .clock = 69300, 1670 .hdisplay = 1366, 1671 .hsync_start = 1366 + 48, 1672 .hsync_end = 1366 + 48 + 32, 1673 .htotal = 1366 + 48 + 32 + 20, 1674 .vdisplay = 768, 1675 .vsync_start = 768 + 16, 1676 .vsync_end = 768 + 16 + 8, 1677 .vtotal = 768 + 16 + 8 + 16, 1678 }; 1679 1680 static const struct panel_desc chunghwa_claa101wb01 = { 1681 .modes = &chunghwa_claa101wb01_mode, 1682 .num_modes = 1, 1683 .bpc = 6, 1684 .size = { 1685 .width = 223, 1686 .height = 125, 1687 }, 1688 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1689 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1690 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1691 }; 1692 1693 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1694 .pixelclock = { 5000000, 9000000, 12000000 }, 1695 .hactive = { 480, 480, 480 }, 1696 .hfront_porch = { 12, 12, 12 }, 1697 .hback_porch = { 12, 12, 12 }, 1698 .hsync_len = { 21, 21, 21 }, 1699 .vactive = { 272, 272, 272 }, 1700 .vfront_porch = { 4, 4, 4 }, 1701 .vback_porch = { 4, 4, 4 }, 1702 .vsync_len = { 8, 8, 8 }, 1703 }; 1704 1705 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1706 .timings = &dataimage_fg040346dsswbg04_timing, 1707 .num_timings = 1, 1708 .bpc = 8, 1709 .size = { 1710 .width = 95, 1711 .height = 54, 1712 }, 1713 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1714 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1715 .connector_type = DRM_MODE_CONNECTOR_DPI, 1716 }; 1717 1718 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1719 .pixelclock = { 68900000, 71110000, 73400000 }, 1720 .hactive = { 1280, 1280, 1280 }, 1721 .vactive = { 800, 800, 800 }, 1722 .hback_porch = { 100, 100, 100 }, 1723 .hfront_porch = { 100, 100, 100 }, 1724 .vback_porch = { 5, 5, 5 }, 1725 .vfront_porch = { 5, 5, 5 }, 1726 .hsync_len = { 24, 24, 24 }, 1727 .vsync_len = { 3, 3, 3 }, 1728 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1729 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1730 }; 1731 1732 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1733 .timings = &dataimage_fg1001l0dsswmg01_timing, 1734 .num_timings = 1, 1735 .bpc = 8, 1736 .size = { 1737 .width = 217, 1738 .height = 136, 1739 }, 1740 }; 1741 1742 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1743 .clock = 33260, 1744 .hdisplay = 800, 1745 .hsync_start = 800 + 40, 1746 .hsync_end = 800 + 40 + 128, 1747 .htotal = 800 + 40 + 128 + 88, 1748 .vdisplay = 480, 1749 .vsync_start = 480 + 10, 1750 .vsync_end = 480 + 10 + 2, 1751 .vtotal = 480 + 10 + 2 + 33, 1752 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1753 }; 1754 1755 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1756 .modes = &dataimage_scf0700c48ggu18_mode, 1757 .num_modes = 1, 1758 .bpc = 8, 1759 .size = { 1760 .width = 152, 1761 .height = 91, 1762 }, 1763 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1764 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1765 }; 1766 1767 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1768 .pixelclock = { 45000000, 51200000, 57000000 }, 1769 .hactive = { 1024, 1024, 1024 }, 1770 .hfront_porch = { 100, 106, 113 }, 1771 .hback_porch = { 100, 106, 113 }, 1772 .hsync_len = { 100, 108, 114 }, 1773 .vactive = { 600, 600, 600 }, 1774 .vfront_porch = { 8, 11, 15 }, 1775 .vback_porch = { 8, 11, 15 }, 1776 .vsync_len = { 9, 13, 15 }, 1777 .flags = DISPLAY_FLAGS_DE_HIGH, 1778 }; 1779 1780 static const struct panel_desc dlc_dlc0700yzg_1 = { 1781 .timings = &dlc_dlc0700yzg_1_timing, 1782 .num_timings = 1, 1783 .bpc = 6, 1784 .size = { 1785 .width = 154, 1786 .height = 86, 1787 }, 1788 .delay = { 1789 .prepare = 30, 1790 .enable = 200, 1791 .disable = 200, 1792 }, 1793 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1794 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1795 }; 1796 1797 static const struct display_timing dlc_dlc1010gig_timing = { 1798 .pixelclock = { 68900000, 71100000, 73400000 }, 1799 .hactive = { 1280, 1280, 1280 }, 1800 .hfront_porch = { 43, 53, 63 }, 1801 .hback_porch = { 43, 53, 63 }, 1802 .hsync_len = { 44, 54, 64 }, 1803 .vactive = { 800, 800, 800 }, 1804 .vfront_porch = { 5, 8, 11 }, 1805 .vback_porch = { 5, 8, 11 }, 1806 .vsync_len = { 5, 7, 11 }, 1807 .flags = DISPLAY_FLAGS_DE_HIGH, 1808 }; 1809 1810 static const struct panel_desc dlc_dlc1010gig = { 1811 .timings = &dlc_dlc1010gig_timing, 1812 .num_timings = 1, 1813 .bpc = 8, 1814 .size = { 1815 .width = 216, 1816 .height = 135, 1817 }, 1818 .delay = { 1819 .prepare = 60, 1820 .enable = 150, 1821 .disable = 100, 1822 .unprepare = 60, 1823 }, 1824 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1825 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1826 }; 1827 1828 static const struct drm_display_mode edt_et035012dm6_mode = { 1829 .clock = 6500, 1830 .hdisplay = 320, 1831 .hsync_start = 320 + 20, 1832 .hsync_end = 320 + 20 + 30, 1833 .htotal = 320 + 20 + 68, 1834 .vdisplay = 240, 1835 .vsync_start = 240 + 4, 1836 .vsync_end = 240 + 4 + 4, 1837 .vtotal = 240 + 4 + 4 + 14, 1838 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1839 }; 1840 1841 static const struct panel_desc edt_et035012dm6 = { 1842 .modes = &edt_et035012dm6_mode, 1843 .num_modes = 1, 1844 .bpc = 8, 1845 .size = { 1846 .width = 70, 1847 .height = 52, 1848 }, 1849 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1850 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1851 }; 1852 1853 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1854 .clock = 6520, 1855 .hdisplay = 320, 1856 .hsync_start = 320 + 20, 1857 .hsync_end = 320 + 20 + 68, 1858 .htotal = 320 + 20 + 68, 1859 .vdisplay = 240, 1860 .vsync_start = 240 + 4, 1861 .vsync_end = 240 + 4 + 18, 1862 .vtotal = 240 + 4 + 18, 1863 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1864 }; 1865 1866 static const struct panel_desc edt_etm0350g0dh6 = { 1867 .modes = &edt_etm0350g0dh6_mode, 1868 .num_modes = 1, 1869 .bpc = 6, 1870 .size = { 1871 .width = 70, 1872 .height = 53, 1873 }, 1874 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1875 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1876 .connector_type = DRM_MODE_CONNECTOR_DPI, 1877 }; 1878 1879 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1880 .clock = 10870, 1881 .hdisplay = 480, 1882 .hsync_start = 480 + 8, 1883 .hsync_end = 480 + 8 + 4, 1884 .htotal = 480 + 8 + 4 + 41, 1885 1886 /* 1887 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1888 * fb_align 1889 */ 1890 1891 .vdisplay = 288, 1892 .vsync_start = 288 + 2, 1893 .vsync_end = 288 + 2 + 4, 1894 .vtotal = 288 + 2 + 4 + 10, 1895 }; 1896 1897 static const struct panel_desc edt_etm043080dh6gp = { 1898 .modes = &edt_etm043080dh6gp_mode, 1899 .num_modes = 1, 1900 .bpc = 8, 1901 .size = { 1902 .width = 100, 1903 .height = 65, 1904 }, 1905 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1906 .connector_type = DRM_MODE_CONNECTOR_DPI, 1907 }; 1908 1909 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1910 .clock = 9000, 1911 .hdisplay = 480, 1912 .hsync_start = 480 + 2, 1913 .hsync_end = 480 + 2 + 41, 1914 .htotal = 480 + 2 + 41 + 2, 1915 .vdisplay = 272, 1916 .vsync_start = 272 + 2, 1917 .vsync_end = 272 + 2 + 10, 1918 .vtotal = 272 + 2 + 10 + 2, 1919 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1920 }; 1921 1922 static const struct panel_desc edt_etm0430g0dh6 = { 1923 .modes = &edt_etm0430g0dh6_mode, 1924 .num_modes = 1, 1925 .bpc = 6, 1926 .size = { 1927 .width = 95, 1928 .height = 54, 1929 }, 1930 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1931 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1932 .connector_type = DRM_MODE_CONNECTOR_DPI, 1933 }; 1934 1935 static const struct drm_display_mode edt_et057090dhu_mode = { 1936 .clock = 25175, 1937 .hdisplay = 640, 1938 .hsync_start = 640 + 16, 1939 .hsync_end = 640 + 16 + 30, 1940 .htotal = 640 + 16 + 30 + 114, 1941 .vdisplay = 480, 1942 .vsync_start = 480 + 10, 1943 .vsync_end = 480 + 10 + 3, 1944 .vtotal = 480 + 10 + 3 + 32, 1945 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1946 }; 1947 1948 static const struct panel_desc edt_et057090dhu = { 1949 .modes = &edt_et057090dhu_mode, 1950 .num_modes = 1, 1951 .bpc = 6, 1952 .size = { 1953 .width = 115, 1954 .height = 86, 1955 }, 1956 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1957 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1958 .connector_type = DRM_MODE_CONNECTOR_DPI, 1959 }; 1960 1961 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1962 .clock = 33260, 1963 .hdisplay = 800, 1964 .hsync_start = 800 + 40, 1965 .hsync_end = 800 + 40 + 128, 1966 .htotal = 800 + 40 + 128 + 88, 1967 .vdisplay = 480, 1968 .vsync_start = 480 + 10, 1969 .vsync_end = 480 + 10 + 2, 1970 .vtotal = 480 + 10 + 2 + 33, 1971 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1972 }; 1973 1974 static const struct panel_desc edt_etm0700g0dh6 = { 1975 .modes = &edt_etm0700g0dh6_mode, 1976 .num_modes = 1, 1977 .bpc = 6, 1978 .size = { 1979 .width = 152, 1980 .height = 91, 1981 }, 1982 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1983 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1984 .connector_type = DRM_MODE_CONNECTOR_DPI, 1985 }; 1986 1987 static const struct panel_desc edt_etm0700g0bdh6 = { 1988 .modes = &edt_etm0700g0dh6_mode, 1989 .num_modes = 1, 1990 .bpc = 6, 1991 .size = { 1992 .width = 152, 1993 .height = 91, 1994 }, 1995 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1996 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1997 .connector_type = DRM_MODE_CONNECTOR_DPI, 1998 }; 1999 2000 static const struct display_timing edt_etml0700y5dha_timing = { 2001 .pixelclock = { 40800000, 51200000, 67200000 }, 2002 .hactive = { 1024, 1024, 1024 }, 2003 .hfront_porch = { 30, 106, 125 }, 2004 .hback_porch = { 30, 106, 125 }, 2005 .hsync_len = { 30, 108, 126 }, 2006 .vactive = { 600, 600, 600 }, 2007 .vfront_porch = { 3, 12, 67}, 2008 .vback_porch = { 3, 12, 67 }, 2009 .vsync_len = { 4, 11, 66 }, 2010 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2011 DISPLAY_FLAGS_DE_HIGH, 2012 }; 2013 2014 static const struct panel_desc edt_etml0700y5dha = { 2015 .timings = &edt_etml0700y5dha_timing, 2016 .num_timings = 1, 2017 .bpc = 8, 2018 .size = { 2019 .width = 155, 2020 .height = 86, 2021 }, 2022 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2023 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2024 }; 2025 2026 static const struct display_timing edt_etml1010g3dra_timing = { 2027 .pixelclock = { 66300000, 72400000, 78900000 }, 2028 .hactive = { 1280, 1280, 1280 }, 2029 .hfront_porch = { 12, 72, 132 }, 2030 .hback_porch = { 86, 86, 86 }, 2031 .hsync_len = { 2, 2, 2 }, 2032 .vactive = { 800, 800, 800 }, 2033 .vfront_porch = { 1, 15, 49 }, 2034 .vback_porch = { 21, 21, 21 }, 2035 .vsync_len = { 2, 2, 2 }, 2036 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2037 DISPLAY_FLAGS_DE_HIGH, 2038 }; 2039 2040 static const struct panel_desc edt_etml1010g3dra = { 2041 .timings = &edt_etml1010g3dra_timing, 2042 .num_timings = 1, 2043 .bpc = 8, 2044 .size = { 2045 .width = 216, 2046 .height = 135, 2047 }, 2048 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2049 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2050 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2051 }; 2052 2053 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2054 .clock = 25175, 2055 .hdisplay = 640, 2056 .hsync_start = 640, 2057 .hsync_end = 640 + 16, 2058 .htotal = 640 + 16 + 30 + 114, 2059 .vdisplay = 480, 2060 .vsync_start = 480 + 10, 2061 .vsync_end = 480 + 10 + 3, 2062 .vtotal = 480 + 10 + 3 + 35, 2063 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2064 }; 2065 2066 static const struct panel_desc edt_etmv570g2dhu = { 2067 .modes = &edt_etmv570g2dhu_mode, 2068 .num_modes = 1, 2069 .bpc = 6, 2070 .size = { 2071 .width = 115, 2072 .height = 86, 2073 }, 2074 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2075 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2076 .connector_type = DRM_MODE_CONNECTOR_DPI, 2077 }; 2078 2079 static const struct display_timing eink_vb3300_kca_timing = { 2080 .pixelclock = { 40000000, 40000000, 40000000 }, 2081 .hactive = { 334, 334, 334 }, 2082 .hfront_porch = { 1, 1, 1 }, 2083 .hback_porch = { 1, 1, 1 }, 2084 .hsync_len = { 1, 1, 1 }, 2085 .vactive = { 1405, 1405, 1405 }, 2086 .vfront_porch = { 1, 1, 1 }, 2087 .vback_porch = { 1, 1, 1 }, 2088 .vsync_len = { 1, 1, 1 }, 2089 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2090 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2091 }; 2092 2093 static const struct panel_desc eink_vb3300_kca = { 2094 .timings = &eink_vb3300_kca_timing, 2095 .num_timings = 1, 2096 .bpc = 6, 2097 .size = { 2098 .width = 157, 2099 .height = 209, 2100 }, 2101 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2102 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2103 .connector_type = DRM_MODE_CONNECTOR_DPI, 2104 }; 2105 2106 static const struct display_timing evervision_vgg644804_timing = { 2107 .pixelclock = { 25175000, 25175000, 25175000 }, 2108 .hactive = { 640, 640, 640 }, 2109 .hfront_porch = { 16, 16, 16 }, 2110 .hback_porch = { 82, 114, 170 }, 2111 .hsync_len = { 5, 30, 30 }, 2112 .vactive = { 480, 480, 480 }, 2113 .vfront_porch = { 10, 10, 10 }, 2114 .vback_porch = { 30, 32, 34 }, 2115 .vsync_len = { 1, 3, 5 }, 2116 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2117 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2118 DISPLAY_FLAGS_SYNC_POSEDGE, 2119 }; 2120 2121 static const struct panel_desc evervision_vgg644804 = { 2122 .timings = &evervision_vgg644804_timing, 2123 .num_timings = 1, 2124 .bpc = 8, 2125 .size = { 2126 .width = 115, 2127 .height = 86, 2128 }, 2129 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2130 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2131 }; 2132 2133 static const struct display_timing evervision_vgg804821_timing = { 2134 .pixelclock = { 27600000, 33300000, 50000000 }, 2135 .hactive = { 800, 800, 800 }, 2136 .hfront_porch = { 40, 66, 70 }, 2137 .hback_porch = { 40, 67, 70 }, 2138 .hsync_len = { 40, 67, 70 }, 2139 .vactive = { 480, 480, 480 }, 2140 .vfront_porch = { 6, 10, 10 }, 2141 .vback_porch = { 7, 11, 11 }, 2142 .vsync_len = { 7, 11, 11 }, 2143 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2144 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2145 DISPLAY_FLAGS_SYNC_NEGEDGE, 2146 }; 2147 2148 static const struct panel_desc evervision_vgg804821 = { 2149 .timings = &evervision_vgg804821_timing, 2150 .num_timings = 1, 2151 .bpc = 8, 2152 .size = { 2153 .width = 108, 2154 .height = 64, 2155 }, 2156 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2157 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2158 }; 2159 2160 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2161 .clock = 32260, 2162 .hdisplay = 800, 2163 .hsync_start = 800 + 168, 2164 .hsync_end = 800 + 168 + 64, 2165 .htotal = 800 + 168 + 64 + 88, 2166 .vdisplay = 480, 2167 .vsync_start = 480 + 37, 2168 .vsync_end = 480 + 37 + 2, 2169 .vtotal = 480 + 37 + 2 + 8, 2170 }; 2171 2172 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2173 .modes = &foxlink_fl500wvr00_a0t_mode, 2174 .num_modes = 1, 2175 .bpc = 8, 2176 .size = { 2177 .width = 108, 2178 .height = 65, 2179 }, 2180 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2181 }; 2182 2183 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2184 { /* 60 Hz */ 2185 .clock = 6000, 2186 .hdisplay = 320, 2187 .hsync_start = 320 + 44, 2188 .hsync_end = 320 + 44 + 16, 2189 .htotal = 320 + 44 + 16 + 20, 2190 .vdisplay = 240, 2191 .vsync_start = 240 + 2, 2192 .vsync_end = 240 + 2 + 6, 2193 .vtotal = 240 + 2 + 6 + 2, 2194 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2195 }, 2196 { /* 50 Hz */ 2197 .clock = 5400, 2198 .hdisplay = 320, 2199 .hsync_start = 320 + 56, 2200 .hsync_end = 320 + 56 + 16, 2201 .htotal = 320 + 56 + 16 + 40, 2202 .vdisplay = 240, 2203 .vsync_start = 240 + 2, 2204 .vsync_end = 240 + 2 + 6, 2205 .vtotal = 240 + 2 + 6 + 2, 2206 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2207 }, 2208 }; 2209 2210 static const struct panel_desc frida_frd350h54004 = { 2211 .modes = frida_frd350h54004_modes, 2212 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2213 .bpc = 8, 2214 .size = { 2215 .width = 77, 2216 .height = 64, 2217 }, 2218 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2219 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2220 .connector_type = DRM_MODE_CONNECTOR_DPI, 2221 }; 2222 2223 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2224 .clock = 67185, 2225 .hdisplay = 800, 2226 .hsync_start = 800 + 20, 2227 .hsync_end = 800 + 20 + 24, 2228 .htotal = 800 + 20 + 24 + 20, 2229 .vdisplay = 1280, 2230 .vsync_start = 1280 + 4, 2231 .vsync_end = 1280 + 4 + 8, 2232 .vtotal = 1280 + 4 + 8 + 4, 2233 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2234 }; 2235 2236 static const struct panel_desc friendlyarm_hd702e = { 2237 .modes = &friendlyarm_hd702e_mode, 2238 .num_modes = 1, 2239 .size = { 2240 .width = 94, 2241 .height = 151, 2242 }, 2243 }; 2244 2245 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2246 .clock = 9000, 2247 .hdisplay = 480, 2248 .hsync_start = 480 + 5, 2249 .hsync_end = 480 + 5 + 1, 2250 .htotal = 480 + 5 + 1 + 40, 2251 .vdisplay = 272, 2252 .vsync_start = 272 + 8, 2253 .vsync_end = 272 + 8 + 1, 2254 .vtotal = 272 + 8 + 1 + 8, 2255 }; 2256 2257 static const struct panel_desc giantplus_gpg482739qs5 = { 2258 .modes = &giantplus_gpg482739qs5_mode, 2259 .num_modes = 1, 2260 .bpc = 8, 2261 .size = { 2262 .width = 95, 2263 .height = 54, 2264 }, 2265 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2266 }; 2267 2268 static const struct display_timing giantplus_gpm940b0_timing = { 2269 .pixelclock = { 13500000, 27000000, 27500000 }, 2270 .hactive = { 320, 320, 320 }, 2271 .hfront_porch = { 14, 686, 718 }, 2272 .hback_porch = { 50, 70, 255 }, 2273 .hsync_len = { 1, 1, 1 }, 2274 .vactive = { 240, 240, 240 }, 2275 .vfront_porch = { 1, 1, 179 }, 2276 .vback_porch = { 1, 21, 31 }, 2277 .vsync_len = { 1, 1, 6 }, 2278 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2279 }; 2280 2281 static const struct panel_desc giantplus_gpm940b0 = { 2282 .timings = &giantplus_gpm940b0_timing, 2283 .num_timings = 1, 2284 .bpc = 8, 2285 .size = { 2286 .width = 60, 2287 .height = 45, 2288 }, 2289 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2290 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2291 }; 2292 2293 static const struct display_timing hannstar_hsd070pww1_timing = { 2294 .pixelclock = { 64300000, 71100000, 82000000 }, 2295 .hactive = { 1280, 1280, 1280 }, 2296 .hfront_porch = { 1, 1, 10 }, 2297 .hback_porch = { 1, 1, 10 }, 2298 /* 2299 * According to the data sheet, the minimum horizontal blanking interval 2300 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2301 * minimum working horizontal blanking interval to be 60 clocks. 2302 */ 2303 .hsync_len = { 58, 158, 661 }, 2304 .vactive = { 800, 800, 800 }, 2305 .vfront_porch = { 1, 1, 10 }, 2306 .vback_porch = { 1, 1, 10 }, 2307 .vsync_len = { 1, 21, 203 }, 2308 .flags = DISPLAY_FLAGS_DE_HIGH, 2309 }; 2310 2311 static const struct panel_desc hannstar_hsd070pww1 = { 2312 .timings = &hannstar_hsd070pww1_timing, 2313 .num_timings = 1, 2314 .bpc = 6, 2315 .size = { 2316 .width = 151, 2317 .height = 94, 2318 }, 2319 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2320 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2321 }; 2322 2323 static const struct display_timing hannstar_hsd100pxn1_timing = { 2324 .pixelclock = { 55000000, 65000000, 75000000 }, 2325 .hactive = { 1024, 1024, 1024 }, 2326 .hfront_porch = { 40, 40, 40 }, 2327 .hback_porch = { 220, 220, 220 }, 2328 .hsync_len = { 20, 60, 100 }, 2329 .vactive = { 768, 768, 768 }, 2330 .vfront_porch = { 7, 7, 7 }, 2331 .vback_porch = { 21, 21, 21 }, 2332 .vsync_len = { 10, 10, 10 }, 2333 .flags = DISPLAY_FLAGS_DE_HIGH, 2334 }; 2335 2336 static const struct panel_desc hannstar_hsd100pxn1 = { 2337 .timings = &hannstar_hsd100pxn1_timing, 2338 .num_timings = 1, 2339 .bpc = 6, 2340 .size = { 2341 .width = 203, 2342 .height = 152, 2343 }, 2344 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2345 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2346 }; 2347 2348 static const struct display_timing hannstar_hsd101pww2_timing = { 2349 .pixelclock = { 64300000, 71100000, 82000000 }, 2350 .hactive = { 1280, 1280, 1280 }, 2351 .hfront_porch = { 1, 1, 10 }, 2352 .hback_porch = { 1, 1, 10 }, 2353 .hsync_len = { 58, 158, 661 }, 2354 .vactive = { 800, 800, 800 }, 2355 .vfront_porch = { 1, 1, 10 }, 2356 .vback_porch = { 1, 1, 10 }, 2357 .vsync_len = { 1, 21, 203 }, 2358 .flags = DISPLAY_FLAGS_DE_HIGH, 2359 }; 2360 2361 static const struct panel_desc hannstar_hsd101pww2 = { 2362 .timings = &hannstar_hsd101pww2_timing, 2363 .num_timings = 1, 2364 .bpc = 8, 2365 .size = { 2366 .width = 217, 2367 .height = 136, 2368 }, 2369 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2370 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2371 }; 2372 2373 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2374 .clock = 33333, 2375 .hdisplay = 800, 2376 .hsync_start = 800 + 85, 2377 .hsync_end = 800 + 85 + 86, 2378 .htotal = 800 + 85 + 86 + 85, 2379 .vdisplay = 480, 2380 .vsync_start = 480 + 16, 2381 .vsync_end = 480 + 16 + 13, 2382 .vtotal = 480 + 16 + 13 + 16, 2383 }; 2384 2385 static const struct panel_desc hitachi_tx23d38vm0caa = { 2386 .modes = &hitachi_tx23d38vm0caa_mode, 2387 .num_modes = 1, 2388 .bpc = 6, 2389 .size = { 2390 .width = 195, 2391 .height = 117, 2392 }, 2393 .delay = { 2394 .enable = 160, 2395 .disable = 160, 2396 }, 2397 }; 2398 2399 static const struct drm_display_mode innolux_at043tn24_mode = { 2400 .clock = 9000, 2401 .hdisplay = 480, 2402 .hsync_start = 480 + 2, 2403 .hsync_end = 480 + 2 + 41, 2404 .htotal = 480 + 2 + 41 + 2, 2405 .vdisplay = 272, 2406 .vsync_start = 272 + 2, 2407 .vsync_end = 272 + 2 + 10, 2408 .vtotal = 272 + 2 + 10 + 2, 2409 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2410 }; 2411 2412 static const struct panel_desc innolux_at043tn24 = { 2413 .modes = &innolux_at043tn24_mode, 2414 .num_modes = 1, 2415 .bpc = 8, 2416 .size = { 2417 .width = 95, 2418 .height = 54, 2419 }, 2420 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2421 .connector_type = DRM_MODE_CONNECTOR_DPI, 2422 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2423 }; 2424 2425 static const struct drm_display_mode innolux_at070tn92_mode = { 2426 .clock = 33333, 2427 .hdisplay = 800, 2428 .hsync_start = 800 + 210, 2429 .hsync_end = 800 + 210 + 20, 2430 .htotal = 800 + 210 + 20 + 46, 2431 .vdisplay = 480, 2432 .vsync_start = 480 + 22, 2433 .vsync_end = 480 + 22 + 10, 2434 .vtotal = 480 + 22 + 23 + 10, 2435 }; 2436 2437 static const struct panel_desc innolux_at070tn92 = { 2438 .modes = &innolux_at070tn92_mode, 2439 .num_modes = 1, 2440 .size = { 2441 .width = 154, 2442 .height = 86, 2443 }, 2444 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2445 }; 2446 2447 static const struct display_timing innolux_g070ace_l01_timing = { 2448 .pixelclock = { 25200000, 35000000, 35700000 }, 2449 .hactive = { 800, 800, 800 }, 2450 .hfront_porch = { 30, 32, 87 }, 2451 .hback_porch = { 30, 32, 87 }, 2452 .hsync_len = { 1, 1, 1 }, 2453 .vactive = { 480, 480, 480 }, 2454 .vfront_porch = { 3, 3, 3 }, 2455 .vback_porch = { 13, 13, 13 }, 2456 .vsync_len = { 1, 1, 4 }, 2457 .flags = DISPLAY_FLAGS_DE_HIGH, 2458 }; 2459 2460 static const struct panel_desc innolux_g070ace_l01 = { 2461 .timings = &innolux_g070ace_l01_timing, 2462 .num_timings = 1, 2463 .bpc = 8, 2464 .size = { 2465 .width = 152, 2466 .height = 91, 2467 }, 2468 .delay = { 2469 .prepare = 10, 2470 .enable = 50, 2471 .disable = 50, 2472 .unprepare = 500, 2473 }, 2474 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2475 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2476 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2477 }; 2478 2479 static const struct display_timing innolux_g070y2_l01_timing = { 2480 .pixelclock = { 28000000, 29500000, 32000000 }, 2481 .hactive = { 800, 800, 800 }, 2482 .hfront_porch = { 61, 91, 141 }, 2483 .hback_porch = { 60, 90, 140 }, 2484 .hsync_len = { 12, 12, 12 }, 2485 .vactive = { 480, 480, 480 }, 2486 .vfront_porch = { 4, 9, 30 }, 2487 .vback_porch = { 4, 8, 28 }, 2488 .vsync_len = { 2, 2, 2 }, 2489 .flags = DISPLAY_FLAGS_DE_HIGH, 2490 }; 2491 2492 static const struct panel_desc innolux_g070y2_l01 = { 2493 .timings = &innolux_g070y2_l01_timing, 2494 .num_timings = 1, 2495 .bpc = 8, 2496 .size = { 2497 .width = 152, 2498 .height = 91, 2499 }, 2500 .delay = { 2501 .prepare = 10, 2502 .enable = 100, 2503 .disable = 100, 2504 .unprepare = 800, 2505 }, 2506 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2507 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2508 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2509 }; 2510 2511 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2512 .clock = 33333, 2513 .hdisplay = 800, 2514 .hsync_start = 800 + 210, 2515 .hsync_end = 800 + 210 + 20, 2516 .htotal = 800 + 210 + 20 + 46, 2517 .vdisplay = 480, 2518 .vsync_start = 480 + 22, 2519 .vsync_end = 480 + 22 + 10, 2520 .vtotal = 480 + 22 + 23 + 10, 2521 }; 2522 2523 static const struct panel_desc innolux_g070y2_t02 = { 2524 .modes = &innolux_g070y2_t02_mode, 2525 .num_modes = 1, 2526 .bpc = 8, 2527 .size = { 2528 .width = 152, 2529 .height = 92, 2530 }, 2531 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2532 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2533 .connector_type = DRM_MODE_CONNECTOR_DPI, 2534 }; 2535 2536 static const struct display_timing innolux_g101ice_l01_timing = { 2537 .pixelclock = { 60400000, 71100000, 74700000 }, 2538 .hactive = { 1280, 1280, 1280 }, 2539 .hfront_porch = { 30, 60, 70 }, 2540 .hback_porch = { 30, 60, 70 }, 2541 .hsync_len = { 22, 40, 60 }, 2542 .vactive = { 800, 800, 800 }, 2543 .vfront_porch = { 3, 8, 14 }, 2544 .vback_porch = { 3, 8, 14 }, 2545 .vsync_len = { 4, 7, 12 }, 2546 .flags = DISPLAY_FLAGS_DE_HIGH, 2547 }; 2548 2549 static const struct panel_desc innolux_g101ice_l01 = { 2550 .timings = &innolux_g101ice_l01_timing, 2551 .num_timings = 1, 2552 .bpc = 8, 2553 .size = { 2554 .width = 217, 2555 .height = 135, 2556 }, 2557 .delay = { 2558 .enable = 200, 2559 .disable = 200, 2560 }, 2561 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2562 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2563 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2564 }; 2565 2566 static const struct display_timing innolux_g121i1_l01_timing = { 2567 .pixelclock = { 67450000, 71000000, 74550000 }, 2568 .hactive = { 1280, 1280, 1280 }, 2569 .hfront_porch = { 40, 80, 160 }, 2570 .hback_porch = { 39, 79, 159 }, 2571 .hsync_len = { 1, 1, 1 }, 2572 .vactive = { 800, 800, 800 }, 2573 .vfront_porch = { 5, 11, 100 }, 2574 .vback_porch = { 4, 11, 99 }, 2575 .vsync_len = { 1, 1, 1 }, 2576 }; 2577 2578 static const struct panel_desc innolux_g121i1_l01 = { 2579 .timings = &innolux_g121i1_l01_timing, 2580 .num_timings = 1, 2581 .bpc = 6, 2582 .size = { 2583 .width = 261, 2584 .height = 163, 2585 }, 2586 .delay = { 2587 .enable = 200, 2588 .disable = 20, 2589 }, 2590 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2591 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2592 }; 2593 2594 static const struct display_timing innolux_g121x1_l03_timings = { 2595 .pixelclock = { 57500000, 64900000, 74400000 }, 2596 .hactive = { 1024, 1024, 1024 }, 2597 .hfront_porch = { 90, 140, 190 }, 2598 .hback_porch = { 90, 140, 190 }, 2599 .hsync_len = { 36, 40, 60 }, 2600 .vactive = { 768, 768, 768 }, 2601 .vfront_porch = { 2, 15, 30 }, 2602 .vback_porch = { 2, 15, 30 }, 2603 .vsync_len = { 2, 8, 20 }, 2604 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2605 }; 2606 2607 static const struct panel_desc innolux_g121x1_l03 = { 2608 .timings = &innolux_g121x1_l03_timings, 2609 .num_timings = 1, 2610 .bpc = 6, 2611 .size = { 2612 .width = 246, 2613 .height = 185, 2614 }, 2615 .delay = { 2616 .enable = 200, 2617 .unprepare = 200, 2618 .disable = 400, 2619 }, 2620 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2621 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2622 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2623 }; 2624 2625 static const struct panel_desc innolux_g121xce_l01 = { 2626 .timings = &innolux_g121x1_l03_timings, 2627 .num_timings = 1, 2628 .bpc = 8, 2629 .size = { 2630 .width = 246, 2631 .height = 185, 2632 }, 2633 .delay = { 2634 .enable = 200, 2635 .unprepare = 200, 2636 .disable = 400, 2637 }, 2638 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2639 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2640 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2641 }; 2642 2643 static const struct display_timing innolux_g156hce_l01_timings = { 2644 .pixelclock = { 120000000, 141860000, 150000000 }, 2645 .hactive = { 1920, 1920, 1920 }, 2646 .hfront_porch = { 80, 90, 100 }, 2647 .hback_porch = { 80, 90, 100 }, 2648 .hsync_len = { 20, 30, 30 }, 2649 .vactive = { 1080, 1080, 1080 }, 2650 .vfront_porch = { 3, 10, 20 }, 2651 .vback_porch = { 3, 10, 20 }, 2652 .vsync_len = { 4, 10, 10 }, 2653 }; 2654 2655 static const struct panel_desc innolux_g156hce_l01 = { 2656 .timings = &innolux_g156hce_l01_timings, 2657 .num_timings = 1, 2658 .bpc = 8, 2659 .size = { 2660 .width = 344, 2661 .height = 194, 2662 }, 2663 .delay = { 2664 .prepare = 1, /* T1+T2 */ 2665 .enable = 450, /* T5 */ 2666 .disable = 200, /* T6 */ 2667 .unprepare = 10, /* T3+T7 */ 2668 }, 2669 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2670 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2671 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2672 }; 2673 2674 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2675 .clock = 69300, 2676 .hdisplay = 1366, 2677 .hsync_start = 1366 + 16, 2678 .hsync_end = 1366 + 16 + 34, 2679 .htotal = 1366 + 16 + 34 + 50, 2680 .vdisplay = 768, 2681 .vsync_start = 768 + 2, 2682 .vsync_end = 768 + 2 + 6, 2683 .vtotal = 768 + 2 + 6 + 12, 2684 }; 2685 2686 static const struct panel_desc innolux_n156bge_l21 = { 2687 .modes = &innolux_n156bge_l21_mode, 2688 .num_modes = 1, 2689 .bpc = 6, 2690 .size = { 2691 .width = 344, 2692 .height = 193, 2693 }, 2694 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2695 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2696 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2697 }; 2698 2699 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2700 .clock = 51501, 2701 .hdisplay = 1024, 2702 .hsync_start = 1024 + 128, 2703 .hsync_end = 1024 + 128 + 64, 2704 .htotal = 1024 + 128 + 64 + 128, 2705 .vdisplay = 600, 2706 .vsync_start = 600 + 16, 2707 .vsync_end = 600 + 16 + 4, 2708 .vtotal = 600 + 16 + 4 + 16, 2709 }; 2710 2711 static const struct panel_desc innolux_zj070na_01p = { 2712 .modes = &innolux_zj070na_01p_mode, 2713 .num_modes = 1, 2714 .bpc = 6, 2715 .size = { 2716 .width = 154, 2717 .height = 90, 2718 }, 2719 }; 2720 2721 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2722 .pixelclock = { 5580000, 5850000, 6200000 }, 2723 .hactive = { 320, 320, 320 }, 2724 .hfront_porch = { 30, 30, 30 }, 2725 .hback_porch = { 30, 30, 30 }, 2726 .hsync_len = { 1, 5, 17 }, 2727 .vactive = { 240, 240, 240 }, 2728 .vfront_porch = { 6, 6, 6 }, 2729 .vback_porch = { 5, 5, 5 }, 2730 .vsync_len = { 1, 2, 11 }, 2731 .flags = DISPLAY_FLAGS_DE_HIGH, 2732 }; 2733 2734 static const struct panel_desc koe_tx14d24vm1bpa = { 2735 .timings = &koe_tx14d24vm1bpa_timing, 2736 .num_timings = 1, 2737 .bpc = 6, 2738 .size = { 2739 .width = 115, 2740 .height = 86, 2741 }, 2742 }; 2743 2744 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2745 .pixelclock = { 151820000, 156720000, 159780000 }, 2746 .hactive = { 1920, 1920, 1920 }, 2747 .hfront_porch = { 105, 130, 142 }, 2748 .hback_porch = { 45, 70, 82 }, 2749 .hsync_len = { 30, 30, 30 }, 2750 .vactive = { 1200, 1200, 1200}, 2751 .vfront_porch = { 3, 5, 10 }, 2752 .vback_porch = { 2, 5, 10 }, 2753 .vsync_len = { 5, 5, 5 }, 2754 }; 2755 2756 static const struct panel_desc koe_tx26d202vm0bwa = { 2757 .timings = &koe_tx26d202vm0bwa_timing, 2758 .num_timings = 1, 2759 .bpc = 8, 2760 .size = { 2761 .width = 217, 2762 .height = 136, 2763 }, 2764 .delay = { 2765 .prepare = 1000, 2766 .enable = 1000, 2767 .unprepare = 1000, 2768 .disable = 1000, 2769 }, 2770 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2771 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2772 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2773 }; 2774 2775 static const struct display_timing koe_tx31d200vm0baa_timing = { 2776 .pixelclock = { 39600000, 43200000, 48000000 }, 2777 .hactive = { 1280, 1280, 1280 }, 2778 .hfront_porch = { 16, 36, 56 }, 2779 .hback_porch = { 16, 36, 56 }, 2780 .hsync_len = { 8, 8, 8 }, 2781 .vactive = { 480, 480, 480 }, 2782 .vfront_porch = { 6, 21, 33 }, 2783 .vback_porch = { 6, 21, 33 }, 2784 .vsync_len = { 8, 8, 8 }, 2785 .flags = DISPLAY_FLAGS_DE_HIGH, 2786 }; 2787 2788 static const struct panel_desc koe_tx31d200vm0baa = { 2789 .timings = &koe_tx31d200vm0baa_timing, 2790 .num_timings = 1, 2791 .bpc = 6, 2792 .size = { 2793 .width = 292, 2794 .height = 109, 2795 }, 2796 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2797 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2798 }; 2799 2800 static const struct display_timing kyo_tcg121xglp_timing = { 2801 .pixelclock = { 52000000, 65000000, 71000000 }, 2802 .hactive = { 1024, 1024, 1024 }, 2803 .hfront_porch = { 2, 2, 2 }, 2804 .hback_porch = { 2, 2, 2 }, 2805 .hsync_len = { 86, 124, 244 }, 2806 .vactive = { 768, 768, 768 }, 2807 .vfront_porch = { 2, 2, 2 }, 2808 .vback_porch = { 2, 2, 2 }, 2809 .vsync_len = { 6, 34, 73 }, 2810 .flags = DISPLAY_FLAGS_DE_HIGH, 2811 }; 2812 2813 static const struct panel_desc kyo_tcg121xglp = { 2814 .timings = &kyo_tcg121xglp_timing, 2815 .num_timings = 1, 2816 .bpc = 8, 2817 .size = { 2818 .width = 246, 2819 .height = 184, 2820 }, 2821 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2822 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2823 }; 2824 2825 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2826 .clock = 7000, 2827 .hdisplay = 320, 2828 .hsync_start = 320 + 20, 2829 .hsync_end = 320 + 20 + 30, 2830 .htotal = 320 + 20 + 30 + 38, 2831 .vdisplay = 240, 2832 .vsync_start = 240 + 4, 2833 .vsync_end = 240 + 4 + 3, 2834 .vtotal = 240 + 4 + 3 + 15, 2835 }; 2836 2837 static const struct panel_desc lemaker_bl035_rgb_002 = { 2838 .modes = &lemaker_bl035_rgb_002_mode, 2839 .num_modes = 1, 2840 .size = { 2841 .width = 70, 2842 .height = 52, 2843 }, 2844 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2845 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2846 }; 2847 2848 static const struct display_timing lg_lb070wv8_timing = { 2849 .pixelclock = { 31950000, 33260000, 34600000 }, 2850 .hactive = { 800, 800, 800 }, 2851 .hfront_porch = { 88, 88, 88 }, 2852 .hback_porch = { 88, 88, 88 }, 2853 .hsync_len = { 80, 80, 80 }, 2854 .vactive = { 480, 480, 480 }, 2855 .vfront_porch = { 10, 10, 10 }, 2856 .vback_porch = { 10, 10, 10 }, 2857 .vsync_len = { 25, 25, 25 }, 2858 }; 2859 2860 static const struct panel_desc lg_lb070wv8 = { 2861 .timings = &lg_lb070wv8_timing, 2862 .num_timings = 1, 2863 .bpc = 8, 2864 .size = { 2865 .width = 151, 2866 .height = 91, 2867 }, 2868 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2869 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2870 }; 2871 2872 static const struct display_timing logictechno_lt161010_2nh_timing = { 2873 .pixelclock = { 26400000, 33300000, 46800000 }, 2874 .hactive = { 800, 800, 800 }, 2875 .hfront_porch = { 16, 210, 354 }, 2876 .hback_porch = { 46, 46, 46 }, 2877 .hsync_len = { 1, 20, 40 }, 2878 .vactive = { 480, 480, 480 }, 2879 .vfront_porch = { 7, 22, 147 }, 2880 .vback_porch = { 23, 23, 23 }, 2881 .vsync_len = { 1, 10, 20 }, 2882 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2883 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2884 DISPLAY_FLAGS_SYNC_POSEDGE, 2885 }; 2886 2887 static const struct panel_desc logictechno_lt161010_2nh = { 2888 .timings = &logictechno_lt161010_2nh_timing, 2889 .num_timings = 1, 2890 .bpc = 6, 2891 .size = { 2892 .width = 154, 2893 .height = 86, 2894 }, 2895 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2896 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2897 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2898 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2899 .connector_type = DRM_MODE_CONNECTOR_DPI, 2900 }; 2901 2902 static const struct display_timing logictechno_lt170410_2whc_timing = { 2903 .pixelclock = { 68900000, 71100000, 73400000 }, 2904 .hactive = { 1280, 1280, 1280 }, 2905 .hfront_porch = { 23, 60, 71 }, 2906 .hback_porch = { 23, 60, 71 }, 2907 .hsync_len = { 15, 40, 47 }, 2908 .vactive = { 800, 800, 800 }, 2909 .vfront_porch = { 5, 7, 10 }, 2910 .vback_porch = { 5, 7, 10 }, 2911 .vsync_len = { 6, 9, 12 }, 2912 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2913 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2914 DISPLAY_FLAGS_SYNC_POSEDGE, 2915 }; 2916 2917 static const struct panel_desc logictechno_lt170410_2whc = { 2918 .timings = &logictechno_lt170410_2whc_timing, 2919 .num_timings = 1, 2920 .bpc = 8, 2921 .size = { 2922 .width = 217, 2923 .height = 136, 2924 }, 2925 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2926 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2927 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2928 }; 2929 2930 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2931 .clock = 33000, 2932 .hdisplay = 800, 2933 .hsync_start = 800 + 112, 2934 .hsync_end = 800 + 112 + 3, 2935 .htotal = 800 + 112 + 3 + 85, 2936 .vdisplay = 480, 2937 .vsync_start = 480 + 38, 2938 .vsync_end = 480 + 38 + 3, 2939 .vtotal = 480 + 38 + 3 + 29, 2940 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2941 }; 2942 2943 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2944 .modes = &logictechno_lttd800480070_l2rt_mode, 2945 .num_modes = 1, 2946 .bpc = 8, 2947 .size = { 2948 .width = 154, 2949 .height = 86, 2950 }, 2951 .delay = { 2952 .prepare = 45, 2953 .enable = 100, 2954 .disable = 100, 2955 .unprepare = 45 2956 }, 2957 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2958 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2959 .connector_type = DRM_MODE_CONNECTOR_DPI, 2960 }; 2961 2962 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2963 .clock = 33000, 2964 .hdisplay = 800, 2965 .hsync_start = 800 + 154, 2966 .hsync_end = 800 + 154 + 3, 2967 .htotal = 800 + 154 + 3 + 43, 2968 .vdisplay = 480, 2969 .vsync_start = 480 + 47, 2970 .vsync_end = 480 + 47 + 3, 2971 .vtotal = 480 + 47 + 3 + 20, 2972 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2973 }; 2974 2975 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2976 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2977 .num_modes = 1, 2978 .bpc = 8, 2979 .size = { 2980 .width = 154, 2981 .height = 86, 2982 }, 2983 .delay = { 2984 .prepare = 45, 2985 .enable = 100, 2986 .disable = 100, 2987 .unprepare = 45 2988 }, 2989 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2990 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2991 .connector_type = DRM_MODE_CONNECTOR_DPI, 2992 }; 2993 2994 static const struct drm_display_mode logicpd_type_28_mode = { 2995 .clock = 9107, 2996 .hdisplay = 480, 2997 .hsync_start = 480 + 3, 2998 .hsync_end = 480 + 3 + 42, 2999 .htotal = 480 + 3 + 42 + 2, 3000 3001 .vdisplay = 272, 3002 .vsync_start = 272 + 2, 3003 .vsync_end = 272 + 2 + 11, 3004 .vtotal = 272 + 2 + 11 + 3, 3005 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3006 }; 3007 3008 static const struct panel_desc logicpd_type_28 = { 3009 .modes = &logicpd_type_28_mode, 3010 .num_modes = 1, 3011 .bpc = 8, 3012 .size = { 3013 .width = 105, 3014 .height = 67, 3015 }, 3016 .delay = { 3017 .prepare = 200, 3018 .enable = 200, 3019 .unprepare = 200, 3020 .disable = 200, 3021 }, 3022 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3023 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3024 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3025 .connector_type = DRM_MODE_CONNECTOR_DPI, 3026 }; 3027 3028 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3029 .clock = 30400, 3030 .hdisplay = 800, 3031 .hsync_start = 800 + 0, 3032 .hsync_end = 800 + 1, 3033 .htotal = 800 + 0 + 1 + 160, 3034 .vdisplay = 480, 3035 .vsync_start = 480 + 0, 3036 .vsync_end = 480 + 48 + 1, 3037 .vtotal = 480 + 48 + 1 + 0, 3038 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3039 }; 3040 3041 static const struct panel_desc mitsubishi_aa070mc01 = { 3042 .modes = &mitsubishi_aa070mc01_mode, 3043 .num_modes = 1, 3044 .bpc = 8, 3045 .size = { 3046 .width = 152, 3047 .height = 91, 3048 }, 3049 3050 .delay = { 3051 .enable = 200, 3052 .unprepare = 200, 3053 .disable = 400, 3054 }, 3055 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3056 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3057 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3058 }; 3059 3060 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3061 .clock = 56234, 3062 .hdisplay = 1024, 3063 .hsync_start = 1024 + 24, 3064 .hsync_end = 1024 + 24 + 63, 3065 .htotal = 1024 + 24 + 63 + 1, 3066 .vdisplay = 768, 3067 .vsync_start = 768 + 3, 3068 .vsync_end = 768 + 3 + 6, 3069 .vtotal = 768 + 3 + 6 + 1, 3070 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3071 }; 3072 3073 static const struct panel_desc mitsubishi_aa084xe01 = { 3074 .modes = &mitsubishi_aa084xe01_mode, 3075 .num_modes = 1, 3076 .bpc = 8, 3077 .size = { 3078 .width = 1024, 3079 .height = 768, 3080 }, 3081 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3082 .connector_type = DRM_MODE_CONNECTOR_DPI, 3083 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3084 }; 3085 3086 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3087 .pixelclock = { 29000000, 33000000, 38000000 }, 3088 .hactive = { 800, 800, 800 }, 3089 .hfront_porch = { 180, 210, 240 }, 3090 .hback_porch = { 16, 16, 16 }, 3091 .hsync_len = { 30, 30, 30 }, 3092 .vactive = { 480, 480, 480 }, 3093 .vfront_porch = { 12, 22, 32 }, 3094 .vback_porch = { 10, 10, 10 }, 3095 .vsync_len = { 13, 13, 13 }, 3096 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3097 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3098 DISPLAY_FLAGS_SYNC_POSEDGE, 3099 }; 3100 3101 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3102 .timings = &multi_inno_mi0700s4t_6_timing, 3103 .num_timings = 1, 3104 .bpc = 8, 3105 .size = { 3106 .width = 154, 3107 .height = 86, 3108 }, 3109 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3110 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3111 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3112 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3113 .connector_type = DRM_MODE_CONNECTOR_DPI, 3114 }; 3115 3116 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3117 .pixelclock = { 32000000, 40000000, 50000000 }, 3118 .hactive = { 800, 800, 800 }, 3119 .hfront_porch = { 16, 210, 354 }, 3120 .hback_porch = { 6, 26, 45 }, 3121 .hsync_len = { 1, 20, 40 }, 3122 .vactive = { 600, 600, 600 }, 3123 .vfront_porch = { 1, 12, 77 }, 3124 .vback_porch = { 3, 13, 22 }, 3125 .vsync_len = { 1, 10, 20 }, 3126 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3127 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3128 DISPLAY_FLAGS_SYNC_POSEDGE, 3129 }; 3130 3131 static const struct panel_desc multi_inno_mi0800ft_9 = { 3132 .timings = &multi_inno_mi0800ft_9_timing, 3133 .num_timings = 1, 3134 .bpc = 8, 3135 .size = { 3136 .width = 162, 3137 .height = 122, 3138 }, 3139 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3140 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3141 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3142 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3143 .connector_type = DRM_MODE_CONNECTOR_DPI, 3144 }; 3145 3146 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3147 .pixelclock = { 68900000, 70000000, 73400000 }, 3148 .hactive = { 1280, 1280, 1280 }, 3149 .hfront_porch = { 30, 60, 71 }, 3150 .hback_porch = { 30, 60, 71 }, 3151 .hsync_len = { 10, 10, 48 }, 3152 .vactive = { 800, 800, 800 }, 3153 .vfront_porch = { 5, 10, 10 }, 3154 .vback_porch = { 5, 10, 10 }, 3155 .vsync_len = { 5, 6, 13 }, 3156 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3157 DISPLAY_FLAGS_DE_HIGH, 3158 }; 3159 3160 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3161 .timings = &multi_inno_mi1010ait_1cp_timing, 3162 .num_timings = 1, 3163 .bpc = 8, 3164 .size = { 3165 .width = 217, 3166 .height = 136, 3167 }, 3168 .delay = { 3169 .enable = 50, 3170 .disable = 50, 3171 }, 3172 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3173 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3174 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3175 }; 3176 3177 static const struct display_timing nec_nl12880bc20_05_timing = { 3178 .pixelclock = { 67000000, 71000000, 75000000 }, 3179 .hactive = { 1280, 1280, 1280 }, 3180 .hfront_porch = { 2, 30, 30 }, 3181 .hback_porch = { 6, 100, 100 }, 3182 .hsync_len = { 2, 30, 30 }, 3183 .vactive = { 800, 800, 800 }, 3184 .vfront_porch = { 5, 5, 5 }, 3185 .vback_porch = { 11, 11, 11 }, 3186 .vsync_len = { 7, 7, 7 }, 3187 }; 3188 3189 static const struct panel_desc nec_nl12880bc20_05 = { 3190 .timings = &nec_nl12880bc20_05_timing, 3191 .num_timings = 1, 3192 .bpc = 8, 3193 .size = { 3194 .width = 261, 3195 .height = 163, 3196 }, 3197 .delay = { 3198 .enable = 50, 3199 .disable = 50, 3200 }, 3201 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3202 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3203 }; 3204 3205 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3206 .clock = 10870, 3207 .hdisplay = 480, 3208 .hsync_start = 480 + 2, 3209 .hsync_end = 480 + 2 + 41, 3210 .htotal = 480 + 2 + 41 + 2, 3211 .vdisplay = 272, 3212 .vsync_start = 272 + 2, 3213 .vsync_end = 272 + 2 + 4, 3214 .vtotal = 272 + 2 + 4 + 2, 3215 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3216 }; 3217 3218 static const struct panel_desc nec_nl4827hc19_05b = { 3219 .modes = &nec_nl4827hc19_05b_mode, 3220 .num_modes = 1, 3221 .bpc = 8, 3222 .size = { 3223 .width = 95, 3224 .height = 54, 3225 }, 3226 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3227 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3228 }; 3229 3230 static const struct drm_display_mode netron_dy_e231732_mode = { 3231 .clock = 66000, 3232 .hdisplay = 1024, 3233 .hsync_start = 1024 + 160, 3234 .hsync_end = 1024 + 160 + 70, 3235 .htotal = 1024 + 160 + 70 + 90, 3236 .vdisplay = 600, 3237 .vsync_start = 600 + 127, 3238 .vsync_end = 600 + 127 + 20, 3239 .vtotal = 600 + 127 + 20 + 3, 3240 }; 3241 3242 static const struct panel_desc netron_dy_e231732 = { 3243 .modes = &netron_dy_e231732_mode, 3244 .num_modes = 1, 3245 .size = { 3246 .width = 154, 3247 .height = 87, 3248 }, 3249 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3250 }; 3251 3252 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3253 .clock = 9000, 3254 .hdisplay = 480, 3255 .hsync_start = 480 + 2, 3256 .hsync_end = 480 + 2 + 41, 3257 .htotal = 480 + 2 + 41 + 2, 3258 .vdisplay = 272, 3259 .vsync_start = 272 + 2, 3260 .vsync_end = 272 + 2 + 10, 3261 .vtotal = 272 + 2 + 10 + 2, 3262 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3263 }; 3264 3265 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3266 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3267 .num_modes = 1, 3268 .bpc = 8, 3269 .size = { 3270 .width = 95, 3271 .height = 54, 3272 }, 3273 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3274 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3275 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3276 .connector_type = DRM_MODE_CONNECTOR_DPI, 3277 }; 3278 3279 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3280 .pixelclock = { 130000000, 148350000, 163000000 }, 3281 .hactive = { 1920, 1920, 1920 }, 3282 .hfront_porch = { 80, 100, 100 }, 3283 .hback_porch = { 100, 120, 120 }, 3284 .hsync_len = { 50, 60, 60 }, 3285 .vactive = { 1080, 1080, 1080 }, 3286 .vfront_porch = { 12, 30, 30 }, 3287 .vback_porch = { 4, 10, 10 }, 3288 .vsync_len = { 4, 5, 5 }, 3289 }; 3290 3291 static const struct panel_desc nlt_nl192108ac18_02d = { 3292 .timings = &nlt_nl192108ac18_02d_timing, 3293 .num_timings = 1, 3294 .bpc = 8, 3295 .size = { 3296 .width = 344, 3297 .height = 194, 3298 }, 3299 .delay = { 3300 .unprepare = 500, 3301 }, 3302 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3303 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3304 }; 3305 3306 static const struct drm_display_mode nvd_9128_mode = { 3307 .clock = 29500, 3308 .hdisplay = 800, 3309 .hsync_start = 800 + 130, 3310 .hsync_end = 800 + 130 + 98, 3311 .htotal = 800 + 0 + 130 + 98, 3312 .vdisplay = 480, 3313 .vsync_start = 480 + 10, 3314 .vsync_end = 480 + 10 + 50, 3315 .vtotal = 480 + 0 + 10 + 50, 3316 }; 3317 3318 static const struct panel_desc nvd_9128 = { 3319 .modes = &nvd_9128_mode, 3320 .num_modes = 1, 3321 .bpc = 8, 3322 .size = { 3323 .width = 156, 3324 .height = 88, 3325 }, 3326 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3327 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3328 }; 3329 3330 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3331 .pixelclock = { 30000000, 30000000, 40000000 }, 3332 .hactive = { 800, 800, 800 }, 3333 .hfront_porch = { 40, 40, 40 }, 3334 .hback_porch = { 40, 40, 40 }, 3335 .hsync_len = { 1, 48, 48 }, 3336 .vactive = { 480, 480, 480 }, 3337 .vfront_porch = { 13, 13, 13 }, 3338 .vback_porch = { 29, 29, 29 }, 3339 .vsync_len = { 3, 3, 3 }, 3340 .flags = DISPLAY_FLAGS_DE_HIGH, 3341 }; 3342 3343 static const struct panel_desc okaya_rs800480t_7x0gp = { 3344 .timings = &okaya_rs800480t_7x0gp_timing, 3345 .num_timings = 1, 3346 .bpc = 6, 3347 .size = { 3348 .width = 154, 3349 .height = 87, 3350 }, 3351 .delay = { 3352 .prepare = 41, 3353 .enable = 50, 3354 .unprepare = 41, 3355 .disable = 50, 3356 }, 3357 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3358 }; 3359 3360 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3361 .clock = 9000, 3362 .hdisplay = 480, 3363 .hsync_start = 480 + 5, 3364 .hsync_end = 480 + 5 + 30, 3365 .htotal = 480 + 5 + 30 + 10, 3366 .vdisplay = 272, 3367 .vsync_start = 272 + 8, 3368 .vsync_end = 272 + 8 + 5, 3369 .vtotal = 272 + 8 + 5 + 3, 3370 }; 3371 3372 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3373 .modes = &olimex_lcd_olinuxino_43ts_mode, 3374 .num_modes = 1, 3375 .size = { 3376 .width = 95, 3377 .height = 54, 3378 }, 3379 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3380 }; 3381 3382 /* 3383 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3384 * pixel clocks, but this is the timing that was being used in the Adafruit 3385 * installation instructions. 3386 */ 3387 static const struct drm_display_mode ontat_yx700wv03_mode = { 3388 .clock = 29500, 3389 .hdisplay = 800, 3390 .hsync_start = 824, 3391 .hsync_end = 896, 3392 .htotal = 992, 3393 .vdisplay = 480, 3394 .vsync_start = 483, 3395 .vsync_end = 493, 3396 .vtotal = 500, 3397 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3398 }; 3399 3400 /* 3401 * Specification at: 3402 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3403 */ 3404 static const struct panel_desc ontat_yx700wv03 = { 3405 .modes = &ontat_yx700wv03_mode, 3406 .num_modes = 1, 3407 .bpc = 8, 3408 .size = { 3409 .width = 154, 3410 .height = 83, 3411 }, 3412 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3413 }; 3414 3415 static const struct drm_display_mode ortustech_com37h3m_mode = { 3416 .clock = 22230, 3417 .hdisplay = 480, 3418 .hsync_start = 480 + 40, 3419 .hsync_end = 480 + 40 + 10, 3420 .htotal = 480 + 40 + 10 + 40, 3421 .vdisplay = 640, 3422 .vsync_start = 640 + 4, 3423 .vsync_end = 640 + 4 + 2, 3424 .vtotal = 640 + 4 + 2 + 4, 3425 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3426 }; 3427 3428 static const struct panel_desc ortustech_com37h3m = { 3429 .modes = &ortustech_com37h3m_mode, 3430 .num_modes = 1, 3431 .bpc = 8, 3432 .size = { 3433 .width = 56, /* 56.16mm */ 3434 .height = 75, /* 74.88mm */ 3435 }, 3436 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3437 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3438 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3439 }; 3440 3441 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3442 .clock = 25000, 3443 .hdisplay = 480, 3444 .hsync_start = 480 + 10, 3445 .hsync_end = 480 + 10 + 10, 3446 .htotal = 480 + 10 + 10 + 15, 3447 .vdisplay = 800, 3448 .vsync_start = 800 + 3, 3449 .vsync_end = 800 + 3 + 3, 3450 .vtotal = 800 + 3 + 3 + 3, 3451 }; 3452 3453 static const struct panel_desc ortustech_com43h4m85ulc = { 3454 .modes = &ortustech_com43h4m85ulc_mode, 3455 .num_modes = 1, 3456 .bpc = 6, 3457 .size = { 3458 .width = 56, 3459 .height = 93, 3460 }, 3461 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3462 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3463 .connector_type = DRM_MODE_CONNECTOR_DPI, 3464 }; 3465 3466 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3467 .clock = 33000, 3468 .hdisplay = 800, 3469 .hsync_start = 800 + 210, 3470 .hsync_end = 800 + 210 + 30, 3471 .htotal = 800 + 210 + 30 + 16, 3472 .vdisplay = 480, 3473 .vsync_start = 480 + 22, 3474 .vsync_end = 480 + 22 + 13, 3475 .vtotal = 480 + 22 + 13 + 10, 3476 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3477 }; 3478 3479 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3480 .modes = &osddisplays_osd070t1718_19ts_mode, 3481 .num_modes = 1, 3482 .bpc = 8, 3483 .size = { 3484 .width = 152, 3485 .height = 91, 3486 }, 3487 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3488 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3489 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3490 .connector_type = DRM_MODE_CONNECTOR_DPI, 3491 }; 3492 3493 static const struct drm_display_mode pda_91_00156_a0_mode = { 3494 .clock = 33300, 3495 .hdisplay = 800, 3496 .hsync_start = 800 + 1, 3497 .hsync_end = 800 + 1 + 64, 3498 .htotal = 800 + 1 + 64 + 64, 3499 .vdisplay = 480, 3500 .vsync_start = 480 + 1, 3501 .vsync_end = 480 + 1 + 23, 3502 .vtotal = 480 + 1 + 23 + 22, 3503 }; 3504 3505 static const struct panel_desc pda_91_00156_a0 = { 3506 .modes = &pda_91_00156_a0_mode, 3507 .num_modes = 1, 3508 .size = { 3509 .width = 152, 3510 .height = 91, 3511 }, 3512 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3513 }; 3514 3515 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 3516 .clock = 66500, 3517 .hdisplay = 1280, 3518 .hsync_start = 1280 + 12, 3519 .hsync_end = 1280 + 12 + 20, 3520 .htotal = 1280 + 12 + 20 + 56, 3521 .vdisplay = 800, 3522 .vsync_start = 800 + 1, 3523 .vsync_end = 800 + 1 + 3, 3524 .vtotal = 800 + 1 + 3 + 20, 3525 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3526 }; 3527 3528 static const struct panel_desc powertip_ph128800t006_zhc01 = { 3529 .modes = &powertip_ph128800t006_zhc01_mode, 3530 .num_modes = 1, 3531 .bpc = 8, 3532 .size = { 3533 .width = 216, 3534 .height = 135, 3535 }, 3536 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3537 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3538 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3539 }; 3540 3541 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3542 .clock = 24750, 3543 .hdisplay = 800, 3544 .hsync_start = 800 + 54, 3545 .hsync_end = 800 + 54 + 2, 3546 .htotal = 800 + 54 + 2 + 44, 3547 .vdisplay = 480, 3548 .vsync_start = 480 + 49, 3549 .vsync_end = 480 + 49 + 2, 3550 .vtotal = 480 + 49 + 2 + 22, 3551 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3552 }; 3553 3554 static const struct panel_desc powertip_ph800480t013_idf02 = { 3555 .modes = &powertip_ph800480t013_idf02_mode, 3556 .num_modes = 1, 3557 .bpc = 8, 3558 .size = { 3559 .width = 152, 3560 .height = 91, 3561 }, 3562 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3563 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3564 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3565 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3566 .connector_type = DRM_MODE_CONNECTOR_DPI, 3567 }; 3568 3569 static const struct drm_display_mode qd43003c0_40_mode = { 3570 .clock = 9000, 3571 .hdisplay = 480, 3572 .hsync_start = 480 + 8, 3573 .hsync_end = 480 + 8 + 4, 3574 .htotal = 480 + 8 + 4 + 39, 3575 .vdisplay = 272, 3576 .vsync_start = 272 + 4, 3577 .vsync_end = 272 + 4 + 10, 3578 .vtotal = 272 + 4 + 10 + 2, 3579 }; 3580 3581 static const struct panel_desc qd43003c0_40 = { 3582 .modes = &qd43003c0_40_mode, 3583 .num_modes = 1, 3584 .bpc = 8, 3585 .size = { 3586 .width = 95, 3587 .height = 53, 3588 }, 3589 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3590 }; 3591 3592 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3593 { /* 60 Hz */ 3594 .clock = 10800, 3595 .hdisplay = 480, 3596 .hsync_start = 480 + 77, 3597 .hsync_end = 480 + 77 + 41, 3598 .htotal = 480 + 77 + 41 + 2, 3599 .vdisplay = 272, 3600 .vsync_start = 272 + 16, 3601 .vsync_end = 272 + 16 + 10, 3602 .vtotal = 272 + 16 + 10 + 2, 3603 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3604 }, 3605 { /* 50 Hz */ 3606 .clock = 10800, 3607 .hdisplay = 480, 3608 .hsync_start = 480 + 17, 3609 .hsync_end = 480 + 17 + 41, 3610 .htotal = 480 + 17 + 41 + 2, 3611 .vdisplay = 272, 3612 .vsync_start = 272 + 116, 3613 .vsync_end = 272 + 116 + 10, 3614 .vtotal = 272 + 116 + 10 + 2, 3615 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3616 }, 3617 }; 3618 3619 static const struct panel_desc qishenglong_gopher2b_lcd = { 3620 .modes = qishenglong_gopher2b_lcd_modes, 3621 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3622 .bpc = 8, 3623 .size = { 3624 .width = 95, 3625 .height = 54, 3626 }, 3627 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3628 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3629 .connector_type = DRM_MODE_CONNECTOR_DPI, 3630 }; 3631 3632 static const struct display_timing rocktech_rk043fn48h_timing = { 3633 .pixelclock = { 6000000, 9000000, 12000000 }, 3634 .hactive = { 480, 480, 480 }, 3635 .hback_porch = { 8, 43, 43 }, 3636 .hfront_porch = { 2, 8, 10 }, 3637 .hsync_len = { 1, 1, 1 }, 3638 .vactive = { 272, 272, 272 }, 3639 .vback_porch = { 2, 12, 26 }, 3640 .vfront_porch = { 1, 4, 4 }, 3641 .vsync_len = { 1, 10, 10 }, 3642 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3643 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3644 DISPLAY_FLAGS_SYNC_POSEDGE, 3645 }; 3646 3647 static const struct panel_desc rocktech_rk043fn48h = { 3648 .timings = &rocktech_rk043fn48h_timing, 3649 .num_timings = 1, 3650 .bpc = 8, 3651 .size = { 3652 .width = 95, 3653 .height = 54, 3654 }, 3655 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3656 .connector_type = DRM_MODE_CONNECTOR_DPI, 3657 }; 3658 3659 static const struct display_timing rocktech_rk070er9427_timing = { 3660 .pixelclock = { 26400000, 33300000, 46800000 }, 3661 .hactive = { 800, 800, 800 }, 3662 .hfront_porch = { 16, 210, 354 }, 3663 .hback_porch = { 46, 46, 46 }, 3664 .hsync_len = { 1, 1, 1 }, 3665 .vactive = { 480, 480, 480 }, 3666 .vfront_porch = { 7, 22, 147 }, 3667 .vback_porch = { 23, 23, 23 }, 3668 .vsync_len = { 1, 1, 1 }, 3669 .flags = DISPLAY_FLAGS_DE_HIGH, 3670 }; 3671 3672 static const struct panel_desc rocktech_rk070er9427 = { 3673 .timings = &rocktech_rk070er9427_timing, 3674 .num_timings = 1, 3675 .bpc = 6, 3676 .size = { 3677 .width = 154, 3678 .height = 86, 3679 }, 3680 .delay = { 3681 .prepare = 41, 3682 .enable = 50, 3683 .unprepare = 41, 3684 .disable = 50, 3685 }, 3686 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3687 }; 3688 3689 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3690 .clock = 71100, 3691 .hdisplay = 1280, 3692 .hsync_start = 1280 + 48, 3693 .hsync_end = 1280 + 48 + 32, 3694 .htotal = 1280 + 48 + 32 + 80, 3695 .vdisplay = 800, 3696 .vsync_start = 800 + 2, 3697 .vsync_end = 800 + 2 + 5, 3698 .vtotal = 800 + 2 + 5 + 16, 3699 }; 3700 3701 static const struct panel_desc rocktech_rk101ii01d_ct = { 3702 .modes = &rocktech_rk101ii01d_ct_mode, 3703 .bpc = 8, 3704 .num_modes = 1, 3705 .size = { 3706 .width = 217, 3707 .height = 136, 3708 }, 3709 .delay = { 3710 .prepare = 50, 3711 .disable = 50, 3712 }, 3713 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3714 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3715 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3716 }; 3717 3718 static const struct display_timing samsung_ltl101al01_timing = { 3719 .pixelclock = { 66663000, 66663000, 66663000 }, 3720 .hactive = { 1280, 1280, 1280 }, 3721 .hfront_porch = { 18, 18, 18 }, 3722 .hback_porch = { 36, 36, 36 }, 3723 .hsync_len = { 16, 16, 16 }, 3724 .vactive = { 800, 800, 800 }, 3725 .vfront_porch = { 4, 4, 4 }, 3726 .vback_porch = { 16, 16, 16 }, 3727 .vsync_len = { 3, 3, 3 }, 3728 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3729 }; 3730 3731 static const struct panel_desc samsung_ltl101al01 = { 3732 .timings = &samsung_ltl101al01_timing, 3733 .num_timings = 1, 3734 .bpc = 8, 3735 .size = { 3736 .width = 217, 3737 .height = 135, 3738 }, 3739 .delay = { 3740 .prepare = 40, 3741 .enable = 300, 3742 .disable = 200, 3743 .unprepare = 600, 3744 }, 3745 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3746 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3747 }; 3748 3749 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3750 .clock = 54030, 3751 .hdisplay = 1024, 3752 .hsync_start = 1024 + 24, 3753 .hsync_end = 1024 + 24 + 136, 3754 .htotal = 1024 + 24 + 136 + 160, 3755 .vdisplay = 600, 3756 .vsync_start = 600 + 3, 3757 .vsync_end = 600 + 3 + 6, 3758 .vtotal = 600 + 3 + 6 + 61, 3759 }; 3760 3761 static const struct panel_desc samsung_ltn101nt05 = { 3762 .modes = &samsung_ltn101nt05_mode, 3763 .num_modes = 1, 3764 .bpc = 6, 3765 .size = { 3766 .width = 223, 3767 .height = 125, 3768 }, 3769 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3770 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3771 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3772 }; 3773 3774 static const struct display_timing satoz_sat050at40h12r2_timing = { 3775 .pixelclock = {33300000, 33300000, 50000000}, 3776 .hactive = {800, 800, 800}, 3777 .hfront_porch = {16, 210, 354}, 3778 .hback_porch = {46, 46, 46}, 3779 .hsync_len = {1, 1, 40}, 3780 .vactive = {480, 480, 480}, 3781 .vfront_porch = {7, 22, 147}, 3782 .vback_porch = {23, 23, 23}, 3783 .vsync_len = {1, 1, 20}, 3784 }; 3785 3786 static const struct panel_desc satoz_sat050at40h12r2 = { 3787 .timings = &satoz_sat050at40h12r2_timing, 3788 .num_timings = 1, 3789 .bpc = 8, 3790 .size = { 3791 .width = 108, 3792 .height = 65, 3793 }, 3794 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3795 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3796 }; 3797 3798 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3799 .clock = 33260, 3800 .hdisplay = 800, 3801 .hsync_start = 800 + 64, 3802 .hsync_end = 800 + 64 + 128, 3803 .htotal = 800 + 64 + 128 + 64, 3804 .vdisplay = 480, 3805 .vsync_start = 480 + 8, 3806 .vsync_end = 480 + 8 + 2, 3807 .vtotal = 480 + 8 + 2 + 35, 3808 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3809 }; 3810 3811 static const struct panel_desc sharp_lq070y3dg3b = { 3812 .modes = &sharp_lq070y3dg3b_mode, 3813 .num_modes = 1, 3814 .bpc = 8, 3815 .size = { 3816 .width = 152, /* 152.4mm */ 3817 .height = 91, /* 91.4mm */ 3818 }, 3819 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3820 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3821 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3822 }; 3823 3824 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3825 .clock = 5500, 3826 .hdisplay = 240, 3827 .hsync_start = 240 + 16, 3828 .hsync_end = 240 + 16 + 7, 3829 .htotal = 240 + 16 + 7 + 5, 3830 .vdisplay = 320, 3831 .vsync_start = 320 + 9, 3832 .vsync_end = 320 + 9 + 1, 3833 .vtotal = 320 + 9 + 1 + 7, 3834 }; 3835 3836 static const struct panel_desc sharp_lq035q7db03 = { 3837 .modes = &sharp_lq035q7db03_mode, 3838 .num_modes = 1, 3839 .bpc = 6, 3840 .size = { 3841 .width = 54, 3842 .height = 72, 3843 }, 3844 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3845 }; 3846 3847 static const struct display_timing sharp_lq101k1ly04_timing = { 3848 .pixelclock = { 60000000, 65000000, 80000000 }, 3849 .hactive = { 1280, 1280, 1280 }, 3850 .hfront_porch = { 20, 20, 20 }, 3851 .hback_porch = { 20, 20, 20 }, 3852 .hsync_len = { 10, 10, 10 }, 3853 .vactive = { 800, 800, 800 }, 3854 .vfront_porch = { 4, 4, 4 }, 3855 .vback_porch = { 4, 4, 4 }, 3856 .vsync_len = { 4, 4, 4 }, 3857 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3858 }; 3859 3860 static const struct panel_desc sharp_lq101k1ly04 = { 3861 .timings = &sharp_lq101k1ly04_timing, 3862 .num_timings = 1, 3863 .bpc = 8, 3864 .size = { 3865 .width = 217, 3866 .height = 136, 3867 }, 3868 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3869 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3870 }; 3871 3872 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3873 { /* 50 Hz */ 3874 .clock = 3000, 3875 .hdisplay = 240, 3876 .hsync_start = 240 + 58, 3877 .hsync_end = 240 + 58 + 1, 3878 .htotal = 240 + 58 + 1 + 1, 3879 .vdisplay = 160, 3880 .vsync_start = 160 + 24, 3881 .vsync_end = 160 + 24 + 10, 3882 .vtotal = 160 + 24 + 10 + 6, 3883 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3884 }, 3885 { /* 60 Hz */ 3886 .clock = 3000, 3887 .hdisplay = 240, 3888 .hsync_start = 240 + 8, 3889 .hsync_end = 240 + 8 + 1, 3890 .htotal = 240 + 8 + 1 + 1, 3891 .vdisplay = 160, 3892 .vsync_start = 160 + 24, 3893 .vsync_end = 160 + 24 + 10, 3894 .vtotal = 160 + 24 + 10 + 6, 3895 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3896 }, 3897 }; 3898 3899 static const struct panel_desc sharp_ls020b1dd01d = { 3900 .modes = sharp_ls020b1dd01d_modes, 3901 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3902 .bpc = 6, 3903 .size = { 3904 .width = 42, 3905 .height = 28, 3906 }, 3907 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3908 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3909 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3910 | DRM_BUS_FLAG_SHARP_SIGNALS, 3911 }; 3912 3913 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3914 .clock = 33300, 3915 .hdisplay = 800, 3916 .hsync_start = 800 + 1, 3917 .hsync_end = 800 + 1 + 64, 3918 .htotal = 800 + 1 + 64 + 64, 3919 .vdisplay = 480, 3920 .vsync_start = 480 + 1, 3921 .vsync_end = 480 + 1 + 23, 3922 .vtotal = 480 + 1 + 23 + 22, 3923 }; 3924 3925 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3926 .modes = &shelly_sca07010_bfn_lnn_mode, 3927 .num_modes = 1, 3928 .size = { 3929 .width = 152, 3930 .height = 91, 3931 }, 3932 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3933 }; 3934 3935 static const struct drm_display_mode starry_kr070pe2t_mode = { 3936 .clock = 33000, 3937 .hdisplay = 800, 3938 .hsync_start = 800 + 209, 3939 .hsync_end = 800 + 209 + 1, 3940 .htotal = 800 + 209 + 1 + 45, 3941 .vdisplay = 480, 3942 .vsync_start = 480 + 22, 3943 .vsync_end = 480 + 22 + 1, 3944 .vtotal = 480 + 22 + 1 + 22, 3945 }; 3946 3947 static const struct panel_desc starry_kr070pe2t = { 3948 .modes = &starry_kr070pe2t_mode, 3949 .num_modes = 1, 3950 .bpc = 8, 3951 .size = { 3952 .width = 152, 3953 .height = 86, 3954 }, 3955 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3956 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3957 .connector_type = DRM_MODE_CONNECTOR_DPI, 3958 }; 3959 3960 static const struct display_timing startek_kd070wvfpa_mode = { 3961 .pixelclock = { 25200000, 27200000, 30500000 }, 3962 .hactive = { 800, 800, 800 }, 3963 .hfront_porch = { 19, 44, 115 }, 3964 .hback_porch = { 5, 16, 101 }, 3965 .hsync_len = { 1, 2, 100 }, 3966 .vactive = { 480, 480, 480 }, 3967 .vfront_porch = { 5, 43, 67 }, 3968 .vback_porch = { 5, 5, 67 }, 3969 .vsync_len = { 1, 2, 66 }, 3970 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3971 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3972 DISPLAY_FLAGS_SYNC_POSEDGE, 3973 }; 3974 3975 static const struct panel_desc startek_kd070wvfpa = { 3976 .timings = &startek_kd070wvfpa_mode, 3977 .num_timings = 1, 3978 .bpc = 8, 3979 .size = { 3980 .width = 152, 3981 .height = 91, 3982 }, 3983 .delay = { 3984 .prepare = 20, 3985 .enable = 200, 3986 .disable = 200, 3987 }, 3988 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3989 .connector_type = DRM_MODE_CONNECTOR_DPI, 3990 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3991 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3992 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3993 }; 3994 3995 static const struct display_timing tsd_tst043015cmhx_timing = { 3996 .pixelclock = { 5000000, 9000000, 12000000 }, 3997 .hactive = { 480, 480, 480 }, 3998 .hfront_porch = { 4, 5, 65 }, 3999 .hback_porch = { 36, 40, 255 }, 4000 .hsync_len = { 1, 1, 1 }, 4001 .vactive = { 272, 272, 272 }, 4002 .vfront_porch = { 2, 8, 97 }, 4003 .vback_porch = { 3, 8, 31 }, 4004 .vsync_len = { 1, 1, 1 }, 4005 4006 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4007 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4008 }; 4009 4010 static const struct panel_desc tsd_tst043015cmhx = { 4011 .timings = &tsd_tst043015cmhx_timing, 4012 .num_timings = 1, 4013 .bpc = 8, 4014 .size = { 4015 .width = 105, 4016 .height = 67, 4017 }, 4018 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4019 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4020 }; 4021 4022 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4023 .clock = 30000, 4024 .hdisplay = 800, 4025 .hsync_start = 800 + 39, 4026 .hsync_end = 800 + 39 + 47, 4027 .htotal = 800 + 39 + 47 + 39, 4028 .vdisplay = 480, 4029 .vsync_start = 480 + 13, 4030 .vsync_end = 480 + 13 + 2, 4031 .vtotal = 480 + 13 + 2 + 29, 4032 }; 4033 4034 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4035 .modes = &tfc_s9700rtwv43tr_01b_mode, 4036 .num_modes = 1, 4037 .bpc = 8, 4038 .size = { 4039 .width = 155, 4040 .height = 90, 4041 }, 4042 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4043 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4044 }; 4045 4046 static const struct display_timing tianma_tm070jdhg30_timing = { 4047 .pixelclock = { 62600000, 68200000, 78100000 }, 4048 .hactive = { 1280, 1280, 1280 }, 4049 .hfront_porch = { 15, 64, 159 }, 4050 .hback_porch = { 5, 5, 5 }, 4051 .hsync_len = { 1, 1, 256 }, 4052 .vactive = { 800, 800, 800 }, 4053 .vfront_porch = { 3, 40, 99 }, 4054 .vback_porch = { 2, 2, 2 }, 4055 .vsync_len = { 1, 1, 128 }, 4056 .flags = DISPLAY_FLAGS_DE_HIGH, 4057 }; 4058 4059 static const struct panel_desc tianma_tm070jdhg30 = { 4060 .timings = &tianma_tm070jdhg30_timing, 4061 .num_timings = 1, 4062 .bpc = 8, 4063 .size = { 4064 .width = 151, 4065 .height = 95, 4066 }, 4067 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4068 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4069 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4070 }; 4071 4072 static const struct panel_desc tianma_tm070jvhg33 = { 4073 .timings = &tianma_tm070jdhg30_timing, 4074 .num_timings = 1, 4075 .bpc = 8, 4076 .size = { 4077 .width = 150, 4078 .height = 94, 4079 }, 4080 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4081 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4082 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4083 }; 4084 4085 static const struct display_timing tianma_tm070rvhg71_timing = { 4086 .pixelclock = { 27700000, 29200000, 39600000 }, 4087 .hactive = { 800, 800, 800 }, 4088 .hfront_porch = { 12, 40, 212 }, 4089 .hback_porch = { 88, 88, 88 }, 4090 .hsync_len = { 1, 1, 40 }, 4091 .vactive = { 480, 480, 480 }, 4092 .vfront_porch = { 1, 13, 88 }, 4093 .vback_porch = { 32, 32, 32 }, 4094 .vsync_len = { 1, 1, 3 }, 4095 .flags = DISPLAY_FLAGS_DE_HIGH, 4096 }; 4097 4098 static const struct panel_desc tianma_tm070rvhg71 = { 4099 .timings = &tianma_tm070rvhg71_timing, 4100 .num_timings = 1, 4101 .bpc = 8, 4102 .size = { 4103 .width = 154, 4104 .height = 86, 4105 }, 4106 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4107 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4108 }; 4109 4110 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4111 { 4112 .clock = 10000, 4113 .hdisplay = 320, 4114 .hsync_start = 320 + 50, 4115 .hsync_end = 320 + 50 + 6, 4116 .htotal = 320 + 50 + 6 + 38, 4117 .vdisplay = 240, 4118 .vsync_start = 240 + 3, 4119 .vsync_end = 240 + 3 + 1, 4120 .vtotal = 240 + 3 + 1 + 17, 4121 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4122 }, 4123 }; 4124 4125 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4126 .modes = ti_nspire_cx_lcd_mode, 4127 .num_modes = 1, 4128 .bpc = 8, 4129 .size = { 4130 .width = 65, 4131 .height = 49, 4132 }, 4133 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4134 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4135 }; 4136 4137 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4138 { 4139 .clock = 10000, 4140 .hdisplay = 320, 4141 .hsync_start = 320 + 6, 4142 .hsync_end = 320 + 6 + 6, 4143 .htotal = 320 + 6 + 6 + 6, 4144 .vdisplay = 240, 4145 .vsync_start = 240 + 0, 4146 .vsync_end = 240 + 0 + 1, 4147 .vtotal = 240 + 0 + 1 + 0, 4148 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4149 }, 4150 }; 4151 4152 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4153 .modes = ti_nspire_classic_lcd_mode, 4154 .num_modes = 1, 4155 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4156 .bpc = 8, 4157 .size = { 4158 .width = 71, 4159 .height = 53, 4160 }, 4161 /* This is the grayscale bus format */ 4162 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4163 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4164 }; 4165 4166 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4167 .clock = 79500, 4168 .hdisplay = 1280, 4169 .hsync_start = 1280 + 192, 4170 .hsync_end = 1280 + 192 + 128, 4171 .htotal = 1280 + 192 + 128 + 64, 4172 .vdisplay = 768, 4173 .vsync_start = 768 + 20, 4174 .vsync_end = 768 + 20 + 7, 4175 .vtotal = 768 + 20 + 7 + 3, 4176 }; 4177 4178 static const struct panel_desc toshiba_lt089ac29000 = { 4179 .modes = &toshiba_lt089ac29000_mode, 4180 .num_modes = 1, 4181 .size = { 4182 .width = 194, 4183 .height = 116, 4184 }, 4185 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4186 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4187 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4188 }; 4189 4190 static const struct drm_display_mode tpk_f07a_0102_mode = { 4191 .clock = 33260, 4192 .hdisplay = 800, 4193 .hsync_start = 800 + 40, 4194 .hsync_end = 800 + 40 + 128, 4195 .htotal = 800 + 40 + 128 + 88, 4196 .vdisplay = 480, 4197 .vsync_start = 480 + 10, 4198 .vsync_end = 480 + 10 + 2, 4199 .vtotal = 480 + 10 + 2 + 33, 4200 }; 4201 4202 static const struct panel_desc tpk_f07a_0102 = { 4203 .modes = &tpk_f07a_0102_mode, 4204 .num_modes = 1, 4205 .size = { 4206 .width = 152, 4207 .height = 91, 4208 }, 4209 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4210 }; 4211 4212 static const struct drm_display_mode tpk_f10a_0102_mode = { 4213 .clock = 45000, 4214 .hdisplay = 1024, 4215 .hsync_start = 1024 + 176, 4216 .hsync_end = 1024 + 176 + 5, 4217 .htotal = 1024 + 176 + 5 + 88, 4218 .vdisplay = 600, 4219 .vsync_start = 600 + 20, 4220 .vsync_end = 600 + 20 + 5, 4221 .vtotal = 600 + 20 + 5 + 25, 4222 }; 4223 4224 static const struct panel_desc tpk_f10a_0102 = { 4225 .modes = &tpk_f10a_0102_mode, 4226 .num_modes = 1, 4227 .size = { 4228 .width = 223, 4229 .height = 125, 4230 }, 4231 }; 4232 4233 static const struct display_timing urt_umsh_8596md_timing = { 4234 .pixelclock = { 33260000, 33260000, 33260000 }, 4235 .hactive = { 800, 800, 800 }, 4236 .hfront_porch = { 41, 41, 41 }, 4237 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4238 .hsync_len = { 71, 128, 128 }, 4239 .vactive = { 480, 480, 480 }, 4240 .vfront_porch = { 10, 10, 10 }, 4241 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4242 .vsync_len = { 2, 2, 2 }, 4243 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4244 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4245 }; 4246 4247 static const struct panel_desc urt_umsh_8596md_lvds = { 4248 .timings = &urt_umsh_8596md_timing, 4249 .num_timings = 1, 4250 .bpc = 6, 4251 .size = { 4252 .width = 152, 4253 .height = 91, 4254 }, 4255 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4256 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4257 }; 4258 4259 static const struct panel_desc urt_umsh_8596md_parallel = { 4260 .timings = &urt_umsh_8596md_timing, 4261 .num_timings = 1, 4262 .bpc = 6, 4263 .size = { 4264 .width = 152, 4265 .height = 91, 4266 }, 4267 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4268 }; 4269 4270 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4271 .clock = 60000, 4272 .hdisplay = 1024, 4273 .hsync_start = 1024 + 160, 4274 .hsync_end = 1024 + 160 + 100, 4275 .htotal = 1024 + 160 + 100 + 60, 4276 .vdisplay = 600, 4277 .vsync_start = 600 + 12, 4278 .vsync_end = 600 + 12 + 10, 4279 .vtotal = 600 + 12 + 10 + 13, 4280 }; 4281 4282 static const struct panel_desc vivax_tpc9150_panel = { 4283 .modes = &vivax_tpc9150_panel_mode, 4284 .num_modes = 1, 4285 .bpc = 6, 4286 .size = { 4287 .width = 200, 4288 .height = 115, 4289 }, 4290 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4291 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4292 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4293 }; 4294 4295 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4296 .clock = 33333, 4297 .hdisplay = 800, 4298 .hsync_start = 800 + 210, 4299 .hsync_end = 800 + 210 + 20, 4300 .htotal = 800 + 210 + 20 + 46, 4301 .vdisplay = 480, 4302 .vsync_start = 480 + 22, 4303 .vsync_end = 480 + 22 + 10, 4304 .vtotal = 480 + 22 + 10 + 23, 4305 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4306 }; 4307 4308 static const struct panel_desc vl050_8048nt_c01 = { 4309 .modes = &vl050_8048nt_c01_mode, 4310 .num_modes = 1, 4311 .bpc = 8, 4312 .size = { 4313 .width = 120, 4314 .height = 76, 4315 }, 4316 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4317 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4318 }; 4319 4320 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4321 .clock = 6410, 4322 .hdisplay = 320, 4323 .hsync_start = 320 + 20, 4324 .hsync_end = 320 + 20 + 30, 4325 .htotal = 320 + 20 + 30 + 38, 4326 .vdisplay = 240, 4327 .vsync_start = 240 + 4, 4328 .vsync_end = 240 + 4 + 3, 4329 .vtotal = 240 + 4 + 3 + 15, 4330 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4331 }; 4332 4333 static const struct panel_desc winstar_wf35ltiacd = { 4334 .modes = &winstar_wf35ltiacd_mode, 4335 .num_modes = 1, 4336 .bpc = 8, 4337 .size = { 4338 .width = 70, 4339 .height = 53, 4340 }, 4341 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4342 }; 4343 4344 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4345 .clock = 51200, 4346 .hdisplay = 1024, 4347 .hsync_start = 1024 + 100, 4348 .hsync_end = 1024 + 100 + 100, 4349 .htotal = 1024 + 100 + 100 + 120, 4350 .vdisplay = 600, 4351 .vsync_start = 600 + 10, 4352 .vsync_end = 600 + 10 + 10, 4353 .vtotal = 600 + 10 + 10 + 15, 4354 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4355 }; 4356 4357 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4358 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4359 .num_modes = 1, 4360 .bpc = 8, 4361 .size = { 4362 .width = 154, 4363 .height = 90, 4364 }, 4365 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4366 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4367 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4368 }; 4369 4370 static const struct drm_display_mode arm_rtsm_mode[] = { 4371 { 4372 .clock = 65000, 4373 .hdisplay = 1024, 4374 .hsync_start = 1024 + 24, 4375 .hsync_end = 1024 + 24 + 136, 4376 .htotal = 1024 + 24 + 136 + 160, 4377 .vdisplay = 768, 4378 .vsync_start = 768 + 3, 4379 .vsync_end = 768 + 3 + 6, 4380 .vtotal = 768 + 3 + 6 + 29, 4381 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4382 }, 4383 }; 4384 4385 static const struct panel_desc arm_rtsm = { 4386 .modes = arm_rtsm_mode, 4387 .num_modes = 1, 4388 .bpc = 8, 4389 .size = { 4390 .width = 400, 4391 .height = 300, 4392 }, 4393 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4394 }; 4395 4396 static const struct of_device_id platform_of_match[] = { 4397 { 4398 .compatible = "ampire,am-1280800n3tzqw-t00h", 4399 .data = &ire_am_1280800n3tzqw_t00h, 4400 }, { 4401 .compatible = "ampire,am-480272h3tmqw-t01h", 4402 .data = &ire_am_480272h3tmqw_t01h, 4403 }, { 4404 .compatible = "ampire,am-800480l1tmqw-t00h", 4405 .data = &ire_am_800480l1tmqw_t00h, 4406 }, { 4407 .compatible = "ampire,am800480r3tmqwa1h", 4408 .data = &ire_am800480r3tmqwa1h, 4409 }, { 4410 .compatible = "ampire,am800600p5tmqw-tb8h", 4411 .data = &ire_am800600p5tmqwtb8h, 4412 }, { 4413 .compatible = "arm,rtsm-display", 4414 .data = &arm_rtsm, 4415 }, { 4416 .compatible = "armadeus,st0700-adapt", 4417 .data = &armadeus_st0700_adapt, 4418 }, { 4419 .compatible = "auo,b101aw03", 4420 .data = &auo_b101aw03, 4421 }, { 4422 .compatible = "auo,b101xtn01", 4423 .data = &auo_b101xtn01, 4424 }, { 4425 .compatible = "auo,b116xw03", 4426 .data = &auo_b116xw03, 4427 }, { 4428 .compatible = "auo,g070vvn01", 4429 .data = &auo_g070vvn01, 4430 }, { 4431 .compatible = "auo,g101evn010", 4432 .data = &auo_g101evn010, 4433 }, { 4434 .compatible = "auo,g104sn02", 4435 .data = &auo_g104sn02, 4436 }, { 4437 .compatible = "auo,g121ean01", 4438 .data = &auo_g121ean01, 4439 }, { 4440 .compatible = "auo,g133han01", 4441 .data = &auo_g133han01, 4442 }, { 4443 .compatible = "auo,g156han04", 4444 .data = &auo_g156han04, 4445 }, { 4446 .compatible = "auo,g156xtn01", 4447 .data = &auo_g156xtn01, 4448 }, { 4449 .compatible = "auo,g185han01", 4450 .data = &auo_g185han01, 4451 }, { 4452 .compatible = "auo,g190ean01", 4453 .data = &auo_g190ean01, 4454 }, { 4455 .compatible = "auo,p320hvn03", 4456 .data = &auo_p320hvn03, 4457 }, { 4458 .compatible = "auo,t215hvn01", 4459 .data = &auo_t215hvn01, 4460 }, { 4461 .compatible = "avic,tm070ddh03", 4462 .data = &avic_tm070ddh03, 4463 }, { 4464 .compatible = "bananapi,s070wv20-ct16", 4465 .data = &bananapi_s070wv20_ct16, 4466 }, { 4467 .compatible = "boe,bp082wx1-100", 4468 .data = &boe_bp082wx1_100, 4469 }, { 4470 .compatible = "boe,bp101wx1-100", 4471 .data = &boe_bp101wx1_100, 4472 }, { 4473 .compatible = "boe,ev121wxm-n10-1850", 4474 .data = &boe_ev121wxm_n10_1850, 4475 }, { 4476 .compatible = "boe,hv070wsa-100", 4477 .data = &boe_hv070wsa 4478 }, { 4479 .compatible = "cct,cmt430b19n00", 4480 .data = &cct_cmt430b19n00, 4481 }, { 4482 .compatible = "cdtech,s043wq26h-ct7", 4483 .data = &cdtech_s043wq26h_ct7, 4484 }, { 4485 .compatible = "cdtech,s070pws19hp-fc21", 4486 .data = &cdtech_s070pws19hp_fc21, 4487 }, { 4488 .compatible = "cdtech,s070swv29hg-dc44", 4489 .data = &cdtech_s070swv29hg_dc44, 4490 }, { 4491 .compatible = "cdtech,s070wv95-ct16", 4492 .data = &cdtech_s070wv95_ct16, 4493 }, { 4494 .compatible = "chefree,ch101olhlwh-002", 4495 .data = &chefree_ch101olhlwh_002, 4496 }, { 4497 .compatible = "chunghwa,claa070wp03xg", 4498 .data = &chunghwa_claa070wp03xg, 4499 }, { 4500 .compatible = "chunghwa,claa101wa01a", 4501 .data = &chunghwa_claa101wa01a 4502 }, { 4503 .compatible = "chunghwa,claa101wb01", 4504 .data = &chunghwa_claa101wb01 4505 }, { 4506 .compatible = "dataimage,fg040346dsswbg04", 4507 .data = &dataimage_fg040346dsswbg04, 4508 }, { 4509 .compatible = "dataimage,fg1001l0dsswmg01", 4510 .data = &dataimage_fg1001l0dsswmg01, 4511 }, { 4512 .compatible = "dataimage,scf0700c48ggu18", 4513 .data = &dataimage_scf0700c48ggu18, 4514 }, { 4515 .compatible = "dlc,dlc0700yzg-1", 4516 .data = &dlc_dlc0700yzg_1, 4517 }, { 4518 .compatible = "dlc,dlc1010gig", 4519 .data = &dlc_dlc1010gig, 4520 }, { 4521 .compatible = "edt,et035012dm6", 4522 .data = &edt_et035012dm6, 4523 }, { 4524 .compatible = "edt,etm0350g0dh6", 4525 .data = &edt_etm0350g0dh6, 4526 }, { 4527 .compatible = "edt,etm043080dh6gp", 4528 .data = &edt_etm043080dh6gp, 4529 }, { 4530 .compatible = "edt,etm0430g0dh6", 4531 .data = &edt_etm0430g0dh6, 4532 }, { 4533 .compatible = "edt,et057090dhu", 4534 .data = &edt_et057090dhu, 4535 }, { 4536 .compatible = "edt,et070080dh6", 4537 .data = &edt_etm0700g0dh6, 4538 }, { 4539 .compatible = "edt,etm0700g0dh6", 4540 .data = &edt_etm0700g0dh6, 4541 }, { 4542 .compatible = "edt,etm0700g0bdh6", 4543 .data = &edt_etm0700g0bdh6, 4544 }, { 4545 .compatible = "edt,etm0700g0edh6", 4546 .data = &edt_etm0700g0bdh6, 4547 }, { 4548 .compatible = "edt,etml0700y5dha", 4549 .data = &edt_etml0700y5dha, 4550 }, { 4551 .compatible = "edt,etml1010g3dra", 4552 .data = &edt_etml1010g3dra, 4553 }, { 4554 .compatible = "edt,etmv570g2dhu", 4555 .data = &edt_etmv570g2dhu, 4556 }, { 4557 .compatible = "eink,vb3300-kca", 4558 .data = &eink_vb3300_kca, 4559 }, { 4560 .compatible = "evervision,vgg644804", 4561 .data = &evervision_vgg644804, 4562 }, { 4563 .compatible = "evervision,vgg804821", 4564 .data = &evervision_vgg804821, 4565 }, { 4566 .compatible = "foxlink,fl500wvr00-a0t", 4567 .data = &foxlink_fl500wvr00_a0t, 4568 }, { 4569 .compatible = "frida,frd350h54004", 4570 .data = &frida_frd350h54004, 4571 }, { 4572 .compatible = "friendlyarm,hd702e", 4573 .data = &friendlyarm_hd702e, 4574 }, { 4575 .compatible = "giantplus,gpg482739qs5", 4576 .data = &giantplus_gpg482739qs5 4577 }, { 4578 .compatible = "giantplus,gpm940b0", 4579 .data = &giantplus_gpm940b0, 4580 }, { 4581 .compatible = "hannstar,hsd070pww1", 4582 .data = &hannstar_hsd070pww1, 4583 }, { 4584 .compatible = "hannstar,hsd100pxn1", 4585 .data = &hannstar_hsd100pxn1, 4586 }, { 4587 .compatible = "hannstar,hsd101pww2", 4588 .data = &hannstar_hsd101pww2, 4589 }, { 4590 .compatible = "hit,tx23d38vm0caa", 4591 .data = &hitachi_tx23d38vm0caa 4592 }, { 4593 .compatible = "innolux,at043tn24", 4594 .data = &innolux_at043tn24, 4595 }, { 4596 .compatible = "innolux,at070tn92", 4597 .data = &innolux_at070tn92, 4598 }, { 4599 .compatible = "innolux,g070ace-l01", 4600 .data = &innolux_g070ace_l01, 4601 }, { 4602 .compatible = "innolux,g070y2-l01", 4603 .data = &innolux_g070y2_l01, 4604 }, { 4605 .compatible = "innolux,g070y2-t02", 4606 .data = &innolux_g070y2_t02, 4607 }, { 4608 .compatible = "innolux,g101ice-l01", 4609 .data = &innolux_g101ice_l01 4610 }, { 4611 .compatible = "innolux,g121i1-l01", 4612 .data = &innolux_g121i1_l01 4613 }, { 4614 .compatible = "innolux,g121x1-l03", 4615 .data = &innolux_g121x1_l03, 4616 }, { 4617 .compatible = "innolux,g121xce-l01", 4618 .data = &innolux_g121xce_l01, 4619 }, { 4620 .compatible = "innolux,g156hce-l01", 4621 .data = &innolux_g156hce_l01, 4622 }, { 4623 .compatible = "innolux,n156bge-l21", 4624 .data = &innolux_n156bge_l21, 4625 }, { 4626 .compatible = "innolux,zj070na-01p", 4627 .data = &innolux_zj070na_01p, 4628 }, { 4629 .compatible = "koe,tx14d24vm1bpa", 4630 .data = &koe_tx14d24vm1bpa, 4631 }, { 4632 .compatible = "koe,tx26d202vm0bwa", 4633 .data = &koe_tx26d202vm0bwa, 4634 }, { 4635 .compatible = "koe,tx31d200vm0baa", 4636 .data = &koe_tx31d200vm0baa, 4637 }, { 4638 .compatible = "kyo,tcg121xglp", 4639 .data = &kyo_tcg121xglp, 4640 }, { 4641 .compatible = "lemaker,bl035-rgb-002", 4642 .data = &lemaker_bl035_rgb_002, 4643 }, { 4644 .compatible = "lg,lb070wv8", 4645 .data = &lg_lb070wv8, 4646 }, { 4647 .compatible = "logicpd,type28", 4648 .data = &logicpd_type_28, 4649 }, { 4650 .compatible = "logictechno,lt161010-2nhc", 4651 .data = &logictechno_lt161010_2nh, 4652 }, { 4653 .compatible = "logictechno,lt161010-2nhr", 4654 .data = &logictechno_lt161010_2nh, 4655 }, { 4656 .compatible = "logictechno,lt170410-2whc", 4657 .data = &logictechno_lt170410_2whc, 4658 }, { 4659 .compatible = "logictechno,lttd800480070-l2rt", 4660 .data = &logictechno_lttd800480070_l2rt, 4661 }, { 4662 .compatible = "logictechno,lttd800480070-l6wh-rt", 4663 .data = &logictechno_lttd800480070_l6wh_rt, 4664 }, { 4665 .compatible = "mitsubishi,aa070mc01-ca1", 4666 .data = &mitsubishi_aa070mc01, 4667 }, { 4668 .compatible = "mitsubishi,aa084xe01", 4669 .data = &mitsubishi_aa084xe01, 4670 }, { 4671 .compatible = "multi-inno,mi0700s4t-6", 4672 .data = &multi_inno_mi0700s4t_6, 4673 }, { 4674 .compatible = "multi-inno,mi0800ft-9", 4675 .data = &multi_inno_mi0800ft_9, 4676 }, { 4677 .compatible = "multi-inno,mi1010ait-1cp", 4678 .data = &multi_inno_mi1010ait_1cp, 4679 }, { 4680 .compatible = "nec,nl12880bc20-05", 4681 .data = &nec_nl12880bc20_05, 4682 }, { 4683 .compatible = "nec,nl4827hc19-05b", 4684 .data = &nec_nl4827hc19_05b, 4685 }, { 4686 .compatible = "netron-dy,e231732", 4687 .data = &netron_dy_e231732, 4688 }, { 4689 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4690 .data = &newhaven_nhd_43_480272ef_atxl, 4691 }, { 4692 .compatible = "nlt,nl192108ac18-02d", 4693 .data = &nlt_nl192108ac18_02d, 4694 }, { 4695 .compatible = "nvd,9128", 4696 .data = &nvd_9128, 4697 }, { 4698 .compatible = "okaya,rs800480t-7x0gp", 4699 .data = &okaya_rs800480t_7x0gp, 4700 }, { 4701 .compatible = "olimex,lcd-olinuxino-43-ts", 4702 .data = &olimex_lcd_olinuxino_43ts, 4703 }, { 4704 .compatible = "ontat,yx700wv03", 4705 .data = &ontat_yx700wv03, 4706 }, { 4707 .compatible = "ortustech,com37h3m05dtc", 4708 .data = &ortustech_com37h3m, 4709 }, { 4710 .compatible = "ortustech,com37h3m99dtc", 4711 .data = &ortustech_com37h3m, 4712 }, { 4713 .compatible = "ortustech,com43h4m85ulc", 4714 .data = &ortustech_com43h4m85ulc, 4715 }, { 4716 .compatible = "osddisplays,osd070t1718-19ts", 4717 .data = &osddisplays_osd070t1718_19ts, 4718 }, { 4719 .compatible = "pda,91-00156-a0", 4720 .data = &pda_91_00156_a0, 4721 }, { 4722 .compatible = "powertip,ph128800t006-zhc01", 4723 .data = &powertip_ph128800t006_zhc01, 4724 }, { 4725 .compatible = "powertip,ph800480t013-idf02", 4726 .data = &powertip_ph800480t013_idf02, 4727 }, { 4728 .compatible = "qiaodian,qd43003c0-40", 4729 .data = &qd43003c0_40, 4730 }, { 4731 .compatible = "qishenglong,gopher2b-lcd", 4732 .data = &qishenglong_gopher2b_lcd, 4733 }, { 4734 .compatible = "rocktech,rk043fn48h", 4735 .data = &rocktech_rk043fn48h, 4736 }, { 4737 .compatible = "rocktech,rk070er9427", 4738 .data = &rocktech_rk070er9427, 4739 }, { 4740 .compatible = "rocktech,rk101ii01d-ct", 4741 .data = &rocktech_rk101ii01d_ct, 4742 }, { 4743 .compatible = "samsung,ltl101al01", 4744 .data = &samsung_ltl101al01, 4745 }, { 4746 .compatible = "samsung,ltn101nt05", 4747 .data = &samsung_ltn101nt05, 4748 }, { 4749 .compatible = "satoz,sat050at40h12r2", 4750 .data = &satoz_sat050at40h12r2, 4751 }, { 4752 .compatible = "sharp,lq035q7db03", 4753 .data = &sharp_lq035q7db03, 4754 }, { 4755 .compatible = "sharp,lq070y3dg3b", 4756 .data = &sharp_lq070y3dg3b, 4757 }, { 4758 .compatible = "sharp,lq101k1ly04", 4759 .data = &sharp_lq101k1ly04, 4760 }, { 4761 .compatible = "sharp,ls020b1dd01d", 4762 .data = &sharp_ls020b1dd01d, 4763 }, { 4764 .compatible = "shelly,sca07010-bfn-lnn", 4765 .data = &shelly_sca07010_bfn_lnn, 4766 }, { 4767 .compatible = "starry,kr070pe2t", 4768 .data = &starry_kr070pe2t, 4769 }, { 4770 .compatible = "startek,kd070wvfpa", 4771 .data = &startek_kd070wvfpa, 4772 }, { 4773 .compatible = "team-source-display,tst043015cmhx", 4774 .data = &tsd_tst043015cmhx, 4775 }, { 4776 .compatible = "tfc,s9700rtwv43tr-01b", 4777 .data = &tfc_s9700rtwv43tr_01b, 4778 }, { 4779 .compatible = "tianma,tm070jdhg30", 4780 .data = &tianma_tm070jdhg30, 4781 }, { 4782 .compatible = "tianma,tm070jvhg33", 4783 .data = &tianma_tm070jvhg33, 4784 }, { 4785 .compatible = "tianma,tm070rvhg71", 4786 .data = &tianma_tm070rvhg71, 4787 }, { 4788 .compatible = "ti,nspire-cx-lcd-panel", 4789 .data = &ti_nspire_cx_lcd_panel, 4790 }, { 4791 .compatible = "ti,nspire-classic-lcd-panel", 4792 .data = &ti_nspire_classic_lcd_panel, 4793 }, { 4794 .compatible = "toshiba,lt089ac29000", 4795 .data = &toshiba_lt089ac29000, 4796 }, { 4797 .compatible = "tpk,f07a-0102", 4798 .data = &tpk_f07a_0102, 4799 }, { 4800 .compatible = "tpk,f10a-0102", 4801 .data = &tpk_f10a_0102, 4802 }, { 4803 .compatible = "urt,umsh-8596md-t", 4804 .data = &urt_umsh_8596md_parallel, 4805 }, { 4806 .compatible = "urt,umsh-8596md-1t", 4807 .data = &urt_umsh_8596md_parallel, 4808 }, { 4809 .compatible = "urt,umsh-8596md-7t", 4810 .data = &urt_umsh_8596md_parallel, 4811 }, { 4812 .compatible = "urt,umsh-8596md-11t", 4813 .data = &urt_umsh_8596md_lvds, 4814 }, { 4815 .compatible = "urt,umsh-8596md-19t", 4816 .data = &urt_umsh_8596md_lvds, 4817 }, { 4818 .compatible = "urt,umsh-8596md-20t", 4819 .data = &urt_umsh_8596md_parallel, 4820 }, { 4821 .compatible = "vivax,tpc9150-panel", 4822 .data = &vivax_tpc9150_panel, 4823 }, { 4824 .compatible = "vxt,vl050-8048nt-c01", 4825 .data = &vl050_8048nt_c01, 4826 }, { 4827 .compatible = "winstar,wf35ltiacd", 4828 .data = &winstar_wf35ltiacd, 4829 }, { 4830 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4831 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4832 }, { 4833 /* Must be the last entry */ 4834 .compatible = "panel-dpi", 4835 .data = &panel_dpi, 4836 }, { 4837 /* sentinel */ 4838 } 4839 }; 4840 MODULE_DEVICE_TABLE(of, platform_of_match); 4841 4842 static int panel_simple_platform_probe(struct platform_device *pdev) 4843 { 4844 const struct panel_desc *desc; 4845 4846 desc = of_device_get_match_data(&pdev->dev); 4847 if (!desc) 4848 return -ENODEV; 4849 4850 return panel_simple_probe(&pdev->dev, desc); 4851 } 4852 4853 static void panel_simple_platform_remove(struct platform_device *pdev) 4854 { 4855 panel_simple_remove(&pdev->dev); 4856 } 4857 4858 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4859 { 4860 panel_simple_shutdown(&pdev->dev); 4861 } 4862 4863 static const struct dev_pm_ops panel_simple_pm_ops = { 4864 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4865 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4866 pm_runtime_force_resume) 4867 }; 4868 4869 static struct platform_driver panel_simple_platform_driver = { 4870 .driver = { 4871 .name = "panel-simple", 4872 .of_match_table = platform_of_match, 4873 .pm = &panel_simple_pm_ops, 4874 }, 4875 .probe = panel_simple_platform_probe, 4876 .remove_new = panel_simple_platform_remove, 4877 .shutdown = panel_simple_platform_shutdown, 4878 }; 4879 4880 struct panel_desc_dsi { 4881 struct panel_desc desc; 4882 4883 unsigned long flags; 4884 enum mipi_dsi_pixel_format format; 4885 unsigned int lanes; 4886 }; 4887 4888 static const struct drm_display_mode auo_b080uan01_mode = { 4889 .clock = 154500, 4890 .hdisplay = 1200, 4891 .hsync_start = 1200 + 62, 4892 .hsync_end = 1200 + 62 + 4, 4893 .htotal = 1200 + 62 + 4 + 62, 4894 .vdisplay = 1920, 4895 .vsync_start = 1920 + 9, 4896 .vsync_end = 1920 + 9 + 2, 4897 .vtotal = 1920 + 9 + 2 + 8, 4898 }; 4899 4900 static const struct panel_desc_dsi auo_b080uan01 = { 4901 .desc = { 4902 .modes = &auo_b080uan01_mode, 4903 .num_modes = 1, 4904 .bpc = 8, 4905 .size = { 4906 .width = 108, 4907 .height = 272, 4908 }, 4909 .connector_type = DRM_MODE_CONNECTOR_DSI, 4910 }, 4911 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4912 .format = MIPI_DSI_FMT_RGB888, 4913 .lanes = 4, 4914 }; 4915 4916 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4917 .clock = 160000, 4918 .hdisplay = 1200, 4919 .hsync_start = 1200 + 120, 4920 .hsync_end = 1200 + 120 + 20, 4921 .htotal = 1200 + 120 + 20 + 21, 4922 .vdisplay = 1920, 4923 .vsync_start = 1920 + 21, 4924 .vsync_end = 1920 + 21 + 3, 4925 .vtotal = 1920 + 21 + 3 + 18, 4926 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4927 }; 4928 4929 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4930 .desc = { 4931 .modes = &boe_tv080wum_nl0_mode, 4932 .num_modes = 1, 4933 .size = { 4934 .width = 107, 4935 .height = 172, 4936 }, 4937 .connector_type = DRM_MODE_CONNECTOR_DSI, 4938 }, 4939 .flags = MIPI_DSI_MODE_VIDEO | 4940 MIPI_DSI_MODE_VIDEO_BURST | 4941 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4942 .format = MIPI_DSI_FMT_RGB888, 4943 .lanes = 4, 4944 }; 4945 4946 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4947 .clock = 71000, 4948 .hdisplay = 800, 4949 .hsync_start = 800 + 32, 4950 .hsync_end = 800 + 32 + 1, 4951 .htotal = 800 + 32 + 1 + 57, 4952 .vdisplay = 1280, 4953 .vsync_start = 1280 + 28, 4954 .vsync_end = 1280 + 28 + 1, 4955 .vtotal = 1280 + 28 + 1 + 14, 4956 }; 4957 4958 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4959 .desc = { 4960 .modes = &lg_ld070wx3_sl01_mode, 4961 .num_modes = 1, 4962 .bpc = 8, 4963 .size = { 4964 .width = 94, 4965 .height = 151, 4966 }, 4967 .connector_type = DRM_MODE_CONNECTOR_DSI, 4968 }, 4969 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4970 .format = MIPI_DSI_FMT_RGB888, 4971 .lanes = 4, 4972 }; 4973 4974 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4975 .clock = 67000, 4976 .hdisplay = 720, 4977 .hsync_start = 720 + 12, 4978 .hsync_end = 720 + 12 + 4, 4979 .htotal = 720 + 12 + 4 + 112, 4980 .vdisplay = 1280, 4981 .vsync_start = 1280 + 8, 4982 .vsync_end = 1280 + 8 + 4, 4983 .vtotal = 1280 + 8 + 4 + 12, 4984 }; 4985 4986 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4987 .desc = { 4988 .modes = &lg_lh500wx1_sd03_mode, 4989 .num_modes = 1, 4990 .bpc = 8, 4991 .size = { 4992 .width = 62, 4993 .height = 110, 4994 }, 4995 .connector_type = DRM_MODE_CONNECTOR_DSI, 4996 }, 4997 .flags = MIPI_DSI_MODE_VIDEO, 4998 .format = MIPI_DSI_FMT_RGB888, 4999 .lanes = 4, 5000 }; 5001 5002 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5003 .clock = 157200, 5004 .hdisplay = 1920, 5005 .hsync_start = 1920 + 154, 5006 .hsync_end = 1920 + 154 + 16, 5007 .htotal = 1920 + 154 + 16 + 32, 5008 .vdisplay = 1200, 5009 .vsync_start = 1200 + 17, 5010 .vsync_end = 1200 + 17 + 2, 5011 .vtotal = 1200 + 17 + 2 + 16, 5012 }; 5013 5014 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5015 .desc = { 5016 .modes = &panasonic_vvx10f004b00_mode, 5017 .num_modes = 1, 5018 .bpc = 8, 5019 .size = { 5020 .width = 217, 5021 .height = 136, 5022 }, 5023 .connector_type = DRM_MODE_CONNECTOR_DSI, 5024 }, 5025 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5026 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5027 .format = MIPI_DSI_FMT_RGB888, 5028 .lanes = 4, 5029 }; 5030 5031 static const struct drm_display_mode lg_acx467akm_7_mode = { 5032 .clock = 150000, 5033 .hdisplay = 1080, 5034 .hsync_start = 1080 + 2, 5035 .hsync_end = 1080 + 2 + 2, 5036 .htotal = 1080 + 2 + 2 + 2, 5037 .vdisplay = 1920, 5038 .vsync_start = 1920 + 2, 5039 .vsync_end = 1920 + 2 + 2, 5040 .vtotal = 1920 + 2 + 2 + 2, 5041 }; 5042 5043 static const struct panel_desc_dsi lg_acx467akm_7 = { 5044 .desc = { 5045 .modes = &lg_acx467akm_7_mode, 5046 .num_modes = 1, 5047 .bpc = 8, 5048 .size = { 5049 .width = 62, 5050 .height = 110, 5051 }, 5052 .connector_type = DRM_MODE_CONNECTOR_DSI, 5053 }, 5054 .flags = 0, 5055 .format = MIPI_DSI_FMT_RGB888, 5056 .lanes = 4, 5057 }; 5058 5059 static const struct drm_display_mode osd101t2045_53ts_mode = { 5060 .clock = 154500, 5061 .hdisplay = 1920, 5062 .hsync_start = 1920 + 112, 5063 .hsync_end = 1920 + 112 + 16, 5064 .htotal = 1920 + 112 + 16 + 32, 5065 .vdisplay = 1200, 5066 .vsync_start = 1200 + 16, 5067 .vsync_end = 1200 + 16 + 2, 5068 .vtotal = 1200 + 16 + 2 + 16, 5069 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5070 }; 5071 5072 static const struct panel_desc_dsi osd101t2045_53ts = { 5073 .desc = { 5074 .modes = &osd101t2045_53ts_mode, 5075 .num_modes = 1, 5076 .bpc = 8, 5077 .size = { 5078 .width = 217, 5079 .height = 136, 5080 }, 5081 .connector_type = DRM_MODE_CONNECTOR_DSI, 5082 }, 5083 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5084 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5085 MIPI_DSI_MODE_NO_EOT_PACKET, 5086 .format = MIPI_DSI_FMT_RGB888, 5087 .lanes = 4, 5088 }; 5089 5090 static const struct of_device_id dsi_of_match[] = { 5091 { 5092 .compatible = "auo,b080uan01", 5093 .data = &auo_b080uan01 5094 }, { 5095 .compatible = "boe,tv080wum-nl0", 5096 .data = &boe_tv080wum_nl0 5097 }, { 5098 .compatible = "lg,ld070wx3-sl01", 5099 .data = &lg_ld070wx3_sl01 5100 }, { 5101 .compatible = "lg,lh500wx1-sd03", 5102 .data = &lg_lh500wx1_sd03 5103 }, { 5104 .compatible = "panasonic,vvx10f004b00", 5105 .data = &panasonic_vvx10f004b00 5106 }, { 5107 .compatible = "lg,acx467akm-7", 5108 .data = &lg_acx467akm_7 5109 }, { 5110 .compatible = "osddisplays,osd101t2045-53ts", 5111 .data = &osd101t2045_53ts 5112 }, { 5113 /* sentinel */ 5114 } 5115 }; 5116 MODULE_DEVICE_TABLE(of, dsi_of_match); 5117 5118 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5119 { 5120 const struct panel_desc_dsi *desc; 5121 int err; 5122 5123 desc = of_device_get_match_data(&dsi->dev); 5124 if (!desc) 5125 return -ENODEV; 5126 5127 err = panel_simple_probe(&dsi->dev, &desc->desc); 5128 if (err < 0) 5129 return err; 5130 5131 dsi->mode_flags = desc->flags; 5132 dsi->format = desc->format; 5133 dsi->lanes = desc->lanes; 5134 5135 err = mipi_dsi_attach(dsi); 5136 if (err) { 5137 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5138 5139 drm_panel_remove(&panel->base); 5140 } 5141 5142 return err; 5143 } 5144 5145 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5146 { 5147 int err; 5148 5149 err = mipi_dsi_detach(dsi); 5150 if (err < 0) 5151 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5152 5153 panel_simple_remove(&dsi->dev); 5154 } 5155 5156 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5157 { 5158 panel_simple_shutdown(&dsi->dev); 5159 } 5160 5161 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5162 .driver = { 5163 .name = "panel-simple-dsi", 5164 .of_match_table = dsi_of_match, 5165 .pm = &panel_simple_pm_ops, 5166 }, 5167 .probe = panel_simple_dsi_probe, 5168 .remove = panel_simple_dsi_remove, 5169 .shutdown = panel_simple_dsi_shutdown, 5170 }; 5171 5172 static int __init panel_simple_init(void) 5173 { 5174 int err; 5175 5176 err = platform_driver_register(&panel_simple_platform_driver); 5177 if (err < 0) 5178 return err; 5179 5180 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5181 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5182 if (err < 0) 5183 goto err_did_platform_register; 5184 } 5185 5186 return 0; 5187 5188 err_did_platform_register: 5189 platform_driver_unregister(&panel_simple_platform_driver); 5190 5191 return err; 5192 } 5193 module_init(panel_simple_init); 5194 5195 static void __exit panel_simple_exit(void) 5196 { 5197 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5198 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5199 5200 platform_driver_unregister(&panel_simple_platform_driver); 5201 } 5202 module_exit(panel_simple_exit); 5203 5204 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5205 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5206 MODULE_LICENSE("GPL and additional rights"); 5207