1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_mipi_dsi.h> 39 #include <drm/drm_panel.h> 40 41 /** 42 * struct panel_desc - Describes a simple panel. 43 */ 44 struct panel_desc { 45 /** 46 * @modes: Pointer to array of fixed modes appropriate for this panel. 47 * 48 * If only one mode then this can just be the address of the mode. 49 * NOTE: cannot be used with "timings" and also if this is specified 50 * then you cannot override the mode in the device tree. 51 */ 52 const struct drm_display_mode *modes; 53 54 /** @num_modes: Number of elements in modes array. */ 55 unsigned int num_modes; 56 57 /** 58 * @timings: Pointer to array of display timings 59 * 60 * NOTE: cannot be used with "modes" and also these will be used to 61 * validate a device tree override if one is present. 62 */ 63 const struct display_timing *timings; 64 65 /** @num_timings: Number of elements in timings array. */ 66 unsigned int num_timings; 67 68 /** @bpc: Bits per color. */ 69 unsigned int bpc; 70 71 /** @size: Structure containing the physical size of this panel. */ 72 struct { 73 /** 74 * @size.width: Width (in mm) of the active display area. 75 */ 76 unsigned int width; 77 78 /** 79 * @size.height: Height (in mm) of the active display area. 80 */ 81 unsigned int height; 82 } size; 83 84 /** @delay: Structure containing various delay values for this panel. */ 85 struct { 86 /** 87 * @delay.prepare: Time for the panel to become ready. 88 * 89 * The time (in milliseconds) that it takes for the panel to 90 * become ready and start receiving video data 91 */ 92 unsigned int prepare; 93 94 /** 95 * @delay.enable: Time for the panel to display a valid frame. 96 * 97 * The time (in milliseconds) that it takes for the panel to 98 * display the first valid frame after starting to receive 99 * video data. 100 */ 101 unsigned int enable; 102 103 /** 104 * @delay.disable: Time for the panel to turn the display off. 105 * 106 * The time (in milliseconds) that it takes for the panel to 107 * turn the display off (no content is visible). 108 */ 109 unsigned int disable; 110 111 /** 112 * @delay.unprepare: Time to power down completely. 113 * 114 * The time (in milliseconds) that it takes for the panel 115 * to power itself down completely. 116 * 117 * This time is used to prevent a future "prepare" from 118 * starting until at least this many milliseconds has passed. 119 * If at prepare time less time has passed since unprepare 120 * finished, the driver waits for the remaining time. 121 */ 122 unsigned int unprepare; 123 } delay; 124 125 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 126 u32 bus_format; 127 128 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 129 u32 bus_flags; 130 131 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 132 int connector_type; 133 }; 134 135 struct panel_simple { 136 struct drm_panel base; 137 bool enabled; 138 139 bool prepared; 140 141 ktime_t prepared_time; 142 ktime_t unprepared_time; 143 144 const struct panel_desc *desc; 145 146 struct regulator *supply; 147 struct i2c_adapter *ddc; 148 149 struct gpio_desc *enable_gpio; 150 151 struct edid *edid; 152 153 struct drm_display_mode override_mode; 154 155 enum drm_panel_orientation orientation; 156 }; 157 158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 159 { 160 return container_of(panel, struct panel_simple, base); 161 } 162 163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 164 struct drm_connector *connector) 165 { 166 struct drm_display_mode *mode; 167 unsigned int i, num = 0; 168 169 for (i = 0; i < panel->desc->num_timings; i++) { 170 const struct display_timing *dt = &panel->desc->timings[i]; 171 struct videomode vm; 172 173 videomode_from_timing(dt, &vm); 174 mode = drm_mode_create(connector->dev); 175 if (!mode) { 176 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 177 dt->hactive.typ, dt->vactive.typ); 178 continue; 179 } 180 181 drm_display_mode_from_videomode(&vm, mode); 182 183 mode->type |= DRM_MODE_TYPE_DRIVER; 184 185 if (panel->desc->num_timings == 1) 186 mode->type |= DRM_MODE_TYPE_PREFERRED; 187 188 drm_mode_probed_add(connector, mode); 189 num++; 190 } 191 192 return num; 193 } 194 195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 196 struct drm_connector *connector) 197 { 198 struct drm_display_mode *mode; 199 unsigned int i, num = 0; 200 201 for (i = 0; i < panel->desc->num_modes; i++) { 202 const struct drm_display_mode *m = &panel->desc->modes[i]; 203 204 mode = drm_mode_duplicate(connector->dev, m); 205 if (!mode) { 206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 207 m->hdisplay, m->vdisplay, 208 drm_mode_vrefresh(m)); 209 continue; 210 } 211 212 mode->type |= DRM_MODE_TYPE_DRIVER; 213 214 if (panel->desc->num_modes == 1) 215 mode->type |= DRM_MODE_TYPE_PREFERRED; 216 217 drm_mode_set_name(mode); 218 219 drm_mode_probed_add(connector, mode); 220 num++; 221 } 222 223 return num; 224 } 225 226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 227 struct drm_connector *connector) 228 { 229 struct drm_display_mode *mode; 230 bool has_override = panel->override_mode.type; 231 unsigned int num = 0; 232 233 if (!panel->desc) 234 return 0; 235 236 if (has_override) { 237 mode = drm_mode_duplicate(connector->dev, 238 &panel->override_mode); 239 if (mode) { 240 drm_mode_probed_add(connector, mode); 241 num = 1; 242 } else { 243 dev_err(panel->base.dev, "failed to add override mode\n"); 244 } 245 } 246 247 /* Only add timings if override was not there or failed to validate */ 248 if (num == 0 && panel->desc->num_timings) 249 num = panel_simple_get_timings_modes(panel, connector); 250 251 /* 252 * Only add fixed modes if timings/override added no mode. 253 * 254 * We should only ever have either the display timings specified 255 * or a fixed mode. Anything else is rather bogus. 256 */ 257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 258 if (num == 0) 259 num = panel_simple_get_display_modes(panel, connector); 260 261 connector->display_info.bpc = panel->desc->bpc; 262 connector->display_info.width_mm = panel->desc->size.width; 263 connector->display_info.height_mm = panel->desc->size.height; 264 if (panel->desc->bus_format) 265 drm_display_info_set_bus_formats(&connector->display_info, 266 &panel->desc->bus_format, 1); 267 connector->display_info.bus_flags = panel->desc->bus_flags; 268 269 return num; 270 } 271 272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 273 { 274 ktime_t now_ktime, min_ktime; 275 276 if (!min_ms) 277 return; 278 279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 280 now_ktime = ktime_get(); 281 282 if (ktime_before(now_ktime, min_ktime)) 283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 284 } 285 286 static int panel_simple_disable(struct drm_panel *panel) 287 { 288 struct panel_simple *p = to_panel_simple(panel); 289 290 if (!p->enabled) 291 return 0; 292 293 if (p->desc->delay.disable) 294 msleep(p->desc->delay.disable); 295 296 p->enabled = false; 297 298 return 0; 299 } 300 301 static int panel_simple_suspend(struct device *dev) 302 { 303 struct panel_simple *p = dev_get_drvdata(dev); 304 305 gpiod_set_value_cansleep(p->enable_gpio, 0); 306 regulator_disable(p->supply); 307 p->unprepared_time = ktime_get(); 308 309 kfree(p->edid); 310 p->edid = NULL; 311 312 return 0; 313 } 314 315 static int panel_simple_unprepare(struct drm_panel *panel) 316 { 317 struct panel_simple *p = to_panel_simple(panel); 318 int ret; 319 320 /* Unpreparing when already unprepared is a no-op */ 321 if (!p->prepared) 322 return 0; 323 324 pm_runtime_mark_last_busy(panel->dev); 325 ret = pm_runtime_put_autosuspend(panel->dev); 326 if (ret < 0) 327 return ret; 328 p->prepared = false; 329 330 return 0; 331 } 332 333 static int panel_simple_resume(struct device *dev) 334 { 335 struct panel_simple *p = dev_get_drvdata(dev); 336 int err; 337 338 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 339 340 err = regulator_enable(p->supply); 341 if (err < 0) { 342 dev_err(dev, "failed to enable supply: %d\n", err); 343 return err; 344 } 345 346 gpiod_set_value_cansleep(p->enable_gpio, 1); 347 348 if (p->desc->delay.prepare) 349 msleep(p->desc->delay.prepare); 350 351 p->prepared_time = ktime_get(); 352 353 return 0; 354 } 355 356 static int panel_simple_prepare(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 int ret; 360 361 /* Preparing when already prepared is a no-op */ 362 if (p->prepared) 363 return 0; 364 365 ret = pm_runtime_get_sync(panel->dev); 366 if (ret < 0) { 367 pm_runtime_put_autosuspend(panel->dev); 368 return ret; 369 } 370 371 p->prepared = true; 372 373 return 0; 374 } 375 376 static int panel_simple_enable(struct drm_panel *panel) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 380 if (p->enabled) 381 return 0; 382 383 if (p->desc->delay.enable) 384 msleep(p->desc->delay.enable); 385 386 p->enabled = true; 387 388 return 0; 389 } 390 391 static int panel_simple_get_modes(struct drm_panel *panel, 392 struct drm_connector *connector) 393 { 394 struct panel_simple *p = to_panel_simple(panel); 395 int num = 0; 396 397 /* probe EDID if a DDC bus is available */ 398 if (p->ddc) { 399 pm_runtime_get_sync(panel->dev); 400 401 if (!p->edid) 402 p->edid = drm_get_edid(connector, p->ddc); 403 404 if (p->edid) 405 num += drm_add_edid_modes(connector, p->edid); 406 407 pm_runtime_mark_last_busy(panel->dev); 408 pm_runtime_put_autosuspend(panel->dev); 409 } 410 411 /* add hard-coded panel modes */ 412 num += panel_simple_get_non_edid_modes(p, connector); 413 414 /* set up connector's "panel orientation" property */ 415 drm_connector_set_panel_orientation(connector, p->orientation); 416 417 return num; 418 } 419 420 static int panel_simple_get_timings(struct drm_panel *panel, 421 unsigned int num_timings, 422 struct display_timing *timings) 423 { 424 struct panel_simple *p = to_panel_simple(panel); 425 unsigned int i; 426 427 if (p->desc->num_timings < num_timings) 428 num_timings = p->desc->num_timings; 429 430 if (timings) 431 for (i = 0; i < num_timings; i++) 432 timings[i] = p->desc->timings[i]; 433 434 return p->desc->num_timings; 435 } 436 437 static const struct drm_panel_funcs panel_simple_funcs = { 438 .disable = panel_simple_disable, 439 .unprepare = panel_simple_unprepare, 440 .prepare = panel_simple_prepare, 441 .enable = panel_simple_enable, 442 .get_modes = panel_simple_get_modes, 443 .get_timings = panel_simple_get_timings, 444 }; 445 446 static struct panel_desc panel_dpi; 447 448 static int panel_dpi_probe(struct device *dev, 449 struct panel_simple *panel) 450 { 451 struct display_timing *timing; 452 const struct device_node *np; 453 struct panel_desc *desc; 454 unsigned int bus_flags; 455 struct videomode vm; 456 int ret; 457 458 np = dev->of_node; 459 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 460 if (!desc) 461 return -ENOMEM; 462 463 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 464 if (!timing) 465 return -ENOMEM; 466 467 ret = of_get_display_timing(np, "panel-timing", timing); 468 if (ret < 0) { 469 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 470 np); 471 return ret; 472 } 473 474 desc->timings = timing; 475 desc->num_timings = 1; 476 477 of_property_read_u32(np, "width-mm", &desc->size.width); 478 of_property_read_u32(np, "height-mm", &desc->size.height); 479 480 /* Extract bus_flags from display_timing */ 481 bus_flags = 0; 482 vm.flags = timing->flags; 483 drm_bus_flags_from_videomode(&vm, &bus_flags); 484 desc->bus_flags = bus_flags; 485 486 /* We do not know the connector for the DT node, so guess it */ 487 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 488 489 panel->desc = desc; 490 491 return 0; 492 } 493 494 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 495 (to_check->field.typ >= bounds->field.min && \ 496 to_check->field.typ <= bounds->field.max) 497 static void panel_simple_parse_panel_timing_node(struct device *dev, 498 struct panel_simple *panel, 499 const struct display_timing *ot) 500 { 501 const struct panel_desc *desc = panel->desc; 502 struct videomode vm; 503 unsigned int i; 504 505 if (WARN_ON(desc->num_modes)) { 506 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 507 return; 508 } 509 if (WARN_ON(!desc->num_timings)) { 510 dev_err(dev, "Reject override mode: no timings specified\n"); 511 return; 512 } 513 514 for (i = 0; i < panel->desc->num_timings; i++) { 515 const struct display_timing *dt = &panel->desc->timings[i]; 516 517 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 518 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 519 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 520 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 521 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 522 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 523 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 524 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 525 continue; 526 527 if (ot->flags != dt->flags) 528 continue; 529 530 videomode_from_timing(ot, &vm); 531 drm_display_mode_from_videomode(&vm, &panel->override_mode); 532 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 533 DRM_MODE_TYPE_PREFERRED; 534 break; 535 } 536 537 if (WARN_ON(!panel->override_mode.type)) 538 dev_err(dev, "Reject override mode: No display_timing found\n"); 539 } 540 541 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 542 { 543 struct panel_simple *panel; 544 struct display_timing dt; 545 struct device_node *ddc; 546 int connector_type; 547 u32 bus_flags; 548 int err; 549 550 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 551 if (!panel) 552 return -ENOMEM; 553 554 panel->enabled = false; 555 panel->prepared_time = 0; 556 panel->desc = desc; 557 558 panel->supply = devm_regulator_get(dev, "power"); 559 if (IS_ERR(panel->supply)) 560 return PTR_ERR(panel->supply); 561 562 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 563 GPIOD_OUT_LOW); 564 if (IS_ERR(panel->enable_gpio)) { 565 err = PTR_ERR(panel->enable_gpio); 566 if (err != -EPROBE_DEFER) 567 dev_err(dev, "failed to request GPIO: %d\n", err); 568 return err; 569 } 570 571 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 572 if (err) { 573 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 574 return err; 575 } 576 577 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 578 if (ddc) { 579 panel->ddc = of_find_i2c_adapter_by_node(ddc); 580 of_node_put(ddc); 581 582 if (!panel->ddc) 583 return -EPROBE_DEFER; 584 } 585 586 if (desc == &panel_dpi) { 587 /* Handle the generic panel-dpi binding */ 588 err = panel_dpi_probe(dev, panel); 589 if (err) 590 goto free_ddc; 591 } else { 592 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 593 panel_simple_parse_panel_timing_node(dev, panel, &dt); 594 } 595 596 connector_type = desc->connector_type; 597 /* Catch common mistakes for panels. */ 598 switch (connector_type) { 599 case 0: 600 dev_warn(dev, "Specify missing connector_type\n"); 601 connector_type = DRM_MODE_CONNECTOR_DPI; 602 break; 603 case DRM_MODE_CONNECTOR_LVDS: 604 WARN_ON(desc->bus_flags & 605 ~(DRM_BUS_FLAG_DE_LOW | 606 DRM_BUS_FLAG_DE_HIGH | 607 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 608 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 609 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 610 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 611 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 612 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 613 desc->bpc != 6); 614 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 615 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 616 desc->bpc != 8); 617 break; 618 case DRM_MODE_CONNECTOR_eDP: 619 dev_warn(dev, "eDP panels moved to panel-edp\n"); 620 err = -EINVAL; 621 goto free_ddc; 622 case DRM_MODE_CONNECTOR_DSI: 623 if (desc->bpc != 6 && desc->bpc != 8) 624 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 625 break; 626 case DRM_MODE_CONNECTOR_DPI: 627 bus_flags = DRM_BUS_FLAG_DE_LOW | 628 DRM_BUS_FLAG_DE_HIGH | 629 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 630 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 631 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 632 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 633 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 634 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 635 if (desc->bus_flags & ~bus_flags) 636 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 637 if (!(desc->bus_flags & bus_flags)) 638 dev_warn(dev, "Specify missing bus_flags\n"); 639 if (desc->bus_format == 0) 640 dev_warn(dev, "Specify missing bus_format\n"); 641 if (desc->bpc != 6 && desc->bpc != 8) 642 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 643 break; 644 default: 645 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 646 connector_type = DRM_MODE_CONNECTOR_DPI; 647 break; 648 } 649 650 dev_set_drvdata(dev, panel); 651 652 /* 653 * We use runtime PM for prepare / unprepare since those power the panel 654 * on and off and those can be very slow operations. This is important 655 * to optimize powering the panel on briefly to read the EDID before 656 * fully enabling the panel. 657 */ 658 pm_runtime_enable(dev); 659 pm_runtime_set_autosuspend_delay(dev, 1000); 660 pm_runtime_use_autosuspend(dev); 661 662 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 663 664 err = drm_panel_of_backlight(&panel->base); 665 if (err) 666 goto disable_pm_runtime; 667 668 drm_panel_add(&panel->base); 669 670 return 0; 671 672 disable_pm_runtime: 673 pm_runtime_dont_use_autosuspend(dev); 674 pm_runtime_disable(dev); 675 free_ddc: 676 if (panel->ddc) 677 put_device(&panel->ddc->dev); 678 679 return err; 680 } 681 682 static int panel_simple_remove(struct device *dev) 683 { 684 struct panel_simple *panel = dev_get_drvdata(dev); 685 686 drm_panel_remove(&panel->base); 687 drm_panel_disable(&panel->base); 688 drm_panel_unprepare(&panel->base); 689 690 pm_runtime_dont_use_autosuspend(dev); 691 pm_runtime_disable(dev); 692 if (panel->ddc) 693 put_device(&panel->ddc->dev); 694 695 return 0; 696 } 697 698 static void panel_simple_shutdown(struct device *dev) 699 { 700 struct panel_simple *panel = dev_get_drvdata(dev); 701 702 drm_panel_disable(&panel->base); 703 drm_panel_unprepare(&panel->base); 704 } 705 706 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 707 .clock = 71100, 708 .hdisplay = 1280, 709 .hsync_start = 1280 + 40, 710 .hsync_end = 1280 + 40 + 80, 711 .htotal = 1280 + 40 + 80 + 40, 712 .vdisplay = 800, 713 .vsync_start = 800 + 3, 714 .vsync_end = 800 + 3 + 10, 715 .vtotal = 800 + 3 + 10 + 10, 716 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 717 }; 718 719 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 720 .modes = &ire_am_1280800n3tzqw_t00h_mode, 721 .num_modes = 1, 722 .bpc = 6, 723 .size = { 724 .width = 217, 725 .height = 136, 726 }, 727 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 728 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 729 .connector_type = DRM_MODE_CONNECTOR_LVDS, 730 }; 731 732 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 733 .clock = 9000, 734 .hdisplay = 480, 735 .hsync_start = 480 + 2, 736 .hsync_end = 480 + 2 + 41, 737 .htotal = 480 + 2 + 41 + 2, 738 .vdisplay = 272, 739 .vsync_start = 272 + 2, 740 .vsync_end = 272 + 2 + 10, 741 .vtotal = 272 + 2 + 10 + 2, 742 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 743 }; 744 745 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 746 .modes = &ire_am_480272h3tmqw_t01h_mode, 747 .num_modes = 1, 748 .bpc = 8, 749 .size = { 750 .width = 105, 751 .height = 67, 752 }, 753 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 754 }; 755 756 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 757 .clock = 33333, 758 .hdisplay = 800, 759 .hsync_start = 800 + 0, 760 .hsync_end = 800 + 0 + 255, 761 .htotal = 800 + 0 + 255 + 0, 762 .vdisplay = 480, 763 .vsync_start = 480 + 2, 764 .vsync_end = 480 + 2 + 45, 765 .vtotal = 480 + 2 + 45 + 0, 766 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 767 }; 768 769 static const struct panel_desc ampire_am800480r3tmqwa1h = { 770 .modes = &ire_am800480r3tmqwa1h_mode, 771 .num_modes = 1, 772 .bpc = 6, 773 .size = { 774 .width = 152, 775 .height = 91, 776 }, 777 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 778 }; 779 780 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 781 .pixelclock = { 26400000, 33300000, 46800000 }, 782 .hactive = { 800, 800, 800 }, 783 .hfront_porch = { 16, 210, 354 }, 784 .hback_porch = { 45, 36, 6 }, 785 .hsync_len = { 1, 10, 40 }, 786 .vactive = { 480, 480, 480 }, 787 .vfront_porch = { 7, 22, 147 }, 788 .vback_porch = { 22, 13, 3 }, 789 .vsync_len = { 1, 10, 20 }, 790 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 791 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 792 }; 793 794 static const struct panel_desc armadeus_st0700_adapt = { 795 .timings = &santek_st0700i5y_rbslw_f_timing, 796 .num_timings = 1, 797 .bpc = 6, 798 .size = { 799 .width = 154, 800 .height = 86, 801 }, 802 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 803 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 804 }; 805 806 static const struct drm_display_mode auo_b101aw03_mode = { 807 .clock = 51450, 808 .hdisplay = 1024, 809 .hsync_start = 1024 + 156, 810 .hsync_end = 1024 + 156 + 8, 811 .htotal = 1024 + 156 + 8 + 156, 812 .vdisplay = 600, 813 .vsync_start = 600 + 16, 814 .vsync_end = 600 + 16 + 6, 815 .vtotal = 600 + 16 + 6 + 16, 816 }; 817 818 static const struct panel_desc auo_b101aw03 = { 819 .modes = &auo_b101aw03_mode, 820 .num_modes = 1, 821 .bpc = 6, 822 .size = { 823 .width = 223, 824 .height = 125, 825 }, 826 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 827 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 828 .connector_type = DRM_MODE_CONNECTOR_LVDS, 829 }; 830 831 static const struct drm_display_mode auo_b101xtn01_mode = { 832 .clock = 72000, 833 .hdisplay = 1366, 834 .hsync_start = 1366 + 20, 835 .hsync_end = 1366 + 20 + 70, 836 .htotal = 1366 + 20 + 70, 837 .vdisplay = 768, 838 .vsync_start = 768 + 14, 839 .vsync_end = 768 + 14 + 42, 840 .vtotal = 768 + 14 + 42, 841 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 842 }; 843 844 static const struct panel_desc auo_b101xtn01 = { 845 .modes = &auo_b101xtn01_mode, 846 .num_modes = 1, 847 .bpc = 6, 848 .size = { 849 .width = 223, 850 .height = 125, 851 }, 852 }; 853 854 static const struct display_timing auo_g070vvn01_timings = { 855 .pixelclock = { 33300000, 34209000, 45000000 }, 856 .hactive = { 800, 800, 800 }, 857 .hfront_porch = { 20, 40, 200 }, 858 .hback_porch = { 87, 40, 1 }, 859 .hsync_len = { 1, 48, 87 }, 860 .vactive = { 480, 480, 480 }, 861 .vfront_porch = { 5, 13, 200 }, 862 .vback_porch = { 31, 31, 29 }, 863 .vsync_len = { 1, 1, 3 }, 864 }; 865 866 static const struct panel_desc auo_g070vvn01 = { 867 .timings = &auo_g070vvn01_timings, 868 .num_timings = 1, 869 .bpc = 8, 870 .size = { 871 .width = 152, 872 .height = 91, 873 }, 874 .delay = { 875 .prepare = 200, 876 .enable = 50, 877 .disable = 50, 878 .unprepare = 1000, 879 }, 880 }; 881 882 static const struct drm_display_mode auo_g101evn010_mode = { 883 .clock = 68930, 884 .hdisplay = 1280, 885 .hsync_start = 1280 + 82, 886 .hsync_end = 1280 + 82 + 2, 887 .htotal = 1280 + 82 + 2 + 84, 888 .vdisplay = 800, 889 .vsync_start = 800 + 8, 890 .vsync_end = 800 + 8 + 2, 891 .vtotal = 800 + 8 + 2 + 6, 892 }; 893 894 static const struct panel_desc auo_g101evn010 = { 895 .modes = &auo_g101evn010_mode, 896 .num_modes = 1, 897 .bpc = 6, 898 .size = { 899 .width = 216, 900 .height = 135, 901 }, 902 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 903 .connector_type = DRM_MODE_CONNECTOR_LVDS, 904 }; 905 906 static const struct drm_display_mode auo_g104sn02_mode = { 907 .clock = 40000, 908 .hdisplay = 800, 909 .hsync_start = 800 + 40, 910 .hsync_end = 800 + 40 + 216, 911 .htotal = 800 + 40 + 216 + 128, 912 .vdisplay = 600, 913 .vsync_start = 600 + 10, 914 .vsync_end = 600 + 10 + 35, 915 .vtotal = 600 + 10 + 35 + 2, 916 }; 917 918 static const struct panel_desc auo_g104sn02 = { 919 .modes = &auo_g104sn02_mode, 920 .num_modes = 1, 921 .bpc = 8, 922 .size = { 923 .width = 211, 924 .height = 158, 925 }, 926 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 927 .connector_type = DRM_MODE_CONNECTOR_LVDS, 928 }; 929 930 static const struct drm_display_mode auo_g121ean01_mode = { 931 .clock = 66700, 932 .hdisplay = 1280, 933 .hsync_start = 1280 + 58, 934 .hsync_end = 1280 + 58 + 8, 935 .htotal = 1280 + 58 + 8 + 70, 936 .vdisplay = 800, 937 .vsync_start = 800 + 6, 938 .vsync_end = 800 + 6 + 4, 939 .vtotal = 800 + 6 + 4 + 10, 940 }; 941 942 static const struct panel_desc auo_g121ean01 = { 943 .modes = &auo_g121ean01_mode, 944 .num_modes = 1, 945 .bpc = 8, 946 .size = { 947 .width = 261, 948 .height = 163, 949 }, 950 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 951 .connector_type = DRM_MODE_CONNECTOR_LVDS, 952 }; 953 954 static const struct display_timing auo_g133han01_timings = { 955 .pixelclock = { 134000000, 141200000, 149000000 }, 956 .hactive = { 1920, 1920, 1920 }, 957 .hfront_porch = { 39, 58, 77 }, 958 .hback_porch = { 59, 88, 117 }, 959 .hsync_len = { 28, 42, 56 }, 960 .vactive = { 1080, 1080, 1080 }, 961 .vfront_porch = { 3, 8, 11 }, 962 .vback_porch = { 5, 14, 19 }, 963 .vsync_len = { 4, 14, 19 }, 964 }; 965 966 static const struct panel_desc auo_g133han01 = { 967 .timings = &auo_g133han01_timings, 968 .num_timings = 1, 969 .bpc = 8, 970 .size = { 971 .width = 293, 972 .height = 165, 973 }, 974 .delay = { 975 .prepare = 200, 976 .enable = 50, 977 .disable = 50, 978 .unprepare = 1000, 979 }, 980 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 981 .connector_type = DRM_MODE_CONNECTOR_LVDS, 982 }; 983 984 static const struct drm_display_mode auo_g156xtn01_mode = { 985 .clock = 76000, 986 .hdisplay = 1366, 987 .hsync_start = 1366 + 33, 988 .hsync_end = 1366 + 33 + 67, 989 .htotal = 1560, 990 .vdisplay = 768, 991 .vsync_start = 768 + 4, 992 .vsync_end = 768 + 4 + 4, 993 .vtotal = 806, 994 }; 995 996 static const struct panel_desc auo_g156xtn01 = { 997 .modes = &auo_g156xtn01_mode, 998 .num_modes = 1, 999 .bpc = 8, 1000 .size = { 1001 .width = 344, 1002 .height = 194, 1003 }, 1004 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1005 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1006 }; 1007 1008 static const struct display_timing auo_g185han01_timings = { 1009 .pixelclock = { 120000000, 144000000, 175000000 }, 1010 .hactive = { 1920, 1920, 1920 }, 1011 .hfront_porch = { 36, 120, 148 }, 1012 .hback_porch = { 24, 88, 108 }, 1013 .hsync_len = { 20, 48, 64 }, 1014 .vactive = { 1080, 1080, 1080 }, 1015 .vfront_porch = { 6, 10, 40 }, 1016 .vback_porch = { 2, 5, 20 }, 1017 .vsync_len = { 2, 5, 20 }, 1018 }; 1019 1020 static const struct panel_desc auo_g185han01 = { 1021 .timings = &auo_g185han01_timings, 1022 .num_timings = 1, 1023 .bpc = 8, 1024 .size = { 1025 .width = 409, 1026 .height = 230, 1027 }, 1028 .delay = { 1029 .prepare = 50, 1030 .enable = 200, 1031 .disable = 110, 1032 .unprepare = 1000, 1033 }, 1034 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1035 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1036 }; 1037 1038 static const struct display_timing auo_g190ean01_timings = { 1039 .pixelclock = { 90000000, 108000000, 135000000 }, 1040 .hactive = { 1280, 1280, 1280 }, 1041 .hfront_porch = { 126, 184, 1266 }, 1042 .hback_porch = { 84, 122, 844 }, 1043 .hsync_len = { 70, 102, 704 }, 1044 .vactive = { 1024, 1024, 1024 }, 1045 .vfront_porch = { 4, 26, 76 }, 1046 .vback_porch = { 2, 8, 25 }, 1047 .vsync_len = { 2, 8, 25 }, 1048 }; 1049 1050 static const struct panel_desc auo_g190ean01 = { 1051 .timings = &auo_g190ean01_timings, 1052 .num_timings = 1, 1053 .bpc = 8, 1054 .size = { 1055 .width = 376, 1056 .height = 301, 1057 }, 1058 .delay = { 1059 .prepare = 50, 1060 .enable = 200, 1061 .disable = 110, 1062 .unprepare = 1000, 1063 }, 1064 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1065 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1066 }; 1067 1068 static const struct display_timing auo_p320hvn03_timings = { 1069 .pixelclock = { 106000000, 148500000, 164000000 }, 1070 .hactive = { 1920, 1920, 1920 }, 1071 .hfront_porch = { 25, 50, 130 }, 1072 .hback_porch = { 25, 50, 130 }, 1073 .hsync_len = { 20, 40, 105 }, 1074 .vactive = { 1080, 1080, 1080 }, 1075 .vfront_porch = { 8, 17, 150 }, 1076 .vback_porch = { 8, 17, 150 }, 1077 .vsync_len = { 4, 11, 100 }, 1078 }; 1079 1080 static const struct panel_desc auo_p320hvn03 = { 1081 .timings = &auo_p320hvn03_timings, 1082 .num_timings = 1, 1083 .bpc = 8, 1084 .size = { 1085 .width = 698, 1086 .height = 393, 1087 }, 1088 .delay = { 1089 .prepare = 1, 1090 .enable = 450, 1091 .unprepare = 500, 1092 }, 1093 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1094 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1095 }; 1096 1097 static const struct drm_display_mode auo_t215hvn01_mode = { 1098 .clock = 148800, 1099 .hdisplay = 1920, 1100 .hsync_start = 1920 + 88, 1101 .hsync_end = 1920 + 88 + 44, 1102 .htotal = 1920 + 88 + 44 + 148, 1103 .vdisplay = 1080, 1104 .vsync_start = 1080 + 4, 1105 .vsync_end = 1080 + 4 + 5, 1106 .vtotal = 1080 + 4 + 5 + 36, 1107 }; 1108 1109 static const struct panel_desc auo_t215hvn01 = { 1110 .modes = &auo_t215hvn01_mode, 1111 .num_modes = 1, 1112 .bpc = 8, 1113 .size = { 1114 .width = 430, 1115 .height = 270, 1116 }, 1117 .delay = { 1118 .disable = 5, 1119 .unprepare = 1000, 1120 } 1121 }; 1122 1123 static const struct drm_display_mode avic_tm070ddh03_mode = { 1124 .clock = 51200, 1125 .hdisplay = 1024, 1126 .hsync_start = 1024 + 160, 1127 .hsync_end = 1024 + 160 + 4, 1128 .htotal = 1024 + 160 + 4 + 156, 1129 .vdisplay = 600, 1130 .vsync_start = 600 + 17, 1131 .vsync_end = 600 + 17 + 1, 1132 .vtotal = 600 + 17 + 1 + 17, 1133 }; 1134 1135 static const struct panel_desc avic_tm070ddh03 = { 1136 .modes = &avic_tm070ddh03_mode, 1137 .num_modes = 1, 1138 .bpc = 8, 1139 .size = { 1140 .width = 154, 1141 .height = 90, 1142 }, 1143 .delay = { 1144 .prepare = 20, 1145 .enable = 200, 1146 .disable = 200, 1147 }, 1148 }; 1149 1150 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1151 .clock = 30000, 1152 .hdisplay = 800, 1153 .hsync_start = 800 + 40, 1154 .hsync_end = 800 + 40 + 48, 1155 .htotal = 800 + 40 + 48 + 40, 1156 .vdisplay = 480, 1157 .vsync_start = 480 + 13, 1158 .vsync_end = 480 + 13 + 3, 1159 .vtotal = 480 + 13 + 3 + 29, 1160 }; 1161 1162 static const struct panel_desc bananapi_s070wv20_ct16 = { 1163 .modes = &bananapi_s070wv20_ct16_mode, 1164 .num_modes = 1, 1165 .bpc = 6, 1166 .size = { 1167 .width = 154, 1168 .height = 86, 1169 }, 1170 }; 1171 1172 static const struct drm_display_mode boe_hv070wsa_mode = { 1173 .clock = 42105, 1174 .hdisplay = 1024, 1175 .hsync_start = 1024 + 30, 1176 .hsync_end = 1024 + 30 + 30, 1177 .htotal = 1024 + 30 + 30 + 30, 1178 .vdisplay = 600, 1179 .vsync_start = 600 + 10, 1180 .vsync_end = 600 + 10 + 10, 1181 .vtotal = 600 + 10 + 10 + 10, 1182 }; 1183 1184 static const struct panel_desc boe_hv070wsa = { 1185 .modes = &boe_hv070wsa_mode, 1186 .num_modes = 1, 1187 .bpc = 8, 1188 .size = { 1189 .width = 154, 1190 .height = 90, 1191 }, 1192 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1193 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1194 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1195 }; 1196 1197 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1198 .clock = 9000, 1199 .hdisplay = 480, 1200 .hsync_start = 480 + 5, 1201 .hsync_end = 480 + 5 + 5, 1202 .htotal = 480 + 5 + 5 + 40, 1203 .vdisplay = 272, 1204 .vsync_start = 272 + 8, 1205 .vsync_end = 272 + 8 + 8, 1206 .vtotal = 272 + 8 + 8 + 8, 1207 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1208 }; 1209 1210 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1211 .modes = &cdtech_s043wq26h_ct7_mode, 1212 .num_modes = 1, 1213 .bpc = 8, 1214 .size = { 1215 .width = 95, 1216 .height = 54, 1217 }, 1218 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1219 }; 1220 1221 /* S070PWS19HP-FC21 2017/04/22 */ 1222 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1223 .clock = 51200, 1224 .hdisplay = 1024, 1225 .hsync_start = 1024 + 160, 1226 .hsync_end = 1024 + 160 + 20, 1227 .htotal = 1024 + 160 + 20 + 140, 1228 .vdisplay = 600, 1229 .vsync_start = 600 + 12, 1230 .vsync_end = 600 + 12 + 3, 1231 .vtotal = 600 + 12 + 3 + 20, 1232 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1233 }; 1234 1235 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1236 .modes = &cdtech_s070pws19hp_fc21_mode, 1237 .num_modes = 1, 1238 .bpc = 6, 1239 .size = { 1240 .width = 154, 1241 .height = 86, 1242 }, 1243 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1244 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1245 .connector_type = DRM_MODE_CONNECTOR_DPI, 1246 }; 1247 1248 /* S070SWV29HG-DC44 2017/09/21 */ 1249 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1250 .clock = 33300, 1251 .hdisplay = 800, 1252 .hsync_start = 800 + 210, 1253 .hsync_end = 800 + 210 + 2, 1254 .htotal = 800 + 210 + 2 + 44, 1255 .vdisplay = 480, 1256 .vsync_start = 480 + 22, 1257 .vsync_end = 480 + 22 + 2, 1258 .vtotal = 480 + 22 + 2 + 21, 1259 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1260 }; 1261 1262 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1263 .modes = &cdtech_s070swv29hg_dc44_mode, 1264 .num_modes = 1, 1265 .bpc = 6, 1266 .size = { 1267 .width = 154, 1268 .height = 86, 1269 }, 1270 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1271 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1272 .connector_type = DRM_MODE_CONNECTOR_DPI, 1273 }; 1274 1275 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1276 .clock = 35000, 1277 .hdisplay = 800, 1278 .hsync_start = 800 + 40, 1279 .hsync_end = 800 + 40 + 40, 1280 .htotal = 800 + 40 + 40 + 48, 1281 .vdisplay = 480, 1282 .vsync_start = 480 + 29, 1283 .vsync_end = 480 + 29 + 13, 1284 .vtotal = 480 + 29 + 13 + 3, 1285 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1286 }; 1287 1288 static const struct panel_desc cdtech_s070wv95_ct16 = { 1289 .modes = &cdtech_s070wv95_ct16_mode, 1290 .num_modes = 1, 1291 .bpc = 8, 1292 .size = { 1293 .width = 154, 1294 .height = 85, 1295 }, 1296 }; 1297 1298 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1299 .pixelclock = { 68900000, 71100000, 73400000 }, 1300 .hactive = { 1280, 1280, 1280 }, 1301 .hfront_porch = { 65, 80, 95 }, 1302 .hback_porch = { 64, 79, 94 }, 1303 .hsync_len = { 1, 1, 1 }, 1304 .vactive = { 800, 800, 800 }, 1305 .vfront_porch = { 7, 11, 14 }, 1306 .vback_porch = { 7, 11, 14 }, 1307 .vsync_len = { 1, 1, 1 }, 1308 .flags = DISPLAY_FLAGS_DE_HIGH, 1309 }; 1310 1311 static const struct panel_desc chefree_ch101olhlwh_002 = { 1312 .timings = &chefree_ch101olhlwh_002_timing, 1313 .num_timings = 1, 1314 .bpc = 8, 1315 .size = { 1316 .width = 217, 1317 .height = 135, 1318 }, 1319 .delay = { 1320 .enable = 200, 1321 .disable = 200, 1322 }, 1323 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1324 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1325 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1326 }; 1327 1328 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1329 .clock = 66770, 1330 .hdisplay = 800, 1331 .hsync_start = 800 + 49, 1332 .hsync_end = 800 + 49 + 33, 1333 .htotal = 800 + 49 + 33 + 17, 1334 .vdisplay = 1280, 1335 .vsync_start = 1280 + 1, 1336 .vsync_end = 1280 + 1 + 7, 1337 .vtotal = 1280 + 1 + 7 + 15, 1338 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1339 }; 1340 1341 static const struct panel_desc chunghwa_claa070wp03xg = { 1342 .modes = &chunghwa_claa070wp03xg_mode, 1343 .num_modes = 1, 1344 .bpc = 6, 1345 .size = { 1346 .width = 94, 1347 .height = 150, 1348 }, 1349 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1350 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1351 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1352 }; 1353 1354 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1355 .clock = 72070, 1356 .hdisplay = 1366, 1357 .hsync_start = 1366 + 58, 1358 .hsync_end = 1366 + 58 + 58, 1359 .htotal = 1366 + 58 + 58 + 58, 1360 .vdisplay = 768, 1361 .vsync_start = 768 + 4, 1362 .vsync_end = 768 + 4 + 4, 1363 .vtotal = 768 + 4 + 4 + 4, 1364 }; 1365 1366 static const struct panel_desc chunghwa_claa101wa01a = { 1367 .modes = &chunghwa_claa101wa01a_mode, 1368 .num_modes = 1, 1369 .bpc = 6, 1370 .size = { 1371 .width = 220, 1372 .height = 120, 1373 }, 1374 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1375 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1376 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1377 }; 1378 1379 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1380 .clock = 69300, 1381 .hdisplay = 1366, 1382 .hsync_start = 1366 + 48, 1383 .hsync_end = 1366 + 48 + 32, 1384 .htotal = 1366 + 48 + 32 + 20, 1385 .vdisplay = 768, 1386 .vsync_start = 768 + 16, 1387 .vsync_end = 768 + 16 + 8, 1388 .vtotal = 768 + 16 + 8 + 16, 1389 }; 1390 1391 static const struct panel_desc chunghwa_claa101wb01 = { 1392 .modes = &chunghwa_claa101wb01_mode, 1393 .num_modes = 1, 1394 .bpc = 6, 1395 .size = { 1396 .width = 223, 1397 .height = 125, 1398 }, 1399 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1400 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1401 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1402 }; 1403 1404 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1405 .clock = 33260, 1406 .hdisplay = 800, 1407 .hsync_start = 800 + 40, 1408 .hsync_end = 800 + 40 + 128, 1409 .htotal = 800 + 40 + 128 + 88, 1410 .vdisplay = 480, 1411 .vsync_start = 480 + 10, 1412 .vsync_end = 480 + 10 + 2, 1413 .vtotal = 480 + 10 + 2 + 33, 1414 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1415 }; 1416 1417 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1418 .modes = &dataimage_scf0700c48ggu18_mode, 1419 .num_modes = 1, 1420 .bpc = 8, 1421 .size = { 1422 .width = 152, 1423 .height = 91, 1424 }, 1425 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1426 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1427 }; 1428 1429 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1430 .pixelclock = { 45000000, 51200000, 57000000 }, 1431 .hactive = { 1024, 1024, 1024 }, 1432 .hfront_porch = { 100, 106, 113 }, 1433 .hback_porch = { 100, 106, 113 }, 1434 .hsync_len = { 100, 108, 114 }, 1435 .vactive = { 600, 600, 600 }, 1436 .vfront_porch = { 8, 11, 15 }, 1437 .vback_porch = { 8, 11, 15 }, 1438 .vsync_len = { 9, 13, 15 }, 1439 .flags = DISPLAY_FLAGS_DE_HIGH, 1440 }; 1441 1442 static const struct panel_desc dlc_dlc0700yzg_1 = { 1443 .timings = &dlc_dlc0700yzg_1_timing, 1444 .num_timings = 1, 1445 .bpc = 6, 1446 .size = { 1447 .width = 154, 1448 .height = 86, 1449 }, 1450 .delay = { 1451 .prepare = 30, 1452 .enable = 200, 1453 .disable = 200, 1454 }, 1455 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1456 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1457 }; 1458 1459 static const struct display_timing dlc_dlc1010gig_timing = { 1460 .pixelclock = { 68900000, 71100000, 73400000 }, 1461 .hactive = { 1280, 1280, 1280 }, 1462 .hfront_porch = { 43, 53, 63 }, 1463 .hback_porch = { 43, 53, 63 }, 1464 .hsync_len = { 44, 54, 64 }, 1465 .vactive = { 800, 800, 800 }, 1466 .vfront_porch = { 5, 8, 11 }, 1467 .vback_porch = { 5, 8, 11 }, 1468 .vsync_len = { 5, 7, 11 }, 1469 .flags = DISPLAY_FLAGS_DE_HIGH, 1470 }; 1471 1472 static const struct panel_desc dlc_dlc1010gig = { 1473 .timings = &dlc_dlc1010gig_timing, 1474 .num_timings = 1, 1475 .bpc = 8, 1476 .size = { 1477 .width = 216, 1478 .height = 135, 1479 }, 1480 .delay = { 1481 .prepare = 60, 1482 .enable = 150, 1483 .disable = 100, 1484 .unprepare = 60, 1485 }, 1486 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1487 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1488 }; 1489 1490 static const struct drm_display_mode edt_et035012dm6_mode = { 1491 .clock = 6500, 1492 .hdisplay = 320, 1493 .hsync_start = 320 + 20, 1494 .hsync_end = 320 + 20 + 30, 1495 .htotal = 320 + 20 + 68, 1496 .vdisplay = 240, 1497 .vsync_start = 240 + 4, 1498 .vsync_end = 240 + 4 + 4, 1499 .vtotal = 240 + 4 + 4 + 14, 1500 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1501 }; 1502 1503 static const struct panel_desc edt_et035012dm6 = { 1504 .modes = &edt_et035012dm6_mode, 1505 .num_modes = 1, 1506 .bpc = 8, 1507 .size = { 1508 .width = 70, 1509 .height = 52, 1510 }, 1511 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1512 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1513 }; 1514 1515 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1516 .clock = 6520, 1517 .hdisplay = 320, 1518 .hsync_start = 320 + 20, 1519 .hsync_end = 320 + 20 + 68, 1520 .htotal = 320 + 20 + 68, 1521 .vdisplay = 240, 1522 .vsync_start = 240 + 4, 1523 .vsync_end = 240 + 4 + 18, 1524 .vtotal = 240 + 4 + 18, 1525 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1526 }; 1527 1528 static const struct panel_desc edt_etm0350g0dh6 = { 1529 .modes = &edt_etm0350g0dh6_mode, 1530 .num_modes = 1, 1531 .bpc = 6, 1532 .size = { 1533 .width = 70, 1534 .height = 53, 1535 }, 1536 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1537 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1538 .connector_type = DRM_MODE_CONNECTOR_DPI, 1539 }; 1540 1541 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1542 .clock = 10870, 1543 .hdisplay = 480, 1544 .hsync_start = 480 + 8, 1545 .hsync_end = 480 + 8 + 4, 1546 .htotal = 480 + 8 + 4 + 41, 1547 1548 /* 1549 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1550 * fb_align 1551 */ 1552 1553 .vdisplay = 288, 1554 .vsync_start = 288 + 2, 1555 .vsync_end = 288 + 2 + 4, 1556 .vtotal = 288 + 2 + 4 + 10, 1557 }; 1558 1559 static const struct panel_desc edt_etm043080dh6gp = { 1560 .modes = &edt_etm043080dh6gp_mode, 1561 .num_modes = 1, 1562 .bpc = 8, 1563 .size = { 1564 .width = 100, 1565 .height = 65, 1566 }, 1567 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1568 .connector_type = DRM_MODE_CONNECTOR_DPI, 1569 }; 1570 1571 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1572 .clock = 9000, 1573 .hdisplay = 480, 1574 .hsync_start = 480 + 2, 1575 .hsync_end = 480 + 2 + 41, 1576 .htotal = 480 + 2 + 41 + 2, 1577 .vdisplay = 272, 1578 .vsync_start = 272 + 2, 1579 .vsync_end = 272 + 2 + 10, 1580 .vtotal = 272 + 2 + 10 + 2, 1581 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1582 }; 1583 1584 static const struct panel_desc edt_etm0430g0dh6 = { 1585 .modes = &edt_etm0430g0dh6_mode, 1586 .num_modes = 1, 1587 .bpc = 6, 1588 .size = { 1589 .width = 95, 1590 .height = 54, 1591 }, 1592 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1593 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1594 .connector_type = DRM_MODE_CONNECTOR_DPI, 1595 }; 1596 1597 static const struct drm_display_mode edt_et057090dhu_mode = { 1598 .clock = 25175, 1599 .hdisplay = 640, 1600 .hsync_start = 640 + 16, 1601 .hsync_end = 640 + 16 + 30, 1602 .htotal = 640 + 16 + 30 + 114, 1603 .vdisplay = 480, 1604 .vsync_start = 480 + 10, 1605 .vsync_end = 480 + 10 + 3, 1606 .vtotal = 480 + 10 + 3 + 32, 1607 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1608 }; 1609 1610 static const struct panel_desc edt_et057090dhu = { 1611 .modes = &edt_et057090dhu_mode, 1612 .num_modes = 1, 1613 .bpc = 6, 1614 .size = { 1615 .width = 115, 1616 .height = 86, 1617 }, 1618 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1619 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1620 .connector_type = DRM_MODE_CONNECTOR_DPI, 1621 }; 1622 1623 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1624 .clock = 33260, 1625 .hdisplay = 800, 1626 .hsync_start = 800 + 40, 1627 .hsync_end = 800 + 40 + 128, 1628 .htotal = 800 + 40 + 128 + 88, 1629 .vdisplay = 480, 1630 .vsync_start = 480 + 10, 1631 .vsync_end = 480 + 10 + 2, 1632 .vtotal = 480 + 10 + 2 + 33, 1633 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1634 }; 1635 1636 static const struct panel_desc edt_etm0700g0dh6 = { 1637 .modes = &edt_etm0700g0dh6_mode, 1638 .num_modes = 1, 1639 .bpc = 6, 1640 .size = { 1641 .width = 152, 1642 .height = 91, 1643 }, 1644 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1645 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1646 .connector_type = DRM_MODE_CONNECTOR_DPI, 1647 }; 1648 1649 static const struct panel_desc edt_etm0700g0bdh6 = { 1650 .modes = &edt_etm0700g0dh6_mode, 1651 .num_modes = 1, 1652 .bpc = 6, 1653 .size = { 1654 .width = 152, 1655 .height = 91, 1656 }, 1657 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1658 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1659 .connector_type = DRM_MODE_CONNECTOR_DPI, 1660 }; 1661 1662 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1663 .clock = 25175, 1664 .hdisplay = 640, 1665 .hsync_start = 640, 1666 .hsync_end = 640 + 16, 1667 .htotal = 640 + 16 + 30 + 114, 1668 .vdisplay = 480, 1669 .vsync_start = 480 + 10, 1670 .vsync_end = 480 + 10 + 3, 1671 .vtotal = 480 + 10 + 3 + 35, 1672 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1673 }; 1674 1675 static const struct panel_desc edt_etmv570g2dhu = { 1676 .modes = &edt_etmv570g2dhu_mode, 1677 .num_modes = 1, 1678 .bpc = 6, 1679 .size = { 1680 .width = 115, 1681 .height = 86, 1682 }, 1683 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1684 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1685 .connector_type = DRM_MODE_CONNECTOR_DPI, 1686 }; 1687 1688 static const struct display_timing eink_vb3300_kca_timing = { 1689 .pixelclock = { 40000000, 40000000, 40000000 }, 1690 .hactive = { 334, 334, 334 }, 1691 .hfront_porch = { 1, 1, 1 }, 1692 .hback_porch = { 1, 1, 1 }, 1693 .hsync_len = { 1, 1, 1 }, 1694 .vactive = { 1405, 1405, 1405 }, 1695 .vfront_porch = { 1, 1, 1 }, 1696 .vback_porch = { 1, 1, 1 }, 1697 .vsync_len = { 1, 1, 1 }, 1698 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1699 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1700 }; 1701 1702 static const struct panel_desc eink_vb3300_kca = { 1703 .timings = &eink_vb3300_kca_timing, 1704 .num_timings = 1, 1705 .bpc = 6, 1706 .size = { 1707 .width = 157, 1708 .height = 209, 1709 }, 1710 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1711 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1712 .connector_type = DRM_MODE_CONNECTOR_DPI, 1713 }; 1714 1715 static const struct display_timing evervision_vgg804821_timing = { 1716 .pixelclock = { 27600000, 33300000, 50000000 }, 1717 .hactive = { 800, 800, 800 }, 1718 .hfront_porch = { 40, 66, 70 }, 1719 .hback_porch = { 40, 67, 70 }, 1720 .hsync_len = { 40, 67, 70 }, 1721 .vactive = { 480, 480, 480 }, 1722 .vfront_porch = { 6, 10, 10 }, 1723 .vback_porch = { 7, 11, 11 }, 1724 .vsync_len = { 7, 11, 11 }, 1725 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1726 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1727 DISPLAY_FLAGS_SYNC_NEGEDGE, 1728 }; 1729 1730 static const struct panel_desc evervision_vgg804821 = { 1731 .timings = &evervision_vgg804821_timing, 1732 .num_timings = 1, 1733 .bpc = 8, 1734 .size = { 1735 .width = 108, 1736 .height = 64, 1737 }, 1738 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1739 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1740 }; 1741 1742 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1743 .clock = 32260, 1744 .hdisplay = 800, 1745 .hsync_start = 800 + 168, 1746 .hsync_end = 800 + 168 + 64, 1747 .htotal = 800 + 168 + 64 + 88, 1748 .vdisplay = 480, 1749 .vsync_start = 480 + 37, 1750 .vsync_end = 480 + 37 + 2, 1751 .vtotal = 480 + 37 + 2 + 8, 1752 }; 1753 1754 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1755 .modes = &foxlink_fl500wvr00_a0t_mode, 1756 .num_modes = 1, 1757 .bpc = 8, 1758 .size = { 1759 .width = 108, 1760 .height = 65, 1761 }, 1762 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1763 }; 1764 1765 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1766 { /* 60 Hz */ 1767 .clock = 6000, 1768 .hdisplay = 320, 1769 .hsync_start = 320 + 44, 1770 .hsync_end = 320 + 44 + 16, 1771 .htotal = 320 + 44 + 16 + 20, 1772 .vdisplay = 240, 1773 .vsync_start = 240 + 2, 1774 .vsync_end = 240 + 2 + 6, 1775 .vtotal = 240 + 2 + 6 + 2, 1776 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1777 }, 1778 { /* 50 Hz */ 1779 .clock = 5400, 1780 .hdisplay = 320, 1781 .hsync_start = 320 + 56, 1782 .hsync_end = 320 + 56 + 16, 1783 .htotal = 320 + 56 + 16 + 40, 1784 .vdisplay = 240, 1785 .vsync_start = 240 + 2, 1786 .vsync_end = 240 + 2 + 6, 1787 .vtotal = 240 + 2 + 6 + 2, 1788 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1789 }, 1790 }; 1791 1792 static const struct panel_desc frida_frd350h54004 = { 1793 .modes = frida_frd350h54004_modes, 1794 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1795 .bpc = 8, 1796 .size = { 1797 .width = 77, 1798 .height = 64, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1802 .connector_type = DRM_MODE_CONNECTOR_DPI, 1803 }; 1804 1805 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1806 .clock = 67185, 1807 .hdisplay = 800, 1808 .hsync_start = 800 + 20, 1809 .hsync_end = 800 + 20 + 24, 1810 .htotal = 800 + 20 + 24 + 20, 1811 .vdisplay = 1280, 1812 .vsync_start = 1280 + 4, 1813 .vsync_end = 1280 + 4 + 8, 1814 .vtotal = 1280 + 4 + 8 + 4, 1815 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1816 }; 1817 1818 static const struct panel_desc friendlyarm_hd702e = { 1819 .modes = &friendlyarm_hd702e_mode, 1820 .num_modes = 1, 1821 .size = { 1822 .width = 94, 1823 .height = 151, 1824 }, 1825 }; 1826 1827 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1828 .clock = 9000, 1829 .hdisplay = 480, 1830 .hsync_start = 480 + 5, 1831 .hsync_end = 480 + 5 + 1, 1832 .htotal = 480 + 5 + 1 + 40, 1833 .vdisplay = 272, 1834 .vsync_start = 272 + 8, 1835 .vsync_end = 272 + 8 + 1, 1836 .vtotal = 272 + 8 + 1 + 8, 1837 }; 1838 1839 static const struct panel_desc giantplus_gpg482739qs5 = { 1840 .modes = &giantplus_gpg482739qs5_mode, 1841 .num_modes = 1, 1842 .bpc = 8, 1843 .size = { 1844 .width = 95, 1845 .height = 54, 1846 }, 1847 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1848 }; 1849 1850 static const struct display_timing giantplus_gpm940b0_timing = { 1851 .pixelclock = { 13500000, 27000000, 27500000 }, 1852 .hactive = { 320, 320, 320 }, 1853 .hfront_porch = { 14, 686, 718 }, 1854 .hback_porch = { 50, 70, 255 }, 1855 .hsync_len = { 1, 1, 1 }, 1856 .vactive = { 240, 240, 240 }, 1857 .vfront_porch = { 1, 1, 179 }, 1858 .vback_porch = { 1, 21, 31 }, 1859 .vsync_len = { 1, 1, 6 }, 1860 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1861 }; 1862 1863 static const struct panel_desc giantplus_gpm940b0 = { 1864 .timings = &giantplus_gpm940b0_timing, 1865 .num_timings = 1, 1866 .bpc = 8, 1867 .size = { 1868 .width = 60, 1869 .height = 45, 1870 }, 1871 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1872 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1873 }; 1874 1875 static const struct display_timing hannstar_hsd070pww1_timing = { 1876 .pixelclock = { 64300000, 71100000, 82000000 }, 1877 .hactive = { 1280, 1280, 1280 }, 1878 .hfront_porch = { 1, 1, 10 }, 1879 .hback_porch = { 1, 1, 10 }, 1880 /* 1881 * According to the data sheet, the minimum horizontal blanking interval 1882 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1883 * minimum working horizontal blanking interval to be 60 clocks. 1884 */ 1885 .hsync_len = { 58, 158, 661 }, 1886 .vactive = { 800, 800, 800 }, 1887 .vfront_porch = { 1, 1, 10 }, 1888 .vback_porch = { 1, 1, 10 }, 1889 .vsync_len = { 1, 21, 203 }, 1890 .flags = DISPLAY_FLAGS_DE_HIGH, 1891 }; 1892 1893 static const struct panel_desc hannstar_hsd070pww1 = { 1894 .timings = &hannstar_hsd070pww1_timing, 1895 .num_timings = 1, 1896 .bpc = 6, 1897 .size = { 1898 .width = 151, 1899 .height = 94, 1900 }, 1901 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1902 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1903 }; 1904 1905 static const struct display_timing hannstar_hsd100pxn1_timing = { 1906 .pixelclock = { 55000000, 65000000, 75000000 }, 1907 .hactive = { 1024, 1024, 1024 }, 1908 .hfront_porch = { 40, 40, 40 }, 1909 .hback_porch = { 220, 220, 220 }, 1910 .hsync_len = { 20, 60, 100 }, 1911 .vactive = { 768, 768, 768 }, 1912 .vfront_porch = { 7, 7, 7 }, 1913 .vback_porch = { 21, 21, 21 }, 1914 .vsync_len = { 10, 10, 10 }, 1915 .flags = DISPLAY_FLAGS_DE_HIGH, 1916 }; 1917 1918 static const struct panel_desc hannstar_hsd100pxn1 = { 1919 .timings = &hannstar_hsd100pxn1_timing, 1920 .num_timings = 1, 1921 .bpc = 6, 1922 .size = { 1923 .width = 203, 1924 .height = 152, 1925 }, 1926 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1927 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1928 }; 1929 1930 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1931 .clock = 33333, 1932 .hdisplay = 800, 1933 .hsync_start = 800 + 85, 1934 .hsync_end = 800 + 85 + 86, 1935 .htotal = 800 + 85 + 86 + 85, 1936 .vdisplay = 480, 1937 .vsync_start = 480 + 16, 1938 .vsync_end = 480 + 16 + 13, 1939 .vtotal = 480 + 16 + 13 + 16, 1940 }; 1941 1942 static const struct panel_desc hitachi_tx23d38vm0caa = { 1943 .modes = &hitachi_tx23d38vm0caa_mode, 1944 .num_modes = 1, 1945 .bpc = 6, 1946 .size = { 1947 .width = 195, 1948 .height = 117, 1949 }, 1950 .delay = { 1951 .enable = 160, 1952 .disable = 160, 1953 }, 1954 }; 1955 1956 static const struct drm_display_mode innolux_at043tn24_mode = { 1957 .clock = 9000, 1958 .hdisplay = 480, 1959 .hsync_start = 480 + 2, 1960 .hsync_end = 480 + 2 + 41, 1961 .htotal = 480 + 2 + 41 + 2, 1962 .vdisplay = 272, 1963 .vsync_start = 272 + 2, 1964 .vsync_end = 272 + 2 + 10, 1965 .vtotal = 272 + 2 + 10 + 2, 1966 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1967 }; 1968 1969 static const struct panel_desc innolux_at043tn24 = { 1970 .modes = &innolux_at043tn24_mode, 1971 .num_modes = 1, 1972 .bpc = 8, 1973 .size = { 1974 .width = 95, 1975 .height = 54, 1976 }, 1977 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1978 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1979 }; 1980 1981 static const struct drm_display_mode innolux_at070tn92_mode = { 1982 .clock = 33333, 1983 .hdisplay = 800, 1984 .hsync_start = 800 + 210, 1985 .hsync_end = 800 + 210 + 20, 1986 .htotal = 800 + 210 + 20 + 46, 1987 .vdisplay = 480, 1988 .vsync_start = 480 + 22, 1989 .vsync_end = 480 + 22 + 10, 1990 .vtotal = 480 + 22 + 23 + 10, 1991 }; 1992 1993 static const struct panel_desc innolux_at070tn92 = { 1994 .modes = &innolux_at070tn92_mode, 1995 .num_modes = 1, 1996 .size = { 1997 .width = 154, 1998 .height = 86, 1999 }, 2000 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2001 }; 2002 2003 static const struct display_timing innolux_g070y2_l01_timing = { 2004 .pixelclock = { 28000000, 29500000, 32000000 }, 2005 .hactive = { 800, 800, 800 }, 2006 .hfront_porch = { 61, 91, 141 }, 2007 .hback_porch = { 60, 90, 140 }, 2008 .hsync_len = { 12, 12, 12 }, 2009 .vactive = { 480, 480, 480 }, 2010 .vfront_porch = { 4, 9, 30 }, 2011 .vback_porch = { 4, 8, 28 }, 2012 .vsync_len = { 2, 2, 2 }, 2013 .flags = DISPLAY_FLAGS_DE_HIGH, 2014 }; 2015 2016 static const struct panel_desc innolux_g070y2_l01 = { 2017 .timings = &innolux_g070y2_l01_timing, 2018 .num_timings = 1, 2019 .bpc = 6, 2020 .size = { 2021 .width = 152, 2022 .height = 91, 2023 }, 2024 .delay = { 2025 .prepare = 10, 2026 .enable = 100, 2027 .disable = 100, 2028 .unprepare = 800, 2029 }, 2030 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2031 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2032 }; 2033 2034 static const struct display_timing innolux_g101ice_l01_timing = { 2035 .pixelclock = { 60400000, 71100000, 74700000 }, 2036 .hactive = { 1280, 1280, 1280 }, 2037 .hfront_porch = { 41, 80, 100 }, 2038 .hback_porch = { 40, 79, 99 }, 2039 .hsync_len = { 1, 1, 1 }, 2040 .vactive = { 800, 800, 800 }, 2041 .vfront_porch = { 5, 11, 14 }, 2042 .vback_porch = { 4, 11, 14 }, 2043 .vsync_len = { 1, 1, 1 }, 2044 .flags = DISPLAY_FLAGS_DE_HIGH, 2045 }; 2046 2047 static const struct panel_desc innolux_g101ice_l01 = { 2048 .timings = &innolux_g101ice_l01_timing, 2049 .num_timings = 1, 2050 .bpc = 8, 2051 .size = { 2052 .width = 217, 2053 .height = 135, 2054 }, 2055 .delay = { 2056 .enable = 200, 2057 .disable = 200, 2058 }, 2059 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2060 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2061 }; 2062 2063 static const struct display_timing innolux_g121i1_l01_timing = { 2064 .pixelclock = { 67450000, 71000000, 74550000 }, 2065 .hactive = { 1280, 1280, 1280 }, 2066 .hfront_porch = { 40, 80, 160 }, 2067 .hback_porch = { 39, 79, 159 }, 2068 .hsync_len = { 1, 1, 1 }, 2069 .vactive = { 800, 800, 800 }, 2070 .vfront_porch = { 5, 11, 100 }, 2071 .vback_porch = { 4, 11, 99 }, 2072 .vsync_len = { 1, 1, 1 }, 2073 }; 2074 2075 static const struct panel_desc innolux_g121i1_l01 = { 2076 .timings = &innolux_g121i1_l01_timing, 2077 .num_timings = 1, 2078 .bpc = 6, 2079 .size = { 2080 .width = 261, 2081 .height = 163, 2082 }, 2083 .delay = { 2084 .enable = 200, 2085 .disable = 20, 2086 }, 2087 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2088 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2089 }; 2090 2091 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2092 .clock = 65000, 2093 .hdisplay = 1024, 2094 .hsync_start = 1024 + 0, 2095 .hsync_end = 1024 + 1, 2096 .htotal = 1024 + 0 + 1 + 320, 2097 .vdisplay = 768, 2098 .vsync_start = 768 + 38, 2099 .vsync_end = 768 + 38 + 1, 2100 .vtotal = 768 + 38 + 1 + 0, 2101 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2102 }; 2103 2104 static const struct panel_desc innolux_g121x1_l03 = { 2105 .modes = &innolux_g121x1_l03_mode, 2106 .num_modes = 1, 2107 .bpc = 6, 2108 .size = { 2109 .width = 246, 2110 .height = 185, 2111 }, 2112 .delay = { 2113 .enable = 200, 2114 .unprepare = 200, 2115 .disable = 400, 2116 }, 2117 }; 2118 2119 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2120 .clock = 69300, 2121 .hdisplay = 1366, 2122 .hsync_start = 1366 + 16, 2123 .hsync_end = 1366 + 16 + 34, 2124 .htotal = 1366 + 16 + 34 + 50, 2125 .vdisplay = 768, 2126 .vsync_start = 768 + 2, 2127 .vsync_end = 768 + 2 + 6, 2128 .vtotal = 768 + 2 + 6 + 12, 2129 }; 2130 2131 static const struct panel_desc innolux_n156bge_l21 = { 2132 .modes = &innolux_n156bge_l21_mode, 2133 .num_modes = 1, 2134 .bpc = 6, 2135 .size = { 2136 .width = 344, 2137 .height = 193, 2138 }, 2139 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2140 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2141 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2142 }; 2143 2144 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2145 .clock = 51501, 2146 .hdisplay = 1024, 2147 .hsync_start = 1024 + 128, 2148 .hsync_end = 1024 + 128 + 64, 2149 .htotal = 1024 + 128 + 64 + 128, 2150 .vdisplay = 600, 2151 .vsync_start = 600 + 16, 2152 .vsync_end = 600 + 16 + 4, 2153 .vtotal = 600 + 16 + 4 + 16, 2154 }; 2155 2156 static const struct panel_desc innolux_zj070na_01p = { 2157 .modes = &innolux_zj070na_01p_mode, 2158 .num_modes = 1, 2159 .bpc = 6, 2160 .size = { 2161 .width = 154, 2162 .height = 90, 2163 }, 2164 }; 2165 2166 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2167 .pixelclock = { 5580000, 5850000, 6200000 }, 2168 .hactive = { 320, 320, 320 }, 2169 .hfront_porch = { 30, 30, 30 }, 2170 .hback_porch = { 30, 30, 30 }, 2171 .hsync_len = { 1, 5, 17 }, 2172 .vactive = { 240, 240, 240 }, 2173 .vfront_porch = { 6, 6, 6 }, 2174 .vback_porch = { 5, 5, 5 }, 2175 .vsync_len = { 1, 2, 11 }, 2176 .flags = DISPLAY_FLAGS_DE_HIGH, 2177 }; 2178 2179 static const struct panel_desc koe_tx14d24vm1bpa = { 2180 .timings = &koe_tx14d24vm1bpa_timing, 2181 .num_timings = 1, 2182 .bpc = 6, 2183 .size = { 2184 .width = 115, 2185 .height = 86, 2186 }, 2187 }; 2188 2189 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2190 .pixelclock = { 151820000, 156720000, 159780000 }, 2191 .hactive = { 1920, 1920, 1920 }, 2192 .hfront_porch = { 105, 130, 142 }, 2193 .hback_porch = { 45, 70, 82 }, 2194 .hsync_len = { 30, 30, 30 }, 2195 .vactive = { 1200, 1200, 1200}, 2196 .vfront_porch = { 3, 5, 10 }, 2197 .vback_porch = { 2, 5, 10 }, 2198 .vsync_len = { 5, 5, 5 }, 2199 }; 2200 2201 static const struct panel_desc koe_tx26d202vm0bwa = { 2202 .timings = &koe_tx26d202vm0bwa_timing, 2203 .num_timings = 1, 2204 .bpc = 8, 2205 .size = { 2206 .width = 217, 2207 .height = 136, 2208 }, 2209 .delay = { 2210 .prepare = 1000, 2211 .enable = 1000, 2212 .unprepare = 1000, 2213 .disable = 1000, 2214 }, 2215 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2216 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2217 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2218 }; 2219 2220 static const struct display_timing koe_tx31d200vm0baa_timing = { 2221 .pixelclock = { 39600000, 43200000, 48000000 }, 2222 .hactive = { 1280, 1280, 1280 }, 2223 .hfront_porch = { 16, 36, 56 }, 2224 .hback_porch = { 16, 36, 56 }, 2225 .hsync_len = { 8, 8, 8 }, 2226 .vactive = { 480, 480, 480 }, 2227 .vfront_porch = { 6, 21, 33 }, 2228 .vback_porch = { 6, 21, 33 }, 2229 .vsync_len = { 8, 8, 8 }, 2230 .flags = DISPLAY_FLAGS_DE_HIGH, 2231 }; 2232 2233 static const struct panel_desc koe_tx31d200vm0baa = { 2234 .timings = &koe_tx31d200vm0baa_timing, 2235 .num_timings = 1, 2236 .bpc = 6, 2237 .size = { 2238 .width = 292, 2239 .height = 109, 2240 }, 2241 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2242 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2243 }; 2244 2245 static const struct display_timing kyo_tcg121xglp_timing = { 2246 .pixelclock = { 52000000, 65000000, 71000000 }, 2247 .hactive = { 1024, 1024, 1024 }, 2248 .hfront_porch = { 2, 2, 2 }, 2249 .hback_porch = { 2, 2, 2 }, 2250 .hsync_len = { 86, 124, 244 }, 2251 .vactive = { 768, 768, 768 }, 2252 .vfront_porch = { 2, 2, 2 }, 2253 .vback_porch = { 2, 2, 2 }, 2254 .vsync_len = { 6, 34, 73 }, 2255 .flags = DISPLAY_FLAGS_DE_HIGH, 2256 }; 2257 2258 static const struct panel_desc kyo_tcg121xglp = { 2259 .timings = &kyo_tcg121xglp_timing, 2260 .num_timings = 1, 2261 .bpc = 8, 2262 .size = { 2263 .width = 246, 2264 .height = 184, 2265 }, 2266 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2267 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2268 }; 2269 2270 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2271 .clock = 7000, 2272 .hdisplay = 320, 2273 .hsync_start = 320 + 20, 2274 .hsync_end = 320 + 20 + 30, 2275 .htotal = 320 + 20 + 30 + 38, 2276 .vdisplay = 240, 2277 .vsync_start = 240 + 4, 2278 .vsync_end = 240 + 4 + 3, 2279 .vtotal = 240 + 4 + 3 + 15, 2280 }; 2281 2282 static const struct panel_desc lemaker_bl035_rgb_002 = { 2283 .modes = &lemaker_bl035_rgb_002_mode, 2284 .num_modes = 1, 2285 .size = { 2286 .width = 70, 2287 .height = 52, 2288 }, 2289 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2290 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2291 }; 2292 2293 static const struct drm_display_mode lg_lb070wv8_mode = { 2294 .clock = 33246, 2295 .hdisplay = 800, 2296 .hsync_start = 800 + 88, 2297 .hsync_end = 800 + 88 + 80, 2298 .htotal = 800 + 88 + 80 + 88, 2299 .vdisplay = 480, 2300 .vsync_start = 480 + 10, 2301 .vsync_end = 480 + 10 + 25, 2302 .vtotal = 480 + 10 + 25 + 10, 2303 }; 2304 2305 static const struct panel_desc lg_lb070wv8 = { 2306 .modes = &lg_lb070wv8_mode, 2307 .num_modes = 1, 2308 .bpc = 8, 2309 .size = { 2310 .width = 151, 2311 .height = 91, 2312 }, 2313 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2314 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2315 }; 2316 2317 static const struct display_timing logictechno_lt161010_2nh_timing = { 2318 .pixelclock = { 26400000, 33300000, 46800000 }, 2319 .hactive = { 800, 800, 800 }, 2320 .hfront_porch = { 16, 210, 354 }, 2321 .hback_porch = { 46, 46, 46 }, 2322 .hsync_len = { 1, 20, 40 }, 2323 .vactive = { 480, 480, 480 }, 2324 .vfront_porch = { 7, 22, 147 }, 2325 .vback_porch = { 23, 23, 23 }, 2326 .vsync_len = { 1, 10, 20 }, 2327 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2328 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2329 DISPLAY_FLAGS_SYNC_POSEDGE, 2330 }; 2331 2332 static const struct panel_desc logictechno_lt161010_2nh = { 2333 .timings = &logictechno_lt161010_2nh_timing, 2334 .num_timings = 1, 2335 .size = { 2336 .width = 154, 2337 .height = 86, 2338 }, 2339 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2340 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2341 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2342 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2343 .connector_type = DRM_MODE_CONNECTOR_DPI, 2344 }; 2345 2346 static const struct display_timing logictechno_lt170410_2whc_timing = { 2347 .pixelclock = { 68900000, 71100000, 73400000 }, 2348 .hactive = { 1280, 1280, 1280 }, 2349 .hfront_porch = { 23, 60, 71 }, 2350 .hback_porch = { 23, 60, 71 }, 2351 .hsync_len = { 15, 40, 47 }, 2352 .vactive = { 800, 800, 800 }, 2353 .vfront_porch = { 5, 7, 10 }, 2354 .vback_porch = { 5, 7, 10 }, 2355 .vsync_len = { 6, 9, 12 }, 2356 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2357 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2358 DISPLAY_FLAGS_SYNC_POSEDGE, 2359 }; 2360 2361 static const struct panel_desc logictechno_lt170410_2whc = { 2362 .timings = &logictechno_lt170410_2whc_timing, 2363 .num_timings = 1, 2364 .size = { 2365 .width = 217, 2366 .height = 136, 2367 }, 2368 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2369 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2370 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2371 }; 2372 2373 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2374 .clock = 33000, 2375 .hdisplay = 800, 2376 .hsync_start = 800 + 154, 2377 .hsync_end = 800 + 154 + 3, 2378 .htotal = 800 + 154 + 3 + 43, 2379 .vdisplay = 480, 2380 .vsync_start = 480 + 47, 2381 .vsync_end = 480 + 47 + 3, 2382 .vtotal = 480 + 47 + 3 + 20, 2383 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2384 }; 2385 2386 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2387 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2388 .num_modes = 1, 2389 .bpc = 8, 2390 .size = { 2391 .width = 154, 2392 .height = 86, 2393 }, 2394 .delay = { 2395 .prepare = 45, 2396 .enable = 100, 2397 .disable = 100, 2398 .unprepare = 45 2399 }, 2400 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2401 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2402 .connector_type = DRM_MODE_CONNECTOR_DPI, 2403 }; 2404 2405 static const struct drm_display_mode logicpd_type_28_mode = { 2406 .clock = 9107, 2407 .hdisplay = 480, 2408 .hsync_start = 480 + 3, 2409 .hsync_end = 480 + 3 + 42, 2410 .htotal = 480 + 3 + 42 + 2, 2411 2412 .vdisplay = 272, 2413 .vsync_start = 272 + 2, 2414 .vsync_end = 272 + 2 + 11, 2415 .vtotal = 272 + 2 + 11 + 3, 2416 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2417 }; 2418 2419 static const struct panel_desc logicpd_type_28 = { 2420 .modes = &logicpd_type_28_mode, 2421 .num_modes = 1, 2422 .bpc = 8, 2423 .size = { 2424 .width = 105, 2425 .height = 67, 2426 }, 2427 .delay = { 2428 .prepare = 200, 2429 .enable = 200, 2430 .unprepare = 200, 2431 .disable = 200, 2432 }, 2433 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2434 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2435 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2436 .connector_type = DRM_MODE_CONNECTOR_DPI, 2437 }; 2438 2439 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2440 .clock = 30400, 2441 .hdisplay = 800, 2442 .hsync_start = 800 + 0, 2443 .hsync_end = 800 + 1, 2444 .htotal = 800 + 0 + 1 + 160, 2445 .vdisplay = 480, 2446 .vsync_start = 480 + 0, 2447 .vsync_end = 480 + 48 + 1, 2448 .vtotal = 480 + 48 + 1 + 0, 2449 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2450 }; 2451 2452 static const struct panel_desc mitsubishi_aa070mc01 = { 2453 .modes = &mitsubishi_aa070mc01_mode, 2454 .num_modes = 1, 2455 .bpc = 8, 2456 .size = { 2457 .width = 152, 2458 .height = 91, 2459 }, 2460 2461 .delay = { 2462 .enable = 200, 2463 .unprepare = 200, 2464 .disable = 400, 2465 }, 2466 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2467 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2468 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2469 }; 2470 2471 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2472 .pixelclock = { 68900000, 70000000, 73400000 }, 2473 .hactive = { 1280, 1280, 1280 }, 2474 .hfront_porch = { 30, 60, 71 }, 2475 .hback_porch = { 30, 60, 71 }, 2476 .hsync_len = { 10, 10, 48 }, 2477 .vactive = { 800, 800, 800 }, 2478 .vfront_porch = { 5, 10, 10 }, 2479 .vback_porch = { 5, 10, 10 }, 2480 .vsync_len = { 5, 6, 13 }, 2481 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2482 DISPLAY_FLAGS_DE_HIGH, 2483 }; 2484 2485 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2486 .timings = &multi_inno_mi1010ait_1cp_timing, 2487 .num_timings = 1, 2488 .bpc = 8, 2489 .size = { 2490 .width = 217, 2491 .height = 136, 2492 }, 2493 .delay = { 2494 .enable = 50, 2495 .disable = 50, 2496 }, 2497 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2498 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2499 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2500 }; 2501 2502 static const struct display_timing nec_nl12880bc20_05_timing = { 2503 .pixelclock = { 67000000, 71000000, 75000000 }, 2504 .hactive = { 1280, 1280, 1280 }, 2505 .hfront_porch = { 2, 30, 30 }, 2506 .hback_porch = { 6, 100, 100 }, 2507 .hsync_len = { 2, 30, 30 }, 2508 .vactive = { 800, 800, 800 }, 2509 .vfront_porch = { 5, 5, 5 }, 2510 .vback_porch = { 11, 11, 11 }, 2511 .vsync_len = { 7, 7, 7 }, 2512 }; 2513 2514 static const struct panel_desc nec_nl12880bc20_05 = { 2515 .timings = &nec_nl12880bc20_05_timing, 2516 .num_timings = 1, 2517 .bpc = 8, 2518 .size = { 2519 .width = 261, 2520 .height = 163, 2521 }, 2522 .delay = { 2523 .enable = 50, 2524 .disable = 50, 2525 }, 2526 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2527 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2528 }; 2529 2530 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2531 .clock = 10870, 2532 .hdisplay = 480, 2533 .hsync_start = 480 + 2, 2534 .hsync_end = 480 + 2 + 41, 2535 .htotal = 480 + 2 + 41 + 2, 2536 .vdisplay = 272, 2537 .vsync_start = 272 + 2, 2538 .vsync_end = 272 + 2 + 4, 2539 .vtotal = 272 + 2 + 4 + 2, 2540 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2541 }; 2542 2543 static const struct panel_desc nec_nl4827hc19_05b = { 2544 .modes = &nec_nl4827hc19_05b_mode, 2545 .num_modes = 1, 2546 .bpc = 8, 2547 .size = { 2548 .width = 95, 2549 .height = 54, 2550 }, 2551 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2552 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2553 }; 2554 2555 static const struct drm_display_mode netron_dy_e231732_mode = { 2556 .clock = 66000, 2557 .hdisplay = 1024, 2558 .hsync_start = 1024 + 160, 2559 .hsync_end = 1024 + 160 + 70, 2560 .htotal = 1024 + 160 + 70 + 90, 2561 .vdisplay = 600, 2562 .vsync_start = 600 + 127, 2563 .vsync_end = 600 + 127 + 20, 2564 .vtotal = 600 + 127 + 20 + 3, 2565 }; 2566 2567 static const struct panel_desc netron_dy_e231732 = { 2568 .modes = &netron_dy_e231732_mode, 2569 .num_modes = 1, 2570 .size = { 2571 .width = 154, 2572 .height = 87, 2573 }, 2574 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2575 }; 2576 2577 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2578 .clock = 9000, 2579 .hdisplay = 480, 2580 .hsync_start = 480 + 2, 2581 .hsync_end = 480 + 2 + 41, 2582 .htotal = 480 + 2 + 41 + 2, 2583 .vdisplay = 272, 2584 .vsync_start = 272 + 2, 2585 .vsync_end = 272 + 2 + 10, 2586 .vtotal = 272 + 2 + 10 + 2, 2587 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2588 }; 2589 2590 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2591 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2592 .num_modes = 1, 2593 .bpc = 8, 2594 .size = { 2595 .width = 95, 2596 .height = 54, 2597 }, 2598 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2599 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2600 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2601 .connector_type = DRM_MODE_CONNECTOR_DPI, 2602 }; 2603 2604 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2605 .pixelclock = { 130000000, 148350000, 163000000 }, 2606 .hactive = { 1920, 1920, 1920 }, 2607 .hfront_porch = { 80, 100, 100 }, 2608 .hback_porch = { 100, 120, 120 }, 2609 .hsync_len = { 50, 60, 60 }, 2610 .vactive = { 1080, 1080, 1080 }, 2611 .vfront_porch = { 12, 30, 30 }, 2612 .vback_porch = { 4, 10, 10 }, 2613 .vsync_len = { 4, 5, 5 }, 2614 }; 2615 2616 static const struct panel_desc nlt_nl192108ac18_02d = { 2617 .timings = &nlt_nl192108ac18_02d_timing, 2618 .num_timings = 1, 2619 .bpc = 8, 2620 .size = { 2621 .width = 344, 2622 .height = 194, 2623 }, 2624 .delay = { 2625 .unprepare = 500, 2626 }, 2627 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2628 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2629 }; 2630 2631 static const struct drm_display_mode nvd_9128_mode = { 2632 .clock = 29500, 2633 .hdisplay = 800, 2634 .hsync_start = 800 + 130, 2635 .hsync_end = 800 + 130 + 98, 2636 .htotal = 800 + 0 + 130 + 98, 2637 .vdisplay = 480, 2638 .vsync_start = 480 + 10, 2639 .vsync_end = 480 + 10 + 50, 2640 .vtotal = 480 + 0 + 10 + 50, 2641 }; 2642 2643 static const struct panel_desc nvd_9128 = { 2644 .modes = &nvd_9128_mode, 2645 .num_modes = 1, 2646 .bpc = 8, 2647 .size = { 2648 .width = 156, 2649 .height = 88, 2650 }, 2651 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2652 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2653 }; 2654 2655 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2656 .pixelclock = { 30000000, 30000000, 40000000 }, 2657 .hactive = { 800, 800, 800 }, 2658 .hfront_porch = { 40, 40, 40 }, 2659 .hback_porch = { 40, 40, 40 }, 2660 .hsync_len = { 1, 48, 48 }, 2661 .vactive = { 480, 480, 480 }, 2662 .vfront_porch = { 13, 13, 13 }, 2663 .vback_porch = { 29, 29, 29 }, 2664 .vsync_len = { 3, 3, 3 }, 2665 .flags = DISPLAY_FLAGS_DE_HIGH, 2666 }; 2667 2668 static const struct panel_desc okaya_rs800480t_7x0gp = { 2669 .timings = &okaya_rs800480t_7x0gp_timing, 2670 .num_timings = 1, 2671 .bpc = 6, 2672 .size = { 2673 .width = 154, 2674 .height = 87, 2675 }, 2676 .delay = { 2677 .prepare = 41, 2678 .enable = 50, 2679 .unprepare = 41, 2680 .disable = 50, 2681 }, 2682 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2683 }; 2684 2685 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2686 .clock = 9000, 2687 .hdisplay = 480, 2688 .hsync_start = 480 + 5, 2689 .hsync_end = 480 + 5 + 30, 2690 .htotal = 480 + 5 + 30 + 10, 2691 .vdisplay = 272, 2692 .vsync_start = 272 + 8, 2693 .vsync_end = 272 + 8 + 5, 2694 .vtotal = 272 + 8 + 5 + 3, 2695 }; 2696 2697 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2698 .modes = &olimex_lcd_olinuxino_43ts_mode, 2699 .num_modes = 1, 2700 .size = { 2701 .width = 95, 2702 .height = 54, 2703 }, 2704 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2705 }; 2706 2707 /* 2708 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2709 * pixel clocks, but this is the timing that was being used in the Adafruit 2710 * installation instructions. 2711 */ 2712 static const struct drm_display_mode ontat_yx700wv03_mode = { 2713 .clock = 29500, 2714 .hdisplay = 800, 2715 .hsync_start = 824, 2716 .hsync_end = 896, 2717 .htotal = 992, 2718 .vdisplay = 480, 2719 .vsync_start = 483, 2720 .vsync_end = 493, 2721 .vtotal = 500, 2722 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2723 }; 2724 2725 /* 2726 * Specification at: 2727 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2728 */ 2729 static const struct panel_desc ontat_yx700wv03 = { 2730 .modes = &ontat_yx700wv03_mode, 2731 .num_modes = 1, 2732 .bpc = 8, 2733 .size = { 2734 .width = 154, 2735 .height = 83, 2736 }, 2737 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2738 }; 2739 2740 static const struct drm_display_mode ortustech_com37h3m_mode = { 2741 .clock = 22230, 2742 .hdisplay = 480, 2743 .hsync_start = 480 + 40, 2744 .hsync_end = 480 + 40 + 10, 2745 .htotal = 480 + 40 + 10 + 40, 2746 .vdisplay = 640, 2747 .vsync_start = 640 + 4, 2748 .vsync_end = 640 + 4 + 2, 2749 .vtotal = 640 + 4 + 2 + 4, 2750 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2751 }; 2752 2753 static const struct panel_desc ortustech_com37h3m = { 2754 .modes = &ortustech_com37h3m_mode, 2755 .num_modes = 1, 2756 .bpc = 8, 2757 .size = { 2758 .width = 56, /* 56.16mm */ 2759 .height = 75, /* 74.88mm */ 2760 }, 2761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2762 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2763 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2764 }; 2765 2766 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 2767 .clock = 25000, 2768 .hdisplay = 480, 2769 .hsync_start = 480 + 10, 2770 .hsync_end = 480 + 10 + 10, 2771 .htotal = 480 + 10 + 10 + 15, 2772 .vdisplay = 800, 2773 .vsync_start = 800 + 3, 2774 .vsync_end = 800 + 3 + 3, 2775 .vtotal = 800 + 3 + 3 + 3, 2776 }; 2777 2778 static const struct panel_desc ortustech_com43h4m85ulc = { 2779 .modes = &ortustech_com43h4m85ulc_mode, 2780 .num_modes = 1, 2781 .bpc = 6, 2782 .size = { 2783 .width = 56, 2784 .height = 93, 2785 }, 2786 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2787 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2788 .connector_type = DRM_MODE_CONNECTOR_DPI, 2789 }; 2790 2791 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 2792 .clock = 33000, 2793 .hdisplay = 800, 2794 .hsync_start = 800 + 210, 2795 .hsync_end = 800 + 210 + 30, 2796 .htotal = 800 + 210 + 30 + 16, 2797 .vdisplay = 480, 2798 .vsync_start = 480 + 22, 2799 .vsync_end = 480 + 22 + 13, 2800 .vtotal = 480 + 22 + 13 + 10, 2801 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2802 }; 2803 2804 static const struct panel_desc osddisplays_osd070t1718_19ts = { 2805 .modes = &osddisplays_osd070t1718_19ts_mode, 2806 .num_modes = 1, 2807 .bpc = 8, 2808 .size = { 2809 .width = 152, 2810 .height = 91, 2811 }, 2812 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2813 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2814 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2815 .connector_type = DRM_MODE_CONNECTOR_DPI, 2816 }; 2817 2818 static const struct drm_display_mode pda_91_00156_a0_mode = { 2819 .clock = 33300, 2820 .hdisplay = 800, 2821 .hsync_start = 800 + 1, 2822 .hsync_end = 800 + 1 + 64, 2823 .htotal = 800 + 1 + 64 + 64, 2824 .vdisplay = 480, 2825 .vsync_start = 480 + 1, 2826 .vsync_end = 480 + 1 + 23, 2827 .vtotal = 480 + 1 + 23 + 22, 2828 }; 2829 2830 static const struct panel_desc pda_91_00156_a0 = { 2831 .modes = &pda_91_00156_a0_mode, 2832 .num_modes = 1, 2833 .size = { 2834 .width = 152, 2835 .height = 91, 2836 }, 2837 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2838 }; 2839 2840 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 2841 .clock = 24750, 2842 .hdisplay = 800, 2843 .hsync_start = 800 + 54, 2844 .hsync_end = 800 + 54 + 2, 2845 .htotal = 800 + 54 + 2 + 44, 2846 .vdisplay = 480, 2847 .vsync_start = 480 + 49, 2848 .vsync_end = 480 + 49 + 2, 2849 .vtotal = 480 + 49 + 2 + 22, 2850 }; 2851 2852 static const struct panel_desc powertip_ph800480t013_idf02 = { 2853 .modes = &powertip_ph800480t013_idf02_mode, 2854 .num_modes = 1, 2855 .size = { 2856 .width = 152, 2857 .height = 91, 2858 }, 2859 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2860 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2861 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2862 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2863 .connector_type = DRM_MODE_CONNECTOR_DPI, 2864 }; 2865 2866 static const struct drm_display_mode qd43003c0_40_mode = { 2867 .clock = 9000, 2868 .hdisplay = 480, 2869 .hsync_start = 480 + 8, 2870 .hsync_end = 480 + 8 + 4, 2871 .htotal = 480 + 8 + 4 + 39, 2872 .vdisplay = 272, 2873 .vsync_start = 272 + 4, 2874 .vsync_end = 272 + 4 + 10, 2875 .vtotal = 272 + 4 + 10 + 2, 2876 }; 2877 2878 static const struct panel_desc qd43003c0_40 = { 2879 .modes = &qd43003c0_40_mode, 2880 .num_modes = 1, 2881 .bpc = 8, 2882 .size = { 2883 .width = 95, 2884 .height = 53, 2885 }, 2886 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2887 }; 2888 2889 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 2890 { /* 60 Hz */ 2891 .clock = 10800, 2892 .hdisplay = 480, 2893 .hsync_start = 480 + 77, 2894 .hsync_end = 480 + 77 + 41, 2895 .htotal = 480 + 77 + 41 + 2, 2896 .vdisplay = 272, 2897 .vsync_start = 272 + 16, 2898 .vsync_end = 272 + 16 + 10, 2899 .vtotal = 272 + 16 + 10 + 2, 2900 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2901 }, 2902 { /* 50 Hz */ 2903 .clock = 10800, 2904 .hdisplay = 480, 2905 .hsync_start = 480 + 17, 2906 .hsync_end = 480 + 17 + 41, 2907 .htotal = 480 + 17 + 41 + 2, 2908 .vdisplay = 272, 2909 .vsync_start = 272 + 116, 2910 .vsync_end = 272 + 116 + 10, 2911 .vtotal = 272 + 116 + 10 + 2, 2912 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2913 }, 2914 }; 2915 2916 static const struct panel_desc qishenglong_gopher2b_lcd = { 2917 .modes = qishenglong_gopher2b_lcd_modes, 2918 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 2919 .bpc = 8, 2920 .size = { 2921 .width = 95, 2922 .height = 54, 2923 }, 2924 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2925 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2926 .connector_type = DRM_MODE_CONNECTOR_DPI, 2927 }; 2928 2929 static const struct display_timing rocktech_rk070er9427_timing = { 2930 .pixelclock = { 26400000, 33300000, 46800000 }, 2931 .hactive = { 800, 800, 800 }, 2932 .hfront_porch = { 16, 210, 354 }, 2933 .hback_porch = { 46, 46, 46 }, 2934 .hsync_len = { 1, 1, 1 }, 2935 .vactive = { 480, 480, 480 }, 2936 .vfront_porch = { 7, 22, 147 }, 2937 .vback_porch = { 23, 23, 23 }, 2938 .vsync_len = { 1, 1, 1 }, 2939 .flags = DISPLAY_FLAGS_DE_HIGH, 2940 }; 2941 2942 static const struct panel_desc rocktech_rk070er9427 = { 2943 .timings = &rocktech_rk070er9427_timing, 2944 .num_timings = 1, 2945 .bpc = 6, 2946 .size = { 2947 .width = 154, 2948 .height = 86, 2949 }, 2950 .delay = { 2951 .prepare = 41, 2952 .enable = 50, 2953 .unprepare = 41, 2954 .disable = 50, 2955 }, 2956 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2957 }; 2958 2959 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 2960 .clock = 71100, 2961 .hdisplay = 1280, 2962 .hsync_start = 1280 + 48, 2963 .hsync_end = 1280 + 48 + 32, 2964 .htotal = 1280 + 48 + 32 + 80, 2965 .vdisplay = 800, 2966 .vsync_start = 800 + 2, 2967 .vsync_end = 800 + 2 + 5, 2968 .vtotal = 800 + 2 + 5 + 16, 2969 }; 2970 2971 static const struct panel_desc rocktech_rk101ii01d_ct = { 2972 .modes = &rocktech_rk101ii01d_ct_mode, 2973 .num_modes = 1, 2974 .size = { 2975 .width = 217, 2976 .height = 136, 2977 }, 2978 .delay = { 2979 .prepare = 50, 2980 .disable = 50, 2981 }, 2982 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2983 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2984 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2985 }; 2986 2987 static const struct drm_display_mode samsung_ltn101nt05_mode = { 2988 .clock = 54030, 2989 .hdisplay = 1024, 2990 .hsync_start = 1024 + 24, 2991 .hsync_end = 1024 + 24 + 136, 2992 .htotal = 1024 + 24 + 136 + 160, 2993 .vdisplay = 600, 2994 .vsync_start = 600 + 3, 2995 .vsync_end = 600 + 3 + 6, 2996 .vtotal = 600 + 3 + 6 + 61, 2997 }; 2998 2999 static const struct panel_desc samsung_ltn101nt05 = { 3000 .modes = &samsung_ltn101nt05_mode, 3001 .num_modes = 1, 3002 .bpc = 6, 3003 .size = { 3004 .width = 223, 3005 .height = 125, 3006 }, 3007 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3008 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3009 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3010 }; 3011 3012 static const struct display_timing satoz_sat050at40h12r2_timing = { 3013 .pixelclock = {33300000, 33300000, 50000000}, 3014 .hactive = {800, 800, 800}, 3015 .hfront_porch = {16, 210, 354}, 3016 .hback_porch = {46, 46, 46}, 3017 .hsync_len = {1, 1, 40}, 3018 .vactive = {480, 480, 480}, 3019 .vfront_porch = {7, 22, 147}, 3020 .vback_porch = {23, 23, 23}, 3021 .vsync_len = {1, 1, 20}, 3022 }; 3023 3024 static const struct panel_desc satoz_sat050at40h12r2 = { 3025 .timings = &satoz_sat050at40h12r2_timing, 3026 .num_timings = 1, 3027 .bpc = 8, 3028 .size = { 3029 .width = 108, 3030 .height = 65, 3031 }, 3032 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3033 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3034 }; 3035 3036 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3037 .clock = 33260, 3038 .hdisplay = 800, 3039 .hsync_start = 800 + 64, 3040 .hsync_end = 800 + 64 + 128, 3041 .htotal = 800 + 64 + 128 + 64, 3042 .vdisplay = 480, 3043 .vsync_start = 480 + 8, 3044 .vsync_end = 480 + 8 + 2, 3045 .vtotal = 480 + 8 + 2 + 35, 3046 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3047 }; 3048 3049 static const struct panel_desc sharp_lq070y3dg3b = { 3050 .modes = &sharp_lq070y3dg3b_mode, 3051 .num_modes = 1, 3052 .bpc = 8, 3053 .size = { 3054 .width = 152, /* 152.4mm */ 3055 .height = 91, /* 91.4mm */ 3056 }, 3057 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3058 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3059 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3060 }; 3061 3062 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3063 .clock = 5500, 3064 .hdisplay = 240, 3065 .hsync_start = 240 + 16, 3066 .hsync_end = 240 + 16 + 7, 3067 .htotal = 240 + 16 + 7 + 5, 3068 .vdisplay = 320, 3069 .vsync_start = 320 + 9, 3070 .vsync_end = 320 + 9 + 1, 3071 .vtotal = 320 + 9 + 1 + 7, 3072 }; 3073 3074 static const struct panel_desc sharp_lq035q7db03 = { 3075 .modes = &sharp_lq035q7db03_mode, 3076 .num_modes = 1, 3077 .bpc = 6, 3078 .size = { 3079 .width = 54, 3080 .height = 72, 3081 }, 3082 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3083 }; 3084 3085 static const struct display_timing sharp_lq101k1ly04_timing = { 3086 .pixelclock = { 60000000, 65000000, 80000000 }, 3087 .hactive = { 1280, 1280, 1280 }, 3088 .hfront_porch = { 20, 20, 20 }, 3089 .hback_porch = { 20, 20, 20 }, 3090 .hsync_len = { 10, 10, 10 }, 3091 .vactive = { 800, 800, 800 }, 3092 .vfront_porch = { 4, 4, 4 }, 3093 .vback_porch = { 4, 4, 4 }, 3094 .vsync_len = { 4, 4, 4 }, 3095 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3096 }; 3097 3098 static const struct panel_desc sharp_lq101k1ly04 = { 3099 .timings = &sharp_lq101k1ly04_timing, 3100 .num_timings = 1, 3101 .bpc = 8, 3102 .size = { 3103 .width = 217, 3104 .height = 136, 3105 }, 3106 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3107 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3108 }; 3109 3110 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3111 { /* 50 Hz */ 3112 .clock = 3000, 3113 .hdisplay = 240, 3114 .hsync_start = 240 + 58, 3115 .hsync_end = 240 + 58 + 1, 3116 .htotal = 240 + 58 + 1 + 1, 3117 .vdisplay = 160, 3118 .vsync_start = 160 + 24, 3119 .vsync_end = 160 + 24 + 10, 3120 .vtotal = 160 + 24 + 10 + 6, 3121 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3122 }, 3123 { /* 60 Hz */ 3124 .clock = 3000, 3125 .hdisplay = 240, 3126 .hsync_start = 240 + 8, 3127 .hsync_end = 240 + 8 + 1, 3128 .htotal = 240 + 8 + 1 + 1, 3129 .vdisplay = 160, 3130 .vsync_start = 160 + 24, 3131 .vsync_end = 160 + 24 + 10, 3132 .vtotal = 160 + 24 + 10 + 6, 3133 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3134 }, 3135 }; 3136 3137 static const struct panel_desc sharp_ls020b1dd01d = { 3138 .modes = sharp_ls020b1dd01d_modes, 3139 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3140 .bpc = 6, 3141 .size = { 3142 .width = 42, 3143 .height = 28, 3144 }, 3145 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3146 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3147 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3148 | DRM_BUS_FLAG_SHARP_SIGNALS, 3149 }; 3150 3151 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3152 .clock = 33300, 3153 .hdisplay = 800, 3154 .hsync_start = 800 + 1, 3155 .hsync_end = 800 + 1 + 64, 3156 .htotal = 800 + 1 + 64 + 64, 3157 .vdisplay = 480, 3158 .vsync_start = 480 + 1, 3159 .vsync_end = 480 + 1 + 23, 3160 .vtotal = 480 + 1 + 23 + 22, 3161 }; 3162 3163 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3164 .modes = &shelly_sca07010_bfn_lnn_mode, 3165 .num_modes = 1, 3166 .size = { 3167 .width = 152, 3168 .height = 91, 3169 }, 3170 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3171 }; 3172 3173 static const struct drm_display_mode starry_kr070pe2t_mode = { 3174 .clock = 33000, 3175 .hdisplay = 800, 3176 .hsync_start = 800 + 209, 3177 .hsync_end = 800 + 209 + 1, 3178 .htotal = 800 + 209 + 1 + 45, 3179 .vdisplay = 480, 3180 .vsync_start = 480 + 22, 3181 .vsync_end = 480 + 22 + 1, 3182 .vtotal = 480 + 22 + 1 + 22, 3183 }; 3184 3185 static const struct panel_desc starry_kr070pe2t = { 3186 .modes = &starry_kr070pe2t_mode, 3187 .num_modes = 1, 3188 .bpc = 8, 3189 .size = { 3190 .width = 152, 3191 .height = 86, 3192 }, 3193 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3194 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3195 .connector_type = DRM_MODE_CONNECTOR_DPI, 3196 }; 3197 3198 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3199 .clock = 30000, 3200 .hdisplay = 800, 3201 .hsync_start = 800 + 39, 3202 .hsync_end = 800 + 39 + 47, 3203 .htotal = 800 + 39 + 47 + 39, 3204 .vdisplay = 480, 3205 .vsync_start = 480 + 13, 3206 .vsync_end = 480 + 13 + 2, 3207 .vtotal = 480 + 13 + 2 + 29, 3208 }; 3209 3210 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3211 .modes = &tfc_s9700rtwv43tr_01b_mode, 3212 .num_modes = 1, 3213 .bpc = 8, 3214 .size = { 3215 .width = 155, 3216 .height = 90, 3217 }, 3218 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3219 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3220 }; 3221 3222 static const struct display_timing tianma_tm070jdhg30_timing = { 3223 .pixelclock = { 62600000, 68200000, 78100000 }, 3224 .hactive = { 1280, 1280, 1280 }, 3225 .hfront_porch = { 15, 64, 159 }, 3226 .hback_porch = { 5, 5, 5 }, 3227 .hsync_len = { 1, 1, 256 }, 3228 .vactive = { 800, 800, 800 }, 3229 .vfront_porch = { 3, 40, 99 }, 3230 .vback_porch = { 2, 2, 2 }, 3231 .vsync_len = { 1, 1, 128 }, 3232 .flags = DISPLAY_FLAGS_DE_HIGH, 3233 }; 3234 3235 static const struct panel_desc tianma_tm070jdhg30 = { 3236 .timings = &tianma_tm070jdhg30_timing, 3237 .num_timings = 1, 3238 .bpc = 8, 3239 .size = { 3240 .width = 151, 3241 .height = 95, 3242 }, 3243 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3244 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3245 }; 3246 3247 static const struct panel_desc tianma_tm070jvhg33 = { 3248 .timings = &tianma_tm070jdhg30_timing, 3249 .num_timings = 1, 3250 .bpc = 8, 3251 .size = { 3252 .width = 150, 3253 .height = 94, 3254 }, 3255 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3256 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3257 }; 3258 3259 static const struct display_timing tianma_tm070rvhg71_timing = { 3260 .pixelclock = { 27700000, 29200000, 39600000 }, 3261 .hactive = { 800, 800, 800 }, 3262 .hfront_porch = { 12, 40, 212 }, 3263 .hback_porch = { 88, 88, 88 }, 3264 .hsync_len = { 1, 1, 40 }, 3265 .vactive = { 480, 480, 480 }, 3266 .vfront_porch = { 1, 13, 88 }, 3267 .vback_porch = { 32, 32, 32 }, 3268 .vsync_len = { 1, 1, 3 }, 3269 .flags = DISPLAY_FLAGS_DE_HIGH, 3270 }; 3271 3272 static const struct panel_desc tianma_tm070rvhg71 = { 3273 .timings = &tianma_tm070rvhg71_timing, 3274 .num_timings = 1, 3275 .bpc = 8, 3276 .size = { 3277 .width = 154, 3278 .height = 86, 3279 }, 3280 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3281 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3282 }; 3283 3284 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3285 { 3286 .clock = 10000, 3287 .hdisplay = 320, 3288 .hsync_start = 320 + 50, 3289 .hsync_end = 320 + 50 + 6, 3290 .htotal = 320 + 50 + 6 + 38, 3291 .vdisplay = 240, 3292 .vsync_start = 240 + 3, 3293 .vsync_end = 240 + 3 + 1, 3294 .vtotal = 240 + 3 + 1 + 17, 3295 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3296 }, 3297 }; 3298 3299 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3300 .modes = ti_nspire_cx_lcd_mode, 3301 .num_modes = 1, 3302 .bpc = 8, 3303 .size = { 3304 .width = 65, 3305 .height = 49, 3306 }, 3307 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3308 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3309 }; 3310 3311 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3312 { 3313 .clock = 10000, 3314 .hdisplay = 320, 3315 .hsync_start = 320 + 6, 3316 .hsync_end = 320 + 6 + 6, 3317 .htotal = 320 + 6 + 6 + 6, 3318 .vdisplay = 240, 3319 .vsync_start = 240 + 0, 3320 .vsync_end = 240 + 0 + 1, 3321 .vtotal = 240 + 0 + 1 + 0, 3322 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3323 }, 3324 }; 3325 3326 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3327 .modes = ti_nspire_classic_lcd_mode, 3328 .num_modes = 1, 3329 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3330 .bpc = 8, 3331 .size = { 3332 .width = 71, 3333 .height = 53, 3334 }, 3335 /* This is the grayscale bus format */ 3336 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3337 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3338 }; 3339 3340 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3341 .clock = 79500, 3342 .hdisplay = 1280, 3343 .hsync_start = 1280 + 192, 3344 .hsync_end = 1280 + 192 + 128, 3345 .htotal = 1280 + 192 + 128 + 64, 3346 .vdisplay = 768, 3347 .vsync_start = 768 + 20, 3348 .vsync_end = 768 + 20 + 7, 3349 .vtotal = 768 + 20 + 7 + 3, 3350 }; 3351 3352 static const struct panel_desc toshiba_lt089ac29000 = { 3353 .modes = &toshiba_lt089ac29000_mode, 3354 .num_modes = 1, 3355 .size = { 3356 .width = 194, 3357 .height = 116, 3358 }, 3359 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3360 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3361 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3362 }; 3363 3364 static const struct drm_display_mode tpk_f07a_0102_mode = { 3365 .clock = 33260, 3366 .hdisplay = 800, 3367 .hsync_start = 800 + 40, 3368 .hsync_end = 800 + 40 + 128, 3369 .htotal = 800 + 40 + 128 + 88, 3370 .vdisplay = 480, 3371 .vsync_start = 480 + 10, 3372 .vsync_end = 480 + 10 + 2, 3373 .vtotal = 480 + 10 + 2 + 33, 3374 }; 3375 3376 static const struct panel_desc tpk_f07a_0102 = { 3377 .modes = &tpk_f07a_0102_mode, 3378 .num_modes = 1, 3379 .size = { 3380 .width = 152, 3381 .height = 91, 3382 }, 3383 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3384 }; 3385 3386 static const struct drm_display_mode tpk_f10a_0102_mode = { 3387 .clock = 45000, 3388 .hdisplay = 1024, 3389 .hsync_start = 1024 + 176, 3390 .hsync_end = 1024 + 176 + 5, 3391 .htotal = 1024 + 176 + 5 + 88, 3392 .vdisplay = 600, 3393 .vsync_start = 600 + 20, 3394 .vsync_end = 600 + 20 + 5, 3395 .vtotal = 600 + 20 + 5 + 25, 3396 }; 3397 3398 static const struct panel_desc tpk_f10a_0102 = { 3399 .modes = &tpk_f10a_0102_mode, 3400 .num_modes = 1, 3401 .size = { 3402 .width = 223, 3403 .height = 125, 3404 }, 3405 }; 3406 3407 static const struct display_timing urt_umsh_8596md_timing = { 3408 .pixelclock = { 33260000, 33260000, 33260000 }, 3409 .hactive = { 800, 800, 800 }, 3410 .hfront_porch = { 41, 41, 41 }, 3411 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3412 .hsync_len = { 71, 128, 128 }, 3413 .vactive = { 480, 480, 480 }, 3414 .vfront_porch = { 10, 10, 10 }, 3415 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3416 .vsync_len = { 2, 2, 2 }, 3417 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3418 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3419 }; 3420 3421 static const struct panel_desc urt_umsh_8596md_lvds = { 3422 .timings = &urt_umsh_8596md_timing, 3423 .num_timings = 1, 3424 .bpc = 6, 3425 .size = { 3426 .width = 152, 3427 .height = 91, 3428 }, 3429 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3430 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3431 }; 3432 3433 static const struct panel_desc urt_umsh_8596md_parallel = { 3434 .timings = &urt_umsh_8596md_timing, 3435 .num_timings = 1, 3436 .bpc = 6, 3437 .size = { 3438 .width = 152, 3439 .height = 91, 3440 }, 3441 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3442 }; 3443 3444 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3445 .clock = 33333, 3446 .hdisplay = 800, 3447 .hsync_start = 800 + 210, 3448 .hsync_end = 800 + 210 + 20, 3449 .htotal = 800 + 210 + 20 + 46, 3450 .vdisplay = 480, 3451 .vsync_start = 480 + 22, 3452 .vsync_end = 480 + 22 + 10, 3453 .vtotal = 480 + 22 + 10 + 23, 3454 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3455 }; 3456 3457 static const struct panel_desc vl050_8048nt_c01 = { 3458 .modes = &vl050_8048nt_c01_mode, 3459 .num_modes = 1, 3460 .bpc = 8, 3461 .size = { 3462 .width = 120, 3463 .height = 76, 3464 }, 3465 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3466 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3467 }; 3468 3469 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3470 .clock = 6410, 3471 .hdisplay = 320, 3472 .hsync_start = 320 + 20, 3473 .hsync_end = 320 + 20 + 30, 3474 .htotal = 320 + 20 + 30 + 38, 3475 .vdisplay = 240, 3476 .vsync_start = 240 + 4, 3477 .vsync_end = 240 + 4 + 3, 3478 .vtotal = 240 + 4 + 3 + 15, 3479 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3480 }; 3481 3482 static const struct panel_desc winstar_wf35ltiacd = { 3483 .modes = &winstar_wf35ltiacd_mode, 3484 .num_modes = 1, 3485 .bpc = 8, 3486 .size = { 3487 .width = 70, 3488 .height = 53, 3489 }, 3490 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3491 }; 3492 3493 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 3494 .clock = 51200, 3495 .hdisplay = 1024, 3496 .hsync_start = 1024 + 100, 3497 .hsync_end = 1024 + 100 + 100, 3498 .htotal = 1024 + 100 + 100 + 120, 3499 .vdisplay = 600, 3500 .vsync_start = 600 + 10, 3501 .vsync_end = 600 + 10 + 10, 3502 .vtotal = 600 + 10 + 10 + 15, 3503 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3504 }; 3505 3506 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 3507 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 3508 .num_modes = 1, 3509 .bpc = 8, 3510 .size = { 3511 .width = 154, 3512 .height = 90, 3513 }, 3514 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3515 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3516 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3517 }; 3518 3519 static const struct drm_display_mode arm_rtsm_mode[] = { 3520 { 3521 .clock = 65000, 3522 .hdisplay = 1024, 3523 .hsync_start = 1024 + 24, 3524 .hsync_end = 1024 + 24 + 136, 3525 .htotal = 1024 + 24 + 136 + 160, 3526 .vdisplay = 768, 3527 .vsync_start = 768 + 3, 3528 .vsync_end = 768 + 3 + 6, 3529 .vtotal = 768 + 3 + 6 + 29, 3530 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3531 }, 3532 }; 3533 3534 static const struct panel_desc arm_rtsm = { 3535 .modes = arm_rtsm_mode, 3536 .num_modes = 1, 3537 .bpc = 8, 3538 .size = { 3539 .width = 400, 3540 .height = 300, 3541 }, 3542 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3543 }; 3544 3545 static const struct of_device_id platform_of_match[] = { 3546 { 3547 .compatible = "ampire,am-1280800n3tzqw-t00h", 3548 .data = &ire_am_1280800n3tzqw_t00h, 3549 }, { 3550 .compatible = "ampire,am-480272h3tmqw-t01h", 3551 .data = &ire_am_480272h3tmqw_t01h, 3552 }, { 3553 .compatible = "ampire,am800480r3tmqwa1h", 3554 .data = &ire_am800480r3tmqwa1h, 3555 }, { 3556 .compatible = "arm,rtsm-display", 3557 .data = &arm_rtsm, 3558 }, { 3559 .compatible = "armadeus,st0700-adapt", 3560 .data = &armadeus_st0700_adapt, 3561 }, { 3562 .compatible = "auo,b101aw03", 3563 .data = &auo_b101aw03, 3564 }, { 3565 .compatible = "auo,b101xtn01", 3566 .data = &auo_b101xtn01, 3567 }, { 3568 .compatible = "auo,g070vvn01", 3569 .data = &auo_g070vvn01, 3570 }, { 3571 .compatible = "auo,g101evn010", 3572 .data = &auo_g101evn010, 3573 }, { 3574 .compatible = "auo,g104sn02", 3575 .data = &auo_g104sn02, 3576 }, { 3577 .compatible = "auo,g121ean01", 3578 .data = &auo_g121ean01, 3579 }, { 3580 .compatible = "auo,g133han01", 3581 .data = &auo_g133han01, 3582 }, { 3583 .compatible = "auo,g156xtn01", 3584 .data = &auo_g156xtn01, 3585 }, { 3586 .compatible = "auo,g185han01", 3587 .data = &auo_g185han01, 3588 }, { 3589 .compatible = "auo,g190ean01", 3590 .data = &auo_g190ean01, 3591 }, { 3592 .compatible = "auo,p320hvn03", 3593 .data = &auo_p320hvn03, 3594 }, { 3595 .compatible = "auo,t215hvn01", 3596 .data = &auo_t215hvn01, 3597 }, { 3598 .compatible = "avic,tm070ddh03", 3599 .data = &avic_tm070ddh03, 3600 }, { 3601 .compatible = "bananapi,s070wv20-ct16", 3602 .data = &bananapi_s070wv20_ct16, 3603 }, { 3604 .compatible = "boe,hv070wsa-100", 3605 .data = &boe_hv070wsa 3606 }, { 3607 .compatible = "cdtech,s043wq26h-ct7", 3608 .data = &cdtech_s043wq26h_ct7, 3609 }, { 3610 .compatible = "cdtech,s070pws19hp-fc21", 3611 .data = &cdtech_s070pws19hp_fc21, 3612 }, { 3613 .compatible = "cdtech,s070swv29hg-dc44", 3614 .data = &cdtech_s070swv29hg_dc44, 3615 }, { 3616 .compatible = "cdtech,s070wv95-ct16", 3617 .data = &cdtech_s070wv95_ct16, 3618 }, { 3619 .compatible = "chefree,ch101olhlwh-002", 3620 .data = &chefree_ch101olhlwh_002, 3621 }, { 3622 .compatible = "chunghwa,claa070wp03xg", 3623 .data = &chunghwa_claa070wp03xg, 3624 }, { 3625 .compatible = "chunghwa,claa101wa01a", 3626 .data = &chunghwa_claa101wa01a 3627 }, { 3628 .compatible = "chunghwa,claa101wb01", 3629 .data = &chunghwa_claa101wb01 3630 }, { 3631 .compatible = "dataimage,scf0700c48ggu18", 3632 .data = &dataimage_scf0700c48ggu18, 3633 }, { 3634 .compatible = "dlc,dlc0700yzg-1", 3635 .data = &dlc_dlc0700yzg_1, 3636 }, { 3637 .compatible = "dlc,dlc1010gig", 3638 .data = &dlc_dlc1010gig, 3639 }, { 3640 .compatible = "edt,et035012dm6", 3641 .data = &edt_et035012dm6, 3642 }, { 3643 .compatible = "edt,etm0350g0dh6", 3644 .data = &edt_etm0350g0dh6, 3645 }, { 3646 .compatible = "edt,etm043080dh6gp", 3647 .data = &edt_etm043080dh6gp, 3648 }, { 3649 .compatible = "edt,etm0430g0dh6", 3650 .data = &edt_etm0430g0dh6, 3651 }, { 3652 .compatible = "edt,et057090dhu", 3653 .data = &edt_et057090dhu, 3654 }, { 3655 .compatible = "edt,et070080dh6", 3656 .data = &edt_etm0700g0dh6, 3657 }, { 3658 .compatible = "edt,etm0700g0dh6", 3659 .data = &edt_etm0700g0dh6, 3660 }, { 3661 .compatible = "edt,etm0700g0bdh6", 3662 .data = &edt_etm0700g0bdh6, 3663 }, { 3664 .compatible = "edt,etm0700g0edh6", 3665 .data = &edt_etm0700g0bdh6, 3666 }, { 3667 .compatible = "edt,etmv570g2dhu", 3668 .data = &edt_etmv570g2dhu, 3669 }, { 3670 .compatible = "eink,vb3300-kca", 3671 .data = &eink_vb3300_kca, 3672 }, { 3673 .compatible = "evervision,vgg804821", 3674 .data = &evervision_vgg804821, 3675 }, { 3676 .compatible = "foxlink,fl500wvr00-a0t", 3677 .data = &foxlink_fl500wvr00_a0t, 3678 }, { 3679 .compatible = "frida,frd350h54004", 3680 .data = &frida_frd350h54004, 3681 }, { 3682 .compatible = "friendlyarm,hd702e", 3683 .data = &friendlyarm_hd702e, 3684 }, { 3685 .compatible = "giantplus,gpg482739qs5", 3686 .data = &giantplus_gpg482739qs5 3687 }, { 3688 .compatible = "giantplus,gpm940b0", 3689 .data = &giantplus_gpm940b0, 3690 }, { 3691 .compatible = "hannstar,hsd070pww1", 3692 .data = &hannstar_hsd070pww1, 3693 }, { 3694 .compatible = "hannstar,hsd100pxn1", 3695 .data = &hannstar_hsd100pxn1, 3696 }, { 3697 .compatible = "hit,tx23d38vm0caa", 3698 .data = &hitachi_tx23d38vm0caa 3699 }, { 3700 .compatible = "innolux,at043tn24", 3701 .data = &innolux_at043tn24, 3702 }, { 3703 .compatible = "innolux,at070tn92", 3704 .data = &innolux_at070tn92, 3705 }, { 3706 .compatible = "innolux,g070y2-l01", 3707 .data = &innolux_g070y2_l01, 3708 }, { 3709 .compatible = "innolux,g101ice-l01", 3710 .data = &innolux_g101ice_l01 3711 }, { 3712 .compatible = "innolux,g121i1-l01", 3713 .data = &innolux_g121i1_l01 3714 }, { 3715 .compatible = "innolux,g121x1-l03", 3716 .data = &innolux_g121x1_l03, 3717 }, { 3718 .compatible = "innolux,n156bge-l21", 3719 .data = &innolux_n156bge_l21, 3720 }, { 3721 .compatible = "innolux,zj070na-01p", 3722 .data = &innolux_zj070na_01p, 3723 }, { 3724 .compatible = "koe,tx14d24vm1bpa", 3725 .data = &koe_tx14d24vm1bpa, 3726 }, { 3727 .compatible = "koe,tx26d202vm0bwa", 3728 .data = &koe_tx26d202vm0bwa, 3729 }, { 3730 .compatible = "koe,tx31d200vm0baa", 3731 .data = &koe_tx31d200vm0baa, 3732 }, { 3733 .compatible = "kyo,tcg121xglp", 3734 .data = &kyo_tcg121xglp, 3735 }, { 3736 .compatible = "lemaker,bl035-rgb-002", 3737 .data = &lemaker_bl035_rgb_002, 3738 }, { 3739 .compatible = "lg,lb070wv8", 3740 .data = &lg_lb070wv8, 3741 }, { 3742 .compatible = "logicpd,type28", 3743 .data = &logicpd_type_28, 3744 }, { 3745 .compatible = "logictechno,lt161010-2nhc", 3746 .data = &logictechno_lt161010_2nh, 3747 }, { 3748 .compatible = "logictechno,lt161010-2nhr", 3749 .data = &logictechno_lt161010_2nh, 3750 }, { 3751 .compatible = "logictechno,lt170410-2whc", 3752 .data = &logictechno_lt170410_2whc, 3753 }, { 3754 .compatible = "logictechno,lttd800480070-l6wh-rt", 3755 .data = &logictechno_lttd800480070_l6wh_rt, 3756 }, { 3757 .compatible = "mitsubishi,aa070mc01-ca1", 3758 .data = &mitsubishi_aa070mc01, 3759 }, { 3760 .compatible = "multi-inno,mi1010ait-1cp", 3761 .data = &multi_inno_mi1010ait_1cp, 3762 }, { 3763 .compatible = "nec,nl12880bc20-05", 3764 .data = &nec_nl12880bc20_05, 3765 }, { 3766 .compatible = "nec,nl4827hc19-05b", 3767 .data = &nec_nl4827hc19_05b, 3768 }, { 3769 .compatible = "netron-dy,e231732", 3770 .data = &netron_dy_e231732, 3771 }, { 3772 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 3773 .data = &newhaven_nhd_43_480272ef_atxl, 3774 }, { 3775 .compatible = "nlt,nl192108ac18-02d", 3776 .data = &nlt_nl192108ac18_02d, 3777 }, { 3778 .compatible = "nvd,9128", 3779 .data = &nvd_9128, 3780 }, { 3781 .compatible = "okaya,rs800480t-7x0gp", 3782 .data = &okaya_rs800480t_7x0gp, 3783 }, { 3784 .compatible = "olimex,lcd-olinuxino-43-ts", 3785 .data = &olimex_lcd_olinuxino_43ts, 3786 }, { 3787 .compatible = "ontat,yx700wv03", 3788 .data = &ontat_yx700wv03, 3789 }, { 3790 .compatible = "ortustech,com37h3m05dtc", 3791 .data = &ortustech_com37h3m, 3792 }, { 3793 .compatible = "ortustech,com37h3m99dtc", 3794 .data = &ortustech_com37h3m, 3795 }, { 3796 .compatible = "ortustech,com43h4m85ulc", 3797 .data = &ortustech_com43h4m85ulc, 3798 }, { 3799 .compatible = "osddisplays,osd070t1718-19ts", 3800 .data = &osddisplays_osd070t1718_19ts, 3801 }, { 3802 .compatible = "pda,91-00156-a0", 3803 .data = &pda_91_00156_a0, 3804 }, { 3805 .compatible = "powertip,ph800480t013-idf02", 3806 .data = &powertip_ph800480t013_idf02, 3807 }, { 3808 .compatible = "qiaodian,qd43003c0-40", 3809 .data = &qd43003c0_40, 3810 }, { 3811 .compatible = "qishenglong,gopher2b-lcd", 3812 .data = &qishenglong_gopher2b_lcd, 3813 }, { 3814 .compatible = "rocktech,rk070er9427", 3815 .data = &rocktech_rk070er9427, 3816 }, { 3817 .compatible = "rocktech,rk101ii01d-ct", 3818 .data = &rocktech_rk101ii01d_ct, 3819 }, { 3820 .compatible = "samsung,ltn101nt05", 3821 .data = &samsung_ltn101nt05, 3822 }, { 3823 .compatible = "satoz,sat050at40h12r2", 3824 .data = &satoz_sat050at40h12r2, 3825 }, { 3826 .compatible = "sharp,lq035q7db03", 3827 .data = &sharp_lq035q7db03, 3828 }, { 3829 .compatible = "sharp,lq070y3dg3b", 3830 .data = &sharp_lq070y3dg3b, 3831 }, { 3832 .compatible = "sharp,lq101k1ly04", 3833 .data = &sharp_lq101k1ly04, 3834 }, { 3835 .compatible = "sharp,ls020b1dd01d", 3836 .data = &sharp_ls020b1dd01d, 3837 }, { 3838 .compatible = "shelly,sca07010-bfn-lnn", 3839 .data = &shelly_sca07010_bfn_lnn, 3840 }, { 3841 .compatible = "starry,kr070pe2t", 3842 .data = &starry_kr070pe2t, 3843 }, { 3844 .compatible = "tfc,s9700rtwv43tr-01b", 3845 .data = &tfc_s9700rtwv43tr_01b, 3846 }, { 3847 .compatible = "tianma,tm070jdhg30", 3848 .data = &tianma_tm070jdhg30, 3849 }, { 3850 .compatible = "tianma,tm070jvhg33", 3851 .data = &tianma_tm070jvhg33, 3852 }, { 3853 .compatible = "tianma,tm070rvhg71", 3854 .data = &tianma_tm070rvhg71, 3855 }, { 3856 .compatible = "ti,nspire-cx-lcd-panel", 3857 .data = &ti_nspire_cx_lcd_panel, 3858 }, { 3859 .compatible = "ti,nspire-classic-lcd-panel", 3860 .data = &ti_nspire_classic_lcd_panel, 3861 }, { 3862 .compatible = "toshiba,lt089ac29000", 3863 .data = &toshiba_lt089ac29000, 3864 }, { 3865 .compatible = "tpk,f07a-0102", 3866 .data = &tpk_f07a_0102, 3867 }, { 3868 .compatible = "tpk,f10a-0102", 3869 .data = &tpk_f10a_0102, 3870 }, { 3871 .compatible = "urt,umsh-8596md-t", 3872 .data = &urt_umsh_8596md_parallel, 3873 }, { 3874 .compatible = "urt,umsh-8596md-1t", 3875 .data = &urt_umsh_8596md_parallel, 3876 }, { 3877 .compatible = "urt,umsh-8596md-7t", 3878 .data = &urt_umsh_8596md_parallel, 3879 }, { 3880 .compatible = "urt,umsh-8596md-11t", 3881 .data = &urt_umsh_8596md_lvds, 3882 }, { 3883 .compatible = "urt,umsh-8596md-19t", 3884 .data = &urt_umsh_8596md_lvds, 3885 }, { 3886 .compatible = "urt,umsh-8596md-20t", 3887 .data = &urt_umsh_8596md_parallel, 3888 }, { 3889 .compatible = "vxt,vl050-8048nt-c01", 3890 .data = &vl050_8048nt_c01, 3891 }, { 3892 .compatible = "winstar,wf35ltiacd", 3893 .data = &winstar_wf35ltiacd, 3894 }, { 3895 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 3896 .data = &yes_optoelectronics_ytc700tlag_05_201c, 3897 }, { 3898 /* Must be the last entry */ 3899 .compatible = "panel-dpi", 3900 .data = &panel_dpi, 3901 }, { 3902 /* sentinel */ 3903 } 3904 }; 3905 MODULE_DEVICE_TABLE(of, platform_of_match); 3906 3907 static int panel_simple_platform_probe(struct platform_device *pdev) 3908 { 3909 const struct of_device_id *id; 3910 3911 id = of_match_node(platform_of_match, pdev->dev.of_node); 3912 if (!id) 3913 return -ENODEV; 3914 3915 return panel_simple_probe(&pdev->dev, id->data); 3916 } 3917 3918 static int panel_simple_platform_remove(struct platform_device *pdev) 3919 { 3920 return panel_simple_remove(&pdev->dev); 3921 } 3922 3923 static void panel_simple_platform_shutdown(struct platform_device *pdev) 3924 { 3925 panel_simple_shutdown(&pdev->dev); 3926 } 3927 3928 static const struct dev_pm_ops panel_simple_pm_ops = { 3929 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 3930 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 3931 pm_runtime_force_resume) 3932 }; 3933 3934 static struct platform_driver panel_simple_platform_driver = { 3935 .driver = { 3936 .name = "panel-simple", 3937 .of_match_table = platform_of_match, 3938 .pm = &panel_simple_pm_ops, 3939 }, 3940 .probe = panel_simple_platform_probe, 3941 .remove = panel_simple_platform_remove, 3942 .shutdown = panel_simple_platform_shutdown, 3943 }; 3944 3945 struct panel_desc_dsi { 3946 struct panel_desc desc; 3947 3948 unsigned long flags; 3949 enum mipi_dsi_pixel_format format; 3950 unsigned int lanes; 3951 }; 3952 3953 static const struct drm_display_mode auo_b080uan01_mode = { 3954 .clock = 154500, 3955 .hdisplay = 1200, 3956 .hsync_start = 1200 + 62, 3957 .hsync_end = 1200 + 62 + 4, 3958 .htotal = 1200 + 62 + 4 + 62, 3959 .vdisplay = 1920, 3960 .vsync_start = 1920 + 9, 3961 .vsync_end = 1920 + 9 + 2, 3962 .vtotal = 1920 + 9 + 2 + 8, 3963 }; 3964 3965 static const struct panel_desc_dsi auo_b080uan01 = { 3966 .desc = { 3967 .modes = &auo_b080uan01_mode, 3968 .num_modes = 1, 3969 .bpc = 8, 3970 .size = { 3971 .width = 108, 3972 .height = 272, 3973 }, 3974 .connector_type = DRM_MODE_CONNECTOR_DSI, 3975 }, 3976 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 3977 .format = MIPI_DSI_FMT_RGB888, 3978 .lanes = 4, 3979 }; 3980 3981 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 3982 .clock = 160000, 3983 .hdisplay = 1200, 3984 .hsync_start = 1200 + 120, 3985 .hsync_end = 1200 + 120 + 20, 3986 .htotal = 1200 + 120 + 20 + 21, 3987 .vdisplay = 1920, 3988 .vsync_start = 1920 + 21, 3989 .vsync_end = 1920 + 21 + 3, 3990 .vtotal = 1920 + 21 + 3 + 18, 3991 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3992 }; 3993 3994 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 3995 .desc = { 3996 .modes = &boe_tv080wum_nl0_mode, 3997 .num_modes = 1, 3998 .size = { 3999 .width = 107, 4000 .height = 172, 4001 }, 4002 .connector_type = DRM_MODE_CONNECTOR_DSI, 4003 }, 4004 .flags = MIPI_DSI_MODE_VIDEO | 4005 MIPI_DSI_MODE_VIDEO_BURST | 4006 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4007 .format = MIPI_DSI_FMT_RGB888, 4008 .lanes = 4, 4009 }; 4010 4011 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4012 .clock = 71000, 4013 .hdisplay = 800, 4014 .hsync_start = 800 + 32, 4015 .hsync_end = 800 + 32 + 1, 4016 .htotal = 800 + 32 + 1 + 57, 4017 .vdisplay = 1280, 4018 .vsync_start = 1280 + 28, 4019 .vsync_end = 1280 + 28 + 1, 4020 .vtotal = 1280 + 28 + 1 + 14, 4021 }; 4022 4023 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4024 .desc = { 4025 .modes = &lg_ld070wx3_sl01_mode, 4026 .num_modes = 1, 4027 .bpc = 8, 4028 .size = { 4029 .width = 94, 4030 .height = 151, 4031 }, 4032 .connector_type = DRM_MODE_CONNECTOR_DSI, 4033 }, 4034 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4035 .format = MIPI_DSI_FMT_RGB888, 4036 .lanes = 4, 4037 }; 4038 4039 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4040 .clock = 67000, 4041 .hdisplay = 720, 4042 .hsync_start = 720 + 12, 4043 .hsync_end = 720 + 12 + 4, 4044 .htotal = 720 + 12 + 4 + 112, 4045 .vdisplay = 1280, 4046 .vsync_start = 1280 + 8, 4047 .vsync_end = 1280 + 8 + 4, 4048 .vtotal = 1280 + 8 + 4 + 12, 4049 }; 4050 4051 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4052 .desc = { 4053 .modes = &lg_lh500wx1_sd03_mode, 4054 .num_modes = 1, 4055 .bpc = 8, 4056 .size = { 4057 .width = 62, 4058 .height = 110, 4059 }, 4060 .connector_type = DRM_MODE_CONNECTOR_DSI, 4061 }, 4062 .flags = MIPI_DSI_MODE_VIDEO, 4063 .format = MIPI_DSI_FMT_RGB888, 4064 .lanes = 4, 4065 }; 4066 4067 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4068 .clock = 157200, 4069 .hdisplay = 1920, 4070 .hsync_start = 1920 + 154, 4071 .hsync_end = 1920 + 154 + 16, 4072 .htotal = 1920 + 154 + 16 + 32, 4073 .vdisplay = 1200, 4074 .vsync_start = 1200 + 17, 4075 .vsync_end = 1200 + 17 + 2, 4076 .vtotal = 1200 + 17 + 2 + 16, 4077 }; 4078 4079 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4080 .desc = { 4081 .modes = &panasonic_vvx10f004b00_mode, 4082 .num_modes = 1, 4083 .bpc = 8, 4084 .size = { 4085 .width = 217, 4086 .height = 136, 4087 }, 4088 .connector_type = DRM_MODE_CONNECTOR_DSI, 4089 }, 4090 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4091 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4092 .format = MIPI_DSI_FMT_RGB888, 4093 .lanes = 4, 4094 }; 4095 4096 static const struct drm_display_mode lg_acx467akm_7_mode = { 4097 .clock = 150000, 4098 .hdisplay = 1080, 4099 .hsync_start = 1080 + 2, 4100 .hsync_end = 1080 + 2 + 2, 4101 .htotal = 1080 + 2 + 2 + 2, 4102 .vdisplay = 1920, 4103 .vsync_start = 1920 + 2, 4104 .vsync_end = 1920 + 2 + 2, 4105 .vtotal = 1920 + 2 + 2 + 2, 4106 }; 4107 4108 static const struct panel_desc_dsi lg_acx467akm_7 = { 4109 .desc = { 4110 .modes = &lg_acx467akm_7_mode, 4111 .num_modes = 1, 4112 .bpc = 8, 4113 .size = { 4114 .width = 62, 4115 .height = 110, 4116 }, 4117 .connector_type = DRM_MODE_CONNECTOR_DSI, 4118 }, 4119 .flags = 0, 4120 .format = MIPI_DSI_FMT_RGB888, 4121 .lanes = 4, 4122 }; 4123 4124 static const struct drm_display_mode osd101t2045_53ts_mode = { 4125 .clock = 154500, 4126 .hdisplay = 1920, 4127 .hsync_start = 1920 + 112, 4128 .hsync_end = 1920 + 112 + 16, 4129 .htotal = 1920 + 112 + 16 + 32, 4130 .vdisplay = 1200, 4131 .vsync_start = 1200 + 16, 4132 .vsync_end = 1200 + 16 + 2, 4133 .vtotal = 1200 + 16 + 2 + 16, 4134 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4135 }; 4136 4137 static const struct panel_desc_dsi osd101t2045_53ts = { 4138 .desc = { 4139 .modes = &osd101t2045_53ts_mode, 4140 .num_modes = 1, 4141 .bpc = 8, 4142 .size = { 4143 .width = 217, 4144 .height = 136, 4145 }, 4146 .connector_type = DRM_MODE_CONNECTOR_DSI, 4147 }, 4148 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4149 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4150 MIPI_DSI_MODE_NO_EOT_PACKET, 4151 .format = MIPI_DSI_FMT_RGB888, 4152 .lanes = 4, 4153 }; 4154 4155 static const struct of_device_id dsi_of_match[] = { 4156 { 4157 .compatible = "auo,b080uan01", 4158 .data = &auo_b080uan01 4159 }, { 4160 .compatible = "boe,tv080wum-nl0", 4161 .data = &boe_tv080wum_nl0 4162 }, { 4163 .compatible = "lg,ld070wx3-sl01", 4164 .data = &lg_ld070wx3_sl01 4165 }, { 4166 .compatible = "lg,lh500wx1-sd03", 4167 .data = &lg_lh500wx1_sd03 4168 }, { 4169 .compatible = "panasonic,vvx10f004b00", 4170 .data = &panasonic_vvx10f004b00 4171 }, { 4172 .compatible = "lg,acx467akm-7", 4173 .data = &lg_acx467akm_7 4174 }, { 4175 .compatible = "osddisplays,osd101t2045-53ts", 4176 .data = &osd101t2045_53ts 4177 }, { 4178 /* sentinel */ 4179 } 4180 }; 4181 MODULE_DEVICE_TABLE(of, dsi_of_match); 4182 4183 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4184 { 4185 const struct panel_desc_dsi *desc; 4186 const struct of_device_id *id; 4187 int err; 4188 4189 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4190 if (!id) 4191 return -ENODEV; 4192 4193 desc = id->data; 4194 4195 err = panel_simple_probe(&dsi->dev, &desc->desc); 4196 if (err < 0) 4197 return err; 4198 4199 dsi->mode_flags = desc->flags; 4200 dsi->format = desc->format; 4201 dsi->lanes = desc->lanes; 4202 4203 err = mipi_dsi_attach(dsi); 4204 if (err) { 4205 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4206 4207 drm_panel_remove(&panel->base); 4208 } 4209 4210 return err; 4211 } 4212 4213 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4214 { 4215 int err; 4216 4217 err = mipi_dsi_detach(dsi); 4218 if (err < 0) 4219 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4220 4221 return panel_simple_remove(&dsi->dev); 4222 } 4223 4224 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4225 { 4226 panel_simple_shutdown(&dsi->dev); 4227 } 4228 4229 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4230 .driver = { 4231 .name = "panel-simple-dsi", 4232 .of_match_table = dsi_of_match, 4233 .pm = &panel_simple_pm_ops, 4234 }, 4235 .probe = panel_simple_dsi_probe, 4236 .remove = panel_simple_dsi_remove, 4237 .shutdown = panel_simple_dsi_shutdown, 4238 }; 4239 4240 static int __init panel_simple_init(void) 4241 { 4242 int err; 4243 4244 err = platform_driver_register(&panel_simple_platform_driver); 4245 if (err < 0) 4246 return err; 4247 4248 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4249 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4250 if (err < 0) 4251 goto err_did_platform_register; 4252 } 4253 4254 return 0; 4255 4256 err_did_platform_register: 4257 platform_driver_unregister(&panel_simple_platform_driver); 4258 4259 return err; 4260 } 4261 module_init(panel_simple_init); 4262 4263 static void __exit panel_simple_exit(void) 4264 { 4265 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4266 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4267 4268 platform_driver_unregister(&panel_simple_platform_driver); 4269 } 4270 module_exit(panel_simple_exit); 4271 4272 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4273 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4274 MODULE_LICENSE("GPL and additional rights"); 4275