xref: /linux/drivers/gpu/drm/panel/panel-simple.c (revision dec1c62e91ba268ab2a6e339d4d7a59287d5eba1)
1 /*
2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the
12  * next paragraph) shall be included in all copies or substantial portions
13  * of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/regulator/consumer.h>
31 
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
35 
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
40 
41 /**
42  * struct panel_desc - Describes a simple panel.
43  */
44 struct panel_desc {
45 	/**
46 	 * @modes: Pointer to array of fixed modes appropriate for this panel.
47 	 *
48 	 * If only one mode then this can just be the address of the mode.
49 	 * NOTE: cannot be used with "timings" and also if this is specified
50 	 * then you cannot override the mode in the device tree.
51 	 */
52 	const struct drm_display_mode *modes;
53 
54 	/** @num_modes: Number of elements in modes array. */
55 	unsigned int num_modes;
56 
57 	/**
58 	 * @timings: Pointer to array of display timings
59 	 *
60 	 * NOTE: cannot be used with "modes" and also these will be used to
61 	 * validate a device tree override if one is present.
62 	 */
63 	const struct display_timing *timings;
64 
65 	/** @num_timings: Number of elements in timings array. */
66 	unsigned int num_timings;
67 
68 	/** @bpc: Bits per color. */
69 	unsigned int bpc;
70 
71 	/** @size: Structure containing the physical size of this panel. */
72 	struct {
73 		/**
74 		 * @size.width: Width (in mm) of the active display area.
75 		 */
76 		unsigned int width;
77 
78 		/**
79 		 * @size.height: Height (in mm) of the active display area.
80 		 */
81 		unsigned int height;
82 	} size;
83 
84 	/** @delay: Structure containing various delay values for this panel. */
85 	struct {
86 		/**
87 		 * @delay.prepare: Time for the panel to become ready.
88 		 *
89 		 * The time (in milliseconds) that it takes for the panel to
90 		 * become ready and start receiving video data
91 		 */
92 		unsigned int prepare;
93 
94 		/**
95 		 * @delay.enable: Time for the panel to display a valid frame.
96 		 *
97 		 * The time (in milliseconds) that it takes for the panel to
98 		 * display the first valid frame after starting to receive
99 		 * video data.
100 		 */
101 		unsigned int enable;
102 
103 		/**
104 		 * @delay.disable: Time for the panel to turn the display off.
105 		 *
106 		 * The time (in milliseconds) that it takes for the panel to
107 		 * turn the display off (no content is visible).
108 		 */
109 		unsigned int disable;
110 
111 		/**
112 		 * @delay.unprepare: Time to power down completely.
113 		 *
114 		 * The time (in milliseconds) that it takes for the panel
115 		 * to power itself down completely.
116 		 *
117 		 * This time is used to prevent a future "prepare" from
118 		 * starting until at least this many milliseconds has passed.
119 		 * If at prepare time less time has passed since unprepare
120 		 * finished, the driver waits for the remaining time.
121 		 */
122 		unsigned int unprepare;
123 	} delay;
124 
125 	/** @bus_format: See MEDIA_BUS_FMT_... defines. */
126 	u32 bus_format;
127 
128 	/** @bus_flags: See DRM_BUS_FLAG_... defines. */
129 	u32 bus_flags;
130 
131 	/** @connector_type: LVDS, eDP, DSI, DPI, etc. */
132 	int connector_type;
133 };
134 
135 struct panel_simple {
136 	struct drm_panel base;
137 	bool enabled;
138 
139 	bool prepared;
140 
141 	ktime_t prepared_time;
142 	ktime_t unprepared_time;
143 
144 	const struct panel_desc *desc;
145 
146 	struct regulator *supply;
147 	struct i2c_adapter *ddc;
148 
149 	struct gpio_desc *enable_gpio;
150 
151 	struct edid *edid;
152 
153 	struct drm_display_mode override_mode;
154 
155 	enum drm_panel_orientation orientation;
156 };
157 
158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
159 {
160 	return container_of(panel, struct panel_simple, base);
161 }
162 
163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
164 						   struct drm_connector *connector)
165 {
166 	struct drm_display_mode *mode;
167 	unsigned int i, num = 0;
168 
169 	for (i = 0; i < panel->desc->num_timings; i++) {
170 		const struct display_timing *dt = &panel->desc->timings[i];
171 		struct videomode vm;
172 
173 		videomode_from_timing(dt, &vm);
174 		mode = drm_mode_create(connector->dev);
175 		if (!mode) {
176 			dev_err(panel->base.dev, "failed to add mode %ux%u\n",
177 				dt->hactive.typ, dt->vactive.typ);
178 			continue;
179 		}
180 
181 		drm_display_mode_from_videomode(&vm, mode);
182 
183 		mode->type |= DRM_MODE_TYPE_DRIVER;
184 
185 		if (panel->desc->num_timings == 1)
186 			mode->type |= DRM_MODE_TYPE_PREFERRED;
187 
188 		drm_mode_probed_add(connector, mode);
189 		num++;
190 	}
191 
192 	return num;
193 }
194 
195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
196 						   struct drm_connector *connector)
197 {
198 	struct drm_display_mode *mode;
199 	unsigned int i, num = 0;
200 
201 	for (i = 0; i < panel->desc->num_modes; i++) {
202 		const struct drm_display_mode *m = &panel->desc->modes[i];
203 
204 		mode = drm_mode_duplicate(connector->dev, m);
205 		if (!mode) {
206 			dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
207 				m->hdisplay, m->vdisplay,
208 				drm_mode_vrefresh(m));
209 			continue;
210 		}
211 
212 		mode->type |= DRM_MODE_TYPE_DRIVER;
213 
214 		if (panel->desc->num_modes == 1)
215 			mode->type |= DRM_MODE_TYPE_PREFERRED;
216 
217 		drm_mode_set_name(mode);
218 
219 		drm_mode_probed_add(connector, mode);
220 		num++;
221 	}
222 
223 	return num;
224 }
225 
226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
227 					   struct drm_connector *connector)
228 {
229 	struct drm_display_mode *mode;
230 	bool has_override = panel->override_mode.type;
231 	unsigned int num = 0;
232 
233 	if (!panel->desc)
234 		return 0;
235 
236 	if (has_override) {
237 		mode = drm_mode_duplicate(connector->dev,
238 					  &panel->override_mode);
239 		if (mode) {
240 			drm_mode_probed_add(connector, mode);
241 			num = 1;
242 		} else {
243 			dev_err(panel->base.dev, "failed to add override mode\n");
244 		}
245 	}
246 
247 	/* Only add timings if override was not there or failed to validate */
248 	if (num == 0 && panel->desc->num_timings)
249 		num = panel_simple_get_timings_modes(panel, connector);
250 
251 	/*
252 	 * Only add fixed modes if timings/override added no mode.
253 	 *
254 	 * We should only ever have either the display timings specified
255 	 * or a fixed mode. Anything else is rather bogus.
256 	 */
257 	WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
258 	if (num == 0)
259 		num = panel_simple_get_display_modes(panel, connector);
260 
261 	connector->display_info.bpc = panel->desc->bpc;
262 	connector->display_info.width_mm = panel->desc->size.width;
263 	connector->display_info.height_mm = panel->desc->size.height;
264 	if (panel->desc->bus_format)
265 		drm_display_info_set_bus_formats(&connector->display_info,
266 						 &panel->desc->bus_format, 1);
267 	connector->display_info.bus_flags = panel->desc->bus_flags;
268 
269 	return num;
270 }
271 
272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
273 {
274 	ktime_t now_ktime, min_ktime;
275 
276 	if (!min_ms)
277 		return;
278 
279 	min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
280 	now_ktime = ktime_get();
281 
282 	if (ktime_before(now_ktime, min_ktime))
283 		msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
284 }
285 
286 static int panel_simple_disable(struct drm_panel *panel)
287 {
288 	struct panel_simple *p = to_panel_simple(panel);
289 
290 	if (!p->enabled)
291 		return 0;
292 
293 	if (p->desc->delay.disable)
294 		msleep(p->desc->delay.disable);
295 
296 	p->enabled = false;
297 
298 	return 0;
299 }
300 
301 static int panel_simple_suspend(struct device *dev)
302 {
303 	struct panel_simple *p = dev_get_drvdata(dev);
304 
305 	gpiod_set_value_cansleep(p->enable_gpio, 0);
306 	regulator_disable(p->supply);
307 	p->unprepared_time = ktime_get();
308 
309 	kfree(p->edid);
310 	p->edid = NULL;
311 
312 	return 0;
313 }
314 
315 static int panel_simple_unprepare(struct drm_panel *panel)
316 {
317 	struct panel_simple *p = to_panel_simple(panel);
318 	int ret;
319 
320 	/* Unpreparing when already unprepared is a no-op */
321 	if (!p->prepared)
322 		return 0;
323 
324 	pm_runtime_mark_last_busy(panel->dev);
325 	ret = pm_runtime_put_autosuspend(panel->dev);
326 	if (ret < 0)
327 		return ret;
328 	p->prepared = false;
329 
330 	return 0;
331 }
332 
333 static int panel_simple_resume(struct device *dev)
334 {
335 	struct panel_simple *p = dev_get_drvdata(dev);
336 	int err;
337 
338 	panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
339 
340 	err = regulator_enable(p->supply);
341 	if (err < 0) {
342 		dev_err(dev, "failed to enable supply: %d\n", err);
343 		return err;
344 	}
345 
346 	gpiod_set_value_cansleep(p->enable_gpio, 1);
347 
348 	if (p->desc->delay.prepare)
349 		msleep(p->desc->delay.prepare);
350 
351 	p->prepared_time = ktime_get();
352 
353 	return 0;
354 }
355 
356 static int panel_simple_prepare(struct drm_panel *panel)
357 {
358 	struct panel_simple *p = to_panel_simple(panel);
359 	int ret;
360 
361 	/* Preparing when already prepared is a no-op */
362 	if (p->prepared)
363 		return 0;
364 
365 	ret = pm_runtime_get_sync(panel->dev);
366 	if (ret < 0) {
367 		pm_runtime_put_autosuspend(panel->dev);
368 		return ret;
369 	}
370 
371 	p->prepared = true;
372 
373 	return 0;
374 }
375 
376 static int panel_simple_enable(struct drm_panel *panel)
377 {
378 	struct panel_simple *p = to_panel_simple(panel);
379 
380 	if (p->enabled)
381 		return 0;
382 
383 	if (p->desc->delay.enable)
384 		msleep(p->desc->delay.enable);
385 
386 	p->enabled = true;
387 
388 	return 0;
389 }
390 
391 static int panel_simple_get_modes(struct drm_panel *panel,
392 				  struct drm_connector *connector)
393 {
394 	struct panel_simple *p = to_panel_simple(panel);
395 	int num = 0;
396 
397 	/* probe EDID if a DDC bus is available */
398 	if (p->ddc) {
399 		pm_runtime_get_sync(panel->dev);
400 
401 		if (!p->edid)
402 			p->edid = drm_get_edid(connector, p->ddc);
403 
404 		if (p->edid)
405 			num += drm_add_edid_modes(connector, p->edid);
406 
407 		pm_runtime_mark_last_busy(panel->dev);
408 		pm_runtime_put_autosuspend(panel->dev);
409 	}
410 
411 	/* add hard-coded panel modes */
412 	num += panel_simple_get_non_edid_modes(p, connector);
413 
414 	/* set up connector's "panel orientation" property */
415 	drm_connector_set_panel_orientation(connector, p->orientation);
416 
417 	return num;
418 }
419 
420 static int panel_simple_get_timings(struct drm_panel *panel,
421 				    unsigned int num_timings,
422 				    struct display_timing *timings)
423 {
424 	struct panel_simple *p = to_panel_simple(panel);
425 	unsigned int i;
426 
427 	if (p->desc->num_timings < num_timings)
428 		num_timings = p->desc->num_timings;
429 
430 	if (timings)
431 		for (i = 0; i < num_timings; i++)
432 			timings[i] = p->desc->timings[i];
433 
434 	return p->desc->num_timings;
435 }
436 
437 static const struct drm_panel_funcs panel_simple_funcs = {
438 	.disable = panel_simple_disable,
439 	.unprepare = panel_simple_unprepare,
440 	.prepare = panel_simple_prepare,
441 	.enable = panel_simple_enable,
442 	.get_modes = panel_simple_get_modes,
443 	.get_timings = panel_simple_get_timings,
444 };
445 
446 static struct panel_desc panel_dpi;
447 
448 static int panel_dpi_probe(struct device *dev,
449 			   struct panel_simple *panel)
450 {
451 	struct display_timing *timing;
452 	const struct device_node *np;
453 	struct panel_desc *desc;
454 	unsigned int bus_flags;
455 	struct videomode vm;
456 	int ret;
457 
458 	np = dev->of_node;
459 	desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
460 	if (!desc)
461 		return -ENOMEM;
462 
463 	timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
464 	if (!timing)
465 		return -ENOMEM;
466 
467 	ret = of_get_display_timing(np, "panel-timing", timing);
468 	if (ret < 0) {
469 		dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
470 			np);
471 		return ret;
472 	}
473 
474 	desc->timings = timing;
475 	desc->num_timings = 1;
476 
477 	of_property_read_u32(np, "width-mm", &desc->size.width);
478 	of_property_read_u32(np, "height-mm", &desc->size.height);
479 
480 	/* Extract bus_flags from display_timing */
481 	bus_flags = 0;
482 	vm.flags = timing->flags;
483 	drm_bus_flags_from_videomode(&vm, &bus_flags);
484 	desc->bus_flags = bus_flags;
485 
486 	/* We do not know the connector for the DT node, so guess it */
487 	desc->connector_type = DRM_MODE_CONNECTOR_DPI;
488 
489 	panel->desc = desc;
490 
491 	return 0;
492 }
493 
494 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
495 	(to_check->field.typ >= bounds->field.min && \
496 	 to_check->field.typ <= bounds->field.max)
497 static void panel_simple_parse_panel_timing_node(struct device *dev,
498 						 struct panel_simple *panel,
499 						 const struct display_timing *ot)
500 {
501 	const struct panel_desc *desc = panel->desc;
502 	struct videomode vm;
503 	unsigned int i;
504 
505 	if (WARN_ON(desc->num_modes)) {
506 		dev_err(dev, "Reject override mode: panel has a fixed mode\n");
507 		return;
508 	}
509 	if (WARN_ON(!desc->num_timings)) {
510 		dev_err(dev, "Reject override mode: no timings specified\n");
511 		return;
512 	}
513 
514 	for (i = 0; i < panel->desc->num_timings; i++) {
515 		const struct display_timing *dt = &panel->desc->timings[i];
516 
517 		if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
518 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
519 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
520 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
521 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
522 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
523 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
524 		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
525 			continue;
526 
527 		if (ot->flags != dt->flags)
528 			continue;
529 
530 		videomode_from_timing(ot, &vm);
531 		drm_display_mode_from_videomode(&vm, &panel->override_mode);
532 		panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
533 					     DRM_MODE_TYPE_PREFERRED;
534 		break;
535 	}
536 
537 	if (WARN_ON(!panel->override_mode.type))
538 		dev_err(dev, "Reject override mode: No display_timing found\n");
539 }
540 
541 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
542 {
543 	struct panel_simple *panel;
544 	struct display_timing dt;
545 	struct device_node *ddc;
546 	int connector_type;
547 	u32 bus_flags;
548 	int err;
549 
550 	panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
551 	if (!panel)
552 		return -ENOMEM;
553 
554 	panel->enabled = false;
555 	panel->prepared_time = 0;
556 	panel->desc = desc;
557 
558 	panel->supply = devm_regulator_get(dev, "power");
559 	if (IS_ERR(panel->supply))
560 		return PTR_ERR(panel->supply);
561 
562 	panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
563 						     GPIOD_OUT_LOW);
564 	if (IS_ERR(panel->enable_gpio)) {
565 		err = PTR_ERR(panel->enable_gpio);
566 		if (err != -EPROBE_DEFER)
567 			dev_err(dev, "failed to request GPIO: %d\n", err);
568 		return err;
569 	}
570 
571 	err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
572 	if (err) {
573 		dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
574 		return err;
575 	}
576 
577 	ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
578 	if (ddc) {
579 		panel->ddc = of_find_i2c_adapter_by_node(ddc);
580 		of_node_put(ddc);
581 
582 		if (!panel->ddc)
583 			return -EPROBE_DEFER;
584 	}
585 
586 	if (desc == &panel_dpi) {
587 		/* Handle the generic panel-dpi binding */
588 		err = panel_dpi_probe(dev, panel);
589 		if (err)
590 			goto free_ddc;
591 		desc = panel->desc;
592 	} else {
593 		if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
594 			panel_simple_parse_panel_timing_node(dev, panel, &dt);
595 	}
596 
597 	connector_type = desc->connector_type;
598 	/* Catch common mistakes for panels. */
599 	switch (connector_type) {
600 	case 0:
601 		dev_warn(dev, "Specify missing connector_type\n");
602 		connector_type = DRM_MODE_CONNECTOR_DPI;
603 		break;
604 	case DRM_MODE_CONNECTOR_LVDS:
605 		WARN_ON(desc->bus_flags &
606 			~(DRM_BUS_FLAG_DE_LOW |
607 			  DRM_BUS_FLAG_DE_HIGH |
608 			  DRM_BUS_FLAG_DATA_MSB_TO_LSB |
609 			  DRM_BUS_FLAG_DATA_LSB_TO_MSB));
610 		WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
611 			desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
612 			desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
613 		WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
614 			desc->bpc != 6);
615 		WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
616 			 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
617 			desc->bpc != 8);
618 		break;
619 	case DRM_MODE_CONNECTOR_eDP:
620 		dev_warn(dev, "eDP panels moved to panel-edp\n");
621 		err = -EINVAL;
622 		goto free_ddc;
623 	case DRM_MODE_CONNECTOR_DSI:
624 		if (desc->bpc != 6 && desc->bpc != 8)
625 			dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
626 		break;
627 	case DRM_MODE_CONNECTOR_DPI:
628 		bus_flags = DRM_BUS_FLAG_DE_LOW |
629 			    DRM_BUS_FLAG_DE_HIGH |
630 			    DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
631 			    DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
632 			    DRM_BUS_FLAG_DATA_MSB_TO_LSB |
633 			    DRM_BUS_FLAG_DATA_LSB_TO_MSB |
634 			    DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
635 			    DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
636 		if (desc->bus_flags & ~bus_flags)
637 			dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
638 		if (!(desc->bus_flags & bus_flags))
639 			dev_warn(dev, "Specify missing bus_flags\n");
640 		if (desc->bus_format == 0)
641 			dev_warn(dev, "Specify missing bus_format\n");
642 		if (desc->bpc != 6 && desc->bpc != 8)
643 			dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
644 		break;
645 	default:
646 		dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
647 		connector_type = DRM_MODE_CONNECTOR_DPI;
648 		break;
649 	}
650 
651 	dev_set_drvdata(dev, panel);
652 
653 	/*
654 	 * We use runtime PM for prepare / unprepare since those power the panel
655 	 * on and off and those can be very slow operations. This is important
656 	 * to optimize powering the panel on briefly to read the EDID before
657 	 * fully enabling the panel.
658 	 */
659 	pm_runtime_enable(dev);
660 	pm_runtime_set_autosuspend_delay(dev, 1000);
661 	pm_runtime_use_autosuspend(dev);
662 
663 	drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
664 
665 	err = drm_panel_of_backlight(&panel->base);
666 	if (err)
667 		goto disable_pm_runtime;
668 
669 	drm_panel_add(&panel->base);
670 
671 	return 0;
672 
673 disable_pm_runtime:
674 	pm_runtime_dont_use_autosuspend(dev);
675 	pm_runtime_disable(dev);
676 free_ddc:
677 	if (panel->ddc)
678 		put_device(&panel->ddc->dev);
679 
680 	return err;
681 }
682 
683 static int panel_simple_remove(struct device *dev)
684 {
685 	struct panel_simple *panel = dev_get_drvdata(dev);
686 
687 	drm_panel_remove(&panel->base);
688 	drm_panel_disable(&panel->base);
689 	drm_panel_unprepare(&panel->base);
690 
691 	pm_runtime_dont_use_autosuspend(dev);
692 	pm_runtime_disable(dev);
693 	if (panel->ddc)
694 		put_device(&panel->ddc->dev);
695 
696 	return 0;
697 }
698 
699 static void panel_simple_shutdown(struct device *dev)
700 {
701 	struct panel_simple *panel = dev_get_drvdata(dev);
702 
703 	drm_panel_disable(&panel->base);
704 	drm_panel_unprepare(&panel->base);
705 }
706 
707 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
708 	.clock = 71100,
709 	.hdisplay = 1280,
710 	.hsync_start = 1280 + 40,
711 	.hsync_end = 1280 + 40 + 80,
712 	.htotal = 1280 + 40 + 80 + 40,
713 	.vdisplay = 800,
714 	.vsync_start = 800 + 3,
715 	.vsync_end = 800 + 3 + 10,
716 	.vtotal = 800 + 3 + 10 + 10,
717 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
718 };
719 
720 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
721 	.modes = &ampire_am_1280800n3tzqw_t00h_mode,
722 	.num_modes = 1,
723 	.bpc = 8,
724 	.size = {
725 		.width = 217,
726 		.height = 136,
727 	},
728 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
729 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
730 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
731 };
732 
733 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
734 	.clock = 9000,
735 	.hdisplay = 480,
736 	.hsync_start = 480 + 2,
737 	.hsync_end = 480 + 2 + 41,
738 	.htotal = 480 + 2 + 41 + 2,
739 	.vdisplay = 272,
740 	.vsync_start = 272 + 2,
741 	.vsync_end = 272 + 2 + 10,
742 	.vtotal = 272 + 2 + 10 + 2,
743 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
744 };
745 
746 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
747 	.modes = &ampire_am_480272h3tmqw_t01h_mode,
748 	.num_modes = 1,
749 	.bpc = 8,
750 	.size = {
751 		.width = 105,
752 		.height = 67,
753 	},
754 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
755 };
756 
757 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
758 	.clock = 33333,
759 	.hdisplay = 800,
760 	.hsync_start = 800 + 0,
761 	.hsync_end = 800 + 0 + 255,
762 	.htotal = 800 + 0 + 255 + 0,
763 	.vdisplay = 480,
764 	.vsync_start = 480 + 2,
765 	.vsync_end = 480 + 2 + 45,
766 	.vtotal = 480 + 2 + 45 + 0,
767 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
768 };
769 
770 static const struct panel_desc ampire_am800480r3tmqwa1h = {
771 	.modes = &ampire_am800480r3tmqwa1h_mode,
772 	.num_modes = 1,
773 	.bpc = 6,
774 	.size = {
775 		.width = 152,
776 		.height = 91,
777 	},
778 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
779 };
780 
781 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
782 	.pixelclock = { 26400000, 33300000, 46800000 },
783 	.hactive = { 800, 800, 800 },
784 	.hfront_porch = { 16, 210, 354 },
785 	.hback_porch = { 45, 36, 6 },
786 	.hsync_len = { 1, 10, 40 },
787 	.vactive = { 480, 480, 480 },
788 	.vfront_porch = { 7, 22, 147 },
789 	.vback_porch = { 22, 13, 3 },
790 	.vsync_len = { 1, 10, 20 },
791 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
792 		DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
793 };
794 
795 static const struct panel_desc armadeus_st0700_adapt = {
796 	.timings = &santek_st0700i5y_rbslw_f_timing,
797 	.num_timings = 1,
798 	.bpc = 6,
799 	.size = {
800 		.width = 154,
801 		.height = 86,
802 	},
803 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
804 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
805 };
806 
807 static const struct drm_display_mode auo_b101aw03_mode = {
808 	.clock = 51450,
809 	.hdisplay = 1024,
810 	.hsync_start = 1024 + 156,
811 	.hsync_end = 1024 + 156 + 8,
812 	.htotal = 1024 + 156 + 8 + 156,
813 	.vdisplay = 600,
814 	.vsync_start = 600 + 16,
815 	.vsync_end = 600 + 16 + 6,
816 	.vtotal = 600 + 16 + 6 + 16,
817 };
818 
819 static const struct panel_desc auo_b101aw03 = {
820 	.modes = &auo_b101aw03_mode,
821 	.num_modes = 1,
822 	.bpc = 6,
823 	.size = {
824 		.width = 223,
825 		.height = 125,
826 	},
827 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
828 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
829 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
830 };
831 
832 static const struct drm_display_mode auo_b101xtn01_mode = {
833 	.clock = 72000,
834 	.hdisplay = 1366,
835 	.hsync_start = 1366 + 20,
836 	.hsync_end = 1366 + 20 + 70,
837 	.htotal = 1366 + 20 + 70,
838 	.vdisplay = 768,
839 	.vsync_start = 768 + 14,
840 	.vsync_end = 768 + 14 + 42,
841 	.vtotal = 768 + 14 + 42,
842 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
843 };
844 
845 static const struct panel_desc auo_b101xtn01 = {
846 	.modes = &auo_b101xtn01_mode,
847 	.num_modes = 1,
848 	.bpc = 6,
849 	.size = {
850 		.width = 223,
851 		.height = 125,
852 	},
853 };
854 
855 static const struct display_timing auo_g070vvn01_timings = {
856 	.pixelclock = { 33300000, 34209000, 45000000 },
857 	.hactive = { 800, 800, 800 },
858 	.hfront_porch = { 20, 40, 200 },
859 	.hback_porch = { 87, 40, 1 },
860 	.hsync_len = { 1, 48, 87 },
861 	.vactive = { 480, 480, 480 },
862 	.vfront_porch = { 5, 13, 200 },
863 	.vback_porch = { 31, 31, 29 },
864 	.vsync_len = { 1, 1, 3 },
865 };
866 
867 static const struct panel_desc auo_g070vvn01 = {
868 	.timings = &auo_g070vvn01_timings,
869 	.num_timings = 1,
870 	.bpc = 8,
871 	.size = {
872 		.width = 152,
873 		.height = 91,
874 	},
875 	.delay = {
876 		.prepare = 200,
877 		.enable = 50,
878 		.disable = 50,
879 		.unprepare = 1000,
880 	},
881 };
882 
883 static const struct drm_display_mode auo_g101evn010_mode = {
884 	.clock = 68930,
885 	.hdisplay = 1280,
886 	.hsync_start = 1280 + 82,
887 	.hsync_end = 1280 + 82 + 2,
888 	.htotal = 1280 + 82 + 2 + 84,
889 	.vdisplay = 800,
890 	.vsync_start = 800 + 8,
891 	.vsync_end = 800 + 8 + 2,
892 	.vtotal = 800 + 8 + 2 + 6,
893 };
894 
895 static const struct panel_desc auo_g101evn010 = {
896 	.modes = &auo_g101evn010_mode,
897 	.num_modes = 1,
898 	.bpc = 6,
899 	.size = {
900 		.width = 216,
901 		.height = 135,
902 	},
903 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
904 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
905 };
906 
907 static const struct drm_display_mode auo_g104sn02_mode = {
908 	.clock = 40000,
909 	.hdisplay = 800,
910 	.hsync_start = 800 + 40,
911 	.hsync_end = 800 + 40 + 216,
912 	.htotal = 800 + 40 + 216 + 128,
913 	.vdisplay = 600,
914 	.vsync_start = 600 + 10,
915 	.vsync_end = 600 + 10 + 35,
916 	.vtotal = 600 + 10 + 35 + 2,
917 };
918 
919 static const struct panel_desc auo_g104sn02 = {
920 	.modes = &auo_g104sn02_mode,
921 	.num_modes = 1,
922 	.bpc = 8,
923 	.size = {
924 		.width = 211,
925 		.height = 158,
926 	},
927 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
928 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
929 };
930 
931 static const struct drm_display_mode auo_g121ean01_mode = {
932 	.clock = 66700,
933 	.hdisplay = 1280,
934 	.hsync_start = 1280 + 58,
935 	.hsync_end = 1280 + 58 + 8,
936 	.htotal = 1280 + 58 + 8 + 70,
937 	.vdisplay = 800,
938 	.vsync_start = 800 + 6,
939 	.vsync_end = 800 + 6 + 4,
940 	.vtotal = 800 + 6 + 4 + 10,
941 };
942 
943 static const struct panel_desc auo_g121ean01 = {
944 	.modes = &auo_g121ean01_mode,
945 	.num_modes = 1,
946 	.bpc = 8,
947 	.size = {
948 		.width = 261,
949 		.height = 163,
950 	},
951 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
952 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
953 };
954 
955 static const struct display_timing auo_g133han01_timings = {
956 	.pixelclock = { 134000000, 141200000, 149000000 },
957 	.hactive = { 1920, 1920, 1920 },
958 	.hfront_porch = { 39, 58, 77 },
959 	.hback_porch = { 59, 88, 117 },
960 	.hsync_len = { 28, 42, 56 },
961 	.vactive = { 1080, 1080, 1080 },
962 	.vfront_porch = { 3, 8, 11 },
963 	.vback_porch = { 5, 14, 19 },
964 	.vsync_len = { 4, 14, 19 },
965 };
966 
967 static const struct panel_desc auo_g133han01 = {
968 	.timings = &auo_g133han01_timings,
969 	.num_timings = 1,
970 	.bpc = 8,
971 	.size = {
972 		.width = 293,
973 		.height = 165,
974 	},
975 	.delay = {
976 		.prepare = 200,
977 		.enable = 50,
978 		.disable = 50,
979 		.unprepare = 1000,
980 	},
981 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
982 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
983 };
984 
985 static const struct drm_display_mode auo_g156xtn01_mode = {
986 	.clock = 76000,
987 	.hdisplay = 1366,
988 	.hsync_start = 1366 + 33,
989 	.hsync_end = 1366 + 33 + 67,
990 	.htotal = 1560,
991 	.vdisplay = 768,
992 	.vsync_start = 768 + 4,
993 	.vsync_end = 768 + 4 + 4,
994 	.vtotal = 806,
995 };
996 
997 static const struct panel_desc auo_g156xtn01 = {
998 	.modes = &auo_g156xtn01_mode,
999 	.num_modes = 1,
1000 	.bpc = 8,
1001 	.size = {
1002 		.width = 344,
1003 		.height = 194,
1004 	},
1005 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1006 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1007 };
1008 
1009 static const struct display_timing auo_g185han01_timings = {
1010 	.pixelclock = { 120000000, 144000000, 175000000 },
1011 	.hactive = { 1920, 1920, 1920 },
1012 	.hfront_porch = { 36, 120, 148 },
1013 	.hback_porch = { 24, 88, 108 },
1014 	.hsync_len = { 20, 48, 64 },
1015 	.vactive = { 1080, 1080, 1080 },
1016 	.vfront_porch = { 6, 10, 40 },
1017 	.vback_porch = { 2, 5, 20 },
1018 	.vsync_len = { 2, 5, 20 },
1019 };
1020 
1021 static const struct panel_desc auo_g185han01 = {
1022 	.timings = &auo_g185han01_timings,
1023 	.num_timings = 1,
1024 	.bpc = 8,
1025 	.size = {
1026 		.width = 409,
1027 		.height = 230,
1028 	},
1029 	.delay = {
1030 		.prepare = 50,
1031 		.enable = 200,
1032 		.disable = 110,
1033 		.unprepare = 1000,
1034 	},
1035 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1036 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1037 };
1038 
1039 static const struct display_timing auo_g190ean01_timings = {
1040 	.pixelclock = { 90000000, 108000000, 135000000 },
1041 	.hactive = { 1280, 1280, 1280 },
1042 	.hfront_porch = { 126, 184, 1266 },
1043 	.hback_porch = { 84, 122, 844 },
1044 	.hsync_len = { 70, 102, 704 },
1045 	.vactive = { 1024, 1024, 1024 },
1046 	.vfront_porch = { 4, 26, 76 },
1047 	.vback_porch = { 2, 8, 25 },
1048 	.vsync_len = { 2, 8, 25 },
1049 };
1050 
1051 static const struct panel_desc auo_g190ean01 = {
1052 	.timings = &auo_g190ean01_timings,
1053 	.num_timings = 1,
1054 	.bpc = 8,
1055 	.size = {
1056 		.width = 376,
1057 		.height = 301,
1058 	},
1059 	.delay = {
1060 		.prepare = 50,
1061 		.enable = 200,
1062 		.disable = 110,
1063 		.unprepare = 1000,
1064 	},
1065 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1066 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1067 };
1068 
1069 static const struct display_timing auo_p320hvn03_timings = {
1070 	.pixelclock = { 106000000, 148500000, 164000000 },
1071 	.hactive = { 1920, 1920, 1920 },
1072 	.hfront_porch = { 25, 50, 130 },
1073 	.hback_porch = { 25, 50, 130 },
1074 	.hsync_len = { 20, 40, 105 },
1075 	.vactive = { 1080, 1080, 1080 },
1076 	.vfront_porch = { 8, 17, 150 },
1077 	.vback_porch = { 8, 17, 150 },
1078 	.vsync_len = { 4, 11, 100 },
1079 };
1080 
1081 static const struct panel_desc auo_p320hvn03 = {
1082 	.timings = &auo_p320hvn03_timings,
1083 	.num_timings = 1,
1084 	.bpc = 8,
1085 	.size = {
1086 		.width = 698,
1087 		.height = 393,
1088 	},
1089 	.delay = {
1090 		.prepare = 1,
1091 		.enable = 450,
1092 		.unprepare = 500,
1093 	},
1094 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1095 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1096 };
1097 
1098 static const struct drm_display_mode auo_t215hvn01_mode = {
1099 	.clock = 148800,
1100 	.hdisplay = 1920,
1101 	.hsync_start = 1920 + 88,
1102 	.hsync_end = 1920 + 88 + 44,
1103 	.htotal = 1920 + 88 + 44 + 148,
1104 	.vdisplay = 1080,
1105 	.vsync_start = 1080 + 4,
1106 	.vsync_end = 1080 + 4 + 5,
1107 	.vtotal = 1080 + 4 + 5 + 36,
1108 };
1109 
1110 static const struct panel_desc auo_t215hvn01 = {
1111 	.modes = &auo_t215hvn01_mode,
1112 	.num_modes = 1,
1113 	.bpc = 8,
1114 	.size = {
1115 		.width = 430,
1116 		.height = 270,
1117 	},
1118 	.delay = {
1119 		.disable = 5,
1120 		.unprepare = 1000,
1121 	}
1122 };
1123 
1124 static const struct drm_display_mode avic_tm070ddh03_mode = {
1125 	.clock = 51200,
1126 	.hdisplay = 1024,
1127 	.hsync_start = 1024 + 160,
1128 	.hsync_end = 1024 + 160 + 4,
1129 	.htotal = 1024 + 160 + 4 + 156,
1130 	.vdisplay = 600,
1131 	.vsync_start = 600 + 17,
1132 	.vsync_end = 600 + 17 + 1,
1133 	.vtotal = 600 + 17 + 1 + 17,
1134 };
1135 
1136 static const struct panel_desc avic_tm070ddh03 = {
1137 	.modes = &avic_tm070ddh03_mode,
1138 	.num_modes = 1,
1139 	.bpc = 8,
1140 	.size = {
1141 		.width = 154,
1142 		.height = 90,
1143 	},
1144 	.delay = {
1145 		.prepare = 20,
1146 		.enable = 200,
1147 		.disable = 200,
1148 	},
1149 };
1150 
1151 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1152 	.clock = 30000,
1153 	.hdisplay = 800,
1154 	.hsync_start = 800 + 40,
1155 	.hsync_end = 800 + 40 + 48,
1156 	.htotal = 800 + 40 + 48 + 40,
1157 	.vdisplay = 480,
1158 	.vsync_start = 480 + 13,
1159 	.vsync_end = 480 + 13 + 3,
1160 	.vtotal = 480 + 13 + 3 + 29,
1161 };
1162 
1163 static const struct panel_desc bananapi_s070wv20_ct16 = {
1164 	.modes = &bananapi_s070wv20_ct16_mode,
1165 	.num_modes = 1,
1166 	.bpc = 6,
1167 	.size = {
1168 		.width = 154,
1169 		.height = 86,
1170 	},
1171 };
1172 
1173 static const struct drm_display_mode boe_hv070wsa_mode = {
1174 	.clock = 42105,
1175 	.hdisplay = 1024,
1176 	.hsync_start = 1024 + 30,
1177 	.hsync_end = 1024 + 30 + 30,
1178 	.htotal = 1024 + 30 + 30 + 30,
1179 	.vdisplay = 600,
1180 	.vsync_start = 600 + 10,
1181 	.vsync_end = 600 + 10 + 10,
1182 	.vtotal = 600 + 10 + 10 + 10,
1183 };
1184 
1185 static const struct panel_desc boe_hv070wsa = {
1186 	.modes = &boe_hv070wsa_mode,
1187 	.num_modes = 1,
1188 	.bpc = 8,
1189 	.size = {
1190 		.width = 154,
1191 		.height = 90,
1192 	},
1193 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1194 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1195 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1196 };
1197 
1198 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1199 	.clock = 9000,
1200 	.hdisplay = 480,
1201 	.hsync_start = 480 + 5,
1202 	.hsync_end = 480 + 5 + 5,
1203 	.htotal = 480 + 5 + 5 + 40,
1204 	.vdisplay = 272,
1205 	.vsync_start = 272 + 8,
1206 	.vsync_end = 272 + 8 + 8,
1207 	.vtotal = 272 + 8 + 8 + 8,
1208 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1209 };
1210 
1211 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1212 	.modes = &cdtech_s043wq26h_ct7_mode,
1213 	.num_modes = 1,
1214 	.bpc = 8,
1215 	.size = {
1216 		.width = 95,
1217 		.height = 54,
1218 	},
1219 	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1220 };
1221 
1222 /* S070PWS19HP-FC21 2017/04/22 */
1223 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1224 	.clock = 51200,
1225 	.hdisplay = 1024,
1226 	.hsync_start = 1024 + 160,
1227 	.hsync_end = 1024 + 160 + 20,
1228 	.htotal = 1024 + 160 + 20 + 140,
1229 	.vdisplay = 600,
1230 	.vsync_start = 600 + 12,
1231 	.vsync_end = 600 + 12 + 3,
1232 	.vtotal = 600 + 12 + 3 + 20,
1233 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1234 };
1235 
1236 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1237 	.modes = &cdtech_s070pws19hp_fc21_mode,
1238 	.num_modes = 1,
1239 	.bpc = 6,
1240 	.size = {
1241 		.width = 154,
1242 		.height = 86,
1243 	},
1244 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1245 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1246 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1247 };
1248 
1249 /* S070SWV29HG-DC44 2017/09/21 */
1250 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1251 	.clock = 33300,
1252 	.hdisplay = 800,
1253 	.hsync_start = 800 + 210,
1254 	.hsync_end = 800 + 210 + 2,
1255 	.htotal = 800 + 210 + 2 + 44,
1256 	.vdisplay = 480,
1257 	.vsync_start = 480 + 22,
1258 	.vsync_end = 480 + 22 + 2,
1259 	.vtotal = 480 + 22 + 2 + 21,
1260 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1261 };
1262 
1263 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1264 	.modes = &cdtech_s070swv29hg_dc44_mode,
1265 	.num_modes = 1,
1266 	.bpc = 6,
1267 	.size = {
1268 		.width = 154,
1269 		.height = 86,
1270 	},
1271 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1272 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1273 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1274 };
1275 
1276 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1277 	.clock = 35000,
1278 	.hdisplay = 800,
1279 	.hsync_start = 800 + 40,
1280 	.hsync_end = 800 + 40 + 40,
1281 	.htotal = 800 + 40 + 40 + 48,
1282 	.vdisplay = 480,
1283 	.vsync_start = 480 + 29,
1284 	.vsync_end = 480 + 29 + 13,
1285 	.vtotal = 480 + 29 + 13 + 3,
1286 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1287 };
1288 
1289 static const struct panel_desc cdtech_s070wv95_ct16 = {
1290 	.modes = &cdtech_s070wv95_ct16_mode,
1291 	.num_modes = 1,
1292 	.bpc = 8,
1293 	.size = {
1294 		.width = 154,
1295 		.height = 85,
1296 	},
1297 };
1298 
1299 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1300 	.pixelclock = { 68900000, 71100000, 73400000 },
1301 	.hactive = { 1280, 1280, 1280 },
1302 	.hfront_porch = { 65, 80, 95 },
1303 	.hback_porch = { 64, 79, 94 },
1304 	.hsync_len = { 1, 1, 1 },
1305 	.vactive = { 800, 800, 800 },
1306 	.vfront_porch = { 7, 11, 14 },
1307 	.vback_porch = { 7, 11, 14 },
1308 	.vsync_len = { 1, 1, 1 },
1309 	.flags = DISPLAY_FLAGS_DE_HIGH,
1310 };
1311 
1312 static const struct panel_desc chefree_ch101olhlwh_002 = {
1313 	.timings = &chefree_ch101olhlwh_002_timing,
1314 	.num_timings = 1,
1315 	.bpc = 8,
1316 	.size = {
1317 		.width = 217,
1318 		.height = 135,
1319 	},
1320 	.delay = {
1321 		.enable = 200,
1322 		.disable = 200,
1323 	},
1324 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1325 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1326 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1327 };
1328 
1329 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1330 	.clock = 66770,
1331 	.hdisplay = 800,
1332 	.hsync_start = 800 + 49,
1333 	.hsync_end = 800 + 49 + 33,
1334 	.htotal = 800 + 49 + 33 + 17,
1335 	.vdisplay = 1280,
1336 	.vsync_start = 1280 + 1,
1337 	.vsync_end = 1280 + 1 + 7,
1338 	.vtotal = 1280 + 1 + 7 + 15,
1339 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1340 };
1341 
1342 static const struct panel_desc chunghwa_claa070wp03xg = {
1343 	.modes = &chunghwa_claa070wp03xg_mode,
1344 	.num_modes = 1,
1345 	.bpc = 6,
1346 	.size = {
1347 		.width = 94,
1348 		.height = 150,
1349 	},
1350 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1351 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1352 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1353 };
1354 
1355 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1356 	.clock = 72070,
1357 	.hdisplay = 1366,
1358 	.hsync_start = 1366 + 58,
1359 	.hsync_end = 1366 + 58 + 58,
1360 	.htotal = 1366 + 58 + 58 + 58,
1361 	.vdisplay = 768,
1362 	.vsync_start = 768 + 4,
1363 	.vsync_end = 768 + 4 + 4,
1364 	.vtotal = 768 + 4 + 4 + 4,
1365 };
1366 
1367 static const struct panel_desc chunghwa_claa101wa01a = {
1368 	.modes = &chunghwa_claa101wa01a_mode,
1369 	.num_modes = 1,
1370 	.bpc = 6,
1371 	.size = {
1372 		.width = 220,
1373 		.height = 120,
1374 	},
1375 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1376 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1377 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1378 };
1379 
1380 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1381 	.clock = 69300,
1382 	.hdisplay = 1366,
1383 	.hsync_start = 1366 + 48,
1384 	.hsync_end = 1366 + 48 + 32,
1385 	.htotal = 1366 + 48 + 32 + 20,
1386 	.vdisplay = 768,
1387 	.vsync_start = 768 + 16,
1388 	.vsync_end = 768 + 16 + 8,
1389 	.vtotal = 768 + 16 + 8 + 16,
1390 };
1391 
1392 static const struct panel_desc chunghwa_claa101wb01 = {
1393 	.modes = &chunghwa_claa101wb01_mode,
1394 	.num_modes = 1,
1395 	.bpc = 6,
1396 	.size = {
1397 		.width = 223,
1398 		.height = 125,
1399 	},
1400 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1401 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
1402 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1403 };
1404 
1405 static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1406 	.pixelclock = { 5000000, 9000000, 12000000 },
1407 	.hactive = { 480, 480, 480 },
1408 	.hfront_porch = { 12, 12, 12 },
1409 	.hback_porch = { 12, 12, 12 },
1410 	.hsync_len = { 21, 21, 21 },
1411 	.vactive = { 272, 272, 272 },
1412 	.vfront_porch = { 4, 4, 4 },
1413 	.vback_porch = { 4, 4, 4 },
1414 	.vsync_len = { 8, 8, 8 },
1415 };
1416 
1417 static const struct panel_desc dataimage_fg040346dsswbg04 = {
1418 	.timings = &dataimage_fg040346dsswbg04_timing,
1419 	.num_timings = 1,
1420 	.bpc = 8,
1421 	.size = {
1422 		.width = 95,
1423 		.height = 54,
1424 	},
1425 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1426 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1427 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1428 };
1429 
1430 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1431 	.clock = 33260,
1432 	.hdisplay = 800,
1433 	.hsync_start = 800 + 40,
1434 	.hsync_end = 800 + 40 + 128,
1435 	.htotal = 800 + 40 + 128 + 88,
1436 	.vdisplay = 480,
1437 	.vsync_start = 480 + 10,
1438 	.vsync_end = 480 + 10 + 2,
1439 	.vtotal = 480 + 10 + 2 + 33,
1440 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1441 };
1442 
1443 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1444 	.modes = &dataimage_scf0700c48ggu18_mode,
1445 	.num_modes = 1,
1446 	.bpc = 8,
1447 	.size = {
1448 		.width = 152,
1449 		.height = 91,
1450 	},
1451 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1452 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1453 };
1454 
1455 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1456 	.pixelclock = { 45000000, 51200000, 57000000 },
1457 	.hactive = { 1024, 1024, 1024 },
1458 	.hfront_porch = { 100, 106, 113 },
1459 	.hback_porch = { 100, 106, 113 },
1460 	.hsync_len = { 100, 108, 114 },
1461 	.vactive = { 600, 600, 600 },
1462 	.vfront_porch = { 8, 11, 15 },
1463 	.vback_porch = { 8, 11, 15 },
1464 	.vsync_len = { 9, 13, 15 },
1465 	.flags = DISPLAY_FLAGS_DE_HIGH,
1466 };
1467 
1468 static const struct panel_desc dlc_dlc0700yzg_1 = {
1469 	.timings = &dlc_dlc0700yzg_1_timing,
1470 	.num_timings = 1,
1471 	.bpc = 6,
1472 	.size = {
1473 		.width = 154,
1474 		.height = 86,
1475 	},
1476 	.delay = {
1477 		.prepare = 30,
1478 		.enable = 200,
1479 		.disable = 200,
1480 	},
1481 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1482 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1483 };
1484 
1485 static const struct display_timing dlc_dlc1010gig_timing = {
1486 	.pixelclock = { 68900000, 71100000, 73400000 },
1487 	.hactive = { 1280, 1280, 1280 },
1488 	.hfront_porch = { 43, 53, 63 },
1489 	.hback_porch = { 43, 53, 63 },
1490 	.hsync_len = { 44, 54, 64 },
1491 	.vactive = { 800, 800, 800 },
1492 	.vfront_porch = { 5, 8, 11 },
1493 	.vback_porch = { 5, 8, 11 },
1494 	.vsync_len = { 5, 7, 11 },
1495 	.flags = DISPLAY_FLAGS_DE_HIGH,
1496 };
1497 
1498 static const struct panel_desc dlc_dlc1010gig = {
1499 	.timings = &dlc_dlc1010gig_timing,
1500 	.num_timings = 1,
1501 	.bpc = 8,
1502 	.size = {
1503 		.width = 216,
1504 		.height = 135,
1505 	},
1506 	.delay = {
1507 		.prepare = 60,
1508 		.enable = 150,
1509 		.disable = 100,
1510 		.unprepare = 60,
1511 	},
1512 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1513 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1514 };
1515 
1516 static const struct drm_display_mode edt_et035012dm6_mode = {
1517 	.clock = 6500,
1518 	.hdisplay = 320,
1519 	.hsync_start = 320 + 20,
1520 	.hsync_end = 320 + 20 + 30,
1521 	.htotal = 320 + 20 + 68,
1522 	.vdisplay = 240,
1523 	.vsync_start = 240 + 4,
1524 	.vsync_end = 240 + 4 + 4,
1525 	.vtotal = 240 + 4 + 4 + 14,
1526 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1527 };
1528 
1529 static const struct panel_desc edt_et035012dm6 = {
1530 	.modes = &edt_et035012dm6_mode,
1531 	.num_modes = 1,
1532 	.bpc = 8,
1533 	.size = {
1534 		.width = 70,
1535 		.height = 52,
1536 	},
1537 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1538 	.bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1539 };
1540 
1541 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1542 	.clock = 6520,
1543 	.hdisplay = 320,
1544 	.hsync_start = 320 + 20,
1545 	.hsync_end = 320 + 20 + 68,
1546 	.htotal = 320 + 20 + 68,
1547 	.vdisplay = 240,
1548 	.vsync_start = 240 + 4,
1549 	.vsync_end = 240 + 4 + 18,
1550 	.vtotal = 240 + 4 + 18,
1551 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1552 };
1553 
1554 static const struct panel_desc edt_etm0350g0dh6 = {
1555 	.modes = &edt_etm0350g0dh6_mode,
1556 	.num_modes = 1,
1557 	.bpc = 6,
1558 	.size = {
1559 		.width = 70,
1560 		.height = 53,
1561 	},
1562 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1563 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1564 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1565 };
1566 
1567 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1568 	.clock = 10870,
1569 	.hdisplay = 480,
1570 	.hsync_start = 480 + 8,
1571 	.hsync_end = 480 + 8 + 4,
1572 	.htotal = 480 + 8 + 4 + 41,
1573 
1574 	/*
1575 	 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1576 	 * fb_align
1577 	 */
1578 
1579 	.vdisplay = 288,
1580 	.vsync_start = 288 + 2,
1581 	.vsync_end = 288 + 2 + 4,
1582 	.vtotal = 288 + 2 + 4 + 10,
1583 };
1584 
1585 static const struct panel_desc edt_etm043080dh6gp = {
1586 	.modes = &edt_etm043080dh6gp_mode,
1587 	.num_modes = 1,
1588 	.bpc = 8,
1589 	.size = {
1590 		.width = 100,
1591 		.height = 65,
1592 	},
1593 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1594 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1595 };
1596 
1597 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1598 	.clock = 9000,
1599 	.hdisplay = 480,
1600 	.hsync_start = 480 + 2,
1601 	.hsync_end = 480 + 2 + 41,
1602 	.htotal = 480 + 2 + 41 + 2,
1603 	.vdisplay = 272,
1604 	.vsync_start = 272 + 2,
1605 	.vsync_end = 272 + 2 + 10,
1606 	.vtotal = 272 + 2 + 10 + 2,
1607 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1608 };
1609 
1610 static const struct panel_desc edt_etm0430g0dh6 = {
1611 	.modes = &edt_etm0430g0dh6_mode,
1612 	.num_modes = 1,
1613 	.bpc = 6,
1614 	.size = {
1615 		.width = 95,
1616 		.height = 54,
1617 	},
1618 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1619 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1620 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1621 };
1622 
1623 static const struct drm_display_mode edt_et057090dhu_mode = {
1624 	.clock = 25175,
1625 	.hdisplay = 640,
1626 	.hsync_start = 640 + 16,
1627 	.hsync_end = 640 + 16 + 30,
1628 	.htotal = 640 + 16 + 30 + 114,
1629 	.vdisplay = 480,
1630 	.vsync_start = 480 + 10,
1631 	.vsync_end = 480 + 10 + 3,
1632 	.vtotal = 480 + 10 + 3 + 32,
1633 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1634 };
1635 
1636 static const struct panel_desc edt_et057090dhu = {
1637 	.modes = &edt_et057090dhu_mode,
1638 	.num_modes = 1,
1639 	.bpc = 6,
1640 	.size = {
1641 		.width = 115,
1642 		.height = 86,
1643 	},
1644 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1645 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1646 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1647 };
1648 
1649 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1650 	.clock = 33260,
1651 	.hdisplay = 800,
1652 	.hsync_start = 800 + 40,
1653 	.hsync_end = 800 + 40 + 128,
1654 	.htotal = 800 + 40 + 128 + 88,
1655 	.vdisplay = 480,
1656 	.vsync_start = 480 + 10,
1657 	.vsync_end = 480 + 10 + 2,
1658 	.vtotal = 480 + 10 + 2 + 33,
1659 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1660 };
1661 
1662 static const struct panel_desc edt_etm0700g0dh6 = {
1663 	.modes = &edt_etm0700g0dh6_mode,
1664 	.num_modes = 1,
1665 	.bpc = 6,
1666 	.size = {
1667 		.width = 152,
1668 		.height = 91,
1669 	},
1670 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1671 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1672 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1673 };
1674 
1675 static const struct panel_desc edt_etm0700g0bdh6 = {
1676 	.modes = &edt_etm0700g0dh6_mode,
1677 	.num_modes = 1,
1678 	.bpc = 6,
1679 	.size = {
1680 		.width = 152,
1681 		.height = 91,
1682 	},
1683 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1684 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1685 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1686 };
1687 
1688 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
1689 	.clock = 25175,
1690 	.hdisplay = 640,
1691 	.hsync_start = 640,
1692 	.hsync_end = 640 + 16,
1693 	.htotal = 640 + 16 + 30 + 114,
1694 	.vdisplay = 480,
1695 	.vsync_start = 480 + 10,
1696 	.vsync_end = 480 + 10 + 3,
1697 	.vtotal = 480 + 10 + 3 + 35,
1698 	.flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
1699 };
1700 
1701 static const struct panel_desc edt_etmv570g2dhu = {
1702 	.modes = &edt_etmv570g2dhu_mode,
1703 	.num_modes = 1,
1704 	.bpc = 6,
1705 	.size = {
1706 		.width = 115,
1707 		.height = 86,
1708 	},
1709 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1710 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1711 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1712 };
1713 
1714 static const struct display_timing eink_vb3300_kca_timing = {
1715 	.pixelclock = { 40000000, 40000000, 40000000 },
1716 	.hactive = { 334, 334, 334 },
1717 	.hfront_porch = { 1, 1, 1 },
1718 	.hback_porch = { 1, 1, 1 },
1719 	.hsync_len = { 1, 1, 1 },
1720 	.vactive = { 1405, 1405, 1405 },
1721 	.vfront_porch = { 1, 1, 1 },
1722 	.vback_porch = { 1, 1, 1 },
1723 	.vsync_len = { 1, 1, 1 },
1724 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1725 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
1726 };
1727 
1728 static const struct panel_desc eink_vb3300_kca = {
1729 	.timings = &eink_vb3300_kca_timing,
1730 	.num_timings = 1,
1731 	.bpc = 6,
1732 	.size = {
1733 		.width = 157,
1734 		.height = 209,
1735 	},
1736 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1737 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1738 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1739 };
1740 
1741 static const struct display_timing evervision_vgg804821_timing = {
1742 	.pixelclock = { 27600000, 33300000, 50000000 },
1743 	.hactive = { 800, 800, 800 },
1744 	.hfront_porch = { 40, 66, 70 },
1745 	.hback_porch = { 40, 67, 70 },
1746 	.hsync_len = { 40, 67, 70 },
1747 	.vactive = { 480, 480, 480 },
1748 	.vfront_porch = { 6, 10, 10 },
1749 	.vback_porch = { 7, 11, 11 },
1750 	.vsync_len = { 7, 11, 11 },
1751 	.flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1752 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1753 		 DISPLAY_FLAGS_SYNC_NEGEDGE,
1754 };
1755 
1756 static const struct panel_desc evervision_vgg804821 = {
1757 	.timings = &evervision_vgg804821_timing,
1758 	.num_timings = 1,
1759 	.bpc = 8,
1760 	.size = {
1761 		.width = 108,
1762 		.height = 64,
1763 	},
1764 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1765 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1766 };
1767 
1768 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1769 	.clock = 32260,
1770 	.hdisplay = 800,
1771 	.hsync_start = 800 + 168,
1772 	.hsync_end = 800 + 168 + 64,
1773 	.htotal = 800 + 168 + 64 + 88,
1774 	.vdisplay = 480,
1775 	.vsync_start = 480 + 37,
1776 	.vsync_end = 480 + 37 + 2,
1777 	.vtotal = 480 + 37 + 2 + 8,
1778 };
1779 
1780 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1781 	.modes = &foxlink_fl500wvr00_a0t_mode,
1782 	.num_modes = 1,
1783 	.bpc = 8,
1784 	.size = {
1785 		.width = 108,
1786 		.height = 65,
1787 	},
1788 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1789 };
1790 
1791 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1792 	{ /* 60 Hz */
1793 		.clock = 6000,
1794 		.hdisplay = 320,
1795 		.hsync_start = 320 + 44,
1796 		.hsync_end = 320 + 44 + 16,
1797 		.htotal = 320 + 44 + 16 + 20,
1798 		.vdisplay = 240,
1799 		.vsync_start = 240 + 2,
1800 		.vsync_end = 240 + 2 + 6,
1801 		.vtotal = 240 + 2 + 6 + 2,
1802 		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1803 	},
1804 	{ /* 50 Hz */
1805 		.clock = 5400,
1806 		.hdisplay = 320,
1807 		.hsync_start = 320 + 56,
1808 		.hsync_end = 320 + 56 + 16,
1809 		.htotal = 320 + 56 + 16 + 40,
1810 		.vdisplay = 240,
1811 		.vsync_start = 240 + 2,
1812 		.vsync_end = 240 + 2 + 6,
1813 		.vtotal = 240 + 2 + 6 + 2,
1814 		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1815 	},
1816 };
1817 
1818 static const struct panel_desc frida_frd350h54004 = {
1819 	.modes = frida_frd350h54004_modes,
1820 	.num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
1821 	.bpc = 8,
1822 	.size = {
1823 		.width = 77,
1824 		.height = 64,
1825 	},
1826 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1827 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1828 	.connector_type = DRM_MODE_CONNECTOR_DPI,
1829 };
1830 
1831 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1832 	.clock		= 67185,
1833 	.hdisplay	= 800,
1834 	.hsync_start	= 800 + 20,
1835 	.hsync_end	= 800 + 20 + 24,
1836 	.htotal		= 800 + 20 + 24 + 20,
1837 	.vdisplay	= 1280,
1838 	.vsync_start	= 1280 + 4,
1839 	.vsync_end	= 1280 + 4 + 8,
1840 	.vtotal		= 1280 + 4 + 8 + 4,
1841 	.flags		= DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1842 };
1843 
1844 static const struct panel_desc friendlyarm_hd702e = {
1845 	.modes = &friendlyarm_hd702e_mode,
1846 	.num_modes = 1,
1847 	.size = {
1848 		.width	= 94,
1849 		.height	= 151,
1850 	},
1851 };
1852 
1853 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1854 	.clock = 9000,
1855 	.hdisplay = 480,
1856 	.hsync_start = 480 + 5,
1857 	.hsync_end = 480 + 5 + 1,
1858 	.htotal = 480 + 5 + 1 + 40,
1859 	.vdisplay = 272,
1860 	.vsync_start = 272 + 8,
1861 	.vsync_end = 272 + 8 + 1,
1862 	.vtotal = 272 + 8 + 1 + 8,
1863 };
1864 
1865 static const struct panel_desc giantplus_gpg482739qs5 = {
1866 	.modes = &giantplus_gpg482739qs5_mode,
1867 	.num_modes = 1,
1868 	.bpc = 8,
1869 	.size = {
1870 		.width = 95,
1871 		.height = 54,
1872 	},
1873 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1874 };
1875 
1876 static const struct display_timing giantplus_gpm940b0_timing = {
1877 	.pixelclock = { 13500000, 27000000, 27500000 },
1878 	.hactive = { 320, 320, 320 },
1879 	.hfront_porch = { 14, 686, 718 },
1880 	.hback_porch = { 50, 70, 255 },
1881 	.hsync_len = { 1, 1, 1 },
1882 	.vactive = { 240, 240, 240 },
1883 	.vfront_porch = { 1, 1, 179 },
1884 	.vback_porch = { 1, 21, 31 },
1885 	.vsync_len = { 1, 1, 6 },
1886 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1887 };
1888 
1889 static const struct panel_desc giantplus_gpm940b0 = {
1890 	.timings = &giantplus_gpm940b0_timing,
1891 	.num_timings = 1,
1892 	.bpc = 8,
1893 	.size = {
1894 		.width = 60,
1895 		.height = 45,
1896 	},
1897 	.bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1898 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1899 };
1900 
1901 static const struct display_timing hannstar_hsd070pww1_timing = {
1902 	.pixelclock = { 64300000, 71100000, 82000000 },
1903 	.hactive = { 1280, 1280, 1280 },
1904 	.hfront_porch = { 1, 1, 10 },
1905 	.hback_porch = { 1, 1, 10 },
1906 	/*
1907 	 * According to the data sheet, the minimum horizontal blanking interval
1908 	 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1909 	 * minimum working horizontal blanking interval to be 60 clocks.
1910 	 */
1911 	.hsync_len = { 58, 158, 661 },
1912 	.vactive = { 800, 800, 800 },
1913 	.vfront_porch = { 1, 1, 10 },
1914 	.vback_porch = { 1, 1, 10 },
1915 	.vsync_len = { 1, 21, 203 },
1916 	.flags = DISPLAY_FLAGS_DE_HIGH,
1917 };
1918 
1919 static const struct panel_desc hannstar_hsd070pww1 = {
1920 	.timings = &hannstar_hsd070pww1_timing,
1921 	.num_timings = 1,
1922 	.bpc = 6,
1923 	.size = {
1924 		.width = 151,
1925 		.height = 94,
1926 	},
1927 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1928 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1929 };
1930 
1931 static const struct display_timing hannstar_hsd100pxn1_timing = {
1932 	.pixelclock = { 55000000, 65000000, 75000000 },
1933 	.hactive = { 1024, 1024, 1024 },
1934 	.hfront_porch = { 40, 40, 40 },
1935 	.hback_porch = { 220, 220, 220 },
1936 	.hsync_len = { 20, 60, 100 },
1937 	.vactive = { 768, 768, 768 },
1938 	.vfront_porch = { 7, 7, 7 },
1939 	.vback_porch = { 21, 21, 21 },
1940 	.vsync_len = { 10, 10, 10 },
1941 	.flags = DISPLAY_FLAGS_DE_HIGH,
1942 };
1943 
1944 static const struct panel_desc hannstar_hsd100pxn1 = {
1945 	.timings = &hannstar_hsd100pxn1_timing,
1946 	.num_timings = 1,
1947 	.bpc = 6,
1948 	.size = {
1949 		.width = 203,
1950 		.height = 152,
1951 	},
1952 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1953 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
1954 };
1955 
1956 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1957 	.clock = 33333,
1958 	.hdisplay = 800,
1959 	.hsync_start = 800 + 85,
1960 	.hsync_end = 800 + 85 + 86,
1961 	.htotal = 800 + 85 + 86 + 85,
1962 	.vdisplay = 480,
1963 	.vsync_start = 480 + 16,
1964 	.vsync_end = 480 + 16 + 13,
1965 	.vtotal = 480 + 16 + 13 + 16,
1966 };
1967 
1968 static const struct panel_desc hitachi_tx23d38vm0caa = {
1969 	.modes = &hitachi_tx23d38vm0caa_mode,
1970 	.num_modes = 1,
1971 	.bpc = 6,
1972 	.size = {
1973 		.width = 195,
1974 		.height = 117,
1975 	},
1976 	.delay = {
1977 		.enable = 160,
1978 		.disable = 160,
1979 	},
1980 };
1981 
1982 static const struct drm_display_mode innolux_at043tn24_mode = {
1983 	.clock = 9000,
1984 	.hdisplay = 480,
1985 	.hsync_start = 480 + 2,
1986 	.hsync_end = 480 + 2 + 41,
1987 	.htotal = 480 + 2 + 41 + 2,
1988 	.vdisplay = 272,
1989 	.vsync_start = 272 + 2,
1990 	.vsync_end = 272 + 2 + 10,
1991 	.vtotal = 272 + 2 + 10 + 2,
1992 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1993 };
1994 
1995 static const struct panel_desc innolux_at043tn24 = {
1996 	.modes = &innolux_at043tn24_mode,
1997 	.num_modes = 1,
1998 	.bpc = 8,
1999 	.size = {
2000 		.width = 95,
2001 		.height = 54,
2002 	},
2003 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2004 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2005 };
2006 
2007 static const struct drm_display_mode innolux_at070tn92_mode = {
2008 	.clock = 33333,
2009 	.hdisplay = 800,
2010 	.hsync_start = 800 + 210,
2011 	.hsync_end = 800 + 210 + 20,
2012 	.htotal = 800 + 210 + 20 + 46,
2013 	.vdisplay = 480,
2014 	.vsync_start = 480 + 22,
2015 	.vsync_end = 480 + 22 + 10,
2016 	.vtotal = 480 + 22 + 23 + 10,
2017 };
2018 
2019 static const struct panel_desc innolux_at070tn92 = {
2020 	.modes = &innolux_at070tn92_mode,
2021 	.num_modes = 1,
2022 	.size = {
2023 		.width = 154,
2024 		.height = 86,
2025 	},
2026 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2027 };
2028 
2029 static const struct display_timing innolux_g070y2_l01_timing = {
2030 	.pixelclock = { 28000000, 29500000, 32000000 },
2031 	.hactive = { 800, 800, 800 },
2032 	.hfront_porch = { 61, 91, 141 },
2033 	.hback_porch = { 60, 90, 140 },
2034 	.hsync_len = { 12, 12, 12 },
2035 	.vactive = { 480, 480, 480 },
2036 	.vfront_porch = { 4, 9, 30 },
2037 	.vback_porch = { 4, 8, 28 },
2038 	.vsync_len = { 2, 2, 2 },
2039 	.flags = DISPLAY_FLAGS_DE_HIGH,
2040 };
2041 
2042 static const struct panel_desc innolux_g070y2_l01 = {
2043 	.timings = &innolux_g070y2_l01_timing,
2044 	.num_timings = 1,
2045 	.bpc = 8,
2046 	.size = {
2047 		.width = 152,
2048 		.height = 91,
2049 	},
2050 	.delay = {
2051 		.prepare = 10,
2052 		.enable = 100,
2053 		.disable = 100,
2054 		.unprepare = 800,
2055 	},
2056 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2057 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2058 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2059 };
2060 
2061 static const struct drm_display_mode innolux_g070y2_t02_mode = {
2062 	.clock = 33333,
2063 	.hdisplay = 800,
2064 	.hsync_start = 800 + 210,
2065 	.hsync_end = 800 + 210 + 20,
2066 	.htotal = 800 + 210 + 20 + 46,
2067 	.vdisplay = 480,
2068 	.vsync_start = 480 + 22,
2069 	.vsync_end = 480 + 22 + 10,
2070 	.vtotal = 480 + 22 + 23 + 10,
2071 };
2072 
2073 static const struct panel_desc innolux_g070y2_t02 = {
2074 	.modes = &innolux_g070y2_t02_mode,
2075 	.num_modes = 1,
2076 	.bpc = 8,
2077 	.size = {
2078 		.width = 152,
2079 		.height = 92,
2080 	},
2081 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2082 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2083 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2084 };
2085 
2086 static const struct display_timing innolux_g101ice_l01_timing = {
2087 	.pixelclock = { 60400000, 71100000, 74700000 },
2088 	.hactive = { 1280, 1280, 1280 },
2089 	.hfront_porch = { 41, 80, 100 },
2090 	.hback_porch = { 40, 79, 99 },
2091 	.hsync_len = { 1, 1, 1 },
2092 	.vactive = { 800, 800, 800 },
2093 	.vfront_porch = { 5, 11, 14 },
2094 	.vback_porch = { 4, 11, 14 },
2095 	.vsync_len = { 1, 1, 1 },
2096 	.flags = DISPLAY_FLAGS_DE_HIGH,
2097 };
2098 
2099 static const struct panel_desc innolux_g101ice_l01 = {
2100 	.timings = &innolux_g101ice_l01_timing,
2101 	.num_timings = 1,
2102 	.bpc = 8,
2103 	.size = {
2104 		.width = 217,
2105 		.height = 135,
2106 	},
2107 	.delay = {
2108 		.enable = 200,
2109 		.disable = 200,
2110 	},
2111 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2112 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2113 };
2114 
2115 static const struct display_timing innolux_g121i1_l01_timing = {
2116 	.pixelclock = { 67450000, 71000000, 74550000 },
2117 	.hactive = { 1280, 1280, 1280 },
2118 	.hfront_porch = { 40, 80, 160 },
2119 	.hback_porch = { 39, 79, 159 },
2120 	.hsync_len = { 1, 1, 1 },
2121 	.vactive = { 800, 800, 800 },
2122 	.vfront_porch = { 5, 11, 100 },
2123 	.vback_porch = { 4, 11, 99 },
2124 	.vsync_len = { 1, 1, 1 },
2125 };
2126 
2127 static const struct panel_desc innolux_g121i1_l01 = {
2128 	.timings = &innolux_g121i1_l01_timing,
2129 	.num_timings = 1,
2130 	.bpc = 6,
2131 	.size = {
2132 		.width = 261,
2133 		.height = 163,
2134 	},
2135 	.delay = {
2136 		.enable = 200,
2137 		.disable = 20,
2138 	},
2139 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2140 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2141 };
2142 
2143 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2144 	.clock = 65000,
2145 	.hdisplay = 1024,
2146 	.hsync_start = 1024 + 0,
2147 	.hsync_end = 1024 + 1,
2148 	.htotal = 1024 + 0 + 1 + 320,
2149 	.vdisplay = 768,
2150 	.vsync_start = 768 + 38,
2151 	.vsync_end = 768 + 38 + 1,
2152 	.vtotal = 768 + 38 + 1 + 0,
2153 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2154 };
2155 
2156 static const struct panel_desc innolux_g121x1_l03 = {
2157 	.modes = &innolux_g121x1_l03_mode,
2158 	.num_modes = 1,
2159 	.bpc = 6,
2160 	.size = {
2161 		.width = 246,
2162 		.height = 185,
2163 	},
2164 	.delay = {
2165 		.enable = 200,
2166 		.unprepare = 200,
2167 		.disable = 400,
2168 	},
2169 };
2170 
2171 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2172 	.clock = 69300,
2173 	.hdisplay = 1366,
2174 	.hsync_start = 1366 + 16,
2175 	.hsync_end = 1366 + 16 + 34,
2176 	.htotal = 1366 + 16 + 34 + 50,
2177 	.vdisplay = 768,
2178 	.vsync_start = 768 + 2,
2179 	.vsync_end = 768 + 2 + 6,
2180 	.vtotal = 768 + 2 + 6 + 12,
2181 };
2182 
2183 static const struct panel_desc innolux_n156bge_l21 = {
2184 	.modes = &innolux_n156bge_l21_mode,
2185 	.num_modes = 1,
2186 	.bpc = 6,
2187 	.size = {
2188 		.width = 344,
2189 		.height = 193,
2190 	},
2191 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2192 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2193 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2194 };
2195 
2196 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2197 	.clock = 51501,
2198 	.hdisplay = 1024,
2199 	.hsync_start = 1024 + 128,
2200 	.hsync_end = 1024 + 128 + 64,
2201 	.htotal = 1024 + 128 + 64 + 128,
2202 	.vdisplay = 600,
2203 	.vsync_start = 600 + 16,
2204 	.vsync_end = 600 + 16 + 4,
2205 	.vtotal = 600 + 16 + 4 + 16,
2206 };
2207 
2208 static const struct panel_desc innolux_zj070na_01p = {
2209 	.modes = &innolux_zj070na_01p_mode,
2210 	.num_modes = 1,
2211 	.bpc = 6,
2212 	.size = {
2213 		.width = 154,
2214 		.height = 90,
2215 	},
2216 };
2217 
2218 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2219 	.pixelclock = { 5580000, 5850000, 6200000 },
2220 	.hactive = { 320, 320, 320 },
2221 	.hfront_porch = { 30, 30, 30 },
2222 	.hback_porch = { 30, 30, 30 },
2223 	.hsync_len = { 1, 5, 17 },
2224 	.vactive = { 240, 240, 240 },
2225 	.vfront_porch = { 6, 6, 6 },
2226 	.vback_porch = { 5, 5, 5 },
2227 	.vsync_len = { 1, 2, 11 },
2228 	.flags = DISPLAY_FLAGS_DE_HIGH,
2229 };
2230 
2231 static const struct panel_desc koe_tx14d24vm1bpa = {
2232 	.timings = &koe_tx14d24vm1bpa_timing,
2233 	.num_timings = 1,
2234 	.bpc = 6,
2235 	.size = {
2236 		.width = 115,
2237 		.height = 86,
2238 	},
2239 };
2240 
2241 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2242 	.pixelclock = { 151820000, 156720000, 159780000 },
2243 	.hactive = { 1920, 1920, 1920 },
2244 	.hfront_porch = { 105, 130, 142 },
2245 	.hback_porch = { 45, 70, 82 },
2246 	.hsync_len = { 30, 30, 30 },
2247 	.vactive = { 1200, 1200, 1200},
2248 	.vfront_porch = { 3, 5, 10 },
2249 	.vback_porch = { 2, 5, 10 },
2250 	.vsync_len = { 5, 5, 5 },
2251 };
2252 
2253 static const struct panel_desc koe_tx26d202vm0bwa = {
2254 	.timings = &koe_tx26d202vm0bwa_timing,
2255 	.num_timings = 1,
2256 	.bpc = 8,
2257 	.size = {
2258 		.width = 217,
2259 		.height = 136,
2260 	},
2261 	.delay = {
2262 		.prepare = 1000,
2263 		.enable = 1000,
2264 		.unprepare = 1000,
2265 		.disable = 1000,
2266 	},
2267 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2268 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2269 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2270 };
2271 
2272 static const struct display_timing koe_tx31d200vm0baa_timing = {
2273 	.pixelclock = { 39600000, 43200000, 48000000 },
2274 	.hactive = { 1280, 1280, 1280 },
2275 	.hfront_porch = { 16, 36, 56 },
2276 	.hback_porch = { 16, 36, 56 },
2277 	.hsync_len = { 8, 8, 8 },
2278 	.vactive = { 480, 480, 480 },
2279 	.vfront_porch = { 6, 21, 33 },
2280 	.vback_porch = { 6, 21, 33 },
2281 	.vsync_len = { 8, 8, 8 },
2282 	.flags = DISPLAY_FLAGS_DE_HIGH,
2283 };
2284 
2285 static const struct panel_desc koe_tx31d200vm0baa = {
2286 	.timings = &koe_tx31d200vm0baa_timing,
2287 	.num_timings = 1,
2288 	.bpc = 6,
2289 	.size = {
2290 		.width = 292,
2291 		.height = 109,
2292 	},
2293 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2294 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2295 };
2296 
2297 static const struct display_timing kyo_tcg121xglp_timing = {
2298 	.pixelclock = { 52000000, 65000000, 71000000 },
2299 	.hactive = { 1024, 1024, 1024 },
2300 	.hfront_porch = { 2, 2, 2 },
2301 	.hback_porch = { 2, 2, 2 },
2302 	.hsync_len = { 86, 124, 244 },
2303 	.vactive = { 768, 768, 768 },
2304 	.vfront_porch = { 2, 2, 2 },
2305 	.vback_porch = { 2, 2, 2 },
2306 	.vsync_len = { 6, 34, 73 },
2307 	.flags = DISPLAY_FLAGS_DE_HIGH,
2308 };
2309 
2310 static const struct panel_desc kyo_tcg121xglp = {
2311 	.timings = &kyo_tcg121xglp_timing,
2312 	.num_timings = 1,
2313 	.bpc = 8,
2314 	.size = {
2315 		.width = 246,
2316 		.height = 184,
2317 	},
2318 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2319 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2320 };
2321 
2322 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2323 	.clock = 7000,
2324 	.hdisplay = 320,
2325 	.hsync_start = 320 + 20,
2326 	.hsync_end = 320 + 20 + 30,
2327 	.htotal = 320 + 20 + 30 + 38,
2328 	.vdisplay = 240,
2329 	.vsync_start = 240 + 4,
2330 	.vsync_end = 240 + 4 + 3,
2331 	.vtotal = 240 + 4 + 3 + 15,
2332 };
2333 
2334 static const struct panel_desc lemaker_bl035_rgb_002 = {
2335 	.modes = &lemaker_bl035_rgb_002_mode,
2336 	.num_modes = 1,
2337 	.size = {
2338 		.width = 70,
2339 		.height = 52,
2340 	},
2341 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2342 	.bus_flags = DRM_BUS_FLAG_DE_LOW,
2343 };
2344 
2345 static const struct drm_display_mode lg_lb070wv8_mode = {
2346 	.clock = 33246,
2347 	.hdisplay = 800,
2348 	.hsync_start = 800 + 88,
2349 	.hsync_end = 800 + 88 + 80,
2350 	.htotal = 800 + 88 + 80 + 88,
2351 	.vdisplay = 480,
2352 	.vsync_start = 480 + 10,
2353 	.vsync_end = 480 + 10 + 25,
2354 	.vtotal = 480 + 10 + 25 + 10,
2355 };
2356 
2357 static const struct panel_desc lg_lb070wv8 = {
2358 	.modes = &lg_lb070wv8_mode,
2359 	.num_modes = 1,
2360 	.bpc = 8,
2361 	.size = {
2362 		.width = 151,
2363 		.height = 91,
2364 	},
2365 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2366 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2367 };
2368 
2369 static const struct display_timing logictechno_lt161010_2nh_timing = {
2370 	.pixelclock = { 26400000, 33300000, 46800000 },
2371 	.hactive = { 800, 800, 800 },
2372 	.hfront_porch = { 16, 210, 354 },
2373 	.hback_porch = { 46, 46, 46 },
2374 	.hsync_len = { 1, 20, 40 },
2375 	.vactive = { 480, 480, 480 },
2376 	.vfront_porch = { 7, 22, 147 },
2377 	.vback_porch = { 23, 23, 23 },
2378 	.vsync_len = { 1, 10, 20 },
2379 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2380 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2381 		 DISPLAY_FLAGS_SYNC_POSEDGE,
2382 };
2383 
2384 static const struct panel_desc logictechno_lt161010_2nh = {
2385 	.timings = &logictechno_lt161010_2nh_timing,
2386 	.num_timings = 1,
2387 	.size = {
2388 		.width = 154,
2389 		.height = 86,
2390 	},
2391 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2392 	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
2393 		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2394 		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2395 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2396 };
2397 
2398 static const struct display_timing logictechno_lt170410_2whc_timing = {
2399 	.pixelclock = { 68900000, 71100000, 73400000 },
2400 	.hactive = { 1280, 1280, 1280 },
2401 	.hfront_porch = { 23, 60, 71 },
2402 	.hback_porch = { 23, 60, 71 },
2403 	.hsync_len = { 15, 40, 47 },
2404 	.vactive = { 800, 800, 800 },
2405 	.vfront_porch = { 5, 7, 10 },
2406 	.vback_porch = { 5, 7, 10 },
2407 	.vsync_len = { 6, 9, 12 },
2408 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2409 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2410 		 DISPLAY_FLAGS_SYNC_POSEDGE,
2411 };
2412 
2413 static const struct panel_desc logictechno_lt170410_2whc = {
2414 	.timings = &logictechno_lt170410_2whc_timing,
2415 	.num_timings = 1,
2416 	.size = {
2417 		.width = 217,
2418 		.height = 136,
2419 	},
2420 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2421 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2422 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2423 };
2424 
2425 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
2426 	.clock = 33000,
2427 	.hdisplay = 800,
2428 	.hsync_start = 800 + 112,
2429 	.hsync_end = 800 + 112 + 3,
2430 	.htotal = 800 + 112 + 3 + 85,
2431 	.vdisplay = 480,
2432 	.vsync_start = 480 + 38,
2433 	.vsync_end = 480 + 38 + 3,
2434 	.vtotal = 480 + 38 + 3 + 29,
2435 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2436 };
2437 
2438 static const struct panel_desc logictechno_lttd800480070_l2rt = {
2439 	.modes = &logictechno_lttd800480070_l2rt_mode,
2440 	.num_modes = 1,
2441 	.bpc = 8,
2442 	.size = {
2443 		.width = 154,
2444 		.height = 86,
2445 	},
2446 	.delay = {
2447 		.prepare = 45,
2448 		.enable = 100,
2449 		.disable = 100,
2450 		.unprepare = 45
2451 	},
2452 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2453 	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2454 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2455 };
2456 
2457 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
2458 	.clock = 33000,
2459 	.hdisplay = 800,
2460 	.hsync_start = 800 + 154,
2461 	.hsync_end = 800 + 154 + 3,
2462 	.htotal = 800 + 154 + 3 + 43,
2463 	.vdisplay = 480,
2464 	.vsync_start = 480 + 47,
2465 	.vsync_end = 480 + 47 + 3,
2466 	.vtotal = 480 + 47 + 3 + 20,
2467 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2468 };
2469 
2470 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
2471 	.modes = &logictechno_lttd800480070_l6wh_rt_mode,
2472 	.num_modes = 1,
2473 	.bpc = 8,
2474 	.size = {
2475 		.width = 154,
2476 		.height = 86,
2477 	},
2478 	.delay = {
2479 		.prepare = 45,
2480 		.enable = 100,
2481 		.disable = 100,
2482 		.unprepare = 45
2483 	},
2484 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2485 	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2486 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2487 };
2488 
2489 static const struct drm_display_mode logicpd_type_28_mode = {
2490 	.clock = 9107,
2491 	.hdisplay = 480,
2492 	.hsync_start = 480 + 3,
2493 	.hsync_end = 480 + 3 + 42,
2494 	.htotal = 480 + 3 + 42 + 2,
2495 
2496 	.vdisplay = 272,
2497 	.vsync_start = 272 + 2,
2498 	.vsync_end = 272 + 2 + 11,
2499 	.vtotal = 272 + 2 + 11 + 3,
2500 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2501 };
2502 
2503 static const struct panel_desc logicpd_type_28 = {
2504 	.modes = &logicpd_type_28_mode,
2505 	.num_modes = 1,
2506 	.bpc = 8,
2507 	.size = {
2508 		.width = 105,
2509 		.height = 67,
2510 	},
2511 	.delay = {
2512 		.prepare = 200,
2513 		.enable = 200,
2514 		.unprepare = 200,
2515 		.disable = 200,
2516 	},
2517 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2518 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2519 		     DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2520 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2521 };
2522 
2523 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2524 	.clock = 30400,
2525 	.hdisplay = 800,
2526 	.hsync_start = 800 + 0,
2527 	.hsync_end = 800 + 1,
2528 	.htotal = 800 + 0 + 1 + 160,
2529 	.vdisplay = 480,
2530 	.vsync_start = 480 + 0,
2531 	.vsync_end = 480 + 48 + 1,
2532 	.vtotal = 480 + 48 + 1 + 0,
2533 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2534 };
2535 
2536 static const struct panel_desc mitsubishi_aa070mc01 = {
2537 	.modes = &mitsubishi_aa070mc01_mode,
2538 	.num_modes = 1,
2539 	.bpc = 8,
2540 	.size = {
2541 		.width = 152,
2542 		.height = 91,
2543 	},
2544 
2545 	.delay = {
2546 		.enable = 200,
2547 		.unprepare = 200,
2548 		.disable = 400,
2549 	},
2550 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2551 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2552 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2553 };
2554 
2555 static const struct display_timing multi_inno_mi0700s4t_6_timing = {
2556 	.pixelclock = { 29000000, 33000000, 38000000 },
2557 	.hactive = { 800, 800, 800 },
2558 	.hfront_porch = { 180, 210, 240 },
2559 	.hback_porch = { 16, 16, 16 },
2560 	.hsync_len = { 30, 30, 30 },
2561 	.vactive = { 480, 480, 480 },
2562 	.vfront_porch = { 12, 22, 32 },
2563 	.vback_porch = { 10, 10, 10 },
2564 	.vsync_len = { 13, 13, 13 },
2565 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2566 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2567 		 DISPLAY_FLAGS_SYNC_POSEDGE,
2568 };
2569 
2570 static const struct panel_desc multi_inno_mi0700s4t_6 = {
2571 	.timings = &multi_inno_mi0700s4t_6_timing,
2572 	.num_timings = 1,
2573 	.bpc = 8,
2574 	.size = {
2575 		.width = 154,
2576 		.height = 86,
2577 	},
2578 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2579 	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
2580 		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2581 		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2582 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2583 };
2584 
2585 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
2586 	.pixelclock = { 68900000, 70000000, 73400000 },
2587 	.hactive = { 1280, 1280, 1280 },
2588 	.hfront_porch = { 30, 60, 71 },
2589 	.hback_porch = { 30, 60, 71 },
2590 	.hsync_len = { 10, 10, 48 },
2591 	.vactive = { 800, 800, 800 },
2592 	.vfront_porch = { 5, 10, 10 },
2593 	.vback_porch = { 5, 10, 10 },
2594 	.vsync_len = { 5, 6, 13 },
2595 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2596 		 DISPLAY_FLAGS_DE_HIGH,
2597 };
2598 
2599 static const struct panel_desc multi_inno_mi1010ait_1cp = {
2600 	.timings = &multi_inno_mi1010ait_1cp_timing,
2601 	.num_timings = 1,
2602 	.bpc = 8,
2603 	.size = {
2604 		.width = 217,
2605 		.height = 136,
2606 	},
2607 	.delay = {
2608 		.enable = 50,
2609 		.disable = 50,
2610 	},
2611 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2612 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
2613 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2614 };
2615 
2616 static const struct display_timing nec_nl12880bc20_05_timing = {
2617 	.pixelclock = { 67000000, 71000000, 75000000 },
2618 	.hactive = { 1280, 1280, 1280 },
2619 	.hfront_porch = { 2, 30, 30 },
2620 	.hback_porch = { 6, 100, 100 },
2621 	.hsync_len = { 2, 30, 30 },
2622 	.vactive = { 800, 800, 800 },
2623 	.vfront_porch = { 5, 5, 5 },
2624 	.vback_porch = { 11, 11, 11 },
2625 	.vsync_len = { 7, 7, 7 },
2626 };
2627 
2628 static const struct panel_desc nec_nl12880bc20_05 = {
2629 	.timings = &nec_nl12880bc20_05_timing,
2630 	.num_timings = 1,
2631 	.bpc = 8,
2632 	.size = {
2633 		.width = 261,
2634 		.height = 163,
2635 	},
2636 	.delay = {
2637 		.enable = 50,
2638 		.disable = 50,
2639 	},
2640 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2641 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2642 };
2643 
2644 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2645 	.clock = 10870,
2646 	.hdisplay = 480,
2647 	.hsync_start = 480 + 2,
2648 	.hsync_end = 480 + 2 + 41,
2649 	.htotal = 480 + 2 + 41 + 2,
2650 	.vdisplay = 272,
2651 	.vsync_start = 272 + 2,
2652 	.vsync_end = 272 + 2 + 4,
2653 	.vtotal = 272 + 2 + 4 + 2,
2654 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2655 };
2656 
2657 static const struct panel_desc nec_nl4827hc19_05b = {
2658 	.modes = &nec_nl4827hc19_05b_mode,
2659 	.num_modes = 1,
2660 	.bpc = 8,
2661 	.size = {
2662 		.width = 95,
2663 		.height = 54,
2664 	},
2665 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2666 	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2667 };
2668 
2669 static const struct drm_display_mode netron_dy_e231732_mode = {
2670 	.clock = 66000,
2671 	.hdisplay = 1024,
2672 	.hsync_start = 1024 + 160,
2673 	.hsync_end = 1024 + 160 + 70,
2674 	.htotal = 1024 + 160 + 70 + 90,
2675 	.vdisplay = 600,
2676 	.vsync_start = 600 + 127,
2677 	.vsync_end = 600 + 127 + 20,
2678 	.vtotal = 600 + 127 + 20 + 3,
2679 };
2680 
2681 static const struct panel_desc netron_dy_e231732 = {
2682 	.modes = &netron_dy_e231732_mode,
2683 	.num_modes = 1,
2684 	.size = {
2685 		.width = 154,
2686 		.height = 87,
2687 	},
2688 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2689 };
2690 
2691 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2692 	.clock = 9000,
2693 	.hdisplay = 480,
2694 	.hsync_start = 480 + 2,
2695 	.hsync_end = 480 + 2 + 41,
2696 	.htotal = 480 + 2 + 41 + 2,
2697 	.vdisplay = 272,
2698 	.vsync_start = 272 + 2,
2699 	.vsync_end = 272 + 2 + 10,
2700 	.vtotal = 272 + 2 + 10 + 2,
2701 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2702 };
2703 
2704 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2705 	.modes = &newhaven_nhd_43_480272ef_atxl_mode,
2706 	.num_modes = 1,
2707 	.bpc = 8,
2708 	.size = {
2709 		.width = 95,
2710 		.height = 54,
2711 	},
2712 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2713 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2714 		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2715 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2716 };
2717 
2718 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2719 	.pixelclock = { 130000000, 148350000, 163000000 },
2720 	.hactive = { 1920, 1920, 1920 },
2721 	.hfront_porch = { 80, 100, 100 },
2722 	.hback_porch = { 100, 120, 120 },
2723 	.hsync_len = { 50, 60, 60 },
2724 	.vactive = { 1080, 1080, 1080 },
2725 	.vfront_porch = { 12, 30, 30 },
2726 	.vback_porch = { 4, 10, 10 },
2727 	.vsync_len = { 4, 5, 5 },
2728 };
2729 
2730 static const struct panel_desc nlt_nl192108ac18_02d = {
2731 	.timings = &nlt_nl192108ac18_02d_timing,
2732 	.num_timings = 1,
2733 	.bpc = 8,
2734 	.size = {
2735 		.width = 344,
2736 		.height = 194,
2737 	},
2738 	.delay = {
2739 		.unprepare = 500,
2740 	},
2741 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2742 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2743 };
2744 
2745 static const struct drm_display_mode nvd_9128_mode = {
2746 	.clock = 29500,
2747 	.hdisplay = 800,
2748 	.hsync_start = 800 + 130,
2749 	.hsync_end = 800 + 130 + 98,
2750 	.htotal = 800 + 0 + 130 + 98,
2751 	.vdisplay = 480,
2752 	.vsync_start = 480 + 10,
2753 	.vsync_end = 480 + 10 + 50,
2754 	.vtotal = 480 + 0 + 10 + 50,
2755 };
2756 
2757 static const struct panel_desc nvd_9128 = {
2758 	.modes = &nvd_9128_mode,
2759 	.num_modes = 1,
2760 	.bpc = 8,
2761 	.size = {
2762 		.width = 156,
2763 		.height = 88,
2764 	},
2765 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2766 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
2767 };
2768 
2769 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2770 	.pixelclock = { 30000000, 30000000, 40000000 },
2771 	.hactive = { 800, 800, 800 },
2772 	.hfront_porch = { 40, 40, 40 },
2773 	.hback_porch = { 40, 40, 40 },
2774 	.hsync_len = { 1, 48, 48 },
2775 	.vactive = { 480, 480, 480 },
2776 	.vfront_porch = { 13, 13, 13 },
2777 	.vback_porch = { 29, 29, 29 },
2778 	.vsync_len = { 3, 3, 3 },
2779 	.flags = DISPLAY_FLAGS_DE_HIGH,
2780 };
2781 
2782 static const struct panel_desc okaya_rs800480t_7x0gp = {
2783 	.timings = &okaya_rs800480t_7x0gp_timing,
2784 	.num_timings = 1,
2785 	.bpc = 6,
2786 	.size = {
2787 		.width = 154,
2788 		.height = 87,
2789 	},
2790 	.delay = {
2791 		.prepare = 41,
2792 		.enable = 50,
2793 		.unprepare = 41,
2794 		.disable = 50,
2795 	},
2796 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2797 };
2798 
2799 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2800 	.clock = 9000,
2801 	.hdisplay = 480,
2802 	.hsync_start = 480 + 5,
2803 	.hsync_end = 480 + 5 + 30,
2804 	.htotal = 480 + 5 + 30 + 10,
2805 	.vdisplay = 272,
2806 	.vsync_start = 272 + 8,
2807 	.vsync_end = 272 + 8 + 5,
2808 	.vtotal = 272 + 8 + 5 + 3,
2809 };
2810 
2811 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2812 	.modes = &olimex_lcd_olinuxino_43ts_mode,
2813 	.num_modes = 1,
2814 	.size = {
2815 		.width = 95,
2816 		.height = 54,
2817 	},
2818 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2819 };
2820 
2821 /*
2822  * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2823  * pixel clocks, but this is the timing that was being used in the Adafruit
2824  * installation instructions.
2825  */
2826 static const struct drm_display_mode ontat_yx700wv03_mode = {
2827 	.clock = 29500,
2828 	.hdisplay = 800,
2829 	.hsync_start = 824,
2830 	.hsync_end = 896,
2831 	.htotal = 992,
2832 	.vdisplay = 480,
2833 	.vsync_start = 483,
2834 	.vsync_end = 493,
2835 	.vtotal = 500,
2836 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2837 };
2838 
2839 /*
2840  * Specification at:
2841  * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2842  */
2843 static const struct panel_desc ontat_yx700wv03 = {
2844 	.modes = &ontat_yx700wv03_mode,
2845 	.num_modes = 1,
2846 	.bpc = 8,
2847 	.size = {
2848 		.width = 154,
2849 		.height = 83,
2850 	},
2851 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2852 };
2853 
2854 static const struct drm_display_mode ortustech_com37h3m_mode  = {
2855 	.clock = 22230,
2856 	.hdisplay = 480,
2857 	.hsync_start = 480 + 40,
2858 	.hsync_end = 480 + 40 + 10,
2859 	.htotal = 480 + 40 + 10 + 40,
2860 	.vdisplay = 640,
2861 	.vsync_start = 640 + 4,
2862 	.vsync_end = 640 + 4 + 2,
2863 	.vtotal = 640 + 4 + 2 + 4,
2864 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2865 };
2866 
2867 static const struct panel_desc ortustech_com37h3m = {
2868 	.modes = &ortustech_com37h3m_mode,
2869 	.num_modes = 1,
2870 	.bpc = 8,
2871 	.size = {
2872 		.width = 56,	/* 56.16mm */
2873 		.height = 75,	/* 74.88mm */
2874 	},
2875 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2876 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2877 		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2878 };
2879 
2880 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
2881 	.clock = 25000,
2882 	.hdisplay = 480,
2883 	.hsync_start = 480 + 10,
2884 	.hsync_end = 480 + 10 + 10,
2885 	.htotal = 480 + 10 + 10 + 15,
2886 	.vdisplay = 800,
2887 	.vsync_start = 800 + 3,
2888 	.vsync_end = 800 + 3 + 3,
2889 	.vtotal = 800 + 3 + 3 + 3,
2890 };
2891 
2892 static const struct panel_desc ortustech_com43h4m85ulc = {
2893 	.modes = &ortustech_com43h4m85ulc_mode,
2894 	.num_modes = 1,
2895 	.bpc = 6,
2896 	.size = {
2897 		.width = 56,
2898 		.height = 93,
2899 	},
2900 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2901 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2902 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2903 };
2904 
2905 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode  = {
2906 	.clock = 33000,
2907 	.hdisplay = 800,
2908 	.hsync_start = 800 + 210,
2909 	.hsync_end = 800 + 210 + 30,
2910 	.htotal = 800 + 210 + 30 + 16,
2911 	.vdisplay = 480,
2912 	.vsync_start = 480 + 22,
2913 	.vsync_end = 480 + 22 + 13,
2914 	.vtotal = 480 + 22 + 13 + 10,
2915 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2916 };
2917 
2918 static const struct panel_desc osddisplays_osd070t1718_19ts = {
2919 	.modes = &osddisplays_osd070t1718_19ts_mode,
2920 	.num_modes = 1,
2921 	.bpc = 8,
2922 	.size = {
2923 		.width = 152,
2924 		.height = 91,
2925 	},
2926 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2927 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2928 		DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2929 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2930 };
2931 
2932 static const struct drm_display_mode pda_91_00156_a0_mode = {
2933 	.clock = 33300,
2934 	.hdisplay = 800,
2935 	.hsync_start = 800 + 1,
2936 	.hsync_end = 800 + 1 + 64,
2937 	.htotal = 800 + 1 + 64 + 64,
2938 	.vdisplay = 480,
2939 	.vsync_start = 480 + 1,
2940 	.vsync_end = 480 + 1 + 23,
2941 	.vtotal = 480 + 1 + 23 + 22,
2942 };
2943 
2944 static const struct panel_desc pda_91_00156_a0  = {
2945 	.modes = &pda_91_00156_a0_mode,
2946 	.num_modes = 1,
2947 	.size = {
2948 		.width = 152,
2949 		.height = 91,
2950 	},
2951 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2952 };
2953 
2954 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
2955 	.clock = 24750,
2956 	.hdisplay = 800,
2957 	.hsync_start = 800 + 54,
2958 	.hsync_end = 800 + 54 + 2,
2959 	.htotal = 800 + 54 + 2 + 44,
2960 	.vdisplay = 480,
2961 	.vsync_start = 480 + 49,
2962 	.vsync_end = 480 + 49 + 2,
2963 	.vtotal = 480 + 49 + 2 + 22,
2964 };
2965 
2966 static const struct panel_desc powertip_ph800480t013_idf02  = {
2967 	.modes = &powertip_ph800480t013_idf02_mode,
2968 	.num_modes = 1,
2969 	.size = {
2970 		.width = 152,
2971 		.height = 91,
2972 	},
2973 	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
2974 		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2975 		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2976 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2977 	.connector_type = DRM_MODE_CONNECTOR_DPI,
2978 };
2979 
2980 static const struct drm_display_mode qd43003c0_40_mode = {
2981 	.clock = 9000,
2982 	.hdisplay = 480,
2983 	.hsync_start = 480 + 8,
2984 	.hsync_end = 480 + 8 + 4,
2985 	.htotal = 480 + 8 + 4 + 39,
2986 	.vdisplay = 272,
2987 	.vsync_start = 272 + 4,
2988 	.vsync_end = 272 + 4 + 10,
2989 	.vtotal = 272 + 4 + 10 + 2,
2990 };
2991 
2992 static const struct panel_desc qd43003c0_40 = {
2993 	.modes = &qd43003c0_40_mode,
2994 	.num_modes = 1,
2995 	.bpc = 8,
2996 	.size = {
2997 		.width = 95,
2998 		.height = 53,
2999 	},
3000 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3001 };
3002 
3003 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3004 	{ /* 60 Hz */
3005 		.clock = 10800,
3006 		.hdisplay = 480,
3007 		.hsync_start = 480 + 77,
3008 		.hsync_end = 480 + 77 + 41,
3009 		.htotal = 480 + 77 + 41 + 2,
3010 		.vdisplay = 272,
3011 		.vsync_start = 272 + 16,
3012 		.vsync_end = 272 + 16 + 10,
3013 		.vtotal = 272 + 16 + 10 + 2,
3014 		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3015 	},
3016 	{ /* 50 Hz */
3017 		.clock = 10800,
3018 		.hdisplay = 480,
3019 		.hsync_start = 480 + 17,
3020 		.hsync_end = 480 + 17 + 41,
3021 		.htotal = 480 + 17 + 41 + 2,
3022 		.vdisplay = 272,
3023 		.vsync_start = 272 + 116,
3024 		.vsync_end = 272 + 116 + 10,
3025 		.vtotal = 272 + 116 + 10 + 2,
3026 		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3027 	},
3028 };
3029 
3030 static const struct panel_desc qishenglong_gopher2b_lcd = {
3031 	.modes = qishenglong_gopher2b_lcd_modes,
3032 	.num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3033 	.bpc = 8,
3034 	.size = {
3035 		.width = 95,
3036 		.height = 54,
3037 	},
3038 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3039 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3040 	.connector_type = DRM_MODE_CONNECTOR_DPI,
3041 };
3042 
3043 static const struct display_timing rocktech_rk070er9427_timing = {
3044 	.pixelclock = { 26400000, 33300000, 46800000 },
3045 	.hactive = { 800, 800, 800 },
3046 	.hfront_porch = { 16, 210, 354 },
3047 	.hback_porch = { 46, 46, 46 },
3048 	.hsync_len = { 1, 1, 1 },
3049 	.vactive = { 480, 480, 480 },
3050 	.vfront_porch = { 7, 22, 147 },
3051 	.vback_porch = { 23, 23, 23 },
3052 	.vsync_len = { 1, 1, 1 },
3053 	.flags = DISPLAY_FLAGS_DE_HIGH,
3054 };
3055 
3056 static const struct panel_desc rocktech_rk070er9427 = {
3057 	.timings = &rocktech_rk070er9427_timing,
3058 	.num_timings = 1,
3059 	.bpc = 6,
3060 	.size = {
3061 		.width = 154,
3062 		.height = 86,
3063 	},
3064 	.delay = {
3065 		.prepare = 41,
3066 		.enable = 50,
3067 		.unprepare = 41,
3068 		.disable = 50,
3069 	},
3070 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3071 };
3072 
3073 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3074 	.clock = 71100,
3075 	.hdisplay = 1280,
3076 	.hsync_start = 1280 + 48,
3077 	.hsync_end = 1280 + 48 + 32,
3078 	.htotal = 1280 + 48 + 32 + 80,
3079 	.vdisplay = 800,
3080 	.vsync_start = 800 + 2,
3081 	.vsync_end = 800 + 2 + 5,
3082 	.vtotal = 800 + 2 + 5 + 16,
3083 };
3084 
3085 static const struct panel_desc rocktech_rk101ii01d_ct = {
3086 	.modes = &rocktech_rk101ii01d_ct_mode,
3087 	.bpc = 8,
3088 	.num_modes = 1,
3089 	.size = {
3090 		.width = 217,
3091 		.height = 136,
3092 	},
3093 	.delay = {
3094 		.prepare = 50,
3095 		.disable = 50,
3096 	},
3097 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
3098 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3099 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3100 };
3101 
3102 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3103 	.clock = 54030,
3104 	.hdisplay = 1024,
3105 	.hsync_start = 1024 + 24,
3106 	.hsync_end = 1024 + 24 + 136,
3107 	.htotal = 1024 + 24 + 136 + 160,
3108 	.vdisplay = 600,
3109 	.vsync_start = 600 + 3,
3110 	.vsync_end = 600 + 3 + 6,
3111 	.vtotal = 600 + 3 + 6 + 61,
3112 };
3113 
3114 static const struct panel_desc samsung_ltn101nt05 = {
3115 	.modes = &samsung_ltn101nt05_mode,
3116 	.num_modes = 1,
3117 	.bpc = 6,
3118 	.size = {
3119 		.width = 223,
3120 		.height = 125,
3121 	},
3122 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3123 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
3124 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3125 };
3126 
3127 static const struct display_timing satoz_sat050at40h12r2_timing = {
3128 	.pixelclock = {33300000, 33300000, 50000000},
3129 	.hactive = {800, 800, 800},
3130 	.hfront_porch = {16, 210, 354},
3131 	.hback_porch = {46, 46, 46},
3132 	.hsync_len = {1, 1, 40},
3133 	.vactive = {480, 480, 480},
3134 	.vfront_porch = {7, 22, 147},
3135 	.vback_porch = {23, 23, 23},
3136 	.vsync_len = {1, 1, 20},
3137 };
3138 
3139 static const struct panel_desc satoz_sat050at40h12r2 = {
3140 	.timings = &satoz_sat050at40h12r2_timing,
3141 	.num_timings = 1,
3142 	.bpc = 8,
3143 	.size = {
3144 		.width = 108,
3145 		.height = 65,
3146 	},
3147 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3148 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3149 };
3150 
3151 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3152 	.clock = 33260,
3153 	.hdisplay = 800,
3154 	.hsync_start = 800 + 64,
3155 	.hsync_end = 800 + 64 + 128,
3156 	.htotal = 800 + 64 + 128 + 64,
3157 	.vdisplay = 480,
3158 	.vsync_start = 480 + 8,
3159 	.vsync_end = 480 + 8 + 2,
3160 	.vtotal = 480 + 8 + 2 + 35,
3161 	.flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3162 };
3163 
3164 static const struct panel_desc sharp_lq070y3dg3b = {
3165 	.modes = &sharp_lq070y3dg3b_mode,
3166 	.num_modes = 1,
3167 	.bpc = 8,
3168 	.size = {
3169 		.width = 152,	/* 152.4mm */
3170 		.height = 91,	/* 91.4mm */
3171 	},
3172 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3173 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3174 		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3175 };
3176 
3177 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3178 	.clock = 5500,
3179 	.hdisplay = 240,
3180 	.hsync_start = 240 + 16,
3181 	.hsync_end = 240 + 16 + 7,
3182 	.htotal = 240 + 16 + 7 + 5,
3183 	.vdisplay = 320,
3184 	.vsync_start = 320 + 9,
3185 	.vsync_end = 320 + 9 + 1,
3186 	.vtotal = 320 + 9 + 1 + 7,
3187 };
3188 
3189 static const struct panel_desc sharp_lq035q7db03 = {
3190 	.modes = &sharp_lq035q7db03_mode,
3191 	.num_modes = 1,
3192 	.bpc = 6,
3193 	.size = {
3194 		.width = 54,
3195 		.height = 72,
3196 	},
3197 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3198 };
3199 
3200 static const struct display_timing sharp_lq101k1ly04_timing = {
3201 	.pixelclock = { 60000000, 65000000, 80000000 },
3202 	.hactive = { 1280, 1280, 1280 },
3203 	.hfront_porch = { 20, 20, 20 },
3204 	.hback_porch = { 20, 20, 20 },
3205 	.hsync_len = { 10, 10, 10 },
3206 	.vactive = { 800, 800, 800 },
3207 	.vfront_porch = { 4, 4, 4 },
3208 	.vback_porch = { 4, 4, 4 },
3209 	.vsync_len = { 4, 4, 4 },
3210 	.flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3211 };
3212 
3213 static const struct panel_desc sharp_lq101k1ly04 = {
3214 	.timings = &sharp_lq101k1ly04_timing,
3215 	.num_timings = 1,
3216 	.bpc = 8,
3217 	.size = {
3218 		.width = 217,
3219 		.height = 136,
3220 	},
3221 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3222 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3223 };
3224 
3225 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3226 	{ /* 50 Hz */
3227 		.clock = 3000,
3228 		.hdisplay = 240,
3229 		.hsync_start = 240 + 58,
3230 		.hsync_end = 240 + 58 + 1,
3231 		.htotal = 240 + 58 + 1 + 1,
3232 		.vdisplay = 160,
3233 		.vsync_start = 160 + 24,
3234 		.vsync_end = 160 + 24 + 10,
3235 		.vtotal = 160 + 24 + 10 + 6,
3236 		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3237 	},
3238 	{ /* 60 Hz */
3239 		.clock = 3000,
3240 		.hdisplay = 240,
3241 		.hsync_start = 240 + 8,
3242 		.hsync_end = 240 + 8 + 1,
3243 		.htotal = 240 + 8 + 1 + 1,
3244 		.vdisplay = 160,
3245 		.vsync_start = 160 + 24,
3246 		.vsync_end = 160 + 24 + 10,
3247 		.vtotal = 160 + 24 + 10 + 6,
3248 		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3249 	},
3250 };
3251 
3252 static const struct panel_desc sharp_ls020b1dd01d = {
3253 	.modes = sharp_ls020b1dd01d_modes,
3254 	.num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3255 	.bpc = 6,
3256 	.size = {
3257 		.width = 42,
3258 		.height = 28,
3259 	},
3260 	.bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3261 	.bus_flags = DRM_BUS_FLAG_DE_HIGH
3262 		   | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3263 		   | DRM_BUS_FLAG_SHARP_SIGNALS,
3264 };
3265 
3266 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3267 	.clock = 33300,
3268 	.hdisplay = 800,
3269 	.hsync_start = 800 + 1,
3270 	.hsync_end = 800 + 1 + 64,
3271 	.htotal = 800 + 1 + 64 + 64,
3272 	.vdisplay = 480,
3273 	.vsync_start = 480 + 1,
3274 	.vsync_end = 480 + 1 + 23,
3275 	.vtotal = 480 + 1 + 23 + 22,
3276 };
3277 
3278 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3279 	.modes = &shelly_sca07010_bfn_lnn_mode,
3280 	.num_modes = 1,
3281 	.size = {
3282 		.width = 152,
3283 		.height = 91,
3284 	},
3285 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3286 };
3287 
3288 static const struct drm_display_mode starry_kr070pe2t_mode = {
3289 	.clock = 33000,
3290 	.hdisplay = 800,
3291 	.hsync_start = 800 + 209,
3292 	.hsync_end = 800 + 209 + 1,
3293 	.htotal = 800 + 209 + 1 + 45,
3294 	.vdisplay = 480,
3295 	.vsync_start = 480 + 22,
3296 	.vsync_end = 480 + 22 + 1,
3297 	.vtotal = 480 + 22 + 1 + 22,
3298 };
3299 
3300 static const struct panel_desc starry_kr070pe2t = {
3301 	.modes = &starry_kr070pe2t_mode,
3302 	.num_modes = 1,
3303 	.bpc = 8,
3304 	.size = {
3305 		.width = 152,
3306 		.height = 86,
3307 	},
3308 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3309 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3310 	.connector_type = DRM_MODE_CONNECTOR_DPI,
3311 };
3312 
3313 static const struct display_timing startek_kd070wvfpa_mode = {
3314 	.pixelclock = { 25200000, 27200000, 30500000 },
3315 	.hactive = { 800, 800, 800 },
3316 	.hfront_porch = { 19, 44, 115 },
3317 	.hback_porch = { 5, 16, 101 },
3318 	.hsync_len = { 1, 2, 100 },
3319 	.vactive = { 480, 480, 480 },
3320 	.vfront_porch = { 5, 43, 67 },
3321 	.vback_porch = { 5, 5, 67 },
3322 	.vsync_len = { 1, 2, 66 },
3323 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3324 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3325 		 DISPLAY_FLAGS_SYNC_POSEDGE,
3326 };
3327 
3328 static const struct panel_desc startek_kd070wvfpa = {
3329 	.timings = &startek_kd070wvfpa_mode,
3330 	.num_timings = 1,
3331 	.bpc = 8,
3332 	.size = {
3333 		.width = 152,
3334 		.height = 91,
3335 	},
3336 	.delay = {
3337 		.prepare = 20,
3338 		.enable = 200,
3339 		.disable = 200,
3340 	},
3341 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3342 	.connector_type = DRM_MODE_CONNECTOR_DPI,
3343 	.bus_flags = DRM_BUS_FLAG_DE_HIGH |
3344 		     DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3345 		     DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3346 };
3347 
3348 static const struct display_timing tsd_tst043015cmhx_timing = {
3349 	.pixelclock = { 5000000, 9000000, 12000000 },
3350 	.hactive = { 480, 480, 480 },
3351 	.hfront_porch = { 4, 5, 65 },
3352 	.hback_porch = { 36, 40, 255 },
3353 	.hsync_len = { 1, 1, 1 },
3354 	.vactive = { 272, 272, 272 },
3355 	.vfront_porch = { 2, 8, 97 },
3356 	.vback_porch = { 3, 8, 31 },
3357 	.vsync_len = { 1, 1, 1 },
3358 
3359 	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3360 		 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3361 };
3362 
3363 static const struct panel_desc tsd_tst043015cmhx = {
3364 	.timings = &tsd_tst043015cmhx_timing,
3365 	.num_timings = 1,
3366 	.bpc = 8,
3367 	.size = {
3368 		.width = 105,
3369 		.height = 67,
3370 	},
3371 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3372 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3373 };
3374 
3375 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3376 	.clock = 30000,
3377 	.hdisplay = 800,
3378 	.hsync_start = 800 + 39,
3379 	.hsync_end = 800 + 39 + 47,
3380 	.htotal = 800 + 39 + 47 + 39,
3381 	.vdisplay = 480,
3382 	.vsync_start = 480 + 13,
3383 	.vsync_end = 480 + 13 + 2,
3384 	.vtotal = 480 + 13 + 2 + 29,
3385 };
3386 
3387 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3388 	.modes = &tfc_s9700rtwv43tr_01b_mode,
3389 	.num_modes = 1,
3390 	.bpc = 8,
3391 	.size = {
3392 		.width = 155,
3393 		.height = 90,
3394 	},
3395 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3396 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3397 };
3398 
3399 static const struct display_timing tianma_tm070jdhg30_timing = {
3400 	.pixelclock = { 62600000, 68200000, 78100000 },
3401 	.hactive = { 1280, 1280, 1280 },
3402 	.hfront_porch = { 15, 64, 159 },
3403 	.hback_porch = { 5, 5, 5 },
3404 	.hsync_len = { 1, 1, 256 },
3405 	.vactive = { 800, 800, 800 },
3406 	.vfront_porch = { 3, 40, 99 },
3407 	.vback_porch = { 2, 2, 2 },
3408 	.vsync_len = { 1, 1, 128 },
3409 	.flags = DISPLAY_FLAGS_DE_HIGH,
3410 };
3411 
3412 static const struct panel_desc tianma_tm070jdhg30 = {
3413 	.timings = &tianma_tm070jdhg30_timing,
3414 	.num_timings = 1,
3415 	.bpc = 8,
3416 	.size = {
3417 		.width = 151,
3418 		.height = 95,
3419 	},
3420 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3421 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3422 };
3423 
3424 static const struct panel_desc tianma_tm070jvhg33 = {
3425 	.timings = &tianma_tm070jdhg30_timing,
3426 	.num_timings = 1,
3427 	.bpc = 8,
3428 	.size = {
3429 		.width = 150,
3430 		.height = 94,
3431 	},
3432 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3433 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3434 };
3435 
3436 static const struct display_timing tianma_tm070rvhg71_timing = {
3437 	.pixelclock = { 27700000, 29200000, 39600000 },
3438 	.hactive = { 800, 800, 800 },
3439 	.hfront_porch = { 12, 40, 212 },
3440 	.hback_porch = { 88, 88, 88 },
3441 	.hsync_len = { 1, 1, 40 },
3442 	.vactive = { 480, 480, 480 },
3443 	.vfront_porch = { 1, 13, 88 },
3444 	.vback_porch = { 32, 32, 32 },
3445 	.vsync_len = { 1, 1, 3 },
3446 	.flags = DISPLAY_FLAGS_DE_HIGH,
3447 };
3448 
3449 static const struct panel_desc tianma_tm070rvhg71 = {
3450 	.timings = &tianma_tm070rvhg71_timing,
3451 	.num_timings = 1,
3452 	.bpc = 8,
3453 	.size = {
3454 		.width = 154,
3455 		.height = 86,
3456 	},
3457 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3458 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3459 };
3460 
3461 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3462 	{
3463 		.clock = 10000,
3464 		.hdisplay = 320,
3465 		.hsync_start = 320 + 50,
3466 		.hsync_end = 320 + 50 + 6,
3467 		.htotal = 320 + 50 + 6 + 38,
3468 		.vdisplay = 240,
3469 		.vsync_start = 240 + 3,
3470 		.vsync_end = 240 + 3 + 1,
3471 		.vtotal = 240 + 3 + 1 + 17,
3472 		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3473 	},
3474 };
3475 
3476 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3477 	.modes = ti_nspire_cx_lcd_mode,
3478 	.num_modes = 1,
3479 	.bpc = 8,
3480 	.size = {
3481 		.width = 65,
3482 		.height = 49,
3483 	},
3484 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3485 	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3486 };
3487 
3488 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3489 	{
3490 		.clock = 10000,
3491 		.hdisplay = 320,
3492 		.hsync_start = 320 + 6,
3493 		.hsync_end = 320 + 6 + 6,
3494 		.htotal = 320 + 6 + 6 + 6,
3495 		.vdisplay = 240,
3496 		.vsync_start = 240 + 0,
3497 		.vsync_end = 240 + 0 + 1,
3498 		.vtotal = 240 + 0 + 1 + 0,
3499 		.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3500 	},
3501 };
3502 
3503 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3504 	.modes = ti_nspire_classic_lcd_mode,
3505 	.num_modes = 1,
3506 	/* The grayscale panel has 8 bit for the color .. Y (black) */
3507 	.bpc = 8,
3508 	.size = {
3509 		.width = 71,
3510 		.height = 53,
3511 	},
3512 	/* This is the grayscale bus format */
3513 	.bus_format = MEDIA_BUS_FMT_Y8_1X8,
3514 	.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3515 };
3516 
3517 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3518 	.clock = 79500,
3519 	.hdisplay = 1280,
3520 	.hsync_start = 1280 + 192,
3521 	.hsync_end = 1280 + 192 + 128,
3522 	.htotal = 1280 + 192 + 128 + 64,
3523 	.vdisplay = 768,
3524 	.vsync_start = 768 + 20,
3525 	.vsync_end = 768 + 20 + 7,
3526 	.vtotal = 768 + 20 + 7 + 3,
3527 };
3528 
3529 static const struct panel_desc toshiba_lt089ac29000 = {
3530 	.modes = &toshiba_lt089ac29000_mode,
3531 	.num_modes = 1,
3532 	.size = {
3533 		.width = 194,
3534 		.height = 116,
3535 	},
3536 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3537 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
3538 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3539 };
3540 
3541 static const struct drm_display_mode tpk_f07a_0102_mode = {
3542 	.clock = 33260,
3543 	.hdisplay = 800,
3544 	.hsync_start = 800 + 40,
3545 	.hsync_end = 800 + 40 + 128,
3546 	.htotal = 800 + 40 + 128 + 88,
3547 	.vdisplay = 480,
3548 	.vsync_start = 480 + 10,
3549 	.vsync_end = 480 + 10 + 2,
3550 	.vtotal = 480 + 10 + 2 + 33,
3551 };
3552 
3553 static const struct panel_desc tpk_f07a_0102 = {
3554 	.modes = &tpk_f07a_0102_mode,
3555 	.num_modes = 1,
3556 	.size = {
3557 		.width = 152,
3558 		.height = 91,
3559 	},
3560 	.bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3561 };
3562 
3563 static const struct drm_display_mode tpk_f10a_0102_mode = {
3564 	.clock = 45000,
3565 	.hdisplay = 1024,
3566 	.hsync_start = 1024 + 176,
3567 	.hsync_end = 1024 + 176 + 5,
3568 	.htotal = 1024 + 176 + 5 + 88,
3569 	.vdisplay = 600,
3570 	.vsync_start = 600 + 20,
3571 	.vsync_end = 600 + 20 + 5,
3572 	.vtotal = 600 + 20 + 5 + 25,
3573 };
3574 
3575 static const struct panel_desc tpk_f10a_0102 = {
3576 	.modes = &tpk_f10a_0102_mode,
3577 	.num_modes = 1,
3578 	.size = {
3579 		.width = 223,
3580 		.height = 125,
3581 	},
3582 };
3583 
3584 static const struct display_timing urt_umsh_8596md_timing = {
3585 	.pixelclock = { 33260000, 33260000, 33260000 },
3586 	.hactive = { 800, 800, 800 },
3587 	.hfront_porch = { 41, 41, 41 },
3588 	.hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3589 	.hsync_len = { 71, 128, 128 },
3590 	.vactive = { 480, 480, 480 },
3591 	.vfront_porch = { 10, 10, 10 },
3592 	.vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3593 	.vsync_len = { 2, 2, 2 },
3594 	.flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3595 		DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3596 };
3597 
3598 static const struct panel_desc urt_umsh_8596md_lvds = {
3599 	.timings = &urt_umsh_8596md_timing,
3600 	.num_timings = 1,
3601 	.bpc = 6,
3602 	.size = {
3603 		.width = 152,
3604 		.height = 91,
3605 	},
3606 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3607 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3608 };
3609 
3610 static const struct panel_desc urt_umsh_8596md_parallel = {
3611 	.timings = &urt_umsh_8596md_timing,
3612 	.num_timings = 1,
3613 	.bpc = 6,
3614 	.size = {
3615 		.width = 152,
3616 		.height = 91,
3617 	},
3618 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3619 };
3620 
3621 static const struct drm_display_mode vivax_tpc9150_panel_mode = {
3622 	.clock = 60000,
3623 	.hdisplay = 1024,
3624 	.hsync_start = 1024 + 160,
3625 	.hsync_end = 1024 + 160 + 100,
3626 	.htotal = 1024 + 160 + 100 + 60,
3627 	.vdisplay = 600,
3628 	.vsync_start = 600 + 12,
3629 	.vsync_end = 600 + 12 + 10,
3630 	.vtotal = 600 + 12 + 10 + 13,
3631 };
3632 
3633 static const struct panel_desc vivax_tpc9150_panel = {
3634 	.modes = &vivax_tpc9150_panel_mode,
3635 	.num_modes = 1,
3636 	.bpc = 6,
3637 	.size = {
3638 		.width = 200,
3639 		.height = 115,
3640 	},
3641 	.bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3642 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
3643 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3644 };
3645 
3646 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3647 	.clock = 33333,
3648 	.hdisplay = 800,
3649 	.hsync_start = 800 + 210,
3650 	.hsync_end = 800 + 210 + 20,
3651 	.htotal = 800 + 210 + 20 + 46,
3652 	.vdisplay =  480,
3653 	.vsync_start = 480 + 22,
3654 	.vsync_end = 480 + 22 + 10,
3655 	.vtotal = 480 + 22 + 10 + 23,
3656 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3657 };
3658 
3659 static const struct panel_desc vl050_8048nt_c01 = {
3660 	.modes = &vl050_8048nt_c01_mode,
3661 	.num_modes = 1,
3662 	.bpc = 8,
3663 	.size = {
3664 		.width = 120,
3665 		.height = 76,
3666 	},
3667 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3668 	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3669 };
3670 
3671 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3672 	.clock = 6410,
3673 	.hdisplay = 320,
3674 	.hsync_start = 320 + 20,
3675 	.hsync_end = 320 + 20 + 30,
3676 	.htotal = 320 + 20 + 30 + 38,
3677 	.vdisplay = 240,
3678 	.vsync_start = 240 + 4,
3679 	.vsync_end = 240 + 4 + 3,
3680 	.vtotal = 240 + 4 + 3 + 15,
3681 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3682 };
3683 
3684 static const struct panel_desc winstar_wf35ltiacd = {
3685 	.modes = &winstar_wf35ltiacd_mode,
3686 	.num_modes = 1,
3687 	.bpc = 8,
3688 	.size = {
3689 		.width = 70,
3690 		.height = 53,
3691 	},
3692 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3693 };
3694 
3695 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
3696 	.clock = 51200,
3697 	.hdisplay = 1024,
3698 	.hsync_start = 1024 + 100,
3699 	.hsync_end = 1024 + 100 + 100,
3700 	.htotal = 1024 + 100 + 100 + 120,
3701 	.vdisplay = 600,
3702 	.vsync_start = 600 + 10,
3703 	.vsync_end = 600 + 10 + 10,
3704 	.vtotal = 600 + 10 + 10 + 15,
3705 	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3706 };
3707 
3708 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
3709 	.modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
3710 	.num_modes = 1,
3711 	.bpc = 8,
3712 	.size = {
3713 		.width = 154,
3714 		.height = 90,
3715 	},
3716 	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
3717 	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3718 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
3719 };
3720 
3721 static const struct drm_display_mode arm_rtsm_mode[] = {
3722 	{
3723 		.clock = 65000,
3724 		.hdisplay = 1024,
3725 		.hsync_start = 1024 + 24,
3726 		.hsync_end = 1024 + 24 + 136,
3727 		.htotal = 1024 + 24 + 136 + 160,
3728 		.vdisplay = 768,
3729 		.vsync_start = 768 + 3,
3730 		.vsync_end = 768 + 3 + 6,
3731 		.vtotal = 768 + 3 + 6 + 29,
3732 		.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3733 	},
3734 };
3735 
3736 static const struct panel_desc arm_rtsm = {
3737 	.modes = arm_rtsm_mode,
3738 	.num_modes = 1,
3739 	.bpc = 8,
3740 	.size = {
3741 		.width = 400,
3742 		.height = 300,
3743 	},
3744 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3745 };
3746 
3747 static const struct of_device_id platform_of_match[] = {
3748 	{
3749 		.compatible = "ampire,am-1280800n3tzqw-t00h",
3750 		.data = &ampire_am_1280800n3tzqw_t00h,
3751 	}, {
3752 		.compatible = "ampire,am-480272h3tmqw-t01h",
3753 		.data = &ampire_am_480272h3tmqw_t01h,
3754 	}, {
3755 		.compatible = "ampire,am800480r3tmqwa1h",
3756 		.data = &ampire_am800480r3tmqwa1h,
3757 	}, {
3758 		.compatible = "arm,rtsm-display",
3759 		.data = &arm_rtsm,
3760 	}, {
3761 		.compatible = "armadeus,st0700-adapt",
3762 		.data = &armadeus_st0700_adapt,
3763 	}, {
3764 		.compatible = "auo,b101aw03",
3765 		.data = &auo_b101aw03,
3766 	}, {
3767 		.compatible = "auo,b101xtn01",
3768 		.data = &auo_b101xtn01,
3769 	}, {
3770 		.compatible = "auo,g070vvn01",
3771 		.data = &auo_g070vvn01,
3772 	}, {
3773 		.compatible = "auo,g101evn010",
3774 		.data = &auo_g101evn010,
3775 	}, {
3776 		.compatible = "auo,g104sn02",
3777 		.data = &auo_g104sn02,
3778 	}, {
3779 		.compatible = "auo,g121ean01",
3780 		.data = &auo_g121ean01,
3781 	}, {
3782 		.compatible = "auo,g133han01",
3783 		.data = &auo_g133han01,
3784 	}, {
3785 		.compatible = "auo,g156xtn01",
3786 		.data = &auo_g156xtn01,
3787 	}, {
3788 		.compatible = "auo,g185han01",
3789 		.data = &auo_g185han01,
3790 	}, {
3791 		.compatible = "auo,g190ean01",
3792 		.data = &auo_g190ean01,
3793 	}, {
3794 		.compatible = "auo,p320hvn03",
3795 		.data = &auo_p320hvn03,
3796 	}, {
3797 		.compatible = "auo,t215hvn01",
3798 		.data = &auo_t215hvn01,
3799 	}, {
3800 		.compatible = "avic,tm070ddh03",
3801 		.data = &avic_tm070ddh03,
3802 	}, {
3803 		.compatible = "bananapi,s070wv20-ct16",
3804 		.data = &bananapi_s070wv20_ct16,
3805 	}, {
3806 		.compatible = "boe,hv070wsa-100",
3807 		.data = &boe_hv070wsa
3808 	}, {
3809 		.compatible = "cdtech,s043wq26h-ct7",
3810 		.data = &cdtech_s043wq26h_ct7,
3811 	}, {
3812 		.compatible = "cdtech,s070pws19hp-fc21",
3813 		.data = &cdtech_s070pws19hp_fc21,
3814 	}, {
3815 		.compatible = "cdtech,s070swv29hg-dc44",
3816 		.data = &cdtech_s070swv29hg_dc44,
3817 	}, {
3818 		.compatible = "cdtech,s070wv95-ct16",
3819 		.data = &cdtech_s070wv95_ct16,
3820 	}, {
3821 		.compatible = "chefree,ch101olhlwh-002",
3822 		.data = &chefree_ch101olhlwh_002,
3823 	}, {
3824 		.compatible = "chunghwa,claa070wp03xg",
3825 		.data = &chunghwa_claa070wp03xg,
3826 	}, {
3827 		.compatible = "chunghwa,claa101wa01a",
3828 		.data = &chunghwa_claa101wa01a
3829 	}, {
3830 		.compatible = "chunghwa,claa101wb01",
3831 		.data = &chunghwa_claa101wb01
3832 	}, {
3833 		.compatible = "dataimage,fg040346dsswbg04",
3834 		.data = &dataimage_fg040346dsswbg04,
3835 	}, {
3836 		.compatible = "dataimage,scf0700c48ggu18",
3837 		.data = &dataimage_scf0700c48ggu18,
3838 	}, {
3839 		.compatible = "dlc,dlc0700yzg-1",
3840 		.data = &dlc_dlc0700yzg_1,
3841 	}, {
3842 		.compatible = "dlc,dlc1010gig",
3843 		.data = &dlc_dlc1010gig,
3844 	}, {
3845 		.compatible = "edt,et035012dm6",
3846 		.data = &edt_et035012dm6,
3847 	}, {
3848 		.compatible = "edt,etm0350g0dh6",
3849 		.data = &edt_etm0350g0dh6,
3850 	}, {
3851 		.compatible = "edt,etm043080dh6gp",
3852 		.data = &edt_etm043080dh6gp,
3853 	}, {
3854 		.compatible = "edt,etm0430g0dh6",
3855 		.data = &edt_etm0430g0dh6,
3856 	}, {
3857 		.compatible = "edt,et057090dhu",
3858 		.data = &edt_et057090dhu,
3859 	}, {
3860 		.compatible = "edt,et070080dh6",
3861 		.data = &edt_etm0700g0dh6,
3862 	}, {
3863 		.compatible = "edt,etm0700g0dh6",
3864 		.data = &edt_etm0700g0dh6,
3865 	}, {
3866 		.compatible = "edt,etm0700g0bdh6",
3867 		.data = &edt_etm0700g0bdh6,
3868 	}, {
3869 		.compatible = "edt,etm0700g0edh6",
3870 		.data = &edt_etm0700g0bdh6,
3871 	}, {
3872 		.compatible = "edt,etmv570g2dhu",
3873 		.data = &edt_etmv570g2dhu,
3874 	}, {
3875 		.compatible = "eink,vb3300-kca",
3876 		.data = &eink_vb3300_kca,
3877 	}, {
3878 		.compatible = "evervision,vgg804821",
3879 		.data = &evervision_vgg804821,
3880 	}, {
3881 		.compatible = "foxlink,fl500wvr00-a0t",
3882 		.data = &foxlink_fl500wvr00_a0t,
3883 	}, {
3884 		.compatible = "frida,frd350h54004",
3885 		.data = &frida_frd350h54004,
3886 	}, {
3887 		.compatible = "friendlyarm,hd702e",
3888 		.data = &friendlyarm_hd702e,
3889 	}, {
3890 		.compatible = "giantplus,gpg482739qs5",
3891 		.data = &giantplus_gpg482739qs5
3892 	}, {
3893 		.compatible = "giantplus,gpm940b0",
3894 		.data = &giantplus_gpm940b0,
3895 	}, {
3896 		.compatible = "hannstar,hsd070pww1",
3897 		.data = &hannstar_hsd070pww1,
3898 	}, {
3899 		.compatible = "hannstar,hsd100pxn1",
3900 		.data = &hannstar_hsd100pxn1,
3901 	}, {
3902 		.compatible = "hit,tx23d38vm0caa",
3903 		.data = &hitachi_tx23d38vm0caa
3904 	}, {
3905 		.compatible = "innolux,at043tn24",
3906 		.data = &innolux_at043tn24,
3907 	}, {
3908 		.compatible = "innolux,at070tn92",
3909 		.data = &innolux_at070tn92,
3910 	}, {
3911 		.compatible = "innolux,g070y2-l01",
3912 		.data = &innolux_g070y2_l01,
3913 	}, {
3914 		.compatible = "innolux,g070y2-t02",
3915 		.data = &innolux_g070y2_t02,
3916 	}, {
3917 		.compatible = "innolux,g101ice-l01",
3918 		.data = &innolux_g101ice_l01
3919 	}, {
3920 		.compatible = "innolux,g121i1-l01",
3921 		.data = &innolux_g121i1_l01
3922 	}, {
3923 		.compatible = "innolux,g121x1-l03",
3924 		.data = &innolux_g121x1_l03,
3925 	}, {
3926 		.compatible = "innolux,n156bge-l21",
3927 		.data = &innolux_n156bge_l21,
3928 	}, {
3929 		.compatible = "innolux,zj070na-01p",
3930 		.data = &innolux_zj070na_01p,
3931 	}, {
3932 		.compatible = "koe,tx14d24vm1bpa",
3933 		.data = &koe_tx14d24vm1bpa,
3934 	}, {
3935 		.compatible = "koe,tx26d202vm0bwa",
3936 		.data = &koe_tx26d202vm0bwa,
3937 	}, {
3938 		.compatible = "koe,tx31d200vm0baa",
3939 		.data = &koe_tx31d200vm0baa,
3940 	}, {
3941 		.compatible = "kyo,tcg121xglp",
3942 		.data = &kyo_tcg121xglp,
3943 	}, {
3944 		.compatible = "lemaker,bl035-rgb-002",
3945 		.data = &lemaker_bl035_rgb_002,
3946 	}, {
3947 		.compatible = "lg,lb070wv8",
3948 		.data = &lg_lb070wv8,
3949 	}, {
3950 		.compatible = "logicpd,type28",
3951 		.data = &logicpd_type_28,
3952 	}, {
3953 		.compatible = "logictechno,lt161010-2nhc",
3954 		.data = &logictechno_lt161010_2nh,
3955 	}, {
3956 		.compatible = "logictechno,lt161010-2nhr",
3957 		.data = &logictechno_lt161010_2nh,
3958 	}, {
3959 		.compatible = "logictechno,lt170410-2whc",
3960 		.data = &logictechno_lt170410_2whc,
3961 	}, {
3962 		.compatible = "logictechno,lttd800480070-l2rt",
3963 		.data = &logictechno_lttd800480070_l2rt,
3964 	}, {
3965 		.compatible = "logictechno,lttd800480070-l6wh-rt",
3966 		.data = &logictechno_lttd800480070_l6wh_rt,
3967 	}, {
3968 		.compatible = "mitsubishi,aa070mc01-ca1",
3969 		.data = &mitsubishi_aa070mc01,
3970 	}, {
3971 		.compatible = "multi-inno,mi0700s4t-6",
3972 		.data = &multi_inno_mi0700s4t_6,
3973 	}, {
3974 		.compatible = "multi-inno,mi1010ait-1cp",
3975 		.data = &multi_inno_mi1010ait_1cp,
3976 	}, {
3977 		.compatible = "nec,nl12880bc20-05",
3978 		.data = &nec_nl12880bc20_05,
3979 	}, {
3980 		.compatible = "nec,nl4827hc19-05b",
3981 		.data = &nec_nl4827hc19_05b,
3982 	}, {
3983 		.compatible = "netron-dy,e231732",
3984 		.data = &netron_dy_e231732,
3985 	}, {
3986 		.compatible = "newhaven,nhd-4.3-480272ef-atxl",
3987 		.data = &newhaven_nhd_43_480272ef_atxl,
3988 	}, {
3989 		.compatible = "nlt,nl192108ac18-02d",
3990 		.data = &nlt_nl192108ac18_02d,
3991 	}, {
3992 		.compatible = "nvd,9128",
3993 		.data = &nvd_9128,
3994 	}, {
3995 		.compatible = "okaya,rs800480t-7x0gp",
3996 		.data = &okaya_rs800480t_7x0gp,
3997 	}, {
3998 		.compatible = "olimex,lcd-olinuxino-43-ts",
3999 		.data = &olimex_lcd_olinuxino_43ts,
4000 	}, {
4001 		.compatible = "ontat,yx700wv03",
4002 		.data = &ontat_yx700wv03,
4003 	}, {
4004 		.compatible = "ortustech,com37h3m05dtc",
4005 		.data = &ortustech_com37h3m,
4006 	}, {
4007 		.compatible = "ortustech,com37h3m99dtc",
4008 		.data = &ortustech_com37h3m,
4009 	}, {
4010 		.compatible = "ortustech,com43h4m85ulc",
4011 		.data = &ortustech_com43h4m85ulc,
4012 	}, {
4013 		.compatible = "osddisplays,osd070t1718-19ts",
4014 		.data = &osddisplays_osd070t1718_19ts,
4015 	}, {
4016 		.compatible = "pda,91-00156-a0",
4017 		.data = &pda_91_00156_a0,
4018 	}, {
4019 		.compatible = "powertip,ph800480t013-idf02",
4020 		.data = &powertip_ph800480t013_idf02,
4021 	}, {
4022 		.compatible = "qiaodian,qd43003c0-40",
4023 		.data = &qd43003c0_40,
4024 	}, {
4025 		.compatible = "qishenglong,gopher2b-lcd",
4026 		.data = &qishenglong_gopher2b_lcd,
4027 	}, {
4028 		.compatible = "rocktech,rk070er9427",
4029 		.data = &rocktech_rk070er9427,
4030 	}, {
4031 		.compatible = "rocktech,rk101ii01d-ct",
4032 		.data = &rocktech_rk101ii01d_ct,
4033 	}, {
4034 		.compatible = "samsung,ltn101nt05",
4035 		.data = &samsung_ltn101nt05,
4036 	}, {
4037 		.compatible = "satoz,sat050at40h12r2",
4038 		.data = &satoz_sat050at40h12r2,
4039 	}, {
4040 		.compatible = "sharp,lq035q7db03",
4041 		.data = &sharp_lq035q7db03,
4042 	}, {
4043 		.compatible = "sharp,lq070y3dg3b",
4044 		.data = &sharp_lq070y3dg3b,
4045 	}, {
4046 		.compatible = "sharp,lq101k1ly04",
4047 		.data = &sharp_lq101k1ly04,
4048 	}, {
4049 		.compatible = "sharp,ls020b1dd01d",
4050 		.data = &sharp_ls020b1dd01d,
4051 	}, {
4052 		.compatible = "shelly,sca07010-bfn-lnn",
4053 		.data = &shelly_sca07010_bfn_lnn,
4054 	}, {
4055 		.compatible = "starry,kr070pe2t",
4056 		.data = &starry_kr070pe2t,
4057 	}, {
4058 		.compatible = "startek,kd070wvfpa",
4059 		.data = &startek_kd070wvfpa,
4060 	}, {
4061 		.compatible = "team-source-display,tst043015cmhx",
4062 		.data = &tsd_tst043015cmhx,
4063 	}, {
4064 		.compatible = "tfc,s9700rtwv43tr-01b",
4065 		.data = &tfc_s9700rtwv43tr_01b,
4066 	}, {
4067 		.compatible = "tianma,tm070jdhg30",
4068 		.data = &tianma_tm070jdhg30,
4069 	}, {
4070 		.compatible = "tianma,tm070jvhg33",
4071 		.data = &tianma_tm070jvhg33,
4072 	}, {
4073 		.compatible = "tianma,tm070rvhg71",
4074 		.data = &tianma_tm070rvhg71,
4075 	}, {
4076 		.compatible = "ti,nspire-cx-lcd-panel",
4077 		.data = &ti_nspire_cx_lcd_panel,
4078 	}, {
4079 		.compatible = "ti,nspire-classic-lcd-panel",
4080 		.data = &ti_nspire_classic_lcd_panel,
4081 	}, {
4082 		.compatible = "toshiba,lt089ac29000",
4083 		.data = &toshiba_lt089ac29000,
4084 	}, {
4085 		.compatible = "tpk,f07a-0102",
4086 		.data = &tpk_f07a_0102,
4087 	}, {
4088 		.compatible = "tpk,f10a-0102",
4089 		.data = &tpk_f10a_0102,
4090 	}, {
4091 		.compatible = "urt,umsh-8596md-t",
4092 		.data = &urt_umsh_8596md_parallel,
4093 	}, {
4094 		.compatible = "urt,umsh-8596md-1t",
4095 		.data = &urt_umsh_8596md_parallel,
4096 	}, {
4097 		.compatible = "urt,umsh-8596md-7t",
4098 		.data = &urt_umsh_8596md_parallel,
4099 	}, {
4100 		.compatible = "urt,umsh-8596md-11t",
4101 		.data = &urt_umsh_8596md_lvds,
4102 	}, {
4103 		.compatible = "urt,umsh-8596md-19t",
4104 		.data = &urt_umsh_8596md_lvds,
4105 	}, {
4106 		.compatible = "urt,umsh-8596md-20t",
4107 		.data = &urt_umsh_8596md_parallel,
4108 	}, {
4109 		.compatible = "vivax,tpc9150-panel",
4110 		.data = &vivax_tpc9150_panel,
4111 	}, {
4112 		.compatible = "vxt,vl050-8048nt-c01",
4113 		.data = &vl050_8048nt_c01,
4114 	}, {
4115 		.compatible = "winstar,wf35ltiacd",
4116 		.data = &winstar_wf35ltiacd,
4117 	}, {
4118 		.compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4119 		.data = &yes_optoelectronics_ytc700tlag_05_201c,
4120 	}, {
4121 		/* Must be the last entry */
4122 		.compatible = "panel-dpi",
4123 		.data = &panel_dpi,
4124 	}, {
4125 		/* sentinel */
4126 	}
4127 };
4128 MODULE_DEVICE_TABLE(of, platform_of_match);
4129 
4130 static int panel_simple_platform_probe(struct platform_device *pdev)
4131 {
4132 	const struct of_device_id *id;
4133 
4134 	id = of_match_node(platform_of_match, pdev->dev.of_node);
4135 	if (!id)
4136 		return -ENODEV;
4137 
4138 	return panel_simple_probe(&pdev->dev, id->data);
4139 }
4140 
4141 static int panel_simple_platform_remove(struct platform_device *pdev)
4142 {
4143 	return panel_simple_remove(&pdev->dev);
4144 }
4145 
4146 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4147 {
4148 	panel_simple_shutdown(&pdev->dev);
4149 }
4150 
4151 static const struct dev_pm_ops panel_simple_pm_ops = {
4152 	SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4153 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4154 				pm_runtime_force_resume)
4155 };
4156 
4157 static struct platform_driver panel_simple_platform_driver = {
4158 	.driver = {
4159 		.name = "panel-simple",
4160 		.of_match_table = platform_of_match,
4161 		.pm = &panel_simple_pm_ops,
4162 	},
4163 	.probe = panel_simple_platform_probe,
4164 	.remove = panel_simple_platform_remove,
4165 	.shutdown = panel_simple_platform_shutdown,
4166 };
4167 
4168 struct panel_desc_dsi {
4169 	struct panel_desc desc;
4170 
4171 	unsigned long flags;
4172 	enum mipi_dsi_pixel_format format;
4173 	unsigned int lanes;
4174 };
4175 
4176 static const struct drm_display_mode auo_b080uan01_mode = {
4177 	.clock = 154500,
4178 	.hdisplay = 1200,
4179 	.hsync_start = 1200 + 62,
4180 	.hsync_end = 1200 + 62 + 4,
4181 	.htotal = 1200 + 62 + 4 + 62,
4182 	.vdisplay = 1920,
4183 	.vsync_start = 1920 + 9,
4184 	.vsync_end = 1920 + 9 + 2,
4185 	.vtotal = 1920 + 9 + 2 + 8,
4186 };
4187 
4188 static const struct panel_desc_dsi auo_b080uan01 = {
4189 	.desc = {
4190 		.modes = &auo_b080uan01_mode,
4191 		.num_modes = 1,
4192 		.bpc = 8,
4193 		.size = {
4194 			.width = 108,
4195 			.height = 272,
4196 		},
4197 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4198 	},
4199 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4200 	.format = MIPI_DSI_FMT_RGB888,
4201 	.lanes = 4,
4202 };
4203 
4204 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4205 	.clock = 160000,
4206 	.hdisplay = 1200,
4207 	.hsync_start = 1200 + 120,
4208 	.hsync_end = 1200 + 120 + 20,
4209 	.htotal = 1200 + 120 + 20 + 21,
4210 	.vdisplay = 1920,
4211 	.vsync_start = 1920 + 21,
4212 	.vsync_end = 1920 + 21 + 3,
4213 	.vtotal = 1920 + 21 + 3 + 18,
4214 	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4215 };
4216 
4217 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4218 	.desc = {
4219 		.modes = &boe_tv080wum_nl0_mode,
4220 		.num_modes = 1,
4221 		.size = {
4222 			.width = 107,
4223 			.height = 172,
4224 		},
4225 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4226 	},
4227 	.flags = MIPI_DSI_MODE_VIDEO |
4228 		 MIPI_DSI_MODE_VIDEO_BURST |
4229 		 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4230 	.format = MIPI_DSI_FMT_RGB888,
4231 	.lanes = 4,
4232 };
4233 
4234 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4235 	.clock = 71000,
4236 	.hdisplay = 800,
4237 	.hsync_start = 800 + 32,
4238 	.hsync_end = 800 + 32 + 1,
4239 	.htotal = 800 + 32 + 1 + 57,
4240 	.vdisplay = 1280,
4241 	.vsync_start = 1280 + 28,
4242 	.vsync_end = 1280 + 28 + 1,
4243 	.vtotal = 1280 + 28 + 1 + 14,
4244 };
4245 
4246 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4247 	.desc = {
4248 		.modes = &lg_ld070wx3_sl01_mode,
4249 		.num_modes = 1,
4250 		.bpc = 8,
4251 		.size = {
4252 			.width = 94,
4253 			.height = 151,
4254 		},
4255 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4256 	},
4257 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4258 	.format = MIPI_DSI_FMT_RGB888,
4259 	.lanes = 4,
4260 };
4261 
4262 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4263 	.clock = 67000,
4264 	.hdisplay = 720,
4265 	.hsync_start = 720 + 12,
4266 	.hsync_end = 720 + 12 + 4,
4267 	.htotal = 720 + 12 + 4 + 112,
4268 	.vdisplay = 1280,
4269 	.vsync_start = 1280 + 8,
4270 	.vsync_end = 1280 + 8 + 4,
4271 	.vtotal = 1280 + 8 + 4 + 12,
4272 };
4273 
4274 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4275 	.desc = {
4276 		.modes = &lg_lh500wx1_sd03_mode,
4277 		.num_modes = 1,
4278 		.bpc = 8,
4279 		.size = {
4280 			.width = 62,
4281 			.height = 110,
4282 		},
4283 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4284 	},
4285 	.flags = MIPI_DSI_MODE_VIDEO,
4286 	.format = MIPI_DSI_FMT_RGB888,
4287 	.lanes = 4,
4288 };
4289 
4290 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4291 	.clock = 157200,
4292 	.hdisplay = 1920,
4293 	.hsync_start = 1920 + 154,
4294 	.hsync_end = 1920 + 154 + 16,
4295 	.htotal = 1920 + 154 + 16 + 32,
4296 	.vdisplay = 1200,
4297 	.vsync_start = 1200 + 17,
4298 	.vsync_end = 1200 + 17 + 2,
4299 	.vtotal = 1200 + 17 + 2 + 16,
4300 };
4301 
4302 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4303 	.desc = {
4304 		.modes = &panasonic_vvx10f004b00_mode,
4305 		.num_modes = 1,
4306 		.bpc = 8,
4307 		.size = {
4308 			.width = 217,
4309 			.height = 136,
4310 		},
4311 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4312 	},
4313 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4314 		 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4315 	.format = MIPI_DSI_FMT_RGB888,
4316 	.lanes = 4,
4317 };
4318 
4319 static const struct drm_display_mode lg_acx467akm_7_mode = {
4320 	.clock = 150000,
4321 	.hdisplay = 1080,
4322 	.hsync_start = 1080 + 2,
4323 	.hsync_end = 1080 + 2 + 2,
4324 	.htotal = 1080 + 2 + 2 + 2,
4325 	.vdisplay = 1920,
4326 	.vsync_start = 1920 + 2,
4327 	.vsync_end = 1920 + 2 + 2,
4328 	.vtotal = 1920 + 2 + 2 + 2,
4329 };
4330 
4331 static const struct panel_desc_dsi lg_acx467akm_7 = {
4332 	.desc = {
4333 		.modes = &lg_acx467akm_7_mode,
4334 		.num_modes = 1,
4335 		.bpc = 8,
4336 		.size = {
4337 			.width = 62,
4338 			.height = 110,
4339 		},
4340 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4341 	},
4342 	.flags = 0,
4343 	.format = MIPI_DSI_FMT_RGB888,
4344 	.lanes = 4,
4345 };
4346 
4347 static const struct drm_display_mode osd101t2045_53ts_mode = {
4348 	.clock = 154500,
4349 	.hdisplay = 1920,
4350 	.hsync_start = 1920 + 112,
4351 	.hsync_end = 1920 + 112 + 16,
4352 	.htotal = 1920 + 112 + 16 + 32,
4353 	.vdisplay = 1200,
4354 	.vsync_start = 1200 + 16,
4355 	.vsync_end = 1200 + 16 + 2,
4356 	.vtotal = 1200 + 16 + 2 + 16,
4357 	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4358 };
4359 
4360 static const struct panel_desc_dsi osd101t2045_53ts = {
4361 	.desc = {
4362 		.modes = &osd101t2045_53ts_mode,
4363 		.num_modes = 1,
4364 		.bpc = 8,
4365 		.size = {
4366 			.width = 217,
4367 			.height = 136,
4368 		},
4369 		.connector_type = DRM_MODE_CONNECTOR_DSI,
4370 	},
4371 	.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4372 		 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4373 		 MIPI_DSI_MODE_NO_EOT_PACKET,
4374 	.format = MIPI_DSI_FMT_RGB888,
4375 	.lanes = 4,
4376 };
4377 
4378 static const struct of_device_id dsi_of_match[] = {
4379 	{
4380 		.compatible = "auo,b080uan01",
4381 		.data = &auo_b080uan01
4382 	}, {
4383 		.compatible = "boe,tv080wum-nl0",
4384 		.data = &boe_tv080wum_nl0
4385 	}, {
4386 		.compatible = "lg,ld070wx3-sl01",
4387 		.data = &lg_ld070wx3_sl01
4388 	}, {
4389 		.compatible = "lg,lh500wx1-sd03",
4390 		.data = &lg_lh500wx1_sd03
4391 	}, {
4392 		.compatible = "panasonic,vvx10f004b00",
4393 		.data = &panasonic_vvx10f004b00
4394 	}, {
4395 		.compatible = "lg,acx467akm-7",
4396 		.data = &lg_acx467akm_7
4397 	}, {
4398 		.compatible = "osddisplays,osd101t2045-53ts",
4399 		.data = &osd101t2045_53ts
4400 	}, {
4401 		/* sentinel */
4402 	}
4403 };
4404 MODULE_DEVICE_TABLE(of, dsi_of_match);
4405 
4406 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4407 {
4408 	const struct panel_desc_dsi *desc;
4409 	const struct of_device_id *id;
4410 	int err;
4411 
4412 	id = of_match_node(dsi_of_match, dsi->dev.of_node);
4413 	if (!id)
4414 		return -ENODEV;
4415 
4416 	desc = id->data;
4417 
4418 	err = panel_simple_probe(&dsi->dev, &desc->desc);
4419 	if (err < 0)
4420 		return err;
4421 
4422 	dsi->mode_flags = desc->flags;
4423 	dsi->format = desc->format;
4424 	dsi->lanes = desc->lanes;
4425 
4426 	err = mipi_dsi_attach(dsi);
4427 	if (err) {
4428 		struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
4429 
4430 		drm_panel_remove(&panel->base);
4431 	}
4432 
4433 	return err;
4434 }
4435 
4436 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4437 {
4438 	int err;
4439 
4440 	err = mipi_dsi_detach(dsi);
4441 	if (err < 0)
4442 		dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4443 
4444 	return panel_simple_remove(&dsi->dev);
4445 }
4446 
4447 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4448 {
4449 	panel_simple_shutdown(&dsi->dev);
4450 }
4451 
4452 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4453 	.driver = {
4454 		.name = "panel-simple-dsi",
4455 		.of_match_table = dsi_of_match,
4456 		.pm = &panel_simple_pm_ops,
4457 	},
4458 	.probe = panel_simple_dsi_probe,
4459 	.remove = panel_simple_dsi_remove,
4460 	.shutdown = panel_simple_dsi_shutdown,
4461 };
4462 
4463 static int __init panel_simple_init(void)
4464 {
4465 	int err;
4466 
4467 	err = platform_driver_register(&panel_simple_platform_driver);
4468 	if (err < 0)
4469 		return err;
4470 
4471 	if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4472 		err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4473 		if (err < 0)
4474 			goto err_did_platform_register;
4475 	}
4476 
4477 	return 0;
4478 
4479 err_did_platform_register:
4480 	platform_driver_unregister(&panel_simple_platform_driver);
4481 
4482 	return err;
4483 }
4484 module_init(panel_simple_init);
4485 
4486 static void __exit panel_simple_exit(void)
4487 {
4488 	if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4489 		mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4490 
4491 	platform_driver_unregister(&panel_simple_platform_driver);
4492 }
4493 module_exit(panel_simple_exit);
4494 
4495 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4496 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4497 MODULE_LICENSE("GPL and additional rights");
4498