1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_device.h> 30 #include <linux/of_platform.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/regulator/consumer.h> 34 35 #include <video/display_timing.h> 36 #include <video/of_display_timing.h> 37 #include <video/videomode.h> 38 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_device.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_mipi_dsi.h> 43 #include <drm/drm_panel.h> 44 #include <drm/drm_of.h> 45 46 /** 47 * struct panel_desc - Describes a simple panel. 48 */ 49 struct panel_desc { 50 /** 51 * @modes: Pointer to array of fixed modes appropriate for this panel. 52 * 53 * If only one mode then this can just be the address of the mode. 54 * NOTE: cannot be used with "timings" and also if this is specified 55 * then you cannot override the mode in the device tree. 56 */ 57 const struct drm_display_mode *modes; 58 59 /** @num_modes: Number of elements in modes array. */ 60 unsigned int num_modes; 61 62 /** 63 * @timings: Pointer to array of display timings 64 * 65 * NOTE: cannot be used with "modes" and also these will be used to 66 * validate a device tree override if one is present. 67 */ 68 const struct display_timing *timings; 69 70 /** @num_timings: Number of elements in timings array. */ 71 unsigned int num_timings; 72 73 /** @bpc: Bits per color. */ 74 unsigned int bpc; 75 76 /** @size: Structure containing the physical size of this panel. */ 77 struct { 78 /** 79 * @size.width: Width (in mm) of the active display area. 80 */ 81 unsigned int width; 82 83 /** 84 * @size.height: Height (in mm) of the active display area. 85 */ 86 unsigned int height; 87 } size; 88 89 /** @delay: Structure containing various delay values for this panel. */ 90 struct { 91 /** 92 * @delay.prepare: Time for the panel to become ready. 93 * 94 * The time (in milliseconds) that it takes for the panel to 95 * become ready and start receiving video data 96 */ 97 unsigned int prepare; 98 99 /** 100 * @delay.enable: Time for the panel to display a valid frame. 101 * 102 * The time (in milliseconds) that it takes for the panel to 103 * display the first valid frame after starting to receive 104 * video data. 105 */ 106 unsigned int enable; 107 108 /** 109 * @delay.disable: Time for the panel to turn the display off. 110 * 111 * The time (in milliseconds) that it takes for the panel to 112 * turn the display off (no content is visible). 113 */ 114 unsigned int disable; 115 116 /** 117 * @delay.unprepare: Time to power down completely. 118 * 119 * The time (in milliseconds) that it takes for the panel 120 * to power itself down completely. 121 * 122 * This time is used to prevent a future "prepare" from 123 * starting until at least this many milliseconds has passed. 124 * If at prepare time less time has passed since unprepare 125 * finished, the driver waits for the remaining time. 126 */ 127 unsigned int unprepare; 128 } delay; 129 130 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 131 u32 bus_format; 132 133 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 134 u32 bus_flags; 135 136 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 137 int connector_type; 138 }; 139 140 struct panel_desc_dsi { 141 struct panel_desc desc; 142 143 unsigned long flags; 144 enum mipi_dsi_pixel_format format; 145 unsigned int lanes; 146 }; 147 148 struct panel_simple { 149 struct drm_panel base; 150 151 ktime_t unprepared_time; 152 153 const struct panel_desc *desc; 154 155 struct regulator *supply; 156 struct i2c_adapter *ddc; 157 158 struct gpio_desc *enable_gpio; 159 160 const struct drm_edid *drm_edid; 161 162 struct drm_display_mode override_mode; 163 164 enum drm_panel_orientation orientation; 165 }; 166 167 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 168 { 169 return container_of(panel, struct panel_simple, base); 170 } 171 172 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 173 struct drm_connector *connector) 174 { 175 struct drm_display_mode *mode; 176 unsigned int i, num = 0; 177 178 for (i = 0; i < panel->desc->num_timings; i++) { 179 const struct display_timing *dt = &panel->desc->timings[i]; 180 struct videomode vm; 181 182 videomode_from_timing(dt, &vm); 183 mode = drm_mode_create(connector->dev); 184 if (!mode) { 185 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 186 dt->hactive.typ, dt->vactive.typ); 187 continue; 188 } 189 190 drm_display_mode_from_videomode(&vm, mode); 191 192 mode->type |= DRM_MODE_TYPE_DRIVER; 193 194 if (panel->desc->num_timings == 1) 195 mode->type |= DRM_MODE_TYPE_PREFERRED; 196 197 drm_mode_probed_add(connector, mode); 198 num++; 199 } 200 201 return num; 202 } 203 204 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 205 struct drm_connector *connector) 206 { 207 struct drm_display_mode *mode; 208 unsigned int i, num = 0; 209 210 for (i = 0; i < panel->desc->num_modes; i++) { 211 const struct drm_display_mode *m = &panel->desc->modes[i]; 212 213 mode = drm_mode_duplicate(connector->dev, m); 214 if (!mode) { 215 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 216 m->hdisplay, m->vdisplay, 217 drm_mode_vrefresh(m)); 218 continue; 219 } 220 221 mode->type |= DRM_MODE_TYPE_DRIVER; 222 223 if (panel->desc->num_modes == 1) 224 mode->type |= DRM_MODE_TYPE_PREFERRED; 225 226 drm_mode_set_name(mode); 227 228 drm_mode_probed_add(connector, mode); 229 num++; 230 } 231 232 return num; 233 } 234 235 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 236 struct drm_connector *connector) 237 { 238 struct drm_display_mode *mode; 239 bool has_override = panel->override_mode.type; 240 unsigned int num = 0; 241 242 if (!panel->desc) 243 return 0; 244 245 if (has_override) { 246 mode = drm_mode_duplicate(connector->dev, 247 &panel->override_mode); 248 if (mode) { 249 drm_mode_probed_add(connector, mode); 250 num = 1; 251 } else { 252 dev_err(panel->base.dev, "failed to add override mode\n"); 253 } 254 } 255 256 /* Only add timings if override was not there or failed to validate */ 257 if (num == 0 && panel->desc->num_timings) 258 num = panel_simple_get_timings_modes(panel, connector); 259 260 /* 261 * Only add fixed modes if timings/override added no mode. 262 * 263 * We should only ever have either the display timings specified 264 * or a fixed mode. Anything else is rather bogus. 265 */ 266 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 267 if (num == 0) 268 num = panel_simple_get_display_modes(panel, connector); 269 270 connector->display_info.bpc = panel->desc->bpc; 271 connector->display_info.width_mm = panel->desc->size.width; 272 connector->display_info.height_mm = panel->desc->size.height; 273 if (panel->desc->bus_format) 274 drm_display_info_set_bus_formats(&connector->display_info, 275 &panel->desc->bus_format, 1); 276 connector->display_info.bus_flags = panel->desc->bus_flags; 277 278 return num; 279 } 280 281 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 282 { 283 ktime_t now_ktime, min_ktime; 284 285 if (!min_ms) 286 return; 287 288 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 289 now_ktime = ktime_get_boottime(); 290 291 if (ktime_before(now_ktime, min_ktime)) 292 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 293 } 294 295 static int panel_simple_disable(struct drm_panel *panel) 296 { 297 struct panel_simple *p = to_panel_simple(panel); 298 299 if (p->desc->delay.disable) 300 msleep(p->desc->delay.disable); 301 302 return 0; 303 } 304 305 static int panel_simple_suspend(struct device *dev) 306 { 307 struct panel_simple *p = dev_get_drvdata(dev); 308 309 gpiod_set_value_cansleep(p->enable_gpio, 0); 310 regulator_disable(p->supply); 311 p->unprepared_time = ktime_get_boottime(); 312 313 drm_edid_free(p->drm_edid); 314 p->drm_edid = NULL; 315 316 return 0; 317 } 318 319 static int panel_simple_unprepare(struct drm_panel *panel) 320 { 321 int ret; 322 323 pm_runtime_mark_last_busy(panel->dev); 324 ret = pm_runtime_put_autosuspend(panel->dev); 325 if (ret < 0) 326 return ret; 327 328 return 0; 329 } 330 331 static int panel_simple_resume(struct device *dev) 332 { 333 struct panel_simple *p = dev_get_drvdata(dev); 334 int err; 335 336 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 337 338 err = regulator_enable(p->supply); 339 if (err < 0) { 340 dev_err(dev, "failed to enable supply: %d\n", err); 341 return err; 342 } 343 344 gpiod_set_value_cansleep(p->enable_gpio, 1); 345 346 if (p->desc->delay.prepare) 347 msleep(p->desc->delay.prepare); 348 349 return 0; 350 } 351 352 static int panel_simple_prepare(struct drm_panel *panel) 353 { 354 int ret; 355 356 ret = pm_runtime_get_sync(panel->dev); 357 if (ret < 0) { 358 pm_runtime_put_autosuspend(panel->dev); 359 return ret; 360 } 361 362 return 0; 363 } 364 365 static int panel_simple_enable(struct drm_panel *panel) 366 { 367 struct panel_simple *p = to_panel_simple(panel); 368 369 if (p->desc->delay.enable) 370 msleep(p->desc->delay.enable); 371 372 return 0; 373 } 374 375 static int panel_simple_get_modes(struct drm_panel *panel, 376 struct drm_connector *connector) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 int num = 0; 380 381 /* probe EDID if a DDC bus is available */ 382 if (p->ddc) { 383 pm_runtime_get_sync(panel->dev); 384 385 if (!p->drm_edid) 386 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 387 388 drm_edid_connector_update(connector, p->drm_edid); 389 390 num += drm_edid_connector_add_modes(connector); 391 392 pm_runtime_mark_last_busy(panel->dev); 393 pm_runtime_put_autosuspend(panel->dev); 394 } 395 396 /* add hard-coded panel modes */ 397 num += panel_simple_get_non_edid_modes(p, connector); 398 399 /* 400 * TODO: Remove once all drm drivers call 401 * drm_connector_set_orientation_from_panel() 402 */ 403 drm_connector_set_panel_orientation(connector, p->orientation); 404 405 return num; 406 } 407 408 static int panel_simple_get_timings(struct drm_panel *panel, 409 unsigned int num_timings, 410 struct display_timing *timings) 411 { 412 struct panel_simple *p = to_panel_simple(panel); 413 unsigned int i; 414 415 if (p->desc->num_timings < num_timings) 416 num_timings = p->desc->num_timings; 417 418 if (timings) 419 for (i = 0; i < num_timings; i++) 420 timings[i] = p->desc->timings[i]; 421 422 return p->desc->num_timings; 423 } 424 425 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 426 { 427 struct panel_simple *p = to_panel_simple(panel); 428 429 return p->orientation; 430 } 431 432 static const struct drm_panel_funcs panel_simple_funcs = { 433 .disable = panel_simple_disable, 434 .unprepare = panel_simple_unprepare, 435 .prepare = panel_simple_prepare, 436 .enable = panel_simple_enable, 437 .get_modes = panel_simple_get_modes, 438 .get_orientation = panel_simple_get_orientation, 439 .get_timings = panel_simple_get_timings, 440 }; 441 442 static struct panel_desc *panel_dpi_probe(struct device *dev) 443 { 444 struct display_timing *timing; 445 const struct device_node *np; 446 struct panel_desc *desc; 447 unsigned int bus_flags; 448 struct videomode vm; 449 int ret; 450 451 np = dev->of_node; 452 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 453 if (!desc) 454 return ERR_PTR(-ENOMEM); 455 456 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 457 if (!timing) 458 return ERR_PTR(-ENOMEM); 459 460 ret = of_get_display_timing(np, "panel-timing", timing); 461 if (ret < 0) { 462 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 463 np); 464 return ERR_PTR(ret); 465 } 466 467 desc->timings = timing; 468 desc->num_timings = 1; 469 470 of_property_read_u32(np, "width-mm", &desc->size.width); 471 of_property_read_u32(np, "height-mm", &desc->size.height); 472 473 /* Extract bus_flags from display_timing */ 474 bus_flags = 0; 475 vm.flags = timing->flags; 476 drm_bus_flags_from_videomode(&vm, &bus_flags); 477 desc->bus_flags = bus_flags; 478 479 /* We do not know the connector for the DT node, so guess it */ 480 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 481 482 return desc; 483 } 484 485 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 486 (to_check->field.typ >= bounds->field.min && \ 487 to_check->field.typ <= bounds->field.max) 488 static void panel_simple_parse_panel_timing_node(struct device *dev, 489 struct panel_simple *panel, 490 const struct display_timing *ot) 491 { 492 const struct panel_desc *desc = panel->desc; 493 struct videomode vm; 494 unsigned int i; 495 496 if (WARN_ON(desc->num_modes)) { 497 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 498 return; 499 } 500 if (WARN_ON(!desc->num_timings)) { 501 dev_err(dev, "Reject override mode: no timings specified\n"); 502 return; 503 } 504 505 for (i = 0; i < panel->desc->num_timings; i++) { 506 const struct display_timing *dt = &panel->desc->timings[i]; 507 508 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 512 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 513 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 514 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 515 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 516 continue; 517 518 if (ot->flags != dt->flags) 519 continue; 520 521 videomode_from_timing(ot, &vm); 522 drm_display_mode_from_videomode(&vm, &panel->override_mode); 523 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 524 DRM_MODE_TYPE_PREFERRED; 525 break; 526 } 527 528 if (WARN_ON(!panel->override_mode.type)) 529 dev_err(dev, "Reject override mode: No display_timing found\n"); 530 } 531 532 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 533 struct panel_simple *panel) 534 { 535 int ret, bpc; 536 537 ret = drm_of_lvds_get_data_mapping(dev->of_node); 538 if (ret < 0) { 539 if (ret == -EINVAL) 540 dev_warn(dev, "Ignore invalid data-mapping property\n"); 541 542 /* 543 * Ignore non-existing or malformatted property, fallback to 544 * default data-mapping, and return 0. 545 */ 546 return 0; 547 } 548 549 switch (ret) { 550 default: 551 WARN_ON(1); 552 fallthrough; 553 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 554 fallthrough; 555 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 556 bpc = 8; 557 break; 558 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 559 bpc = 6; 560 } 561 562 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 563 struct panel_desc *override_desc; 564 565 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 566 if (!override_desc) 567 return -ENOMEM; 568 569 override_desc->bus_format = ret; 570 override_desc->bpc = bpc; 571 panel->desc = override_desc; 572 } 573 574 return 0; 575 } 576 577 static const struct panel_desc *panel_simple_get_desc(struct device *dev) 578 { 579 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI) && 580 dev_is_mipi_dsi(dev)) { 581 const struct panel_desc_dsi *dsi_desc; 582 583 dsi_desc = of_device_get_match_data(dev); 584 if (!dsi_desc) 585 return ERR_PTR(-ENODEV); 586 587 return &dsi_desc->desc; 588 } 589 590 if (dev_is_platform(dev)) { 591 const struct panel_desc *desc; 592 593 desc = of_device_get_match_data(dev); 594 if (!desc) { 595 /* 596 * panel-dpi probes without a descriptor and 597 * panel_dpi_probe() will initialize one for us 598 * based on the device tree. 599 */ 600 if (of_device_is_compatible(dev->of_node, "panel-dpi")) 601 return panel_dpi_probe(dev); 602 else 603 return ERR_PTR(-ENODEV); 604 } 605 606 return desc; 607 } 608 609 return ERR_PTR(-ENODEV); 610 } 611 612 static struct panel_simple *panel_simple_probe(struct device *dev) 613 { 614 const struct panel_desc *desc; 615 struct panel_simple *panel; 616 struct display_timing dt; 617 struct device_node *ddc; 618 int connector_type; 619 u32 bus_flags; 620 int err; 621 622 desc = panel_simple_get_desc(dev); 623 if (IS_ERR(desc)) 624 return ERR_CAST(desc); 625 626 connector_type = desc->connector_type; 627 /* Catch common mistakes for panels. */ 628 switch (connector_type) { 629 case 0: 630 dev_warn(dev, "Specify missing connector_type\n"); 631 connector_type = DRM_MODE_CONNECTOR_DPI; 632 break; 633 case DRM_MODE_CONNECTOR_LVDS: 634 WARN_ON(desc->bus_flags & 635 ~(DRM_BUS_FLAG_DE_LOW | 636 DRM_BUS_FLAG_DE_HIGH | 637 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 638 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 639 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 640 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 641 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 642 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 643 desc->bpc != 6); 644 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 645 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 646 desc->bpc != 8); 647 break; 648 case DRM_MODE_CONNECTOR_eDP: 649 dev_warn(dev, "eDP panels moved to panel-edp\n"); 650 return ERR_PTR(-EINVAL); 651 case DRM_MODE_CONNECTOR_DSI: 652 if (desc->bpc != 6 && desc->bpc != 8) 653 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 654 break; 655 case DRM_MODE_CONNECTOR_DPI: 656 bus_flags = DRM_BUS_FLAG_DE_LOW | 657 DRM_BUS_FLAG_DE_HIGH | 658 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 659 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 660 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 661 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 662 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 663 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 664 if (desc->bus_flags & ~bus_flags) 665 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 666 if (!(desc->bus_flags & bus_flags)) 667 dev_warn(dev, "Specify missing bus_flags\n"); 668 if (desc->bus_format == 0) 669 dev_warn(dev, "Specify missing bus_format\n"); 670 if (desc->bpc != 6 && desc->bpc != 8) 671 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 672 break; 673 default: 674 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 675 connector_type = DRM_MODE_CONNECTOR_DPI; 676 break; 677 } 678 679 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 680 &panel_simple_funcs, connector_type); 681 if (IS_ERR(panel)) 682 return ERR_CAST(panel); 683 684 panel->desc = desc; 685 686 panel->supply = devm_regulator_get(dev, "power"); 687 if (IS_ERR(panel->supply)) 688 return ERR_CAST(panel->supply); 689 690 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 691 GPIOD_OUT_LOW); 692 if (IS_ERR(panel->enable_gpio)) 693 return dev_err_cast_probe(dev, panel->enable_gpio, 694 "failed to request GPIO\n"); 695 696 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 697 if (err) { 698 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 699 return ERR_PTR(err); 700 } 701 702 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 703 if (ddc) { 704 panel->ddc = of_find_i2c_adapter_by_node(ddc); 705 of_node_put(ddc); 706 707 if (!panel->ddc) 708 return ERR_PTR(-EPROBE_DEFER); 709 } 710 711 if (!of_device_is_compatible(dev->of_node, "panel-dpi") && 712 !of_get_display_timing(dev->of_node, "panel-timing", &dt)) 713 panel_simple_parse_panel_timing_node(dev, panel, &dt); 714 715 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 716 /* Optional data-mapping property for overriding bus format */ 717 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 718 if (err) 719 goto free_ddc; 720 } 721 722 dev_set_drvdata(dev, panel); 723 724 /* 725 * We use runtime PM for prepare / unprepare since those power the panel 726 * on and off and those can be very slow operations. This is important 727 * to optimize powering the panel on briefly to read the EDID before 728 * fully enabling the panel. 729 */ 730 pm_runtime_enable(dev); 731 pm_runtime_set_autosuspend_delay(dev, 1000); 732 pm_runtime_use_autosuspend(dev); 733 734 err = drm_panel_of_backlight(&panel->base); 735 if (err) { 736 dev_err_probe(dev, err, "Could not find backlight\n"); 737 goto disable_pm_runtime; 738 } 739 740 drm_panel_add(&panel->base); 741 742 return panel; 743 744 disable_pm_runtime: 745 pm_runtime_dont_use_autosuspend(dev); 746 pm_runtime_disable(dev); 747 free_ddc: 748 if (panel->ddc) 749 put_device(&panel->ddc->dev); 750 751 return ERR_PTR(err); 752 } 753 754 static void panel_simple_shutdown(struct device *dev) 755 { 756 struct panel_simple *panel = dev_get_drvdata(dev); 757 758 /* 759 * NOTE: the following two calls don't really belong here. It is the 760 * responsibility of a correctly written DRM modeset driver to call 761 * drm_atomic_helper_shutdown() at shutdown time and that should 762 * cause the panel to be disabled / unprepared if needed. For now, 763 * however, we'll keep these calls due to the sheer number of 764 * different DRM modeset drivers used with panel-simple. Once we've 765 * confirmed that all DRM modeset drivers using this panel properly 766 * call drm_atomic_helper_shutdown() we can simply delete the two 767 * calls below. 768 * 769 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 770 * PANEL DRIVERS. 771 * 772 * FIXME: If we're still haven't figured out if all DRM modeset 773 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 774 * managed to make sure that DRM modeset drivers get their shutdown() 775 * callback before the panel's shutdown() callback (perhaps using 776 * device link), we could add a WARN_ON here to help move forward. 777 */ 778 if (panel->base.enabled) 779 drm_panel_disable(&panel->base); 780 if (panel->base.prepared) 781 drm_panel_unprepare(&panel->base); 782 } 783 784 static void panel_simple_remove(struct device *dev) 785 { 786 struct panel_simple *panel = dev_get_drvdata(dev); 787 788 drm_panel_remove(&panel->base); 789 panel_simple_shutdown(dev); 790 791 pm_runtime_dont_use_autosuspend(dev); 792 pm_runtime_disable(dev); 793 if (panel->ddc) 794 put_device(&panel->ddc->dev); 795 } 796 797 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 798 .clock = 71100, 799 .hdisplay = 1280, 800 .hsync_start = 1280 + 40, 801 .hsync_end = 1280 + 40 + 80, 802 .htotal = 1280 + 40 + 80 + 40, 803 .vdisplay = 800, 804 .vsync_start = 800 + 3, 805 .vsync_end = 800 + 3 + 10, 806 .vtotal = 800 + 3 + 10 + 10, 807 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 808 }; 809 810 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 811 .modes = &ire_am_1280800n3tzqw_t00h_mode, 812 .num_modes = 1, 813 .bpc = 8, 814 .size = { 815 .width = 217, 816 .height = 136, 817 }, 818 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 819 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 820 .connector_type = DRM_MODE_CONNECTOR_LVDS, 821 }; 822 823 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 824 .clock = 9000, 825 .hdisplay = 480, 826 .hsync_start = 480 + 2, 827 .hsync_end = 480 + 2 + 41, 828 .htotal = 480 + 2 + 41 + 2, 829 .vdisplay = 272, 830 .vsync_start = 272 + 2, 831 .vsync_end = 272 + 2 + 10, 832 .vtotal = 272 + 2 + 10 + 2, 833 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 834 }; 835 836 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 837 .modes = &ire_am_480272h3tmqw_t01h_mode, 838 .num_modes = 1, 839 .bpc = 8, 840 .size = { 841 .width = 99, 842 .height = 58, 843 }, 844 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 845 }; 846 847 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 848 .clock = 33333, 849 .hdisplay = 800, 850 .hsync_start = 800 + 0, 851 .hsync_end = 800 + 0 + 255, 852 .htotal = 800 + 0 + 255 + 0, 853 .vdisplay = 480, 854 .vsync_start = 480 + 2, 855 .vsync_end = 480 + 2 + 45, 856 .vtotal = 480 + 2 + 45 + 0, 857 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 858 }; 859 860 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 861 .pixelclock = { 29930000, 33260000, 36590000 }, 862 .hactive = { 800, 800, 800 }, 863 .hfront_porch = { 1, 40, 168 }, 864 .hback_porch = { 88, 88, 88 }, 865 .hsync_len = { 1, 128, 128 }, 866 .vactive = { 480, 480, 480 }, 867 .vfront_porch = { 1, 35, 37 }, 868 .vback_porch = { 8, 8, 8 }, 869 .vsync_len = { 1, 2, 2 }, 870 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 871 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 872 DISPLAY_FLAGS_SYNC_POSEDGE, 873 }; 874 875 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 876 .timings = &ire_am_800480l1tmqw_t00h_timing, 877 .num_timings = 1, 878 .bpc = 8, 879 .size = { 880 .width = 111, 881 .height = 67, 882 }, 883 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 884 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 885 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 886 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 887 .connector_type = DRM_MODE_CONNECTOR_DPI, 888 }; 889 890 static const struct panel_desc ampire_am800480r3tmqwa1h = { 891 .modes = &ire_am800480r3tmqwa1h_mode, 892 .num_modes = 1, 893 .bpc = 6, 894 .size = { 895 .width = 152, 896 .height = 91, 897 }, 898 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 899 }; 900 901 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 902 .pixelclock = { 34500000, 39600000, 50400000 }, 903 .hactive = { 800, 800, 800 }, 904 .hfront_porch = { 12, 112, 312 }, 905 .hback_porch = { 87, 87, 48 }, 906 .hsync_len = { 1, 1, 40 }, 907 .vactive = { 600, 600, 600 }, 908 .vfront_porch = { 1, 21, 61 }, 909 .vback_porch = { 38, 38, 19 }, 910 .vsync_len = { 1, 1, 20 }, 911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 913 DISPLAY_FLAGS_SYNC_POSEDGE, 914 }; 915 916 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 917 .timings = &ire_am800600p5tmqw_tb8h_timing, 918 .num_timings = 1, 919 .bpc = 6, 920 .size = { 921 .width = 162, 922 .height = 122, 923 }, 924 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 925 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 926 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 927 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 928 .connector_type = DRM_MODE_CONNECTOR_DPI, 929 }; 930 931 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 932 .pixelclock = { 26400000, 33300000, 46800000 }, 933 .hactive = { 800, 800, 800 }, 934 .hfront_porch = { 16, 210, 354 }, 935 .hback_porch = { 45, 36, 6 }, 936 .hsync_len = { 1, 10, 40 }, 937 .vactive = { 480, 480, 480 }, 938 .vfront_porch = { 7, 22, 147 }, 939 .vback_porch = { 22, 13, 3 }, 940 .vsync_len = { 1, 10, 20 }, 941 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 942 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 943 }; 944 945 static const struct panel_desc armadeus_st0700_adapt = { 946 .timings = &santek_st0700i5y_rbslw_f_timing, 947 .num_timings = 1, 948 .bpc = 6, 949 .size = { 950 .width = 154, 951 .height = 86, 952 }, 953 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 954 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 955 }; 956 957 static const struct drm_display_mode auo_b101aw03_mode = { 958 .clock = 51450, 959 .hdisplay = 1024, 960 .hsync_start = 1024 + 156, 961 .hsync_end = 1024 + 156 + 8, 962 .htotal = 1024 + 156 + 8 + 156, 963 .vdisplay = 600, 964 .vsync_start = 600 + 16, 965 .vsync_end = 600 + 16 + 6, 966 .vtotal = 600 + 16 + 6 + 16, 967 }; 968 969 static const struct panel_desc auo_b101aw03 = { 970 .modes = &auo_b101aw03_mode, 971 .num_modes = 1, 972 .bpc = 6, 973 .size = { 974 .width = 223, 975 .height = 125, 976 }, 977 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 978 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 979 .connector_type = DRM_MODE_CONNECTOR_LVDS, 980 }; 981 982 static const struct drm_display_mode auo_b101xtn01_mode = { 983 .clock = 72000, 984 .hdisplay = 1366, 985 .hsync_start = 1366 + 20, 986 .hsync_end = 1366 + 20 + 70, 987 .htotal = 1366 + 20 + 70, 988 .vdisplay = 768, 989 .vsync_start = 768 + 14, 990 .vsync_end = 768 + 14 + 42, 991 .vtotal = 768 + 14 + 42, 992 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 993 }; 994 995 static const struct panel_desc auo_b101xtn01 = { 996 .modes = &auo_b101xtn01_mode, 997 .num_modes = 1, 998 .bpc = 6, 999 .size = { 1000 .width = 223, 1001 .height = 125, 1002 }, 1003 }; 1004 1005 static const struct drm_display_mode auo_b116xw03_mode = { 1006 .clock = 70589, 1007 .hdisplay = 1366, 1008 .hsync_start = 1366 + 40, 1009 .hsync_end = 1366 + 40 + 40, 1010 .htotal = 1366 + 40 + 40 + 32, 1011 .vdisplay = 768, 1012 .vsync_start = 768 + 10, 1013 .vsync_end = 768 + 10 + 12, 1014 .vtotal = 768 + 10 + 12 + 6, 1015 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1016 }; 1017 1018 static const struct panel_desc auo_b116xw03 = { 1019 .modes = &auo_b116xw03_mode, 1020 .num_modes = 1, 1021 .bpc = 6, 1022 .size = { 1023 .width = 256, 1024 .height = 144, 1025 }, 1026 .delay = { 1027 .prepare = 1, 1028 .enable = 200, 1029 .disable = 200, 1030 .unprepare = 500, 1031 }, 1032 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1033 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1034 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1035 }; 1036 1037 static const struct display_timing auo_g070vvn01_timings = { 1038 .pixelclock = { 33300000, 34209000, 45000000 }, 1039 .hactive = { 800, 800, 800 }, 1040 .hfront_porch = { 20, 40, 200 }, 1041 .hback_porch = { 87, 40, 1 }, 1042 .hsync_len = { 1, 48, 87 }, 1043 .vactive = { 480, 480, 480 }, 1044 .vfront_porch = { 5, 13, 200 }, 1045 .vback_porch = { 31, 31, 29 }, 1046 .vsync_len = { 1, 1, 3 }, 1047 }; 1048 1049 static const struct panel_desc auo_g070vvn01 = { 1050 .timings = &auo_g070vvn01_timings, 1051 .num_timings = 1, 1052 .bpc = 8, 1053 .size = { 1054 .width = 152, 1055 .height = 91, 1056 }, 1057 .delay = { 1058 .prepare = 200, 1059 .enable = 50, 1060 .disable = 50, 1061 .unprepare = 1000, 1062 }, 1063 }; 1064 1065 static const struct display_timing auo_g101evn010_timing = { 1066 .pixelclock = { 64000000, 68930000, 85000000 }, 1067 .hactive = { 1280, 1280, 1280 }, 1068 .hfront_porch = { 8, 64, 256 }, 1069 .hback_porch = { 8, 64, 256 }, 1070 .hsync_len = { 40, 168, 767 }, 1071 .vactive = { 800, 800, 800 }, 1072 .vfront_porch = { 4, 8, 100 }, 1073 .vback_porch = { 4, 8, 100 }, 1074 .vsync_len = { 8, 16, 223 }, 1075 }; 1076 1077 static const struct panel_desc auo_g101evn010 = { 1078 .timings = &auo_g101evn010_timing, 1079 .num_timings = 1, 1080 .bpc = 6, 1081 .size = { 1082 .width = 216, 1083 .height = 135, 1084 }, 1085 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1086 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1087 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1088 }; 1089 1090 static const struct drm_display_mode auo_g104sn02_mode = { 1091 .clock = 40000, 1092 .hdisplay = 800, 1093 .hsync_start = 800 + 40, 1094 .hsync_end = 800 + 40 + 216, 1095 .htotal = 800 + 40 + 216 + 128, 1096 .vdisplay = 600, 1097 .vsync_start = 600 + 10, 1098 .vsync_end = 600 + 10 + 35, 1099 .vtotal = 600 + 10 + 35 + 2, 1100 }; 1101 1102 static const struct panel_desc auo_g104sn02 = { 1103 .modes = &auo_g104sn02_mode, 1104 .num_modes = 1, 1105 .bpc = 8, 1106 .size = { 1107 .width = 211, 1108 .height = 158, 1109 }, 1110 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1111 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1112 }; 1113 1114 static const struct drm_display_mode auo_g104stn01_mode = { 1115 .clock = 40000, 1116 .hdisplay = 800, 1117 .hsync_start = 800 + 40, 1118 .hsync_end = 800 + 40 + 88, 1119 .htotal = 800 + 40 + 88 + 128, 1120 .vdisplay = 600, 1121 .vsync_start = 600 + 1, 1122 .vsync_end = 600 + 1 + 23, 1123 .vtotal = 600 + 1 + 23 + 4, 1124 }; 1125 1126 static const struct panel_desc auo_g104stn01 = { 1127 .modes = &auo_g104stn01_mode, 1128 .num_modes = 1, 1129 .bpc = 8, 1130 .size = { 1131 .width = 211, 1132 .height = 158, 1133 }, 1134 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1135 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1136 }; 1137 1138 static const struct display_timing auo_g121ean01_timing = { 1139 .pixelclock = { 60000000, 74400000, 90000000 }, 1140 .hactive = { 1280, 1280, 1280 }, 1141 .hfront_porch = { 20, 50, 100 }, 1142 .hback_porch = { 20, 50, 100 }, 1143 .hsync_len = { 30, 100, 200 }, 1144 .vactive = { 800, 800, 800 }, 1145 .vfront_porch = { 2, 10, 25 }, 1146 .vback_porch = { 2, 10, 25 }, 1147 .vsync_len = { 4, 18, 50 }, 1148 }; 1149 1150 static const struct panel_desc auo_g121ean01 = { 1151 .timings = &auo_g121ean01_timing, 1152 .num_timings = 1, 1153 .bpc = 8, 1154 .size = { 1155 .width = 261, 1156 .height = 163, 1157 }, 1158 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1159 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1160 }; 1161 1162 static const struct display_timing auo_g133han01_timings = { 1163 .pixelclock = { 134000000, 141200000, 149000000 }, 1164 .hactive = { 1920, 1920, 1920 }, 1165 .hfront_porch = { 39, 58, 77 }, 1166 .hback_porch = { 59, 88, 117 }, 1167 .hsync_len = { 28, 42, 56 }, 1168 .vactive = { 1080, 1080, 1080 }, 1169 .vfront_porch = { 3, 8, 11 }, 1170 .vback_porch = { 5, 14, 19 }, 1171 .vsync_len = { 4, 14, 19 }, 1172 }; 1173 1174 static const struct panel_desc auo_g133han01 = { 1175 .timings = &auo_g133han01_timings, 1176 .num_timings = 1, 1177 .bpc = 8, 1178 .size = { 1179 .width = 293, 1180 .height = 165, 1181 }, 1182 .delay = { 1183 .prepare = 200, 1184 .enable = 50, 1185 .disable = 50, 1186 .unprepare = 1000, 1187 }, 1188 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1189 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1190 }; 1191 1192 static const struct display_timing auo_g156han04_timings = { 1193 .pixelclock = { 137000000, 141000000, 146000000 }, 1194 .hactive = { 1920, 1920, 1920 }, 1195 .hfront_porch = { 60, 60, 60 }, 1196 .hback_porch = { 90, 92, 111 }, 1197 .hsync_len = { 32, 32, 32 }, 1198 .vactive = { 1080, 1080, 1080 }, 1199 .vfront_porch = { 12, 12, 12 }, 1200 .vback_porch = { 24, 36, 56 }, 1201 .vsync_len = { 8, 8, 8 }, 1202 }; 1203 1204 static const struct panel_desc auo_g156han04 = { 1205 .timings = &auo_g156han04_timings, 1206 .num_timings = 1, 1207 .bpc = 8, 1208 .size = { 1209 .width = 344, 1210 .height = 194, 1211 }, 1212 .delay = { 1213 .prepare = 50, /* T2 */ 1214 .enable = 200, /* T3 */ 1215 .disable = 110, /* T10 */ 1216 .unprepare = 1000, /* T13 */ 1217 }, 1218 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1219 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1220 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1221 }; 1222 1223 static const struct drm_display_mode auo_g156xtn01_mode = { 1224 .clock = 76000, 1225 .hdisplay = 1366, 1226 .hsync_start = 1366 + 33, 1227 .hsync_end = 1366 + 33 + 67, 1228 .htotal = 1560, 1229 .vdisplay = 768, 1230 .vsync_start = 768 + 4, 1231 .vsync_end = 768 + 4 + 4, 1232 .vtotal = 806, 1233 }; 1234 1235 static const struct panel_desc auo_g156xtn01 = { 1236 .modes = &auo_g156xtn01_mode, 1237 .num_modes = 1, 1238 .bpc = 8, 1239 .size = { 1240 .width = 344, 1241 .height = 194, 1242 }, 1243 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1244 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1245 }; 1246 1247 static const struct display_timing auo_g185han01_timings = { 1248 .pixelclock = { 120000000, 144000000, 175000000 }, 1249 .hactive = { 1920, 1920, 1920 }, 1250 .hfront_porch = { 36, 120, 148 }, 1251 .hback_porch = { 24, 88, 108 }, 1252 .hsync_len = { 20, 48, 64 }, 1253 .vactive = { 1080, 1080, 1080 }, 1254 .vfront_porch = { 6, 10, 40 }, 1255 .vback_porch = { 2, 5, 20 }, 1256 .vsync_len = { 2, 5, 20 }, 1257 }; 1258 1259 static const struct panel_desc auo_g185han01 = { 1260 .timings = &auo_g185han01_timings, 1261 .num_timings = 1, 1262 .bpc = 8, 1263 .size = { 1264 .width = 409, 1265 .height = 230, 1266 }, 1267 .delay = { 1268 .prepare = 50, 1269 .enable = 200, 1270 .disable = 110, 1271 .unprepare = 1000, 1272 }, 1273 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1274 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1275 }; 1276 1277 static const struct display_timing auo_g190ean01_timings = { 1278 .pixelclock = { 90000000, 108000000, 135000000 }, 1279 .hactive = { 1280, 1280, 1280 }, 1280 .hfront_porch = { 126, 184, 1266 }, 1281 .hback_porch = { 84, 122, 844 }, 1282 .hsync_len = { 70, 102, 704 }, 1283 .vactive = { 1024, 1024, 1024 }, 1284 .vfront_porch = { 4, 26, 76 }, 1285 .vback_porch = { 2, 8, 25 }, 1286 .vsync_len = { 2, 8, 25 }, 1287 }; 1288 1289 static const struct panel_desc auo_g190ean01 = { 1290 .timings = &auo_g190ean01_timings, 1291 .num_timings = 1, 1292 .bpc = 8, 1293 .size = { 1294 .width = 376, 1295 .height = 301, 1296 }, 1297 .delay = { 1298 .prepare = 50, 1299 .enable = 200, 1300 .disable = 110, 1301 .unprepare = 1000, 1302 }, 1303 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1304 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1305 }; 1306 1307 static const struct display_timing auo_p238han01_timings = { 1308 .pixelclock = { 107400000, 142400000, 180000000 }, 1309 .hactive = { 1920, 1920, 1920 }, 1310 .hfront_porch = { 30, 70, 650 }, 1311 .hback_porch = { 30, 70, 650 }, 1312 .hsync_len = { 20, 40, 136 }, 1313 .vactive = { 1080, 1080, 1080 }, 1314 .vfront_porch = { 5, 19, 318 }, 1315 .vback_porch = { 5, 19, 318 }, 1316 .vsync_len = { 4, 12, 120 }, 1317 }; 1318 1319 static const struct panel_desc auo_p238han01 = { 1320 .timings = &auo_p238han01_timings, 1321 .num_timings = 1, 1322 .bpc = 8, 1323 .size = { 1324 .width = 527, 1325 .height = 296, 1326 }, 1327 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1328 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1329 }; 1330 1331 static const struct display_timing auo_p320hvn03_timings = { 1332 .pixelclock = { 106000000, 148500000, 164000000 }, 1333 .hactive = { 1920, 1920, 1920 }, 1334 .hfront_porch = { 25, 50, 130 }, 1335 .hback_porch = { 25, 50, 130 }, 1336 .hsync_len = { 20, 40, 105 }, 1337 .vactive = { 1080, 1080, 1080 }, 1338 .vfront_porch = { 8, 17, 150 }, 1339 .vback_porch = { 8, 17, 150 }, 1340 .vsync_len = { 4, 11, 100 }, 1341 }; 1342 1343 static const struct panel_desc auo_p320hvn03 = { 1344 .timings = &auo_p320hvn03_timings, 1345 .num_timings = 1, 1346 .bpc = 8, 1347 .size = { 1348 .width = 698, 1349 .height = 393, 1350 }, 1351 .delay = { 1352 .prepare = 1, 1353 .enable = 450, 1354 .unprepare = 500, 1355 }, 1356 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1357 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1358 }; 1359 1360 static const struct drm_display_mode auo_t215hvn01_mode = { 1361 .clock = 148800, 1362 .hdisplay = 1920, 1363 .hsync_start = 1920 + 88, 1364 .hsync_end = 1920 + 88 + 44, 1365 .htotal = 1920 + 88 + 44 + 148, 1366 .vdisplay = 1080, 1367 .vsync_start = 1080 + 4, 1368 .vsync_end = 1080 + 4 + 5, 1369 .vtotal = 1080 + 4 + 5 + 36, 1370 }; 1371 1372 static const struct panel_desc auo_t215hvn01 = { 1373 .modes = &auo_t215hvn01_mode, 1374 .num_modes = 1, 1375 .bpc = 8, 1376 .size = { 1377 .width = 430, 1378 .height = 270, 1379 }, 1380 .delay = { 1381 .disable = 5, 1382 .unprepare = 1000, 1383 }, 1384 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1385 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1386 }; 1387 1388 static const struct drm_display_mode avic_tm070ddh03_mode = { 1389 .clock = 51200, 1390 .hdisplay = 1024, 1391 .hsync_start = 1024 + 160, 1392 .hsync_end = 1024 + 160 + 4, 1393 .htotal = 1024 + 160 + 4 + 156, 1394 .vdisplay = 600, 1395 .vsync_start = 600 + 17, 1396 .vsync_end = 600 + 17 + 1, 1397 .vtotal = 600 + 17 + 1 + 17, 1398 }; 1399 1400 static const struct panel_desc avic_tm070ddh03 = { 1401 .modes = &avic_tm070ddh03_mode, 1402 .num_modes = 1, 1403 .bpc = 8, 1404 .size = { 1405 .width = 154, 1406 .height = 90, 1407 }, 1408 .delay = { 1409 .prepare = 20, 1410 .enable = 200, 1411 .disable = 200, 1412 }, 1413 }; 1414 1415 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1416 .clock = 30000, 1417 .hdisplay = 800, 1418 .hsync_start = 800 + 40, 1419 .hsync_end = 800 + 40 + 48, 1420 .htotal = 800 + 40 + 48 + 40, 1421 .vdisplay = 480, 1422 .vsync_start = 480 + 13, 1423 .vsync_end = 480 + 13 + 3, 1424 .vtotal = 480 + 13 + 3 + 29, 1425 }; 1426 1427 static const struct panel_desc bananapi_s070wv20_ct16 = { 1428 .modes = &bananapi_s070wv20_ct16_mode, 1429 .num_modes = 1, 1430 .bpc = 6, 1431 .size = { 1432 .width = 154, 1433 .height = 86, 1434 }, 1435 }; 1436 1437 static const struct display_timing boe_av101hdt_a10_timing = { 1438 .pixelclock = { 74210000, 75330000, 76780000, }, 1439 .hactive = { 1280, 1280, 1280, }, 1440 .hfront_porch = { 10, 42, 33, }, 1441 .hback_porch = { 10, 18, 33, }, 1442 .hsync_len = { 30, 10, 30, }, 1443 .vactive = { 720, 720, 720, }, 1444 .vfront_porch = { 200, 183, 200, }, 1445 .vback_porch = { 8, 8, 8, }, 1446 .vsync_len = { 2, 19, 2, }, 1447 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1448 }; 1449 1450 static const struct panel_desc boe_av101hdt_a10 = { 1451 .timings = &boe_av101hdt_a10_timing, 1452 .num_timings = 1, 1453 .bpc = 8, 1454 .size = { 1455 .width = 224, 1456 .height = 126, 1457 }, 1458 .delay = { 1459 .enable = 50, 1460 .disable = 50, 1461 }, 1462 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1463 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1464 }; 1465 1466 static const struct display_timing boe_av123z7m_n17_timing = { 1467 .pixelclock = { 86600000, 88000000, 90800000, }, 1468 .hactive = { 1920, 1920, 1920, }, 1469 .hfront_porch = { 10, 10, 10, }, 1470 .hback_porch = { 10, 10, 10, }, 1471 .hsync_len = { 9, 12, 25, }, 1472 .vactive = { 720, 720, 720, }, 1473 .vfront_porch = { 7, 10, 13, }, 1474 .vback_porch = { 7, 10, 13, }, 1475 .vsync_len = { 7, 11, 14, }, 1476 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1477 }; 1478 1479 static const struct panel_desc boe_av123z7m_n17 = { 1480 .timings = &boe_av123z7m_n17_timing, 1481 .bpc = 8, 1482 .num_timings = 1, 1483 .size = { 1484 .width = 292, 1485 .height = 110, 1486 }, 1487 .delay = { 1488 .prepare = 50, 1489 .disable = 50, 1490 }, 1491 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1492 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1493 }; 1494 1495 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1496 .clock = 78945, 1497 .hdisplay = 1280, 1498 .hsync_start = 1280 + 0, 1499 .hsync_end = 1280 + 0 + 2, 1500 .htotal = 1280 + 62 + 0 + 2, 1501 .vdisplay = 800, 1502 .vsync_start = 800 + 8, 1503 .vsync_end = 800 + 8 + 2, 1504 .vtotal = 800 + 6 + 8 + 2, 1505 }; 1506 1507 static const struct panel_desc boe_bp082wx1_100 = { 1508 .modes = &boe_bp101wx1_100_mode, 1509 .num_modes = 1, 1510 .bpc = 8, 1511 .size = { 1512 .width = 177, 1513 .height = 110, 1514 }, 1515 .delay = { 1516 .enable = 50, 1517 .disable = 50, 1518 }, 1519 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1520 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1521 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1522 }; 1523 1524 static const struct panel_desc boe_bp101wx1_100 = { 1525 .modes = &boe_bp101wx1_100_mode, 1526 .num_modes = 1, 1527 .bpc = 8, 1528 .size = { 1529 .width = 217, 1530 .height = 136, 1531 }, 1532 .delay = { 1533 .enable = 50, 1534 .disable = 50, 1535 }, 1536 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1537 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1538 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1539 }; 1540 1541 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1542 .pixelclock = { 69922000, 71000000, 72293000 }, 1543 .hactive = { 1280, 1280, 1280 }, 1544 .hfront_porch = { 48, 48, 48 }, 1545 .hback_porch = { 80, 80, 80 }, 1546 .hsync_len = { 32, 32, 32 }, 1547 .vactive = { 800, 800, 800 }, 1548 .vfront_porch = { 3, 3, 3 }, 1549 .vback_porch = { 14, 14, 14 }, 1550 .vsync_len = { 6, 6, 6 }, 1551 }; 1552 1553 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1554 .timings = &boe_ev121wxm_n10_1850_timing, 1555 .num_timings = 1, 1556 .bpc = 8, 1557 .size = { 1558 .width = 261, 1559 .height = 163, 1560 }, 1561 .delay = { 1562 .prepare = 9, 1563 .enable = 300, 1564 .unprepare = 300, 1565 .disable = 560, 1566 }, 1567 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1568 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1569 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1570 }; 1571 1572 static const struct drm_display_mode boe_hv070wsa_mode = { 1573 .clock = 42105, 1574 .hdisplay = 1024, 1575 .hsync_start = 1024 + 30, 1576 .hsync_end = 1024 + 30 + 30, 1577 .htotal = 1024 + 30 + 30 + 30, 1578 .vdisplay = 600, 1579 .vsync_start = 600 + 10, 1580 .vsync_end = 600 + 10 + 10, 1581 .vtotal = 600 + 10 + 10 + 10, 1582 }; 1583 1584 static const struct panel_desc boe_hv070wsa = { 1585 .modes = &boe_hv070wsa_mode, 1586 .num_modes = 1, 1587 .bpc = 8, 1588 .size = { 1589 .width = 154, 1590 .height = 90, 1591 }, 1592 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1593 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1594 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1595 }; 1596 1597 static const struct display_timing cct_cmt430b19n00_timing = { 1598 .pixelclock = { 8000000, 9000000, 12000000 }, 1599 .hactive = { 480, 480, 480 }, 1600 .hfront_porch = { 2, 8, 75 }, 1601 .hback_porch = { 3, 43, 43 }, 1602 .hsync_len = { 2, 4, 75 }, 1603 .vactive = { 272, 272, 272 }, 1604 .vfront_porch = { 2, 8, 37 }, 1605 .vback_porch = { 2, 12, 12 }, 1606 .vsync_len = { 2, 4, 37 }, 1607 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1608 }; 1609 1610 static const struct panel_desc cct_cmt430b19n00 = { 1611 .timings = &cct_cmt430b19n00_timing, 1612 .num_timings = 1, 1613 .bpc = 8, 1614 .size = { 1615 .width = 95, 1616 .height = 53, 1617 }, 1618 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1619 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1620 .connector_type = DRM_MODE_CONNECTOR_DPI, 1621 }; 1622 1623 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1624 .clock = 9000, 1625 .hdisplay = 480, 1626 .hsync_start = 480 + 5, 1627 .hsync_end = 480 + 5 + 5, 1628 .htotal = 480 + 5 + 5 + 40, 1629 .vdisplay = 272, 1630 .vsync_start = 272 + 8, 1631 .vsync_end = 272 + 8 + 8, 1632 .vtotal = 272 + 8 + 8 + 8, 1633 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1634 }; 1635 1636 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1637 .modes = &cdtech_s043wq26h_ct7_mode, 1638 .num_modes = 1, 1639 .bpc = 8, 1640 .size = { 1641 .width = 95, 1642 .height = 54, 1643 }, 1644 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1645 }; 1646 1647 /* S070PWS19HP-FC21 2017/04/22 */ 1648 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1649 .clock = 51200, 1650 .hdisplay = 1024, 1651 .hsync_start = 1024 + 160, 1652 .hsync_end = 1024 + 160 + 20, 1653 .htotal = 1024 + 160 + 20 + 140, 1654 .vdisplay = 600, 1655 .vsync_start = 600 + 12, 1656 .vsync_end = 600 + 12 + 3, 1657 .vtotal = 600 + 12 + 3 + 20, 1658 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1659 }; 1660 1661 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1662 .modes = &cdtech_s070pws19hp_fc21_mode, 1663 .num_modes = 1, 1664 .bpc = 6, 1665 .size = { 1666 .width = 154, 1667 .height = 86, 1668 }, 1669 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1670 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1671 .connector_type = DRM_MODE_CONNECTOR_DPI, 1672 }; 1673 1674 /* S070SWV29HG-DC44 2017/09/21 */ 1675 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1676 .clock = 33300, 1677 .hdisplay = 800, 1678 .hsync_start = 800 + 210, 1679 .hsync_end = 800 + 210 + 2, 1680 .htotal = 800 + 210 + 2 + 44, 1681 .vdisplay = 480, 1682 .vsync_start = 480 + 22, 1683 .vsync_end = 480 + 22 + 2, 1684 .vtotal = 480 + 22 + 2 + 21, 1685 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1686 }; 1687 1688 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1689 .modes = &cdtech_s070swv29hg_dc44_mode, 1690 .num_modes = 1, 1691 .bpc = 6, 1692 .size = { 1693 .width = 154, 1694 .height = 86, 1695 }, 1696 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1697 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1698 .connector_type = DRM_MODE_CONNECTOR_DPI, 1699 }; 1700 1701 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1702 .clock = 35000, 1703 .hdisplay = 800, 1704 .hsync_start = 800 + 40, 1705 .hsync_end = 800 + 40 + 40, 1706 .htotal = 800 + 40 + 40 + 48, 1707 .vdisplay = 480, 1708 .vsync_start = 480 + 29, 1709 .vsync_end = 480 + 29 + 13, 1710 .vtotal = 480 + 29 + 13 + 3, 1711 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1712 }; 1713 1714 static const struct panel_desc cdtech_s070wv95_ct16 = { 1715 .modes = &cdtech_s070wv95_ct16_mode, 1716 .num_modes = 1, 1717 .bpc = 8, 1718 .size = { 1719 .width = 154, 1720 .height = 85, 1721 }, 1722 }; 1723 1724 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1725 .pixelclock = { 68900000, 71100000, 73400000 }, 1726 .hactive = { 1280, 1280, 1280 }, 1727 .hfront_porch = { 65, 80, 95 }, 1728 .hback_porch = { 64, 79, 94 }, 1729 .hsync_len = { 1, 1, 1 }, 1730 .vactive = { 800, 800, 800 }, 1731 .vfront_porch = { 7, 11, 14 }, 1732 .vback_porch = { 7, 11, 14 }, 1733 .vsync_len = { 1, 1, 1 }, 1734 .flags = DISPLAY_FLAGS_DE_HIGH, 1735 }; 1736 1737 static const struct panel_desc chefree_ch101olhlwh_002 = { 1738 .timings = &chefree_ch101olhlwh_002_timing, 1739 .num_timings = 1, 1740 .bpc = 8, 1741 .size = { 1742 .width = 217, 1743 .height = 135, 1744 }, 1745 .delay = { 1746 .enable = 200, 1747 .disable = 200, 1748 }, 1749 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1750 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1751 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1752 }; 1753 1754 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1755 .clock = 66770, 1756 .hdisplay = 800, 1757 .hsync_start = 800 + 49, 1758 .hsync_end = 800 + 49 + 33, 1759 .htotal = 800 + 49 + 33 + 17, 1760 .vdisplay = 1280, 1761 .vsync_start = 1280 + 1, 1762 .vsync_end = 1280 + 1 + 7, 1763 .vtotal = 1280 + 1 + 7 + 15, 1764 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1765 }; 1766 1767 static const struct panel_desc chunghwa_claa070wp03xg = { 1768 .modes = &chunghwa_claa070wp03xg_mode, 1769 .num_modes = 1, 1770 .bpc = 6, 1771 .size = { 1772 .width = 94, 1773 .height = 150, 1774 }, 1775 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1776 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1777 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1778 }; 1779 1780 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1781 .clock = 72070, 1782 .hdisplay = 1366, 1783 .hsync_start = 1366 + 58, 1784 .hsync_end = 1366 + 58 + 58, 1785 .htotal = 1366 + 58 + 58 + 58, 1786 .vdisplay = 768, 1787 .vsync_start = 768 + 4, 1788 .vsync_end = 768 + 4 + 4, 1789 .vtotal = 768 + 4 + 4 + 4, 1790 }; 1791 1792 static const struct panel_desc chunghwa_claa101wa01a = { 1793 .modes = &chunghwa_claa101wa01a_mode, 1794 .num_modes = 1, 1795 .bpc = 6, 1796 .size = { 1797 .width = 220, 1798 .height = 120, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1802 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1803 }; 1804 1805 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1806 .clock = 69300, 1807 .hdisplay = 1366, 1808 .hsync_start = 1366 + 48, 1809 .hsync_end = 1366 + 48 + 32, 1810 .htotal = 1366 + 48 + 32 + 20, 1811 .vdisplay = 768, 1812 .vsync_start = 768 + 16, 1813 .vsync_end = 768 + 16 + 8, 1814 .vtotal = 768 + 16 + 8 + 16, 1815 }; 1816 1817 static const struct panel_desc chunghwa_claa101wb01 = { 1818 .modes = &chunghwa_claa101wb01_mode, 1819 .num_modes = 1, 1820 .bpc = 6, 1821 .size = { 1822 .width = 223, 1823 .height = 125, 1824 }, 1825 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1826 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1827 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1828 }; 1829 1830 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1831 .pixelclock = { 5000000, 9000000, 12000000 }, 1832 .hactive = { 480, 480, 480 }, 1833 .hfront_porch = { 12, 12, 12 }, 1834 .hback_porch = { 12, 12, 12 }, 1835 .hsync_len = { 21, 21, 21 }, 1836 .vactive = { 272, 272, 272 }, 1837 .vfront_porch = { 4, 4, 4 }, 1838 .vback_porch = { 4, 4, 4 }, 1839 .vsync_len = { 8, 8, 8 }, 1840 }; 1841 1842 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1843 .timings = &dataimage_fg040346dsswbg04_timing, 1844 .num_timings = 1, 1845 .bpc = 8, 1846 .size = { 1847 .width = 95, 1848 .height = 54, 1849 }, 1850 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1851 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1852 .connector_type = DRM_MODE_CONNECTOR_DPI, 1853 }; 1854 1855 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1856 .pixelclock = { 68900000, 71110000, 73400000 }, 1857 .hactive = { 1280, 1280, 1280 }, 1858 .vactive = { 800, 800, 800 }, 1859 .hback_porch = { 100, 100, 100 }, 1860 .hfront_porch = { 100, 100, 100 }, 1861 .vback_porch = { 5, 5, 5 }, 1862 .vfront_porch = { 5, 5, 5 }, 1863 .hsync_len = { 24, 24, 24 }, 1864 .vsync_len = { 3, 3, 3 }, 1865 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1866 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1867 }; 1868 1869 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1870 .timings = &dataimage_fg1001l0dsswmg01_timing, 1871 .num_timings = 1, 1872 .bpc = 8, 1873 .size = { 1874 .width = 217, 1875 .height = 136, 1876 }, 1877 }; 1878 1879 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1880 .clock = 33260, 1881 .hdisplay = 800, 1882 .hsync_start = 800 + 40, 1883 .hsync_end = 800 + 40 + 128, 1884 .htotal = 800 + 40 + 128 + 88, 1885 .vdisplay = 480, 1886 .vsync_start = 480 + 10, 1887 .vsync_end = 480 + 10 + 2, 1888 .vtotal = 480 + 10 + 2 + 33, 1889 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1890 }; 1891 1892 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1893 .modes = &dataimage_scf0700c48ggu18_mode, 1894 .num_modes = 1, 1895 .bpc = 8, 1896 .size = { 1897 .width = 152, 1898 .height = 91, 1899 }, 1900 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1901 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1902 .connector_type = DRM_MODE_CONNECTOR_DPI, 1903 }; 1904 1905 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1906 .pixelclock = { 45000000, 51200000, 57000000 }, 1907 .hactive = { 1024, 1024, 1024 }, 1908 .hfront_porch = { 100, 106, 113 }, 1909 .hback_porch = { 100, 106, 113 }, 1910 .hsync_len = { 100, 108, 114 }, 1911 .vactive = { 600, 600, 600 }, 1912 .vfront_porch = { 8, 11, 15 }, 1913 .vback_porch = { 8, 11, 15 }, 1914 .vsync_len = { 9, 13, 15 }, 1915 .flags = DISPLAY_FLAGS_DE_HIGH, 1916 }; 1917 1918 static const struct panel_desc dlc_dlc0700yzg_1 = { 1919 .timings = &dlc_dlc0700yzg_1_timing, 1920 .num_timings = 1, 1921 .bpc = 6, 1922 .size = { 1923 .width = 154, 1924 .height = 86, 1925 }, 1926 .delay = { 1927 .prepare = 30, 1928 .enable = 200, 1929 .disable = 200, 1930 }, 1931 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1932 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1933 }; 1934 1935 static const struct display_timing dlc_dlc1010gig_timing = { 1936 .pixelclock = { 68900000, 71100000, 73400000 }, 1937 .hactive = { 1280, 1280, 1280 }, 1938 .hfront_porch = { 43, 53, 63 }, 1939 .hback_porch = { 43, 53, 63 }, 1940 .hsync_len = { 44, 54, 64 }, 1941 .vactive = { 800, 800, 800 }, 1942 .vfront_porch = { 5, 8, 11 }, 1943 .vback_porch = { 5, 8, 11 }, 1944 .vsync_len = { 5, 7, 11 }, 1945 .flags = DISPLAY_FLAGS_DE_HIGH, 1946 }; 1947 1948 static const struct panel_desc dlc_dlc1010gig = { 1949 .timings = &dlc_dlc1010gig_timing, 1950 .num_timings = 1, 1951 .bpc = 8, 1952 .size = { 1953 .width = 216, 1954 .height = 135, 1955 }, 1956 .delay = { 1957 .prepare = 60, 1958 .enable = 150, 1959 .disable = 100, 1960 .unprepare = 60, 1961 }, 1962 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1963 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1964 }; 1965 1966 static const struct drm_display_mode edt_et035012dm6_mode = { 1967 .clock = 6500, 1968 .hdisplay = 320, 1969 .hsync_start = 320 + 20, 1970 .hsync_end = 320 + 20 + 30, 1971 .htotal = 320 + 20 + 68, 1972 .vdisplay = 240, 1973 .vsync_start = 240 + 4, 1974 .vsync_end = 240 + 4 + 4, 1975 .vtotal = 240 + 4 + 4 + 14, 1976 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1977 }; 1978 1979 static const struct panel_desc edt_et035012dm6 = { 1980 .modes = &edt_et035012dm6_mode, 1981 .num_modes = 1, 1982 .bpc = 8, 1983 .size = { 1984 .width = 70, 1985 .height = 52, 1986 }, 1987 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1988 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1989 }; 1990 1991 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1992 .clock = 6520, 1993 .hdisplay = 320, 1994 .hsync_start = 320 + 20, 1995 .hsync_end = 320 + 20 + 68, 1996 .htotal = 320 + 20 + 68, 1997 .vdisplay = 240, 1998 .vsync_start = 240 + 4, 1999 .vsync_end = 240 + 4 + 18, 2000 .vtotal = 240 + 4 + 18, 2001 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2002 }; 2003 2004 static const struct panel_desc edt_etm0350g0dh6 = { 2005 .modes = &edt_etm0350g0dh6_mode, 2006 .num_modes = 1, 2007 .bpc = 6, 2008 .size = { 2009 .width = 70, 2010 .height = 53, 2011 }, 2012 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2013 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2014 .connector_type = DRM_MODE_CONNECTOR_DPI, 2015 }; 2016 2017 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 2018 .clock = 10870, 2019 .hdisplay = 480, 2020 .hsync_start = 480 + 8, 2021 .hsync_end = 480 + 8 + 4, 2022 .htotal = 480 + 8 + 4 + 41, 2023 2024 /* 2025 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 2026 * fb_align 2027 */ 2028 2029 .vdisplay = 288, 2030 .vsync_start = 288 + 2, 2031 .vsync_end = 288 + 2 + 4, 2032 .vtotal = 288 + 2 + 4 + 10, 2033 }; 2034 2035 static const struct panel_desc edt_etm043080dh6gp = { 2036 .modes = &edt_etm043080dh6gp_mode, 2037 .num_modes = 1, 2038 .bpc = 8, 2039 .size = { 2040 .width = 100, 2041 .height = 65, 2042 }, 2043 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2044 .connector_type = DRM_MODE_CONNECTOR_DPI, 2045 }; 2046 2047 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 2048 .clock = 9000, 2049 .hdisplay = 480, 2050 .hsync_start = 480 + 2, 2051 .hsync_end = 480 + 2 + 41, 2052 .htotal = 480 + 2 + 41 + 2, 2053 .vdisplay = 272, 2054 .vsync_start = 272 + 2, 2055 .vsync_end = 272 + 2 + 10, 2056 .vtotal = 272 + 2 + 10 + 2, 2057 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2058 }; 2059 2060 static const struct panel_desc edt_etm0430g0dh6 = { 2061 .modes = &edt_etm0430g0dh6_mode, 2062 .num_modes = 1, 2063 .bpc = 6, 2064 .size = { 2065 .width = 95, 2066 .height = 54, 2067 }, 2068 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2069 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2070 .connector_type = DRM_MODE_CONNECTOR_DPI, 2071 }; 2072 2073 static const struct drm_display_mode edt_et057090dhu_mode = { 2074 .clock = 25175, 2075 .hdisplay = 640, 2076 .hsync_start = 640 + 16, 2077 .hsync_end = 640 + 16 + 30, 2078 .htotal = 640 + 16 + 30 + 114, 2079 .vdisplay = 480, 2080 .vsync_start = 480 + 10, 2081 .vsync_end = 480 + 10 + 3, 2082 .vtotal = 480 + 10 + 3 + 32, 2083 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2084 }; 2085 2086 static const struct panel_desc edt_et057090dhu = { 2087 .modes = &edt_et057090dhu_mode, 2088 .num_modes = 1, 2089 .bpc = 6, 2090 .size = { 2091 .width = 115, 2092 .height = 86, 2093 }, 2094 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2095 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2096 .connector_type = DRM_MODE_CONNECTOR_DPI, 2097 }; 2098 2099 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2100 .clock = 33260, 2101 .hdisplay = 800, 2102 .hsync_start = 800 + 40, 2103 .hsync_end = 800 + 40 + 128, 2104 .htotal = 800 + 40 + 128 + 88, 2105 .vdisplay = 480, 2106 .vsync_start = 480 + 10, 2107 .vsync_end = 480 + 10 + 2, 2108 .vtotal = 480 + 10 + 2 + 33, 2109 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2110 }; 2111 2112 static const struct panel_desc edt_etm0700g0dh6 = { 2113 .modes = &edt_etm0700g0dh6_mode, 2114 .num_modes = 1, 2115 .bpc = 6, 2116 .size = { 2117 .width = 152, 2118 .height = 91, 2119 }, 2120 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2121 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2122 .connector_type = DRM_MODE_CONNECTOR_DPI, 2123 }; 2124 2125 static const struct panel_desc edt_etm0700g0bdh6 = { 2126 .modes = &edt_etm0700g0dh6_mode, 2127 .num_modes = 1, 2128 .bpc = 6, 2129 .size = { 2130 .width = 152, 2131 .height = 91, 2132 }, 2133 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2134 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2135 .connector_type = DRM_MODE_CONNECTOR_DPI, 2136 }; 2137 2138 static const struct display_timing edt_etml0700y5dha_timing = { 2139 .pixelclock = { 40800000, 51200000, 67200000 }, 2140 .hactive = { 1024, 1024, 1024 }, 2141 .hfront_porch = { 30, 106, 125 }, 2142 .hback_porch = { 30, 106, 125 }, 2143 .hsync_len = { 30, 108, 126 }, 2144 .vactive = { 600, 600, 600 }, 2145 .vfront_porch = { 3, 12, 67}, 2146 .vback_porch = { 3, 12, 67 }, 2147 .vsync_len = { 4, 11, 66 }, 2148 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2149 DISPLAY_FLAGS_DE_HIGH, 2150 }; 2151 2152 static const struct panel_desc edt_etml0700y5dha = { 2153 .timings = &edt_etml0700y5dha_timing, 2154 .num_timings = 1, 2155 .bpc = 8, 2156 .size = { 2157 .width = 155, 2158 .height = 86, 2159 }, 2160 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2161 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2162 }; 2163 2164 static const struct display_timing edt_etml1010g3dra_timing = { 2165 .pixelclock = { 66300000, 72400000, 78900000 }, 2166 .hactive = { 1280, 1280, 1280 }, 2167 .hfront_porch = { 12, 72, 132 }, 2168 .hback_porch = { 86, 86, 86 }, 2169 .hsync_len = { 2, 2, 2 }, 2170 .vactive = { 800, 800, 800 }, 2171 .vfront_porch = { 1, 15, 49 }, 2172 .vback_porch = { 21, 21, 21 }, 2173 .vsync_len = { 2, 2, 2 }, 2174 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2175 DISPLAY_FLAGS_DE_HIGH, 2176 }; 2177 2178 static const struct panel_desc edt_etml1010g3dra = { 2179 .timings = &edt_etml1010g3dra_timing, 2180 .num_timings = 1, 2181 .bpc = 8, 2182 .size = { 2183 .width = 216, 2184 .height = 135, 2185 }, 2186 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2187 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2188 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2189 }; 2190 2191 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2192 .clock = 25175, 2193 .hdisplay = 640, 2194 .hsync_start = 640, 2195 .hsync_end = 640 + 16, 2196 .htotal = 640 + 16 + 30 + 114, 2197 .vdisplay = 480, 2198 .vsync_start = 480 + 10, 2199 .vsync_end = 480 + 10 + 3, 2200 .vtotal = 480 + 10 + 3 + 35, 2201 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2202 }; 2203 2204 static const struct panel_desc edt_etmv570g2dhu = { 2205 .modes = &edt_etmv570g2dhu_mode, 2206 .num_modes = 1, 2207 .bpc = 6, 2208 .size = { 2209 .width = 115, 2210 .height = 86, 2211 }, 2212 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2213 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2214 .connector_type = DRM_MODE_CONNECTOR_DPI, 2215 }; 2216 2217 static const struct display_timing eink_vb3300_kca_timing = { 2218 .pixelclock = { 40000000, 40000000, 40000000 }, 2219 .hactive = { 334, 334, 334 }, 2220 .hfront_porch = { 1, 1, 1 }, 2221 .hback_porch = { 1, 1, 1 }, 2222 .hsync_len = { 1, 1, 1 }, 2223 .vactive = { 1405, 1405, 1405 }, 2224 .vfront_porch = { 1, 1, 1 }, 2225 .vback_porch = { 1, 1, 1 }, 2226 .vsync_len = { 1, 1, 1 }, 2227 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2228 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2229 }; 2230 2231 static const struct panel_desc eink_vb3300_kca = { 2232 .timings = &eink_vb3300_kca_timing, 2233 .num_timings = 1, 2234 .bpc = 6, 2235 .size = { 2236 .width = 157, 2237 .height = 209, 2238 }, 2239 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2240 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2241 .connector_type = DRM_MODE_CONNECTOR_DPI, 2242 }; 2243 2244 static const struct display_timing evervision_vgg644804_timing = { 2245 .pixelclock = { 25175000, 25175000, 25175000 }, 2246 .hactive = { 640, 640, 640 }, 2247 .hfront_porch = { 16, 16, 16 }, 2248 .hback_porch = { 82, 114, 170 }, 2249 .hsync_len = { 5, 30, 30 }, 2250 .vactive = { 480, 480, 480 }, 2251 .vfront_porch = { 10, 10, 10 }, 2252 .vback_porch = { 30, 32, 34 }, 2253 .vsync_len = { 1, 3, 5 }, 2254 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2255 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2256 DISPLAY_FLAGS_SYNC_POSEDGE, 2257 }; 2258 2259 static const struct panel_desc evervision_vgg644804 = { 2260 .timings = &evervision_vgg644804_timing, 2261 .num_timings = 1, 2262 .bpc = 6, 2263 .size = { 2264 .width = 115, 2265 .height = 86, 2266 }, 2267 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2268 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2269 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2270 }; 2271 2272 static const struct display_timing evervision_vgg804821_timing = { 2273 .pixelclock = { 27600000, 33300000, 50000000 }, 2274 .hactive = { 800, 800, 800 }, 2275 .hfront_porch = { 40, 66, 70 }, 2276 .hback_porch = { 40, 67, 70 }, 2277 .hsync_len = { 40, 67, 70 }, 2278 .vactive = { 480, 480, 480 }, 2279 .vfront_porch = { 6, 10, 10 }, 2280 .vback_porch = { 7, 11, 11 }, 2281 .vsync_len = { 7, 11, 11 }, 2282 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2283 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2284 DISPLAY_FLAGS_SYNC_NEGEDGE, 2285 }; 2286 2287 static const struct panel_desc evervision_vgg804821 = { 2288 .timings = &evervision_vgg804821_timing, 2289 .num_timings = 1, 2290 .bpc = 8, 2291 .size = { 2292 .width = 108, 2293 .height = 64, 2294 }, 2295 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2296 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2297 }; 2298 2299 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2300 .clock = 32260, 2301 .hdisplay = 800, 2302 .hsync_start = 800 + 168, 2303 .hsync_end = 800 + 168 + 64, 2304 .htotal = 800 + 168 + 64 + 88, 2305 .vdisplay = 480, 2306 .vsync_start = 480 + 37, 2307 .vsync_end = 480 + 37 + 2, 2308 .vtotal = 480 + 37 + 2 + 8, 2309 }; 2310 2311 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2312 .modes = &foxlink_fl500wvr00_a0t_mode, 2313 .num_modes = 1, 2314 .bpc = 8, 2315 .size = { 2316 .width = 108, 2317 .height = 65, 2318 }, 2319 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2320 }; 2321 2322 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2323 { /* 60 Hz */ 2324 .clock = 6000, 2325 .hdisplay = 320, 2326 .hsync_start = 320 + 44, 2327 .hsync_end = 320 + 44 + 16, 2328 .htotal = 320 + 44 + 16 + 20, 2329 .vdisplay = 240, 2330 .vsync_start = 240 + 2, 2331 .vsync_end = 240 + 2 + 6, 2332 .vtotal = 240 + 2 + 6 + 2, 2333 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2334 }, 2335 { /* 50 Hz */ 2336 .clock = 5400, 2337 .hdisplay = 320, 2338 .hsync_start = 320 + 56, 2339 .hsync_end = 320 + 56 + 16, 2340 .htotal = 320 + 56 + 16 + 40, 2341 .vdisplay = 240, 2342 .vsync_start = 240 + 2, 2343 .vsync_end = 240 + 2 + 6, 2344 .vtotal = 240 + 2 + 6 + 2, 2345 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2346 }, 2347 }; 2348 2349 static const struct panel_desc frida_frd350h54004 = { 2350 .modes = frida_frd350h54004_modes, 2351 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2352 .bpc = 8, 2353 .size = { 2354 .width = 77, 2355 .height = 64, 2356 }, 2357 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2358 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2359 .connector_type = DRM_MODE_CONNECTOR_DPI, 2360 }; 2361 2362 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2363 .clock = 9000, 2364 .hdisplay = 480, 2365 .hsync_start = 480 + 5, 2366 .hsync_end = 480 + 5 + 1, 2367 .htotal = 480 + 5 + 1 + 40, 2368 .vdisplay = 272, 2369 .vsync_start = 272 + 8, 2370 .vsync_end = 272 + 8 + 1, 2371 .vtotal = 272 + 8 + 1 + 8, 2372 }; 2373 2374 static const struct panel_desc giantplus_gpg482739qs5 = { 2375 .modes = &giantplus_gpg482739qs5_mode, 2376 .num_modes = 1, 2377 .bpc = 8, 2378 .size = { 2379 .width = 95, 2380 .height = 54, 2381 }, 2382 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2383 }; 2384 2385 static const struct display_timing giantplus_gpm940b0_timing = { 2386 .pixelclock = { 13500000, 27000000, 27500000 }, 2387 .hactive = { 320, 320, 320 }, 2388 .hfront_porch = { 14, 686, 718 }, 2389 .hback_porch = { 50, 70, 255 }, 2390 .hsync_len = { 1, 1, 1 }, 2391 .vactive = { 240, 240, 240 }, 2392 .vfront_porch = { 1, 1, 179 }, 2393 .vback_porch = { 1, 21, 31 }, 2394 .vsync_len = { 1, 1, 6 }, 2395 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2396 }; 2397 2398 static const struct panel_desc giantplus_gpm940b0 = { 2399 .timings = &giantplus_gpm940b0_timing, 2400 .num_timings = 1, 2401 .bpc = 8, 2402 .size = { 2403 .width = 60, 2404 .height = 45, 2405 }, 2406 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2407 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2408 }; 2409 2410 static const struct display_timing hannstar_hsd070pww1_timing = { 2411 .pixelclock = { 64300000, 71100000, 82000000 }, 2412 .hactive = { 1280, 1280, 1280 }, 2413 .hfront_porch = { 1, 1, 10 }, 2414 .hback_porch = { 1, 1, 10 }, 2415 /* 2416 * According to the data sheet, the minimum horizontal blanking interval 2417 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2418 * minimum working horizontal blanking interval to be 60 clocks. 2419 */ 2420 .hsync_len = { 58, 158, 661 }, 2421 .vactive = { 800, 800, 800 }, 2422 .vfront_porch = { 1, 1, 10 }, 2423 .vback_porch = { 1, 1, 10 }, 2424 .vsync_len = { 1, 21, 203 }, 2425 .flags = DISPLAY_FLAGS_DE_HIGH, 2426 }; 2427 2428 static const struct panel_desc hannstar_hsd070pww1 = { 2429 .timings = &hannstar_hsd070pww1_timing, 2430 .num_timings = 1, 2431 .bpc = 6, 2432 .size = { 2433 .width = 151, 2434 .height = 94, 2435 }, 2436 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2437 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2438 }; 2439 2440 static const struct display_timing hannstar_hsd100pxn1_timing = { 2441 .pixelclock = { 55000000, 65000000, 75000000 }, 2442 .hactive = { 1024, 1024, 1024 }, 2443 .hfront_porch = { 40, 40, 40 }, 2444 .hback_porch = { 220, 220, 220 }, 2445 .hsync_len = { 20, 60, 100 }, 2446 .vactive = { 768, 768, 768 }, 2447 .vfront_porch = { 7, 7, 7 }, 2448 .vback_porch = { 21, 21, 21 }, 2449 .vsync_len = { 10, 10, 10 }, 2450 .flags = DISPLAY_FLAGS_DE_HIGH, 2451 }; 2452 2453 static const struct panel_desc hannstar_hsd100pxn1 = { 2454 .timings = &hannstar_hsd100pxn1_timing, 2455 .num_timings = 1, 2456 .bpc = 6, 2457 .size = { 2458 .width = 203, 2459 .height = 152, 2460 }, 2461 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2462 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2463 }; 2464 2465 static const struct display_timing hannstar_hsd101pww2_timing = { 2466 .pixelclock = { 64300000, 71100000, 82000000 }, 2467 .hactive = { 1280, 1280, 1280 }, 2468 .hfront_porch = { 1, 1, 10 }, 2469 .hback_porch = { 1, 1, 10 }, 2470 .hsync_len = { 58, 158, 661 }, 2471 .vactive = { 800, 800, 800 }, 2472 .vfront_porch = { 1, 1, 10 }, 2473 .vback_porch = { 1, 1, 10 }, 2474 .vsync_len = { 1, 21, 203 }, 2475 .flags = DISPLAY_FLAGS_DE_HIGH, 2476 }; 2477 2478 static const struct panel_desc hannstar_hsd101pww2 = { 2479 .timings = &hannstar_hsd101pww2_timing, 2480 .num_timings = 1, 2481 .bpc = 8, 2482 .size = { 2483 .width = 217, 2484 .height = 136, 2485 }, 2486 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2487 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2488 }; 2489 2490 static const struct display_timing hannstar_hsd156juw2_timing = { 2491 .pixelclock = { 66000000, 72800000, 80500000 }, 2492 .hactive = { 1920, 1920, 1920 }, 2493 .hfront_porch = { 20, 30, 30 }, 2494 .hback_porch = { 20, 30, 30 }, 2495 .hsync_len = { 50, 60, 90 }, 2496 .vactive = { 1080, 1080, 1080 }, 2497 .vfront_porch = { 1, 2, 4 }, 2498 .vback_porch = { 1, 2, 4 }, 2499 .vsync_len = { 3, 40, 80 }, 2500 .flags = DISPLAY_FLAGS_DE_HIGH, 2501 }; 2502 2503 static const struct panel_desc hannstar_hsd156juw2 = { 2504 .timings = &hannstar_hsd156juw2_timing, 2505 .num_timings = 1, 2506 .bpc = 8, 2507 .size = { 2508 .width = 344, 2509 .height = 194, 2510 }, 2511 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2512 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2513 }; 2514 2515 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2516 .clock = 33333, 2517 .hdisplay = 800, 2518 .hsync_start = 800 + 85, 2519 .hsync_end = 800 + 85 + 86, 2520 .htotal = 800 + 85 + 86 + 85, 2521 .vdisplay = 480, 2522 .vsync_start = 480 + 16, 2523 .vsync_end = 480 + 16 + 13, 2524 .vtotal = 480 + 16 + 13 + 16, 2525 }; 2526 2527 static const struct panel_desc hitachi_tx23d38vm0caa = { 2528 .modes = &hitachi_tx23d38vm0caa_mode, 2529 .num_modes = 1, 2530 .bpc = 6, 2531 .size = { 2532 .width = 195, 2533 .height = 117, 2534 }, 2535 .delay = { 2536 .enable = 160, 2537 .disable = 160, 2538 }, 2539 }; 2540 2541 static const struct drm_display_mode innolux_at043tn24_mode = { 2542 .clock = 9000, 2543 .hdisplay = 480, 2544 .hsync_start = 480 + 2, 2545 .hsync_end = 480 + 2 + 41, 2546 .htotal = 480 + 2 + 41 + 2, 2547 .vdisplay = 272, 2548 .vsync_start = 272 + 2, 2549 .vsync_end = 272 + 2 + 10, 2550 .vtotal = 272 + 2 + 10 + 2, 2551 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2552 }; 2553 2554 static const struct panel_desc innolux_at043tn24 = { 2555 .modes = &innolux_at043tn24_mode, 2556 .num_modes = 1, 2557 .bpc = 8, 2558 .size = { 2559 .width = 95, 2560 .height = 54, 2561 }, 2562 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2563 .connector_type = DRM_MODE_CONNECTOR_DPI, 2564 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2565 }; 2566 2567 static const struct drm_display_mode innolux_at070tn92_mode = { 2568 .clock = 33333, 2569 .hdisplay = 800, 2570 .hsync_start = 800 + 210, 2571 .hsync_end = 800 + 210 + 20, 2572 .htotal = 800 + 210 + 20 + 46, 2573 .vdisplay = 480, 2574 .vsync_start = 480 + 22, 2575 .vsync_end = 480 + 22 + 10, 2576 .vtotal = 480 + 22 + 23 + 10, 2577 }; 2578 2579 static const struct panel_desc innolux_at070tn92 = { 2580 .modes = &innolux_at070tn92_mode, 2581 .num_modes = 1, 2582 .size = { 2583 .width = 154, 2584 .height = 86, 2585 }, 2586 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2587 }; 2588 2589 static const struct display_timing innolux_g070ace_l01_timing = { 2590 .pixelclock = { 25200000, 35000000, 35700000 }, 2591 .hactive = { 800, 800, 800 }, 2592 .hfront_porch = { 30, 32, 87 }, 2593 .hback_porch = { 30, 32, 87 }, 2594 .hsync_len = { 1, 1, 1 }, 2595 .vactive = { 480, 480, 480 }, 2596 .vfront_porch = { 3, 3, 3 }, 2597 .vback_porch = { 13, 13, 13 }, 2598 .vsync_len = { 1, 1, 4 }, 2599 .flags = DISPLAY_FLAGS_DE_HIGH, 2600 }; 2601 2602 static const struct panel_desc innolux_g070ace_l01 = { 2603 .timings = &innolux_g070ace_l01_timing, 2604 .num_timings = 1, 2605 .bpc = 8, 2606 .size = { 2607 .width = 152, 2608 .height = 91, 2609 }, 2610 .delay = { 2611 .prepare = 10, 2612 .enable = 50, 2613 .disable = 50, 2614 .unprepare = 500, 2615 }, 2616 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2617 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2618 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2619 }; 2620 2621 static const struct display_timing innolux_g070y2_l01_timing = { 2622 .pixelclock = { 28000000, 29500000, 32000000 }, 2623 .hactive = { 800, 800, 800 }, 2624 .hfront_porch = { 61, 91, 141 }, 2625 .hback_porch = { 60, 90, 140 }, 2626 .hsync_len = { 12, 12, 12 }, 2627 .vactive = { 480, 480, 480 }, 2628 .vfront_porch = { 4, 9, 30 }, 2629 .vback_porch = { 4, 8, 28 }, 2630 .vsync_len = { 2, 2, 2 }, 2631 .flags = DISPLAY_FLAGS_DE_HIGH, 2632 }; 2633 2634 static const struct panel_desc innolux_g070y2_l01 = { 2635 .timings = &innolux_g070y2_l01_timing, 2636 .num_timings = 1, 2637 .bpc = 8, 2638 .size = { 2639 .width = 152, 2640 .height = 91, 2641 }, 2642 .delay = { 2643 .prepare = 10, 2644 .enable = 100, 2645 .disable = 100, 2646 .unprepare = 800, 2647 }, 2648 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2649 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2650 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2651 }; 2652 2653 static const struct display_timing innolux_g070ace_lh3_timing = { 2654 .pixelclock = { 25200000, 25400000, 35700000 }, 2655 .hactive = { 800, 800, 800 }, 2656 .hfront_porch = { 30, 32, 87 }, 2657 .hback_porch = { 29, 31, 86 }, 2658 .hsync_len = { 1, 1, 1 }, 2659 .vactive = { 480, 480, 480 }, 2660 .vfront_porch = { 4, 5, 65 }, 2661 .vback_porch = { 3, 4, 65 }, 2662 .vsync_len = { 1, 1, 1 }, 2663 .flags = DISPLAY_FLAGS_DE_HIGH, 2664 }; 2665 2666 static const struct panel_desc innolux_g070ace_lh3 = { 2667 .timings = &innolux_g070ace_lh3_timing, 2668 .num_timings = 1, 2669 .bpc = 8, 2670 .size = { 2671 .width = 152, 2672 .height = 91, 2673 }, 2674 .delay = { 2675 .prepare = 10, 2676 .enable = 450, 2677 .disable = 200, 2678 .unprepare = 510, 2679 }, 2680 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2681 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2682 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2683 }; 2684 2685 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2686 .clock = 33333, 2687 .hdisplay = 800, 2688 .hsync_start = 800 + 210, 2689 .hsync_end = 800 + 210 + 20, 2690 .htotal = 800 + 210 + 20 + 46, 2691 .vdisplay = 480, 2692 .vsync_start = 480 + 22, 2693 .vsync_end = 480 + 22 + 10, 2694 .vtotal = 480 + 22 + 23 + 10, 2695 }; 2696 2697 static const struct panel_desc innolux_g070y2_t02 = { 2698 .modes = &innolux_g070y2_t02_mode, 2699 .num_modes = 1, 2700 .bpc = 8, 2701 .size = { 2702 .width = 152, 2703 .height = 92, 2704 }, 2705 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2706 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2707 .connector_type = DRM_MODE_CONNECTOR_DPI, 2708 }; 2709 2710 static const struct display_timing innolux_g101ice_l01_timing = { 2711 .pixelclock = { 60400000, 71100000, 74700000 }, 2712 .hactive = { 1280, 1280, 1280 }, 2713 .hfront_porch = { 30, 60, 70 }, 2714 .hback_porch = { 30, 60, 70 }, 2715 .hsync_len = { 22, 40, 60 }, 2716 .vactive = { 800, 800, 800 }, 2717 .vfront_porch = { 3, 8, 14 }, 2718 .vback_porch = { 3, 8, 14 }, 2719 .vsync_len = { 4, 7, 12 }, 2720 .flags = DISPLAY_FLAGS_DE_HIGH, 2721 }; 2722 2723 static const struct panel_desc innolux_g101ice_l01 = { 2724 .timings = &innolux_g101ice_l01_timing, 2725 .num_timings = 1, 2726 .bpc = 8, 2727 .size = { 2728 .width = 217, 2729 .height = 135, 2730 }, 2731 .delay = { 2732 .enable = 200, 2733 .disable = 200, 2734 }, 2735 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2736 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2737 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2738 }; 2739 2740 static const struct display_timing innolux_g121i1_l01_timing = { 2741 .pixelclock = { 67450000, 71000000, 74550000 }, 2742 .hactive = { 1280, 1280, 1280 }, 2743 .hfront_porch = { 40, 80, 160 }, 2744 .hback_porch = { 39, 79, 159 }, 2745 .hsync_len = { 1, 1, 1 }, 2746 .vactive = { 800, 800, 800 }, 2747 .vfront_porch = { 5, 11, 100 }, 2748 .vback_porch = { 4, 11, 99 }, 2749 .vsync_len = { 1, 1, 1 }, 2750 }; 2751 2752 static const struct panel_desc innolux_g121i1_l01 = { 2753 .timings = &innolux_g121i1_l01_timing, 2754 .num_timings = 1, 2755 .bpc = 6, 2756 .size = { 2757 .width = 261, 2758 .height = 163, 2759 }, 2760 .delay = { 2761 .enable = 200, 2762 .disable = 20, 2763 }, 2764 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2765 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2766 }; 2767 2768 static const struct display_timing innolux_g121x1_l03_timings = { 2769 .pixelclock = { 57500000, 64900000, 74400000 }, 2770 .hactive = { 1024, 1024, 1024 }, 2771 .hfront_porch = { 90, 140, 190 }, 2772 .hback_porch = { 90, 140, 190 }, 2773 .hsync_len = { 36, 40, 60 }, 2774 .vactive = { 768, 768, 768 }, 2775 .vfront_porch = { 2, 15, 30 }, 2776 .vback_porch = { 2, 15, 30 }, 2777 .vsync_len = { 2, 8, 20 }, 2778 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2779 }; 2780 2781 static const struct panel_desc innolux_g121x1_l03 = { 2782 .timings = &innolux_g121x1_l03_timings, 2783 .num_timings = 1, 2784 .bpc = 6, 2785 .size = { 2786 .width = 246, 2787 .height = 185, 2788 }, 2789 .delay = { 2790 .enable = 200, 2791 .unprepare = 200, 2792 .disable = 400, 2793 }, 2794 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2795 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2796 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2797 }; 2798 2799 static const struct panel_desc innolux_g121xce_l01 = { 2800 .timings = &innolux_g121x1_l03_timings, 2801 .num_timings = 1, 2802 .bpc = 8, 2803 .size = { 2804 .width = 246, 2805 .height = 185, 2806 }, 2807 .delay = { 2808 .enable = 200, 2809 .unprepare = 200, 2810 .disable = 400, 2811 }, 2812 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2813 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2814 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2815 }; 2816 2817 static const struct display_timing innolux_g150xge_l05_timing = { 2818 .pixelclock = { 53350000, 65000000, 80000000 }, 2819 .hactive = { 1024, 1024, 1024 }, 2820 .hfront_porch = { 58, 160, 288 }, 2821 .hback_porch = { 58, 160, 288 }, 2822 .hsync_len = { 1, 1, 1 }, 2823 .vactive = { 768, 768, 768 }, 2824 .vfront_porch = { 6, 19, 216 }, 2825 .vback_porch = { 6, 19, 216 }, 2826 .vsync_len = { 1, 1, 1 }, 2827 .flags = DISPLAY_FLAGS_DE_HIGH, 2828 }; 2829 2830 static const struct panel_desc innolux_g150xge_l05 = { 2831 .timings = &innolux_g150xge_l05_timing, 2832 .num_timings = 1, 2833 .bpc = 8, 2834 .size = { 2835 .width = 304, 2836 .height = 228, 2837 }, 2838 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2839 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2840 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2841 }; 2842 2843 static const struct display_timing innolux_g156hce_l01_timings = { 2844 .pixelclock = { 120000000, 141860000, 150000000 }, 2845 .hactive = { 1920, 1920, 1920 }, 2846 .hfront_porch = { 80, 90, 100 }, 2847 .hback_porch = { 80, 90, 100 }, 2848 .hsync_len = { 20, 30, 30 }, 2849 .vactive = { 1080, 1080, 1080 }, 2850 .vfront_porch = { 3, 10, 20 }, 2851 .vback_porch = { 3, 10, 20 }, 2852 .vsync_len = { 4, 10, 10 }, 2853 }; 2854 2855 static const struct panel_desc innolux_g156hce_l01 = { 2856 .timings = &innolux_g156hce_l01_timings, 2857 .num_timings = 1, 2858 .bpc = 8, 2859 .size = { 2860 .width = 344, 2861 .height = 194, 2862 }, 2863 .delay = { 2864 .prepare = 1, /* T1+T2 */ 2865 .enable = 450, /* T5 */ 2866 .disable = 200, /* T6 */ 2867 .unprepare = 10, /* T3+T7 */ 2868 }, 2869 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2870 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2871 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2872 }; 2873 2874 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2875 .clock = 69300, 2876 .hdisplay = 1366, 2877 .hsync_start = 1366 + 16, 2878 .hsync_end = 1366 + 16 + 34, 2879 .htotal = 1366 + 16 + 34 + 50, 2880 .vdisplay = 768, 2881 .vsync_start = 768 + 2, 2882 .vsync_end = 768 + 2 + 6, 2883 .vtotal = 768 + 2 + 6 + 12, 2884 }; 2885 2886 static const struct panel_desc innolux_n156bge_l21 = { 2887 .modes = &innolux_n156bge_l21_mode, 2888 .num_modes = 1, 2889 .bpc = 6, 2890 .size = { 2891 .width = 344, 2892 .height = 193, 2893 }, 2894 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2895 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2896 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2897 }; 2898 2899 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2900 .clock = 51501, 2901 .hdisplay = 1024, 2902 .hsync_start = 1024 + 128, 2903 .hsync_end = 1024 + 128 + 64, 2904 .htotal = 1024 + 128 + 64 + 128, 2905 .vdisplay = 600, 2906 .vsync_start = 600 + 16, 2907 .vsync_end = 600 + 16 + 4, 2908 .vtotal = 600 + 16 + 4 + 16, 2909 }; 2910 2911 static const struct panel_desc innolux_zj070na_01p = { 2912 .modes = &innolux_zj070na_01p_mode, 2913 .num_modes = 1, 2914 .bpc = 6, 2915 .size = { 2916 .width = 154, 2917 .height = 90, 2918 }, 2919 }; 2920 2921 static const struct display_timing jutouch_jt101tm023_timing = { 2922 .pixelclock = { 66300000, 72400000, 78900000 }, 2923 .hactive = { 1280, 1280, 1280 }, 2924 .hfront_porch = { 12, 72, 132 }, 2925 .hback_porch = { 88, 88, 88 }, 2926 .hsync_len = { 10, 10, 48 }, 2927 .vactive = { 800, 800, 800 }, 2928 .vfront_porch = { 1, 15, 49 }, 2929 .vback_porch = { 23, 23, 23 }, 2930 .vsync_len = { 5, 6, 13 }, 2931 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2932 DISPLAY_FLAGS_DE_HIGH, 2933 }; 2934 2935 static const struct panel_desc jutouch_jt101tm023 = { 2936 .timings = &jutouch_jt101tm023_timing, 2937 .num_timings = 1, 2938 .bpc = 8, 2939 .size = { 2940 .width = 217, 2941 .height = 136, 2942 }, 2943 .delay = { 2944 .enable = 50, 2945 .disable = 50, 2946 }, 2947 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2948 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2949 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2950 }; 2951 2952 2953 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2954 .pixelclock = { 5580000, 5850000, 6200000 }, 2955 .hactive = { 320, 320, 320 }, 2956 .hfront_porch = { 30, 30, 30 }, 2957 .hback_porch = { 30, 30, 30 }, 2958 .hsync_len = { 1, 5, 17 }, 2959 .vactive = { 240, 240, 240 }, 2960 .vfront_porch = { 6, 6, 6 }, 2961 .vback_porch = { 5, 5, 5 }, 2962 .vsync_len = { 1, 2, 11 }, 2963 .flags = DISPLAY_FLAGS_DE_HIGH, 2964 }; 2965 2966 static const struct panel_desc koe_tx14d24vm1bpa = { 2967 .timings = &koe_tx14d24vm1bpa_timing, 2968 .num_timings = 1, 2969 .bpc = 6, 2970 .size = { 2971 .width = 115, 2972 .height = 86, 2973 }, 2974 }; 2975 2976 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2977 .pixelclock = { 151820000, 156720000, 159780000 }, 2978 .hactive = { 1920, 1920, 1920 }, 2979 .hfront_porch = { 105, 130, 142 }, 2980 .hback_porch = { 45, 70, 82 }, 2981 .hsync_len = { 30, 30, 30 }, 2982 .vactive = { 1200, 1200, 1200}, 2983 .vfront_porch = { 3, 5, 10 }, 2984 .vback_porch = { 2, 5, 10 }, 2985 .vsync_len = { 5, 5, 5 }, 2986 .flags = DISPLAY_FLAGS_DE_HIGH, 2987 }; 2988 2989 static const struct panel_desc koe_tx26d202vm0bwa = { 2990 .timings = &koe_tx26d202vm0bwa_timing, 2991 .num_timings = 1, 2992 .bpc = 8, 2993 .size = { 2994 .width = 217, 2995 .height = 136, 2996 }, 2997 .delay = { 2998 .prepare = 1000, 2999 .enable = 1000, 3000 .unprepare = 1000, 3001 .disable = 1000, 3002 }, 3003 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3004 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3005 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3006 }; 3007 3008 static const struct display_timing koe_tx31d200vm0baa_timing = { 3009 .pixelclock = { 39600000, 43200000, 48000000 }, 3010 .hactive = { 1280, 1280, 1280 }, 3011 .hfront_porch = { 16, 36, 56 }, 3012 .hback_porch = { 16, 36, 56 }, 3013 .hsync_len = { 8, 8, 8 }, 3014 .vactive = { 480, 480, 480 }, 3015 .vfront_porch = { 6, 21, 33 }, 3016 .vback_porch = { 6, 21, 33 }, 3017 .vsync_len = { 8, 8, 8 }, 3018 .flags = DISPLAY_FLAGS_DE_HIGH, 3019 }; 3020 3021 static const struct panel_desc koe_tx31d200vm0baa = { 3022 .timings = &koe_tx31d200vm0baa_timing, 3023 .num_timings = 1, 3024 .bpc = 6, 3025 .size = { 3026 .width = 292, 3027 .height = 109, 3028 }, 3029 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3030 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3031 }; 3032 3033 static const struct display_timing kyo_tcg121xglp_timing = { 3034 .pixelclock = { 52000000, 65000000, 71000000 }, 3035 .hactive = { 1024, 1024, 1024 }, 3036 .hfront_porch = { 2, 2, 2 }, 3037 .hback_porch = { 2, 2, 2 }, 3038 .hsync_len = { 86, 124, 244 }, 3039 .vactive = { 768, 768, 768 }, 3040 .vfront_porch = { 2, 2, 2 }, 3041 .vback_porch = { 2, 2, 2 }, 3042 .vsync_len = { 6, 34, 73 }, 3043 .flags = DISPLAY_FLAGS_DE_HIGH, 3044 }; 3045 3046 static const struct panel_desc kyo_tcg121xglp = { 3047 .timings = &kyo_tcg121xglp_timing, 3048 .num_timings = 1, 3049 .bpc = 8, 3050 .size = { 3051 .width = 246, 3052 .height = 184, 3053 }, 3054 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3055 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3056 }; 3057 3058 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 3059 .clock = 7000, 3060 .hdisplay = 320, 3061 .hsync_start = 320 + 20, 3062 .hsync_end = 320 + 20 + 30, 3063 .htotal = 320 + 20 + 30 + 38, 3064 .vdisplay = 240, 3065 .vsync_start = 240 + 4, 3066 .vsync_end = 240 + 4 + 3, 3067 .vtotal = 240 + 4 + 3 + 15, 3068 }; 3069 3070 static const struct panel_desc lemaker_bl035_rgb_002 = { 3071 .modes = &lemaker_bl035_rgb_002_mode, 3072 .num_modes = 1, 3073 .size = { 3074 .width = 70, 3075 .height = 52, 3076 }, 3077 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3078 .bus_flags = DRM_BUS_FLAG_DE_LOW, 3079 }; 3080 3081 static const struct display_timing lg_lb070wv8_timing = { 3082 .pixelclock = { 31950000, 33260000, 34600000 }, 3083 .hactive = { 800, 800, 800 }, 3084 .hfront_porch = { 88, 88, 88 }, 3085 .hback_porch = { 88, 88, 88 }, 3086 .hsync_len = { 80, 80, 80 }, 3087 .vactive = { 480, 480, 480 }, 3088 .vfront_porch = { 10, 10, 10 }, 3089 .vback_porch = { 10, 10, 10 }, 3090 .vsync_len = { 25, 25, 25 }, 3091 }; 3092 3093 static const struct panel_desc lg_lb070wv8 = { 3094 .timings = &lg_lb070wv8_timing, 3095 .num_timings = 1, 3096 .bpc = 8, 3097 .size = { 3098 .width = 151, 3099 .height = 91, 3100 }, 3101 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3102 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3103 }; 3104 3105 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 3106 .clock = 155127, 3107 .hdisplay = 1920, 3108 .hsync_start = 1920 + 128, 3109 .hsync_end = 1920 + 128 + 20, 3110 .htotal = 1920 + 128 + 20 + 12, 3111 .vdisplay = 1200, 3112 .vsync_start = 1200 + 19, 3113 .vsync_end = 1200 + 19 + 4, 3114 .vtotal = 1200 + 19 + 4 + 20, 3115 }; 3116 3117 static const struct panel_desc lincolntech_lcd185_101ct = { 3118 .modes = &lincolntech_lcd185_101ct_mode, 3119 .bpc = 8, 3120 .num_modes = 1, 3121 .size = { 3122 .width = 217, 3123 .height = 136, 3124 }, 3125 .delay = { 3126 .prepare = 50, 3127 .disable = 50, 3128 }, 3129 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3130 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3131 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3132 }; 3133 3134 static const struct display_timing logictechno_lt161010_2nh_timing = { 3135 .pixelclock = { 26400000, 33300000, 46800000 }, 3136 .hactive = { 800, 800, 800 }, 3137 .hfront_porch = { 16, 210, 354 }, 3138 .hback_porch = { 46, 46, 46 }, 3139 .hsync_len = { 1, 20, 40 }, 3140 .vactive = { 480, 480, 480 }, 3141 .vfront_porch = { 7, 22, 147 }, 3142 .vback_porch = { 23, 23, 23 }, 3143 .vsync_len = { 1, 10, 20 }, 3144 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3145 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3146 DISPLAY_FLAGS_SYNC_POSEDGE, 3147 }; 3148 3149 static const struct panel_desc logictechno_lt161010_2nh = { 3150 .timings = &logictechno_lt161010_2nh_timing, 3151 .num_timings = 1, 3152 .bpc = 6, 3153 .size = { 3154 .width = 154, 3155 .height = 86, 3156 }, 3157 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3158 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3159 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3160 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3161 .connector_type = DRM_MODE_CONNECTOR_DPI, 3162 }; 3163 3164 static const struct display_timing logictechno_lt170410_2whc_timing = { 3165 .pixelclock = { 68900000, 71100000, 73400000 }, 3166 .hactive = { 1280, 1280, 1280 }, 3167 .hfront_porch = { 23, 60, 71 }, 3168 .hback_porch = { 23, 60, 71 }, 3169 .hsync_len = { 15, 40, 47 }, 3170 .vactive = { 800, 800, 800 }, 3171 .vfront_porch = { 5, 7, 10 }, 3172 .vback_porch = { 5, 7, 10 }, 3173 .vsync_len = { 6, 9, 12 }, 3174 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3175 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3176 DISPLAY_FLAGS_SYNC_POSEDGE, 3177 }; 3178 3179 static const struct panel_desc logictechno_lt170410_2whc = { 3180 .timings = &logictechno_lt170410_2whc_timing, 3181 .num_timings = 1, 3182 .bpc = 8, 3183 .size = { 3184 .width = 217, 3185 .height = 136, 3186 }, 3187 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3188 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3189 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3190 }; 3191 3192 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3193 .clock = 33000, 3194 .hdisplay = 800, 3195 .hsync_start = 800 + 112, 3196 .hsync_end = 800 + 112 + 3, 3197 .htotal = 800 + 112 + 3 + 85, 3198 .vdisplay = 480, 3199 .vsync_start = 480 + 38, 3200 .vsync_end = 480 + 38 + 3, 3201 .vtotal = 480 + 38 + 3 + 29, 3202 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3203 }; 3204 3205 static const struct panel_desc logictechno_lttd800480070_l2rt = { 3206 .modes = &logictechno_lttd800480070_l2rt_mode, 3207 .num_modes = 1, 3208 .bpc = 8, 3209 .size = { 3210 .width = 154, 3211 .height = 86, 3212 }, 3213 .delay = { 3214 .prepare = 45, 3215 .enable = 100, 3216 .disable = 100, 3217 .unprepare = 45 3218 }, 3219 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3220 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3221 .connector_type = DRM_MODE_CONNECTOR_DPI, 3222 }; 3223 3224 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3225 .clock = 33000, 3226 .hdisplay = 800, 3227 .hsync_start = 800 + 154, 3228 .hsync_end = 800 + 154 + 3, 3229 .htotal = 800 + 154 + 3 + 43, 3230 .vdisplay = 480, 3231 .vsync_start = 480 + 47, 3232 .vsync_end = 480 + 47 + 3, 3233 .vtotal = 480 + 47 + 3 + 20, 3234 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3235 }; 3236 3237 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3238 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3239 .num_modes = 1, 3240 .bpc = 8, 3241 .size = { 3242 .width = 154, 3243 .height = 86, 3244 }, 3245 .delay = { 3246 .prepare = 45, 3247 .enable = 100, 3248 .disable = 100, 3249 .unprepare = 45 3250 }, 3251 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3252 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3253 .connector_type = DRM_MODE_CONNECTOR_DPI, 3254 }; 3255 3256 static const struct drm_display_mode logicpd_type_28_mode = { 3257 .clock = 9107, 3258 .hdisplay = 480, 3259 .hsync_start = 480 + 3, 3260 .hsync_end = 480 + 3 + 42, 3261 .htotal = 480 + 3 + 42 + 2, 3262 3263 .vdisplay = 272, 3264 .vsync_start = 272 + 2, 3265 .vsync_end = 272 + 2 + 11, 3266 .vtotal = 272 + 2 + 11 + 3, 3267 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3268 }; 3269 3270 static const struct panel_desc logicpd_type_28 = { 3271 .modes = &logicpd_type_28_mode, 3272 .num_modes = 1, 3273 .bpc = 8, 3274 .size = { 3275 .width = 105, 3276 .height = 67, 3277 }, 3278 .delay = { 3279 .prepare = 200, 3280 .enable = 200, 3281 .unprepare = 200, 3282 .disable = 200, 3283 }, 3284 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3285 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3286 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3287 .connector_type = DRM_MODE_CONNECTOR_DPI, 3288 }; 3289 3290 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3291 .clock = 150275, 3292 .hdisplay = 1920, 3293 .hsync_start = 1920 + 32, 3294 .hsync_end = 1920 + 32 + 52, 3295 .htotal = 1920 + 32 + 52 + 24, 3296 .vdisplay = 1200, 3297 .vsync_start = 1200 + 24, 3298 .vsync_end = 1200 + 24 + 8, 3299 .vtotal = 1200 + 24 + 8 + 3, 3300 }; 3301 3302 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3303 .modes = µtips_mf_101hiebcaf0_c_mode, 3304 .bpc = 8, 3305 .num_modes = 1, 3306 .size = { 3307 .width = 217, 3308 .height = 136, 3309 }, 3310 .delay = { 3311 .prepare = 50, 3312 .disable = 50, 3313 }, 3314 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3315 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3316 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3317 }; 3318 3319 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3320 .clock = 93301, 3321 .hdisplay = 1920, 3322 .hsync_start = 1920 + 72, 3323 .hsync_end = 1920 + 72 + 72, 3324 .htotal = 1920 + 72 + 72 + 72, 3325 .vdisplay = 720, 3326 .vsync_start = 720 + 3, 3327 .vsync_end = 720 + 3 + 3, 3328 .vtotal = 720 + 3 + 3 + 2, 3329 }; 3330 3331 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3332 .modes = µtips_mf_103hieb0ga0_mode, 3333 .bpc = 8, 3334 .num_modes = 1, 3335 .size = { 3336 .width = 244, 3337 .height = 92, 3338 }, 3339 .delay = { 3340 .prepare = 50, 3341 .disable = 50, 3342 }, 3343 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3344 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3345 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3346 }; 3347 3348 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3349 .clock = 30400, 3350 .hdisplay = 800, 3351 .hsync_start = 800 + 0, 3352 .hsync_end = 800 + 1, 3353 .htotal = 800 + 0 + 1 + 160, 3354 .vdisplay = 480, 3355 .vsync_start = 480 + 0, 3356 .vsync_end = 480 + 48 + 1, 3357 .vtotal = 480 + 48 + 1 + 0, 3358 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3359 }; 3360 3361 static const struct panel_desc mitsubishi_aa070mc01 = { 3362 .modes = &mitsubishi_aa070mc01_mode, 3363 .num_modes = 1, 3364 .bpc = 8, 3365 .size = { 3366 .width = 152, 3367 .height = 91, 3368 }, 3369 3370 .delay = { 3371 .enable = 200, 3372 .unprepare = 200, 3373 .disable = 400, 3374 }, 3375 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3376 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3377 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3378 }; 3379 3380 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3381 .clock = 56234, 3382 .hdisplay = 1024, 3383 .hsync_start = 1024 + 24, 3384 .hsync_end = 1024 + 24 + 63, 3385 .htotal = 1024 + 24 + 63 + 1, 3386 .vdisplay = 768, 3387 .vsync_start = 768 + 3, 3388 .vsync_end = 768 + 3 + 6, 3389 .vtotal = 768 + 3 + 6 + 1, 3390 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3391 }; 3392 3393 static const struct panel_desc mitsubishi_aa084xe01 = { 3394 .modes = &mitsubishi_aa084xe01_mode, 3395 .num_modes = 1, 3396 .bpc = 8, 3397 .size = { 3398 .width = 1024, 3399 .height = 768, 3400 }, 3401 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3402 .connector_type = DRM_MODE_CONNECTOR_DPI, 3403 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3404 }; 3405 3406 static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3407 .pixelclock = { 26400000, 33000000, 46800000 }, 3408 .hactive = { 800, 800, 800 }, 3409 .hfront_porch = { 16, 204, 354 }, 3410 .hback_porch = { 46, 46, 46 }, 3411 .hsync_len = { 1, 6, 40 }, 3412 .vactive = { 480, 480, 480 }, 3413 .vfront_porch = { 7, 22, 147 }, 3414 .vback_porch = { 23, 23, 23 }, 3415 .vsync_len = { 1, 3, 20 }, 3416 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3417 DISPLAY_FLAGS_DE_HIGH, 3418 }; 3419 3420 static const struct panel_desc multi_inno_mi0700a2t_30 = { 3421 .timings = &multi_inno_mi0700a2t_30_timing, 3422 .num_timings = 1, 3423 .bpc = 6, 3424 .size = { 3425 .width = 153, 3426 .height = 92, 3427 }, 3428 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3429 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3430 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3431 }; 3432 3433 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3434 .pixelclock = { 29000000, 33000000, 38000000 }, 3435 .hactive = { 800, 800, 800 }, 3436 .hfront_porch = { 180, 210, 240 }, 3437 .hback_porch = { 16, 16, 16 }, 3438 .hsync_len = { 30, 30, 30 }, 3439 .vactive = { 480, 480, 480 }, 3440 .vfront_porch = { 12, 22, 32 }, 3441 .vback_porch = { 10, 10, 10 }, 3442 .vsync_len = { 13, 13, 13 }, 3443 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3444 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3445 DISPLAY_FLAGS_SYNC_POSEDGE, 3446 }; 3447 3448 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3449 .timings = &multi_inno_mi0700s4t_6_timing, 3450 .num_timings = 1, 3451 .bpc = 8, 3452 .size = { 3453 .width = 154, 3454 .height = 86, 3455 }, 3456 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3457 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3458 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3459 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3460 .connector_type = DRM_MODE_CONNECTOR_DPI, 3461 }; 3462 3463 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3464 .pixelclock = { 32000000, 40000000, 50000000 }, 3465 .hactive = { 800, 800, 800 }, 3466 .hfront_porch = { 16, 210, 354 }, 3467 .hback_porch = { 6, 26, 45 }, 3468 .hsync_len = { 1, 20, 40 }, 3469 .vactive = { 600, 600, 600 }, 3470 .vfront_porch = { 1, 12, 77 }, 3471 .vback_porch = { 3, 13, 22 }, 3472 .vsync_len = { 1, 10, 20 }, 3473 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3474 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3475 DISPLAY_FLAGS_SYNC_POSEDGE, 3476 }; 3477 3478 static const struct panel_desc multi_inno_mi0800ft_9 = { 3479 .timings = &multi_inno_mi0800ft_9_timing, 3480 .num_timings = 1, 3481 .bpc = 8, 3482 .size = { 3483 .width = 162, 3484 .height = 122, 3485 }, 3486 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3487 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3488 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3489 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3490 .connector_type = DRM_MODE_CONNECTOR_DPI, 3491 }; 3492 3493 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3494 .pixelclock = { 68900000, 70000000, 73400000 }, 3495 .hactive = { 1280, 1280, 1280 }, 3496 .hfront_porch = { 30, 60, 71 }, 3497 .hback_porch = { 30, 60, 71 }, 3498 .hsync_len = { 10, 10, 48 }, 3499 .vactive = { 800, 800, 800 }, 3500 .vfront_porch = { 5, 10, 10 }, 3501 .vback_porch = { 5, 10, 10 }, 3502 .vsync_len = { 5, 6, 13 }, 3503 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3504 DISPLAY_FLAGS_DE_HIGH, 3505 }; 3506 3507 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3508 .timings = &multi_inno_mi1010ait_1cp_timing, 3509 .num_timings = 1, 3510 .bpc = 8, 3511 .size = { 3512 .width = 217, 3513 .height = 136, 3514 }, 3515 .delay = { 3516 .enable = 50, 3517 .disable = 50, 3518 }, 3519 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3520 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3521 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3522 }; 3523 3524 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3525 .pixelclock = { 40800000, 51200000, 67200000 }, 3526 .hactive = { 1024, 1024, 1024 }, 3527 .hfront_porch = { 30, 110, 130 }, 3528 .hback_porch = { 30, 110, 130 }, 3529 .hsync_len = { 30, 100, 116 }, 3530 .vactive = { 600, 600, 600 }, 3531 .vfront_porch = { 4, 13, 80 }, 3532 .vback_porch = { 4, 13, 80 }, 3533 .vsync_len = { 2, 9, 40 }, 3534 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3535 DISPLAY_FLAGS_DE_HIGH, 3536 }; 3537 3538 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3539 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3540 .num_timings = 1, 3541 .bpc = 6, 3542 .size = { 3543 .width = 260, 3544 .height = 162, 3545 }, 3546 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3547 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3548 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3549 }; 3550 3551 static const struct display_timing nec_nl12880bc20_05_timing = { 3552 .pixelclock = { 67000000, 71000000, 75000000 }, 3553 .hactive = { 1280, 1280, 1280 }, 3554 .hfront_porch = { 2, 30, 30 }, 3555 .hback_porch = { 6, 100, 100 }, 3556 .hsync_len = { 2, 30, 30 }, 3557 .vactive = { 800, 800, 800 }, 3558 .vfront_porch = { 5, 5, 5 }, 3559 .vback_porch = { 11, 11, 11 }, 3560 .vsync_len = { 7, 7, 7 }, 3561 }; 3562 3563 static const struct panel_desc nec_nl12880bc20_05 = { 3564 .timings = &nec_nl12880bc20_05_timing, 3565 .num_timings = 1, 3566 .bpc = 8, 3567 .size = { 3568 .width = 261, 3569 .height = 163, 3570 }, 3571 .delay = { 3572 .enable = 50, 3573 .disable = 50, 3574 }, 3575 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3576 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3577 }; 3578 3579 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3580 .clock = 10870, 3581 .hdisplay = 480, 3582 .hsync_start = 480 + 2, 3583 .hsync_end = 480 + 2 + 41, 3584 .htotal = 480 + 2 + 41 + 2, 3585 .vdisplay = 272, 3586 .vsync_start = 272 + 2, 3587 .vsync_end = 272 + 2 + 4, 3588 .vtotal = 272 + 2 + 4 + 2, 3589 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3590 }; 3591 3592 static const struct panel_desc nec_nl4827hc19_05b = { 3593 .modes = &nec_nl4827hc19_05b_mode, 3594 .num_modes = 1, 3595 .bpc = 8, 3596 .size = { 3597 .width = 95, 3598 .height = 54, 3599 }, 3600 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3601 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3602 }; 3603 3604 static const struct drm_display_mode netron_dy_e231732_mode = { 3605 .clock = 66000, 3606 .hdisplay = 1024, 3607 .hsync_start = 1024 + 160, 3608 .hsync_end = 1024 + 160 + 70, 3609 .htotal = 1024 + 160 + 70 + 90, 3610 .vdisplay = 600, 3611 .vsync_start = 600 + 127, 3612 .vsync_end = 600 + 127 + 20, 3613 .vtotal = 600 + 127 + 20 + 3, 3614 }; 3615 3616 static const struct panel_desc netron_dy_e231732 = { 3617 .modes = &netron_dy_e231732_mode, 3618 .num_modes = 1, 3619 .size = { 3620 .width = 154, 3621 .height = 87, 3622 }, 3623 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3624 }; 3625 3626 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3627 .clock = 9000, 3628 .hdisplay = 480, 3629 .hsync_start = 480 + 2, 3630 .hsync_end = 480 + 2 + 41, 3631 .htotal = 480 + 2 + 41 + 2, 3632 .vdisplay = 272, 3633 .vsync_start = 272 + 2, 3634 .vsync_end = 272 + 2 + 10, 3635 .vtotal = 272 + 2 + 10 + 2, 3636 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3637 }; 3638 3639 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3640 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3641 .num_modes = 1, 3642 .bpc = 8, 3643 .size = { 3644 .width = 95, 3645 .height = 54, 3646 }, 3647 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3648 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3649 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3650 .connector_type = DRM_MODE_CONNECTOR_DPI, 3651 }; 3652 3653 static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { 3654 .clock = 75400, 3655 .hdisplay = 1366, 3656 .hsync_start = 1366 + 14, 3657 .hsync_end = 1366 + 14 + 56, 3658 .htotal = 1366 + 14 + 56 + 64, 3659 .vdisplay = 768, 3660 .vsync_start = 768 + 1, 3661 .vsync_end = 768 + 1 + 3, 3662 .vtotal = 768 + 1 + 3 + 22, 3663 }; 3664 3665 static const struct panel_desc nlt_nl13676bc25_03f = { 3666 .modes = &nlt_nl13676bc25_03f_mode, 3667 .num_modes = 1, 3668 .bpc = 8, 3669 .size = { 3670 .width = 363, 3671 .height = 215, 3672 }, 3673 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3674 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3675 }; 3676 3677 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3678 .pixelclock = { 130000000, 148350000, 163000000 }, 3679 .hactive = { 1920, 1920, 1920 }, 3680 .hfront_porch = { 80, 100, 100 }, 3681 .hback_porch = { 100, 120, 120 }, 3682 .hsync_len = { 50, 60, 60 }, 3683 .vactive = { 1080, 1080, 1080 }, 3684 .vfront_porch = { 12, 30, 30 }, 3685 .vback_porch = { 4, 10, 10 }, 3686 .vsync_len = { 4, 5, 5 }, 3687 }; 3688 3689 static const struct panel_desc nlt_nl192108ac18_02d = { 3690 .timings = &nlt_nl192108ac18_02d_timing, 3691 .num_timings = 1, 3692 .bpc = 8, 3693 .size = { 3694 .width = 344, 3695 .height = 194, 3696 }, 3697 .delay = { 3698 .unprepare = 500, 3699 }, 3700 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3701 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3702 }; 3703 3704 static const struct drm_display_mode nvd_9128_mode = { 3705 .clock = 29500, 3706 .hdisplay = 800, 3707 .hsync_start = 800 + 130, 3708 .hsync_end = 800 + 130 + 98, 3709 .htotal = 800 + 0 + 130 + 98, 3710 .vdisplay = 480, 3711 .vsync_start = 480 + 10, 3712 .vsync_end = 480 + 10 + 50, 3713 .vtotal = 480 + 0 + 10 + 50, 3714 }; 3715 3716 static const struct panel_desc nvd_9128 = { 3717 .modes = &nvd_9128_mode, 3718 .num_modes = 1, 3719 .bpc = 8, 3720 .size = { 3721 .width = 156, 3722 .height = 88, 3723 }, 3724 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3725 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3726 }; 3727 3728 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3729 .pixelclock = { 30000000, 30000000, 40000000 }, 3730 .hactive = { 800, 800, 800 }, 3731 .hfront_porch = { 40, 40, 40 }, 3732 .hback_porch = { 40, 40, 40 }, 3733 .hsync_len = { 1, 48, 48 }, 3734 .vactive = { 480, 480, 480 }, 3735 .vfront_porch = { 13, 13, 13 }, 3736 .vback_porch = { 29, 29, 29 }, 3737 .vsync_len = { 3, 3, 3 }, 3738 .flags = DISPLAY_FLAGS_DE_HIGH, 3739 }; 3740 3741 static const struct panel_desc okaya_rs800480t_7x0gp = { 3742 .timings = &okaya_rs800480t_7x0gp_timing, 3743 .num_timings = 1, 3744 .bpc = 6, 3745 .size = { 3746 .width = 154, 3747 .height = 87, 3748 }, 3749 .delay = { 3750 .prepare = 41, 3751 .enable = 50, 3752 .unprepare = 41, 3753 .disable = 50, 3754 }, 3755 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3756 }; 3757 3758 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3759 .clock = 9000, 3760 .hdisplay = 480, 3761 .hsync_start = 480 + 5, 3762 .hsync_end = 480 + 5 + 30, 3763 .htotal = 480 + 5 + 30 + 10, 3764 .vdisplay = 272, 3765 .vsync_start = 272 + 8, 3766 .vsync_end = 272 + 8 + 5, 3767 .vtotal = 272 + 8 + 5 + 3, 3768 }; 3769 3770 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3771 .modes = &olimex_lcd_olinuxino_43ts_mode, 3772 .num_modes = 1, 3773 .size = { 3774 .width = 95, 3775 .height = 54, 3776 }, 3777 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3778 }; 3779 3780 static const struct drm_display_mode olimex_lcd_olinuxino_5cts_mode = { 3781 .clock = 33300, 3782 .hdisplay = 800, 3783 .hsync_start = 800 + 210, 3784 .hsync_end = 800 + 210 + 20, 3785 .htotal = 800 + 210 + 20 + 26, 3786 .vdisplay = 480, 3787 .vsync_start = 480 + 22, 3788 .vsync_end = 480 + 22 + 10, 3789 .vtotal = 480 + 22 + 10 + 13, 3790 }; 3791 3792 static const struct panel_desc olimex_lcd_olinuxino_5cts = { 3793 .modes = &olimex_lcd_olinuxino_5cts_mode, 3794 .num_modes = 1, 3795 .size = { 3796 .width = 154, 3797 .height = 86, 3798 }, 3799 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3800 }; 3801 3802 3803 static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 3804 .pixelclock = { 30000000, 30000000, 50000000 }, 3805 .hactive = { 800, 800, 800 }, 3806 .hfront_porch = { 1, 40, 255 }, 3807 .hback_porch = { 1, 40, 87 }, 3808 .hsync_len = { 1, 48, 87 }, 3809 .vactive = { 480, 480, 480 }, 3810 .vfront_porch = { 1, 13, 255 }, 3811 .vback_porch = { 1, 29, 29 }, 3812 .vsync_len = { 3, 3, 31 }, 3813 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3814 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3815 }; 3816 3817 static const struct panel_desc ontat_kd50g21_40nt_a1 = { 3818 .timings = &ontat_kd50g21_40nt_a1_timing, 3819 .num_timings = 1, 3820 .bpc = 8, 3821 .size = { 3822 .width = 108, 3823 .height = 65, 3824 }, 3825 .delay = { 3826 .prepare = 147, /* 5 VSDs */ 3827 .enable = 147, /* 5 VSDs */ 3828 .disable = 88, /* 3 VSDs */ 3829 .unprepare = 117, /* 4 VSDs */ 3830 }, 3831 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3832 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3833 .connector_type = DRM_MODE_CONNECTOR_DPI, 3834 }; 3835 3836 /* 3837 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3838 * pixel clocks, but this is the timing that was being used in the Adafruit 3839 * installation instructions. 3840 */ 3841 static const struct drm_display_mode ontat_yx700wv03_mode = { 3842 .clock = 29500, 3843 .hdisplay = 800, 3844 .hsync_start = 824, 3845 .hsync_end = 896, 3846 .htotal = 992, 3847 .vdisplay = 480, 3848 .vsync_start = 483, 3849 .vsync_end = 493, 3850 .vtotal = 500, 3851 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3852 }; 3853 3854 /* 3855 * Specification at: 3856 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3857 */ 3858 static const struct panel_desc ontat_yx700wv03 = { 3859 .modes = &ontat_yx700wv03_mode, 3860 .num_modes = 1, 3861 .bpc = 8, 3862 .size = { 3863 .width = 154, 3864 .height = 83, 3865 }, 3866 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3867 }; 3868 3869 static const struct drm_display_mode ortustech_com37h3m_mode = { 3870 .clock = 22230, 3871 .hdisplay = 480, 3872 .hsync_start = 480 + 40, 3873 .hsync_end = 480 + 40 + 10, 3874 .htotal = 480 + 40 + 10 + 40, 3875 .vdisplay = 640, 3876 .vsync_start = 640 + 4, 3877 .vsync_end = 640 + 4 + 2, 3878 .vtotal = 640 + 4 + 2 + 4, 3879 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3880 }; 3881 3882 static const struct panel_desc ortustech_com37h3m = { 3883 .modes = &ortustech_com37h3m_mode, 3884 .num_modes = 1, 3885 .bpc = 8, 3886 .size = { 3887 .width = 56, /* 56.16mm */ 3888 .height = 75, /* 74.88mm */ 3889 }, 3890 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3891 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3892 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3893 }; 3894 3895 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3896 .clock = 25000, 3897 .hdisplay = 480, 3898 .hsync_start = 480 + 10, 3899 .hsync_end = 480 + 10 + 10, 3900 .htotal = 480 + 10 + 10 + 15, 3901 .vdisplay = 800, 3902 .vsync_start = 800 + 3, 3903 .vsync_end = 800 + 3 + 3, 3904 .vtotal = 800 + 3 + 3 + 3, 3905 }; 3906 3907 static const struct panel_desc ortustech_com43h4m85ulc = { 3908 .modes = &ortustech_com43h4m85ulc_mode, 3909 .num_modes = 1, 3910 .bpc = 6, 3911 .size = { 3912 .width = 56, 3913 .height = 93, 3914 }, 3915 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3916 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3917 .connector_type = DRM_MODE_CONNECTOR_DPI, 3918 }; 3919 3920 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3921 .clock = 33000, 3922 .hdisplay = 800, 3923 .hsync_start = 800 + 210, 3924 .hsync_end = 800 + 210 + 30, 3925 .htotal = 800 + 210 + 30 + 16, 3926 .vdisplay = 480, 3927 .vsync_start = 480 + 22, 3928 .vsync_end = 480 + 22 + 13, 3929 .vtotal = 480 + 22 + 13 + 10, 3930 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3931 }; 3932 3933 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3934 .modes = &osddisplays_osd070t1718_19ts_mode, 3935 .num_modes = 1, 3936 .bpc = 8, 3937 .size = { 3938 .width = 152, 3939 .height = 91, 3940 }, 3941 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3942 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3943 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3944 .connector_type = DRM_MODE_CONNECTOR_DPI, 3945 }; 3946 3947 static const struct drm_display_mode pda_91_00156_a0_mode = { 3948 .clock = 33300, 3949 .hdisplay = 800, 3950 .hsync_start = 800 + 1, 3951 .hsync_end = 800 + 1 + 64, 3952 .htotal = 800 + 1 + 64 + 64, 3953 .vdisplay = 480, 3954 .vsync_start = 480 + 1, 3955 .vsync_end = 480 + 1 + 23, 3956 .vtotal = 480 + 1 + 23 + 22, 3957 }; 3958 3959 static const struct panel_desc pda_91_00156_a0 = { 3960 .modes = &pda_91_00156_a0_mode, 3961 .num_modes = 1, 3962 .size = { 3963 .width = 152, 3964 .height = 91, 3965 }, 3966 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3967 }; 3968 3969 static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { 3970 .clock = 71150, 3971 .hdisplay = 1280, 3972 .hsync_start = 1280 + 48, 3973 .hsync_end = 1280 + 48 + 32, 3974 .htotal = 1280 + 48 + 32 + 80, 3975 .vdisplay = 800, 3976 .vsync_start = 800 + 9, 3977 .vsync_end = 800 + 9 + 8, 3978 .vtotal = 800 + 9 + 8 + 6, 3979 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3980 }; 3981 3982 static const struct panel_desc powertip_ph128800t004_zza01 = { 3983 .modes = &powertip_ph128800t004_zza01_mode, 3984 .num_modes = 1, 3985 .bpc = 8, 3986 .size = { 3987 .width = 216, 3988 .height = 135, 3989 }, 3990 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3991 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3992 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3993 }; 3994 3995 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 3996 .clock = 66500, 3997 .hdisplay = 1280, 3998 .hsync_start = 1280 + 12, 3999 .hsync_end = 1280 + 12 + 20, 4000 .htotal = 1280 + 12 + 20 + 56, 4001 .vdisplay = 800, 4002 .vsync_start = 800 + 1, 4003 .vsync_end = 800 + 1 + 3, 4004 .vtotal = 800 + 1 + 3 + 20, 4005 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4006 }; 4007 4008 static const struct panel_desc powertip_ph128800t006_zhc01 = { 4009 .modes = &powertip_ph128800t006_zhc01_mode, 4010 .num_modes = 1, 4011 .bpc = 8, 4012 .size = { 4013 .width = 216, 4014 .height = 135, 4015 }, 4016 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4017 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4018 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4019 }; 4020 4021 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 4022 .clock = 24750, 4023 .hdisplay = 800, 4024 .hsync_start = 800 + 54, 4025 .hsync_end = 800 + 54 + 2, 4026 .htotal = 800 + 54 + 2 + 44, 4027 .vdisplay = 480, 4028 .vsync_start = 480 + 49, 4029 .vsync_end = 480 + 49 + 2, 4030 .vtotal = 480 + 49 + 2 + 22, 4031 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4032 }; 4033 4034 static const struct panel_desc powertip_ph800480t013_idf02 = { 4035 .modes = &powertip_ph800480t013_idf02_mode, 4036 .num_modes = 1, 4037 .bpc = 8, 4038 .size = { 4039 .width = 152, 4040 .height = 91, 4041 }, 4042 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4043 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4044 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4045 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4046 .connector_type = DRM_MODE_CONNECTOR_DPI, 4047 }; 4048 4049 static const struct drm_display_mode primeview_pm070wl4_mode = { 4050 .clock = 32000, 4051 .hdisplay = 800, 4052 .hsync_start = 800 + 42, 4053 .hsync_end = 800 + 42 + 128, 4054 .htotal = 800 + 42 + 128 + 86, 4055 .vdisplay = 480, 4056 .vsync_start = 480 + 10, 4057 .vsync_end = 480 + 10 + 2, 4058 .vtotal = 480 + 10 + 2 + 33, 4059 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4060 }; 4061 4062 static const struct panel_desc primeview_pm070wl4 = { 4063 .modes = &primeview_pm070wl4_mode, 4064 .num_modes = 1, 4065 .bpc = 6, 4066 .size = { 4067 .width = 152, 4068 .height = 91, 4069 }, 4070 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4071 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4072 .connector_type = DRM_MODE_CONNECTOR_DPI, 4073 }; 4074 4075 static const struct drm_display_mode qd43003c0_40_mode = { 4076 .clock = 9000, 4077 .hdisplay = 480, 4078 .hsync_start = 480 + 8, 4079 .hsync_end = 480 + 8 + 4, 4080 .htotal = 480 + 8 + 4 + 39, 4081 .vdisplay = 272, 4082 .vsync_start = 272 + 4, 4083 .vsync_end = 272 + 4 + 10, 4084 .vtotal = 272 + 4 + 10 + 2, 4085 }; 4086 4087 static const struct panel_desc qd43003c0_40 = { 4088 .modes = &qd43003c0_40_mode, 4089 .num_modes = 1, 4090 .bpc = 8, 4091 .size = { 4092 .width = 95, 4093 .height = 53, 4094 }, 4095 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4096 }; 4097 4098 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 4099 { /* 60 Hz */ 4100 .clock = 10800, 4101 .hdisplay = 480, 4102 .hsync_start = 480 + 77, 4103 .hsync_end = 480 + 77 + 41, 4104 .htotal = 480 + 77 + 41 + 2, 4105 .vdisplay = 272, 4106 .vsync_start = 272 + 16, 4107 .vsync_end = 272 + 16 + 10, 4108 .vtotal = 272 + 16 + 10 + 2, 4109 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4110 }, 4111 { /* 50 Hz */ 4112 .clock = 10800, 4113 .hdisplay = 480, 4114 .hsync_start = 480 + 17, 4115 .hsync_end = 480 + 17 + 41, 4116 .htotal = 480 + 17 + 41 + 2, 4117 .vdisplay = 272, 4118 .vsync_start = 272 + 116, 4119 .vsync_end = 272 + 116 + 10, 4120 .vtotal = 272 + 116 + 10 + 2, 4121 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4122 }, 4123 }; 4124 4125 static const struct panel_desc qishenglong_gopher2b_lcd = { 4126 .modes = qishenglong_gopher2b_lcd_modes, 4127 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 4128 .bpc = 8, 4129 .size = { 4130 .width = 95, 4131 .height = 54, 4132 }, 4133 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4134 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4135 .connector_type = DRM_MODE_CONNECTOR_DPI, 4136 }; 4137 4138 static const struct display_timing raystar_rff500f_awh_dnn_timing = { 4139 .pixelclock = { 23000000, 25000000, 27000000 }, 4140 .hactive = { 800, 800, 800 }, 4141 .hback_porch = { 4, 8, 48 }, 4142 .hfront_porch = { 4, 8, 48 }, 4143 .hsync_len = { 2, 4, 8 }, 4144 .vactive = { 480, 480, 480 }, 4145 .vback_porch = { 4, 8, 12 }, 4146 .vfront_porch = { 4, 8, 12 }, 4147 .vsync_len = { 2, 4, 8 }, 4148 }; 4149 4150 static const struct panel_desc raystar_rff500f_awh_dnn = { 4151 .timings = &raystar_rff500f_awh_dnn_timing, 4152 .num_timings = 1, 4153 .bpc = 8, 4154 .size = { 4155 .width = 108, 4156 .height = 65, 4157 }, 4158 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4159 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4160 }; 4161 4162 static const struct display_timing rocktech_rk043fn48h_timing = { 4163 .pixelclock = { 6000000, 9000000, 12000000 }, 4164 .hactive = { 480, 480, 480 }, 4165 .hback_porch = { 8, 43, 43 }, 4166 .hfront_porch = { 2, 8, 10 }, 4167 .hsync_len = { 1, 1, 1 }, 4168 .vactive = { 272, 272, 272 }, 4169 .vback_porch = { 2, 12, 26 }, 4170 .vfront_porch = { 1, 4, 4 }, 4171 .vsync_len = { 1, 10, 10 }, 4172 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 4173 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4174 DISPLAY_FLAGS_SYNC_POSEDGE, 4175 }; 4176 4177 static const struct panel_desc rocktech_rk043fn48h = { 4178 .timings = &rocktech_rk043fn48h_timing, 4179 .num_timings = 1, 4180 .bpc = 8, 4181 .size = { 4182 .width = 95, 4183 .height = 54, 4184 }, 4185 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4186 .connector_type = DRM_MODE_CONNECTOR_DPI, 4187 }; 4188 4189 static const struct display_timing rocktech_rk070er9427_timing = { 4190 .pixelclock = { 26400000, 33300000, 46800000 }, 4191 .hactive = { 800, 800, 800 }, 4192 .hfront_porch = { 16, 210, 354 }, 4193 .hback_porch = { 46, 46, 46 }, 4194 .hsync_len = { 1, 1, 1 }, 4195 .vactive = { 480, 480, 480 }, 4196 .vfront_porch = { 7, 22, 147 }, 4197 .vback_porch = { 23, 23, 23 }, 4198 .vsync_len = { 1, 1, 1 }, 4199 .flags = DISPLAY_FLAGS_DE_HIGH, 4200 }; 4201 4202 static const struct panel_desc rocktech_rk070er9427 = { 4203 .timings = &rocktech_rk070er9427_timing, 4204 .num_timings = 1, 4205 .bpc = 6, 4206 .size = { 4207 .width = 154, 4208 .height = 86, 4209 }, 4210 .delay = { 4211 .prepare = 41, 4212 .enable = 50, 4213 .unprepare = 41, 4214 .disable = 50, 4215 }, 4216 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4217 }; 4218 4219 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4220 .clock = 71100, 4221 .hdisplay = 1280, 4222 .hsync_start = 1280 + 48, 4223 .hsync_end = 1280 + 48 + 32, 4224 .htotal = 1280 + 48 + 32 + 80, 4225 .vdisplay = 800, 4226 .vsync_start = 800 + 2, 4227 .vsync_end = 800 + 2 + 5, 4228 .vtotal = 800 + 2 + 5 + 16, 4229 }; 4230 4231 static const struct panel_desc rocktech_rk101ii01d_ct = { 4232 .modes = &rocktech_rk101ii01d_ct_mode, 4233 .bpc = 8, 4234 .num_modes = 1, 4235 .size = { 4236 .width = 217, 4237 .height = 136, 4238 }, 4239 .delay = { 4240 .prepare = 50, 4241 .disable = 50, 4242 }, 4243 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4244 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4245 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4246 }; 4247 4248 static const struct display_timing samsung_ltl101al01_timing = { 4249 .pixelclock = { 66663000, 66663000, 66663000 }, 4250 .hactive = { 1280, 1280, 1280 }, 4251 .hfront_porch = { 18, 18, 18 }, 4252 .hback_porch = { 36, 36, 36 }, 4253 .hsync_len = { 16, 16, 16 }, 4254 .vactive = { 800, 800, 800 }, 4255 .vfront_porch = { 4, 4, 4 }, 4256 .vback_porch = { 16, 16, 16 }, 4257 .vsync_len = { 3, 3, 3 }, 4258 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4259 }; 4260 4261 static const struct panel_desc samsung_ltl101al01 = { 4262 .timings = &samsung_ltl101al01_timing, 4263 .num_timings = 1, 4264 .bpc = 8, 4265 .size = { 4266 .width = 217, 4267 .height = 135, 4268 }, 4269 .delay = { 4270 .prepare = 40, 4271 .enable = 300, 4272 .disable = 200, 4273 .unprepare = 600, 4274 }, 4275 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4276 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4277 }; 4278 4279 static const struct display_timing samsung_ltl106al01_timing = { 4280 .pixelclock = { 71980000, 71980000, 71980000 }, 4281 .hactive = { 1366, 1366, 1366 }, 4282 .hfront_porch = { 56, 56, 56 }, 4283 .hback_porch = { 106, 106, 106 }, 4284 .hsync_len = { 14, 14, 14 }, 4285 .vactive = { 768, 768, 768 }, 4286 .vfront_porch = { 3, 3, 3 }, 4287 .vback_porch = { 6, 6, 6 }, 4288 .vsync_len = { 1, 1, 1 }, 4289 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4290 }; 4291 4292 static const struct panel_desc samsung_ltl106al01 = { 4293 .timings = &samsung_ltl106al01_timing, 4294 .num_timings = 1, 4295 .bpc = 8, 4296 .size = { 4297 .width = 235, 4298 .height = 132, 4299 }, 4300 .delay = { 4301 .prepare = 5, 4302 .enable = 10, 4303 .disable = 10, 4304 .unprepare = 5, 4305 }, 4306 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4307 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4308 }; 4309 4310 static const struct drm_display_mode samsung_ltn101nt05_mode = { 4311 .clock = 54030, 4312 .hdisplay = 1024, 4313 .hsync_start = 1024 + 24, 4314 .hsync_end = 1024 + 24 + 136, 4315 .htotal = 1024 + 24 + 136 + 160, 4316 .vdisplay = 600, 4317 .vsync_start = 600 + 3, 4318 .vsync_end = 600 + 3 + 6, 4319 .vtotal = 600 + 3 + 6 + 61, 4320 }; 4321 4322 static const struct panel_desc samsung_ltn101nt05 = { 4323 .modes = &samsung_ltn101nt05_mode, 4324 .num_modes = 1, 4325 .bpc = 6, 4326 .size = { 4327 .width = 223, 4328 .height = 125, 4329 }, 4330 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4331 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4332 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4333 }; 4334 4335 static const struct display_timing satoz_sat050at40h12r2_timing = { 4336 .pixelclock = {33300000, 33300000, 50000000}, 4337 .hactive = {800, 800, 800}, 4338 .hfront_porch = {16, 210, 354}, 4339 .hback_porch = {46, 46, 46}, 4340 .hsync_len = {1, 1, 40}, 4341 .vactive = {480, 480, 480}, 4342 .vfront_porch = {7, 22, 147}, 4343 .vback_porch = {23, 23, 23}, 4344 .vsync_len = {1, 1, 20}, 4345 }; 4346 4347 static const struct panel_desc satoz_sat050at40h12r2 = { 4348 .timings = &satoz_sat050at40h12r2_timing, 4349 .num_timings = 1, 4350 .bpc = 8, 4351 .size = { 4352 .width = 108, 4353 .height = 65, 4354 }, 4355 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4356 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4357 }; 4358 4359 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4360 .clock = 33260, 4361 .hdisplay = 800, 4362 .hsync_start = 800 + 64, 4363 .hsync_end = 800 + 64 + 128, 4364 .htotal = 800 + 64 + 128 + 64, 4365 .vdisplay = 480, 4366 .vsync_start = 480 + 8, 4367 .vsync_end = 480 + 8 + 2, 4368 .vtotal = 480 + 8 + 2 + 35, 4369 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4370 }; 4371 4372 static const struct panel_desc sharp_lq070y3dg3b = { 4373 .modes = &sharp_lq070y3dg3b_mode, 4374 .num_modes = 1, 4375 .bpc = 8, 4376 .size = { 4377 .width = 152, /* 152.4mm */ 4378 .height = 91, /* 91.4mm */ 4379 }, 4380 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4381 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4382 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4383 }; 4384 4385 static const struct drm_display_mode sharp_lq035q7db03_mode = { 4386 .clock = 5500, 4387 .hdisplay = 240, 4388 .hsync_start = 240 + 16, 4389 .hsync_end = 240 + 16 + 7, 4390 .htotal = 240 + 16 + 7 + 5, 4391 .vdisplay = 320, 4392 .vsync_start = 320 + 9, 4393 .vsync_end = 320 + 9 + 1, 4394 .vtotal = 320 + 9 + 1 + 7, 4395 }; 4396 4397 static const struct panel_desc sharp_lq035q7db03 = { 4398 .modes = &sharp_lq035q7db03_mode, 4399 .num_modes = 1, 4400 .bpc = 6, 4401 .size = { 4402 .width = 54, 4403 .height = 72, 4404 }, 4405 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4406 }; 4407 4408 static const struct display_timing sharp_lq101k1ly04_timing = { 4409 .pixelclock = { 60000000, 65000000, 80000000 }, 4410 .hactive = { 1280, 1280, 1280 }, 4411 .hfront_porch = { 20, 20, 20 }, 4412 .hback_porch = { 20, 20, 20 }, 4413 .hsync_len = { 10, 10, 10 }, 4414 .vactive = { 800, 800, 800 }, 4415 .vfront_porch = { 4, 4, 4 }, 4416 .vback_porch = { 4, 4, 4 }, 4417 .vsync_len = { 4, 4, 4 }, 4418 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4419 }; 4420 4421 static const struct panel_desc sharp_lq101k1ly04 = { 4422 .timings = &sharp_lq101k1ly04_timing, 4423 .num_timings = 1, 4424 .bpc = 8, 4425 .size = { 4426 .width = 217, 4427 .height = 136, 4428 }, 4429 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4430 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4431 }; 4432 4433 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4434 { /* 50 Hz */ 4435 .clock = 3000, 4436 .hdisplay = 240, 4437 .hsync_start = 240 + 58, 4438 .hsync_end = 240 + 58 + 1, 4439 .htotal = 240 + 58 + 1 + 1, 4440 .vdisplay = 160, 4441 .vsync_start = 160 + 24, 4442 .vsync_end = 160 + 24 + 10, 4443 .vtotal = 160 + 24 + 10 + 6, 4444 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4445 }, 4446 { /* 60 Hz */ 4447 .clock = 3000, 4448 .hdisplay = 240, 4449 .hsync_start = 240 + 8, 4450 .hsync_end = 240 + 8 + 1, 4451 .htotal = 240 + 8 + 1 + 1, 4452 .vdisplay = 160, 4453 .vsync_start = 160 + 24, 4454 .vsync_end = 160 + 24 + 10, 4455 .vtotal = 160 + 24 + 10 + 6, 4456 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4457 }, 4458 }; 4459 4460 static const struct panel_desc sharp_ls020b1dd01d = { 4461 .modes = sharp_ls020b1dd01d_modes, 4462 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4463 .bpc = 6, 4464 .size = { 4465 .width = 42, 4466 .height = 28, 4467 }, 4468 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4469 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4470 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4471 | DRM_BUS_FLAG_SHARP_SIGNALS, 4472 }; 4473 4474 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4475 .clock = 33300, 4476 .hdisplay = 800, 4477 .hsync_start = 800 + 1, 4478 .hsync_end = 800 + 1 + 64, 4479 .htotal = 800 + 1 + 64 + 64, 4480 .vdisplay = 480, 4481 .vsync_start = 480 + 1, 4482 .vsync_end = 480 + 1 + 23, 4483 .vtotal = 480 + 1 + 23 + 22, 4484 }; 4485 4486 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4487 .modes = &shelly_sca07010_bfn_lnn_mode, 4488 .num_modes = 1, 4489 .size = { 4490 .width = 152, 4491 .height = 91, 4492 }, 4493 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4494 }; 4495 4496 static const struct drm_display_mode starry_kr070pe2t_mode = { 4497 .clock = 33000, 4498 .hdisplay = 800, 4499 .hsync_start = 800 + 209, 4500 .hsync_end = 800 + 209 + 1, 4501 .htotal = 800 + 209 + 1 + 45, 4502 .vdisplay = 480, 4503 .vsync_start = 480 + 22, 4504 .vsync_end = 480 + 22 + 1, 4505 .vtotal = 480 + 22 + 1 + 22, 4506 }; 4507 4508 static const struct panel_desc starry_kr070pe2t = { 4509 .modes = &starry_kr070pe2t_mode, 4510 .num_modes = 1, 4511 .bpc = 8, 4512 .size = { 4513 .width = 152, 4514 .height = 86, 4515 }, 4516 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4517 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4518 .connector_type = DRM_MODE_CONNECTOR_DPI, 4519 }; 4520 4521 static const struct display_timing startek_kd070wvfpa_mode = { 4522 .pixelclock = { 25200000, 27200000, 30500000 }, 4523 .hactive = { 800, 800, 800 }, 4524 .hfront_porch = { 19, 44, 115 }, 4525 .hback_porch = { 5, 16, 101 }, 4526 .hsync_len = { 1, 2, 100 }, 4527 .vactive = { 480, 480, 480 }, 4528 .vfront_porch = { 5, 43, 67 }, 4529 .vback_porch = { 5, 5, 67 }, 4530 .vsync_len = { 1, 2, 66 }, 4531 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4532 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4533 DISPLAY_FLAGS_SYNC_POSEDGE, 4534 }; 4535 4536 static const struct panel_desc startek_kd070wvfpa = { 4537 .timings = &startek_kd070wvfpa_mode, 4538 .num_timings = 1, 4539 .bpc = 8, 4540 .size = { 4541 .width = 152, 4542 .height = 91, 4543 }, 4544 .delay = { 4545 .prepare = 20, 4546 .enable = 200, 4547 .disable = 200, 4548 }, 4549 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4550 .connector_type = DRM_MODE_CONNECTOR_DPI, 4551 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4552 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4553 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4554 }; 4555 4556 static const struct display_timing tsd_tst043015cmhx_timing = { 4557 .pixelclock = { 5000000, 9000000, 12000000 }, 4558 .hactive = { 480, 480, 480 }, 4559 .hfront_porch = { 4, 5, 65 }, 4560 .hback_porch = { 36, 40, 255 }, 4561 .hsync_len = { 1, 1, 1 }, 4562 .vactive = { 272, 272, 272 }, 4563 .vfront_porch = { 2, 8, 97 }, 4564 .vback_porch = { 3, 8, 31 }, 4565 .vsync_len = { 1, 1, 1 }, 4566 4567 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4568 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4569 }; 4570 4571 static const struct panel_desc tsd_tst043015cmhx = { 4572 .timings = &tsd_tst043015cmhx_timing, 4573 .num_timings = 1, 4574 .bpc = 8, 4575 .size = { 4576 .width = 105, 4577 .height = 67, 4578 }, 4579 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4580 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4581 }; 4582 4583 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4584 .clock = 30000, 4585 .hdisplay = 800, 4586 .hsync_start = 800 + 39, 4587 .hsync_end = 800 + 39 + 47, 4588 .htotal = 800 + 39 + 47 + 39, 4589 .vdisplay = 480, 4590 .vsync_start = 480 + 13, 4591 .vsync_end = 480 + 13 + 2, 4592 .vtotal = 480 + 13 + 2 + 29, 4593 }; 4594 4595 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4596 .modes = &tfc_s9700rtwv43tr_01b_mode, 4597 .num_modes = 1, 4598 .bpc = 8, 4599 .size = { 4600 .width = 155, 4601 .height = 90, 4602 }, 4603 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4604 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4605 }; 4606 4607 static const struct display_timing tianma_tm070jdhg30_timing = { 4608 .pixelclock = { 62600000, 68200000, 78100000 }, 4609 .hactive = { 1280, 1280, 1280 }, 4610 .hfront_porch = { 15, 64, 159 }, 4611 .hback_porch = { 5, 5, 5 }, 4612 .hsync_len = { 1, 1, 256 }, 4613 .vactive = { 800, 800, 800 }, 4614 .vfront_porch = { 3, 40, 99 }, 4615 .vback_porch = { 2, 2, 2 }, 4616 .vsync_len = { 1, 1, 128 }, 4617 .flags = DISPLAY_FLAGS_DE_HIGH, 4618 }; 4619 4620 static const struct panel_desc tianma_tm070jdhg30 = { 4621 .timings = &tianma_tm070jdhg30_timing, 4622 .num_timings = 1, 4623 .bpc = 8, 4624 .size = { 4625 .width = 151, 4626 .height = 95, 4627 }, 4628 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4629 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4630 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4631 }; 4632 4633 static const struct panel_desc tianma_tm070jvhg33 = { 4634 .timings = &tianma_tm070jdhg30_timing, 4635 .num_timings = 1, 4636 .bpc = 8, 4637 .size = { 4638 .width = 150, 4639 .height = 94, 4640 }, 4641 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4642 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4643 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4644 }; 4645 4646 /* 4647 * The TM070JDHG34-00 datasheet computes total blanking as back porch + 4648 * front porch, not including sync pulse width. This is for both H and 4649 * V. To make the total blanking and period correct, subtract the pulse 4650 * width from the front porch. 4651 * 4652 * This works well for the Min and Typ values, but for Max values the sync 4653 * pulse width is higher than back porch + front porch, so work around that 4654 * by reducing the Max sync length value to 1 and then treating the Max 4655 * porches as in the Min and Typ cases. 4656 * 4657 * Exact datasheet values are added as a comment where they differ from the 4658 * ones implemented for the above reason. 4659 * 4660 * The P0700WXF1MBAA datasheet is even less detailed, only listing period 4661 * and total blanking time, however the resulting values are the same as 4662 * the TM070JDHG34-00. 4663 */ 4664 static const struct display_timing tianma_tm070jdhg34_00_timing = { 4665 .pixelclock = { 68400000, 71900000, 78100000 }, 4666 .hactive = { 1280, 1280, 1280 }, 4667 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4668 .hback_porch = { 5, 5, 5 }, 4669 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4670 .vactive = { 800, 800, 800 }, 4671 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4672 .vback_porch = { 2, 2, 2 }, 4673 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4674 .flags = DISPLAY_FLAGS_DE_HIGH, 4675 }; 4676 4677 static const struct panel_desc tianma_tm070jdhg34_00 = { 4678 .timings = &tianma_tm070jdhg34_00_timing, 4679 .num_timings = 1, 4680 .bpc = 8, 4681 .size = { 4682 .width = 150, /* 149.76 */ 4683 .height = 94, /* 93.60 */ 4684 }, 4685 .delay = { 4686 .prepare = 15, /* Tp1 */ 4687 .enable = 150, /* Tp2 */ 4688 .disable = 150, /* Tp4 */ 4689 .unprepare = 120, /* Tp3 */ 4690 }, 4691 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4692 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4693 }; 4694 4695 static const struct panel_desc tianma_p0700wxf1mbaa = { 4696 .timings = &tianma_tm070jdhg34_00_timing, 4697 .num_timings = 1, 4698 .bpc = 8, 4699 .size = { 4700 .width = 150, /* 149.76 */ 4701 .height = 94, /* 93.60 */ 4702 }, 4703 .delay = { 4704 .prepare = 18, /* Tr + Tp1 */ 4705 .enable = 152, /* Tp2 + Tp5 */ 4706 .disable = 152, /* Tp6 + Tp4 */ 4707 .unprepare = 120, /* Tp3 */ 4708 }, 4709 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4710 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4711 }; 4712 4713 static const struct display_timing tianma_tm070rvhg71_timing = { 4714 .pixelclock = { 27700000, 29200000, 39600000 }, 4715 .hactive = { 800, 800, 800 }, 4716 .hfront_porch = { 12, 40, 212 }, 4717 .hback_porch = { 88, 88, 88 }, 4718 .hsync_len = { 1, 1, 40 }, 4719 .vactive = { 480, 480, 480 }, 4720 .vfront_porch = { 1, 13, 88 }, 4721 .vback_porch = { 32, 32, 32 }, 4722 .vsync_len = { 1, 1, 3 }, 4723 .flags = DISPLAY_FLAGS_DE_HIGH, 4724 }; 4725 4726 static const struct panel_desc tianma_tm070rvhg71 = { 4727 .timings = &tianma_tm070rvhg71_timing, 4728 .num_timings = 1, 4729 .bpc = 8, 4730 .size = { 4731 .width = 154, 4732 .height = 86, 4733 }, 4734 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4735 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4736 }; 4737 4738 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4739 { 4740 .clock = 10000, 4741 .hdisplay = 320, 4742 .hsync_start = 320 + 50, 4743 .hsync_end = 320 + 50 + 6, 4744 .htotal = 320 + 50 + 6 + 38, 4745 .vdisplay = 240, 4746 .vsync_start = 240 + 3, 4747 .vsync_end = 240 + 3 + 1, 4748 .vtotal = 240 + 3 + 1 + 17, 4749 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4750 }, 4751 }; 4752 4753 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4754 .modes = ti_nspire_cx_lcd_mode, 4755 .num_modes = 1, 4756 .bpc = 8, 4757 .size = { 4758 .width = 65, 4759 .height = 49, 4760 }, 4761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4762 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4763 }; 4764 4765 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4766 { 4767 .clock = 10000, 4768 .hdisplay = 320, 4769 .hsync_start = 320 + 6, 4770 .hsync_end = 320 + 6 + 6, 4771 .htotal = 320 + 6 + 6 + 6, 4772 .vdisplay = 240, 4773 .vsync_start = 240 + 0, 4774 .vsync_end = 240 + 0 + 1, 4775 .vtotal = 240 + 0 + 1 + 0, 4776 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4777 }, 4778 }; 4779 4780 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4781 .modes = ti_nspire_classic_lcd_mode, 4782 .num_modes = 1, 4783 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4784 .bpc = 8, 4785 .size = { 4786 .width = 71, 4787 .height = 53, 4788 }, 4789 /* This is the grayscale bus format */ 4790 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4791 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4792 }; 4793 4794 static const struct display_timing topland_tian_g07017_01_timing = { 4795 .pixelclock = { 44900000, 51200000, 63000000 }, 4796 .hactive = { 1024, 1024, 1024 }, 4797 .hfront_porch = { 16, 160, 216 }, 4798 .hback_porch = { 160, 160, 160 }, 4799 .hsync_len = { 1, 1, 140 }, 4800 .vactive = { 600, 600, 600 }, 4801 .vfront_porch = { 1, 12, 127 }, 4802 .vback_porch = { 23, 23, 23 }, 4803 .vsync_len = { 1, 1, 20 }, 4804 }; 4805 4806 static const struct panel_desc topland_tian_g07017_01 = { 4807 .timings = &topland_tian_g07017_01_timing, 4808 .num_timings = 1, 4809 .bpc = 8, 4810 .size = { 4811 .width = 154, 4812 .height = 86, 4813 }, 4814 .delay = { 4815 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 4816 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 4817 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 4818 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 4819 }, 4820 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4821 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4822 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4823 }; 4824 4825 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4826 .clock = 79500, 4827 .hdisplay = 1280, 4828 .hsync_start = 1280 + 192, 4829 .hsync_end = 1280 + 192 + 128, 4830 .htotal = 1280 + 192 + 128 + 64, 4831 .vdisplay = 768, 4832 .vsync_start = 768 + 20, 4833 .vsync_end = 768 + 20 + 7, 4834 .vtotal = 768 + 20 + 7 + 3, 4835 }; 4836 4837 static const struct panel_desc toshiba_lt089ac29000 = { 4838 .modes = &toshiba_lt089ac29000_mode, 4839 .num_modes = 1, 4840 .size = { 4841 .width = 194, 4842 .height = 116, 4843 }, 4844 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4845 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4846 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4847 }; 4848 4849 static const struct drm_display_mode tpk_f07a_0102_mode = { 4850 .clock = 33260, 4851 .hdisplay = 800, 4852 .hsync_start = 800 + 40, 4853 .hsync_end = 800 + 40 + 128, 4854 .htotal = 800 + 40 + 128 + 88, 4855 .vdisplay = 480, 4856 .vsync_start = 480 + 10, 4857 .vsync_end = 480 + 10 + 2, 4858 .vtotal = 480 + 10 + 2 + 33, 4859 }; 4860 4861 static const struct panel_desc tpk_f07a_0102 = { 4862 .modes = &tpk_f07a_0102_mode, 4863 .num_modes = 1, 4864 .size = { 4865 .width = 152, 4866 .height = 91, 4867 }, 4868 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4869 }; 4870 4871 static const struct drm_display_mode tpk_f10a_0102_mode = { 4872 .clock = 45000, 4873 .hdisplay = 1024, 4874 .hsync_start = 1024 + 176, 4875 .hsync_end = 1024 + 176 + 5, 4876 .htotal = 1024 + 176 + 5 + 88, 4877 .vdisplay = 600, 4878 .vsync_start = 600 + 20, 4879 .vsync_end = 600 + 20 + 5, 4880 .vtotal = 600 + 20 + 5 + 25, 4881 }; 4882 4883 static const struct panel_desc tpk_f10a_0102 = { 4884 .modes = &tpk_f10a_0102_mode, 4885 .num_modes = 1, 4886 .size = { 4887 .width = 223, 4888 .height = 125, 4889 }, 4890 }; 4891 4892 static const struct display_timing urt_umsh_8596md_timing = { 4893 .pixelclock = { 33260000, 33260000, 33260000 }, 4894 .hactive = { 800, 800, 800 }, 4895 .hfront_porch = { 41, 41, 41 }, 4896 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4897 .hsync_len = { 71, 128, 128 }, 4898 .vactive = { 480, 480, 480 }, 4899 .vfront_porch = { 10, 10, 10 }, 4900 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4901 .vsync_len = { 2, 2, 2 }, 4902 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4903 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4904 }; 4905 4906 static const struct panel_desc urt_umsh_8596md_lvds = { 4907 .timings = &urt_umsh_8596md_timing, 4908 .num_timings = 1, 4909 .bpc = 6, 4910 .size = { 4911 .width = 152, 4912 .height = 91, 4913 }, 4914 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4915 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4916 }; 4917 4918 static const struct panel_desc urt_umsh_8596md_parallel = { 4919 .timings = &urt_umsh_8596md_timing, 4920 .num_timings = 1, 4921 .bpc = 6, 4922 .size = { 4923 .width = 152, 4924 .height = 91, 4925 }, 4926 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4927 }; 4928 4929 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4930 .clock = 60000, 4931 .hdisplay = 1024, 4932 .hsync_start = 1024 + 160, 4933 .hsync_end = 1024 + 160 + 100, 4934 .htotal = 1024 + 160 + 100 + 60, 4935 .vdisplay = 600, 4936 .vsync_start = 600 + 12, 4937 .vsync_end = 600 + 12 + 10, 4938 .vtotal = 600 + 12 + 10 + 13, 4939 }; 4940 4941 static const struct panel_desc vivax_tpc9150_panel = { 4942 .modes = &vivax_tpc9150_panel_mode, 4943 .num_modes = 1, 4944 .bpc = 6, 4945 .size = { 4946 .width = 200, 4947 .height = 115, 4948 }, 4949 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4950 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4951 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4952 }; 4953 4954 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4955 .clock = 33333, 4956 .hdisplay = 800, 4957 .hsync_start = 800 + 210, 4958 .hsync_end = 800 + 210 + 20, 4959 .htotal = 800 + 210 + 20 + 46, 4960 .vdisplay = 480, 4961 .vsync_start = 480 + 22, 4962 .vsync_end = 480 + 22 + 10, 4963 .vtotal = 480 + 22 + 10 + 23, 4964 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4965 }; 4966 4967 static const struct panel_desc vl050_8048nt_c01 = { 4968 .modes = &vl050_8048nt_c01_mode, 4969 .num_modes = 1, 4970 .bpc = 8, 4971 .size = { 4972 .width = 120, 4973 .height = 76, 4974 }, 4975 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4976 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4977 }; 4978 4979 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4980 .clock = 6410, 4981 .hdisplay = 320, 4982 .hsync_start = 320 + 20, 4983 .hsync_end = 320 + 20 + 30, 4984 .htotal = 320 + 20 + 30 + 38, 4985 .vdisplay = 240, 4986 .vsync_start = 240 + 4, 4987 .vsync_end = 240 + 4 + 3, 4988 .vtotal = 240 + 4 + 3 + 15, 4989 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4990 }; 4991 4992 static const struct panel_desc winstar_wf35ltiacd = { 4993 .modes = &winstar_wf35ltiacd_mode, 4994 .num_modes = 1, 4995 .bpc = 8, 4996 .size = { 4997 .width = 70, 4998 .height = 53, 4999 }, 5000 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5001 }; 5002 5003 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 5004 .clock = 51200, 5005 .hdisplay = 1024, 5006 .hsync_start = 1024 + 100, 5007 .hsync_end = 1024 + 100 + 100, 5008 .htotal = 1024 + 100 + 100 + 120, 5009 .vdisplay = 600, 5010 .vsync_start = 600 + 10, 5011 .vsync_end = 600 + 10 + 10, 5012 .vtotal = 600 + 10 + 10 + 15, 5013 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 5014 }; 5015 5016 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 5017 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 5018 .num_modes = 1, 5019 .bpc = 8, 5020 .size = { 5021 .width = 154, 5022 .height = 90, 5023 }, 5024 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5025 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5026 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5027 }; 5028 5029 static const struct drm_display_mode mchp_ac69t88a_mode = { 5030 .clock = 25000, 5031 .hdisplay = 800, 5032 .hsync_start = 800 + 88, 5033 .hsync_end = 800 + 88 + 5, 5034 .htotal = 800 + 88 + 5 + 40, 5035 .vdisplay = 480, 5036 .vsync_start = 480 + 23, 5037 .vsync_end = 480 + 23 + 5, 5038 .vtotal = 480 + 23 + 5 + 1, 5039 }; 5040 5041 static const struct panel_desc mchp_ac69t88a = { 5042 .modes = &mchp_ac69t88a_mode, 5043 .num_modes = 1, 5044 .bpc = 8, 5045 .size = { 5046 .width = 108, 5047 .height = 65, 5048 }, 5049 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5050 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 5051 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5052 }; 5053 5054 static const struct drm_display_mode arm_rtsm_mode[] = { 5055 { 5056 .clock = 65000, 5057 .hdisplay = 1024, 5058 .hsync_start = 1024 + 24, 5059 .hsync_end = 1024 + 24 + 136, 5060 .htotal = 1024 + 24 + 136 + 160, 5061 .vdisplay = 768, 5062 .vsync_start = 768 + 3, 5063 .vsync_end = 768 + 3 + 6, 5064 .vtotal = 768 + 3 + 6 + 29, 5065 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5066 }, 5067 }; 5068 5069 static const struct panel_desc arm_rtsm = { 5070 .modes = arm_rtsm_mode, 5071 .num_modes = 1, 5072 .bpc = 8, 5073 .size = { 5074 .width = 400, 5075 .height = 300, 5076 }, 5077 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5078 }; 5079 5080 static const struct of_device_id platform_of_match[] = { 5081 { 5082 .compatible = "ampire,am-1280800n3tzqw-t00h", 5083 .data = &ire_am_1280800n3tzqw_t00h, 5084 }, { 5085 .compatible = "ampire,am-480272h3tmqw-t01h", 5086 .data = &ire_am_480272h3tmqw_t01h, 5087 }, { 5088 .compatible = "ampire,am-800480l1tmqw-t00h", 5089 .data = &ire_am_800480l1tmqw_t00h, 5090 }, { 5091 .compatible = "ampire,am800480r3tmqwa1h", 5092 .data = &ire_am800480r3tmqwa1h, 5093 }, { 5094 .compatible = "ampire,am800600p5tmqw-tb8h", 5095 .data = &ire_am800600p5tmqwtb8h, 5096 }, { 5097 .compatible = "arm,rtsm-display", 5098 .data = &arm_rtsm, 5099 }, { 5100 .compatible = "armadeus,st0700-adapt", 5101 .data = &armadeus_st0700_adapt, 5102 }, { 5103 .compatible = "auo,b101aw03", 5104 .data = &auo_b101aw03, 5105 }, { 5106 .compatible = "auo,b101xtn01", 5107 .data = &auo_b101xtn01, 5108 }, { 5109 .compatible = "auo,b116xw03", 5110 .data = &auo_b116xw03, 5111 }, { 5112 .compatible = "auo,g070vvn01", 5113 .data = &auo_g070vvn01, 5114 }, { 5115 .compatible = "auo,g101evn010", 5116 .data = &auo_g101evn010, 5117 }, { 5118 .compatible = "auo,g104sn02", 5119 .data = &auo_g104sn02, 5120 }, { 5121 .compatible = "auo,g104stn01", 5122 .data = &auo_g104stn01, 5123 }, { 5124 .compatible = "auo,g121ean01", 5125 .data = &auo_g121ean01, 5126 }, { 5127 .compatible = "auo,g133han01", 5128 .data = &auo_g133han01, 5129 }, { 5130 .compatible = "auo,g156han04", 5131 .data = &auo_g156han04, 5132 }, { 5133 .compatible = "auo,g156xtn01", 5134 .data = &auo_g156xtn01, 5135 }, { 5136 .compatible = "auo,g185han01", 5137 .data = &auo_g185han01, 5138 }, { 5139 .compatible = "auo,g190ean01", 5140 .data = &auo_g190ean01, 5141 }, { 5142 .compatible = "auo,p238han01", 5143 .data = &auo_p238han01, 5144 }, { 5145 .compatible = "auo,p320hvn03", 5146 .data = &auo_p320hvn03, 5147 }, { 5148 .compatible = "auo,t215hvn01", 5149 .data = &auo_t215hvn01, 5150 }, { 5151 .compatible = "avic,tm070ddh03", 5152 .data = &avic_tm070ddh03, 5153 }, { 5154 .compatible = "bananapi,s070wv20-ct16", 5155 .data = &bananapi_s070wv20_ct16, 5156 }, { 5157 .compatible = "boe,av101hdt-a10", 5158 .data = &boe_av101hdt_a10, 5159 }, { 5160 .compatible = "boe,av123z7m-n17", 5161 .data = &boe_av123z7m_n17, 5162 }, { 5163 .compatible = "boe,bp082wx1-100", 5164 .data = &boe_bp082wx1_100, 5165 }, { 5166 .compatible = "boe,bp101wx1-100", 5167 .data = &boe_bp101wx1_100, 5168 }, { 5169 .compatible = "boe,ev121wxm-n10-1850", 5170 .data = &boe_ev121wxm_n10_1850, 5171 }, { 5172 .compatible = "boe,hv070wsa-100", 5173 .data = &boe_hv070wsa 5174 }, { 5175 .compatible = "cct,cmt430b19n00", 5176 .data = &cct_cmt430b19n00, 5177 }, { 5178 .compatible = "cdtech,s043wq26h-ct7", 5179 .data = &cdtech_s043wq26h_ct7, 5180 }, { 5181 .compatible = "cdtech,s070pws19hp-fc21", 5182 .data = &cdtech_s070pws19hp_fc21, 5183 }, { 5184 .compatible = "cdtech,s070swv29hg-dc44", 5185 .data = &cdtech_s070swv29hg_dc44, 5186 }, { 5187 .compatible = "cdtech,s070wv95-ct16", 5188 .data = &cdtech_s070wv95_ct16, 5189 }, { 5190 .compatible = "chefree,ch101olhlwh-002", 5191 .data = &chefree_ch101olhlwh_002, 5192 }, { 5193 .compatible = "chunghwa,claa070wp03xg", 5194 .data = &chunghwa_claa070wp03xg, 5195 }, { 5196 .compatible = "chunghwa,claa101wa01a", 5197 .data = &chunghwa_claa101wa01a 5198 }, { 5199 .compatible = "chunghwa,claa101wb01", 5200 .data = &chunghwa_claa101wb01 5201 }, { 5202 .compatible = "dataimage,fg040346dsswbg04", 5203 .data = &dataimage_fg040346dsswbg04, 5204 }, { 5205 .compatible = "dataimage,fg1001l0dsswmg01", 5206 .data = &dataimage_fg1001l0dsswmg01, 5207 }, { 5208 .compatible = "dataimage,scf0700c48ggu18", 5209 .data = &dataimage_scf0700c48ggu18, 5210 }, { 5211 .compatible = "dlc,dlc0700yzg-1", 5212 .data = &dlc_dlc0700yzg_1, 5213 }, { 5214 .compatible = "dlc,dlc1010gig", 5215 .data = &dlc_dlc1010gig, 5216 }, { 5217 .compatible = "edt,et035012dm6", 5218 .data = &edt_et035012dm6, 5219 }, { 5220 .compatible = "edt,etm0350g0dh6", 5221 .data = &edt_etm0350g0dh6, 5222 }, { 5223 .compatible = "edt,etm043080dh6gp", 5224 .data = &edt_etm043080dh6gp, 5225 }, { 5226 .compatible = "edt,etm0430g0dh6", 5227 .data = &edt_etm0430g0dh6, 5228 }, { 5229 .compatible = "edt,et057090dhu", 5230 .data = &edt_et057090dhu, 5231 }, { 5232 .compatible = "edt,et070080dh6", 5233 .data = &edt_etm0700g0dh6, 5234 }, { 5235 .compatible = "edt,etm0700g0dh6", 5236 .data = &edt_etm0700g0dh6, 5237 }, { 5238 .compatible = "edt,etm0700g0bdh6", 5239 .data = &edt_etm0700g0bdh6, 5240 }, { 5241 .compatible = "edt,etm0700g0edh6", 5242 .data = &edt_etm0700g0bdh6, 5243 }, { 5244 .compatible = "edt,etml0700y5dha", 5245 .data = &edt_etml0700y5dha, 5246 }, { 5247 .compatible = "edt,etml1010g3dra", 5248 .data = &edt_etml1010g3dra, 5249 }, { 5250 .compatible = "edt,etmv570g2dhu", 5251 .data = &edt_etmv570g2dhu, 5252 }, { 5253 .compatible = "eink,vb3300-kca", 5254 .data = &eink_vb3300_kca, 5255 }, { 5256 .compatible = "evervision,vgg644804", 5257 .data = &evervision_vgg644804, 5258 }, { 5259 .compatible = "evervision,vgg804821", 5260 .data = &evervision_vgg804821, 5261 }, { 5262 .compatible = "foxlink,fl500wvr00-a0t", 5263 .data = &foxlink_fl500wvr00_a0t, 5264 }, { 5265 .compatible = "frida,frd350h54004", 5266 .data = &frida_frd350h54004, 5267 }, { 5268 .compatible = "giantplus,gpg482739qs5", 5269 .data = &giantplus_gpg482739qs5 5270 }, { 5271 .compatible = "giantplus,gpm940b0", 5272 .data = &giantplus_gpm940b0, 5273 }, { 5274 .compatible = "hannstar,hsd070pww1", 5275 .data = &hannstar_hsd070pww1, 5276 }, { 5277 .compatible = "hannstar,hsd100pxn1", 5278 .data = &hannstar_hsd100pxn1, 5279 }, { 5280 .compatible = "hannstar,hsd101pww2", 5281 .data = &hannstar_hsd101pww2, 5282 }, { 5283 .compatible = "hannstar,hsd156juw2", 5284 .data = &hannstar_hsd156juw2, 5285 }, { 5286 .compatible = "hit,tx23d38vm0caa", 5287 .data = &hitachi_tx23d38vm0caa 5288 }, { 5289 .compatible = "innolux,at043tn24", 5290 .data = &innolux_at043tn24, 5291 }, { 5292 .compatible = "innolux,at070tn92", 5293 .data = &innolux_at070tn92, 5294 }, { 5295 .compatible = "innolux,g070ace-l01", 5296 .data = &innolux_g070ace_l01, 5297 }, { 5298 .compatible = "innolux,g070ace-lh3", 5299 .data = &innolux_g070ace_lh3, 5300 }, { 5301 .compatible = "innolux,g070y2-l01", 5302 .data = &innolux_g070y2_l01, 5303 }, { 5304 .compatible = "innolux,g070y2-t02", 5305 .data = &innolux_g070y2_t02, 5306 }, { 5307 .compatible = "innolux,g101ice-l01", 5308 .data = &innolux_g101ice_l01 5309 }, { 5310 .compatible = "innolux,g121i1-l01", 5311 .data = &innolux_g121i1_l01 5312 }, { 5313 .compatible = "innolux,g121x1-l03", 5314 .data = &innolux_g121x1_l03, 5315 }, { 5316 .compatible = "innolux,g121xce-l01", 5317 .data = &innolux_g121xce_l01, 5318 }, { 5319 .compatible = "innolux,g150xge-l05", 5320 .data = &innolux_g150xge_l05, 5321 }, { 5322 .compatible = "innolux,g156hce-l01", 5323 .data = &innolux_g156hce_l01, 5324 }, { 5325 .compatible = "innolux,n156bge-l21", 5326 .data = &innolux_n156bge_l21, 5327 }, { 5328 .compatible = "innolux,zj070na-01p", 5329 .data = &innolux_zj070na_01p, 5330 }, { 5331 .compatible = "jutouch,jt101tm023", 5332 .data = &jutouch_jt101tm023, 5333 }, { 5334 .compatible = "koe,tx14d24vm1bpa", 5335 .data = &koe_tx14d24vm1bpa, 5336 }, { 5337 .compatible = "koe,tx26d202vm0bwa", 5338 .data = &koe_tx26d202vm0bwa, 5339 }, { 5340 .compatible = "koe,tx31d200vm0baa", 5341 .data = &koe_tx31d200vm0baa, 5342 }, { 5343 .compatible = "kyo,tcg121xglp", 5344 .data = &kyo_tcg121xglp, 5345 }, { 5346 .compatible = "lemaker,bl035-rgb-002", 5347 .data = &lemaker_bl035_rgb_002, 5348 }, { 5349 .compatible = "lg,lb070wv8", 5350 .data = &lg_lb070wv8, 5351 }, { 5352 .compatible = "lincolntech,lcd185-101ct", 5353 .data = &lincolntech_lcd185_101ct, 5354 }, { 5355 .compatible = "logicpd,type28", 5356 .data = &logicpd_type_28, 5357 }, { 5358 .compatible = "logictechno,lt161010-2nhc", 5359 .data = &logictechno_lt161010_2nh, 5360 }, { 5361 .compatible = "logictechno,lt161010-2nhr", 5362 .data = &logictechno_lt161010_2nh, 5363 }, { 5364 .compatible = "logictechno,lt170410-2whc", 5365 .data = &logictechno_lt170410_2whc, 5366 }, { 5367 .compatible = "logictechno,lttd800480070-l2rt", 5368 .data = &logictechno_lttd800480070_l2rt, 5369 }, { 5370 .compatible = "logictechno,lttd800480070-l6wh-rt", 5371 .data = &logictechno_lttd800480070_l6wh_rt, 5372 }, { 5373 .compatible = "microtips,mf-101hiebcaf0", 5374 .data = µtips_mf_101hiebcaf0_c, 5375 }, { 5376 .compatible = "microtips,mf-103hieb0ga0", 5377 .data = µtips_mf_103hieb0ga0, 5378 }, { 5379 .compatible = "mitsubishi,aa070mc01-ca1", 5380 .data = &mitsubishi_aa070mc01, 5381 }, { 5382 .compatible = "mitsubishi,aa084xe01", 5383 .data = &mitsubishi_aa084xe01, 5384 }, { 5385 .compatible = "multi-inno,mi0700a2t-30", 5386 .data = &multi_inno_mi0700a2t_30, 5387 }, { 5388 .compatible = "multi-inno,mi0700s4t-6", 5389 .data = &multi_inno_mi0700s4t_6, 5390 }, { 5391 .compatible = "multi-inno,mi0800ft-9", 5392 .data = &multi_inno_mi0800ft_9, 5393 }, { 5394 .compatible = "multi-inno,mi1010ait-1cp", 5395 .data = &multi_inno_mi1010ait_1cp, 5396 }, { 5397 .compatible = "multi-inno,mi1010z1t-1cp11", 5398 .data = &multi_inno_mi1010z1t_1cp11, 5399 }, { 5400 .compatible = "nec,nl12880bc20-05", 5401 .data = &nec_nl12880bc20_05, 5402 }, { 5403 .compatible = "nec,nl4827hc19-05b", 5404 .data = &nec_nl4827hc19_05b, 5405 }, { 5406 .compatible = "netron-dy,e231732", 5407 .data = &netron_dy_e231732, 5408 }, { 5409 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 5410 .data = &newhaven_nhd_43_480272ef_atxl, 5411 }, { 5412 .compatible = "nlt,nl13676bc25-03f", 5413 .data = &nlt_nl13676bc25_03f, 5414 }, { 5415 .compatible = "nlt,nl192108ac18-02d", 5416 .data = &nlt_nl192108ac18_02d, 5417 }, { 5418 .compatible = "nvd,9128", 5419 .data = &nvd_9128, 5420 }, { 5421 .compatible = "okaya,rs800480t-7x0gp", 5422 .data = &okaya_rs800480t_7x0gp, 5423 }, { 5424 .compatible = "olimex,lcd-olinuxino-43-ts", 5425 .data = &olimex_lcd_olinuxino_43ts, 5426 }, { 5427 .compatible = "olimex,lcd-olinuxino-5-cts", 5428 .data = &olimex_lcd_olinuxino_5cts, 5429 }, { 5430 .compatible = "ontat,kd50g21-40nt-a1", 5431 .data = &ontat_kd50g21_40nt_a1, 5432 }, { 5433 .compatible = "ontat,yx700wv03", 5434 .data = &ontat_yx700wv03, 5435 }, { 5436 .compatible = "ortustech,com37h3m05dtc", 5437 .data = &ortustech_com37h3m, 5438 }, { 5439 .compatible = "ortustech,com37h3m99dtc", 5440 .data = &ortustech_com37h3m, 5441 }, { 5442 .compatible = "ortustech,com43h4m85ulc", 5443 .data = &ortustech_com43h4m85ulc, 5444 }, { 5445 .compatible = "osddisplays,osd070t1718-19ts", 5446 .data = &osddisplays_osd070t1718_19ts, 5447 }, { 5448 .compatible = "pda,91-00156-a0", 5449 .data = &pda_91_00156_a0, 5450 }, { 5451 .compatible = "powertip,ph128800t004-zza01", 5452 .data = &powertip_ph128800t004_zza01, 5453 }, { 5454 .compatible = "powertip,ph128800t006-zhc01", 5455 .data = &powertip_ph128800t006_zhc01, 5456 }, { 5457 .compatible = "powertip,ph800480t013-idf02", 5458 .data = &powertip_ph800480t013_idf02, 5459 }, { 5460 .compatible = "primeview,pm070wl4", 5461 .data = &primeview_pm070wl4, 5462 }, { 5463 .compatible = "qiaodian,qd43003c0-40", 5464 .data = &qd43003c0_40, 5465 }, { 5466 .compatible = "qishenglong,gopher2b-lcd", 5467 .data = &qishenglong_gopher2b_lcd, 5468 }, { 5469 .compatible = "raystar,rff500f-awh-dnn", 5470 .data = &raystar_rff500f_awh_dnn, 5471 }, { 5472 .compatible = "rocktech,rk043fn48h", 5473 .data = &rocktech_rk043fn48h, 5474 }, { 5475 .compatible = "rocktech,rk070er9427", 5476 .data = &rocktech_rk070er9427, 5477 }, { 5478 .compatible = "rocktech,rk101ii01d-ct", 5479 .data = &rocktech_rk101ii01d_ct, 5480 }, { 5481 .compatible = "samsung,ltl101al01", 5482 .data = &samsung_ltl101al01, 5483 }, { 5484 .compatible = "samsung,ltl106al01", 5485 .data = &samsung_ltl106al01, 5486 }, { 5487 .compatible = "samsung,ltn101nt05", 5488 .data = &samsung_ltn101nt05, 5489 }, { 5490 .compatible = "satoz,sat050at40h12r2", 5491 .data = &satoz_sat050at40h12r2, 5492 }, { 5493 .compatible = "sharp,lq035q7db03", 5494 .data = &sharp_lq035q7db03, 5495 }, { 5496 .compatible = "sharp,lq070y3dg3b", 5497 .data = &sharp_lq070y3dg3b, 5498 }, { 5499 .compatible = "sharp,lq101k1ly04", 5500 .data = &sharp_lq101k1ly04, 5501 }, { 5502 .compatible = "sharp,ls020b1dd01d", 5503 .data = &sharp_ls020b1dd01d, 5504 }, { 5505 .compatible = "shelly,sca07010-bfn-lnn", 5506 .data = &shelly_sca07010_bfn_lnn, 5507 }, { 5508 .compatible = "starry,kr070pe2t", 5509 .data = &starry_kr070pe2t, 5510 }, { 5511 .compatible = "startek,kd070wvfpa", 5512 .data = &startek_kd070wvfpa, 5513 }, { 5514 .compatible = "team-source-display,tst043015cmhx", 5515 .data = &tsd_tst043015cmhx, 5516 }, { 5517 .compatible = "tfc,s9700rtwv43tr-01b", 5518 .data = &tfc_s9700rtwv43tr_01b, 5519 }, { 5520 .compatible = "tianma,p0700wxf1mbaa", 5521 .data = &tianma_p0700wxf1mbaa, 5522 }, { 5523 .compatible = "tianma,tm070jdhg30", 5524 .data = &tianma_tm070jdhg30, 5525 }, { 5526 .compatible = "tianma,tm070jdhg34-00", 5527 .data = &tianma_tm070jdhg34_00, 5528 }, { 5529 .compatible = "tianma,tm070jvhg33", 5530 .data = &tianma_tm070jvhg33, 5531 }, { 5532 .compatible = "tianma,tm070rvhg71", 5533 .data = &tianma_tm070rvhg71, 5534 }, { 5535 .compatible = "ti,nspire-cx-lcd-panel", 5536 .data = &ti_nspire_cx_lcd_panel, 5537 }, { 5538 .compatible = "ti,nspire-classic-lcd-panel", 5539 .data = &ti_nspire_classic_lcd_panel, 5540 }, { 5541 .compatible = "toshiba,lt089ac29000", 5542 .data = &toshiba_lt089ac29000, 5543 }, { 5544 .compatible = "topland,tian-g07017-01", 5545 .data = &topland_tian_g07017_01, 5546 }, { 5547 .compatible = "tpk,f07a-0102", 5548 .data = &tpk_f07a_0102, 5549 }, { 5550 .compatible = "tpk,f10a-0102", 5551 .data = &tpk_f10a_0102, 5552 }, { 5553 .compatible = "urt,umsh-8596md-t", 5554 .data = &urt_umsh_8596md_parallel, 5555 }, { 5556 .compatible = "urt,umsh-8596md-1t", 5557 .data = &urt_umsh_8596md_parallel, 5558 }, { 5559 .compatible = "urt,umsh-8596md-7t", 5560 .data = &urt_umsh_8596md_parallel, 5561 }, { 5562 .compatible = "urt,umsh-8596md-11t", 5563 .data = &urt_umsh_8596md_lvds, 5564 }, { 5565 .compatible = "urt,umsh-8596md-19t", 5566 .data = &urt_umsh_8596md_lvds, 5567 }, { 5568 .compatible = "urt,umsh-8596md-20t", 5569 .data = &urt_umsh_8596md_parallel, 5570 }, { 5571 .compatible = "vivax,tpc9150-panel", 5572 .data = &vivax_tpc9150_panel, 5573 }, { 5574 .compatible = "vxt,vl050-8048nt-c01", 5575 .data = &vl050_8048nt_c01, 5576 }, { 5577 .compatible = "winstar,wf35ltiacd", 5578 .data = &winstar_wf35ltiacd, 5579 }, { 5580 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 5581 .data = &yes_optoelectronics_ytc700tlag_05_201c, 5582 }, { 5583 .compatible = "microchip,ac69t88a", 5584 .data = &mchp_ac69t88a, 5585 }, { 5586 /* Must be the last entry */ 5587 .compatible = "panel-dpi", 5588 5589 /* 5590 * Explicitly NULL, the panel_desc structure will be 5591 * allocated by panel_dpi_probe(). 5592 */ 5593 .data = NULL, 5594 }, { 5595 /* sentinel */ 5596 } 5597 }; 5598 MODULE_DEVICE_TABLE(of, platform_of_match); 5599 5600 static int panel_simple_platform_probe(struct platform_device *pdev) 5601 { 5602 struct panel_simple *panel; 5603 5604 panel = panel_simple_probe(&pdev->dev); 5605 if (IS_ERR(panel)) 5606 return PTR_ERR(panel); 5607 5608 return 0; 5609 } 5610 5611 static void panel_simple_platform_remove(struct platform_device *pdev) 5612 { 5613 panel_simple_remove(&pdev->dev); 5614 } 5615 5616 static void panel_simple_platform_shutdown(struct platform_device *pdev) 5617 { 5618 panel_simple_shutdown(&pdev->dev); 5619 } 5620 5621 static const struct dev_pm_ops panel_simple_pm_ops = { 5622 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 5623 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5624 pm_runtime_force_resume) 5625 }; 5626 5627 static struct platform_driver panel_simple_platform_driver = { 5628 .driver = { 5629 .name = "panel-simple", 5630 .of_match_table = platform_of_match, 5631 .pm = &panel_simple_pm_ops, 5632 }, 5633 .probe = panel_simple_platform_probe, 5634 .remove = panel_simple_platform_remove, 5635 .shutdown = panel_simple_platform_shutdown, 5636 }; 5637 5638 static const struct drm_display_mode auo_b080uan01_mode = { 5639 .clock = 154500, 5640 .hdisplay = 1200, 5641 .hsync_start = 1200 + 62, 5642 .hsync_end = 1200 + 62 + 4, 5643 .htotal = 1200 + 62 + 4 + 62, 5644 .vdisplay = 1920, 5645 .vsync_start = 1920 + 9, 5646 .vsync_end = 1920 + 9 + 2, 5647 .vtotal = 1920 + 9 + 2 + 8, 5648 }; 5649 5650 static const struct panel_desc_dsi auo_b080uan01 = { 5651 .desc = { 5652 .modes = &auo_b080uan01_mode, 5653 .num_modes = 1, 5654 .bpc = 8, 5655 .size = { 5656 .width = 108, 5657 .height = 272, 5658 }, 5659 .connector_type = DRM_MODE_CONNECTOR_DSI, 5660 }, 5661 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5662 .format = MIPI_DSI_FMT_RGB888, 5663 .lanes = 4, 5664 }; 5665 5666 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5667 .clock = 160000, 5668 .hdisplay = 1200, 5669 .hsync_start = 1200 + 120, 5670 .hsync_end = 1200 + 120 + 20, 5671 .htotal = 1200 + 120 + 20 + 21, 5672 .vdisplay = 1920, 5673 .vsync_start = 1920 + 21, 5674 .vsync_end = 1920 + 21 + 3, 5675 .vtotal = 1920 + 21 + 3 + 18, 5676 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5677 }; 5678 5679 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5680 .desc = { 5681 .modes = &boe_tv080wum_nl0_mode, 5682 .num_modes = 1, 5683 .size = { 5684 .width = 107, 5685 .height = 172, 5686 }, 5687 .connector_type = DRM_MODE_CONNECTOR_DSI, 5688 }, 5689 .flags = MIPI_DSI_MODE_VIDEO | 5690 MIPI_DSI_MODE_VIDEO_BURST | 5691 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5692 .format = MIPI_DSI_FMT_RGB888, 5693 .lanes = 4, 5694 }; 5695 5696 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5697 .clock = 67000, 5698 .hdisplay = 720, 5699 .hsync_start = 720 + 12, 5700 .hsync_end = 720 + 12 + 4, 5701 .htotal = 720 + 12 + 4 + 112, 5702 .vdisplay = 1280, 5703 .vsync_start = 1280 + 8, 5704 .vsync_end = 1280 + 8 + 4, 5705 .vtotal = 1280 + 8 + 4 + 12, 5706 }; 5707 5708 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5709 .desc = { 5710 .modes = &lg_lh500wx1_sd03_mode, 5711 .num_modes = 1, 5712 .bpc = 8, 5713 .size = { 5714 .width = 62, 5715 .height = 110, 5716 }, 5717 .connector_type = DRM_MODE_CONNECTOR_DSI, 5718 }, 5719 .flags = MIPI_DSI_MODE_VIDEO, 5720 .format = MIPI_DSI_FMT_RGB888, 5721 .lanes = 4, 5722 }; 5723 5724 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5725 .clock = 157200, 5726 .hdisplay = 1920, 5727 .hsync_start = 1920 + 154, 5728 .hsync_end = 1920 + 154 + 16, 5729 .htotal = 1920 + 154 + 16 + 32, 5730 .vdisplay = 1200, 5731 .vsync_start = 1200 + 17, 5732 .vsync_end = 1200 + 17 + 2, 5733 .vtotal = 1200 + 17 + 2 + 16, 5734 }; 5735 5736 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5737 .desc = { 5738 .modes = &panasonic_vvx10f004b00_mode, 5739 .num_modes = 1, 5740 .bpc = 8, 5741 .size = { 5742 .width = 217, 5743 .height = 136, 5744 }, 5745 .connector_type = DRM_MODE_CONNECTOR_DSI, 5746 }, 5747 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5748 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5749 .format = MIPI_DSI_FMT_RGB888, 5750 .lanes = 4, 5751 }; 5752 5753 static const struct drm_display_mode lg_acx467akm_7_mode = { 5754 .clock = 150000, 5755 .hdisplay = 1080, 5756 .hsync_start = 1080 + 2, 5757 .hsync_end = 1080 + 2 + 2, 5758 .htotal = 1080 + 2 + 2 + 2, 5759 .vdisplay = 1920, 5760 .vsync_start = 1920 + 2, 5761 .vsync_end = 1920 + 2 + 2, 5762 .vtotal = 1920 + 2 + 2 + 2, 5763 }; 5764 5765 static const struct panel_desc_dsi lg_acx467akm_7 = { 5766 .desc = { 5767 .modes = &lg_acx467akm_7_mode, 5768 .num_modes = 1, 5769 .bpc = 8, 5770 .size = { 5771 .width = 62, 5772 .height = 110, 5773 }, 5774 .connector_type = DRM_MODE_CONNECTOR_DSI, 5775 }, 5776 .flags = 0, 5777 .format = MIPI_DSI_FMT_RGB888, 5778 .lanes = 4, 5779 }; 5780 5781 static const struct drm_display_mode osd101t2045_53ts_mode = { 5782 .clock = 154500, 5783 .hdisplay = 1920, 5784 .hsync_start = 1920 + 112, 5785 .hsync_end = 1920 + 112 + 16, 5786 .htotal = 1920 + 112 + 16 + 32, 5787 .vdisplay = 1200, 5788 .vsync_start = 1200 + 16, 5789 .vsync_end = 1200 + 16 + 2, 5790 .vtotal = 1200 + 16 + 2 + 16, 5791 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5792 }; 5793 5794 static const struct panel_desc_dsi osd101t2045_53ts = { 5795 .desc = { 5796 .modes = &osd101t2045_53ts_mode, 5797 .num_modes = 1, 5798 .bpc = 8, 5799 .size = { 5800 .width = 217, 5801 .height = 136, 5802 }, 5803 .connector_type = DRM_MODE_CONNECTOR_DSI, 5804 }, 5805 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5806 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5807 MIPI_DSI_MODE_NO_EOT_PACKET, 5808 .format = MIPI_DSI_FMT_RGB888, 5809 .lanes = 4, 5810 }; 5811 5812 static const struct of_device_id dsi_of_match[] = { 5813 { 5814 .compatible = "auo,b080uan01", 5815 .data = &auo_b080uan01 5816 }, { 5817 .compatible = "boe,tv080wum-nl0", 5818 .data = &boe_tv080wum_nl0 5819 }, { 5820 .compatible = "lg,lh500wx1-sd03", 5821 .data = &lg_lh500wx1_sd03 5822 }, { 5823 .compatible = "panasonic,vvx10f004b00", 5824 .data = &panasonic_vvx10f004b00 5825 }, { 5826 .compatible = "lg,acx467akm-7", 5827 .data = &lg_acx467akm_7 5828 }, { 5829 .compatible = "osddisplays,osd101t2045-53ts", 5830 .data = &osd101t2045_53ts 5831 }, { 5832 /* sentinel */ 5833 } 5834 }; 5835 MODULE_DEVICE_TABLE(of, dsi_of_match); 5836 5837 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5838 { 5839 const struct panel_desc_dsi *desc; 5840 struct panel_simple *panel; 5841 int err; 5842 5843 panel = panel_simple_probe(&dsi->dev); 5844 if (IS_ERR(panel)) 5845 return PTR_ERR(panel); 5846 5847 desc = container_of(panel->desc, struct panel_desc_dsi, desc); 5848 dsi->mode_flags = desc->flags; 5849 dsi->format = desc->format; 5850 dsi->lanes = desc->lanes; 5851 5852 err = mipi_dsi_attach(dsi); 5853 if (err) { 5854 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5855 5856 drm_panel_remove(&panel->base); 5857 } 5858 5859 return err; 5860 } 5861 5862 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5863 { 5864 int err; 5865 5866 err = mipi_dsi_detach(dsi); 5867 if (err < 0) 5868 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5869 5870 panel_simple_remove(&dsi->dev); 5871 } 5872 5873 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5874 { 5875 panel_simple_shutdown(&dsi->dev); 5876 } 5877 5878 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5879 .driver = { 5880 .name = "panel-simple-dsi", 5881 .of_match_table = dsi_of_match, 5882 .pm = &panel_simple_pm_ops, 5883 }, 5884 .probe = panel_simple_dsi_probe, 5885 .remove = panel_simple_dsi_remove, 5886 .shutdown = panel_simple_dsi_shutdown, 5887 }; 5888 5889 static int __init panel_simple_init(void) 5890 { 5891 int err; 5892 5893 err = platform_driver_register(&panel_simple_platform_driver); 5894 if (err < 0) 5895 return err; 5896 5897 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5898 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5899 if (err < 0) 5900 goto err_did_platform_register; 5901 } 5902 5903 return 0; 5904 5905 err_did_platform_register: 5906 platform_driver_unregister(&panel_simple_platform_driver); 5907 5908 return err; 5909 } 5910 module_init(panel_simple_init); 5911 5912 static void __exit panel_simple_exit(void) 5913 { 5914 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5915 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5916 5917 platform_driver_unregister(&panel_simple_platform_driver); 5918 } 5919 module_exit(panel_simple_exit); 5920 5921 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5922 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5923 MODULE_LICENSE("GPL and additional rights"); 5924