1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 142 ktime_t unprepared_time; 143 144 const struct panel_desc *desc; 145 146 struct regulator *supply; 147 struct i2c_adapter *ddc; 148 149 struct gpio_desc *enable_gpio; 150 151 const struct drm_edid *drm_edid; 152 153 struct drm_display_mode override_mode; 154 155 enum drm_panel_orientation orientation; 156 }; 157 158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 159 { 160 return container_of(panel, struct panel_simple, base); 161 } 162 163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 164 struct drm_connector *connector) 165 { 166 struct drm_display_mode *mode; 167 unsigned int i, num = 0; 168 169 for (i = 0; i < panel->desc->num_timings; i++) { 170 const struct display_timing *dt = &panel->desc->timings[i]; 171 struct videomode vm; 172 173 videomode_from_timing(dt, &vm); 174 mode = drm_mode_create(connector->dev); 175 if (!mode) { 176 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 177 dt->hactive.typ, dt->vactive.typ); 178 continue; 179 } 180 181 drm_display_mode_from_videomode(&vm, mode); 182 183 mode->type |= DRM_MODE_TYPE_DRIVER; 184 185 if (panel->desc->num_timings == 1) 186 mode->type |= DRM_MODE_TYPE_PREFERRED; 187 188 drm_mode_probed_add(connector, mode); 189 num++; 190 } 191 192 return num; 193 } 194 195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 196 struct drm_connector *connector) 197 { 198 struct drm_display_mode *mode; 199 unsigned int i, num = 0; 200 201 for (i = 0; i < panel->desc->num_modes; i++) { 202 const struct drm_display_mode *m = &panel->desc->modes[i]; 203 204 mode = drm_mode_duplicate(connector->dev, m); 205 if (!mode) { 206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 207 m->hdisplay, m->vdisplay, 208 drm_mode_vrefresh(m)); 209 continue; 210 } 211 212 mode->type |= DRM_MODE_TYPE_DRIVER; 213 214 if (panel->desc->num_modes == 1) 215 mode->type |= DRM_MODE_TYPE_PREFERRED; 216 217 drm_mode_set_name(mode); 218 219 drm_mode_probed_add(connector, mode); 220 num++; 221 } 222 223 return num; 224 } 225 226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 227 struct drm_connector *connector) 228 { 229 struct drm_display_mode *mode; 230 bool has_override = panel->override_mode.type; 231 unsigned int num = 0; 232 233 if (!panel->desc) 234 return 0; 235 236 if (has_override) { 237 mode = drm_mode_duplicate(connector->dev, 238 &panel->override_mode); 239 if (mode) { 240 drm_mode_probed_add(connector, mode); 241 num = 1; 242 } else { 243 dev_err(panel->base.dev, "failed to add override mode\n"); 244 } 245 } 246 247 /* Only add timings if override was not there or failed to validate */ 248 if (num == 0 && panel->desc->num_timings) 249 num = panel_simple_get_timings_modes(panel, connector); 250 251 /* 252 * Only add fixed modes if timings/override added no mode. 253 * 254 * We should only ever have either the display timings specified 255 * or a fixed mode. Anything else is rather bogus. 256 */ 257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 258 if (num == 0) 259 num = panel_simple_get_display_modes(panel, connector); 260 261 connector->display_info.bpc = panel->desc->bpc; 262 connector->display_info.width_mm = panel->desc->size.width; 263 connector->display_info.height_mm = panel->desc->size.height; 264 if (panel->desc->bus_format) 265 drm_display_info_set_bus_formats(&connector->display_info, 266 &panel->desc->bus_format, 1); 267 connector->display_info.bus_flags = panel->desc->bus_flags; 268 269 return num; 270 } 271 272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 273 { 274 ktime_t now_ktime, min_ktime; 275 276 if (!min_ms) 277 return; 278 279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 280 now_ktime = ktime_get_boottime(); 281 282 if (ktime_before(now_ktime, min_ktime)) 283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 284 } 285 286 static int panel_simple_disable(struct drm_panel *panel) 287 { 288 struct panel_simple *p = to_panel_simple(panel); 289 290 if (p->desc->delay.disable) 291 msleep(p->desc->delay.disable); 292 293 return 0; 294 } 295 296 static int panel_simple_suspend(struct device *dev) 297 { 298 struct panel_simple *p = dev_get_drvdata(dev); 299 300 gpiod_set_value_cansleep(p->enable_gpio, 0); 301 regulator_disable(p->supply); 302 p->unprepared_time = ktime_get_boottime(); 303 304 drm_edid_free(p->drm_edid); 305 p->drm_edid = NULL; 306 307 return 0; 308 } 309 310 static int panel_simple_unprepare(struct drm_panel *panel) 311 { 312 int ret; 313 314 pm_runtime_mark_last_busy(panel->dev); 315 ret = pm_runtime_put_autosuspend(panel->dev); 316 if (ret < 0) 317 return ret; 318 319 return 0; 320 } 321 322 static int panel_simple_resume(struct device *dev) 323 { 324 struct panel_simple *p = dev_get_drvdata(dev); 325 int err; 326 327 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 328 329 err = regulator_enable(p->supply); 330 if (err < 0) { 331 dev_err(dev, "failed to enable supply: %d\n", err); 332 return err; 333 } 334 335 gpiod_set_value_cansleep(p->enable_gpio, 1); 336 337 if (p->desc->delay.prepare) 338 msleep(p->desc->delay.prepare); 339 340 return 0; 341 } 342 343 static int panel_simple_prepare(struct drm_panel *panel) 344 { 345 int ret; 346 347 ret = pm_runtime_get_sync(panel->dev); 348 if (ret < 0) { 349 pm_runtime_put_autosuspend(panel->dev); 350 return ret; 351 } 352 353 return 0; 354 } 355 356 static int panel_simple_enable(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 360 if (p->desc->delay.enable) 361 msleep(p->desc->delay.enable); 362 363 return 0; 364 } 365 366 static int panel_simple_get_modes(struct drm_panel *panel, 367 struct drm_connector *connector) 368 { 369 struct panel_simple *p = to_panel_simple(panel); 370 int num = 0; 371 372 /* probe EDID if a DDC bus is available */ 373 if (p->ddc) { 374 pm_runtime_get_sync(panel->dev); 375 376 if (!p->drm_edid) 377 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 378 379 drm_edid_connector_update(connector, p->drm_edid); 380 381 num += drm_edid_connector_add_modes(connector); 382 383 pm_runtime_mark_last_busy(panel->dev); 384 pm_runtime_put_autosuspend(panel->dev); 385 } 386 387 /* add hard-coded panel modes */ 388 num += panel_simple_get_non_edid_modes(p, connector); 389 390 /* 391 * TODO: Remove once all drm drivers call 392 * drm_connector_set_orientation_from_panel() 393 */ 394 drm_connector_set_panel_orientation(connector, p->orientation); 395 396 return num; 397 } 398 399 static int panel_simple_get_timings(struct drm_panel *panel, 400 unsigned int num_timings, 401 struct display_timing *timings) 402 { 403 struct panel_simple *p = to_panel_simple(panel); 404 unsigned int i; 405 406 if (p->desc->num_timings < num_timings) 407 num_timings = p->desc->num_timings; 408 409 if (timings) 410 for (i = 0; i < num_timings; i++) 411 timings[i] = p->desc->timings[i]; 412 413 return p->desc->num_timings; 414 } 415 416 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 417 { 418 struct panel_simple *p = to_panel_simple(panel); 419 420 return p->orientation; 421 } 422 423 static const struct drm_panel_funcs panel_simple_funcs = { 424 .disable = panel_simple_disable, 425 .unprepare = panel_simple_unprepare, 426 .prepare = panel_simple_prepare, 427 .enable = panel_simple_enable, 428 .get_modes = panel_simple_get_modes, 429 .get_orientation = panel_simple_get_orientation, 430 .get_timings = panel_simple_get_timings, 431 }; 432 433 static struct panel_desc panel_dpi; 434 435 static int panel_dpi_probe(struct device *dev, 436 struct panel_simple *panel) 437 { 438 struct display_timing *timing; 439 const struct device_node *np; 440 struct panel_desc *desc; 441 unsigned int bus_flags; 442 struct videomode vm; 443 int ret; 444 445 np = dev->of_node; 446 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 447 if (!desc) 448 return -ENOMEM; 449 450 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 451 if (!timing) 452 return -ENOMEM; 453 454 ret = of_get_display_timing(np, "panel-timing", timing); 455 if (ret < 0) { 456 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 457 np); 458 return ret; 459 } 460 461 desc->timings = timing; 462 desc->num_timings = 1; 463 464 of_property_read_u32(np, "width-mm", &desc->size.width); 465 of_property_read_u32(np, "height-mm", &desc->size.height); 466 467 /* Extract bus_flags from display_timing */ 468 bus_flags = 0; 469 vm.flags = timing->flags; 470 drm_bus_flags_from_videomode(&vm, &bus_flags); 471 desc->bus_flags = bus_flags; 472 473 /* We do not know the connector for the DT node, so guess it */ 474 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 475 476 panel->desc = desc; 477 478 return 0; 479 } 480 481 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 482 (to_check->field.typ >= bounds->field.min && \ 483 to_check->field.typ <= bounds->field.max) 484 static void panel_simple_parse_panel_timing_node(struct device *dev, 485 struct panel_simple *panel, 486 const struct display_timing *ot) 487 { 488 const struct panel_desc *desc = panel->desc; 489 struct videomode vm; 490 unsigned int i; 491 492 if (WARN_ON(desc->num_modes)) { 493 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 494 return; 495 } 496 if (WARN_ON(!desc->num_timings)) { 497 dev_err(dev, "Reject override mode: no timings specified\n"); 498 return; 499 } 500 501 for (i = 0; i < panel->desc->num_timings; i++) { 502 const struct display_timing *dt = &panel->desc->timings[i]; 503 504 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 505 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 506 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 507 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 508 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 512 continue; 513 514 if (ot->flags != dt->flags) 515 continue; 516 517 videomode_from_timing(ot, &vm); 518 drm_display_mode_from_videomode(&vm, &panel->override_mode); 519 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 520 DRM_MODE_TYPE_PREFERRED; 521 break; 522 } 523 524 if (WARN_ON(!panel->override_mode.type)) 525 dev_err(dev, "Reject override mode: No display_timing found\n"); 526 } 527 528 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 529 struct panel_simple *panel) 530 { 531 int ret, bpc; 532 533 ret = drm_of_lvds_get_data_mapping(dev->of_node); 534 if (ret < 0) { 535 if (ret == -EINVAL) 536 dev_warn(dev, "Ignore invalid data-mapping property\n"); 537 538 /* 539 * Ignore non-existing or malformatted property, fallback to 540 * default data-mapping, and return 0. 541 */ 542 return 0; 543 } 544 545 switch (ret) { 546 default: 547 WARN_ON(1); 548 fallthrough; 549 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 550 fallthrough; 551 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 552 bpc = 8; 553 break; 554 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 555 bpc = 6; 556 } 557 558 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 559 struct panel_desc *override_desc; 560 561 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 562 if (!override_desc) 563 return -ENOMEM; 564 565 override_desc->bus_format = ret; 566 override_desc->bpc = bpc; 567 panel->desc = override_desc; 568 } 569 570 return 0; 571 } 572 573 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 574 { 575 struct panel_simple *panel; 576 struct display_timing dt; 577 struct device_node *ddc; 578 int connector_type; 579 u32 bus_flags; 580 int err; 581 582 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 583 &panel_simple_funcs, desc->connector_type); 584 if (IS_ERR(panel)) 585 return PTR_ERR(panel); 586 587 panel->desc = desc; 588 589 panel->supply = devm_regulator_get(dev, "power"); 590 if (IS_ERR(panel->supply)) 591 return PTR_ERR(panel->supply); 592 593 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 594 GPIOD_OUT_LOW); 595 if (IS_ERR(panel->enable_gpio)) 596 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 597 "failed to request GPIO\n"); 598 599 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 600 if (err) { 601 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 602 return err; 603 } 604 605 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 606 if (ddc) { 607 panel->ddc = of_find_i2c_adapter_by_node(ddc); 608 of_node_put(ddc); 609 610 if (!panel->ddc) 611 return -EPROBE_DEFER; 612 } 613 614 if (desc == &panel_dpi) { 615 /* Handle the generic panel-dpi binding */ 616 err = panel_dpi_probe(dev, panel); 617 if (err) 618 goto free_ddc; 619 desc = panel->desc; 620 } else { 621 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 622 panel_simple_parse_panel_timing_node(dev, panel, &dt); 623 } 624 625 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 626 /* Optional data-mapping property for overriding bus format */ 627 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 628 if (err) 629 goto free_ddc; 630 } 631 632 connector_type = desc->connector_type; 633 /* Catch common mistakes for panels. */ 634 switch (connector_type) { 635 case 0: 636 dev_warn(dev, "Specify missing connector_type\n"); 637 connector_type = DRM_MODE_CONNECTOR_DPI; 638 break; 639 case DRM_MODE_CONNECTOR_LVDS: 640 WARN_ON(desc->bus_flags & 641 ~(DRM_BUS_FLAG_DE_LOW | 642 DRM_BUS_FLAG_DE_HIGH | 643 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 644 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 645 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 646 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 647 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 648 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 649 desc->bpc != 6); 650 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 651 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 652 desc->bpc != 8); 653 break; 654 case DRM_MODE_CONNECTOR_eDP: 655 dev_warn(dev, "eDP panels moved to panel-edp\n"); 656 err = -EINVAL; 657 goto free_ddc; 658 case DRM_MODE_CONNECTOR_DSI: 659 if (desc->bpc != 6 && desc->bpc != 8) 660 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 661 break; 662 case DRM_MODE_CONNECTOR_DPI: 663 bus_flags = DRM_BUS_FLAG_DE_LOW | 664 DRM_BUS_FLAG_DE_HIGH | 665 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 666 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 667 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 668 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 669 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 670 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 671 if (desc->bus_flags & ~bus_flags) 672 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 673 if (!(desc->bus_flags & bus_flags)) 674 dev_warn(dev, "Specify missing bus_flags\n"); 675 if (desc->bus_format == 0) 676 dev_warn(dev, "Specify missing bus_format\n"); 677 if (desc->bpc != 6 && desc->bpc != 8) 678 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 679 break; 680 default: 681 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 682 connector_type = DRM_MODE_CONNECTOR_DPI; 683 break; 684 } 685 686 dev_set_drvdata(dev, panel); 687 688 /* 689 * We use runtime PM for prepare / unprepare since those power the panel 690 * on and off and those can be very slow operations. This is important 691 * to optimize powering the panel on briefly to read the EDID before 692 * fully enabling the panel. 693 */ 694 pm_runtime_enable(dev); 695 pm_runtime_set_autosuspend_delay(dev, 1000); 696 pm_runtime_use_autosuspend(dev); 697 698 err = drm_panel_of_backlight(&panel->base); 699 if (err) { 700 dev_err_probe(dev, err, "Could not find backlight\n"); 701 goto disable_pm_runtime; 702 } 703 704 drm_panel_add(&panel->base); 705 706 return 0; 707 708 disable_pm_runtime: 709 pm_runtime_dont_use_autosuspend(dev); 710 pm_runtime_disable(dev); 711 free_ddc: 712 if (panel->ddc) 713 put_device(&panel->ddc->dev); 714 715 return err; 716 } 717 718 static void panel_simple_shutdown(struct device *dev) 719 { 720 struct panel_simple *panel = dev_get_drvdata(dev); 721 722 /* 723 * NOTE: the following two calls don't really belong here. It is the 724 * responsibility of a correctly written DRM modeset driver to call 725 * drm_atomic_helper_shutdown() at shutdown time and that should 726 * cause the panel to be disabled / unprepared if needed. For now, 727 * however, we'll keep these calls due to the sheer number of 728 * different DRM modeset drivers used with panel-simple. Once we've 729 * confirmed that all DRM modeset drivers using this panel properly 730 * call drm_atomic_helper_shutdown() we can simply delete the two 731 * calls below. 732 * 733 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 734 * PANEL DRIVERS. 735 * 736 * FIXME: If we're still haven't figured out if all DRM modeset 737 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 738 * managed to make sure that DRM modeset drivers get their shutdown() 739 * callback before the panel's shutdown() callback (perhaps using 740 * device link), we could add a WARN_ON here to help move forward. 741 */ 742 if (panel->base.enabled) 743 drm_panel_disable(&panel->base); 744 if (panel->base.prepared) 745 drm_panel_unprepare(&panel->base); 746 } 747 748 static void panel_simple_remove(struct device *dev) 749 { 750 struct panel_simple *panel = dev_get_drvdata(dev); 751 752 drm_panel_remove(&panel->base); 753 panel_simple_shutdown(dev); 754 755 pm_runtime_dont_use_autosuspend(dev); 756 pm_runtime_disable(dev); 757 if (panel->ddc) 758 put_device(&panel->ddc->dev); 759 } 760 761 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 762 .clock = 71100, 763 .hdisplay = 1280, 764 .hsync_start = 1280 + 40, 765 .hsync_end = 1280 + 40 + 80, 766 .htotal = 1280 + 40 + 80 + 40, 767 .vdisplay = 800, 768 .vsync_start = 800 + 3, 769 .vsync_end = 800 + 3 + 10, 770 .vtotal = 800 + 3 + 10 + 10, 771 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 772 }; 773 774 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 775 .modes = &ire_am_1280800n3tzqw_t00h_mode, 776 .num_modes = 1, 777 .bpc = 8, 778 .size = { 779 .width = 217, 780 .height = 136, 781 }, 782 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 783 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 784 .connector_type = DRM_MODE_CONNECTOR_LVDS, 785 }; 786 787 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 788 .clock = 9000, 789 .hdisplay = 480, 790 .hsync_start = 480 + 2, 791 .hsync_end = 480 + 2 + 41, 792 .htotal = 480 + 2 + 41 + 2, 793 .vdisplay = 272, 794 .vsync_start = 272 + 2, 795 .vsync_end = 272 + 2 + 10, 796 .vtotal = 272 + 2 + 10 + 2, 797 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 798 }; 799 800 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 801 .modes = &ire_am_480272h3tmqw_t01h_mode, 802 .num_modes = 1, 803 .bpc = 8, 804 .size = { 805 .width = 99, 806 .height = 58, 807 }, 808 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 809 }; 810 811 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 812 .clock = 33333, 813 .hdisplay = 800, 814 .hsync_start = 800 + 0, 815 .hsync_end = 800 + 0 + 255, 816 .htotal = 800 + 0 + 255 + 0, 817 .vdisplay = 480, 818 .vsync_start = 480 + 2, 819 .vsync_end = 480 + 2 + 45, 820 .vtotal = 480 + 2 + 45 + 0, 821 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 822 }; 823 824 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 825 .pixelclock = { 29930000, 33260000, 36590000 }, 826 .hactive = { 800, 800, 800 }, 827 .hfront_porch = { 1, 40, 168 }, 828 .hback_porch = { 88, 88, 88 }, 829 .hsync_len = { 1, 128, 128 }, 830 .vactive = { 480, 480, 480 }, 831 .vfront_porch = { 1, 35, 37 }, 832 .vback_porch = { 8, 8, 8 }, 833 .vsync_len = { 1, 2, 2 }, 834 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 835 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 836 DISPLAY_FLAGS_SYNC_POSEDGE, 837 }; 838 839 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 840 .timings = &ire_am_800480l1tmqw_t00h_timing, 841 .num_timings = 1, 842 .bpc = 8, 843 .size = { 844 .width = 111, 845 .height = 67, 846 }, 847 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 848 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 849 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 850 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 851 .connector_type = DRM_MODE_CONNECTOR_DPI, 852 }; 853 854 static const struct panel_desc ampire_am800480r3tmqwa1h = { 855 .modes = &ire_am800480r3tmqwa1h_mode, 856 .num_modes = 1, 857 .bpc = 6, 858 .size = { 859 .width = 152, 860 .height = 91, 861 }, 862 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 863 }; 864 865 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 866 .pixelclock = { 34500000, 39600000, 50400000 }, 867 .hactive = { 800, 800, 800 }, 868 .hfront_porch = { 12, 112, 312 }, 869 .hback_porch = { 87, 87, 48 }, 870 .hsync_len = { 1, 1, 40 }, 871 .vactive = { 600, 600, 600 }, 872 .vfront_porch = { 1, 21, 61 }, 873 .vback_porch = { 38, 38, 19 }, 874 .vsync_len = { 1, 1, 20 }, 875 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 876 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 877 DISPLAY_FLAGS_SYNC_POSEDGE, 878 }; 879 880 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 881 .timings = &ire_am800600p5tmqw_tb8h_timing, 882 .num_timings = 1, 883 .bpc = 6, 884 .size = { 885 .width = 162, 886 .height = 122, 887 }, 888 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 889 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 890 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 891 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 892 .connector_type = DRM_MODE_CONNECTOR_DPI, 893 }; 894 895 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 896 .pixelclock = { 26400000, 33300000, 46800000 }, 897 .hactive = { 800, 800, 800 }, 898 .hfront_porch = { 16, 210, 354 }, 899 .hback_porch = { 45, 36, 6 }, 900 .hsync_len = { 1, 10, 40 }, 901 .vactive = { 480, 480, 480 }, 902 .vfront_porch = { 7, 22, 147 }, 903 .vback_porch = { 22, 13, 3 }, 904 .vsync_len = { 1, 10, 20 }, 905 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 906 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 907 }; 908 909 static const struct panel_desc armadeus_st0700_adapt = { 910 .timings = &santek_st0700i5y_rbslw_f_timing, 911 .num_timings = 1, 912 .bpc = 6, 913 .size = { 914 .width = 154, 915 .height = 86, 916 }, 917 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 918 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 919 }; 920 921 static const struct drm_display_mode auo_b101aw03_mode = { 922 .clock = 51450, 923 .hdisplay = 1024, 924 .hsync_start = 1024 + 156, 925 .hsync_end = 1024 + 156 + 8, 926 .htotal = 1024 + 156 + 8 + 156, 927 .vdisplay = 600, 928 .vsync_start = 600 + 16, 929 .vsync_end = 600 + 16 + 6, 930 .vtotal = 600 + 16 + 6 + 16, 931 }; 932 933 static const struct panel_desc auo_b101aw03 = { 934 .modes = &auo_b101aw03_mode, 935 .num_modes = 1, 936 .bpc = 6, 937 .size = { 938 .width = 223, 939 .height = 125, 940 }, 941 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 942 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 943 .connector_type = DRM_MODE_CONNECTOR_LVDS, 944 }; 945 946 static const struct drm_display_mode auo_b101xtn01_mode = { 947 .clock = 72000, 948 .hdisplay = 1366, 949 .hsync_start = 1366 + 20, 950 .hsync_end = 1366 + 20 + 70, 951 .htotal = 1366 + 20 + 70, 952 .vdisplay = 768, 953 .vsync_start = 768 + 14, 954 .vsync_end = 768 + 14 + 42, 955 .vtotal = 768 + 14 + 42, 956 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 957 }; 958 959 static const struct panel_desc auo_b101xtn01 = { 960 .modes = &auo_b101xtn01_mode, 961 .num_modes = 1, 962 .bpc = 6, 963 .size = { 964 .width = 223, 965 .height = 125, 966 }, 967 }; 968 969 static const struct drm_display_mode auo_b116xw03_mode = { 970 .clock = 70589, 971 .hdisplay = 1366, 972 .hsync_start = 1366 + 40, 973 .hsync_end = 1366 + 40 + 40, 974 .htotal = 1366 + 40 + 40 + 32, 975 .vdisplay = 768, 976 .vsync_start = 768 + 10, 977 .vsync_end = 768 + 10 + 12, 978 .vtotal = 768 + 10 + 12 + 6, 979 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 980 }; 981 982 static const struct panel_desc auo_b116xw03 = { 983 .modes = &auo_b116xw03_mode, 984 .num_modes = 1, 985 .bpc = 6, 986 .size = { 987 .width = 256, 988 .height = 144, 989 }, 990 .delay = { 991 .prepare = 1, 992 .enable = 200, 993 .disable = 200, 994 .unprepare = 500, 995 }, 996 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 997 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 998 .connector_type = DRM_MODE_CONNECTOR_LVDS, 999 }; 1000 1001 static const struct display_timing auo_g070vvn01_timings = { 1002 .pixelclock = { 33300000, 34209000, 45000000 }, 1003 .hactive = { 800, 800, 800 }, 1004 .hfront_porch = { 20, 40, 200 }, 1005 .hback_porch = { 87, 40, 1 }, 1006 .hsync_len = { 1, 48, 87 }, 1007 .vactive = { 480, 480, 480 }, 1008 .vfront_porch = { 5, 13, 200 }, 1009 .vback_porch = { 31, 31, 29 }, 1010 .vsync_len = { 1, 1, 3 }, 1011 }; 1012 1013 static const struct panel_desc auo_g070vvn01 = { 1014 .timings = &auo_g070vvn01_timings, 1015 .num_timings = 1, 1016 .bpc = 8, 1017 .size = { 1018 .width = 152, 1019 .height = 91, 1020 }, 1021 .delay = { 1022 .prepare = 200, 1023 .enable = 50, 1024 .disable = 50, 1025 .unprepare = 1000, 1026 }, 1027 }; 1028 1029 static const struct display_timing auo_g101evn010_timing = { 1030 .pixelclock = { 64000000, 68930000, 85000000 }, 1031 .hactive = { 1280, 1280, 1280 }, 1032 .hfront_porch = { 8, 64, 256 }, 1033 .hback_porch = { 8, 64, 256 }, 1034 .hsync_len = { 40, 168, 767 }, 1035 .vactive = { 800, 800, 800 }, 1036 .vfront_porch = { 4, 8, 100 }, 1037 .vback_porch = { 4, 8, 100 }, 1038 .vsync_len = { 8, 16, 223 }, 1039 }; 1040 1041 static const struct panel_desc auo_g101evn010 = { 1042 .timings = &auo_g101evn010_timing, 1043 .num_timings = 1, 1044 .bpc = 6, 1045 .size = { 1046 .width = 216, 1047 .height = 135, 1048 }, 1049 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1050 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1051 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1052 }; 1053 1054 static const struct drm_display_mode auo_g104sn02_mode = { 1055 .clock = 40000, 1056 .hdisplay = 800, 1057 .hsync_start = 800 + 40, 1058 .hsync_end = 800 + 40 + 216, 1059 .htotal = 800 + 40 + 216 + 128, 1060 .vdisplay = 600, 1061 .vsync_start = 600 + 10, 1062 .vsync_end = 600 + 10 + 35, 1063 .vtotal = 600 + 10 + 35 + 2, 1064 }; 1065 1066 static const struct panel_desc auo_g104sn02 = { 1067 .modes = &auo_g104sn02_mode, 1068 .num_modes = 1, 1069 .bpc = 8, 1070 .size = { 1071 .width = 211, 1072 .height = 158, 1073 }, 1074 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1075 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1076 }; 1077 1078 static const struct drm_display_mode auo_g104stn01_mode = { 1079 .clock = 40000, 1080 .hdisplay = 800, 1081 .hsync_start = 800 + 40, 1082 .hsync_end = 800 + 40 + 88, 1083 .htotal = 800 + 40 + 88 + 128, 1084 .vdisplay = 600, 1085 .vsync_start = 600 + 1, 1086 .vsync_end = 600 + 1 + 23, 1087 .vtotal = 600 + 1 + 23 + 4, 1088 }; 1089 1090 static const struct panel_desc auo_g104stn01 = { 1091 .modes = &auo_g104stn01_mode, 1092 .num_modes = 1, 1093 .bpc = 8, 1094 .size = { 1095 .width = 211, 1096 .height = 158, 1097 }, 1098 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1099 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1100 }; 1101 1102 static const struct display_timing auo_g121ean01_timing = { 1103 .pixelclock = { 60000000, 74400000, 90000000 }, 1104 .hactive = { 1280, 1280, 1280 }, 1105 .hfront_porch = { 20, 50, 100 }, 1106 .hback_porch = { 20, 50, 100 }, 1107 .hsync_len = { 30, 100, 200 }, 1108 .vactive = { 800, 800, 800 }, 1109 .vfront_porch = { 2, 10, 25 }, 1110 .vback_porch = { 2, 10, 25 }, 1111 .vsync_len = { 4, 18, 50 }, 1112 }; 1113 1114 static const struct panel_desc auo_g121ean01 = { 1115 .timings = &auo_g121ean01_timing, 1116 .num_timings = 1, 1117 .bpc = 8, 1118 .size = { 1119 .width = 261, 1120 .height = 163, 1121 }, 1122 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1123 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1124 }; 1125 1126 static const struct display_timing auo_g133han01_timings = { 1127 .pixelclock = { 134000000, 141200000, 149000000 }, 1128 .hactive = { 1920, 1920, 1920 }, 1129 .hfront_porch = { 39, 58, 77 }, 1130 .hback_porch = { 59, 88, 117 }, 1131 .hsync_len = { 28, 42, 56 }, 1132 .vactive = { 1080, 1080, 1080 }, 1133 .vfront_porch = { 3, 8, 11 }, 1134 .vback_porch = { 5, 14, 19 }, 1135 .vsync_len = { 4, 14, 19 }, 1136 }; 1137 1138 static const struct panel_desc auo_g133han01 = { 1139 .timings = &auo_g133han01_timings, 1140 .num_timings = 1, 1141 .bpc = 8, 1142 .size = { 1143 .width = 293, 1144 .height = 165, 1145 }, 1146 .delay = { 1147 .prepare = 200, 1148 .enable = 50, 1149 .disable = 50, 1150 .unprepare = 1000, 1151 }, 1152 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1153 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1154 }; 1155 1156 static const struct display_timing auo_g156han04_timings = { 1157 .pixelclock = { 137000000, 141000000, 146000000 }, 1158 .hactive = { 1920, 1920, 1920 }, 1159 .hfront_porch = { 60, 60, 60 }, 1160 .hback_porch = { 90, 92, 111 }, 1161 .hsync_len = { 32, 32, 32 }, 1162 .vactive = { 1080, 1080, 1080 }, 1163 .vfront_porch = { 12, 12, 12 }, 1164 .vback_porch = { 24, 36, 56 }, 1165 .vsync_len = { 8, 8, 8 }, 1166 }; 1167 1168 static const struct panel_desc auo_g156han04 = { 1169 .timings = &auo_g156han04_timings, 1170 .num_timings = 1, 1171 .bpc = 8, 1172 .size = { 1173 .width = 344, 1174 .height = 194, 1175 }, 1176 .delay = { 1177 .prepare = 50, /* T2 */ 1178 .enable = 200, /* T3 */ 1179 .disable = 110, /* T10 */ 1180 .unprepare = 1000, /* T13 */ 1181 }, 1182 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1183 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1184 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1185 }; 1186 1187 static const struct drm_display_mode auo_g156xtn01_mode = { 1188 .clock = 76000, 1189 .hdisplay = 1366, 1190 .hsync_start = 1366 + 33, 1191 .hsync_end = 1366 + 33 + 67, 1192 .htotal = 1560, 1193 .vdisplay = 768, 1194 .vsync_start = 768 + 4, 1195 .vsync_end = 768 + 4 + 4, 1196 .vtotal = 806, 1197 }; 1198 1199 static const struct panel_desc auo_g156xtn01 = { 1200 .modes = &auo_g156xtn01_mode, 1201 .num_modes = 1, 1202 .bpc = 8, 1203 .size = { 1204 .width = 344, 1205 .height = 194, 1206 }, 1207 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1208 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1209 }; 1210 1211 static const struct display_timing auo_g185han01_timings = { 1212 .pixelclock = { 120000000, 144000000, 175000000 }, 1213 .hactive = { 1920, 1920, 1920 }, 1214 .hfront_porch = { 36, 120, 148 }, 1215 .hback_porch = { 24, 88, 108 }, 1216 .hsync_len = { 20, 48, 64 }, 1217 .vactive = { 1080, 1080, 1080 }, 1218 .vfront_porch = { 6, 10, 40 }, 1219 .vback_porch = { 2, 5, 20 }, 1220 .vsync_len = { 2, 5, 20 }, 1221 }; 1222 1223 static const struct panel_desc auo_g185han01 = { 1224 .timings = &auo_g185han01_timings, 1225 .num_timings = 1, 1226 .bpc = 8, 1227 .size = { 1228 .width = 409, 1229 .height = 230, 1230 }, 1231 .delay = { 1232 .prepare = 50, 1233 .enable = 200, 1234 .disable = 110, 1235 .unprepare = 1000, 1236 }, 1237 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1238 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1239 }; 1240 1241 static const struct display_timing auo_g190ean01_timings = { 1242 .pixelclock = { 90000000, 108000000, 135000000 }, 1243 .hactive = { 1280, 1280, 1280 }, 1244 .hfront_porch = { 126, 184, 1266 }, 1245 .hback_porch = { 84, 122, 844 }, 1246 .hsync_len = { 70, 102, 704 }, 1247 .vactive = { 1024, 1024, 1024 }, 1248 .vfront_porch = { 4, 26, 76 }, 1249 .vback_porch = { 2, 8, 25 }, 1250 .vsync_len = { 2, 8, 25 }, 1251 }; 1252 1253 static const struct panel_desc auo_g190ean01 = { 1254 .timings = &auo_g190ean01_timings, 1255 .num_timings = 1, 1256 .bpc = 8, 1257 .size = { 1258 .width = 376, 1259 .height = 301, 1260 }, 1261 .delay = { 1262 .prepare = 50, 1263 .enable = 200, 1264 .disable = 110, 1265 .unprepare = 1000, 1266 }, 1267 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1268 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1269 }; 1270 1271 static const struct display_timing auo_p320hvn03_timings = { 1272 .pixelclock = { 106000000, 148500000, 164000000 }, 1273 .hactive = { 1920, 1920, 1920 }, 1274 .hfront_porch = { 25, 50, 130 }, 1275 .hback_porch = { 25, 50, 130 }, 1276 .hsync_len = { 20, 40, 105 }, 1277 .vactive = { 1080, 1080, 1080 }, 1278 .vfront_porch = { 8, 17, 150 }, 1279 .vback_porch = { 8, 17, 150 }, 1280 .vsync_len = { 4, 11, 100 }, 1281 }; 1282 1283 static const struct panel_desc auo_p320hvn03 = { 1284 .timings = &auo_p320hvn03_timings, 1285 .num_timings = 1, 1286 .bpc = 8, 1287 .size = { 1288 .width = 698, 1289 .height = 393, 1290 }, 1291 .delay = { 1292 .prepare = 1, 1293 .enable = 450, 1294 .unprepare = 500, 1295 }, 1296 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1297 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1298 }; 1299 1300 static const struct drm_display_mode auo_t215hvn01_mode = { 1301 .clock = 148800, 1302 .hdisplay = 1920, 1303 .hsync_start = 1920 + 88, 1304 .hsync_end = 1920 + 88 + 44, 1305 .htotal = 1920 + 88 + 44 + 148, 1306 .vdisplay = 1080, 1307 .vsync_start = 1080 + 4, 1308 .vsync_end = 1080 + 4 + 5, 1309 .vtotal = 1080 + 4 + 5 + 36, 1310 }; 1311 1312 static const struct panel_desc auo_t215hvn01 = { 1313 .modes = &auo_t215hvn01_mode, 1314 .num_modes = 1, 1315 .bpc = 8, 1316 .size = { 1317 .width = 430, 1318 .height = 270, 1319 }, 1320 .delay = { 1321 .disable = 5, 1322 .unprepare = 1000, 1323 }, 1324 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1325 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1326 }; 1327 1328 static const struct drm_display_mode avic_tm070ddh03_mode = { 1329 .clock = 51200, 1330 .hdisplay = 1024, 1331 .hsync_start = 1024 + 160, 1332 .hsync_end = 1024 + 160 + 4, 1333 .htotal = 1024 + 160 + 4 + 156, 1334 .vdisplay = 600, 1335 .vsync_start = 600 + 17, 1336 .vsync_end = 600 + 17 + 1, 1337 .vtotal = 600 + 17 + 1 + 17, 1338 }; 1339 1340 static const struct panel_desc avic_tm070ddh03 = { 1341 .modes = &avic_tm070ddh03_mode, 1342 .num_modes = 1, 1343 .bpc = 8, 1344 .size = { 1345 .width = 154, 1346 .height = 90, 1347 }, 1348 .delay = { 1349 .prepare = 20, 1350 .enable = 200, 1351 .disable = 200, 1352 }, 1353 }; 1354 1355 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1356 .clock = 30000, 1357 .hdisplay = 800, 1358 .hsync_start = 800 + 40, 1359 .hsync_end = 800 + 40 + 48, 1360 .htotal = 800 + 40 + 48 + 40, 1361 .vdisplay = 480, 1362 .vsync_start = 480 + 13, 1363 .vsync_end = 480 + 13 + 3, 1364 .vtotal = 480 + 13 + 3 + 29, 1365 }; 1366 1367 static const struct panel_desc bananapi_s070wv20_ct16 = { 1368 .modes = &bananapi_s070wv20_ct16_mode, 1369 .num_modes = 1, 1370 .bpc = 6, 1371 .size = { 1372 .width = 154, 1373 .height = 86, 1374 }, 1375 }; 1376 1377 static const struct display_timing boe_av101hdt_a10_timing = { 1378 .pixelclock = { 74210000, 75330000, 76780000, }, 1379 .hactive = { 1280, 1280, 1280, }, 1380 .hfront_porch = { 10, 42, 33, }, 1381 .hback_porch = { 10, 18, 33, }, 1382 .hsync_len = { 30, 10, 30, }, 1383 .vactive = { 720, 720, 720, }, 1384 .vfront_porch = { 200, 183, 200, }, 1385 .vback_porch = { 8, 8, 8, }, 1386 .vsync_len = { 2, 19, 2, }, 1387 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1388 }; 1389 1390 static const struct panel_desc boe_av101hdt_a10 = { 1391 .timings = &boe_av101hdt_a10_timing, 1392 .num_timings = 1, 1393 .bpc = 8, 1394 .size = { 1395 .width = 224, 1396 .height = 126, 1397 }, 1398 .delay = { 1399 .enable = 50, 1400 .disable = 50, 1401 }, 1402 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1403 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1404 }; 1405 1406 static const struct display_timing boe_av123z7m_n17_timing = { 1407 .pixelclock = { 86600000, 88000000, 90800000, }, 1408 .hactive = { 1920, 1920, 1920, }, 1409 .hfront_porch = { 10, 10, 10, }, 1410 .hback_porch = { 10, 10, 10, }, 1411 .hsync_len = { 9, 12, 25, }, 1412 .vactive = { 720, 720, 720, }, 1413 .vfront_porch = { 7, 10, 13, }, 1414 .vback_porch = { 7, 10, 13, }, 1415 .vsync_len = { 7, 11, 14, }, 1416 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1417 }; 1418 1419 static const struct panel_desc boe_av123z7m_n17 = { 1420 .timings = &boe_av123z7m_n17_timing, 1421 .bpc = 8, 1422 .num_timings = 1, 1423 .size = { 1424 .width = 292, 1425 .height = 110, 1426 }, 1427 .delay = { 1428 .prepare = 50, 1429 .disable = 50, 1430 }, 1431 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1432 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1433 }; 1434 1435 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1436 .clock = 78945, 1437 .hdisplay = 1280, 1438 .hsync_start = 1280 + 0, 1439 .hsync_end = 1280 + 0 + 2, 1440 .htotal = 1280 + 62 + 0 + 2, 1441 .vdisplay = 800, 1442 .vsync_start = 800 + 8, 1443 .vsync_end = 800 + 8 + 2, 1444 .vtotal = 800 + 6 + 8 + 2, 1445 }; 1446 1447 static const struct panel_desc boe_bp082wx1_100 = { 1448 .modes = &boe_bp101wx1_100_mode, 1449 .num_modes = 1, 1450 .bpc = 8, 1451 .size = { 1452 .width = 177, 1453 .height = 110, 1454 }, 1455 .delay = { 1456 .enable = 50, 1457 .disable = 50, 1458 }, 1459 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1460 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1461 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1462 }; 1463 1464 static const struct panel_desc boe_bp101wx1_100 = { 1465 .modes = &boe_bp101wx1_100_mode, 1466 .num_modes = 1, 1467 .bpc = 8, 1468 .size = { 1469 .width = 217, 1470 .height = 136, 1471 }, 1472 .delay = { 1473 .enable = 50, 1474 .disable = 50, 1475 }, 1476 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1477 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1478 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1479 }; 1480 1481 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1482 .pixelclock = { 69922000, 71000000, 72293000 }, 1483 .hactive = { 1280, 1280, 1280 }, 1484 .hfront_porch = { 48, 48, 48 }, 1485 .hback_porch = { 80, 80, 80 }, 1486 .hsync_len = { 32, 32, 32 }, 1487 .vactive = { 800, 800, 800 }, 1488 .vfront_porch = { 3, 3, 3 }, 1489 .vback_porch = { 14, 14, 14 }, 1490 .vsync_len = { 6, 6, 6 }, 1491 }; 1492 1493 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1494 .timings = &boe_ev121wxm_n10_1850_timing, 1495 .num_timings = 1, 1496 .bpc = 8, 1497 .size = { 1498 .width = 261, 1499 .height = 163, 1500 }, 1501 .delay = { 1502 .prepare = 9, 1503 .enable = 300, 1504 .unprepare = 300, 1505 .disable = 560, 1506 }, 1507 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1508 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1509 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1510 }; 1511 1512 static const struct drm_display_mode boe_hv070wsa_mode = { 1513 .clock = 42105, 1514 .hdisplay = 1024, 1515 .hsync_start = 1024 + 30, 1516 .hsync_end = 1024 + 30 + 30, 1517 .htotal = 1024 + 30 + 30 + 30, 1518 .vdisplay = 600, 1519 .vsync_start = 600 + 10, 1520 .vsync_end = 600 + 10 + 10, 1521 .vtotal = 600 + 10 + 10 + 10, 1522 }; 1523 1524 static const struct panel_desc boe_hv070wsa = { 1525 .modes = &boe_hv070wsa_mode, 1526 .num_modes = 1, 1527 .bpc = 8, 1528 .size = { 1529 .width = 154, 1530 .height = 90, 1531 }, 1532 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1533 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1534 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1535 }; 1536 1537 static const struct display_timing cct_cmt430b19n00_timing = { 1538 .pixelclock = { 8000000, 9000000, 12000000 }, 1539 .hactive = { 480, 480, 480 }, 1540 .hfront_porch = { 2, 8, 75 }, 1541 .hback_porch = { 3, 43, 43 }, 1542 .hsync_len = { 2, 4, 75 }, 1543 .vactive = { 272, 272, 272 }, 1544 .vfront_porch = { 2, 8, 37 }, 1545 .vback_porch = { 2, 12, 12 }, 1546 .vsync_len = { 2, 4, 37 }, 1547 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1548 }; 1549 1550 static const struct panel_desc cct_cmt430b19n00 = { 1551 .timings = &cct_cmt430b19n00_timing, 1552 .num_timings = 1, 1553 .bpc = 8, 1554 .size = { 1555 .width = 95, 1556 .height = 53, 1557 }, 1558 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1559 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1560 .connector_type = DRM_MODE_CONNECTOR_DPI, 1561 }; 1562 1563 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1564 .clock = 9000, 1565 .hdisplay = 480, 1566 .hsync_start = 480 + 5, 1567 .hsync_end = 480 + 5 + 5, 1568 .htotal = 480 + 5 + 5 + 40, 1569 .vdisplay = 272, 1570 .vsync_start = 272 + 8, 1571 .vsync_end = 272 + 8 + 8, 1572 .vtotal = 272 + 8 + 8 + 8, 1573 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1574 }; 1575 1576 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1577 .modes = &cdtech_s043wq26h_ct7_mode, 1578 .num_modes = 1, 1579 .bpc = 8, 1580 .size = { 1581 .width = 95, 1582 .height = 54, 1583 }, 1584 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1585 }; 1586 1587 /* S070PWS19HP-FC21 2017/04/22 */ 1588 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1589 .clock = 51200, 1590 .hdisplay = 1024, 1591 .hsync_start = 1024 + 160, 1592 .hsync_end = 1024 + 160 + 20, 1593 .htotal = 1024 + 160 + 20 + 140, 1594 .vdisplay = 600, 1595 .vsync_start = 600 + 12, 1596 .vsync_end = 600 + 12 + 3, 1597 .vtotal = 600 + 12 + 3 + 20, 1598 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1599 }; 1600 1601 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1602 .modes = &cdtech_s070pws19hp_fc21_mode, 1603 .num_modes = 1, 1604 .bpc = 6, 1605 .size = { 1606 .width = 154, 1607 .height = 86, 1608 }, 1609 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1610 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1611 .connector_type = DRM_MODE_CONNECTOR_DPI, 1612 }; 1613 1614 /* S070SWV29HG-DC44 2017/09/21 */ 1615 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1616 .clock = 33300, 1617 .hdisplay = 800, 1618 .hsync_start = 800 + 210, 1619 .hsync_end = 800 + 210 + 2, 1620 .htotal = 800 + 210 + 2 + 44, 1621 .vdisplay = 480, 1622 .vsync_start = 480 + 22, 1623 .vsync_end = 480 + 22 + 2, 1624 .vtotal = 480 + 22 + 2 + 21, 1625 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1626 }; 1627 1628 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1629 .modes = &cdtech_s070swv29hg_dc44_mode, 1630 .num_modes = 1, 1631 .bpc = 6, 1632 .size = { 1633 .width = 154, 1634 .height = 86, 1635 }, 1636 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1637 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1638 .connector_type = DRM_MODE_CONNECTOR_DPI, 1639 }; 1640 1641 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1642 .clock = 35000, 1643 .hdisplay = 800, 1644 .hsync_start = 800 + 40, 1645 .hsync_end = 800 + 40 + 40, 1646 .htotal = 800 + 40 + 40 + 48, 1647 .vdisplay = 480, 1648 .vsync_start = 480 + 29, 1649 .vsync_end = 480 + 29 + 13, 1650 .vtotal = 480 + 29 + 13 + 3, 1651 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1652 }; 1653 1654 static const struct panel_desc cdtech_s070wv95_ct16 = { 1655 .modes = &cdtech_s070wv95_ct16_mode, 1656 .num_modes = 1, 1657 .bpc = 8, 1658 .size = { 1659 .width = 154, 1660 .height = 85, 1661 }, 1662 }; 1663 1664 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1665 .pixelclock = { 68900000, 71100000, 73400000 }, 1666 .hactive = { 1280, 1280, 1280 }, 1667 .hfront_porch = { 65, 80, 95 }, 1668 .hback_porch = { 64, 79, 94 }, 1669 .hsync_len = { 1, 1, 1 }, 1670 .vactive = { 800, 800, 800 }, 1671 .vfront_porch = { 7, 11, 14 }, 1672 .vback_porch = { 7, 11, 14 }, 1673 .vsync_len = { 1, 1, 1 }, 1674 .flags = DISPLAY_FLAGS_DE_HIGH, 1675 }; 1676 1677 static const struct panel_desc chefree_ch101olhlwh_002 = { 1678 .timings = &chefree_ch101olhlwh_002_timing, 1679 .num_timings = 1, 1680 .bpc = 8, 1681 .size = { 1682 .width = 217, 1683 .height = 135, 1684 }, 1685 .delay = { 1686 .enable = 200, 1687 .disable = 200, 1688 }, 1689 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1690 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1691 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1692 }; 1693 1694 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1695 .clock = 66770, 1696 .hdisplay = 800, 1697 .hsync_start = 800 + 49, 1698 .hsync_end = 800 + 49 + 33, 1699 .htotal = 800 + 49 + 33 + 17, 1700 .vdisplay = 1280, 1701 .vsync_start = 1280 + 1, 1702 .vsync_end = 1280 + 1 + 7, 1703 .vtotal = 1280 + 1 + 7 + 15, 1704 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1705 }; 1706 1707 static const struct panel_desc chunghwa_claa070wp03xg = { 1708 .modes = &chunghwa_claa070wp03xg_mode, 1709 .num_modes = 1, 1710 .bpc = 6, 1711 .size = { 1712 .width = 94, 1713 .height = 150, 1714 }, 1715 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1716 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1717 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1718 }; 1719 1720 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1721 .clock = 72070, 1722 .hdisplay = 1366, 1723 .hsync_start = 1366 + 58, 1724 .hsync_end = 1366 + 58 + 58, 1725 .htotal = 1366 + 58 + 58 + 58, 1726 .vdisplay = 768, 1727 .vsync_start = 768 + 4, 1728 .vsync_end = 768 + 4 + 4, 1729 .vtotal = 768 + 4 + 4 + 4, 1730 }; 1731 1732 static const struct panel_desc chunghwa_claa101wa01a = { 1733 .modes = &chunghwa_claa101wa01a_mode, 1734 .num_modes = 1, 1735 .bpc = 6, 1736 .size = { 1737 .width = 220, 1738 .height = 120, 1739 }, 1740 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1741 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1742 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1743 }; 1744 1745 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1746 .clock = 69300, 1747 .hdisplay = 1366, 1748 .hsync_start = 1366 + 48, 1749 .hsync_end = 1366 + 48 + 32, 1750 .htotal = 1366 + 48 + 32 + 20, 1751 .vdisplay = 768, 1752 .vsync_start = 768 + 16, 1753 .vsync_end = 768 + 16 + 8, 1754 .vtotal = 768 + 16 + 8 + 16, 1755 }; 1756 1757 static const struct panel_desc chunghwa_claa101wb01 = { 1758 .modes = &chunghwa_claa101wb01_mode, 1759 .num_modes = 1, 1760 .bpc = 6, 1761 .size = { 1762 .width = 223, 1763 .height = 125, 1764 }, 1765 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1766 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1767 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1768 }; 1769 1770 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1771 .pixelclock = { 5000000, 9000000, 12000000 }, 1772 .hactive = { 480, 480, 480 }, 1773 .hfront_porch = { 12, 12, 12 }, 1774 .hback_porch = { 12, 12, 12 }, 1775 .hsync_len = { 21, 21, 21 }, 1776 .vactive = { 272, 272, 272 }, 1777 .vfront_porch = { 4, 4, 4 }, 1778 .vback_porch = { 4, 4, 4 }, 1779 .vsync_len = { 8, 8, 8 }, 1780 }; 1781 1782 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1783 .timings = &dataimage_fg040346dsswbg04_timing, 1784 .num_timings = 1, 1785 .bpc = 8, 1786 .size = { 1787 .width = 95, 1788 .height = 54, 1789 }, 1790 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1791 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1792 .connector_type = DRM_MODE_CONNECTOR_DPI, 1793 }; 1794 1795 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1796 .pixelclock = { 68900000, 71110000, 73400000 }, 1797 .hactive = { 1280, 1280, 1280 }, 1798 .vactive = { 800, 800, 800 }, 1799 .hback_porch = { 100, 100, 100 }, 1800 .hfront_porch = { 100, 100, 100 }, 1801 .vback_porch = { 5, 5, 5 }, 1802 .vfront_porch = { 5, 5, 5 }, 1803 .hsync_len = { 24, 24, 24 }, 1804 .vsync_len = { 3, 3, 3 }, 1805 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1806 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1807 }; 1808 1809 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1810 .timings = &dataimage_fg1001l0dsswmg01_timing, 1811 .num_timings = 1, 1812 .bpc = 8, 1813 .size = { 1814 .width = 217, 1815 .height = 136, 1816 }, 1817 }; 1818 1819 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1820 .clock = 33260, 1821 .hdisplay = 800, 1822 .hsync_start = 800 + 40, 1823 .hsync_end = 800 + 40 + 128, 1824 .htotal = 800 + 40 + 128 + 88, 1825 .vdisplay = 480, 1826 .vsync_start = 480 + 10, 1827 .vsync_end = 480 + 10 + 2, 1828 .vtotal = 480 + 10 + 2 + 33, 1829 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1830 }; 1831 1832 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1833 .modes = &dataimage_scf0700c48ggu18_mode, 1834 .num_modes = 1, 1835 .bpc = 8, 1836 .size = { 1837 .width = 152, 1838 .height = 91, 1839 }, 1840 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1841 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1842 }; 1843 1844 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1845 .pixelclock = { 45000000, 51200000, 57000000 }, 1846 .hactive = { 1024, 1024, 1024 }, 1847 .hfront_porch = { 100, 106, 113 }, 1848 .hback_porch = { 100, 106, 113 }, 1849 .hsync_len = { 100, 108, 114 }, 1850 .vactive = { 600, 600, 600 }, 1851 .vfront_porch = { 8, 11, 15 }, 1852 .vback_porch = { 8, 11, 15 }, 1853 .vsync_len = { 9, 13, 15 }, 1854 .flags = DISPLAY_FLAGS_DE_HIGH, 1855 }; 1856 1857 static const struct panel_desc dlc_dlc0700yzg_1 = { 1858 .timings = &dlc_dlc0700yzg_1_timing, 1859 .num_timings = 1, 1860 .bpc = 6, 1861 .size = { 1862 .width = 154, 1863 .height = 86, 1864 }, 1865 .delay = { 1866 .prepare = 30, 1867 .enable = 200, 1868 .disable = 200, 1869 }, 1870 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1871 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1872 }; 1873 1874 static const struct display_timing dlc_dlc1010gig_timing = { 1875 .pixelclock = { 68900000, 71100000, 73400000 }, 1876 .hactive = { 1280, 1280, 1280 }, 1877 .hfront_porch = { 43, 53, 63 }, 1878 .hback_porch = { 43, 53, 63 }, 1879 .hsync_len = { 44, 54, 64 }, 1880 .vactive = { 800, 800, 800 }, 1881 .vfront_porch = { 5, 8, 11 }, 1882 .vback_porch = { 5, 8, 11 }, 1883 .vsync_len = { 5, 7, 11 }, 1884 .flags = DISPLAY_FLAGS_DE_HIGH, 1885 }; 1886 1887 static const struct panel_desc dlc_dlc1010gig = { 1888 .timings = &dlc_dlc1010gig_timing, 1889 .num_timings = 1, 1890 .bpc = 8, 1891 .size = { 1892 .width = 216, 1893 .height = 135, 1894 }, 1895 .delay = { 1896 .prepare = 60, 1897 .enable = 150, 1898 .disable = 100, 1899 .unprepare = 60, 1900 }, 1901 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1902 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1903 }; 1904 1905 static const struct drm_display_mode edt_et035012dm6_mode = { 1906 .clock = 6500, 1907 .hdisplay = 320, 1908 .hsync_start = 320 + 20, 1909 .hsync_end = 320 + 20 + 30, 1910 .htotal = 320 + 20 + 68, 1911 .vdisplay = 240, 1912 .vsync_start = 240 + 4, 1913 .vsync_end = 240 + 4 + 4, 1914 .vtotal = 240 + 4 + 4 + 14, 1915 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1916 }; 1917 1918 static const struct panel_desc edt_et035012dm6 = { 1919 .modes = &edt_et035012dm6_mode, 1920 .num_modes = 1, 1921 .bpc = 8, 1922 .size = { 1923 .width = 70, 1924 .height = 52, 1925 }, 1926 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1927 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1928 }; 1929 1930 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1931 .clock = 6520, 1932 .hdisplay = 320, 1933 .hsync_start = 320 + 20, 1934 .hsync_end = 320 + 20 + 68, 1935 .htotal = 320 + 20 + 68, 1936 .vdisplay = 240, 1937 .vsync_start = 240 + 4, 1938 .vsync_end = 240 + 4 + 18, 1939 .vtotal = 240 + 4 + 18, 1940 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1941 }; 1942 1943 static const struct panel_desc edt_etm0350g0dh6 = { 1944 .modes = &edt_etm0350g0dh6_mode, 1945 .num_modes = 1, 1946 .bpc = 6, 1947 .size = { 1948 .width = 70, 1949 .height = 53, 1950 }, 1951 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1952 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1953 .connector_type = DRM_MODE_CONNECTOR_DPI, 1954 }; 1955 1956 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1957 .clock = 10870, 1958 .hdisplay = 480, 1959 .hsync_start = 480 + 8, 1960 .hsync_end = 480 + 8 + 4, 1961 .htotal = 480 + 8 + 4 + 41, 1962 1963 /* 1964 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1965 * fb_align 1966 */ 1967 1968 .vdisplay = 288, 1969 .vsync_start = 288 + 2, 1970 .vsync_end = 288 + 2 + 4, 1971 .vtotal = 288 + 2 + 4 + 10, 1972 }; 1973 1974 static const struct panel_desc edt_etm043080dh6gp = { 1975 .modes = &edt_etm043080dh6gp_mode, 1976 .num_modes = 1, 1977 .bpc = 8, 1978 .size = { 1979 .width = 100, 1980 .height = 65, 1981 }, 1982 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1983 .connector_type = DRM_MODE_CONNECTOR_DPI, 1984 }; 1985 1986 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1987 .clock = 9000, 1988 .hdisplay = 480, 1989 .hsync_start = 480 + 2, 1990 .hsync_end = 480 + 2 + 41, 1991 .htotal = 480 + 2 + 41 + 2, 1992 .vdisplay = 272, 1993 .vsync_start = 272 + 2, 1994 .vsync_end = 272 + 2 + 10, 1995 .vtotal = 272 + 2 + 10 + 2, 1996 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1997 }; 1998 1999 static const struct panel_desc edt_etm0430g0dh6 = { 2000 .modes = &edt_etm0430g0dh6_mode, 2001 .num_modes = 1, 2002 .bpc = 6, 2003 .size = { 2004 .width = 95, 2005 .height = 54, 2006 }, 2007 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2008 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2009 .connector_type = DRM_MODE_CONNECTOR_DPI, 2010 }; 2011 2012 static const struct drm_display_mode edt_et057090dhu_mode = { 2013 .clock = 25175, 2014 .hdisplay = 640, 2015 .hsync_start = 640 + 16, 2016 .hsync_end = 640 + 16 + 30, 2017 .htotal = 640 + 16 + 30 + 114, 2018 .vdisplay = 480, 2019 .vsync_start = 480 + 10, 2020 .vsync_end = 480 + 10 + 3, 2021 .vtotal = 480 + 10 + 3 + 32, 2022 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2023 }; 2024 2025 static const struct panel_desc edt_et057090dhu = { 2026 .modes = &edt_et057090dhu_mode, 2027 .num_modes = 1, 2028 .bpc = 6, 2029 .size = { 2030 .width = 115, 2031 .height = 86, 2032 }, 2033 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2034 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2035 .connector_type = DRM_MODE_CONNECTOR_DPI, 2036 }; 2037 2038 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2039 .clock = 33260, 2040 .hdisplay = 800, 2041 .hsync_start = 800 + 40, 2042 .hsync_end = 800 + 40 + 128, 2043 .htotal = 800 + 40 + 128 + 88, 2044 .vdisplay = 480, 2045 .vsync_start = 480 + 10, 2046 .vsync_end = 480 + 10 + 2, 2047 .vtotal = 480 + 10 + 2 + 33, 2048 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2049 }; 2050 2051 static const struct panel_desc edt_etm0700g0dh6 = { 2052 .modes = &edt_etm0700g0dh6_mode, 2053 .num_modes = 1, 2054 .bpc = 6, 2055 .size = { 2056 .width = 152, 2057 .height = 91, 2058 }, 2059 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2060 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2061 .connector_type = DRM_MODE_CONNECTOR_DPI, 2062 }; 2063 2064 static const struct panel_desc edt_etm0700g0bdh6 = { 2065 .modes = &edt_etm0700g0dh6_mode, 2066 .num_modes = 1, 2067 .bpc = 6, 2068 .size = { 2069 .width = 152, 2070 .height = 91, 2071 }, 2072 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2073 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2074 .connector_type = DRM_MODE_CONNECTOR_DPI, 2075 }; 2076 2077 static const struct display_timing edt_etml0700y5dha_timing = { 2078 .pixelclock = { 40800000, 51200000, 67200000 }, 2079 .hactive = { 1024, 1024, 1024 }, 2080 .hfront_porch = { 30, 106, 125 }, 2081 .hback_porch = { 30, 106, 125 }, 2082 .hsync_len = { 30, 108, 126 }, 2083 .vactive = { 600, 600, 600 }, 2084 .vfront_porch = { 3, 12, 67}, 2085 .vback_porch = { 3, 12, 67 }, 2086 .vsync_len = { 4, 11, 66 }, 2087 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2088 DISPLAY_FLAGS_DE_HIGH, 2089 }; 2090 2091 static const struct panel_desc edt_etml0700y5dha = { 2092 .timings = &edt_etml0700y5dha_timing, 2093 .num_timings = 1, 2094 .bpc = 8, 2095 .size = { 2096 .width = 155, 2097 .height = 86, 2098 }, 2099 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2100 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2101 }; 2102 2103 static const struct display_timing edt_etml1010g3dra_timing = { 2104 .pixelclock = { 66300000, 72400000, 78900000 }, 2105 .hactive = { 1280, 1280, 1280 }, 2106 .hfront_porch = { 12, 72, 132 }, 2107 .hback_porch = { 86, 86, 86 }, 2108 .hsync_len = { 2, 2, 2 }, 2109 .vactive = { 800, 800, 800 }, 2110 .vfront_porch = { 1, 15, 49 }, 2111 .vback_porch = { 21, 21, 21 }, 2112 .vsync_len = { 2, 2, 2 }, 2113 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2114 DISPLAY_FLAGS_DE_HIGH, 2115 }; 2116 2117 static const struct panel_desc edt_etml1010g3dra = { 2118 .timings = &edt_etml1010g3dra_timing, 2119 .num_timings = 1, 2120 .bpc = 8, 2121 .size = { 2122 .width = 216, 2123 .height = 135, 2124 }, 2125 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2126 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2127 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2128 }; 2129 2130 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2131 .clock = 25175, 2132 .hdisplay = 640, 2133 .hsync_start = 640, 2134 .hsync_end = 640 + 16, 2135 .htotal = 640 + 16 + 30 + 114, 2136 .vdisplay = 480, 2137 .vsync_start = 480 + 10, 2138 .vsync_end = 480 + 10 + 3, 2139 .vtotal = 480 + 10 + 3 + 35, 2140 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2141 }; 2142 2143 static const struct panel_desc edt_etmv570g2dhu = { 2144 .modes = &edt_etmv570g2dhu_mode, 2145 .num_modes = 1, 2146 .bpc = 6, 2147 .size = { 2148 .width = 115, 2149 .height = 86, 2150 }, 2151 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2152 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2153 .connector_type = DRM_MODE_CONNECTOR_DPI, 2154 }; 2155 2156 static const struct display_timing eink_vb3300_kca_timing = { 2157 .pixelclock = { 40000000, 40000000, 40000000 }, 2158 .hactive = { 334, 334, 334 }, 2159 .hfront_porch = { 1, 1, 1 }, 2160 .hback_porch = { 1, 1, 1 }, 2161 .hsync_len = { 1, 1, 1 }, 2162 .vactive = { 1405, 1405, 1405 }, 2163 .vfront_porch = { 1, 1, 1 }, 2164 .vback_porch = { 1, 1, 1 }, 2165 .vsync_len = { 1, 1, 1 }, 2166 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2167 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2168 }; 2169 2170 static const struct panel_desc eink_vb3300_kca = { 2171 .timings = &eink_vb3300_kca_timing, 2172 .num_timings = 1, 2173 .bpc = 6, 2174 .size = { 2175 .width = 157, 2176 .height = 209, 2177 }, 2178 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2179 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2180 .connector_type = DRM_MODE_CONNECTOR_DPI, 2181 }; 2182 2183 static const struct display_timing evervision_vgg644804_timing = { 2184 .pixelclock = { 25175000, 25175000, 25175000 }, 2185 .hactive = { 640, 640, 640 }, 2186 .hfront_porch = { 16, 16, 16 }, 2187 .hback_porch = { 82, 114, 170 }, 2188 .hsync_len = { 5, 30, 30 }, 2189 .vactive = { 480, 480, 480 }, 2190 .vfront_porch = { 10, 10, 10 }, 2191 .vback_porch = { 30, 32, 34 }, 2192 .vsync_len = { 1, 3, 5 }, 2193 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2194 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2195 DISPLAY_FLAGS_SYNC_POSEDGE, 2196 }; 2197 2198 static const struct panel_desc evervision_vgg644804 = { 2199 .timings = &evervision_vgg644804_timing, 2200 .num_timings = 1, 2201 .bpc = 8, 2202 .size = { 2203 .width = 115, 2204 .height = 86, 2205 }, 2206 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2207 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2208 }; 2209 2210 static const struct display_timing evervision_vgg804821_timing = { 2211 .pixelclock = { 27600000, 33300000, 50000000 }, 2212 .hactive = { 800, 800, 800 }, 2213 .hfront_porch = { 40, 66, 70 }, 2214 .hback_porch = { 40, 67, 70 }, 2215 .hsync_len = { 40, 67, 70 }, 2216 .vactive = { 480, 480, 480 }, 2217 .vfront_porch = { 6, 10, 10 }, 2218 .vback_porch = { 7, 11, 11 }, 2219 .vsync_len = { 7, 11, 11 }, 2220 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2221 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2222 DISPLAY_FLAGS_SYNC_NEGEDGE, 2223 }; 2224 2225 static const struct panel_desc evervision_vgg804821 = { 2226 .timings = &evervision_vgg804821_timing, 2227 .num_timings = 1, 2228 .bpc = 8, 2229 .size = { 2230 .width = 108, 2231 .height = 64, 2232 }, 2233 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2234 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2235 }; 2236 2237 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2238 .clock = 32260, 2239 .hdisplay = 800, 2240 .hsync_start = 800 + 168, 2241 .hsync_end = 800 + 168 + 64, 2242 .htotal = 800 + 168 + 64 + 88, 2243 .vdisplay = 480, 2244 .vsync_start = 480 + 37, 2245 .vsync_end = 480 + 37 + 2, 2246 .vtotal = 480 + 37 + 2 + 8, 2247 }; 2248 2249 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2250 .modes = &foxlink_fl500wvr00_a0t_mode, 2251 .num_modes = 1, 2252 .bpc = 8, 2253 .size = { 2254 .width = 108, 2255 .height = 65, 2256 }, 2257 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2258 }; 2259 2260 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2261 { /* 60 Hz */ 2262 .clock = 6000, 2263 .hdisplay = 320, 2264 .hsync_start = 320 + 44, 2265 .hsync_end = 320 + 44 + 16, 2266 .htotal = 320 + 44 + 16 + 20, 2267 .vdisplay = 240, 2268 .vsync_start = 240 + 2, 2269 .vsync_end = 240 + 2 + 6, 2270 .vtotal = 240 + 2 + 6 + 2, 2271 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2272 }, 2273 { /* 50 Hz */ 2274 .clock = 5400, 2275 .hdisplay = 320, 2276 .hsync_start = 320 + 56, 2277 .hsync_end = 320 + 56 + 16, 2278 .htotal = 320 + 56 + 16 + 40, 2279 .vdisplay = 240, 2280 .vsync_start = 240 + 2, 2281 .vsync_end = 240 + 2 + 6, 2282 .vtotal = 240 + 2 + 6 + 2, 2283 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2284 }, 2285 }; 2286 2287 static const struct panel_desc frida_frd350h54004 = { 2288 .modes = frida_frd350h54004_modes, 2289 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2290 .bpc = 8, 2291 .size = { 2292 .width = 77, 2293 .height = 64, 2294 }, 2295 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2296 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2297 .connector_type = DRM_MODE_CONNECTOR_DPI, 2298 }; 2299 2300 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2301 .clock = 67185, 2302 .hdisplay = 800, 2303 .hsync_start = 800 + 20, 2304 .hsync_end = 800 + 20 + 24, 2305 .htotal = 800 + 20 + 24 + 20, 2306 .vdisplay = 1280, 2307 .vsync_start = 1280 + 4, 2308 .vsync_end = 1280 + 4 + 8, 2309 .vtotal = 1280 + 4 + 8 + 4, 2310 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2311 }; 2312 2313 static const struct panel_desc friendlyarm_hd702e = { 2314 .modes = &friendlyarm_hd702e_mode, 2315 .num_modes = 1, 2316 .size = { 2317 .width = 94, 2318 .height = 151, 2319 }, 2320 }; 2321 2322 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2323 .clock = 9000, 2324 .hdisplay = 480, 2325 .hsync_start = 480 + 5, 2326 .hsync_end = 480 + 5 + 1, 2327 .htotal = 480 + 5 + 1 + 40, 2328 .vdisplay = 272, 2329 .vsync_start = 272 + 8, 2330 .vsync_end = 272 + 8 + 1, 2331 .vtotal = 272 + 8 + 1 + 8, 2332 }; 2333 2334 static const struct panel_desc giantplus_gpg482739qs5 = { 2335 .modes = &giantplus_gpg482739qs5_mode, 2336 .num_modes = 1, 2337 .bpc = 8, 2338 .size = { 2339 .width = 95, 2340 .height = 54, 2341 }, 2342 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2343 }; 2344 2345 static const struct display_timing giantplus_gpm940b0_timing = { 2346 .pixelclock = { 13500000, 27000000, 27500000 }, 2347 .hactive = { 320, 320, 320 }, 2348 .hfront_porch = { 14, 686, 718 }, 2349 .hback_porch = { 50, 70, 255 }, 2350 .hsync_len = { 1, 1, 1 }, 2351 .vactive = { 240, 240, 240 }, 2352 .vfront_porch = { 1, 1, 179 }, 2353 .vback_porch = { 1, 21, 31 }, 2354 .vsync_len = { 1, 1, 6 }, 2355 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2356 }; 2357 2358 static const struct panel_desc giantplus_gpm940b0 = { 2359 .timings = &giantplus_gpm940b0_timing, 2360 .num_timings = 1, 2361 .bpc = 8, 2362 .size = { 2363 .width = 60, 2364 .height = 45, 2365 }, 2366 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2367 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2368 }; 2369 2370 static const struct display_timing hannstar_hsd070pww1_timing = { 2371 .pixelclock = { 64300000, 71100000, 82000000 }, 2372 .hactive = { 1280, 1280, 1280 }, 2373 .hfront_porch = { 1, 1, 10 }, 2374 .hback_porch = { 1, 1, 10 }, 2375 /* 2376 * According to the data sheet, the minimum horizontal blanking interval 2377 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2378 * minimum working horizontal blanking interval to be 60 clocks. 2379 */ 2380 .hsync_len = { 58, 158, 661 }, 2381 .vactive = { 800, 800, 800 }, 2382 .vfront_porch = { 1, 1, 10 }, 2383 .vback_porch = { 1, 1, 10 }, 2384 .vsync_len = { 1, 21, 203 }, 2385 .flags = DISPLAY_FLAGS_DE_HIGH, 2386 }; 2387 2388 static const struct panel_desc hannstar_hsd070pww1 = { 2389 .timings = &hannstar_hsd070pww1_timing, 2390 .num_timings = 1, 2391 .bpc = 6, 2392 .size = { 2393 .width = 151, 2394 .height = 94, 2395 }, 2396 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2397 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2398 }; 2399 2400 static const struct display_timing hannstar_hsd100pxn1_timing = { 2401 .pixelclock = { 55000000, 65000000, 75000000 }, 2402 .hactive = { 1024, 1024, 1024 }, 2403 .hfront_porch = { 40, 40, 40 }, 2404 .hback_porch = { 220, 220, 220 }, 2405 .hsync_len = { 20, 60, 100 }, 2406 .vactive = { 768, 768, 768 }, 2407 .vfront_porch = { 7, 7, 7 }, 2408 .vback_porch = { 21, 21, 21 }, 2409 .vsync_len = { 10, 10, 10 }, 2410 .flags = DISPLAY_FLAGS_DE_HIGH, 2411 }; 2412 2413 static const struct panel_desc hannstar_hsd100pxn1 = { 2414 .timings = &hannstar_hsd100pxn1_timing, 2415 .num_timings = 1, 2416 .bpc = 6, 2417 .size = { 2418 .width = 203, 2419 .height = 152, 2420 }, 2421 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2422 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2423 }; 2424 2425 static const struct display_timing hannstar_hsd101pww2_timing = { 2426 .pixelclock = { 64300000, 71100000, 82000000 }, 2427 .hactive = { 1280, 1280, 1280 }, 2428 .hfront_porch = { 1, 1, 10 }, 2429 .hback_porch = { 1, 1, 10 }, 2430 .hsync_len = { 58, 158, 661 }, 2431 .vactive = { 800, 800, 800 }, 2432 .vfront_porch = { 1, 1, 10 }, 2433 .vback_porch = { 1, 1, 10 }, 2434 .vsync_len = { 1, 21, 203 }, 2435 .flags = DISPLAY_FLAGS_DE_HIGH, 2436 }; 2437 2438 static const struct panel_desc hannstar_hsd101pww2 = { 2439 .timings = &hannstar_hsd101pww2_timing, 2440 .num_timings = 1, 2441 .bpc = 8, 2442 .size = { 2443 .width = 217, 2444 .height = 136, 2445 }, 2446 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2447 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2448 }; 2449 2450 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2451 .clock = 33333, 2452 .hdisplay = 800, 2453 .hsync_start = 800 + 85, 2454 .hsync_end = 800 + 85 + 86, 2455 .htotal = 800 + 85 + 86 + 85, 2456 .vdisplay = 480, 2457 .vsync_start = 480 + 16, 2458 .vsync_end = 480 + 16 + 13, 2459 .vtotal = 480 + 16 + 13 + 16, 2460 }; 2461 2462 static const struct panel_desc hitachi_tx23d38vm0caa = { 2463 .modes = &hitachi_tx23d38vm0caa_mode, 2464 .num_modes = 1, 2465 .bpc = 6, 2466 .size = { 2467 .width = 195, 2468 .height = 117, 2469 }, 2470 .delay = { 2471 .enable = 160, 2472 .disable = 160, 2473 }, 2474 }; 2475 2476 static const struct drm_display_mode innolux_at043tn24_mode = { 2477 .clock = 9000, 2478 .hdisplay = 480, 2479 .hsync_start = 480 + 2, 2480 .hsync_end = 480 + 2 + 41, 2481 .htotal = 480 + 2 + 41 + 2, 2482 .vdisplay = 272, 2483 .vsync_start = 272 + 2, 2484 .vsync_end = 272 + 2 + 10, 2485 .vtotal = 272 + 2 + 10 + 2, 2486 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2487 }; 2488 2489 static const struct panel_desc innolux_at043tn24 = { 2490 .modes = &innolux_at043tn24_mode, 2491 .num_modes = 1, 2492 .bpc = 8, 2493 .size = { 2494 .width = 95, 2495 .height = 54, 2496 }, 2497 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2498 .connector_type = DRM_MODE_CONNECTOR_DPI, 2499 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2500 }; 2501 2502 static const struct drm_display_mode innolux_at070tn92_mode = { 2503 .clock = 33333, 2504 .hdisplay = 800, 2505 .hsync_start = 800 + 210, 2506 .hsync_end = 800 + 210 + 20, 2507 .htotal = 800 + 210 + 20 + 46, 2508 .vdisplay = 480, 2509 .vsync_start = 480 + 22, 2510 .vsync_end = 480 + 22 + 10, 2511 .vtotal = 480 + 22 + 23 + 10, 2512 }; 2513 2514 static const struct panel_desc innolux_at070tn92 = { 2515 .modes = &innolux_at070tn92_mode, 2516 .num_modes = 1, 2517 .size = { 2518 .width = 154, 2519 .height = 86, 2520 }, 2521 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2522 }; 2523 2524 static const struct display_timing innolux_g070ace_l01_timing = { 2525 .pixelclock = { 25200000, 35000000, 35700000 }, 2526 .hactive = { 800, 800, 800 }, 2527 .hfront_porch = { 30, 32, 87 }, 2528 .hback_porch = { 30, 32, 87 }, 2529 .hsync_len = { 1, 1, 1 }, 2530 .vactive = { 480, 480, 480 }, 2531 .vfront_porch = { 3, 3, 3 }, 2532 .vback_porch = { 13, 13, 13 }, 2533 .vsync_len = { 1, 1, 4 }, 2534 .flags = DISPLAY_FLAGS_DE_HIGH, 2535 }; 2536 2537 static const struct panel_desc innolux_g070ace_l01 = { 2538 .timings = &innolux_g070ace_l01_timing, 2539 .num_timings = 1, 2540 .bpc = 8, 2541 .size = { 2542 .width = 152, 2543 .height = 91, 2544 }, 2545 .delay = { 2546 .prepare = 10, 2547 .enable = 50, 2548 .disable = 50, 2549 .unprepare = 500, 2550 }, 2551 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2552 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2553 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2554 }; 2555 2556 static const struct display_timing innolux_g070y2_l01_timing = { 2557 .pixelclock = { 28000000, 29500000, 32000000 }, 2558 .hactive = { 800, 800, 800 }, 2559 .hfront_porch = { 61, 91, 141 }, 2560 .hback_porch = { 60, 90, 140 }, 2561 .hsync_len = { 12, 12, 12 }, 2562 .vactive = { 480, 480, 480 }, 2563 .vfront_porch = { 4, 9, 30 }, 2564 .vback_porch = { 4, 8, 28 }, 2565 .vsync_len = { 2, 2, 2 }, 2566 .flags = DISPLAY_FLAGS_DE_HIGH, 2567 }; 2568 2569 static const struct panel_desc innolux_g070y2_l01 = { 2570 .timings = &innolux_g070y2_l01_timing, 2571 .num_timings = 1, 2572 .bpc = 8, 2573 .size = { 2574 .width = 152, 2575 .height = 91, 2576 }, 2577 .delay = { 2578 .prepare = 10, 2579 .enable = 100, 2580 .disable = 100, 2581 .unprepare = 800, 2582 }, 2583 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2584 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2585 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2586 }; 2587 2588 static const struct display_timing innolux_g070ace_lh3_timing = { 2589 .pixelclock = { 25200000, 25400000, 35700000 }, 2590 .hactive = { 800, 800, 800 }, 2591 .hfront_porch = { 30, 32, 87 }, 2592 .hback_porch = { 29, 31, 86 }, 2593 .hsync_len = { 1, 1, 1 }, 2594 .vactive = { 480, 480, 480 }, 2595 .vfront_porch = { 4, 5, 65 }, 2596 .vback_porch = { 3, 4, 65 }, 2597 .vsync_len = { 1, 1, 1 }, 2598 .flags = DISPLAY_FLAGS_DE_HIGH, 2599 }; 2600 2601 static const struct panel_desc innolux_g070ace_lh3 = { 2602 .timings = &innolux_g070ace_lh3_timing, 2603 .num_timings = 1, 2604 .bpc = 8, 2605 .size = { 2606 .width = 152, 2607 .height = 91, 2608 }, 2609 .delay = { 2610 .prepare = 10, 2611 .enable = 450, 2612 .disable = 200, 2613 .unprepare = 510, 2614 }, 2615 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2616 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2617 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2618 }; 2619 2620 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2621 .clock = 33333, 2622 .hdisplay = 800, 2623 .hsync_start = 800 + 210, 2624 .hsync_end = 800 + 210 + 20, 2625 .htotal = 800 + 210 + 20 + 46, 2626 .vdisplay = 480, 2627 .vsync_start = 480 + 22, 2628 .vsync_end = 480 + 22 + 10, 2629 .vtotal = 480 + 22 + 23 + 10, 2630 }; 2631 2632 static const struct panel_desc innolux_g070y2_t02 = { 2633 .modes = &innolux_g070y2_t02_mode, 2634 .num_modes = 1, 2635 .bpc = 8, 2636 .size = { 2637 .width = 152, 2638 .height = 92, 2639 }, 2640 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2641 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2642 .connector_type = DRM_MODE_CONNECTOR_DPI, 2643 }; 2644 2645 static const struct display_timing innolux_g101ice_l01_timing = { 2646 .pixelclock = { 60400000, 71100000, 74700000 }, 2647 .hactive = { 1280, 1280, 1280 }, 2648 .hfront_porch = { 30, 60, 70 }, 2649 .hback_porch = { 30, 60, 70 }, 2650 .hsync_len = { 22, 40, 60 }, 2651 .vactive = { 800, 800, 800 }, 2652 .vfront_porch = { 3, 8, 14 }, 2653 .vback_porch = { 3, 8, 14 }, 2654 .vsync_len = { 4, 7, 12 }, 2655 .flags = DISPLAY_FLAGS_DE_HIGH, 2656 }; 2657 2658 static const struct panel_desc innolux_g101ice_l01 = { 2659 .timings = &innolux_g101ice_l01_timing, 2660 .num_timings = 1, 2661 .bpc = 8, 2662 .size = { 2663 .width = 217, 2664 .height = 135, 2665 }, 2666 .delay = { 2667 .enable = 200, 2668 .disable = 200, 2669 }, 2670 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2671 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2672 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2673 }; 2674 2675 static const struct display_timing innolux_g121i1_l01_timing = { 2676 .pixelclock = { 67450000, 71000000, 74550000 }, 2677 .hactive = { 1280, 1280, 1280 }, 2678 .hfront_porch = { 40, 80, 160 }, 2679 .hback_porch = { 39, 79, 159 }, 2680 .hsync_len = { 1, 1, 1 }, 2681 .vactive = { 800, 800, 800 }, 2682 .vfront_porch = { 5, 11, 100 }, 2683 .vback_porch = { 4, 11, 99 }, 2684 .vsync_len = { 1, 1, 1 }, 2685 }; 2686 2687 static const struct panel_desc innolux_g121i1_l01 = { 2688 .timings = &innolux_g121i1_l01_timing, 2689 .num_timings = 1, 2690 .bpc = 6, 2691 .size = { 2692 .width = 261, 2693 .height = 163, 2694 }, 2695 .delay = { 2696 .enable = 200, 2697 .disable = 20, 2698 }, 2699 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2700 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2701 }; 2702 2703 static const struct display_timing innolux_g121x1_l03_timings = { 2704 .pixelclock = { 57500000, 64900000, 74400000 }, 2705 .hactive = { 1024, 1024, 1024 }, 2706 .hfront_porch = { 90, 140, 190 }, 2707 .hback_porch = { 90, 140, 190 }, 2708 .hsync_len = { 36, 40, 60 }, 2709 .vactive = { 768, 768, 768 }, 2710 .vfront_porch = { 2, 15, 30 }, 2711 .vback_porch = { 2, 15, 30 }, 2712 .vsync_len = { 2, 8, 20 }, 2713 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2714 }; 2715 2716 static const struct panel_desc innolux_g121x1_l03 = { 2717 .timings = &innolux_g121x1_l03_timings, 2718 .num_timings = 1, 2719 .bpc = 6, 2720 .size = { 2721 .width = 246, 2722 .height = 185, 2723 }, 2724 .delay = { 2725 .enable = 200, 2726 .unprepare = 200, 2727 .disable = 400, 2728 }, 2729 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2730 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2731 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2732 }; 2733 2734 static const struct panel_desc innolux_g121xce_l01 = { 2735 .timings = &innolux_g121x1_l03_timings, 2736 .num_timings = 1, 2737 .bpc = 8, 2738 .size = { 2739 .width = 246, 2740 .height = 185, 2741 }, 2742 .delay = { 2743 .enable = 200, 2744 .unprepare = 200, 2745 .disable = 400, 2746 }, 2747 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2748 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2749 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2750 }; 2751 2752 static const struct display_timing innolux_g156hce_l01_timings = { 2753 .pixelclock = { 120000000, 141860000, 150000000 }, 2754 .hactive = { 1920, 1920, 1920 }, 2755 .hfront_porch = { 80, 90, 100 }, 2756 .hback_porch = { 80, 90, 100 }, 2757 .hsync_len = { 20, 30, 30 }, 2758 .vactive = { 1080, 1080, 1080 }, 2759 .vfront_porch = { 3, 10, 20 }, 2760 .vback_porch = { 3, 10, 20 }, 2761 .vsync_len = { 4, 10, 10 }, 2762 }; 2763 2764 static const struct panel_desc innolux_g156hce_l01 = { 2765 .timings = &innolux_g156hce_l01_timings, 2766 .num_timings = 1, 2767 .bpc = 8, 2768 .size = { 2769 .width = 344, 2770 .height = 194, 2771 }, 2772 .delay = { 2773 .prepare = 1, /* T1+T2 */ 2774 .enable = 450, /* T5 */ 2775 .disable = 200, /* T6 */ 2776 .unprepare = 10, /* T3+T7 */ 2777 }, 2778 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2779 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2780 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2781 }; 2782 2783 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2784 .clock = 69300, 2785 .hdisplay = 1366, 2786 .hsync_start = 1366 + 16, 2787 .hsync_end = 1366 + 16 + 34, 2788 .htotal = 1366 + 16 + 34 + 50, 2789 .vdisplay = 768, 2790 .vsync_start = 768 + 2, 2791 .vsync_end = 768 + 2 + 6, 2792 .vtotal = 768 + 2 + 6 + 12, 2793 }; 2794 2795 static const struct panel_desc innolux_n156bge_l21 = { 2796 .modes = &innolux_n156bge_l21_mode, 2797 .num_modes = 1, 2798 .bpc = 6, 2799 .size = { 2800 .width = 344, 2801 .height = 193, 2802 }, 2803 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2804 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2805 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2806 }; 2807 2808 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2809 .clock = 51501, 2810 .hdisplay = 1024, 2811 .hsync_start = 1024 + 128, 2812 .hsync_end = 1024 + 128 + 64, 2813 .htotal = 1024 + 128 + 64 + 128, 2814 .vdisplay = 600, 2815 .vsync_start = 600 + 16, 2816 .vsync_end = 600 + 16 + 4, 2817 .vtotal = 600 + 16 + 4 + 16, 2818 }; 2819 2820 static const struct panel_desc innolux_zj070na_01p = { 2821 .modes = &innolux_zj070na_01p_mode, 2822 .num_modes = 1, 2823 .bpc = 6, 2824 .size = { 2825 .width = 154, 2826 .height = 90, 2827 }, 2828 }; 2829 2830 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2831 .pixelclock = { 5580000, 5850000, 6200000 }, 2832 .hactive = { 320, 320, 320 }, 2833 .hfront_porch = { 30, 30, 30 }, 2834 .hback_porch = { 30, 30, 30 }, 2835 .hsync_len = { 1, 5, 17 }, 2836 .vactive = { 240, 240, 240 }, 2837 .vfront_porch = { 6, 6, 6 }, 2838 .vback_porch = { 5, 5, 5 }, 2839 .vsync_len = { 1, 2, 11 }, 2840 .flags = DISPLAY_FLAGS_DE_HIGH, 2841 }; 2842 2843 static const struct panel_desc koe_tx14d24vm1bpa = { 2844 .timings = &koe_tx14d24vm1bpa_timing, 2845 .num_timings = 1, 2846 .bpc = 6, 2847 .size = { 2848 .width = 115, 2849 .height = 86, 2850 }, 2851 }; 2852 2853 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2854 .pixelclock = { 151820000, 156720000, 159780000 }, 2855 .hactive = { 1920, 1920, 1920 }, 2856 .hfront_porch = { 105, 130, 142 }, 2857 .hback_porch = { 45, 70, 82 }, 2858 .hsync_len = { 30, 30, 30 }, 2859 .vactive = { 1200, 1200, 1200}, 2860 .vfront_porch = { 3, 5, 10 }, 2861 .vback_porch = { 2, 5, 10 }, 2862 .vsync_len = { 5, 5, 5 }, 2863 .flags = DISPLAY_FLAGS_DE_HIGH, 2864 }; 2865 2866 static const struct panel_desc koe_tx26d202vm0bwa = { 2867 .timings = &koe_tx26d202vm0bwa_timing, 2868 .num_timings = 1, 2869 .bpc = 8, 2870 .size = { 2871 .width = 217, 2872 .height = 136, 2873 }, 2874 .delay = { 2875 .prepare = 1000, 2876 .enable = 1000, 2877 .unprepare = 1000, 2878 .disable = 1000, 2879 }, 2880 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2881 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2882 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2883 }; 2884 2885 static const struct display_timing koe_tx31d200vm0baa_timing = { 2886 .pixelclock = { 39600000, 43200000, 48000000 }, 2887 .hactive = { 1280, 1280, 1280 }, 2888 .hfront_porch = { 16, 36, 56 }, 2889 .hback_porch = { 16, 36, 56 }, 2890 .hsync_len = { 8, 8, 8 }, 2891 .vactive = { 480, 480, 480 }, 2892 .vfront_porch = { 6, 21, 33 }, 2893 .vback_porch = { 6, 21, 33 }, 2894 .vsync_len = { 8, 8, 8 }, 2895 .flags = DISPLAY_FLAGS_DE_HIGH, 2896 }; 2897 2898 static const struct panel_desc koe_tx31d200vm0baa = { 2899 .timings = &koe_tx31d200vm0baa_timing, 2900 .num_timings = 1, 2901 .bpc = 6, 2902 .size = { 2903 .width = 292, 2904 .height = 109, 2905 }, 2906 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2907 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2908 }; 2909 2910 static const struct display_timing kyo_tcg121xglp_timing = { 2911 .pixelclock = { 52000000, 65000000, 71000000 }, 2912 .hactive = { 1024, 1024, 1024 }, 2913 .hfront_porch = { 2, 2, 2 }, 2914 .hback_porch = { 2, 2, 2 }, 2915 .hsync_len = { 86, 124, 244 }, 2916 .vactive = { 768, 768, 768 }, 2917 .vfront_porch = { 2, 2, 2 }, 2918 .vback_porch = { 2, 2, 2 }, 2919 .vsync_len = { 6, 34, 73 }, 2920 .flags = DISPLAY_FLAGS_DE_HIGH, 2921 }; 2922 2923 static const struct panel_desc kyo_tcg121xglp = { 2924 .timings = &kyo_tcg121xglp_timing, 2925 .num_timings = 1, 2926 .bpc = 8, 2927 .size = { 2928 .width = 246, 2929 .height = 184, 2930 }, 2931 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2932 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2933 }; 2934 2935 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2936 .clock = 7000, 2937 .hdisplay = 320, 2938 .hsync_start = 320 + 20, 2939 .hsync_end = 320 + 20 + 30, 2940 .htotal = 320 + 20 + 30 + 38, 2941 .vdisplay = 240, 2942 .vsync_start = 240 + 4, 2943 .vsync_end = 240 + 4 + 3, 2944 .vtotal = 240 + 4 + 3 + 15, 2945 }; 2946 2947 static const struct panel_desc lemaker_bl035_rgb_002 = { 2948 .modes = &lemaker_bl035_rgb_002_mode, 2949 .num_modes = 1, 2950 .size = { 2951 .width = 70, 2952 .height = 52, 2953 }, 2954 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2955 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2956 }; 2957 2958 static const struct display_timing lg_lb070wv8_timing = { 2959 .pixelclock = { 31950000, 33260000, 34600000 }, 2960 .hactive = { 800, 800, 800 }, 2961 .hfront_porch = { 88, 88, 88 }, 2962 .hback_porch = { 88, 88, 88 }, 2963 .hsync_len = { 80, 80, 80 }, 2964 .vactive = { 480, 480, 480 }, 2965 .vfront_porch = { 10, 10, 10 }, 2966 .vback_porch = { 10, 10, 10 }, 2967 .vsync_len = { 25, 25, 25 }, 2968 }; 2969 2970 static const struct panel_desc lg_lb070wv8 = { 2971 .timings = &lg_lb070wv8_timing, 2972 .num_timings = 1, 2973 .bpc = 8, 2974 .size = { 2975 .width = 151, 2976 .height = 91, 2977 }, 2978 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2979 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2980 }; 2981 2982 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 2983 .clock = 155127, 2984 .hdisplay = 1920, 2985 .hsync_start = 1920 + 128, 2986 .hsync_end = 1920 + 128 + 20, 2987 .htotal = 1920 + 128 + 20 + 12, 2988 .vdisplay = 1200, 2989 .vsync_start = 1200 + 19, 2990 .vsync_end = 1200 + 19 + 4, 2991 .vtotal = 1200 + 19 + 4 + 20, 2992 }; 2993 2994 static const struct panel_desc lincolntech_lcd185_101ct = { 2995 .modes = &lincolntech_lcd185_101ct_mode, 2996 .bpc = 8, 2997 .num_modes = 1, 2998 .size = { 2999 .width = 217, 3000 .height = 136, 3001 }, 3002 .delay = { 3003 .prepare = 50, 3004 .disable = 50, 3005 }, 3006 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3007 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3008 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3009 }; 3010 3011 static const struct display_timing logictechno_lt161010_2nh_timing = { 3012 .pixelclock = { 26400000, 33300000, 46800000 }, 3013 .hactive = { 800, 800, 800 }, 3014 .hfront_porch = { 16, 210, 354 }, 3015 .hback_porch = { 46, 46, 46 }, 3016 .hsync_len = { 1, 20, 40 }, 3017 .vactive = { 480, 480, 480 }, 3018 .vfront_porch = { 7, 22, 147 }, 3019 .vback_porch = { 23, 23, 23 }, 3020 .vsync_len = { 1, 10, 20 }, 3021 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3022 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3023 DISPLAY_FLAGS_SYNC_POSEDGE, 3024 }; 3025 3026 static const struct panel_desc logictechno_lt161010_2nh = { 3027 .timings = &logictechno_lt161010_2nh_timing, 3028 .num_timings = 1, 3029 .bpc = 6, 3030 .size = { 3031 .width = 154, 3032 .height = 86, 3033 }, 3034 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3035 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3036 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3037 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3038 .connector_type = DRM_MODE_CONNECTOR_DPI, 3039 }; 3040 3041 static const struct display_timing logictechno_lt170410_2whc_timing = { 3042 .pixelclock = { 68900000, 71100000, 73400000 }, 3043 .hactive = { 1280, 1280, 1280 }, 3044 .hfront_porch = { 23, 60, 71 }, 3045 .hback_porch = { 23, 60, 71 }, 3046 .hsync_len = { 15, 40, 47 }, 3047 .vactive = { 800, 800, 800 }, 3048 .vfront_porch = { 5, 7, 10 }, 3049 .vback_porch = { 5, 7, 10 }, 3050 .vsync_len = { 6, 9, 12 }, 3051 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3052 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3053 DISPLAY_FLAGS_SYNC_POSEDGE, 3054 }; 3055 3056 static const struct panel_desc logictechno_lt170410_2whc = { 3057 .timings = &logictechno_lt170410_2whc_timing, 3058 .num_timings = 1, 3059 .bpc = 8, 3060 .size = { 3061 .width = 217, 3062 .height = 136, 3063 }, 3064 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3065 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3066 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3067 }; 3068 3069 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3070 .clock = 33000, 3071 .hdisplay = 800, 3072 .hsync_start = 800 + 112, 3073 .hsync_end = 800 + 112 + 3, 3074 .htotal = 800 + 112 + 3 + 85, 3075 .vdisplay = 480, 3076 .vsync_start = 480 + 38, 3077 .vsync_end = 480 + 38 + 3, 3078 .vtotal = 480 + 38 + 3 + 29, 3079 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3080 }; 3081 3082 static const struct panel_desc logictechno_lttd800480070_l2rt = { 3083 .modes = &logictechno_lttd800480070_l2rt_mode, 3084 .num_modes = 1, 3085 .bpc = 8, 3086 .size = { 3087 .width = 154, 3088 .height = 86, 3089 }, 3090 .delay = { 3091 .prepare = 45, 3092 .enable = 100, 3093 .disable = 100, 3094 .unprepare = 45 3095 }, 3096 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3097 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3098 .connector_type = DRM_MODE_CONNECTOR_DPI, 3099 }; 3100 3101 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3102 .clock = 33000, 3103 .hdisplay = 800, 3104 .hsync_start = 800 + 154, 3105 .hsync_end = 800 + 154 + 3, 3106 .htotal = 800 + 154 + 3 + 43, 3107 .vdisplay = 480, 3108 .vsync_start = 480 + 47, 3109 .vsync_end = 480 + 47 + 3, 3110 .vtotal = 480 + 47 + 3 + 20, 3111 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3112 }; 3113 3114 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3115 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3116 .num_modes = 1, 3117 .bpc = 8, 3118 .size = { 3119 .width = 154, 3120 .height = 86, 3121 }, 3122 .delay = { 3123 .prepare = 45, 3124 .enable = 100, 3125 .disable = 100, 3126 .unprepare = 45 3127 }, 3128 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3129 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3130 .connector_type = DRM_MODE_CONNECTOR_DPI, 3131 }; 3132 3133 static const struct drm_display_mode logicpd_type_28_mode = { 3134 .clock = 9107, 3135 .hdisplay = 480, 3136 .hsync_start = 480 + 3, 3137 .hsync_end = 480 + 3 + 42, 3138 .htotal = 480 + 3 + 42 + 2, 3139 3140 .vdisplay = 272, 3141 .vsync_start = 272 + 2, 3142 .vsync_end = 272 + 2 + 11, 3143 .vtotal = 272 + 2 + 11 + 3, 3144 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3145 }; 3146 3147 static const struct panel_desc logicpd_type_28 = { 3148 .modes = &logicpd_type_28_mode, 3149 .num_modes = 1, 3150 .bpc = 8, 3151 .size = { 3152 .width = 105, 3153 .height = 67, 3154 }, 3155 .delay = { 3156 .prepare = 200, 3157 .enable = 200, 3158 .unprepare = 200, 3159 .disable = 200, 3160 }, 3161 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3162 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3163 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3164 .connector_type = DRM_MODE_CONNECTOR_DPI, 3165 }; 3166 3167 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3168 .clock = 150275, 3169 .hdisplay = 1920, 3170 .hsync_start = 1920 + 32, 3171 .hsync_end = 1920 + 32 + 52, 3172 .htotal = 1920 + 32 + 52 + 24, 3173 .vdisplay = 1200, 3174 .vsync_start = 1200 + 24, 3175 .vsync_end = 1200 + 24 + 8, 3176 .vtotal = 1200 + 24 + 8 + 3, 3177 }; 3178 3179 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3180 .modes = µtips_mf_101hiebcaf0_c_mode, 3181 .bpc = 8, 3182 .num_modes = 1, 3183 .size = { 3184 .width = 217, 3185 .height = 136, 3186 }, 3187 .delay = { 3188 .prepare = 50, 3189 .disable = 50, 3190 }, 3191 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3192 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3193 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3194 }; 3195 3196 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3197 .clock = 93301, 3198 .hdisplay = 1920, 3199 .hsync_start = 1920 + 72, 3200 .hsync_end = 1920 + 72 + 72, 3201 .htotal = 1920 + 72 + 72 + 72, 3202 .vdisplay = 720, 3203 .vsync_start = 720 + 3, 3204 .vsync_end = 720 + 3 + 3, 3205 .vtotal = 720 + 3 + 3 + 2, 3206 }; 3207 3208 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3209 .modes = µtips_mf_103hieb0ga0_mode, 3210 .bpc = 8, 3211 .num_modes = 1, 3212 .size = { 3213 .width = 244, 3214 .height = 92, 3215 }, 3216 .delay = { 3217 .prepare = 50, 3218 .disable = 50, 3219 }, 3220 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3221 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3222 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3223 }; 3224 3225 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3226 .clock = 30400, 3227 .hdisplay = 800, 3228 .hsync_start = 800 + 0, 3229 .hsync_end = 800 + 1, 3230 .htotal = 800 + 0 + 1 + 160, 3231 .vdisplay = 480, 3232 .vsync_start = 480 + 0, 3233 .vsync_end = 480 + 48 + 1, 3234 .vtotal = 480 + 48 + 1 + 0, 3235 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3236 }; 3237 3238 static const struct panel_desc mitsubishi_aa070mc01 = { 3239 .modes = &mitsubishi_aa070mc01_mode, 3240 .num_modes = 1, 3241 .bpc = 8, 3242 .size = { 3243 .width = 152, 3244 .height = 91, 3245 }, 3246 3247 .delay = { 3248 .enable = 200, 3249 .unprepare = 200, 3250 .disable = 400, 3251 }, 3252 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3253 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3254 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3255 }; 3256 3257 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3258 .clock = 56234, 3259 .hdisplay = 1024, 3260 .hsync_start = 1024 + 24, 3261 .hsync_end = 1024 + 24 + 63, 3262 .htotal = 1024 + 24 + 63 + 1, 3263 .vdisplay = 768, 3264 .vsync_start = 768 + 3, 3265 .vsync_end = 768 + 3 + 6, 3266 .vtotal = 768 + 3 + 6 + 1, 3267 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3268 }; 3269 3270 static const struct panel_desc mitsubishi_aa084xe01 = { 3271 .modes = &mitsubishi_aa084xe01_mode, 3272 .num_modes = 1, 3273 .bpc = 8, 3274 .size = { 3275 .width = 1024, 3276 .height = 768, 3277 }, 3278 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3279 .connector_type = DRM_MODE_CONNECTOR_DPI, 3280 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3281 }; 3282 3283 static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3284 .pixelclock = { 26400000, 33000000, 46800000 }, 3285 .hactive = { 800, 800, 800 }, 3286 .hfront_porch = { 16, 204, 354 }, 3287 .hback_porch = { 46, 46, 46 }, 3288 .hsync_len = { 1, 6, 40 }, 3289 .vactive = { 480, 480, 480 }, 3290 .vfront_porch = { 7, 22, 147 }, 3291 .vback_porch = { 23, 23, 23 }, 3292 .vsync_len = { 1, 3, 20 }, 3293 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3294 DISPLAY_FLAGS_DE_HIGH, 3295 }; 3296 3297 static const struct panel_desc multi_inno_mi0700a2t_30 = { 3298 .timings = &multi_inno_mi0700a2t_30_timing, 3299 .num_timings = 1, 3300 .bpc = 6, 3301 .size = { 3302 .width = 153, 3303 .height = 92, 3304 }, 3305 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3306 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3307 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3308 }; 3309 3310 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3311 .pixelclock = { 29000000, 33000000, 38000000 }, 3312 .hactive = { 800, 800, 800 }, 3313 .hfront_porch = { 180, 210, 240 }, 3314 .hback_porch = { 16, 16, 16 }, 3315 .hsync_len = { 30, 30, 30 }, 3316 .vactive = { 480, 480, 480 }, 3317 .vfront_porch = { 12, 22, 32 }, 3318 .vback_porch = { 10, 10, 10 }, 3319 .vsync_len = { 13, 13, 13 }, 3320 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3321 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3322 DISPLAY_FLAGS_SYNC_POSEDGE, 3323 }; 3324 3325 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3326 .timings = &multi_inno_mi0700s4t_6_timing, 3327 .num_timings = 1, 3328 .bpc = 8, 3329 .size = { 3330 .width = 154, 3331 .height = 86, 3332 }, 3333 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3334 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3335 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3336 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3337 .connector_type = DRM_MODE_CONNECTOR_DPI, 3338 }; 3339 3340 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3341 .pixelclock = { 32000000, 40000000, 50000000 }, 3342 .hactive = { 800, 800, 800 }, 3343 .hfront_porch = { 16, 210, 354 }, 3344 .hback_porch = { 6, 26, 45 }, 3345 .hsync_len = { 1, 20, 40 }, 3346 .vactive = { 600, 600, 600 }, 3347 .vfront_porch = { 1, 12, 77 }, 3348 .vback_porch = { 3, 13, 22 }, 3349 .vsync_len = { 1, 10, 20 }, 3350 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3351 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3352 DISPLAY_FLAGS_SYNC_POSEDGE, 3353 }; 3354 3355 static const struct panel_desc multi_inno_mi0800ft_9 = { 3356 .timings = &multi_inno_mi0800ft_9_timing, 3357 .num_timings = 1, 3358 .bpc = 8, 3359 .size = { 3360 .width = 162, 3361 .height = 122, 3362 }, 3363 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3364 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3365 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3366 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3367 .connector_type = DRM_MODE_CONNECTOR_DPI, 3368 }; 3369 3370 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3371 .pixelclock = { 68900000, 70000000, 73400000 }, 3372 .hactive = { 1280, 1280, 1280 }, 3373 .hfront_porch = { 30, 60, 71 }, 3374 .hback_porch = { 30, 60, 71 }, 3375 .hsync_len = { 10, 10, 48 }, 3376 .vactive = { 800, 800, 800 }, 3377 .vfront_porch = { 5, 10, 10 }, 3378 .vback_porch = { 5, 10, 10 }, 3379 .vsync_len = { 5, 6, 13 }, 3380 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3381 DISPLAY_FLAGS_DE_HIGH, 3382 }; 3383 3384 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3385 .timings = &multi_inno_mi1010ait_1cp_timing, 3386 .num_timings = 1, 3387 .bpc = 8, 3388 .size = { 3389 .width = 217, 3390 .height = 136, 3391 }, 3392 .delay = { 3393 .enable = 50, 3394 .disable = 50, 3395 }, 3396 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3397 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3398 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3399 }; 3400 3401 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3402 .pixelclock = { 40800000, 51200000, 67200000 }, 3403 .hactive = { 1024, 1024, 1024 }, 3404 .hfront_porch = { 30, 110, 130 }, 3405 .hback_porch = { 30, 110, 130 }, 3406 .hsync_len = { 30, 100, 116 }, 3407 .vactive = { 600, 600, 600 }, 3408 .vfront_porch = { 4, 13, 80 }, 3409 .vback_porch = { 4, 13, 80 }, 3410 .vsync_len = { 2, 9, 40 }, 3411 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3412 DISPLAY_FLAGS_DE_HIGH, 3413 }; 3414 3415 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3416 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3417 .num_timings = 1, 3418 .bpc = 6, 3419 .size = { 3420 .width = 260, 3421 .height = 162, 3422 }, 3423 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3424 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3425 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3426 }; 3427 3428 static const struct display_timing nec_nl12880bc20_05_timing = { 3429 .pixelclock = { 67000000, 71000000, 75000000 }, 3430 .hactive = { 1280, 1280, 1280 }, 3431 .hfront_porch = { 2, 30, 30 }, 3432 .hback_porch = { 6, 100, 100 }, 3433 .hsync_len = { 2, 30, 30 }, 3434 .vactive = { 800, 800, 800 }, 3435 .vfront_porch = { 5, 5, 5 }, 3436 .vback_porch = { 11, 11, 11 }, 3437 .vsync_len = { 7, 7, 7 }, 3438 }; 3439 3440 static const struct panel_desc nec_nl12880bc20_05 = { 3441 .timings = &nec_nl12880bc20_05_timing, 3442 .num_timings = 1, 3443 .bpc = 8, 3444 .size = { 3445 .width = 261, 3446 .height = 163, 3447 }, 3448 .delay = { 3449 .enable = 50, 3450 .disable = 50, 3451 }, 3452 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3453 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3454 }; 3455 3456 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3457 .clock = 10870, 3458 .hdisplay = 480, 3459 .hsync_start = 480 + 2, 3460 .hsync_end = 480 + 2 + 41, 3461 .htotal = 480 + 2 + 41 + 2, 3462 .vdisplay = 272, 3463 .vsync_start = 272 + 2, 3464 .vsync_end = 272 + 2 + 4, 3465 .vtotal = 272 + 2 + 4 + 2, 3466 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3467 }; 3468 3469 static const struct panel_desc nec_nl4827hc19_05b = { 3470 .modes = &nec_nl4827hc19_05b_mode, 3471 .num_modes = 1, 3472 .bpc = 8, 3473 .size = { 3474 .width = 95, 3475 .height = 54, 3476 }, 3477 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3478 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3479 }; 3480 3481 static const struct drm_display_mode netron_dy_e231732_mode = { 3482 .clock = 66000, 3483 .hdisplay = 1024, 3484 .hsync_start = 1024 + 160, 3485 .hsync_end = 1024 + 160 + 70, 3486 .htotal = 1024 + 160 + 70 + 90, 3487 .vdisplay = 600, 3488 .vsync_start = 600 + 127, 3489 .vsync_end = 600 + 127 + 20, 3490 .vtotal = 600 + 127 + 20 + 3, 3491 }; 3492 3493 static const struct panel_desc netron_dy_e231732 = { 3494 .modes = &netron_dy_e231732_mode, 3495 .num_modes = 1, 3496 .size = { 3497 .width = 154, 3498 .height = 87, 3499 }, 3500 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3501 }; 3502 3503 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3504 .clock = 9000, 3505 .hdisplay = 480, 3506 .hsync_start = 480 + 2, 3507 .hsync_end = 480 + 2 + 41, 3508 .htotal = 480 + 2 + 41 + 2, 3509 .vdisplay = 272, 3510 .vsync_start = 272 + 2, 3511 .vsync_end = 272 + 2 + 10, 3512 .vtotal = 272 + 2 + 10 + 2, 3513 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3514 }; 3515 3516 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3517 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3518 .num_modes = 1, 3519 .bpc = 8, 3520 .size = { 3521 .width = 95, 3522 .height = 54, 3523 }, 3524 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3525 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3526 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3527 .connector_type = DRM_MODE_CONNECTOR_DPI, 3528 }; 3529 3530 static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { 3531 .clock = 75400, 3532 .hdisplay = 1366, 3533 .hsync_start = 1366 + 14, 3534 .hsync_end = 1366 + 14 + 56, 3535 .htotal = 1366 + 14 + 56 + 64, 3536 .vdisplay = 768, 3537 .vsync_start = 768 + 1, 3538 .vsync_end = 768 + 1 + 3, 3539 .vtotal = 768 + 1 + 3 + 22, 3540 }; 3541 3542 static const struct panel_desc nlt_nl13676bc25_03f = { 3543 .modes = &nlt_nl13676bc25_03f_mode, 3544 .num_modes = 1, 3545 .bpc = 8, 3546 .size = { 3547 .width = 363, 3548 .height = 215, 3549 }, 3550 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3551 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3552 }; 3553 3554 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3555 .pixelclock = { 130000000, 148350000, 163000000 }, 3556 .hactive = { 1920, 1920, 1920 }, 3557 .hfront_porch = { 80, 100, 100 }, 3558 .hback_porch = { 100, 120, 120 }, 3559 .hsync_len = { 50, 60, 60 }, 3560 .vactive = { 1080, 1080, 1080 }, 3561 .vfront_porch = { 12, 30, 30 }, 3562 .vback_porch = { 4, 10, 10 }, 3563 .vsync_len = { 4, 5, 5 }, 3564 }; 3565 3566 static const struct panel_desc nlt_nl192108ac18_02d = { 3567 .timings = &nlt_nl192108ac18_02d_timing, 3568 .num_timings = 1, 3569 .bpc = 8, 3570 .size = { 3571 .width = 344, 3572 .height = 194, 3573 }, 3574 .delay = { 3575 .unprepare = 500, 3576 }, 3577 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3578 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3579 }; 3580 3581 static const struct drm_display_mode nvd_9128_mode = { 3582 .clock = 29500, 3583 .hdisplay = 800, 3584 .hsync_start = 800 + 130, 3585 .hsync_end = 800 + 130 + 98, 3586 .htotal = 800 + 0 + 130 + 98, 3587 .vdisplay = 480, 3588 .vsync_start = 480 + 10, 3589 .vsync_end = 480 + 10 + 50, 3590 .vtotal = 480 + 0 + 10 + 50, 3591 }; 3592 3593 static const struct panel_desc nvd_9128 = { 3594 .modes = &nvd_9128_mode, 3595 .num_modes = 1, 3596 .bpc = 8, 3597 .size = { 3598 .width = 156, 3599 .height = 88, 3600 }, 3601 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3602 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3603 }; 3604 3605 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3606 .pixelclock = { 30000000, 30000000, 40000000 }, 3607 .hactive = { 800, 800, 800 }, 3608 .hfront_porch = { 40, 40, 40 }, 3609 .hback_porch = { 40, 40, 40 }, 3610 .hsync_len = { 1, 48, 48 }, 3611 .vactive = { 480, 480, 480 }, 3612 .vfront_porch = { 13, 13, 13 }, 3613 .vback_porch = { 29, 29, 29 }, 3614 .vsync_len = { 3, 3, 3 }, 3615 .flags = DISPLAY_FLAGS_DE_HIGH, 3616 }; 3617 3618 static const struct panel_desc okaya_rs800480t_7x0gp = { 3619 .timings = &okaya_rs800480t_7x0gp_timing, 3620 .num_timings = 1, 3621 .bpc = 6, 3622 .size = { 3623 .width = 154, 3624 .height = 87, 3625 }, 3626 .delay = { 3627 .prepare = 41, 3628 .enable = 50, 3629 .unprepare = 41, 3630 .disable = 50, 3631 }, 3632 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3633 }; 3634 3635 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3636 .clock = 9000, 3637 .hdisplay = 480, 3638 .hsync_start = 480 + 5, 3639 .hsync_end = 480 + 5 + 30, 3640 .htotal = 480 + 5 + 30 + 10, 3641 .vdisplay = 272, 3642 .vsync_start = 272 + 8, 3643 .vsync_end = 272 + 8 + 5, 3644 .vtotal = 272 + 8 + 5 + 3, 3645 }; 3646 3647 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3648 .modes = &olimex_lcd_olinuxino_43ts_mode, 3649 .num_modes = 1, 3650 .size = { 3651 .width = 95, 3652 .height = 54, 3653 }, 3654 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3655 }; 3656 3657 static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 3658 .pixelclock = { 30000000, 30000000, 50000000 }, 3659 .hactive = { 800, 800, 800 }, 3660 .hfront_porch = { 1, 40, 255 }, 3661 .hback_porch = { 1, 40, 87 }, 3662 .hsync_len = { 1, 48, 87 }, 3663 .vactive = { 480, 480, 480 }, 3664 .vfront_porch = { 1, 13, 255 }, 3665 .vback_porch = { 1, 29, 29 }, 3666 .vsync_len = { 3, 3, 31 }, 3667 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3668 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3669 }; 3670 3671 static const struct panel_desc ontat_kd50g21_40nt_a1 = { 3672 .timings = &ontat_kd50g21_40nt_a1_timing, 3673 .num_timings = 1, 3674 .bpc = 8, 3675 .size = { 3676 .width = 108, 3677 .height = 65, 3678 }, 3679 .delay = { 3680 .prepare = 147, /* 5 VSDs */ 3681 .enable = 147, /* 5 VSDs */ 3682 .disable = 88, /* 3 VSDs */ 3683 .unprepare = 117, /* 4 VSDs */ 3684 }, 3685 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3686 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3687 .connector_type = DRM_MODE_CONNECTOR_DPI, 3688 }; 3689 3690 /* 3691 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3692 * pixel clocks, but this is the timing that was being used in the Adafruit 3693 * installation instructions. 3694 */ 3695 static const struct drm_display_mode ontat_yx700wv03_mode = { 3696 .clock = 29500, 3697 .hdisplay = 800, 3698 .hsync_start = 824, 3699 .hsync_end = 896, 3700 .htotal = 992, 3701 .vdisplay = 480, 3702 .vsync_start = 483, 3703 .vsync_end = 493, 3704 .vtotal = 500, 3705 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3706 }; 3707 3708 /* 3709 * Specification at: 3710 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3711 */ 3712 static const struct panel_desc ontat_yx700wv03 = { 3713 .modes = &ontat_yx700wv03_mode, 3714 .num_modes = 1, 3715 .bpc = 8, 3716 .size = { 3717 .width = 154, 3718 .height = 83, 3719 }, 3720 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3721 }; 3722 3723 static const struct drm_display_mode ortustech_com37h3m_mode = { 3724 .clock = 22230, 3725 .hdisplay = 480, 3726 .hsync_start = 480 + 40, 3727 .hsync_end = 480 + 40 + 10, 3728 .htotal = 480 + 40 + 10 + 40, 3729 .vdisplay = 640, 3730 .vsync_start = 640 + 4, 3731 .vsync_end = 640 + 4 + 2, 3732 .vtotal = 640 + 4 + 2 + 4, 3733 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3734 }; 3735 3736 static const struct panel_desc ortustech_com37h3m = { 3737 .modes = &ortustech_com37h3m_mode, 3738 .num_modes = 1, 3739 .bpc = 8, 3740 .size = { 3741 .width = 56, /* 56.16mm */ 3742 .height = 75, /* 74.88mm */ 3743 }, 3744 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3745 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3746 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3747 }; 3748 3749 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3750 .clock = 25000, 3751 .hdisplay = 480, 3752 .hsync_start = 480 + 10, 3753 .hsync_end = 480 + 10 + 10, 3754 .htotal = 480 + 10 + 10 + 15, 3755 .vdisplay = 800, 3756 .vsync_start = 800 + 3, 3757 .vsync_end = 800 + 3 + 3, 3758 .vtotal = 800 + 3 + 3 + 3, 3759 }; 3760 3761 static const struct panel_desc ortustech_com43h4m85ulc = { 3762 .modes = &ortustech_com43h4m85ulc_mode, 3763 .num_modes = 1, 3764 .bpc = 6, 3765 .size = { 3766 .width = 56, 3767 .height = 93, 3768 }, 3769 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3770 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3771 .connector_type = DRM_MODE_CONNECTOR_DPI, 3772 }; 3773 3774 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3775 .clock = 33000, 3776 .hdisplay = 800, 3777 .hsync_start = 800 + 210, 3778 .hsync_end = 800 + 210 + 30, 3779 .htotal = 800 + 210 + 30 + 16, 3780 .vdisplay = 480, 3781 .vsync_start = 480 + 22, 3782 .vsync_end = 480 + 22 + 13, 3783 .vtotal = 480 + 22 + 13 + 10, 3784 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3785 }; 3786 3787 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3788 .modes = &osddisplays_osd070t1718_19ts_mode, 3789 .num_modes = 1, 3790 .bpc = 8, 3791 .size = { 3792 .width = 152, 3793 .height = 91, 3794 }, 3795 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3796 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3797 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3798 .connector_type = DRM_MODE_CONNECTOR_DPI, 3799 }; 3800 3801 static const struct drm_display_mode pda_91_00156_a0_mode = { 3802 .clock = 33300, 3803 .hdisplay = 800, 3804 .hsync_start = 800 + 1, 3805 .hsync_end = 800 + 1 + 64, 3806 .htotal = 800 + 1 + 64 + 64, 3807 .vdisplay = 480, 3808 .vsync_start = 480 + 1, 3809 .vsync_end = 480 + 1 + 23, 3810 .vtotal = 480 + 1 + 23 + 22, 3811 }; 3812 3813 static const struct panel_desc pda_91_00156_a0 = { 3814 .modes = &pda_91_00156_a0_mode, 3815 .num_modes = 1, 3816 .size = { 3817 .width = 152, 3818 .height = 91, 3819 }, 3820 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3821 }; 3822 3823 static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { 3824 .clock = 71150, 3825 .hdisplay = 1280, 3826 .hsync_start = 1280 + 48, 3827 .hsync_end = 1280 + 48 + 32, 3828 .htotal = 1280 + 48 + 32 + 80, 3829 .vdisplay = 800, 3830 .vsync_start = 800 + 9, 3831 .vsync_end = 800 + 9 + 8, 3832 .vtotal = 800 + 9 + 8 + 6, 3833 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3834 }; 3835 3836 static const struct panel_desc powertip_ph128800t004_zza01 = { 3837 .modes = &powertip_ph128800t004_zza01_mode, 3838 .num_modes = 1, 3839 .bpc = 8, 3840 .size = { 3841 .width = 216, 3842 .height = 135, 3843 }, 3844 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3845 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3846 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3847 }; 3848 3849 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 3850 .clock = 66500, 3851 .hdisplay = 1280, 3852 .hsync_start = 1280 + 12, 3853 .hsync_end = 1280 + 12 + 20, 3854 .htotal = 1280 + 12 + 20 + 56, 3855 .vdisplay = 800, 3856 .vsync_start = 800 + 1, 3857 .vsync_end = 800 + 1 + 3, 3858 .vtotal = 800 + 1 + 3 + 20, 3859 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3860 }; 3861 3862 static const struct panel_desc powertip_ph128800t006_zhc01 = { 3863 .modes = &powertip_ph128800t006_zhc01_mode, 3864 .num_modes = 1, 3865 .bpc = 8, 3866 .size = { 3867 .width = 216, 3868 .height = 135, 3869 }, 3870 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3871 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3872 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3873 }; 3874 3875 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3876 .clock = 24750, 3877 .hdisplay = 800, 3878 .hsync_start = 800 + 54, 3879 .hsync_end = 800 + 54 + 2, 3880 .htotal = 800 + 54 + 2 + 44, 3881 .vdisplay = 480, 3882 .vsync_start = 480 + 49, 3883 .vsync_end = 480 + 49 + 2, 3884 .vtotal = 480 + 49 + 2 + 22, 3885 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3886 }; 3887 3888 static const struct panel_desc powertip_ph800480t013_idf02 = { 3889 .modes = &powertip_ph800480t013_idf02_mode, 3890 .num_modes = 1, 3891 .bpc = 8, 3892 .size = { 3893 .width = 152, 3894 .height = 91, 3895 }, 3896 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3897 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3898 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3899 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3900 .connector_type = DRM_MODE_CONNECTOR_DPI, 3901 }; 3902 3903 static const struct drm_display_mode primeview_pm070wl4_mode = { 3904 .clock = 32000, 3905 .hdisplay = 800, 3906 .hsync_start = 800 + 42, 3907 .hsync_end = 800 + 42 + 128, 3908 .htotal = 800 + 42 + 128 + 86, 3909 .vdisplay = 480, 3910 .vsync_start = 480 + 10, 3911 .vsync_end = 480 + 10 + 2, 3912 .vtotal = 480 + 10 + 2 + 33, 3913 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3914 }; 3915 3916 static const struct panel_desc primeview_pm070wl4 = { 3917 .modes = &primeview_pm070wl4_mode, 3918 .num_modes = 1, 3919 .bpc = 6, 3920 .size = { 3921 .width = 152, 3922 .height = 91, 3923 }, 3924 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3925 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3926 .connector_type = DRM_MODE_CONNECTOR_DPI, 3927 }; 3928 3929 static const struct drm_display_mode qd43003c0_40_mode = { 3930 .clock = 9000, 3931 .hdisplay = 480, 3932 .hsync_start = 480 + 8, 3933 .hsync_end = 480 + 8 + 4, 3934 .htotal = 480 + 8 + 4 + 39, 3935 .vdisplay = 272, 3936 .vsync_start = 272 + 4, 3937 .vsync_end = 272 + 4 + 10, 3938 .vtotal = 272 + 4 + 10 + 2, 3939 }; 3940 3941 static const struct panel_desc qd43003c0_40 = { 3942 .modes = &qd43003c0_40_mode, 3943 .num_modes = 1, 3944 .bpc = 8, 3945 .size = { 3946 .width = 95, 3947 .height = 53, 3948 }, 3949 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3950 }; 3951 3952 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3953 { /* 60 Hz */ 3954 .clock = 10800, 3955 .hdisplay = 480, 3956 .hsync_start = 480 + 77, 3957 .hsync_end = 480 + 77 + 41, 3958 .htotal = 480 + 77 + 41 + 2, 3959 .vdisplay = 272, 3960 .vsync_start = 272 + 16, 3961 .vsync_end = 272 + 16 + 10, 3962 .vtotal = 272 + 16 + 10 + 2, 3963 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3964 }, 3965 { /* 50 Hz */ 3966 .clock = 10800, 3967 .hdisplay = 480, 3968 .hsync_start = 480 + 17, 3969 .hsync_end = 480 + 17 + 41, 3970 .htotal = 480 + 17 + 41 + 2, 3971 .vdisplay = 272, 3972 .vsync_start = 272 + 116, 3973 .vsync_end = 272 + 116 + 10, 3974 .vtotal = 272 + 116 + 10 + 2, 3975 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3976 }, 3977 }; 3978 3979 static const struct panel_desc qishenglong_gopher2b_lcd = { 3980 .modes = qishenglong_gopher2b_lcd_modes, 3981 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3982 .bpc = 8, 3983 .size = { 3984 .width = 95, 3985 .height = 54, 3986 }, 3987 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3988 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3989 .connector_type = DRM_MODE_CONNECTOR_DPI, 3990 }; 3991 3992 static const struct display_timing rocktech_rk043fn48h_timing = { 3993 .pixelclock = { 6000000, 9000000, 12000000 }, 3994 .hactive = { 480, 480, 480 }, 3995 .hback_porch = { 8, 43, 43 }, 3996 .hfront_porch = { 2, 8, 10 }, 3997 .hsync_len = { 1, 1, 1 }, 3998 .vactive = { 272, 272, 272 }, 3999 .vback_porch = { 2, 12, 26 }, 4000 .vfront_porch = { 1, 4, 4 }, 4001 .vsync_len = { 1, 10, 10 }, 4002 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 4003 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4004 DISPLAY_FLAGS_SYNC_POSEDGE, 4005 }; 4006 4007 static const struct panel_desc rocktech_rk043fn48h = { 4008 .timings = &rocktech_rk043fn48h_timing, 4009 .num_timings = 1, 4010 .bpc = 8, 4011 .size = { 4012 .width = 95, 4013 .height = 54, 4014 }, 4015 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4016 .connector_type = DRM_MODE_CONNECTOR_DPI, 4017 }; 4018 4019 static const struct display_timing rocktech_rk070er9427_timing = { 4020 .pixelclock = { 26400000, 33300000, 46800000 }, 4021 .hactive = { 800, 800, 800 }, 4022 .hfront_porch = { 16, 210, 354 }, 4023 .hback_porch = { 46, 46, 46 }, 4024 .hsync_len = { 1, 1, 1 }, 4025 .vactive = { 480, 480, 480 }, 4026 .vfront_porch = { 7, 22, 147 }, 4027 .vback_porch = { 23, 23, 23 }, 4028 .vsync_len = { 1, 1, 1 }, 4029 .flags = DISPLAY_FLAGS_DE_HIGH, 4030 }; 4031 4032 static const struct panel_desc rocktech_rk070er9427 = { 4033 .timings = &rocktech_rk070er9427_timing, 4034 .num_timings = 1, 4035 .bpc = 6, 4036 .size = { 4037 .width = 154, 4038 .height = 86, 4039 }, 4040 .delay = { 4041 .prepare = 41, 4042 .enable = 50, 4043 .unprepare = 41, 4044 .disable = 50, 4045 }, 4046 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4047 }; 4048 4049 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4050 .clock = 71100, 4051 .hdisplay = 1280, 4052 .hsync_start = 1280 + 48, 4053 .hsync_end = 1280 + 48 + 32, 4054 .htotal = 1280 + 48 + 32 + 80, 4055 .vdisplay = 800, 4056 .vsync_start = 800 + 2, 4057 .vsync_end = 800 + 2 + 5, 4058 .vtotal = 800 + 2 + 5 + 16, 4059 }; 4060 4061 static const struct panel_desc rocktech_rk101ii01d_ct = { 4062 .modes = &rocktech_rk101ii01d_ct_mode, 4063 .bpc = 8, 4064 .num_modes = 1, 4065 .size = { 4066 .width = 217, 4067 .height = 136, 4068 }, 4069 .delay = { 4070 .prepare = 50, 4071 .disable = 50, 4072 }, 4073 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4074 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4075 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4076 }; 4077 4078 static const struct display_timing samsung_ltl101al01_timing = { 4079 .pixelclock = { 66663000, 66663000, 66663000 }, 4080 .hactive = { 1280, 1280, 1280 }, 4081 .hfront_porch = { 18, 18, 18 }, 4082 .hback_porch = { 36, 36, 36 }, 4083 .hsync_len = { 16, 16, 16 }, 4084 .vactive = { 800, 800, 800 }, 4085 .vfront_porch = { 4, 4, 4 }, 4086 .vback_porch = { 16, 16, 16 }, 4087 .vsync_len = { 3, 3, 3 }, 4088 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4089 }; 4090 4091 static const struct panel_desc samsung_ltl101al01 = { 4092 .timings = &samsung_ltl101al01_timing, 4093 .num_timings = 1, 4094 .bpc = 8, 4095 .size = { 4096 .width = 217, 4097 .height = 135, 4098 }, 4099 .delay = { 4100 .prepare = 40, 4101 .enable = 300, 4102 .disable = 200, 4103 .unprepare = 600, 4104 }, 4105 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4106 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4107 }; 4108 4109 static const struct drm_display_mode samsung_ltn101nt05_mode = { 4110 .clock = 54030, 4111 .hdisplay = 1024, 4112 .hsync_start = 1024 + 24, 4113 .hsync_end = 1024 + 24 + 136, 4114 .htotal = 1024 + 24 + 136 + 160, 4115 .vdisplay = 600, 4116 .vsync_start = 600 + 3, 4117 .vsync_end = 600 + 3 + 6, 4118 .vtotal = 600 + 3 + 6 + 61, 4119 }; 4120 4121 static const struct panel_desc samsung_ltn101nt05 = { 4122 .modes = &samsung_ltn101nt05_mode, 4123 .num_modes = 1, 4124 .bpc = 6, 4125 .size = { 4126 .width = 223, 4127 .height = 125, 4128 }, 4129 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4130 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4131 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4132 }; 4133 4134 static const struct display_timing satoz_sat050at40h12r2_timing = { 4135 .pixelclock = {33300000, 33300000, 50000000}, 4136 .hactive = {800, 800, 800}, 4137 .hfront_porch = {16, 210, 354}, 4138 .hback_porch = {46, 46, 46}, 4139 .hsync_len = {1, 1, 40}, 4140 .vactive = {480, 480, 480}, 4141 .vfront_porch = {7, 22, 147}, 4142 .vback_porch = {23, 23, 23}, 4143 .vsync_len = {1, 1, 20}, 4144 }; 4145 4146 static const struct panel_desc satoz_sat050at40h12r2 = { 4147 .timings = &satoz_sat050at40h12r2_timing, 4148 .num_timings = 1, 4149 .bpc = 8, 4150 .size = { 4151 .width = 108, 4152 .height = 65, 4153 }, 4154 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4155 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4156 }; 4157 4158 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4159 .clock = 33260, 4160 .hdisplay = 800, 4161 .hsync_start = 800 + 64, 4162 .hsync_end = 800 + 64 + 128, 4163 .htotal = 800 + 64 + 128 + 64, 4164 .vdisplay = 480, 4165 .vsync_start = 480 + 8, 4166 .vsync_end = 480 + 8 + 2, 4167 .vtotal = 480 + 8 + 2 + 35, 4168 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4169 }; 4170 4171 static const struct panel_desc sharp_lq070y3dg3b = { 4172 .modes = &sharp_lq070y3dg3b_mode, 4173 .num_modes = 1, 4174 .bpc = 8, 4175 .size = { 4176 .width = 152, /* 152.4mm */ 4177 .height = 91, /* 91.4mm */ 4178 }, 4179 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4180 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4181 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4182 }; 4183 4184 static const struct drm_display_mode sharp_lq035q7db03_mode = { 4185 .clock = 5500, 4186 .hdisplay = 240, 4187 .hsync_start = 240 + 16, 4188 .hsync_end = 240 + 16 + 7, 4189 .htotal = 240 + 16 + 7 + 5, 4190 .vdisplay = 320, 4191 .vsync_start = 320 + 9, 4192 .vsync_end = 320 + 9 + 1, 4193 .vtotal = 320 + 9 + 1 + 7, 4194 }; 4195 4196 static const struct panel_desc sharp_lq035q7db03 = { 4197 .modes = &sharp_lq035q7db03_mode, 4198 .num_modes = 1, 4199 .bpc = 6, 4200 .size = { 4201 .width = 54, 4202 .height = 72, 4203 }, 4204 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4205 }; 4206 4207 static const struct display_timing sharp_lq101k1ly04_timing = { 4208 .pixelclock = { 60000000, 65000000, 80000000 }, 4209 .hactive = { 1280, 1280, 1280 }, 4210 .hfront_porch = { 20, 20, 20 }, 4211 .hback_porch = { 20, 20, 20 }, 4212 .hsync_len = { 10, 10, 10 }, 4213 .vactive = { 800, 800, 800 }, 4214 .vfront_porch = { 4, 4, 4 }, 4215 .vback_porch = { 4, 4, 4 }, 4216 .vsync_len = { 4, 4, 4 }, 4217 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4218 }; 4219 4220 static const struct panel_desc sharp_lq101k1ly04 = { 4221 .timings = &sharp_lq101k1ly04_timing, 4222 .num_timings = 1, 4223 .bpc = 8, 4224 .size = { 4225 .width = 217, 4226 .height = 136, 4227 }, 4228 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4229 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4230 }; 4231 4232 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4233 { /* 50 Hz */ 4234 .clock = 3000, 4235 .hdisplay = 240, 4236 .hsync_start = 240 + 58, 4237 .hsync_end = 240 + 58 + 1, 4238 .htotal = 240 + 58 + 1 + 1, 4239 .vdisplay = 160, 4240 .vsync_start = 160 + 24, 4241 .vsync_end = 160 + 24 + 10, 4242 .vtotal = 160 + 24 + 10 + 6, 4243 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4244 }, 4245 { /* 60 Hz */ 4246 .clock = 3000, 4247 .hdisplay = 240, 4248 .hsync_start = 240 + 8, 4249 .hsync_end = 240 + 8 + 1, 4250 .htotal = 240 + 8 + 1 + 1, 4251 .vdisplay = 160, 4252 .vsync_start = 160 + 24, 4253 .vsync_end = 160 + 24 + 10, 4254 .vtotal = 160 + 24 + 10 + 6, 4255 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4256 }, 4257 }; 4258 4259 static const struct panel_desc sharp_ls020b1dd01d = { 4260 .modes = sharp_ls020b1dd01d_modes, 4261 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4262 .bpc = 6, 4263 .size = { 4264 .width = 42, 4265 .height = 28, 4266 }, 4267 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4268 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4269 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4270 | DRM_BUS_FLAG_SHARP_SIGNALS, 4271 }; 4272 4273 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4274 .clock = 33300, 4275 .hdisplay = 800, 4276 .hsync_start = 800 + 1, 4277 .hsync_end = 800 + 1 + 64, 4278 .htotal = 800 + 1 + 64 + 64, 4279 .vdisplay = 480, 4280 .vsync_start = 480 + 1, 4281 .vsync_end = 480 + 1 + 23, 4282 .vtotal = 480 + 1 + 23 + 22, 4283 }; 4284 4285 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4286 .modes = &shelly_sca07010_bfn_lnn_mode, 4287 .num_modes = 1, 4288 .size = { 4289 .width = 152, 4290 .height = 91, 4291 }, 4292 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4293 }; 4294 4295 static const struct drm_display_mode starry_kr070pe2t_mode = { 4296 .clock = 33000, 4297 .hdisplay = 800, 4298 .hsync_start = 800 + 209, 4299 .hsync_end = 800 + 209 + 1, 4300 .htotal = 800 + 209 + 1 + 45, 4301 .vdisplay = 480, 4302 .vsync_start = 480 + 22, 4303 .vsync_end = 480 + 22 + 1, 4304 .vtotal = 480 + 22 + 1 + 22, 4305 }; 4306 4307 static const struct panel_desc starry_kr070pe2t = { 4308 .modes = &starry_kr070pe2t_mode, 4309 .num_modes = 1, 4310 .bpc = 8, 4311 .size = { 4312 .width = 152, 4313 .height = 86, 4314 }, 4315 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4316 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4317 .connector_type = DRM_MODE_CONNECTOR_DPI, 4318 }; 4319 4320 static const struct display_timing startek_kd070wvfpa_mode = { 4321 .pixelclock = { 25200000, 27200000, 30500000 }, 4322 .hactive = { 800, 800, 800 }, 4323 .hfront_porch = { 19, 44, 115 }, 4324 .hback_porch = { 5, 16, 101 }, 4325 .hsync_len = { 1, 2, 100 }, 4326 .vactive = { 480, 480, 480 }, 4327 .vfront_porch = { 5, 43, 67 }, 4328 .vback_porch = { 5, 5, 67 }, 4329 .vsync_len = { 1, 2, 66 }, 4330 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4331 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4332 DISPLAY_FLAGS_SYNC_POSEDGE, 4333 }; 4334 4335 static const struct panel_desc startek_kd070wvfpa = { 4336 .timings = &startek_kd070wvfpa_mode, 4337 .num_timings = 1, 4338 .bpc = 8, 4339 .size = { 4340 .width = 152, 4341 .height = 91, 4342 }, 4343 .delay = { 4344 .prepare = 20, 4345 .enable = 200, 4346 .disable = 200, 4347 }, 4348 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4349 .connector_type = DRM_MODE_CONNECTOR_DPI, 4350 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4351 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4352 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4353 }; 4354 4355 static const struct display_timing tsd_tst043015cmhx_timing = { 4356 .pixelclock = { 5000000, 9000000, 12000000 }, 4357 .hactive = { 480, 480, 480 }, 4358 .hfront_porch = { 4, 5, 65 }, 4359 .hback_porch = { 36, 40, 255 }, 4360 .hsync_len = { 1, 1, 1 }, 4361 .vactive = { 272, 272, 272 }, 4362 .vfront_porch = { 2, 8, 97 }, 4363 .vback_porch = { 3, 8, 31 }, 4364 .vsync_len = { 1, 1, 1 }, 4365 4366 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4367 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4368 }; 4369 4370 static const struct panel_desc tsd_tst043015cmhx = { 4371 .timings = &tsd_tst043015cmhx_timing, 4372 .num_timings = 1, 4373 .bpc = 8, 4374 .size = { 4375 .width = 105, 4376 .height = 67, 4377 }, 4378 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4379 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4380 }; 4381 4382 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4383 .clock = 30000, 4384 .hdisplay = 800, 4385 .hsync_start = 800 + 39, 4386 .hsync_end = 800 + 39 + 47, 4387 .htotal = 800 + 39 + 47 + 39, 4388 .vdisplay = 480, 4389 .vsync_start = 480 + 13, 4390 .vsync_end = 480 + 13 + 2, 4391 .vtotal = 480 + 13 + 2 + 29, 4392 }; 4393 4394 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4395 .modes = &tfc_s9700rtwv43tr_01b_mode, 4396 .num_modes = 1, 4397 .bpc = 8, 4398 .size = { 4399 .width = 155, 4400 .height = 90, 4401 }, 4402 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4403 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4404 }; 4405 4406 static const struct display_timing tianma_tm070jdhg30_timing = { 4407 .pixelclock = { 62600000, 68200000, 78100000 }, 4408 .hactive = { 1280, 1280, 1280 }, 4409 .hfront_porch = { 15, 64, 159 }, 4410 .hback_porch = { 5, 5, 5 }, 4411 .hsync_len = { 1, 1, 256 }, 4412 .vactive = { 800, 800, 800 }, 4413 .vfront_porch = { 3, 40, 99 }, 4414 .vback_porch = { 2, 2, 2 }, 4415 .vsync_len = { 1, 1, 128 }, 4416 .flags = DISPLAY_FLAGS_DE_HIGH, 4417 }; 4418 4419 static const struct panel_desc tianma_tm070jdhg30 = { 4420 .timings = &tianma_tm070jdhg30_timing, 4421 .num_timings = 1, 4422 .bpc = 8, 4423 .size = { 4424 .width = 151, 4425 .height = 95, 4426 }, 4427 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4428 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4429 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4430 }; 4431 4432 static const struct panel_desc tianma_tm070jvhg33 = { 4433 .timings = &tianma_tm070jdhg30_timing, 4434 .num_timings = 1, 4435 .bpc = 8, 4436 .size = { 4437 .width = 150, 4438 .height = 94, 4439 }, 4440 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4441 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4442 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4443 }; 4444 4445 /* 4446 * The TM070JDHG34-00 datasheet computes total blanking as back porch + 4447 * front porch, not including sync pulse width. This is for both H and 4448 * V. To make the total blanking and period correct, subtract the pulse 4449 * width from the front porch. 4450 * 4451 * This works well for the Min and Typ values, but for Max values the sync 4452 * pulse width is higher than back porch + front porch, so work around that 4453 * by reducing the Max sync length value to 1 and then treating the Max 4454 * porches as in the Min and Typ cases. 4455 * 4456 * Exact datasheet values are added as a comment where they differ from the 4457 * ones implemented for the above reason. 4458 * 4459 * The P0700WXF1MBAA datasheet is even less detailed, only listing period 4460 * and total blanking time, however the resulting values are the same as 4461 * the TM070JDHG34-00. 4462 */ 4463 static const struct display_timing tianma_tm070jdhg34_00_timing = { 4464 .pixelclock = { 68400000, 71900000, 78100000 }, 4465 .hactive = { 1280, 1280, 1280 }, 4466 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4467 .hback_porch = { 5, 5, 5 }, 4468 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4469 .vactive = { 800, 800, 800 }, 4470 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4471 .vback_porch = { 2, 2, 2 }, 4472 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4473 .flags = DISPLAY_FLAGS_DE_HIGH, 4474 }; 4475 4476 static const struct panel_desc tianma_tm070jdhg34_00 = { 4477 .timings = &tianma_tm070jdhg34_00_timing, 4478 .num_timings = 1, 4479 .bpc = 8, 4480 .size = { 4481 .width = 150, /* 149.76 */ 4482 .height = 94, /* 93.60 */ 4483 }, 4484 .delay = { 4485 .prepare = 15, /* Tp1 */ 4486 .enable = 150, /* Tp2 */ 4487 .disable = 150, /* Tp4 */ 4488 .unprepare = 120, /* Tp3 */ 4489 }, 4490 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4491 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4492 }; 4493 4494 static const struct panel_desc tianma_p0700wxf1mbaa = { 4495 .timings = &tianma_tm070jdhg34_00_timing, 4496 .num_timings = 1, 4497 .bpc = 8, 4498 .size = { 4499 .width = 150, /* 149.76 */ 4500 .height = 94, /* 93.60 */ 4501 }, 4502 .delay = { 4503 .prepare = 18, /* Tr + Tp1 */ 4504 .enable = 152, /* Tp2 + Tp5 */ 4505 .disable = 152, /* Tp6 + Tp4 */ 4506 .unprepare = 120, /* Tp3 */ 4507 }, 4508 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4509 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4510 }; 4511 4512 static const struct display_timing tianma_tm070rvhg71_timing = { 4513 .pixelclock = { 27700000, 29200000, 39600000 }, 4514 .hactive = { 800, 800, 800 }, 4515 .hfront_porch = { 12, 40, 212 }, 4516 .hback_porch = { 88, 88, 88 }, 4517 .hsync_len = { 1, 1, 40 }, 4518 .vactive = { 480, 480, 480 }, 4519 .vfront_porch = { 1, 13, 88 }, 4520 .vback_porch = { 32, 32, 32 }, 4521 .vsync_len = { 1, 1, 3 }, 4522 .flags = DISPLAY_FLAGS_DE_HIGH, 4523 }; 4524 4525 static const struct panel_desc tianma_tm070rvhg71 = { 4526 .timings = &tianma_tm070rvhg71_timing, 4527 .num_timings = 1, 4528 .bpc = 8, 4529 .size = { 4530 .width = 154, 4531 .height = 86, 4532 }, 4533 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4534 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4535 }; 4536 4537 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4538 { 4539 .clock = 10000, 4540 .hdisplay = 320, 4541 .hsync_start = 320 + 50, 4542 .hsync_end = 320 + 50 + 6, 4543 .htotal = 320 + 50 + 6 + 38, 4544 .vdisplay = 240, 4545 .vsync_start = 240 + 3, 4546 .vsync_end = 240 + 3 + 1, 4547 .vtotal = 240 + 3 + 1 + 17, 4548 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4549 }, 4550 }; 4551 4552 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4553 .modes = ti_nspire_cx_lcd_mode, 4554 .num_modes = 1, 4555 .bpc = 8, 4556 .size = { 4557 .width = 65, 4558 .height = 49, 4559 }, 4560 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4561 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4562 }; 4563 4564 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4565 { 4566 .clock = 10000, 4567 .hdisplay = 320, 4568 .hsync_start = 320 + 6, 4569 .hsync_end = 320 + 6 + 6, 4570 .htotal = 320 + 6 + 6 + 6, 4571 .vdisplay = 240, 4572 .vsync_start = 240 + 0, 4573 .vsync_end = 240 + 0 + 1, 4574 .vtotal = 240 + 0 + 1 + 0, 4575 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4576 }, 4577 }; 4578 4579 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4580 .modes = ti_nspire_classic_lcd_mode, 4581 .num_modes = 1, 4582 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4583 .bpc = 8, 4584 .size = { 4585 .width = 71, 4586 .height = 53, 4587 }, 4588 /* This is the grayscale bus format */ 4589 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4590 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4591 }; 4592 4593 static const struct display_timing topland_tian_g07017_01_timing = { 4594 .pixelclock = { 44900000, 51200000, 63000000 }, 4595 .hactive = { 1024, 1024, 1024 }, 4596 .hfront_porch = { 16, 160, 216 }, 4597 .hback_porch = { 160, 160, 160 }, 4598 .hsync_len = { 1, 1, 140 }, 4599 .vactive = { 600, 600, 600 }, 4600 .vfront_porch = { 1, 12, 127 }, 4601 .vback_porch = { 23, 23, 23 }, 4602 .vsync_len = { 1, 1, 20 }, 4603 }; 4604 4605 static const struct panel_desc topland_tian_g07017_01 = { 4606 .timings = &topland_tian_g07017_01_timing, 4607 .num_timings = 1, 4608 .bpc = 8, 4609 .size = { 4610 .width = 154, 4611 .height = 86, 4612 }, 4613 .delay = { 4614 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 4615 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 4616 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 4617 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 4618 }, 4619 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4620 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4621 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4622 }; 4623 4624 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4625 .clock = 79500, 4626 .hdisplay = 1280, 4627 .hsync_start = 1280 + 192, 4628 .hsync_end = 1280 + 192 + 128, 4629 .htotal = 1280 + 192 + 128 + 64, 4630 .vdisplay = 768, 4631 .vsync_start = 768 + 20, 4632 .vsync_end = 768 + 20 + 7, 4633 .vtotal = 768 + 20 + 7 + 3, 4634 }; 4635 4636 static const struct panel_desc toshiba_lt089ac29000 = { 4637 .modes = &toshiba_lt089ac29000_mode, 4638 .num_modes = 1, 4639 .size = { 4640 .width = 194, 4641 .height = 116, 4642 }, 4643 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4644 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4645 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4646 }; 4647 4648 static const struct drm_display_mode tpk_f07a_0102_mode = { 4649 .clock = 33260, 4650 .hdisplay = 800, 4651 .hsync_start = 800 + 40, 4652 .hsync_end = 800 + 40 + 128, 4653 .htotal = 800 + 40 + 128 + 88, 4654 .vdisplay = 480, 4655 .vsync_start = 480 + 10, 4656 .vsync_end = 480 + 10 + 2, 4657 .vtotal = 480 + 10 + 2 + 33, 4658 }; 4659 4660 static const struct panel_desc tpk_f07a_0102 = { 4661 .modes = &tpk_f07a_0102_mode, 4662 .num_modes = 1, 4663 .size = { 4664 .width = 152, 4665 .height = 91, 4666 }, 4667 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4668 }; 4669 4670 static const struct drm_display_mode tpk_f10a_0102_mode = { 4671 .clock = 45000, 4672 .hdisplay = 1024, 4673 .hsync_start = 1024 + 176, 4674 .hsync_end = 1024 + 176 + 5, 4675 .htotal = 1024 + 176 + 5 + 88, 4676 .vdisplay = 600, 4677 .vsync_start = 600 + 20, 4678 .vsync_end = 600 + 20 + 5, 4679 .vtotal = 600 + 20 + 5 + 25, 4680 }; 4681 4682 static const struct panel_desc tpk_f10a_0102 = { 4683 .modes = &tpk_f10a_0102_mode, 4684 .num_modes = 1, 4685 .size = { 4686 .width = 223, 4687 .height = 125, 4688 }, 4689 }; 4690 4691 static const struct display_timing urt_umsh_8596md_timing = { 4692 .pixelclock = { 33260000, 33260000, 33260000 }, 4693 .hactive = { 800, 800, 800 }, 4694 .hfront_porch = { 41, 41, 41 }, 4695 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4696 .hsync_len = { 71, 128, 128 }, 4697 .vactive = { 480, 480, 480 }, 4698 .vfront_porch = { 10, 10, 10 }, 4699 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4700 .vsync_len = { 2, 2, 2 }, 4701 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4702 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4703 }; 4704 4705 static const struct panel_desc urt_umsh_8596md_lvds = { 4706 .timings = &urt_umsh_8596md_timing, 4707 .num_timings = 1, 4708 .bpc = 6, 4709 .size = { 4710 .width = 152, 4711 .height = 91, 4712 }, 4713 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4714 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4715 }; 4716 4717 static const struct panel_desc urt_umsh_8596md_parallel = { 4718 .timings = &urt_umsh_8596md_timing, 4719 .num_timings = 1, 4720 .bpc = 6, 4721 .size = { 4722 .width = 152, 4723 .height = 91, 4724 }, 4725 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4726 }; 4727 4728 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4729 .clock = 60000, 4730 .hdisplay = 1024, 4731 .hsync_start = 1024 + 160, 4732 .hsync_end = 1024 + 160 + 100, 4733 .htotal = 1024 + 160 + 100 + 60, 4734 .vdisplay = 600, 4735 .vsync_start = 600 + 12, 4736 .vsync_end = 600 + 12 + 10, 4737 .vtotal = 600 + 12 + 10 + 13, 4738 }; 4739 4740 static const struct panel_desc vivax_tpc9150_panel = { 4741 .modes = &vivax_tpc9150_panel_mode, 4742 .num_modes = 1, 4743 .bpc = 6, 4744 .size = { 4745 .width = 200, 4746 .height = 115, 4747 }, 4748 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4749 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4750 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4751 }; 4752 4753 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4754 .clock = 33333, 4755 .hdisplay = 800, 4756 .hsync_start = 800 + 210, 4757 .hsync_end = 800 + 210 + 20, 4758 .htotal = 800 + 210 + 20 + 46, 4759 .vdisplay = 480, 4760 .vsync_start = 480 + 22, 4761 .vsync_end = 480 + 22 + 10, 4762 .vtotal = 480 + 22 + 10 + 23, 4763 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4764 }; 4765 4766 static const struct panel_desc vl050_8048nt_c01 = { 4767 .modes = &vl050_8048nt_c01_mode, 4768 .num_modes = 1, 4769 .bpc = 8, 4770 .size = { 4771 .width = 120, 4772 .height = 76, 4773 }, 4774 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4775 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4776 }; 4777 4778 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4779 .clock = 6410, 4780 .hdisplay = 320, 4781 .hsync_start = 320 + 20, 4782 .hsync_end = 320 + 20 + 30, 4783 .htotal = 320 + 20 + 30 + 38, 4784 .vdisplay = 240, 4785 .vsync_start = 240 + 4, 4786 .vsync_end = 240 + 4 + 3, 4787 .vtotal = 240 + 4 + 3 + 15, 4788 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4789 }; 4790 4791 static const struct panel_desc winstar_wf35ltiacd = { 4792 .modes = &winstar_wf35ltiacd_mode, 4793 .num_modes = 1, 4794 .bpc = 8, 4795 .size = { 4796 .width = 70, 4797 .height = 53, 4798 }, 4799 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4800 }; 4801 4802 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4803 .clock = 51200, 4804 .hdisplay = 1024, 4805 .hsync_start = 1024 + 100, 4806 .hsync_end = 1024 + 100 + 100, 4807 .htotal = 1024 + 100 + 100 + 120, 4808 .vdisplay = 600, 4809 .vsync_start = 600 + 10, 4810 .vsync_end = 600 + 10 + 10, 4811 .vtotal = 600 + 10 + 10 + 15, 4812 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4813 }; 4814 4815 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4816 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4817 .num_modes = 1, 4818 .bpc = 8, 4819 .size = { 4820 .width = 154, 4821 .height = 90, 4822 }, 4823 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4824 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4825 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4826 }; 4827 4828 static const struct drm_display_mode mchp_ac69t88a_mode = { 4829 .clock = 25000, 4830 .hdisplay = 800, 4831 .hsync_start = 800 + 88, 4832 .hsync_end = 800 + 88 + 5, 4833 .htotal = 800 + 88 + 5 + 40, 4834 .vdisplay = 480, 4835 .vsync_start = 480 + 23, 4836 .vsync_end = 480 + 23 + 5, 4837 .vtotal = 480 + 23 + 5 + 1, 4838 }; 4839 4840 static const struct panel_desc mchp_ac69t88a = { 4841 .modes = &mchp_ac69t88a_mode, 4842 .num_modes = 1, 4843 .bpc = 8, 4844 .size = { 4845 .width = 108, 4846 .height = 65, 4847 }, 4848 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4849 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4850 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4851 }; 4852 4853 static const struct drm_display_mode arm_rtsm_mode[] = { 4854 { 4855 .clock = 65000, 4856 .hdisplay = 1024, 4857 .hsync_start = 1024 + 24, 4858 .hsync_end = 1024 + 24 + 136, 4859 .htotal = 1024 + 24 + 136 + 160, 4860 .vdisplay = 768, 4861 .vsync_start = 768 + 3, 4862 .vsync_end = 768 + 3 + 6, 4863 .vtotal = 768 + 3 + 6 + 29, 4864 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4865 }, 4866 }; 4867 4868 static const struct panel_desc arm_rtsm = { 4869 .modes = arm_rtsm_mode, 4870 .num_modes = 1, 4871 .bpc = 8, 4872 .size = { 4873 .width = 400, 4874 .height = 300, 4875 }, 4876 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4877 }; 4878 4879 static const struct of_device_id platform_of_match[] = { 4880 { 4881 .compatible = "ampire,am-1280800n3tzqw-t00h", 4882 .data = &ire_am_1280800n3tzqw_t00h, 4883 }, { 4884 .compatible = "ampire,am-480272h3tmqw-t01h", 4885 .data = &ire_am_480272h3tmqw_t01h, 4886 }, { 4887 .compatible = "ampire,am-800480l1tmqw-t00h", 4888 .data = &ire_am_800480l1tmqw_t00h, 4889 }, { 4890 .compatible = "ampire,am800480r3tmqwa1h", 4891 .data = &ire_am800480r3tmqwa1h, 4892 }, { 4893 .compatible = "ampire,am800600p5tmqw-tb8h", 4894 .data = &ire_am800600p5tmqwtb8h, 4895 }, { 4896 .compatible = "arm,rtsm-display", 4897 .data = &arm_rtsm, 4898 }, { 4899 .compatible = "armadeus,st0700-adapt", 4900 .data = &armadeus_st0700_adapt, 4901 }, { 4902 .compatible = "auo,b101aw03", 4903 .data = &auo_b101aw03, 4904 }, { 4905 .compatible = "auo,b101xtn01", 4906 .data = &auo_b101xtn01, 4907 }, { 4908 .compatible = "auo,b116xw03", 4909 .data = &auo_b116xw03, 4910 }, { 4911 .compatible = "auo,g070vvn01", 4912 .data = &auo_g070vvn01, 4913 }, { 4914 .compatible = "auo,g101evn010", 4915 .data = &auo_g101evn010, 4916 }, { 4917 .compatible = "auo,g104sn02", 4918 .data = &auo_g104sn02, 4919 }, { 4920 .compatible = "auo,g104stn01", 4921 .data = &auo_g104stn01, 4922 }, { 4923 .compatible = "auo,g121ean01", 4924 .data = &auo_g121ean01, 4925 }, { 4926 .compatible = "auo,g133han01", 4927 .data = &auo_g133han01, 4928 }, { 4929 .compatible = "auo,g156han04", 4930 .data = &auo_g156han04, 4931 }, { 4932 .compatible = "auo,g156xtn01", 4933 .data = &auo_g156xtn01, 4934 }, { 4935 .compatible = "auo,g185han01", 4936 .data = &auo_g185han01, 4937 }, { 4938 .compatible = "auo,g190ean01", 4939 .data = &auo_g190ean01, 4940 }, { 4941 .compatible = "auo,p320hvn03", 4942 .data = &auo_p320hvn03, 4943 }, { 4944 .compatible = "auo,t215hvn01", 4945 .data = &auo_t215hvn01, 4946 }, { 4947 .compatible = "avic,tm070ddh03", 4948 .data = &avic_tm070ddh03, 4949 }, { 4950 .compatible = "bananapi,s070wv20-ct16", 4951 .data = &bananapi_s070wv20_ct16, 4952 }, { 4953 .compatible = "boe,av101hdt-a10", 4954 .data = &boe_av101hdt_a10, 4955 }, { 4956 .compatible = "boe,av123z7m-n17", 4957 .data = &boe_av123z7m_n17, 4958 }, { 4959 .compatible = "boe,bp082wx1-100", 4960 .data = &boe_bp082wx1_100, 4961 }, { 4962 .compatible = "boe,bp101wx1-100", 4963 .data = &boe_bp101wx1_100, 4964 }, { 4965 .compatible = "boe,ev121wxm-n10-1850", 4966 .data = &boe_ev121wxm_n10_1850, 4967 }, { 4968 .compatible = "boe,hv070wsa-100", 4969 .data = &boe_hv070wsa 4970 }, { 4971 .compatible = "cct,cmt430b19n00", 4972 .data = &cct_cmt430b19n00, 4973 }, { 4974 .compatible = "cdtech,s043wq26h-ct7", 4975 .data = &cdtech_s043wq26h_ct7, 4976 }, { 4977 .compatible = "cdtech,s070pws19hp-fc21", 4978 .data = &cdtech_s070pws19hp_fc21, 4979 }, { 4980 .compatible = "cdtech,s070swv29hg-dc44", 4981 .data = &cdtech_s070swv29hg_dc44, 4982 }, { 4983 .compatible = "cdtech,s070wv95-ct16", 4984 .data = &cdtech_s070wv95_ct16, 4985 }, { 4986 .compatible = "chefree,ch101olhlwh-002", 4987 .data = &chefree_ch101olhlwh_002, 4988 }, { 4989 .compatible = "chunghwa,claa070wp03xg", 4990 .data = &chunghwa_claa070wp03xg, 4991 }, { 4992 .compatible = "chunghwa,claa101wa01a", 4993 .data = &chunghwa_claa101wa01a 4994 }, { 4995 .compatible = "chunghwa,claa101wb01", 4996 .data = &chunghwa_claa101wb01 4997 }, { 4998 .compatible = "dataimage,fg040346dsswbg04", 4999 .data = &dataimage_fg040346dsswbg04, 5000 }, { 5001 .compatible = "dataimage,fg1001l0dsswmg01", 5002 .data = &dataimage_fg1001l0dsswmg01, 5003 }, { 5004 .compatible = "dataimage,scf0700c48ggu18", 5005 .data = &dataimage_scf0700c48ggu18, 5006 }, { 5007 .compatible = "dlc,dlc0700yzg-1", 5008 .data = &dlc_dlc0700yzg_1, 5009 }, { 5010 .compatible = "dlc,dlc1010gig", 5011 .data = &dlc_dlc1010gig, 5012 }, { 5013 .compatible = "edt,et035012dm6", 5014 .data = &edt_et035012dm6, 5015 }, { 5016 .compatible = "edt,etm0350g0dh6", 5017 .data = &edt_etm0350g0dh6, 5018 }, { 5019 .compatible = "edt,etm043080dh6gp", 5020 .data = &edt_etm043080dh6gp, 5021 }, { 5022 .compatible = "edt,etm0430g0dh6", 5023 .data = &edt_etm0430g0dh6, 5024 }, { 5025 .compatible = "edt,et057090dhu", 5026 .data = &edt_et057090dhu, 5027 }, { 5028 .compatible = "edt,et070080dh6", 5029 .data = &edt_etm0700g0dh6, 5030 }, { 5031 .compatible = "edt,etm0700g0dh6", 5032 .data = &edt_etm0700g0dh6, 5033 }, { 5034 .compatible = "edt,etm0700g0bdh6", 5035 .data = &edt_etm0700g0bdh6, 5036 }, { 5037 .compatible = "edt,etm0700g0edh6", 5038 .data = &edt_etm0700g0bdh6, 5039 }, { 5040 .compatible = "edt,etml0700y5dha", 5041 .data = &edt_etml0700y5dha, 5042 }, { 5043 .compatible = "edt,etml1010g3dra", 5044 .data = &edt_etml1010g3dra, 5045 }, { 5046 .compatible = "edt,etmv570g2dhu", 5047 .data = &edt_etmv570g2dhu, 5048 }, { 5049 .compatible = "eink,vb3300-kca", 5050 .data = &eink_vb3300_kca, 5051 }, { 5052 .compatible = "evervision,vgg644804", 5053 .data = &evervision_vgg644804, 5054 }, { 5055 .compatible = "evervision,vgg804821", 5056 .data = &evervision_vgg804821, 5057 }, { 5058 .compatible = "foxlink,fl500wvr00-a0t", 5059 .data = &foxlink_fl500wvr00_a0t, 5060 }, { 5061 .compatible = "frida,frd350h54004", 5062 .data = &frida_frd350h54004, 5063 }, { 5064 .compatible = "friendlyarm,hd702e", 5065 .data = &friendlyarm_hd702e, 5066 }, { 5067 .compatible = "giantplus,gpg482739qs5", 5068 .data = &giantplus_gpg482739qs5 5069 }, { 5070 .compatible = "giantplus,gpm940b0", 5071 .data = &giantplus_gpm940b0, 5072 }, { 5073 .compatible = "hannstar,hsd070pww1", 5074 .data = &hannstar_hsd070pww1, 5075 }, { 5076 .compatible = "hannstar,hsd100pxn1", 5077 .data = &hannstar_hsd100pxn1, 5078 }, { 5079 .compatible = "hannstar,hsd101pww2", 5080 .data = &hannstar_hsd101pww2, 5081 }, { 5082 .compatible = "hit,tx23d38vm0caa", 5083 .data = &hitachi_tx23d38vm0caa 5084 }, { 5085 .compatible = "innolux,at043tn24", 5086 .data = &innolux_at043tn24, 5087 }, { 5088 .compatible = "innolux,at070tn92", 5089 .data = &innolux_at070tn92, 5090 }, { 5091 .compatible = "innolux,g070ace-l01", 5092 .data = &innolux_g070ace_l01, 5093 }, { 5094 .compatible = "innolux,g070ace-lh3", 5095 .data = &innolux_g070ace_lh3, 5096 }, { 5097 .compatible = "innolux,g070y2-l01", 5098 .data = &innolux_g070y2_l01, 5099 }, { 5100 .compatible = "innolux,g070y2-t02", 5101 .data = &innolux_g070y2_t02, 5102 }, { 5103 .compatible = "innolux,g101ice-l01", 5104 .data = &innolux_g101ice_l01 5105 }, { 5106 .compatible = "innolux,g121i1-l01", 5107 .data = &innolux_g121i1_l01 5108 }, { 5109 .compatible = "innolux,g121x1-l03", 5110 .data = &innolux_g121x1_l03, 5111 }, { 5112 .compatible = "innolux,g121xce-l01", 5113 .data = &innolux_g121xce_l01, 5114 }, { 5115 .compatible = "innolux,g156hce-l01", 5116 .data = &innolux_g156hce_l01, 5117 }, { 5118 .compatible = "innolux,n156bge-l21", 5119 .data = &innolux_n156bge_l21, 5120 }, { 5121 .compatible = "innolux,zj070na-01p", 5122 .data = &innolux_zj070na_01p, 5123 }, { 5124 .compatible = "koe,tx14d24vm1bpa", 5125 .data = &koe_tx14d24vm1bpa, 5126 }, { 5127 .compatible = "koe,tx26d202vm0bwa", 5128 .data = &koe_tx26d202vm0bwa, 5129 }, { 5130 .compatible = "koe,tx31d200vm0baa", 5131 .data = &koe_tx31d200vm0baa, 5132 }, { 5133 .compatible = "kyo,tcg121xglp", 5134 .data = &kyo_tcg121xglp, 5135 }, { 5136 .compatible = "lemaker,bl035-rgb-002", 5137 .data = &lemaker_bl035_rgb_002, 5138 }, { 5139 .compatible = "lg,lb070wv8", 5140 .data = &lg_lb070wv8, 5141 }, { 5142 .compatible = "lincolntech,lcd185-101ct", 5143 .data = &lincolntech_lcd185_101ct, 5144 }, { 5145 .compatible = "logicpd,type28", 5146 .data = &logicpd_type_28, 5147 }, { 5148 .compatible = "logictechno,lt161010-2nhc", 5149 .data = &logictechno_lt161010_2nh, 5150 }, { 5151 .compatible = "logictechno,lt161010-2nhr", 5152 .data = &logictechno_lt161010_2nh, 5153 }, { 5154 .compatible = "logictechno,lt170410-2whc", 5155 .data = &logictechno_lt170410_2whc, 5156 }, { 5157 .compatible = "logictechno,lttd800480070-l2rt", 5158 .data = &logictechno_lttd800480070_l2rt, 5159 }, { 5160 .compatible = "logictechno,lttd800480070-l6wh-rt", 5161 .data = &logictechno_lttd800480070_l6wh_rt, 5162 }, { 5163 .compatible = "microtips,mf-101hiebcaf0", 5164 .data = µtips_mf_101hiebcaf0_c, 5165 }, { 5166 .compatible = "microtips,mf-103hieb0ga0", 5167 .data = µtips_mf_103hieb0ga0, 5168 }, { 5169 .compatible = "mitsubishi,aa070mc01-ca1", 5170 .data = &mitsubishi_aa070mc01, 5171 }, { 5172 .compatible = "mitsubishi,aa084xe01", 5173 .data = &mitsubishi_aa084xe01, 5174 }, { 5175 .compatible = "multi-inno,mi0700a2t-30", 5176 .data = &multi_inno_mi0700a2t_30, 5177 }, { 5178 .compatible = "multi-inno,mi0700s4t-6", 5179 .data = &multi_inno_mi0700s4t_6, 5180 }, { 5181 .compatible = "multi-inno,mi0800ft-9", 5182 .data = &multi_inno_mi0800ft_9, 5183 }, { 5184 .compatible = "multi-inno,mi1010ait-1cp", 5185 .data = &multi_inno_mi1010ait_1cp, 5186 }, { 5187 .compatible = "multi-inno,mi1010z1t-1cp11", 5188 .data = &multi_inno_mi1010z1t_1cp11, 5189 }, { 5190 .compatible = "nec,nl12880bc20-05", 5191 .data = &nec_nl12880bc20_05, 5192 }, { 5193 .compatible = "nec,nl4827hc19-05b", 5194 .data = &nec_nl4827hc19_05b, 5195 }, { 5196 .compatible = "netron-dy,e231732", 5197 .data = &netron_dy_e231732, 5198 }, { 5199 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 5200 .data = &newhaven_nhd_43_480272ef_atxl, 5201 }, { 5202 .compatible = "nlt,nl13676bc25-03f", 5203 .data = &nlt_nl13676bc25_03f, 5204 }, { 5205 .compatible = "nlt,nl192108ac18-02d", 5206 .data = &nlt_nl192108ac18_02d, 5207 }, { 5208 .compatible = "nvd,9128", 5209 .data = &nvd_9128, 5210 }, { 5211 .compatible = "okaya,rs800480t-7x0gp", 5212 .data = &okaya_rs800480t_7x0gp, 5213 }, { 5214 .compatible = "olimex,lcd-olinuxino-43-ts", 5215 .data = &olimex_lcd_olinuxino_43ts, 5216 }, { 5217 .compatible = "ontat,kd50g21-40nt-a1", 5218 .data = &ontat_kd50g21_40nt_a1, 5219 }, { 5220 .compatible = "ontat,yx700wv03", 5221 .data = &ontat_yx700wv03, 5222 }, { 5223 .compatible = "ortustech,com37h3m05dtc", 5224 .data = &ortustech_com37h3m, 5225 }, { 5226 .compatible = "ortustech,com37h3m99dtc", 5227 .data = &ortustech_com37h3m, 5228 }, { 5229 .compatible = "ortustech,com43h4m85ulc", 5230 .data = &ortustech_com43h4m85ulc, 5231 }, { 5232 .compatible = "osddisplays,osd070t1718-19ts", 5233 .data = &osddisplays_osd070t1718_19ts, 5234 }, { 5235 .compatible = "pda,91-00156-a0", 5236 .data = &pda_91_00156_a0, 5237 }, { 5238 .compatible = "powertip,ph128800t004-zza01", 5239 .data = &powertip_ph128800t004_zza01, 5240 }, { 5241 .compatible = "powertip,ph128800t006-zhc01", 5242 .data = &powertip_ph128800t006_zhc01, 5243 }, { 5244 .compatible = "powertip,ph800480t013-idf02", 5245 .data = &powertip_ph800480t013_idf02, 5246 }, { 5247 .compatible = "primeview,pm070wl4", 5248 .data = &primeview_pm070wl4, 5249 }, { 5250 .compatible = "qiaodian,qd43003c0-40", 5251 .data = &qd43003c0_40, 5252 }, { 5253 .compatible = "qishenglong,gopher2b-lcd", 5254 .data = &qishenglong_gopher2b_lcd, 5255 }, { 5256 .compatible = "rocktech,rk043fn48h", 5257 .data = &rocktech_rk043fn48h, 5258 }, { 5259 .compatible = "rocktech,rk070er9427", 5260 .data = &rocktech_rk070er9427, 5261 }, { 5262 .compatible = "rocktech,rk101ii01d-ct", 5263 .data = &rocktech_rk101ii01d_ct, 5264 }, { 5265 .compatible = "samsung,ltl101al01", 5266 .data = &samsung_ltl101al01, 5267 }, { 5268 .compatible = "samsung,ltn101nt05", 5269 .data = &samsung_ltn101nt05, 5270 }, { 5271 .compatible = "satoz,sat050at40h12r2", 5272 .data = &satoz_sat050at40h12r2, 5273 }, { 5274 .compatible = "sharp,lq035q7db03", 5275 .data = &sharp_lq035q7db03, 5276 }, { 5277 .compatible = "sharp,lq070y3dg3b", 5278 .data = &sharp_lq070y3dg3b, 5279 }, { 5280 .compatible = "sharp,lq101k1ly04", 5281 .data = &sharp_lq101k1ly04, 5282 }, { 5283 .compatible = "sharp,ls020b1dd01d", 5284 .data = &sharp_ls020b1dd01d, 5285 }, { 5286 .compatible = "shelly,sca07010-bfn-lnn", 5287 .data = &shelly_sca07010_bfn_lnn, 5288 }, { 5289 .compatible = "starry,kr070pe2t", 5290 .data = &starry_kr070pe2t, 5291 }, { 5292 .compatible = "startek,kd070wvfpa", 5293 .data = &startek_kd070wvfpa, 5294 }, { 5295 .compatible = "team-source-display,tst043015cmhx", 5296 .data = &tsd_tst043015cmhx, 5297 }, { 5298 .compatible = "tfc,s9700rtwv43tr-01b", 5299 .data = &tfc_s9700rtwv43tr_01b, 5300 }, { 5301 .compatible = "tianma,p0700wxf1mbaa", 5302 .data = &tianma_p0700wxf1mbaa, 5303 }, { 5304 .compatible = "tianma,tm070jdhg30", 5305 .data = &tianma_tm070jdhg30, 5306 }, { 5307 .compatible = "tianma,tm070jdhg34-00", 5308 .data = &tianma_tm070jdhg34_00, 5309 }, { 5310 .compatible = "tianma,tm070jvhg33", 5311 .data = &tianma_tm070jvhg33, 5312 }, { 5313 .compatible = "tianma,tm070rvhg71", 5314 .data = &tianma_tm070rvhg71, 5315 }, { 5316 .compatible = "ti,nspire-cx-lcd-panel", 5317 .data = &ti_nspire_cx_lcd_panel, 5318 }, { 5319 .compatible = "ti,nspire-classic-lcd-panel", 5320 .data = &ti_nspire_classic_lcd_panel, 5321 }, { 5322 .compatible = "toshiba,lt089ac29000", 5323 .data = &toshiba_lt089ac29000, 5324 }, { 5325 .compatible = "topland,tian-g07017-01", 5326 .data = &topland_tian_g07017_01, 5327 }, { 5328 .compatible = "tpk,f07a-0102", 5329 .data = &tpk_f07a_0102, 5330 }, { 5331 .compatible = "tpk,f10a-0102", 5332 .data = &tpk_f10a_0102, 5333 }, { 5334 .compatible = "urt,umsh-8596md-t", 5335 .data = &urt_umsh_8596md_parallel, 5336 }, { 5337 .compatible = "urt,umsh-8596md-1t", 5338 .data = &urt_umsh_8596md_parallel, 5339 }, { 5340 .compatible = "urt,umsh-8596md-7t", 5341 .data = &urt_umsh_8596md_parallel, 5342 }, { 5343 .compatible = "urt,umsh-8596md-11t", 5344 .data = &urt_umsh_8596md_lvds, 5345 }, { 5346 .compatible = "urt,umsh-8596md-19t", 5347 .data = &urt_umsh_8596md_lvds, 5348 }, { 5349 .compatible = "urt,umsh-8596md-20t", 5350 .data = &urt_umsh_8596md_parallel, 5351 }, { 5352 .compatible = "vivax,tpc9150-panel", 5353 .data = &vivax_tpc9150_panel, 5354 }, { 5355 .compatible = "vxt,vl050-8048nt-c01", 5356 .data = &vl050_8048nt_c01, 5357 }, { 5358 .compatible = "winstar,wf35ltiacd", 5359 .data = &winstar_wf35ltiacd, 5360 }, { 5361 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 5362 .data = &yes_optoelectronics_ytc700tlag_05_201c, 5363 }, { 5364 .compatible = "microchip,ac69t88a", 5365 .data = &mchp_ac69t88a, 5366 }, { 5367 /* Must be the last entry */ 5368 .compatible = "panel-dpi", 5369 .data = &panel_dpi, 5370 }, { 5371 /* sentinel */ 5372 } 5373 }; 5374 MODULE_DEVICE_TABLE(of, platform_of_match); 5375 5376 static int panel_simple_platform_probe(struct platform_device *pdev) 5377 { 5378 const struct panel_desc *desc; 5379 5380 desc = of_device_get_match_data(&pdev->dev); 5381 if (!desc) 5382 return -ENODEV; 5383 5384 return panel_simple_probe(&pdev->dev, desc); 5385 } 5386 5387 static void panel_simple_platform_remove(struct platform_device *pdev) 5388 { 5389 panel_simple_remove(&pdev->dev); 5390 } 5391 5392 static void panel_simple_platform_shutdown(struct platform_device *pdev) 5393 { 5394 panel_simple_shutdown(&pdev->dev); 5395 } 5396 5397 static const struct dev_pm_ops panel_simple_pm_ops = { 5398 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 5399 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5400 pm_runtime_force_resume) 5401 }; 5402 5403 static struct platform_driver panel_simple_platform_driver = { 5404 .driver = { 5405 .name = "panel-simple", 5406 .of_match_table = platform_of_match, 5407 .pm = &panel_simple_pm_ops, 5408 }, 5409 .probe = panel_simple_platform_probe, 5410 .remove = panel_simple_platform_remove, 5411 .shutdown = panel_simple_platform_shutdown, 5412 }; 5413 5414 struct panel_desc_dsi { 5415 struct panel_desc desc; 5416 5417 unsigned long flags; 5418 enum mipi_dsi_pixel_format format; 5419 unsigned int lanes; 5420 }; 5421 5422 static const struct drm_display_mode auo_b080uan01_mode = { 5423 .clock = 154500, 5424 .hdisplay = 1200, 5425 .hsync_start = 1200 + 62, 5426 .hsync_end = 1200 + 62 + 4, 5427 .htotal = 1200 + 62 + 4 + 62, 5428 .vdisplay = 1920, 5429 .vsync_start = 1920 + 9, 5430 .vsync_end = 1920 + 9 + 2, 5431 .vtotal = 1920 + 9 + 2 + 8, 5432 }; 5433 5434 static const struct panel_desc_dsi auo_b080uan01 = { 5435 .desc = { 5436 .modes = &auo_b080uan01_mode, 5437 .num_modes = 1, 5438 .bpc = 8, 5439 .size = { 5440 .width = 108, 5441 .height = 272, 5442 }, 5443 .connector_type = DRM_MODE_CONNECTOR_DSI, 5444 }, 5445 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5446 .format = MIPI_DSI_FMT_RGB888, 5447 .lanes = 4, 5448 }; 5449 5450 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5451 .clock = 160000, 5452 .hdisplay = 1200, 5453 .hsync_start = 1200 + 120, 5454 .hsync_end = 1200 + 120 + 20, 5455 .htotal = 1200 + 120 + 20 + 21, 5456 .vdisplay = 1920, 5457 .vsync_start = 1920 + 21, 5458 .vsync_end = 1920 + 21 + 3, 5459 .vtotal = 1920 + 21 + 3 + 18, 5460 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5461 }; 5462 5463 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5464 .desc = { 5465 .modes = &boe_tv080wum_nl0_mode, 5466 .num_modes = 1, 5467 .size = { 5468 .width = 107, 5469 .height = 172, 5470 }, 5471 .connector_type = DRM_MODE_CONNECTOR_DSI, 5472 }, 5473 .flags = MIPI_DSI_MODE_VIDEO | 5474 MIPI_DSI_MODE_VIDEO_BURST | 5475 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5476 .format = MIPI_DSI_FMT_RGB888, 5477 .lanes = 4, 5478 }; 5479 5480 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 5481 .clock = 71000, 5482 .hdisplay = 800, 5483 .hsync_start = 800 + 32, 5484 .hsync_end = 800 + 32 + 1, 5485 .htotal = 800 + 32 + 1 + 57, 5486 .vdisplay = 1280, 5487 .vsync_start = 1280 + 28, 5488 .vsync_end = 1280 + 28 + 1, 5489 .vtotal = 1280 + 28 + 1 + 14, 5490 }; 5491 5492 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 5493 .desc = { 5494 .modes = &lg_ld070wx3_sl01_mode, 5495 .num_modes = 1, 5496 .bpc = 8, 5497 .size = { 5498 .width = 94, 5499 .height = 151, 5500 }, 5501 .connector_type = DRM_MODE_CONNECTOR_DSI, 5502 }, 5503 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5504 .format = MIPI_DSI_FMT_RGB888, 5505 .lanes = 4, 5506 }; 5507 5508 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5509 .clock = 67000, 5510 .hdisplay = 720, 5511 .hsync_start = 720 + 12, 5512 .hsync_end = 720 + 12 + 4, 5513 .htotal = 720 + 12 + 4 + 112, 5514 .vdisplay = 1280, 5515 .vsync_start = 1280 + 8, 5516 .vsync_end = 1280 + 8 + 4, 5517 .vtotal = 1280 + 8 + 4 + 12, 5518 }; 5519 5520 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5521 .desc = { 5522 .modes = &lg_lh500wx1_sd03_mode, 5523 .num_modes = 1, 5524 .bpc = 8, 5525 .size = { 5526 .width = 62, 5527 .height = 110, 5528 }, 5529 .connector_type = DRM_MODE_CONNECTOR_DSI, 5530 }, 5531 .flags = MIPI_DSI_MODE_VIDEO, 5532 .format = MIPI_DSI_FMT_RGB888, 5533 .lanes = 4, 5534 }; 5535 5536 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5537 .clock = 157200, 5538 .hdisplay = 1920, 5539 .hsync_start = 1920 + 154, 5540 .hsync_end = 1920 + 154 + 16, 5541 .htotal = 1920 + 154 + 16 + 32, 5542 .vdisplay = 1200, 5543 .vsync_start = 1200 + 17, 5544 .vsync_end = 1200 + 17 + 2, 5545 .vtotal = 1200 + 17 + 2 + 16, 5546 }; 5547 5548 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5549 .desc = { 5550 .modes = &panasonic_vvx10f004b00_mode, 5551 .num_modes = 1, 5552 .bpc = 8, 5553 .size = { 5554 .width = 217, 5555 .height = 136, 5556 }, 5557 .connector_type = DRM_MODE_CONNECTOR_DSI, 5558 }, 5559 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5560 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5561 .format = MIPI_DSI_FMT_RGB888, 5562 .lanes = 4, 5563 }; 5564 5565 static const struct drm_display_mode lg_acx467akm_7_mode = { 5566 .clock = 150000, 5567 .hdisplay = 1080, 5568 .hsync_start = 1080 + 2, 5569 .hsync_end = 1080 + 2 + 2, 5570 .htotal = 1080 + 2 + 2 + 2, 5571 .vdisplay = 1920, 5572 .vsync_start = 1920 + 2, 5573 .vsync_end = 1920 + 2 + 2, 5574 .vtotal = 1920 + 2 + 2 + 2, 5575 }; 5576 5577 static const struct panel_desc_dsi lg_acx467akm_7 = { 5578 .desc = { 5579 .modes = &lg_acx467akm_7_mode, 5580 .num_modes = 1, 5581 .bpc = 8, 5582 .size = { 5583 .width = 62, 5584 .height = 110, 5585 }, 5586 .connector_type = DRM_MODE_CONNECTOR_DSI, 5587 }, 5588 .flags = 0, 5589 .format = MIPI_DSI_FMT_RGB888, 5590 .lanes = 4, 5591 }; 5592 5593 static const struct drm_display_mode osd101t2045_53ts_mode = { 5594 .clock = 154500, 5595 .hdisplay = 1920, 5596 .hsync_start = 1920 + 112, 5597 .hsync_end = 1920 + 112 + 16, 5598 .htotal = 1920 + 112 + 16 + 32, 5599 .vdisplay = 1200, 5600 .vsync_start = 1200 + 16, 5601 .vsync_end = 1200 + 16 + 2, 5602 .vtotal = 1200 + 16 + 2 + 16, 5603 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5604 }; 5605 5606 static const struct panel_desc_dsi osd101t2045_53ts = { 5607 .desc = { 5608 .modes = &osd101t2045_53ts_mode, 5609 .num_modes = 1, 5610 .bpc = 8, 5611 .size = { 5612 .width = 217, 5613 .height = 136, 5614 }, 5615 .connector_type = DRM_MODE_CONNECTOR_DSI, 5616 }, 5617 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5618 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5619 MIPI_DSI_MODE_NO_EOT_PACKET, 5620 .format = MIPI_DSI_FMT_RGB888, 5621 .lanes = 4, 5622 }; 5623 5624 static const struct of_device_id dsi_of_match[] = { 5625 { 5626 .compatible = "auo,b080uan01", 5627 .data = &auo_b080uan01 5628 }, { 5629 .compatible = "boe,tv080wum-nl0", 5630 .data = &boe_tv080wum_nl0 5631 }, { 5632 .compatible = "lg,ld070wx3-sl01", 5633 .data = &lg_ld070wx3_sl01 5634 }, { 5635 .compatible = "lg,lh500wx1-sd03", 5636 .data = &lg_lh500wx1_sd03 5637 }, { 5638 .compatible = "panasonic,vvx10f004b00", 5639 .data = &panasonic_vvx10f004b00 5640 }, { 5641 .compatible = "lg,acx467akm-7", 5642 .data = &lg_acx467akm_7 5643 }, { 5644 .compatible = "osddisplays,osd101t2045-53ts", 5645 .data = &osd101t2045_53ts 5646 }, { 5647 /* sentinel */ 5648 } 5649 }; 5650 MODULE_DEVICE_TABLE(of, dsi_of_match); 5651 5652 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5653 { 5654 const struct panel_desc_dsi *desc; 5655 int err; 5656 5657 desc = of_device_get_match_data(&dsi->dev); 5658 if (!desc) 5659 return -ENODEV; 5660 5661 err = panel_simple_probe(&dsi->dev, &desc->desc); 5662 if (err < 0) 5663 return err; 5664 5665 dsi->mode_flags = desc->flags; 5666 dsi->format = desc->format; 5667 dsi->lanes = desc->lanes; 5668 5669 err = mipi_dsi_attach(dsi); 5670 if (err) { 5671 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5672 5673 drm_panel_remove(&panel->base); 5674 } 5675 5676 return err; 5677 } 5678 5679 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5680 { 5681 int err; 5682 5683 err = mipi_dsi_detach(dsi); 5684 if (err < 0) 5685 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5686 5687 panel_simple_remove(&dsi->dev); 5688 } 5689 5690 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5691 { 5692 panel_simple_shutdown(&dsi->dev); 5693 } 5694 5695 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5696 .driver = { 5697 .name = "panel-simple-dsi", 5698 .of_match_table = dsi_of_match, 5699 .pm = &panel_simple_pm_ops, 5700 }, 5701 .probe = panel_simple_dsi_probe, 5702 .remove = panel_simple_dsi_remove, 5703 .shutdown = panel_simple_dsi_shutdown, 5704 }; 5705 5706 static int __init panel_simple_init(void) 5707 { 5708 int err; 5709 5710 err = platform_driver_register(&panel_simple_platform_driver); 5711 if (err < 0) 5712 return err; 5713 5714 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5715 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5716 if (err < 0) 5717 goto err_did_platform_register; 5718 } 5719 5720 return 0; 5721 5722 err_did_platform_register: 5723 platform_driver_unregister(&panel_simple_platform_driver); 5724 5725 return err; 5726 } 5727 module_init(panel_simple_init); 5728 5729 static void __exit panel_simple_exit(void) 5730 { 5731 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5732 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5733 5734 platform_driver_unregister(&panel_simple_platform_driver); 5735 } 5736 module_exit(panel_simple_exit); 5737 5738 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5739 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5740 MODULE_LICENSE("GPL and additional rights"); 5741