1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 bool enabled; 142 143 bool prepared; 144 145 ktime_t unprepared_time; 146 147 const struct panel_desc *desc; 148 149 struct regulator *supply; 150 struct i2c_adapter *ddc; 151 152 struct gpio_desc *enable_gpio; 153 154 struct edid *edid; 155 156 struct drm_display_mode override_mode; 157 158 enum drm_panel_orientation orientation; 159 }; 160 161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 162 { 163 return container_of(panel, struct panel_simple, base); 164 } 165 166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 167 struct drm_connector *connector) 168 { 169 struct drm_display_mode *mode; 170 unsigned int i, num = 0; 171 172 for (i = 0; i < panel->desc->num_timings; i++) { 173 const struct display_timing *dt = &panel->desc->timings[i]; 174 struct videomode vm; 175 176 videomode_from_timing(dt, &vm); 177 mode = drm_mode_create(connector->dev); 178 if (!mode) { 179 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 180 dt->hactive.typ, dt->vactive.typ); 181 continue; 182 } 183 184 drm_display_mode_from_videomode(&vm, mode); 185 186 mode->type |= DRM_MODE_TYPE_DRIVER; 187 188 if (panel->desc->num_timings == 1) 189 mode->type |= DRM_MODE_TYPE_PREFERRED; 190 191 drm_mode_probed_add(connector, mode); 192 num++; 193 } 194 195 return num; 196 } 197 198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 199 struct drm_connector *connector) 200 { 201 struct drm_display_mode *mode; 202 unsigned int i, num = 0; 203 204 for (i = 0; i < panel->desc->num_modes; i++) { 205 const struct drm_display_mode *m = &panel->desc->modes[i]; 206 207 mode = drm_mode_duplicate(connector->dev, m); 208 if (!mode) { 209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 210 m->hdisplay, m->vdisplay, 211 drm_mode_vrefresh(m)); 212 continue; 213 } 214 215 mode->type |= DRM_MODE_TYPE_DRIVER; 216 217 if (panel->desc->num_modes == 1) 218 mode->type |= DRM_MODE_TYPE_PREFERRED; 219 220 drm_mode_set_name(mode); 221 222 drm_mode_probed_add(connector, mode); 223 num++; 224 } 225 226 return num; 227 } 228 229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 230 struct drm_connector *connector) 231 { 232 struct drm_display_mode *mode; 233 bool has_override = panel->override_mode.type; 234 unsigned int num = 0; 235 236 if (!panel->desc) 237 return 0; 238 239 if (has_override) { 240 mode = drm_mode_duplicate(connector->dev, 241 &panel->override_mode); 242 if (mode) { 243 drm_mode_probed_add(connector, mode); 244 num = 1; 245 } else { 246 dev_err(panel->base.dev, "failed to add override mode\n"); 247 } 248 } 249 250 /* Only add timings if override was not there or failed to validate */ 251 if (num == 0 && panel->desc->num_timings) 252 num = panel_simple_get_timings_modes(panel, connector); 253 254 /* 255 * Only add fixed modes if timings/override added no mode. 256 * 257 * We should only ever have either the display timings specified 258 * or a fixed mode. Anything else is rather bogus. 259 */ 260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 261 if (num == 0) 262 num = panel_simple_get_display_modes(panel, connector); 263 264 connector->display_info.bpc = panel->desc->bpc; 265 connector->display_info.width_mm = panel->desc->size.width; 266 connector->display_info.height_mm = panel->desc->size.height; 267 if (panel->desc->bus_format) 268 drm_display_info_set_bus_formats(&connector->display_info, 269 &panel->desc->bus_format, 1); 270 connector->display_info.bus_flags = panel->desc->bus_flags; 271 272 return num; 273 } 274 275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 276 { 277 ktime_t now_ktime, min_ktime; 278 279 if (!min_ms) 280 return; 281 282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 283 now_ktime = ktime_get_boottime(); 284 285 if (ktime_before(now_ktime, min_ktime)) 286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 287 } 288 289 static int panel_simple_disable(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 293 if (!p->enabled) 294 return 0; 295 296 if (p->desc->delay.disable) 297 msleep(p->desc->delay.disable); 298 299 p->enabled = false; 300 301 return 0; 302 } 303 304 static int panel_simple_suspend(struct device *dev) 305 { 306 struct panel_simple *p = dev_get_drvdata(dev); 307 308 gpiod_set_value_cansleep(p->enable_gpio, 0); 309 regulator_disable(p->supply); 310 p->unprepared_time = ktime_get_boottime(); 311 312 kfree(p->edid); 313 p->edid = NULL; 314 315 return 0; 316 } 317 318 static int panel_simple_unprepare(struct drm_panel *panel) 319 { 320 struct panel_simple *p = to_panel_simple(panel); 321 int ret; 322 323 /* Unpreparing when already unprepared is a no-op */ 324 if (!p->prepared) 325 return 0; 326 327 pm_runtime_mark_last_busy(panel->dev); 328 ret = pm_runtime_put_autosuspend(panel->dev); 329 if (ret < 0) 330 return ret; 331 p->prepared = false; 332 333 return 0; 334 } 335 336 static int panel_simple_resume(struct device *dev) 337 { 338 struct panel_simple *p = dev_get_drvdata(dev); 339 int err; 340 341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 342 343 err = regulator_enable(p->supply); 344 if (err < 0) { 345 dev_err(dev, "failed to enable supply: %d\n", err); 346 return err; 347 } 348 349 gpiod_set_value_cansleep(p->enable_gpio, 1); 350 351 if (p->desc->delay.prepare) 352 msleep(p->desc->delay.prepare); 353 354 return 0; 355 } 356 357 static int panel_simple_prepare(struct drm_panel *panel) 358 { 359 struct panel_simple *p = to_panel_simple(panel); 360 int ret; 361 362 /* Preparing when already prepared is a no-op */ 363 if (p->prepared) 364 return 0; 365 366 ret = pm_runtime_get_sync(panel->dev); 367 if (ret < 0) { 368 pm_runtime_put_autosuspend(panel->dev); 369 return ret; 370 } 371 372 p->prepared = true; 373 374 return 0; 375 } 376 377 static int panel_simple_enable(struct drm_panel *panel) 378 { 379 struct panel_simple *p = to_panel_simple(panel); 380 381 if (p->enabled) 382 return 0; 383 384 if (p->desc->delay.enable) 385 msleep(p->desc->delay.enable); 386 387 p->enabled = true; 388 389 return 0; 390 } 391 392 static int panel_simple_get_modes(struct drm_panel *panel, 393 struct drm_connector *connector) 394 { 395 struct panel_simple *p = to_panel_simple(panel); 396 int num = 0; 397 398 /* probe EDID if a DDC bus is available */ 399 if (p->ddc) { 400 pm_runtime_get_sync(panel->dev); 401 402 if (!p->edid) 403 p->edid = drm_get_edid(connector, p->ddc); 404 405 if (p->edid) 406 num += drm_add_edid_modes(connector, p->edid); 407 408 pm_runtime_mark_last_busy(panel->dev); 409 pm_runtime_put_autosuspend(panel->dev); 410 } 411 412 /* add hard-coded panel modes */ 413 num += panel_simple_get_non_edid_modes(p, connector); 414 415 /* 416 * TODO: Remove once all drm drivers call 417 * drm_connector_set_orientation_from_panel() 418 */ 419 drm_connector_set_panel_orientation(connector, p->orientation); 420 421 return num; 422 } 423 424 static int panel_simple_get_timings(struct drm_panel *panel, 425 unsigned int num_timings, 426 struct display_timing *timings) 427 { 428 struct panel_simple *p = to_panel_simple(panel); 429 unsigned int i; 430 431 if (p->desc->num_timings < num_timings) 432 num_timings = p->desc->num_timings; 433 434 if (timings) 435 for (i = 0; i < num_timings; i++) 436 timings[i] = p->desc->timings[i]; 437 438 return p->desc->num_timings; 439 } 440 441 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 442 { 443 struct panel_simple *p = to_panel_simple(panel); 444 445 return p->orientation; 446 } 447 448 static const struct drm_panel_funcs panel_simple_funcs = { 449 .disable = panel_simple_disable, 450 .unprepare = panel_simple_unprepare, 451 .prepare = panel_simple_prepare, 452 .enable = panel_simple_enable, 453 .get_modes = panel_simple_get_modes, 454 .get_orientation = panel_simple_get_orientation, 455 .get_timings = panel_simple_get_timings, 456 }; 457 458 static struct panel_desc panel_dpi; 459 460 static int panel_dpi_probe(struct device *dev, 461 struct panel_simple *panel) 462 { 463 struct display_timing *timing; 464 const struct device_node *np; 465 struct panel_desc *desc; 466 unsigned int bus_flags; 467 struct videomode vm; 468 int ret; 469 470 np = dev->of_node; 471 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 472 if (!desc) 473 return -ENOMEM; 474 475 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 476 if (!timing) 477 return -ENOMEM; 478 479 ret = of_get_display_timing(np, "panel-timing", timing); 480 if (ret < 0) { 481 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 482 np); 483 return ret; 484 } 485 486 desc->timings = timing; 487 desc->num_timings = 1; 488 489 of_property_read_u32(np, "width-mm", &desc->size.width); 490 of_property_read_u32(np, "height-mm", &desc->size.height); 491 492 /* Extract bus_flags from display_timing */ 493 bus_flags = 0; 494 vm.flags = timing->flags; 495 drm_bus_flags_from_videomode(&vm, &bus_flags); 496 desc->bus_flags = bus_flags; 497 498 /* We do not know the connector for the DT node, so guess it */ 499 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 500 501 panel->desc = desc; 502 503 return 0; 504 } 505 506 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 507 (to_check->field.typ >= bounds->field.min && \ 508 to_check->field.typ <= bounds->field.max) 509 static void panel_simple_parse_panel_timing_node(struct device *dev, 510 struct panel_simple *panel, 511 const struct display_timing *ot) 512 { 513 const struct panel_desc *desc = panel->desc; 514 struct videomode vm; 515 unsigned int i; 516 517 if (WARN_ON(desc->num_modes)) { 518 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 519 return; 520 } 521 if (WARN_ON(!desc->num_timings)) { 522 dev_err(dev, "Reject override mode: no timings specified\n"); 523 return; 524 } 525 526 for (i = 0; i < panel->desc->num_timings; i++) { 527 const struct display_timing *dt = &panel->desc->timings[i]; 528 529 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 537 continue; 538 539 if (ot->flags != dt->flags) 540 continue; 541 542 videomode_from_timing(ot, &vm); 543 drm_display_mode_from_videomode(&vm, &panel->override_mode); 544 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 545 DRM_MODE_TYPE_PREFERRED; 546 break; 547 } 548 549 if (WARN_ON(!panel->override_mode.type)) 550 dev_err(dev, "Reject override mode: No display_timing found\n"); 551 } 552 553 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 554 struct panel_simple *panel) 555 { 556 int ret, bpc; 557 558 ret = drm_of_lvds_get_data_mapping(dev->of_node); 559 if (ret < 0) { 560 if (ret == -EINVAL) 561 dev_warn(dev, "Ignore invalid data-mapping property\n"); 562 563 /* 564 * Ignore non-existing or malformatted property, fallback to 565 * default data-mapping, and return 0. 566 */ 567 return 0; 568 } 569 570 switch (ret) { 571 default: 572 WARN_ON(1); 573 fallthrough; 574 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 575 fallthrough; 576 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 577 bpc = 8; 578 break; 579 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 580 bpc = 6; 581 } 582 583 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 584 struct panel_desc *override_desc; 585 586 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 587 if (!override_desc) 588 return -ENOMEM; 589 590 override_desc->bus_format = ret; 591 override_desc->bpc = bpc; 592 panel->desc = override_desc; 593 } 594 595 return 0; 596 } 597 598 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 599 { 600 struct panel_simple *panel; 601 struct display_timing dt; 602 struct device_node *ddc; 603 int connector_type; 604 u32 bus_flags; 605 int err; 606 607 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 608 if (!panel) 609 return -ENOMEM; 610 611 panel->enabled = false; 612 panel->desc = desc; 613 614 panel->supply = devm_regulator_get(dev, "power"); 615 if (IS_ERR(panel->supply)) 616 return PTR_ERR(panel->supply); 617 618 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 619 GPIOD_OUT_LOW); 620 if (IS_ERR(panel->enable_gpio)) 621 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 622 "failed to request GPIO\n"); 623 624 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 625 if (err) { 626 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 627 return err; 628 } 629 630 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 631 if (ddc) { 632 panel->ddc = of_find_i2c_adapter_by_node(ddc); 633 of_node_put(ddc); 634 635 if (!panel->ddc) 636 return -EPROBE_DEFER; 637 } 638 639 if (desc == &panel_dpi) { 640 /* Handle the generic panel-dpi binding */ 641 err = panel_dpi_probe(dev, panel); 642 if (err) 643 goto free_ddc; 644 desc = panel->desc; 645 } else { 646 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 647 panel_simple_parse_panel_timing_node(dev, panel, &dt); 648 } 649 650 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 651 /* Optional data-mapping property for overriding bus format */ 652 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 653 if (err) 654 goto free_ddc; 655 } 656 657 connector_type = desc->connector_type; 658 /* Catch common mistakes for panels. */ 659 switch (connector_type) { 660 case 0: 661 dev_warn(dev, "Specify missing connector_type\n"); 662 connector_type = DRM_MODE_CONNECTOR_DPI; 663 break; 664 case DRM_MODE_CONNECTOR_LVDS: 665 WARN_ON(desc->bus_flags & 666 ~(DRM_BUS_FLAG_DE_LOW | 667 DRM_BUS_FLAG_DE_HIGH | 668 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 669 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 670 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 671 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 672 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 673 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 674 desc->bpc != 6); 675 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 676 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 677 desc->bpc != 8); 678 break; 679 case DRM_MODE_CONNECTOR_eDP: 680 dev_warn(dev, "eDP panels moved to panel-edp\n"); 681 err = -EINVAL; 682 goto free_ddc; 683 case DRM_MODE_CONNECTOR_DSI: 684 if (desc->bpc != 6 && desc->bpc != 8) 685 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 686 break; 687 case DRM_MODE_CONNECTOR_DPI: 688 bus_flags = DRM_BUS_FLAG_DE_LOW | 689 DRM_BUS_FLAG_DE_HIGH | 690 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 691 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 692 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 693 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 694 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 695 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 696 if (desc->bus_flags & ~bus_flags) 697 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 698 if (!(desc->bus_flags & bus_flags)) 699 dev_warn(dev, "Specify missing bus_flags\n"); 700 if (desc->bus_format == 0) 701 dev_warn(dev, "Specify missing bus_format\n"); 702 if (desc->bpc != 6 && desc->bpc != 8) 703 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 704 break; 705 default: 706 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 707 connector_type = DRM_MODE_CONNECTOR_DPI; 708 break; 709 } 710 711 dev_set_drvdata(dev, panel); 712 713 /* 714 * We use runtime PM for prepare / unprepare since those power the panel 715 * on and off and those can be very slow operations. This is important 716 * to optimize powering the panel on briefly to read the EDID before 717 * fully enabling the panel. 718 */ 719 pm_runtime_enable(dev); 720 pm_runtime_set_autosuspend_delay(dev, 1000); 721 pm_runtime_use_autosuspend(dev); 722 723 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 724 725 err = drm_panel_of_backlight(&panel->base); 726 if (err) { 727 dev_err_probe(dev, err, "Could not find backlight\n"); 728 goto disable_pm_runtime; 729 } 730 731 drm_panel_add(&panel->base); 732 733 return 0; 734 735 disable_pm_runtime: 736 pm_runtime_dont_use_autosuspend(dev); 737 pm_runtime_disable(dev); 738 free_ddc: 739 if (panel->ddc) 740 put_device(&panel->ddc->dev); 741 742 return err; 743 } 744 745 static void panel_simple_remove(struct device *dev) 746 { 747 struct panel_simple *panel = dev_get_drvdata(dev); 748 749 drm_panel_remove(&panel->base); 750 drm_panel_disable(&panel->base); 751 drm_panel_unprepare(&panel->base); 752 753 pm_runtime_dont_use_autosuspend(dev); 754 pm_runtime_disable(dev); 755 if (panel->ddc) 756 put_device(&panel->ddc->dev); 757 } 758 759 static void panel_simple_shutdown(struct device *dev) 760 { 761 struct panel_simple *panel = dev_get_drvdata(dev); 762 763 drm_panel_disable(&panel->base); 764 drm_panel_unprepare(&panel->base); 765 } 766 767 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 768 .clock = 71100, 769 .hdisplay = 1280, 770 .hsync_start = 1280 + 40, 771 .hsync_end = 1280 + 40 + 80, 772 .htotal = 1280 + 40 + 80 + 40, 773 .vdisplay = 800, 774 .vsync_start = 800 + 3, 775 .vsync_end = 800 + 3 + 10, 776 .vtotal = 800 + 3 + 10 + 10, 777 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 778 }; 779 780 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 781 .modes = &ire_am_1280800n3tzqw_t00h_mode, 782 .num_modes = 1, 783 .bpc = 8, 784 .size = { 785 .width = 217, 786 .height = 136, 787 }, 788 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 789 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 790 .connector_type = DRM_MODE_CONNECTOR_LVDS, 791 }; 792 793 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 794 .clock = 9000, 795 .hdisplay = 480, 796 .hsync_start = 480 + 2, 797 .hsync_end = 480 + 2 + 41, 798 .htotal = 480 + 2 + 41 + 2, 799 .vdisplay = 272, 800 .vsync_start = 272 + 2, 801 .vsync_end = 272 + 2 + 10, 802 .vtotal = 272 + 2 + 10 + 2, 803 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 804 }; 805 806 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 807 .modes = &ire_am_480272h3tmqw_t01h_mode, 808 .num_modes = 1, 809 .bpc = 8, 810 .size = { 811 .width = 99, 812 .height = 58, 813 }, 814 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 815 }; 816 817 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 818 .clock = 33333, 819 .hdisplay = 800, 820 .hsync_start = 800 + 0, 821 .hsync_end = 800 + 0 + 255, 822 .htotal = 800 + 0 + 255 + 0, 823 .vdisplay = 480, 824 .vsync_start = 480 + 2, 825 .vsync_end = 480 + 2 + 45, 826 .vtotal = 480 + 2 + 45 + 0, 827 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 828 }; 829 830 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 831 .pixelclock = { 29930000, 33260000, 36590000 }, 832 .hactive = { 800, 800, 800 }, 833 .hfront_porch = { 1, 40, 168 }, 834 .hback_porch = { 88, 88, 88 }, 835 .hsync_len = { 1, 128, 128 }, 836 .vactive = { 480, 480, 480 }, 837 .vfront_porch = { 1, 35, 37 }, 838 .vback_porch = { 8, 8, 8 }, 839 .vsync_len = { 1, 2, 2 }, 840 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 841 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 842 DISPLAY_FLAGS_SYNC_POSEDGE, 843 }; 844 845 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 846 .timings = &ire_am_800480l1tmqw_t00h_timing, 847 .num_timings = 1, 848 .bpc = 8, 849 .size = { 850 .width = 111, 851 .height = 67, 852 }, 853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 854 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 855 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 856 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 857 .connector_type = DRM_MODE_CONNECTOR_DPI, 858 }; 859 860 static const struct panel_desc ampire_am800480r3tmqwa1h = { 861 .modes = &ire_am800480r3tmqwa1h_mode, 862 .num_modes = 1, 863 .bpc = 6, 864 .size = { 865 .width = 152, 866 .height = 91, 867 }, 868 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 869 }; 870 871 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 872 .pixelclock = { 34500000, 39600000, 50400000 }, 873 .hactive = { 800, 800, 800 }, 874 .hfront_porch = { 12, 112, 312 }, 875 .hback_porch = { 87, 87, 48 }, 876 .hsync_len = { 1, 1, 40 }, 877 .vactive = { 600, 600, 600 }, 878 .vfront_porch = { 1, 21, 61 }, 879 .vback_porch = { 38, 38, 19 }, 880 .vsync_len = { 1, 1, 20 }, 881 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 882 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 883 DISPLAY_FLAGS_SYNC_POSEDGE, 884 }; 885 886 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 887 .timings = &ire_am800600p5tmqw_tb8h_timing, 888 .num_timings = 1, 889 .bpc = 6, 890 .size = { 891 .width = 162, 892 .height = 122, 893 }, 894 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 895 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 896 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 897 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 898 .connector_type = DRM_MODE_CONNECTOR_DPI, 899 }; 900 901 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 902 .pixelclock = { 26400000, 33300000, 46800000 }, 903 .hactive = { 800, 800, 800 }, 904 .hfront_porch = { 16, 210, 354 }, 905 .hback_porch = { 45, 36, 6 }, 906 .hsync_len = { 1, 10, 40 }, 907 .vactive = { 480, 480, 480 }, 908 .vfront_porch = { 7, 22, 147 }, 909 .vback_porch = { 22, 13, 3 }, 910 .vsync_len = { 1, 10, 20 }, 911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 913 }; 914 915 static const struct panel_desc armadeus_st0700_adapt = { 916 .timings = &santek_st0700i5y_rbslw_f_timing, 917 .num_timings = 1, 918 .bpc = 6, 919 .size = { 920 .width = 154, 921 .height = 86, 922 }, 923 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 924 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 925 }; 926 927 static const struct drm_display_mode auo_b101aw03_mode = { 928 .clock = 51450, 929 .hdisplay = 1024, 930 .hsync_start = 1024 + 156, 931 .hsync_end = 1024 + 156 + 8, 932 .htotal = 1024 + 156 + 8 + 156, 933 .vdisplay = 600, 934 .vsync_start = 600 + 16, 935 .vsync_end = 600 + 16 + 6, 936 .vtotal = 600 + 16 + 6 + 16, 937 }; 938 939 static const struct panel_desc auo_b101aw03 = { 940 .modes = &auo_b101aw03_mode, 941 .num_modes = 1, 942 .bpc = 6, 943 .size = { 944 .width = 223, 945 .height = 125, 946 }, 947 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 948 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 949 .connector_type = DRM_MODE_CONNECTOR_LVDS, 950 }; 951 952 static const struct drm_display_mode auo_b101xtn01_mode = { 953 .clock = 72000, 954 .hdisplay = 1366, 955 .hsync_start = 1366 + 20, 956 .hsync_end = 1366 + 20 + 70, 957 .htotal = 1366 + 20 + 70, 958 .vdisplay = 768, 959 .vsync_start = 768 + 14, 960 .vsync_end = 768 + 14 + 42, 961 .vtotal = 768 + 14 + 42, 962 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 963 }; 964 965 static const struct panel_desc auo_b101xtn01 = { 966 .modes = &auo_b101xtn01_mode, 967 .num_modes = 1, 968 .bpc = 6, 969 .size = { 970 .width = 223, 971 .height = 125, 972 }, 973 }; 974 975 static const struct drm_display_mode auo_b116xw03_mode = { 976 .clock = 70589, 977 .hdisplay = 1366, 978 .hsync_start = 1366 + 40, 979 .hsync_end = 1366 + 40 + 40, 980 .htotal = 1366 + 40 + 40 + 32, 981 .vdisplay = 768, 982 .vsync_start = 768 + 10, 983 .vsync_end = 768 + 10 + 12, 984 .vtotal = 768 + 10 + 12 + 6, 985 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 986 }; 987 988 static const struct panel_desc auo_b116xw03 = { 989 .modes = &auo_b116xw03_mode, 990 .num_modes = 1, 991 .bpc = 6, 992 .size = { 993 .width = 256, 994 .height = 144, 995 }, 996 .delay = { 997 .prepare = 1, 998 .enable = 200, 999 .disable = 200, 1000 .unprepare = 500, 1001 }, 1002 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1003 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1004 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1005 }; 1006 1007 static const struct display_timing auo_g070vvn01_timings = { 1008 .pixelclock = { 33300000, 34209000, 45000000 }, 1009 .hactive = { 800, 800, 800 }, 1010 .hfront_porch = { 20, 40, 200 }, 1011 .hback_porch = { 87, 40, 1 }, 1012 .hsync_len = { 1, 48, 87 }, 1013 .vactive = { 480, 480, 480 }, 1014 .vfront_porch = { 5, 13, 200 }, 1015 .vback_porch = { 31, 31, 29 }, 1016 .vsync_len = { 1, 1, 3 }, 1017 }; 1018 1019 static const struct panel_desc auo_g070vvn01 = { 1020 .timings = &auo_g070vvn01_timings, 1021 .num_timings = 1, 1022 .bpc = 8, 1023 .size = { 1024 .width = 152, 1025 .height = 91, 1026 }, 1027 .delay = { 1028 .prepare = 200, 1029 .enable = 50, 1030 .disable = 50, 1031 .unprepare = 1000, 1032 }, 1033 }; 1034 1035 static const struct drm_display_mode auo_g101evn010_mode = { 1036 .clock = 68930, 1037 .hdisplay = 1280, 1038 .hsync_start = 1280 + 82, 1039 .hsync_end = 1280 + 82 + 2, 1040 .htotal = 1280 + 82 + 2 + 84, 1041 .vdisplay = 800, 1042 .vsync_start = 800 + 8, 1043 .vsync_end = 800 + 8 + 2, 1044 .vtotal = 800 + 8 + 2 + 6, 1045 }; 1046 1047 static const struct panel_desc auo_g101evn010 = { 1048 .modes = &auo_g101evn010_mode, 1049 .num_modes = 1, 1050 .bpc = 6, 1051 .size = { 1052 .width = 216, 1053 .height = 135, 1054 }, 1055 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1056 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1057 }; 1058 1059 static const struct drm_display_mode auo_g104sn02_mode = { 1060 .clock = 40000, 1061 .hdisplay = 800, 1062 .hsync_start = 800 + 40, 1063 .hsync_end = 800 + 40 + 216, 1064 .htotal = 800 + 40 + 216 + 128, 1065 .vdisplay = 600, 1066 .vsync_start = 600 + 10, 1067 .vsync_end = 600 + 10 + 35, 1068 .vtotal = 600 + 10 + 35 + 2, 1069 }; 1070 1071 static const struct panel_desc auo_g104sn02 = { 1072 .modes = &auo_g104sn02_mode, 1073 .num_modes = 1, 1074 .bpc = 8, 1075 .size = { 1076 .width = 211, 1077 .height = 158, 1078 }, 1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1080 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1081 }; 1082 1083 static const struct display_timing auo_g121ean01_timing = { 1084 .pixelclock = { 60000000, 74400000, 90000000 }, 1085 .hactive = { 1280, 1280, 1280 }, 1086 .hfront_porch = { 20, 50, 100 }, 1087 .hback_porch = { 20, 50, 100 }, 1088 .hsync_len = { 30, 100, 200 }, 1089 .vactive = { 800, 800, 800 }, 1090 .vfront_porch = { 2, 10, 25 }, 1091 .vback_porch = { 2, 10, 25 }, 1092 .vsync_len = { 4, 18, 50 }, 1093 }; 1094 1095 static const struct panel_desc auo_g121ean01 = { 1096 .timings = &auo_g121ean01_timing, 1097 .num_timings = 1, 1098 .bpc = 8, 1099 .size = { 1100 .width = 261, 1101 .height = 163, 1102 }, 1103 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1104 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1105 }; 1106 1107 static const struct display_timing auo_g133han01_timings = { 1108 .pixelclock = { 134000000, 141200000, 149000000 }, 1109 .hactive = { 1920, 1920, 1920 }, 1110 .hfront_porch = { 39, 58, 77 }, 1111 .hback_porch = { 59, 88, 117 }, 1112 .hsync_len = { 28, 42, 56 }, 1113 .vactive = { 1080, 1080, 1080 }, 1114 .vfront_porch = { 3, 8, 11 }, 1115 .vback_porch = { 5, 14, 19 }, 1116 .vsync_len = { 4, 14, 19 }, 1117 }; 1118 1119 static const struct panel_desc auo_g133han01 = { 1120 .timings = &auo_g133han01_timings, 1121 .num_timings = 1, 1122 .bpc = 8, 1123 .size = { 1124 .width = 293, 1125 .height = 165, 1126 }, 1127 .delay = { 1128 .prepare = 200, 1129 .enable = 50, 1130 .disable = 50, 1131 .unprepare = 1000, 1132 }, 1133 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1134 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1135 }; 1136 1137 static const struct drm_display_mode auo_g156xtn01_mode = { 1138 .clock = 76000, 1139 .hdisplay = 1366, 1140 .hsync_start = 1366 + 33, 1141 .hsync_end = 1366 + 33 + 67, 1142 .htotal = 1560, 1143 .vdisplay = 768, 1144 .vsync_start = 768 + 4, 1145 .vsync_end = 768 + 4 + 4, 1146 .vtotal = 806, 1147 }; 1148 1149 static const struct panel_desc auo_g156xtn01 = { 1150 .modes = &auo_g156xtn01_mode, 1151 .num_modes = 1, 1152 .bpc = 8, 1153 .size = { 1154 .width = 344, 1155 .height = 194, 1156 }, 1157 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1158 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1159 }; 1160 1161 static const struct display_timing auo_g185han01_timings = { 1162 .pixelclock = { 120000000, 144000000, 175000000 }, 1163 .hactive = { 1920, 1920, 1920 }, 1164 .hfront_porch = { 36, 120, 148 }, 1165 .hback_porch = { 24, 88, 108 }, 1166 .hsync_len = { 20, 48, 64 }, 1167 .vactive = { 1080, 1080, 1080 }, 1168 .vfront_porch = { 6, 10, 40 }, 1169 .vback_porch = { 2, 5, 20 }, 1170 .vsync_len = { 2, 5, 20 }, 1171 }; 1172 1173 static const struct panel_desc auo_g185han01 = { 1174 .timings = &auo_g185han01_timings, 1175 .num_timings = 1, 1176 .bpc = 8, 1177 .size = { 1178 .width = 409, 1179 .height = 230, 1180 }, 1181 .delay = { 1182 .prepare = 50, 1183 .enable = 200, 1184 .disable = 110, 1185 .unprepare = 1000, 1186 }, 1187 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1188 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1189 }; 1190 1191 static const struct display_timing auo_g190ean01_timings = { 1192 .pixelclock = { 90000000, 108000000, 135000000 }, 1193 .hactive = { 1280, 1280, 1280 }, 1194 .hfront_porch = { 126, 184, 1266 }, 1195 .hback_porch = { 84, 122, 844 }, 1196 .hsync_len = { 70, 102, 704 }, 1197 .vactive = { 1024, 1024, 1024 }, 1198 .vfront_porch = { 4, 26, 76 }, 1199 .vback_porch = { 2, 8, 25 }, 1200 .vsync_len = { 2, 8, 25 }, 1201 }; 1202 1203 static const struct panel_desc auo_g190ean01 = { 1204 .timings = &auo_g190ean01_timings, 1205 .num_timings = 1, 1206 .bpc = 8, 1207 .size = { 1208 .width = 376, 1209 .height = 301, 1210 }, 1211 .delay = { 1212 .prepare = 50, 1213 .enable = 200, 1214 .disable = 110, 1215 .unprepare = 1000, 1216 }, 1217 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1218 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1219 }; 1220 1221 static const struct display_timing auo_p320hvn03_timings = { 1222 .pixelclock = { 106000000, 148500000, 164000000 }, 1223 .hactive = { 1920, 1920, 1920 }, 1224 .hfront_porch = { 25, 50, 130 }, 1225 .hback_porch = { 25, 50, 130 }, 1226 .hsync_len = { 20, 40, 105 }, 1227 .vactive = { 1080, 1080, 1080 }, 1228 .vfront_porch = { 8, 17, 150 }, 1229 .vback_porch = { 8, 17, 150 }, 1230 .vsync_len = { 4, 11, 100 }, 1231 }; 1232 1233 static const struct panel_desc auo_p320hvn03 = { 1234 .timings = &auo_p320hvn03_timings, 1235 .num_timings = 1, 1236 .bpc = 8, 1237 .size = { 1238 .width = 698, 1239 .height = 393, 1240 }, 1241 .delay = { 1242 .prepare = 1, 1243 .enable = 450, 1244 .unprepare = 500, 1245 }, 1246 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1247 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1248 }; 1249 1250 static const struct drm_display_mode auo_t215hvn01_mode = { 1251 .clock = 148800, 1252 .hdisplay = 1920, 1253 .hsync_start = 1920 + 88, 1254 .hsync_end = 1920 + 88 + 44, 1255 .htotal = 1920 + 88 + 44 + 148, 1256 .vdisplay = 1080, 1257 .vsync_start = 1080 + 4, 1258 .vsync_end = 1080 + 4 + 5, 1259 .vtotal = 1080 + 4 + 5 + 36, 1260 }; 1261 1262 static const struct panel_desc auo_t215hvn01 = { 1263 .modes = &auo_t215hvn01_mode, 1264 .num_modes = 1, 1265 .bpc = 8, 1266 .size = { 1267 .width = 430, 1268 .height = 270, 1269 }, 1270 .delay = { 1271 .disable = 5, 1272 .unprepare = 1000, 1273 }, 1274 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1275 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1276 }; 1277 1278 static const struct drm_display_mode avic_tm070ddh03_mode = { 1279 .clock = 51200, 1280 .hdisplay = 1024, 1281 .hsync_start = 1024 + 160, 1282 .hsync_end = 1024 + 160 + 4, 1283 .htotal = 1024 + 160 + 4 + 156, 1284 .vdisplay = 600, 1285 .vsync_start = 600 + 17, 1286 .vsync_end = 600 + 17 + 1, 1287 .vtotal = 600 + 17 + 1 + 17, 1288 }; 1289 1290 static const struct panel_desc avic_tm070ddh03 = { 1291 .modes = &avic_tm070ddh03_mode, 1292 .num_modes = 1, 1293 .bpc = 8, 1294 .size = { 1295 .width = 154, 1296 .height = 90, 1297 }, 1298 .delay = { 1299 .prepare = 20, 1300 .enable = 200, 1301 .disable = 200, 1302 }, 1303 }; 1304 1305 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1306 .clock = 30000, 1307 .hdisplay = 800, 1308 .hsync_start = 800 + 40, 1309 .hsync_end = 800 + 40 + 48, 1310 .htotal = 800 + 40 + 48 + 40, 1311 .vdisplay = 480, 1312 .vsync_start = 480 + 13, 1313 .vsync_end = 480 + 13 + 3, 1314 .vtotal = 480 + 13 + 3 + 29, 1315 }; 1316 1317 static const struct panel_desc bananapi_s070wv20_ct16 = { 1318 .modes = &bananapi_s070wv20_ct16_mode, 1319 .num_modes = 1, 1320 .bpc = 6, 1321 .size = { 1322 .width = 154, 1323 .height = 86, 1324 }, 1325 }; 1326 1327 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1328 .clock = 78945, 1329 .hdisplay = 1280, 1330 .hsync_start = 1280 + 0, 1331 .hsync_end = 1280 + 0 + 2, 1332 .htotal = 1280 + 62 + 0 + 2, 1333 .vdisplay = 800, 1334 .vsync_start = 800 + 8, 1335 .vsync_end = 800 + 8 + 2, 1336 .vtotal = 800 + 6 + 8 + 2, 1337 }; 1338 1339 static const struct panel_desc boe_bp101wx1_100 = { 1340 .modes = &boe_bp101wx1_100_mode, 1341 .num_modes = 1, 1342 .bpc = 8, 1343 .size = { 1344 .width = 217, 1345 .height = 136, 1346 }, 1347 .delay = { 1348 .enable = 50, 1349 .disable = 50, 1350 }, 1351 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1352 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1353 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1354 }; 1355 1356 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1357 .pixelclock = { 69922000, 71000000, 72293000 }, 1358 .hactive = { 1280, 1280, 1280 }, 1359 .hfront_porch = { 48, 48, 48 }, 1360 .hback_porch = { 80, 80, 80 }, 1361 .hsync_len = { 32, 32, 32 }, 1362 .vactive = { 800, 800, 800 }, 1363 .vfront_porch = { 3, 3, 3 }, 1364 .vback_porch = { 14, 14, 14 }, 1365 .vsync_len = { 6, 6, 6 }, 1366 }; 1367 1368 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1369 .timings = &boe_ev121wxm_n10_1850_timing, 1370 .num_timings = 1, 1371 .bpc = 8, 1372 .size = { 1373 .width = 261, 1374 .height = 163, 1375 }, 1376 .delay = { 1377 .prepare = 9, 1378 .enable = 300, 1379 .unprepare = 300, 1380 .disable = 560, 1381 }, 1382 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1383 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1384 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1385 }; 1386 1387 static const struct drm_display_mode boe_hv070wsa_mode = { 1388 .clock = 42105, 1389 .hdisplay = 1024, 1390 .hsync_start = 1024 + 30, 1391 .hsync_end = 1024 + 30 + 30, 1392 .htotal = 1024 + 30 + 30 + 30, 1393 .vdisplay = 600, 1394 .vsync_start = 600 + 10, 1395 .vsync_end = 600 + 10 + 10, 1396 .vtotal = 600 + 10 + 10 + 10, 1397 }; 1398 1399 static const struct panel_desc boe_hv070wsa = { 1400 .modes = &boe_hv070wsa_mode, 1401 .num_modes = 1, 1402 .bpc = 8, 1403 .size = { 1404 .width = 154, 1405 .height = 90, 1406 }, 1407 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1408 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1409 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1410 }; 1411 1412 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1413 .clock = 9000, 1414 .hdisplay = 480, 1415 .hsync_start = 480 + 5, 1416 .hsync_end = 480 + 5 + 5, 1417 .htotal = 480 + 5 + 5 + 40, 1418 .vdisplay = 272, 1419 .vsync_start = 272 + 8, 1420 .vsync_end = 272 + 8 + 8, 1421 .vtotal = 272 + 8 + 8 + 8, 1422 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1423 }; 1424 1425 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1426 .modes = &cdtech_s043wq26h_ct7_mode, 1427 .num_modes = 1, 1428 .bpc = 8, 1429 .size = { 1430 .width = 95, 1431 .height = 54, 1432 }, 1433 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1434 }; 1435 1436 /* S070PWS19HP-FC21 2017/04/22 */ 1437 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1438 .clock = 51200, 1439 .hdisplay = 1024, 1440 .hsync_start = 1024 + 160, 1441 .hsync_end = 1024 + 160 + 20, 1442 .htotal = 1024 + 160 + 20 + 140, 1443 .vdisplay = 600, 1444 .vsync_start = 600 + 12, 1445 .vsync_end = 600 + 12 + 3, 1446 .vtotal = 600 + 12 + 3 + 20, 1447 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1448 }; 1449 1450 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1451 .modes = &cdtech_s070pws19hp_fc21_mode, 1452 .num_modes = 1, 1453 .bpc = 6, 1454 .size = { 1455 .width = 154, 1456 .height = 86, 1457 }, 1458 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1459 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1460 .connector_type = DRM_MODE_CONNECTOR_DPI, 1461 }; 1462 1463 /* S070SWV29HG-DC44 2017/09/21 */ 1464 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1465 .clock = 33300, 1466 .hdisplay = 800, 1467 .hsync_start = 800 + 210, 1468 .hsync_end = 800 + 210 + 2, 1469 .htotal = 800 + 210 + 2 + 44, 1470 .vdisplay = 480, 1471 .vsync_start = 480 + 22, 1472 .vsync_end = 480 + 22 + 2, 1473 .vtotal = 480 + 22 + 2 + 21, 1474 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1475 }; 1476 1477 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1478 .modes = &cdtech_s070swv29hg_dc44_mode, 1479 .num_modes = 1, 1480 .bpc = 6, 1481 .size = { 1482 .width = 154, 1483 .height = 86, 1484 }, 1485 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1486 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1487 .connector_type = DRM_MODE_CONNECTOR_DPI, 1488 }; 1489 1490 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1491 .clock = 35000, 1492 .hdisplay = 800, 1493 .hsync_start = 800 + 40, 1494 .hsync_end = 800 + 40 + 40, 1495 .htotal = 800 + 40 + 40 + 48, 1496 .vdisplay = 480, 1497 .vsync_start = 480 + 29, 1498 .vsync_end = 480 + 29 + 13, 1499 .vtotal = 480 + 29 + 13 + 3, 1500 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1501 }; 1502 1503 static const struct panel_desc cdtech_s070wv95_ct16 = { 1504 .modes = &cdtech_s070wv95_ct16_mode, 1505 .num_modes = 1, 1506 .bpc = 8, 1507 .size = { 1508 .width = 154, 1509 .height = 85, 1510 }, 1511 }; 1512 1513 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1514 .pixelclock = { 68900000, 71100000, 73400000 }, 1515 .hactive = { 1280, 1280, 1280 }, 1516 .hfront_porch = { 65, 80, 95 }, 1517 .hback_porch = { 64, 79, 94 }, 1518 .hsync_len = { 1, 1, 1 }, 1519 .vactive = { 800, 800, 800 }, 1520 .vfront_porch = { 7, 11, 14 }, 1521 .vback_porch = { 7, 11, 14 }, 1522 .vsync_len = { 1, 1, 1 }, 1523 .flags = DISPLAY_FLAGS_DE_HIGH, 1524 }; 1525 1526 static const struct panel_desc chefree_ch101olhlwh_002 = { 1527 .timings = &chefree_ch101olhlwh_002_timing, 1528 .num_timings = 1, 1529 .bpc = 8, 1530 .size = { 1531 .width = 217, 1532 .height = 135, 1533 }, 1534 .delay = { 1535 .enable = 200, 1536 .disable = 200, 1537 }, 1538 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1539 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1540 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1541 }; 1542 1543 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1544 .clock = 66770, 1545 .hdisplay = 800, 1546 .hsync_start = 800 + 49, 1547 .hsync_end = 800 + 49 + 33, 1548 .htotal = 800 + 49 + 33 + 17, 1549 .vdisplay = 1280, 1550 .vsync_start = 1280 + 1, 1551 .vsync_end = 1280 + 1 + 7, 1552 .vtotal = 1280 + 1 + 7 + 15, 1553 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1554 }; 1555 1556 static const struct panel_desc chunghwa_claa070wp03xg = { 1557 .modes = &chunghwa_claa070wp03xg_mode, 1558 .num_modes = 1, 1559 .bpc = 6, 1560 .size = { 1561 .width = 94, 1562 .height = 150, 1563 }, 1564 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1565 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1566 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1567 }; 1568 1569 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1570 .clock = 72070, 1571 .hdisplay = 1366, 1572 .hsync_start = 1366 + 58, 1573 .hsync_end = 1366 + 58 + 58, 1574 .htotal = 1366 + 58 + 58 + 58, 1575 .vdisplay = 768, 1576 .vsync_start = 768 + 4, 1577 .vsync_end = 768 + 4 + 4, 1578 .vtotal = 768 + 4 + 4 + 4, 1579 }; 1580 1581 static const struct panel_desc chunghwa_claa101wa01a = { 1582 .modes = &chunghwa_claa101wa01a_mode, 1583 .num_modes = 1, 1584 .bpc = 6, 1585 .size = { 1586 .width = 220, 1587 .height = 120, 1588 }, 1589 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1590 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1591 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1592 }; 1593 1594 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1595 .clock = 69300, 1596 .hdisplay = 1366, 1597 .hsync_start = 1366 + 48, 1598 .hsync_end = 1366 + 48 + 32, 1599 .htotal = 1366 + 48 + 32 + 20, 1600 .vdisplay = 768, 1601 .vsync_start = 768 + 16, 1602 .vsync_end = 768 + 16 + 8, 1603 .vtotal = 768 + 16 + 8 + 16, 1604 }; 1605 1606 static const struct panel_desc chunghwa_claa101wb01 = { 1607 .modes = &chunghwa_claa101wb01_mode, 1608 .num_modes = 1, 1609 .bpc = 6, 1610 .size = { 1611 .width = 223, 1612 .height = 125, 1613 }, 1614 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1615 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1616 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1617 }; 1618 1619 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1620 .pixelclock = { 5000000, 9000000, 12000000 }, 1621 .hactive = { 480, 480, 480 }, 1622 .hfront_porch = { 12, 12, 12 }, 1623 .hback_porch = { 12, 12, 12 }, 1624 .hsync_len = { 21, 21, 21 }, 1625 .vactive = { 272, 272, 272 }, 1626 .vfront_porch = { 4, 4, 4 }, 1627 .vback_porch = { 4, 4, 4 }, 1628 .vsync_len = { 8, 8, 8 }, 1629 }; 1630 1631 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1632 .timings = &dataimage_fg040346dsswbg04_timing, 1633 .num_timings = 1, 1634 .bpc = 8, 1635 .size = { 1636 .width = 95, 1637 .height = 54, 1638 }, 1639 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1640 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1641 .connector_type = DRM_MODE_CONNECTOR_DPI, 1642 }; 1643 1644 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1645 .pixelclock = { 68900000, 71110000, 73400000 }, 1646 .hactive = { 1280, 1280, 1280 }, 1647 .vactive = { 800, 800, 800 }, 1648 .hback_porch = { 100, 100, 100 }, 1649 .hfront_porch = { 100, 100, 100 }, 1650 .vback_porch = { 5, 5, 5 }, 1651 .vfront_porch = { 5, 5, 5 }, 1652 .hsync_len = { 24, 24, 24 }, 1653 .vsync_len = { 3, 3, 3 }, 1654 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1655 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1656 }; 1657 1658 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1659 .timings = &dataimage_fg1001l0dsswmg01_timing, 1660 .num_timings = 1, 1661 .bpc = 8, 1662 .size = { 1663 .width = 217, 1664 .height = 136, 1665 }, 1666 }; 1667 1668 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1669 .clock = 33260, 1670 .hdisplay = 800, 1671 .hsync_start = 800 + 40, 1672 .hsync_end = 800 + 40 + 128, 1673 .htotal = 800 + 40 + 128 + 88, 1674 .vdisplay = 480, 1675 .vsync_start = 480 + 10, 1676 .vsync_end = 480 + 10 + 2, 1677 .vtotal = 480 + 10 + 2 + 33, 1678 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1679 }; 1680 1681 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1682 .modes = &dataimage_scf0700c48ggu18_mode, 1683 .num_modes = 1, 1684 .bpc = 8, 1685 .size = { 1686 .width = 152, 1687 .height = 91, 1688 }, 1689 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1690 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1691 }; 1692 1693 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1694 .pixelclock = { 45000000, 51200000, 57000000 }, 1695 .hactive = { 1024, 1024, 1024 }, 1696 .hfront_porch = { 100, 106, 113 }, 1697 .hback_porch = { 100, 106, 113 }, 1698 .hsync_len = { 100, 108, 114 }, 1699 .vactive = { 600, 600, 600 }, 1700 .vfront_porch = { 8, 11, 15 }, 1701 .vback_porch = { 8, 11, 15 }, 1702 .vsync_len = { 9, 13, 15 }, 1703 .flags = DISPLAY_FLAGS_DE_HIGH, 1704 }; 1705 1706 static const struct panel_desc dlc_dlc0700yzg_1 = { 1707 .timings = &dlc_dlc0700yzg_1_timing, 1708 .num_timings = 1, 1709 .bpc = 6, 1710 .size = { 1711 .width = 154, 1712 .height = 86, 1713 }, 1714 .delay = { 1715 .prepare = 30, 1716 .enable = 200, 1717 .disable = 200, 1718 }, 1719 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1720 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1721 }; 1722 1723 static const struct display_timing dlc_dlc1010gig_timing = { 1724 .pixelclock = { 68900000, 71100000, 73400000 }, 1725 .hactive = { 1280, 1280, 1280 }, 1726 .hfront_porch = { 43, 53, 63 }, 1727 .hback_porch = { 43, 53, 63 }, 1728 .hsync_len = { 44, 54, 64 }, 1729 .vactive = { 800, 800, 800 }, 1730 .vfront_porch = { 5, 8, 11 }, 1731 .vback_porch = { 5, 8, 11 }, 1732 .vsync_len = { 5, 7, 11 }, 1733 .flags = DISPLAY_FLAGS_DE_HIGH, 1734 }; 1735 1736 static const struct panel_desc dlc_dlc1010gig = { 1737 .timings = &dlc_dlc1010gig_timing, 1738 .num_timings = 1, 1739 .bpc = 8, 1740 .size = { 1741 .width = 216, 1742 .height = 135, 1743 }, 1744 .delay = { 1745 .prepare = 60, 1746 .enable = 150, 1747 .disable = 100, 1748 .unprepare = 60, 1749 }, 1750 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1751 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1752 }; 1753 1754 static const struct drm_display_mode edt_et035012dm6_mode = { 1755 .clock = 6500, 1756 .hdisplay = 320, 1757 .hsync_start = 320 + 20, 1758 .hsync_end = 320 + 20 + 30, 1759 .htotal = 320 + 20 + 68, 1760 .vdisplay = 240, 1761 .vsync_start = 240 + 4, 1762 .vsync_end = 240 + 4 + 4, 1763 .vtotal = 240 + 4 + 4 + 14, 1764 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1765 }; 1766 1767 static const struct panel_desc edt_et035012dm6 = { 1768 .modes = &edt_et035012dm6_mode, 1769 .num_modes = 1, 1770 .bpc = 8, 1771 .size = { 1772 .width = 70, 1773 .height = 52, 1774 }, 1775 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1776 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1777 }; 1778 1779 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1780 .clock = 6520, 1781 .hdisplay = 320, 1782 .hsync_start = 320 + 20, 1783 .hsync_end = 320 + 20 + 68, 1784 .htotal = 320 + 20 + 68, 1785 .vdisplay = 240, 1786 .vsync_start = 240 + 4, 1787 .vsync_end = 240 + 4 + 18, 1788 .vtotal = 240 + 4 + 18, 1789 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1790 }; 1791 1792 static const struct panel_desc edt_etm0350g0dh6 = { 1793 .modes = &edt_etm0350g0dh6_mode, 1794 .num_modes = 1, 1795 .bpc = 6, 1796 .size = { 1797 .width = 70, 1798 .height = 53, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1802 .connector_type = DRM_MODE_CONNECTOR_DPI, 1803 }; 1804 1805 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1806 .clock = 10870, 1807 .hdisplay = 480, 1808 .hsync_start = 480 + 8, 1809 .hsync_end = 480 + 8 + 4, 1810 .htotal = 480 + 8 + 4 + 41, 1811 1812 /* 1813 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1814 * fb_align 1815 */ 1816 1817 .vdisplay = 288, 1818 .vsync_start = 288 + 2, 1819 .vsync_end = 288 + 2 + 4, 1820 .vtotal = 288 + 2 + 4 + 10, 1821 }; 1822 1823 static const struct panel_desc edt_etm043080dh6gp = { 1824 .modes = &edt_etm043080dh6gp_mode, 1825 .num_modes = 1, 1826 .bpc = 8, 1827 .size = { 1828 .width = 100, 1829 .height = 65, 1830 }, 1831 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1832 .connector_type = DRM_MODE_CONNECTOR_DPI, 1833 }; 1834 1835 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1836 .clock = 9000, 1837 .hdisplay = 480, 1838 .hsync_start = 480 + 2, 1839 .hsync_end = 480 + 2 + 41, 1840 .htotal = 480 + 2 + 41 + 2, 1841 .vdisplay = 272, 1842 .vsync_start = 272 + 2, 1843 .vsync_end = 272 + 2 + 10, 1844 .vtotal = 272 + 2 + 10 + 2, 1845 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1846 }; 1847 1848 static const struct panel_desc edt_etm0430g0dh6 = { 1849 .modes = &edt_etm0430g0dh6_mode, 1850 .num_modes = 1, 1851 .bpc = 6, 1852 .size = { 1853 .width = 95, 1854 .height = 54, 1855 }, 1856 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1857 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1858 .connector_type = DRM_MODE_CONNECTOR_DPI, 1859 }; 1860 1861 static const struct drm_display_mode edt_et057090dhu_mode = { 1862 .clock = 25175, 1863 .hdisplay = 640, 1864 .hsync_start = 640 + 16, 1865 .hsync_end = 640 + 16 + 30, 1866 .htotal = 640 + 16 + 30 + 114, 1867 .vdisplay = 480, 1868 .vsync_start = 480 + 10, 1869 .vsync_end = 480 + 10 + 3, 1870 .vtotal = 480 + 10 + 3 + 32, 1871 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1872 }; 1873 1874 static const struct panel_desc edt_et057090dhu = { 1875 .modes = &edt_et057090dhu_mode, 1876 .num_modes = 1, 1877 .bpc = 6, 1878 .size = { 1879 .width = 115, 1880 .height = 86, 1881 }, 1882 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1883 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1884 .connector_type = DRM_MODE_CONNECTOR_DPI, 1885 }; 1886 1887 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1888 .clock = 33260, 1889 .hdisplay = 800, 1890 .hsync_start = 800 + 40, 1891 .hsync_end = 800 + 40 + 128, 1892 .htotal = 800 + 40 + 128 + 88, 1893 .vdisplay = 480, 1894 .vsync_start = 480 + 10, 1895 .vsync_end = 480 + 10 + 2, 1896 .vtotal = 480 + 10 + 2 + 33, 1897 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1898 }; 1899 1900 static const struct panel_desc edt_etm0700g0dh6 = { 1901 .modes = &edt_etm0700g0dh6_mode, 1902 .num_modes = 1, 1903 .bpc = 6, 1904 .size = { 1905 .width = 152, 1906 .height = 91, 1907 }, 1908 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1909 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1910 .connector_type = DRM_MODE_CONNECTOR_DPI, 1911 }; 1912 1913 static const struct panel_desc edt_etm0700g0bdh6 = { 1914 .modes = &edt_etm0700g0dh6_mode, 1915 .num_modes = 1, 1916 .bpc = 6, 1917 .size = { 1918 .width = 152, 1919 .height = 91, 1920 }, 1921 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1922 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1923 .connector_type = DRM_MODE_CONNECTOR_DPI, 1924 }; 1925 1926 static const struct display_timing edt_etml0700y5dha_timing = { 1927 .pixelclock = { 40800000, 51200000, 67200000 }, 1928 .hactive = { 1024, 1024, 1024 }, 1929 .hfront_porch = { 30, 106, 125 }, 1930 .hback_porch = { 30, 106, 125 }, 1931 .hsync_len = { 30, 108, 126 }, 1932 .vactive = { 600, 600, 600 }, 1933 .vfront_porch = { 3, 12, 67}, 1934 .vback_porch = { 3, 12, 67 }, 1935 .vsync_len = { 4, 11, 66 }, 1936 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1937 DISPLAY_FLAGS_DE_HIGH, 1938 }; 1939 1940 static const struct panel_desc edt_etml0700y5dha = { 1941 .timings = &edt_etml0700y5dha_timing, 1942 .num_timings = 1, 1943 .bpc = 8, 1944 .size = { 1945 .width = 155, 1946 .height = 86, 1947 }, 1948 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1949 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1950 }; 1951 1952 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1953 .clock = 25175, 1954 .hdisplay = 640, 1955 .hsync_start = 640, 1956 .hsync_end = 640 + 16, 1957 .htotal = 640 + 16 + 30 + 114, 1958 .vdisplay = 480, 1959 .vsync_start = 480 + 10, 1960 .vsync_end = 480 + 10 + 3, 1961 .vtotal = 480 + 10 + 3 + 35, 1962 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1963 }; 1964 1965 static const struct panel_desc edt_etmv570g2dhu = { 1966 .modes = &edt_etmv570g2dhu_mode, 1967 .num_modes = 1, 1968 .bpc = 6, 1969 .size = { 1970 .width = 115, 1971 .height = 86, 1972 }, 1973 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1974 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1975 .connector_type = DRM_MODE_CONNECTOR_DPI, 1976 }; 1977 1978 static const struct display_timing eink_vb3300_kca_timing = { 1979 .pixelclock = { 40000000, 40000000, 40000000 }, 1980 .hactive = { 334, 334, 334 }, 1981 .hfront_porch = { 1, 1, 1 }, 1982 .hback_porch = { 1, 1, 1 }, 1983 .hsync_len = { 1, 1, 1 }, 1984 .vactive = { 1405, 1405, 1405 }, 1985 .vfront_porch = { 1, 1, 1 }, 1986 .vback_porch = { 1, 1, 1 }, 1987 .vsync_len = { 1, 1, 1 }, 1988 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1989 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1990 }; 1991 1992 static const struct panel_desc eink_vb3300_kca = { 1993 .timings = &eink_vb3300_kca_timing, 1994 .num_timings = 1, 1995 .bpc = 6, 1996 .size = { 1997 .width = 157, 1998 .height = 209, 1999 }, 2000 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2001 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2002 .connector_type = DRM_MODE_CONNECTOR_DPI, 2003 }; 2004 2005 static const struct display_timing evervision_vgg644804_timing = { 2006 .pixelclock = { 25175000, 25175000, 25175000 }, 2007 .hactive = { 640, 640, 640 }, 2008 .hfront_porch = { 16, 16, 16 }, 2009 .hback_porch = { 82, 114, 170 }, 2010 .hsync_len = { 5, 30, 30 }, 2011 .vactive = { 480, 480, 480 }, 2012 .vfront_porch = { 10, 10, 10 }, 2013 .vback_porch = { 30, 32, 34 }, 2014 .vsync_len = { 1, 3, 5 }, 2015 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2016 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2017 DISPLAY_FLAGS_SYNC_POSEDGE, 2018 }; 2019 2020 static const struct panel_desc evervision_vgg644804 = { 2021 .timings = &evervision_vgg644804_timing, 2022 .num_timings = 1, 2023 .bpc = 8, 2024 .size = { 2025 .width = 115, 2026 .height = 86, 2027 }, 2028 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2029 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2030 }; 2031 2032 static const struct display_timing evervision_vgg804821_timing = { 2033 .pixelclock = { 27600000, 33300000, 50000000 }, 2034 .hactive = { 800, 800, 800 }, 2035 .hfront_porch = { 40, 66, 70 }, 2036 .hback_porch = { 40, 67, 70 }, 2037 .hsync_len = { 40, 67, 70 }, 2038 .vactive = { 480, 480, 480 }, 2039 .vfront_porch = { 6, 10, 10 }, 2040 .vback_porch = { 7, 11, 11 }, 2041 .vsync_len = { 7, 11, 11 }, 2042 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2043 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2044 DISPLAY_FLAGS_SYNC_NEGEDGE, 2045 }; 2046 2047 static const struct panel_desc evervision_vgg804821 = { 2048 .timings = &evervision_vgg804821_timing, 2049 .num_timings = 1, 2050 .bpc = 8, 2051 .size = { 2052 .width = 108, 2053 .height = 64, 2054 }, 2055 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2056 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2057 }; 2058 2059 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2060 .clock = 32260, 2061 .hdisplay = 800, 2062 .hsync_start = 800 + 168, 2063 .hsync_end = 800 + 168 + 64, 2064 .htotal = 800 + 168 + 64 + 88, 2065 .vdisplay = 480, 2066 .vsync_start = 480 + 37, 2067 .vsync_end = 480 + 37 + 2, 2068 .vtotal = 480 + 37 + 2 + 8, 2069 }; 2070 2071 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2072 .modes = &foxlink_fl500wvr00_a0t_mode, 2073 .num_modes = 1, 2074 .bpc = 8, 2075 .size = { 2076 .width = 108, 2077 .height = 65, 2078 }, 2079 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2080 }; 2081 2082 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2083 { /* 60 Hz */ 2084 .clock = 6000, 2085 .hdisplay = 320, 2086 .hsync_start = 320 + 44, 2087 .hsync_end = 320 + 44 + 16, 2088 .htotal = 320 + 44 + 16 + 20, 2089 .vdisplay = 240, 2090 .vsync_start = 240 + 2, 2091 .vsync_end = 240 + 2 + 6, 2092 .vtotal = 240 + 2 + 6 + 2, 2093 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2094 }, 2095 { /* 50 Hz */ 2096 .clock = 5400, 2097 .hdisplay = 320, 2098 .hsync_start = 320 + 56, 2099 .hsync_end = 320 + 56 + 16, 2100 .htotal = 320 + 56 + 16 + 40, 2101 .vdisplay = 240, 2102 .vsync_start = 240 + 2, 2103 .vsync_end = 240 + 2 + 6, 2104 .vtotal = 240 + 2 + 6 + 2, 2105 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2106 }, 2107 }; 2108 2109 static const struct panel_desc frida_frd350h54004 = { 2110 .modes = frida_frd350h54004_modes, 2111 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2112 .bpc = 8, 2113 .size = { 2114 .width = 77, 2115 .height = 64, 2116 }, 2117 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2118 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2119 .connector_type = DRM_MODE_CONNECTOR_DPI, 2120 }; 2121 2122 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2123 .clock = 67185, 2124 .hdisplay = 800, 2125 .hsync_start = 800 + 20, 2126 .hsync_end = 800 + 20 + 24, 2127 .htotal = 800 + 20 + 24 + 20, 2128 .vdisplay = 1280, 2129 .vsync_start = 1280 + 4, 2130 .vsync_end = 1280 + 4 + 8, 2131 .vtotal = 1280 + 4 + 8 + 4, 2132 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2133 }; 2134 2135 static const struct panel_desc friendlyarm_hd702e = { 2136 .modes = &friendlyarm_hd702e_mode, 2137 .num_modes = 1, 2138 .size = { 2139 .width = 94, 2140 .height = 151, 2141 }, 2142 }; 2143 2144 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2145 .clock = 9000, 2146 .hdisplay = 480, 2147 .hsync_start = 480 + 5, 2148 .hsync_end = 480 + 5 + 1, 2149 .htotal = 480 + 5 + 1 + 40, 2150 .vdisplay = 272, 2151 .vsync_start = 272 + 8, 2152 .vsync_end = 272 + 8 + 1, 2153 .vtotal = 272 + 8 + 1 + 8, 2154 }; 2155 2156 static const struct panel_desc giantplus_gpg482739qs5 = { 2157 .modes = &giantplus_gpg482739qs5_mode, 2158 .num_modes = 1, 2159 .bpc = 8, 2160 .size = { 2161 .width = 95, 2162 .height = 54, 2163 }, 2164 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2165 }; 2166 2167 static const struct display_timing giantplus_gpm940b0_timing = { 2168 .pixelclock = { 13500000, 27000000, 27500000 }, 2169 .hactive = { 320, 320, 320 }, 2170 .hfront_porch = { 14, 686, 718 }, 2171 .hback_porch = { 50, 70, 255 }, 2172 .hsync_len = { 1, 1, 1 }, 2173 .vactive = { 240, 240, 240 }, 2174 .vfront_porch = { 1, 1, 179 }, 2175 .vback_porch = { 1, 21, 31 }, 2176 .vsync_len = { 1, 1, 6 }, 2177 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2178 }; 2179 2180 static const struct panel_desc giantplus_gpm940b0 = { 2181 .timings = &giantplus_gpm940b0_timing, 2182 .num_timings = 1, 2183 .bpc = 8, 2184 .size = { 2185 .width = 60, 2186 .height = 45, 2187 }, 2188 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2189 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2190 }; 2191 2192 static const struct display_timing hannstar_hsd070pww1_timing = { 2193 .pixelclock = { 64300000, 71100000, 82000000 }, 2194 .hactive = { 1280, 1280, 1280 }, 2195 .hfront_porch = { 1, 1, 10 }, 2196 .hback_porch = { 1, 1, 10 }, 2197 /* 2198 * According to the data sheet, the minimum horizontal blanking interval 2199 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2200 * minimum working horizontal blanking interval to be 60 clocks. 2201 */ 2202 .hsync_len = { 58, 158, 661 }, 2203 .vactive = { 800, 800, 800 }, 2204 .vfront_porch = { 1, 1, 10 }, 2205 .vback_porch = { 1, 1, 10 }, 2206 .vsync_len = { 1, 21, 203 }, 2207 .flags = DISPLAY_FLAGS_DE_HIGH, 2208 }; 2209 2210 static const struct panel_desc hannstar_hsd070pww1 = { 2211 .timings = &hannstar_hsd070pww1_timing, 2212 .num_timings = 1, 2213 .bpc = 6, 2214 .size = { 2215 .width = 151, 2216 .height = 94, 2217 }, 2218 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2219 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2220 }; 2221 2222 static const struct display_timing hannstar_hsd100pxn1_timing = { 2223 .pixelclock = { 55000000, 65000000, 75000000 }, 2224 .hactive = { 1024, 1024, 1024 }, 2225 .hfront_porch = { 40, 40, 40 }, 2226 .hback_porch = { 220, 220, 220 }, 2227 .hsync_len = { 20, 60, 100 }, 2228 .vactive = { 768, 768, 768 }, 2229 .vfront_porch = { 7, 7, 7 }, 2230 .vback_porch = { 21, 21, 21 }, 2231 .vsync_len = { 10, 10, 10 }, 2232 .flags = DISPLAY_FLAGS_DE_HIGH, 2233 }; 2234 2235 static const struct panel_desc hannstar_hsd100pxn1 = { 2236 .timings = &hannstar_hsd100pxn1_timing, 2237 .num_timings = 1, 2238 .bpc = 6, 2239 .size = { 2240 .width = 203, 2241 .height = 152, 2242 }, 2243 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2244 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2245 }; 2246 2247 static const struct display_timing hannstar_hsd101pww2_timing = { 2248 .pixelclock = { 64300000, 71100000, 82000000 }, 2249 .hactive = { 1280, 1280, 1280 }, 2250 .hfront_porch = { 1, 1, 10 }, 2251 .hback_porch = { 1, 1, 10 }, 2252 .hsync_len = { 58, 158, 661 }, 2253 .vactive = { 800, 800, 800 }, 2254 .vfront_porch = { 1, 1, 10 }, 2255 .vback_porch = { 1, 1, 10 }, 2256 .vsync_len = { 1, 21, 203 }, 2257 .flags = DISPLAY_FLAGS_DE_HIGH, 2258 }; 2259 2260 static const struct panel_desc hannstar_hsd101pww2 = { 2261 .timings = &hannstar_hsd101pww2_timing, 2262 .num_timings = 1, 2263 .bpc = 8, 2264 .size = { 2265 .width = 217, 2266 .height = 136, 2267 }, 2268 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2269 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2270 }; 2271 2272 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2273 .clock = 33333, 2274 .hdisplay = 800, 2275 .hsync_start = 800 + 85, 2276 .hsync_end = 800 + 85 + 86, 2277 .htotal = 800 + 85 + 86 + 85, 2278 .vdisplay = 480, 2279 .vsync_start = 480 + 16, 2280 .vsync_end = 480 + 16 + 13, 2281 .vtotal = 480 + 16 + 13 + 16, 2282 }; 2283 2284 static const struct panel_desc hitachi_tx23d38vm0caa = { 2285 .modes = &hitachi_tx23d38vm0caa_mode, 2286 .num_modes = 1, 2287 .bpc = 6, 2288 .size = { 2289 .width = 195, 2290 .height = 117, 2291 }, 2292 .delay = { 2293 .enable = 160, 2294 .disable = 160, 2295 }, 2296 }; 2297 2298 static const struct drm_display_mode innolux_at043tn24_mode = { 2299 .clock = 9000, 2300 .hdisplay = 480, 2301 .hsync_start = 480 + 2, 2302 .hsync_end = 480 + 2 + 41, 2303 .htotal = 480 + 2 + 41 + 2, 2304 .vdisplay = 272, 2305 .vsync_start = 272 + 2, 2306 .vsync_end = 272 + 2 + 10, 2307 .vtotal = 272 + 2 + 10 + 2, 2308 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2309 }; 2310 2311 static const struct panel_desc innolux_at043tn24 = { 2312 .modes = &innolux_at043tn24_mode, 2313 .num_modes = 1, 2314 .bpc = 8, 2315 .size = { 2316 .width = 95, 2317 .height = 54, 2318 }, 2319 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2320 .connector_type = DRM_MODE_CONNECTOR_DPI, 2321 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2322 }; 2323 2324 static const struct drm_display_mode innolux_at070tn92_mode = { 2325 .clock = 33333, 2326 .hdisplay = 800, 2327 .hsync_start = 800 + 210, 2328 .hsync_end = 800 + 210 + 20, 2329 .htotal = 800 + 210 + 20 + 46, 2330 .vdisplay = 480, 2331 .vsync_start = 480 + 22, 2332 .vsync_end = 480 + 22 + 10, 2333 .vtotal = 480 + 22 + 23 + 10, 2334 }; 2335 2336 static const struct panel_desc innolux_at070tn92 = { 2337 .modes = &innolux_at070tn92_mode, 2338 .num_modes = 1, 2339 .size = { 2340 .width = 154, 2341 .height = 86, 2342 }, 2343 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2344 }; 2345 2346 static const struct display_timing innolux_g070ace_l01_timing = { 2347 .pixelclock = { 25200000, 35000000, 35700000 }, 2348 .hactive = { 800, 800, 800 }, 2349 .hfront_porch = { 30, 32, 87 }, 2350 .hback_porch = { 30, 32, 87 }, 2351 .hsync_len = { 1, 1, 1 }, 2352 .vactive = { 480, 480, 480 }, 2353 .vfront_porch = { 3, 3, 3 }, 2354 .vback_porch = { 13, 13, 13 }, 2355 .vsync_len = { 1, 1, 4 }, 2356 .flags = DISPLAY_FLAGS_DE_HIGH, 2357 }; 2358 2359 static const struct panel_desc innolux_g070ace_l01 = { 2360 .timings = &innolux_g070ace_l01_timing, 2361 .num_timings = 1, 2362 .bpc = 8, 2363 .size = { 2364 .width = 152, 2365 .height = 91, 2366 }, 2367 .delay = { 2368 .prepare = 10, 2369 .enable = 50, 2370 .disable = 50, 2371 .unprepare = 500, 2372 }, 2373 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2374 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2375 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2376 }; 2377 2378 static const struct display_timing innolux_g070y2_l01_timing = { 2379 .pixelclock = { 28000000, 29500000, 32000000 }, 2380 .hactive = { 800, 800, 800 }, 2381 .hfront_porch = { 61, 91, 141 }, 2382 .hback_porch = { 60, 90, 140 }, 2383 .hsync_len = { 12, 12, 12 }, 2384 .vactive = { 480, 480, 480 }, 2385 .vfront_porch = { 4, 9, 30 }, 2386 .vback_porch = { 4, 8, 28 }, 2387 .vsync_len = { 2, 2, 2 }, 2388 .flags = DISPLAY_FLAGS_DE_HIGH, 2389 }; 2390 2391 static const struct panel_desc innolux_g070y2_l01 = { 2392 .timings = &innolux_g070y2_l01_timing, 2393 .num_timings = 1, 2394 .bpc = 8, 2395 .size = { 2396 .width = 152, 2397 .height = 91, 2398 }, 2399 .delay = { 2400 .prepare = 10, 2401 .enable = 100, 2402 .disable = 100, 2403 .unprepare = 800, 2404 }, 2405 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2406 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2407 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2408 }; 2409 2410 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2411 .clock = 33333, 2412 .hdisplay = 800, 2413 .hsync_start = 800 + 210, 2414 .hsync_end = 800 + 210 + 20, 2415 .htotal = 800 + 210 + 20 + 46, 2416 .vdisplay = 480, 2417 .vsync_start = 480 + 22, 2418 .vsync_end = 480 + 22 + 10, 2419 .vtotal = 480 + 22 + 23 + 10, 2420 }; 2421 2422 static const struct panel_desc innolux_g070y2_t02 = { 2423 .modes = &innolux_g070y2_t02_mode, 2424 .num_modes = 1, 2425 .bpc = 8, 2426 .size = { 2427 .width = 152, 2428 .height = 92, 2429 }, 2430 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2431 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2432 .connector_type = DRM_MODE_CONNECTOR_DPI, 2433 }; 2434 2435 static const struct display_timing innolux_g101ice_l01_timing = { 2436 .pixelclock = { 60400000, 71100000, 74700000 }, 2437 .hactive = { 1280, 1280, 1280 }, 2438 .hfront_porch = { 30, 60, 70 }, 2439 .hback_porch = { 30, 60, 70 }, 2440 .hsync_len = { 22, 40, 60 }, 2441 .vactive = { 800, 800, 800 }, 2442 .vfront_porch = { 3, 8, 14 }, 2443 .vback_porch = { 3, 8, 14 }, 2444 .vsync_len = { 4, 7, 12 }, 2445 .flags = DISPLAY_FLAGS_DE_HIGH, 2446 }; 2447 2448 static const struct panel_desc innolux_g101ice_l01 = { 2449 .timings = &innolux_g101ice_l01_timing, 2450 .num_timings = 1, 2451 .bpc = 8, 2452 .size = { 2453 .width = 217, 2454 .height = 135, 2455 }, 2456 .delay = { 2457 .enable = 200, 2458 .disable = 200, 2459 }, 2460 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2461 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2462 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2463 }; 2464 2465 static const struct display_timing innolux_g121i1_l01_timing = { 2466 .pixelclock = { 67450000, 71000000, 74550000 }, 2467 .hactive = { 1280, 1280, 1280 }, 2468 .hfront_porch = { 40, 80, 160 }, 2469 .hback_porch = { 39, 79, 159 }, 2470 .hsync_len = { 1, 1, 1 }, 2471 .vactive = { 800, 800, 800 }, 2472 .vfront_porch = { 5, 11, 100 }, 2473 .vback_porch = { 4, 11, 99 }, 2474 .vsync_len = { 1, 1, 1 }, 2475 }; 2476 2477 static const struct panel_desc innolux_g121i1_l01 = { 2478 .timings = &innolux_g121i1_l01_timing, 2479 .num_timings = 1, 2480 .bpc = 6, 2481 .size = { 2482 .width = 261, 2483 .height = 163, 2484 }, 2485 .delay = { 2486 .enable = 200, 2487 .disable = 20, 2488 }, 2489 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2490 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2491 }; 2492 2493 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2494 .clock = 65000, 2495 .hdisplay = 1024, 2496 .hsync_start = 1024 + 0, 2497 .hsync_end = 1024 + 1, 2498 .htotal = 1024 + 0 + 1 + 320, 2499 .vdisplay = 768, 2500 .vsync_start = 768 + 38, 2501 .vsync_end = 768 + 38 + 1, 2502 .vtotal = 768 + 38 + 1 + 0, 2503 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2504 }; 2505 2506 static const struct panel_desc innolux_g121x1_l03 = { 2507 .modes = &innolux_g121x1_l03_mode, 2508 .num_modes = 1, 2509 .bpc = 6, 2510 .size = { 2511 .width = 246, 2512 .height = 185, 2513 }, 2514 .delay = { 2515 .enable = 200, 2516 .unprepare = 200, 2517 .disable = 400, 2518 }, 2519 }; 2520 2521 static const struct display_timing innolux_g156hce_l01_timings = { 2522 .pixelclock = { 120000000, 141860000, 150000000 }, 2523 .hactive = { 1920, 1920, 1920 }, 2524 .hfront_porch = { 80, 90, 100 }, 2525 .hback_porch = { 80, 90, 100 }, 2526 .hsync_len = { 20, 30, 30 }, 2527 .vactive = { 1080, 1080, 1080 }, 2528 .vfront_porch = { 3, 10, 20 }, 2529 .vback_porch = { 3, 10, 20 }, 2530 .vsync_len = { 4, 10, 10 }, 2531 }; 2532 2533 static const struct panel_desc innolux_g156hce_l01 = { 2534 .timings = &innolux_g156hce_l01_timings, 2535 .num_timings = 1, 2536 .bpc = 8, 2537 .size = { 2538 .width = 344, 2539 .height = 194, 2540 }, 2541 .delay = { 2542 .prepare = 1, /* T1+T2 */ 2543 .enable = 450, /* T5 */ 2544 .disable = 200, /* T6 */ 2545 .unprepare = 10, /* T3+T7 */ 2546 }, 2547 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2548 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2549 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2550 }; 2551 2552 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2553 .clock = 69300, 2554 .hdisplay = 1366, 2555 .hsync_start = 1366 + 16, 2556 .hsync_end = 1366 + 16 + 34, 2557 .htotal = 1366 + 16 + 34 + 50, 2558 .vdisplay = 768, 2559 .vsync_start = 768 + 2, 2560 .vsync_end = 768 + 2 + 6, 2561 .vtotal = 768 + 2 + 6 + 12, 2562 }; 2563 2564 static const struct panel_desc innolux_n156bge_l21 = { 2565 .modes = &innolux_n156bge_l21_mode, 2566 .num_modes = 1, 2567 .bpc = 6, 2568 .size = { 2569 .width = 344, 2570 .height = 193, 2571 }, 2572 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2573 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2574 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2575 }; 2576 2577 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2578 .clock = 51501, 2579 .hdisplay = 1024, 2580 .hsync_start = 1024 + 128, 2581 .hsync_end = 1024 + 128 + 64, 2582 .htotal = 1024 + 128 + 64 + 128, 2583 .vdisplay = 600, 2584 .vsync_start = 600 + 16, 2585 .vsync_end = 600 + 16 + 4, 2586 .vtotal = 600 + 16 + 4 + 16, 2587 }; 2588 2589 static const struct panel_desc innolux_zj070na_01p = { 2590 .modes = &innolux_zj070na_01p_mode, 2591 .num_modes = 1, 2592 .bpc = 6, 2593 .size = { 2594 .width = 154, 2595 .height = 90, 2596 }, 2597 }; 2598 2599 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2600 .pixelclock = { 5580000, 5850000, 6200000 }, 2601 .hactive = { 320, 320, 320 }, 2602 .hfront_porch = { 30, 30, 30 }, 2603 .hback_porch = { 30, 30, 30 }, 2604 .hsync_len = { 1, 5, 17 }, 2605 .vactive = { 240, 240, 240 }, 2606 .vfront_porch = { 6, 6, 6 }, 2607 .vback_porch = { 5, 5, 5 }, 2608 .vsync_len = { 1, 2, 11 }, 2609 .flags = DISPLAY_FLAGS_DE_HIGH, 2610 }; 2611 2612 static const struct panel_desc koe_tx14d24vm1bpa = { 2613 .timings = &koe_tx14d24vm1bpa_timing, 2614 .num_timings = 1, 2615 .bpc = 6, 2616 .size = { 2617 .width = 115, 2618 .height = 86, 2619 }, 2620 }; 2621 2622 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2623 .pixelclock = { 151820000, 156720000, 159780000 }, 2624 .hactive = { 1920, 1920, 1920 }, 2625 .hfront_porch = { 105, 130, 142 }, 2626 .hback_porch = { 45, 70, 82 }, 2627 .hsync_len = { 30, 30, 30 }, 2628 .vactive = { 1200, 1200, 1200}, 2629 .vfront_porch = { 3, 5, 10 }, 2630 .vback_porch = { 2, 5, 10 }, 2631 .vsync_len = { 5, 5, 5 }, 2632 }; 2633 2634 static const struct panel_desc koe_tx26d202vm0bwa = { 2635 .timings = &koe_tx26d202vm0bwa_timing, 2636 .num_timings = 1, 2637 .bpc = 8, 2638 .size = { 2639 .width = 217, 2640 .height = 136, 2641 }, 2642 .delay = { 2643 .prepare = 1000, 2644 .enable = 1000, 2645 .unprepare = 1000, 2646 .disable = 1000, 2647 }, 2648 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2649 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2650 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2651 }; 2652 2653 static const struct display_timing koe_tx31d200vm0baa_timing = { 2654 .pixelclock = { 39600000, 43200000, 48000000 }, 2655 .hactive = { 1280, 1280, 1280 }, 2656 .hfront_porch = { 16, 36, 56 }, 2657 .hback_porch = { 16, 36, 56 }, 2658 .hsync_len = { 8, 8, 8 }, 2659 .vactive = { 480, 480, 480 }, 2660 .vfront_porch = { 6, 21, 33 }, 2661 .vback_porch = { 6, 21, 33 }, 2662 .vsync_len = { 8, 8, 8 }, 2663 .flags = DISPLAY_FLAGS_DE_HIGH, 2664 }; 2665 2666 static const struct panel_desc koe_tx31d200vm0baa = { 2667 .timings = &koe_tx31d200vm0baa_timing, 2668 .num_timings = 1, 2669 .bpc = 6, 2670 .size = { 2671 .width = 292, 2672 .height = 109, 2673 }, 2674 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2675 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2676 }; 2677 2678 static const struct display_timing kyo_tcg121xglp_timing = { 2679 .pixelclock = { 52000000, 65000000, 71000000 }, 2680 .hactive = { 1024, 1024, 1024 }, 2681 .hfront_porch = { 2, 2, 2 }, 2682 .hback_porch = { 2, 2, 2 }, 2683 .hsync_len = { 86, 124, 244 }, 2684 .vactive = { 768, 768, 768 }, 2685 .vfront_porch = { 2, 2, 2 }, 2686 .vback_porch = { 2, 2, 2 }, 2687 .vsync_len = { 6, 34, 73 }, 2688 .flags = DISPLAY_FLAGS_DE_HIGH, 2689 }; 2690 2691 static const struct panel_desc kyo_tcg121xglp = { 2692 .timings = &kyo_tcg121xglp_timing, 2693 .num_timings = 1, 2694 .bpc = 8, 2695 .size = { 2696 .width = 246, 2697 .height = 184, 2698 }, 2699 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2700 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2701 }; 2702 2703 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2704 .clock = 7000, 2705 .hdisplay = 320, 2706 .hsync_start = 320 + 20, 2707 .hsync_end = 320 + 20 + 30, 2708 .htotal = 320 + 20 + 30 + 38, 2709 .vdisplay = 240, 2710 .vsync_start = 240 + 4, 2711 .vsync_end = 240 + 4 + 3, 2712 .vtotal = 240 + 4 + 3 + 15, 2713 }; 2714 2715 static const struct panel_desc lemaker_bl035_rgb_002 = { 2716 .modes = &lemaker_bl035_rgb_002_mode, 2717 .num_modes = 1, 2718 .size = { 2719 .width = 70, 2720 .height = 52, 2721 }, 2722 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2723 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2724 }; 2725 2726 static const struct drm_display_mode lg_lb070wv8_mode = { 2727 .clock = 33246, 2728 .hdisplay = 800, 2729 .hsync_start = 800 + 88, 2730 .hsync_end = 800 + 88 + 80, 2731 .htotal = 800 + 88 + 80 + 88, 2732 .vdisplay = 480, 2733 .vsync_start = 480 + 10, 2734 .vsync_end = 480 + 10 + 25, 2735 .vtotal = 480 + 10 + 25 + 10, 2736 }; 2737 2738 static const struct panel_desc lg_lb070wv8 = { 2739 .modes = &lg_lb070wv8_mode, 2740 .num_modes = 1, 2741 .bpc = 8, 2742 .size = { 2743 .width = 151, 2744 .height = 91, 2745 }, 2746 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2747 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2748 }; 2749 2750 static const struct display_timing logictechno_lt161010_2nh_timing = { 2751 .pixelclock = { 26400000, 33300000, 46800000 }, 2752 .hactive = { 800, 800, 800 }, 2753 .hfront_porch = { 16, 210, 354 }, 2754 .hback_porch = { 46, 46, 46 }, 2755 .hsync_len = { 1, 20, 40 }, 2756 .vactive = { 480, 480, 480 }, 2757 .vfront_porch = { 7, 22, 147 }, 2758 .vback_porch = { 23, 23, 23 }, 2759 .vsync_len = { 1, 10, 20 }, 2760 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2761 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2762 DISPLAY_FLAGS_SYNC_POSEDGE, 2763 }; 2764 2765 static const struct panel_desc logictechno_lt161010_2nh = { 2766 .timings = &logictechno_lt161010_2nh_timing, 2767 .num_timings = 1, 2768 .bpc = 6, 2769 .size = { 2770 .width = 154, 2771 .height = 86, 2772 }, 2773 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2774 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2775 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2776 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2777 .connector_type = DRM_MODE_CONNECTOR_DPI, 2778 }; 2779 2780 static const struct display_timing logictechno_lt170410_2whc_timing = { 2781 .pixelclock = { 68900000, 71100000, 73400000 }, 2782 .hactive = { 1280, 1280, 1280 }, 2783 .hfront_porch = { 23, 60, 71 }, 2784 .hback_porch = { 23, 60, 71 }, 2785 .hsync_len = { 15, 40, 47 }, 2786 .vactive = { 800, 800, 800 }, 2787 .vfront_porch = { 5, 7, 10 }, 2788 .vback_porch = { 5, 7, 10 }, 2789 .vsync_len = { 6, 9, 12 }, 2790 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2791 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2792 DISPLAY_FLAGS_SYNC_POSEDGE, 2793 }; 2794 2795 static const struct panel_desc logictechno_lt170410_2whc = { 2796 .timings = &logictechno_lt170410_2whc_timing, 2797 .num_timings = 1, 2798 .bpc = 8, 2799 .size = { 2800 .width = 217, 2801 .height = 136, 2802 }, 2803 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2804 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2805 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2806 }; 2807 2808 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2809 .clock = 33000, 2810 .hdisplay = 800, 2811 .hsync_start = 800 + 112, 2812 .hsync_end = 800 + 112 + 3, 2813 .htotal = 800 + 112 + 3 + 85, 2814 .vdisplay = 480, 2815 .vsync_start = 480 + 38, 2816 .vsync_end = 480 + 38 + 3, 2817 .vtotal = 480 + 38 + 3 + 29, 2818 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2819 }; 2820 2821 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2822 .modes = &logictechno_lttd800480070_l2rt_mode, 2823 .num_modes = 1, 2824 .bpc = 8, 2825 .size = { 2826 .width = 154, 2827 .height = 86, 2828 }, 2829 .delay = { 2830 .prepare = 45, 2831 .enable = 100, 2832 .disable = 100, 2833 .unprepare = 45 2834 }, 2835 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2836 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2837 .connector_type = DRM_MODE_CONNECTOR_DPI, 2838 }; 2839 2840 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2841 .clock = 33000, 2842 .hdisplay = 800, 2843 .hsync_start = 800 + 154, 2844 .hsync_end = 800 + 154 + 3, 2845 .htotal = 800 + 154 + 3 + 43, 2846 .vdisplay = 480, 2847 .vsync_start = 480 + 47, 2848 .vsync_end = 480 + 47 + 3, 2849 .vtotal = 480 + 47 + 3 + 20, 2850 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2851 }; 2852 2853 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2854 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2855 .num_modes = 1, 2856 .bpc = 8, 2857 .size = { 2858 .width = 154, 2859 .height = 86, 2860 }, 2861 .delay = { 2862 .prepare = 45, 2863 .enable = 100, 2864 .disable = 100, 2865 .unprepare = 45 2866 }, 2867 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2868 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2869 .connector_type = DRM_MODE_CONNECTOR_DPI, 2870 }; 2871 2872 static const struct drm_display_mode logicpd_type_28_mode = { 2873 .clock = 9107, 2874 .hdisplay = 480, 2875 .hsync_start = 480 + 3, 2876 .hsync_end = 480 + 3 + 42, 2877 .htotal = 480 + 3 + 42 + 2, 2878 2879 .vdisplay = 272, 2880 .vsync_start = 272 + 2, 2881 .vsync_end = 272 + 2 + 11, 2882 .vtotal = 272 + 2 + 11 + 3, 2883 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2884 }; 2885 2886 static const struct panel_desc logicpd_type_28 = { 2887 .modes = &logicpd_type_28_mode, 2888 .num_modes = 1, 2889 .bpc = 8, 2890 .size = { 2891 .width = 105, 2892 .height = 67, 2893 }, 2894 .delay = { 2895 .prepare = 200, 2896 .enable = 200, 2897 .unprepare = 200, 2898 .disable = 200, 2899 }, 2900 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2901 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2902 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2903 .connector_type = DRM_MODE_CONNECTOR_DPI, 2904 }; 2905 2906 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2907 .clock = 30400, 2908 .hdisplay = 800, 2909 .hsync_start = 800 + 0, 2910 .hsync_end = 800 + 1, 2911 .htotal = 800 + 0 + 1 + 160, 2912 .vdisplay = 480, 2913 .vsync_start = 480 + 0, 2914 .vsync_end = 480 + 48 + 1, 2915 .vtotal = 480 + 48 + 1 + 0, 2916 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2917 }; 2918 2919 static const struct panel_desc mitsubishi_aa070mc01 = { 2920 .modes = &mitsubishi_aa070mc01_mode, 2921 .num_modes = 1, 2922 .bpc = 8, 2923 .size = { 2924 .width = 152, 2925 .height = 91, 2926 }, 2927 2928 .delay = { 2929 .enable = 200, 2930 .unprepare = 200, 2931 .disable = 400, 2932 }, 2933 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2934 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2935 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2936 }; 2937 2938 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 2939 .clock = 56234, 2940 .hdisplay = 1024, 2941 .hsync_start = 1024 + 24, 2942 .hsync_end = 1024 + 24 + 63, 2943 .htotal = 1024 + 24 + 63 + 1, 2944 .vdisplay = 768, 2945 .vsync_start = 768 + 3, 2946 .vsync_end = 768 + 3 + 6, 2947 .vtotal = 768 + 3 + 6 + 1, 2948 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2949 }; 2950 2951 static const struct panel_desc mitsubishi_aa084xe01 = { 2952 .modes = &mitsubishi_aa084xe01_mode, 2953 .num_modes = 1, 2954 .bpc = 8, 2955 .size = { 2956 .width = 1024, 2957 .height = 768, 2958 }, 2959 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 2960 .connector_type = DRM_MODE_CONNECTOR_DPI, 2961 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2962 }; 2963 2964 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2965 .pixelclock = { 29000000, 33000000, 38000000 }, 2966 .hactive = { 800, 800, 800 }, 2967 .hfront_porch = { 180, 210, 240 }, 2968 .hback_porch = { 16, 16, 16 }, 2969 .hsync_len = { 30, 30, 30 }, 2970 .vactive = { 480, 480, 480 }, 2971 .vfront_porch = { 12, 22, 32 }, 2972 .vback_porch = { 10, 10, 10 }, 2973 .vsync_len = { 13, 13, 13 }, 2974 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2975 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2976 DISPLAY_FLAGS_SYNC_POSEDGE, 2977 }; 2978 2979 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2980 .timings = &multi_inno_mi0700s4t_6_timing, 2981 .num_timings = 1, 2982 .bpc = 8, 2983 .size = { 2984 .width = 154, 2985 .height = 86, 2986 }, 2987 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2988 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2989 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2990 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2991 .connector_type = DRM_MODE_CONNECTOR_DPI, 2992 }; 2993 2994 static const struct display_timing multi_inno_mi0800ft_9_timing = { 2995 .pixelclock = { 32000000, 40000000, 50000000 }, 2996 .hactive = { 800, 800, 800 }, 2997 .hfront_porch = { 16, 210, 354 }, 2998 .hback_porch = { 6, 26, 45 }, 2999 .hsync_len = { 1, 20, 40 }, 3000 .vactive = { 600, 600, 600 }, 3001 .vfront_porch = { 1, 12, 77 }, 3002 .vback_porch = { 3, 13, 22 }, 3003 .vsync_len = { 1, 10, 20 }, 3004 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3005 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3006 DISPLAY_FLAGS_SYNC_POSEDGE, 3007 }; 3008 3009 static const struct panel_desc multi_inno_mi0800ft_9 = { 3010 .timings = &multi_inno_mi0800ft_9_timing, 3011 .num_timings = 1, 3012 .bpc = 8, 3013 .size = { 3014 .width = 162, 3015 .height = 122, 3016 }, 3017 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3018 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3019 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3020 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3021 .connector_type = DRM_MODE_CONNECTOR_DPI, 3022 }; 3023 3024 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3025 .pixelclock = { 68900000, 70000000, 73400000 }, 3026 .hactive = { 1280, 1280, 1280 }, 3027 .hfront_porch = { 30, 60, 71 }, 3028 .hback_porch = { 30, 60, 71 }, 3029 .hsync_len = { 10, 10, 48 }, 3030 .vactive = { 800, 800, 800 }, 3031 .vfront_porch = { 5, 10, 10 }, 3032 .vback_porch = { 5, 10, 10 }, 3033 .vsync_len = { 5, 6, 13 }, 3034 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3035 DISPLAY_FLAGS_DE_HIGH, 3036 }; 3037 3038 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3039 .timings = &multi_inno_mi1010ait_1cp_timing, 3040 .num_timings = 1, 3041 .bpc = 8, 3042 .size = { 3043 .width = 217, 3044 .height = 136, 3045 }, 3046 .delay = { 3047 .enable = 50, 3048 .disable = 50, 3049 }, 3050 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3051 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3052 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3053 }; 3054 3055 static const struct display_timing nec_nl12880bc20_05_timing = { 3056 .pixelclock = { 67000000, 71000000, 75000000 }, 3057 .hactive = { 1280, 1280, 1280 }, 3058 .hfront_porch = { 2, 30, 30 }, 3059 .hback_porch = { 6, 100, 100 }, 3060 .hsync_len = { 2, 30, 30 }, 3061 .vactive = { 800, 800, 800 }, 3062 .vfront_porch = { 5, 5, 5 }, 3063 .vback_porch = { 11, 11, 11 }, 3064 .vsync_len = { 7, 7, 7 }, 3065 }; 3066 3067 static const struct panel_desc nec_nl12880bc20_05 = { 3068 .timings = &nec_nl12880bc20_05_timing, 3069 .num_timings = 1, 3070 .bpc = 8, 3071 .size = { 3072 .width = 261, 3073 .height = 163, 3074 }, 3075 .delay = { 3076 .enable = 50, 3077 .disable = 50, 3078 }, 3079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3080 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3081 }; 3082 3083 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3084 .clock = 10870, 3085 .hdisplay = 480, 3086 .hsync_start = 480 + 2, 3087 .hsync_end = 480 + 2 + 41, 3088 .htotal = 480 + 2 + 41 + 2, 3089 .vdisplay = 272, 3090 .vsync_start = 272 + 2, 3091 .vsync_end = 272 + 2 + 4, 3092 .vtotal = 272 + 2 + 4 + 2, 3093 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3094 }; 3095 3096 static const struct panel_desc nec_nl4827hc19_05b = { 3097 .modes = &nec_nl4827hc19_05b_mode, 3098 .num_modes = 1, 3099 .bpc = 8, 3100 .size = { 3101 .width = 95, 3102 .height = 54, 3103 }, 3104 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3105 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3106 }; 3107 3108 static const struct drm_display_mode netron_dy_e231732_mode = { 3109 .clock = 66000, 3110 .hdisplay = 1024, 3111 .hsync_start = 1024 + 160, 3112 .hsync_end = 1024 + 160 + 70, 3113 .htotal = 1024 + 160 + 70 + 90, 3114 .vdisplay = 600, 3115 .vsync_start = 600 + 127, 3116 .vsync_end = 600 + 127 + 20, 3117 .vtotal = 600 + 127 + 20 + 3, 3118 }; 3119 3120 static const struct panel_desc netron_dy_e231732 = { 3121 .modes = &netron_dy_e231732_mode, 3122 .num_modes = 1, 3123 .size = { 3124 .width = 154, 3125 .height = 87, 3126 }, 3127 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3128 }; 3129 3130 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3131 .clock = 9000, 3132 .hdisplay = 480, 3133 .hsync_start = 480 + 2, 3134 .hsync_end = 480 + 2 + 41, 3135 .htotal = 480 + 2 + 41 + 2, 3136 .vdisplay = 272, 3137 .vsync_start = 272 + 2, 3138 .vsync_end = 272 + 2 + 10, 3139 .vtotal = 272 + 2 + 10 + 2, 3140 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3141 }; 3142 3143 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3144 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3145 .num_modes = 1, 3146 .bpc = 8, 3147 .size = { 3148 .width = 95, 3149 .height = 54, 3150 }, 3151 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3152 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3153 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3154 .connector_type = DRM_MODE_CONNECTOR_DPI, 3155 }; 3156 3157 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3158 .pixelclock = { 130000000, 148350000, 163000000 }, 3159 .hactive = { 1920, 1920, 1920 }, 3160 .hfront_porch = { 80, 100, 100 }, 3161 .hback_porch = { 100, 120, 120 }, 3162 .hsync_len = { 50, 60, 60 }, 3163 .vactive = { 1080, 1080, 1080 }, 3164 .vfront_porch = { 12, 30, 30 }, 3165 .vback_porch = { 4, 10, 10 }, 3166 .vsync_len = { 4, 5, 5 }, 3167 }; 3168 3169 static const struct panel_desc nlt_nl192108ac18_02d = { 3170 .timings = &nlt_nl192108ac18_02d_timing, 3171 .num_timings = 1, 3172 .bpc = 8, 3173 .size = { 3174 .width = 344, 3175 .height = 194, 3176 }, 3177 .delay = { 3178 .unprepare = 500, 3179 }, 3180 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3181 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3182 }; 3183 3184 static const struct drm_display_mode nvd_9128_mode = { 3185 .clock = 29500, 3186 .hdisplay = 800, 3187 .hsync_start = 800 + 130, 3188 .hsync_end = 800 + 130 + 98, 3189 .htotal = 800 + 0 + 130 + 98, 3190 .vdisplay = 480, 3191 .vsync_start = 480 + 10, 3192 .vsync_end = 480 + 10 + 50, 3193 .vtotal = 480 + 0 + 10 + 50, 3194 }; 3195 3196 static const struct panel_desc nvd_9128 = { 3197 .modes = &nvd_9128_mode, 3198 .num_modes = 1, 3199 .bpc = 8, 3200 .size = { 3201 .width = 156, 3202 .height = 88, 3203 }, 3204 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3205 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3206 }; 3207 3208 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3209 .pixelclock = { 30000000, 30000000, 40000000 }, 3210 .hactive = { 800, 800, 800 }, 3211 .hfront_porch = { 40, 40, 40 }, 3212 .hback_porch = { 40, 40, 40 }, 3213 .hsync_len = { 1, 48, 48 }, 3214 .vactive = { 480, 480, 480 }, 3215 .vfront_porch = { 13, 13, 13 }, 3216 .vback_porch = { 29, 29, 29 }, 3217 .vsync_len = { 3, 3, 3 }, 3218 .flags = DISPLAY_FLAGS_DE_HIGH, 3219 }; 3220 3221 static const struct panel_desc okaya_rs800480t_7x0gp = { 3222 .timings = &okaya_rs800480t_7x0gp_timing, 3223 .num_timings = 1, 3224 .bpc = 6, 3225 .size = { 3226 .width = 154, 3227 .height = 87, 3228 }, 3229 .delay = { 3230 .prepare = 41, 3231 .enable = 50, 3232 .unprepare = 41, 3233 .disable = 50, 3234 }, 3235 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3236 }; 3237 3238 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3239 .clock = 9000, 3240 .hdisplay = 480, 3241 .hsync_start = 480 + 5, 3242 .hsync_end = 480 + 5 + 30, 3243 .htotal = 480 + 5 + 30 + 10, 3244 .vdisplay = 272, 3245 .vsync_start = 272 + 8, 3246 .vsync_end = 272 + 8 + 5, 3247 .vtotal = 272 + 8 + 5 + 3, 3248 }; 3249 3250 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3251 .modes = &olimex_lcd_olinuxino_43ts_mode, 3252 .num_modes = 1, 3253 .size = { 3254 .width = 95, 3255 .height = 54, 3256 }, 3257 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3258 }; 3259 3260 /* 3261 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3262 * pixel clocks, but this is the timing that was being used in the Adafruit 3263 * installation instructions. 3264 */ 3265 static const struct drm_display_mode ontat_yx700wv03_mode = { 3266 .clock = 29500, 3267 .hdisplay = 800, 3268 .hsync_start = 824, 3269 .hsync_end = 896, 3270 .htotal = 992, 3271 .vdisplay = 480, 3272 .vsync_start = 483, 3273 .vsync_end = 493, 3274 .vtotal = 500, 3275 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3276 }; 3277 3278 /* 3279 * Specification at: 3280 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3281 */ 3282 static const struct panel_desc ontat_yx700wv03 = { 3283 .modes = &ontat_yx700wv03_mode, 3284 .num_modes = 1, 3285 .bpc = 8, 3286 .size = { 3287 .width = 154, 3288 .height = 83, 3289 }, 3290 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3291 }; 3292 3293 static const struct drm_display_mode ortustech_com37h3m_mode = { 3294 .clock = 22230, 3295 .hdisplay = 480, 3296 .hsync_start = 480 + 40, 3297 .hsync_end = 480 + 40 + 10, 3298 .htotal = 480 + 40 + 10 + 40, 3299 .vdisplay = 640, 3300 .vsync_start = 640 + 4, 3301 .vsync_end = 640 + 4 + 2, 3302 .vtotal = 640 + 4 + 2 + 4, 3303 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3304 }; 3305 3306 static const struct panel_desc ortustech_com37h3m = { 3307 .modes = &ortustech_com37h3m_mode, 3308 .num_modes = 1, 3309 .bpc = 8, 3310 .size = { 3311 .width = 56, /* 56.16mm */ 3312 .height = 75, /* 74.88mm */ 3313 }, 3314 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3315 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3316 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3317 }; 3318 3319 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3320 .clock = 25000, 3321 .hdisplay = 480, 3322 .hsync_start = 480 + 10, 3323 .hsync_end = 480 + 10 + 10, 3324 .htotal = 480 + 10 + 10 + 15, 3325 .vdisplay = 800, 3326 .vsync_start = 800 + 3, 3327 .vsync_end = 800 + 3 + 3, 3328 .vtotal = 800 + 3 + 3 + 3, 3329 }; 3330 3331 static const struct panel_desc ortustech_com43h4m85ulc = { 3332 .modes = &ortustech_com43h4m85ulc_mode, 3333 .num_modes = 1, 3334 .bpc = 6, 3335 .size = { 3336 .width = 56, 3337 .height = 93, 3338 }, 3339 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3340 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3341 .connector_type = DRM_MODE_CONNECTOR_DPI, 3342 }; 3343 3344 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3345 .clock = 33000, 3346 .hdisplay = 800, 3347 .hsync_start = 800 + 210, 3348 .hsync_end = 800 + 210 + 30, 3349 .htotal = 800 + 210 + 30 + 16, 3350 .vdisplay = 480, 3351 .vsync_start = 480 + 22, 3352 .vsync_end = 480 + 22 + 13, 3353 .vtotal = 480 + 22 + 13 + 10, 3354 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3355 }; 3356 3357 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3358 .modes = &osddisplays_osd070t1718_19ts_mode, 3359 .num_modes = 1, 3360 .bpc = 8, 3361 .size = { 3362 .width = 152, 3363 .height = 91, 3364 }, 3365 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3366 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3367 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3368 .connector_type = DRM_MODE_CONNECTOR_DPI, 3369 }; 3370 3371 static const struct drm_display_mode pda_91_00156_a0_mode = { 3372 .clock = 33300, 3373 .hdisplay = 800, 3374 .hsync_start = 800 + 1, 3375 .hsync_end = 800 + 1 + 64, 3376 .htotal = 800 + 1 + 64 + 64, 3377 .vdisplay = 480, 3378 .vsync_start = 480 + 1, 3379 .vsync_end = 480 + 1 + 23, 3380 .vtotal = 480 + 1 + 23 + 22, 3381 }; 3382 3383 static const struct panel_desc pda_91_00156_a0 = { 3384 .modes = &pda_91_00156_a0_mode, 3385 .num_modes = 1, 3386 .size = { 3387 .width = 152, 3388 .height = 91, 3389 }, 3390 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3391 }; 3392 3393 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3394 .clock = 24750, 3395 .hdisplay = 800, 3396 .hsync_start = 800 + 54, 3397 .hsync_end = 800 + 54 + 2, 3398 .htotal = 800 + 54 + 2 + 44, 3399 .vdisplay = 480, 3400 .vsync_start = 480 + 49, 3401 .vsync_end = 480 + 49 + 2, 3402 .vtotal = 480 + 49 + 2 + 22, 3403 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3404 }; 3405 3406 static const struct panel_desc powertip_ph800480t013_idf02 = { 3407 .modes = &powertip_ph800480t013_idf02_mode, 3408 .num_modes = 1, 3409 .bpc = 8, 3410 .size = { 3411 .width = 152, 3412 .height = 91, 3413 }, 3414 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3415 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3416 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3417 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3418 .connector_type = DRM_MODE_CONNECTOR_DPI, 3419 }; 3420 3421 static const struct drm_display_mode qd43003c0_40_mode = { 3422 .clock = 9000, 3423 .hdisplay = 480, 3424 .hsync_start = 480 + 8, 3425 .hsync_end = 480 + 8 + 4, 3426 .htotal = 480 + 8 + 4 + 39, 3427 .vdisplay = 272, 3428 .vsync_start = 272 + 4, 3429 .vsync_end = 272 + 4 + 10, 3430 .vtotal = 272 + 4 + 10 + 2, 3431 }; 3432 3433 static const struct panel_desc qd43003c0_40 = { 3434 .modes = &qd43003c0_40_mode, 3435 .num_modes = 1, 3436 .bpc = 8, 3437 .size = { 3438 .width = 95, 3439 .height = 53, 3440 }, 3441 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3442 }; 3443 3444 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3445 { /* 60 Hz */ 3446 .clock = 10800, 3447 .hdisplay = 480, 3448 .hsync_start = 480 + 77, 3449 .hsync_end = 480 + 77 + 41, 3450 .htotal = 480 + 77 + 41 + 2, 3451 .vdisplay = 272, 3452 .vsync_start = 272 + 16, 3453 .vsync_end = 272 + 16 + 10, 3454 .vtotal = 272 + 16 + 10 + 2, 3455 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3456 }, 3457 { /* 50 Hz */ 3458 .clock = 10800, 3459 .hdisplay = 480, 3460 .hsync_start = 480 + 17, 3461 .hsync_end = 480 + 17 + 41, 3462 .htotal = 480 + 17 + 41 + 2, 3463 .vdisplay = 272, 3464 .vsync_start = 272 + 116, 3465 .vsync_end = 272 + 116 + 10, 3466 .vtotal = 272 + 116 + 10 + 2, 3467 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3468 }, 3469 }; 3470 3471 static const struct panel_desc qishenglong_gopher2b_lcd = { 3472 .modes = qishenglong_gopher2b_lcd_modes, 3473 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3474 .bpc = 8, 3475 .size = { 3476 .width = 95, 3477 .height = 54, 3478 }, 3479 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3480 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3481 .connector_type = DRM_MODE_CONNECTOR_DPI, 3482 }; 3483 3484 static const struct display_timing rocktech_rk043fn48h_timing = { 3485 .pixelclock = { 6000000, 9000000, 12000000 }, 3486 .hactive = { 480, 480, 480 }, 3487 .hback_porch = { 8, 43, 43 }, 3488 .hfront_porch = { 2, 8, 8 }, 3489 .hsync_len = { 1, 1, 1 }, 3490 .vactive = { 272, 272, 272 }, 3491 .vback_porch = { 2, 12, 12 }, 3492 .vfront_porch = { 1, 4, 4 }, 3493 .vsync_len = { 1, 10, 10 }, 3494 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3495 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3496 }; 3497 3498 static const struct panel_desc rocktech_rk043fn48h = { 3499 .timings = &rocktech_rk043fn48h_timing, 3500 .num_timings = 1, 3501 .bpc = 8, 3502 .size = { 3503 .width = 95, 3504 .height = 54, 3505 }, 3506 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3507 .connector_type = DRM_MODE_CONNECTOR_DPI, 3508 }; 3509 3510 static const struct display_timing rocktech_rk070er9427_timing = { 3511 .pixelclock = { 26400000, 33300000, 46800000 }, 3512 .hactive = { 800, 800, 800 }, 3513 .hfront_porch = { 16, 210, 354 }, 3514 .hback_porch = { 46, 46, 46 }, 3515 .hsync_len = { 1, 1, 1 }, 3516 .vactive = { 480, 480, 480 }, 3517 .vfront_porch = { 7, 22, 147 }, 3518 .vback_porch = { 23, 23, 23 }, 3519 .vsync_len = { 1, 1, 1 }, 3520 .flags = DISPLAY_FLAGS_DE_HIGH, 3521 }; 3522 3523 static const struct panel_desc rocktech_rk070er9427 = { 3524 .timings = &rocktech_rk070er9427_timing, 3525 .num_timings = 1, 3526 .bpc = 6, 3527 .size = { 3528 .width = 154, 3529 .height = 86, 3530 }, 3531 .delay = { 3532 .prepare = 41, 3533 .enable = 50, 3534 .unprepare = 41, 3535 .disable = 50, 3536 }, 3537 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3538 }; 3539 3540 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3541 .clock = 71100, 3542 .hdisplay = 1280, 3543 .hsync_start = 1280 + 48, 3544 .hsync_end = 1280 + 48 + 32, 3545 .htotal = 1280 + 48 + 32 + 80, 3546 .vdisplay = 800, 3547 .vsync_start = 800 + 2, 3548 .vsync_end = 800 + 2 + 5, 3549 .vtotal = 800 + 2 + 5 + 16, 3550 }; 3551 3552 static const struct panel_desc rocktech_rk101ii01d_ct = { 3553 .modes = &rocktech_rk101ii01d_ct_mode, 3554 .bpc = 8, 3555 .num_modes = 1, 3556 .size = { 3557 .width = 217, 3558 .height = 136, 3559 }, 3560 .delay = { 3561 .prepare = 50, 3562 .disable = 50, 3563 }, 3564 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3565 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3566 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3567 }; 3568 3569 static const struct display_timing samsung_ltl101al01_timing = { 3570 .pixelclock = { 66663000, 66663000, 66663000 }, 3571 .hactive = { 1280, 1280, 1280 }, 3572 .hfront_porch = { 18, 18, 18 }, 3573 .hback_porch = { 36, 36, 36 }, 3574 .hsync_len = { 16, 16, 16 }, 3575 .vactive = { 800, 800, 800 }, 3576 .vfront_porch = { 4, 4, 4 }, 3577 .vback_porch = { 16, 16, 16 }, 3578 .vsync_len = { 3, 3, 3 }, 3579 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3580 }; 3581 3582 static const struct panel_desc samsung_ltl101al01 = { 3583 .timings = &samsung_ltl101al01_timing, 3584 .num_timings = 1, 3585 .bpc = 8, 3586 .size = { 3587 .width = 217, 3588 .height = 135, 3589 }, 3590 .delay = { 3591 .prepare = 40, 3592 .enable = 300, 3593 .disable = 200, 3594 .unprepare = 600, 3595 }, 3596 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3597 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3598 }; 3599 3600 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3601 .clock = 54030, 3602 .hdisplay = 1024, 3603 .hsync_start = 1024 + 24, 3604 .hsync_end = 1024 + 24 + 136, 3605 .htotal = 1024 + 24 + 136 + 160, 3606 .vdisplay = 600, 3607 .vsync_start = 600 + 3, 3608 .vsync_end = 600 + 3 + 6, 3609 .vtotal = 600 + 3 + 6 + 61, 3610 }; 3611 3612 static const struct panel_desc samsung_ltn101nt05 = { 3613 .modes = &samsung_ltn101nt05_mode, 3614 .num_modes = 1, 3615 .bpc = 6, 3616 .size = { 3617 .width = 223, 3618 .height = 125, 3619 }, 3620 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3621 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3622 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3623 }; 3624 3625 static const struct display_timing satoz_sat050at40h12r2_timing = { 3626 .pixelclock = {33300000, 33300000, 50000000}, 3627 .hactive = {800, 800, 800}, 3628 .hfront_porch = {16, 210, 354}, 3629 .hback_porch = {46, 46, 46}, 3630 .hsync_len = {1, 1, 40}, 3631 .vactive = {480, 480, 480}, 3632 .vfront_porch = {7, 22, 147}, 3633 .vback_porch = {23, 23, 23}, 3634 .vsync_len = {1, 1, 20}, 3635 }; 3636 3637 static const struct panel_desc satoz_sat050at40h12r2 = { 3638 .timings = &satoz_sat050at40h12r2_timing, 3639 .num_timings = 1, 3640 .bpc = 8, 3641 .size = { 3642 .width = 108, 3643 .height = 65, 3644 }, 3645 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3646 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3647 }; 3648 3649 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3650 .clock = 33260, 3651 .hdisplay = 800, 3652 .hsync_start = 800 + 64, 3653 .hsync_end = 800 + 64 + 128, 3654 .htotal = 800 + 64 + 128 + 64, 3655 .vdisplay = 480, 3656 .vsync_start = 480 + 8, 3657 .vsync_end = 480 + 8 + 2, 3658 .vtotal = 480 + 8 + 2 + 35, 3659 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3660 }; 3661 3662 static const struct panel_desc sharp_lq070y3dg3b = { 3663 .modes = &sharp_lq070y3dg3b_mode, 3664 .num_modes = 1, 3665 .bpc = 8, 3666 .size = { 3667 .width = 152, /* 152.4mm */ 3668 .height = 91, /* 91.4mm */ 3669 }, 3670 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3671 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3672 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3673 }; 3674 3675 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3676 .clock = 5500, 3677 .hdisplay = 240, 3678 .hsync_start = 240 + 16, 3679 .hsync_end = 240 + 16 + 7, 3680 .htotal = 240 + 16 + 7 + 5, 3681 .vdisplay = 320, 3682 .vsync_start = 320 + 9, 3683 .vsync_end = 320 + 9 + 1, 3684 .vtotal = 320 + 9 + 1 + 7, 3685 }; 3686 3687 static const struct panel_desc sharp_lq035q7db03 = { 3688 .modes = &sharp_lq035q7db03_mode, 3689 .num_modes = 1, 3690 .bpc = 6, 3691 .size = { 3692 .width = 54, 3693 .height = 72, 3694 }, 3695 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3696 }; 3697 3698 static const struct display_timing sharp_lq101k1ly04_timing = { 3699 .pixelclock = { 60000000, 65000000, 80000000 }, 3700 .hactive = { 1280, 1280, 1280 }, 3701 .hfront_porch = { 20, 20, 20 }, 3702 .hback_porch = { 20, 20, 20 }, 3703 .hsync_len = { 10, 10, 10 }, 3704 .vactive = { 800, 800, 800 }, 3705 .vfront_porch = { 4, 4, 4 }, 3706 .vback_porch = { 4, 4, 4 }, 3707 .vsync_len = { 4, 4, 4 }, 3708 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3709 }; 3710 3711 static const struct panel_desc sharp_lq101k1ly04 = { 3712 .timings = &sharp_lq101k1ly04_timing, 3713 .num_timings = 1, 3714 .bpc = 8, 3715 .size = { 3716 .width = 217, 3717 .height = 136, 3718 }, 3719 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3720 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3721 }; 3722 3723 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3724 { /* 50 Hz */ 3725 .clock = 3000, 3726 .hdisplay = 240, 3727 .hsync_start = 240 + 58, 3728 .hsync_end = 240 + 58 + 1, 3729 .htotal = 240 + 58 + 1 + 1, 3730 .vdisplay = 160, 3731 .vsync_start = 160 + 24, 3732 .vsync_end = 160 + 24 + 10, 3733 .vtotal = 160 + 24 + 10 + 6, 3734 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3735 }, 3736 { /* 60 Hz */ 3737 .clock = 3000, 3738 .hdisplay = 240, 3739 .hsync_start = 240 + 8, 3740 .hsync_end = 240 + 8 + 1, 3741 .htotal = 240 + 8 + 1 + 1, 3742 .vdisplay = 160, 3743 .vsync_start = 160 + 24, 3744 .vsync_end = 160 + 24 + 10, 3745 .vtotal = 160 + 24 + 10 + 6, 3746 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3747 }, 3748 }; 3749 3750 static const struct panel_desc sharp_ls020b1dd01d = { 3751 .modes = sharp_ls020b1dd01d_modes, 3752 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3753 .bpc = 6, 3754 .size = { 3755 .width = 42, 3756 .height = 28, 3757 }, 3758 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3759 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3760 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3761 | DRM_BUS_FLAG_SHARP_SIGNALS, 3762 }; 3763 3764 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3765 .clock = 33300, 3766 .hdisplay = 800, 3767 .hsync_start = 800 + 1, 3768 .hsync_end = 800 + 1 + 64, 3769 .htotal = 800 + 1 + 64 + 64, 3770 .vdisplay = 480, 3771 .vsync_start = 480 + 1, 3772 .vsync_end = 480 + 1 + 23, 3773 .vtotal = 480 + 1 + 23 + 22, 3774 }; 3775 3776 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3777 .modes = &shelly_sca07010_bfn_lnn_mode, 3778 .num_modes = 1, 3779 .size = { 3780 .width = 152, 3781 .height = 91, 3782 }, 3783 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3784 }; 3785 3786 static const struct drm_display_mode starry_kr070pe2t_mode = { 3787 .clock = 33000, 3788 .hdisplay = 800, 3789 .hsync_start = 800 + 209, 3790 .hsync_end = 800 + 209 + 1, 3791 .htotal = 800 + 209 + 1 + 45, 3792 .vdisplay = 480, 3793 .vsync_start = 480 + 22, 3794 .vsync_end = 480 + 22 + 1, 3795 .vtotal = 480 + 22 + 1 + 22, 3796 }; 3797 3798 static const struct panel_desc starry_kr070pe2t = { 3799 .modes = &starry_kr070pe2t_mode, 3800 .num_modes = 1, 3801 .bpc = 8, 3802 .size = { 3803 .width = 152, 3804 .height = 86, 3805 }, 3806 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3807 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3808 .connector_type = DRM_MODE_CONNECTOR_DPI, 3809 }; 3810 3811 static const struct display_timing startek_kd070wvfpa_mode = { 3812 .pixelclock = { 25200000, 27200000, 30500000 }, 3813 .hactive = { 800, 800, 800 }, 3814 .hfront_porch = { 19, 44, 115 }, 3815 .hback_porch = { 5, 16, 101 }, 3816 .hsync_len = { 1, 2, 100 }, 3817 .vactive = { 480, 480, 480 }, 3818 .vfront_porch = { 5, 43, 67 }, 3819 .vback_porch = { 5, 5, 67 }, 3820 .vsync_len = { 1, 2, 66 }, 3821 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3822 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3823 DISPLAY_FLAGS_SYNC_POSEDGE, 3824 }; 3825 3826 static const struct panel_desc startek_kd070wvfpa = { 3827 .timings = &startek_kd070wvfpa_mode, 3828 .num_timings = 1, 3829 .bpc = 8, 3830 .size = { 3831 .width = 152, 3832 .height = 91, 3833 }, 3834 .delay = { 3835 .prepare = 20, 3836 .enable = 200, 3837 .disable = 200, 3838 }, 3839 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3840 .connector_type = DRM_MODE_CONNECTOR_DPI, 3841 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3842 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3843 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3844 }; 3845 3846 static const struct display_timing tsd_tst043015cmhx_timing = { 3847 .pixelclock = { 5000000, 9000000, 12000000 }, 3848 .hactive = { 480, 480, 480 }, 3849 .hfront_porch = { 4, 5, 65 }, 3850 .hback_porch = { 36, 40, 255 }, 3851 .hsync_len = { 1, 1, 1 }, 3852 .vactive = { 272, 272, 272 }, 3853 .vfront_porch = { 2, 8, 97 }, 3854 .vback_porch = { 3, 8, 31 }, 3855 .vsync_len = { 1, 1, 1 }, 3856 3857 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3858 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3859 }; 3860 3861 static const struct panel_desc tsd_tst043015cmhx = { 3862 .timings = &tsd_tst043015cmhx_timing, 3863 .num_timings = 1, 3864 .bpc = 8, 3865 .size = { 3866 .width = 105, 3867 .height = 67, 3868 }, 3869 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3870 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3871 }; 3872 3873 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3874 .clock = 30000, 3875 .hdisplay = 800, 3876 .hsync_start = 800 + 39, 3877 .hsync_end = 800 + 39 + 47, 3878 .htotal = 800 + 39 + 47 + 39, 3879 .vdisplay = 480, 3880 .vsync_start = 480 + 13, 3881 .vsync_end = 480 + 13 + 2, 3882 .vtotal = 480 + 13 + 2 + 29, 3883 }; 3884 3885 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3886 .modes = &tfc_s9700rtwv43tr_01b_mode, 3887 .num_modes = 1, 3888 .bpc = 8, 3889 .size = { 3890 .width = 155, 3891 .height = 90, 3892 }, 3893 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3894 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3895 }; 3896 3897 static const struct display_timing tianma_tm070jdhg30_timing = { 3898 .pixelclock = { 62600000, 68200000, 78100000 }, 3899 .hactive = { 1280, 1280, 1280 }, 3900 .hfront_porch = { 15, 64, 159 }, 3901 .hback_porch = { 5, 5, 5 }, 3902 .hsync_len = { 1, 1, 256 }, 3903 .vactive = { 800, 800, 800 }, 3904 .vfront_porch = { 3, 40, 99 }, 3905 .vback_porch = { 2, 2, 2 }, 3906 .vsync_len = { 1, 1, 128 }, 3907 .flags = DISPLAY_FLAGS_DE_HIGH, 3908 }; 3909 3910 static const struct panel_desc tianma_tm070jdhg30 = { 3911 .timings = &tianma_tm070jdhg30_timing, 3912 .num_timings = 1, 3913 .bpc = 8, 3914 .size = { 3915 .width = 151, 3916 .height = 95, 3917 }, 3918 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3919 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3920 }; 3921 3922 static const struct panel_desc tianma_tm070jvhg33 = { 3923 .timings = &tianma_tm070jdhg30_timing, 3924 .num_timings = 1, 3925 .bpc = 8, 3926 .size = { 3927 .width = 150, 3928 .height = 94, 3929 }, 3930 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3931 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3932 }; 3933 3934 static const struct display_timing tianma_tm070rvhg71_timing = { 3935 .pixelclock = { 27700000, 29200000, 39600000 }, 3936 .hactive = { 800, 800, 800 }, 3937 .hfront_porch = { 12, 40, 212 }, 3938 .hback_porch = { 88, 88, 88 }, 3939 .hsync_len = { 1, 1, 40 }, 3940 .vactive = { 480, 480, 480 }, 3941 .vfront_porch = { 1, 13, 88 }, 3942 .vback_porch = { 32, 32, 32 }, 3943 .vsync_len = { 1, 1, 3 }, 3944 .flags = DISPLAY_FLAGS_DE_HIGH, 3945 }; 3946 3947 static const struct panel_desc tianma_tm070rvhg71 = { 3948 .timings = &tianma_tm070rvhg71_timing, 3949 .num_timings = 1, 3950 .bpc = 8, 3951 .size = { 3952 .width = 154, 3953 .height = 86, 3954 }, 3955 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3956 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3957 }; 3958 3959 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3960 { 3961 .clock = 10000, 3962 .hdisplay = 320, 3963 .hsync_start = 320 + 50, 3964 .hsync_end = 320 + 50 + 6, 3965 .htotal = 320 + 50 + 6 + 38, 3966 .vdisplay = 240, 3967 .vsync_start = 240 + 3, 3968 .vsync_end = 240 + 3 + 1, 3969 .vtotal = 240 + 3 + 1 + 17, 3970 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3971 }, 3972 }; 3973 3974 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3975 .modes = ti_nspire_cx_lcd_mode, 3976 .num_modes = 1, 3977 .bpc = 8, 3978 .size = { 3979 .width = 65, 3980 .height = 49, 3981 }, 3982 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3983 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3984 }; 3985 3986 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3987 { 3988 .clock = 10000, 3989 .hdisplay = 320, 3990 .hsync_start = 320 + 6, 3991 .hsync_end = 320 + 6 + 6, 3992 .htotal = 320 + 6 + 6 + 6, 3993 .vdisplay = 240, 3994 .vsync_start = 240 + 0, 3995 .vsync_end = 240 + 0 + 1, 3996 .vtotal = 240 + 0 + 1 + 0, 3997 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3998 }, 3999 }; 4000 4001 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4002 .modes = ti_nspire_classic_lcd_mode, 4003 .num_modes = 1, 4004 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4005 .bpc = 8, 4006 .size = { 4007 .width = 71, 4008 .height = 53, 4009 }, 4010 /* This is the grayscale bus format */ 4011 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4012 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4013 }; 4014 4015 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4016 .clock = 79500, 4017 .hdisplay = 1280, 4018 .hsync_start = 1280 + 192, 4019 .hsync_end = 1280 + 192 + 128, 4020 .htotal = 1280 + 192 + 128 + 64, 4021 .vdisplay = 768, 4022 .vsync_start = 768 + 20, 4023 .vsync_end = 768 + 20 + 7, 4024 .vtotal = 768 + 20 + 7 + 3, 4025 }; 4026 4027 static const struct panel_desc toshiba_lt089ac29000 = { 4028 .modes = &toshiba_lt089ac29000_mode, 4029 .num_modes = 1, 4030 .size = { 4031 .width = 194, 4032 .height = 116, 4033 }, 4034 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4035 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4036 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4037 }; 4038 4039 static const struct drm_display_mode tpk_f07a_0102_mode = { 4040 .clock = 33260, 4041 .hdisplay = 800, 4042 .hsync_start = 800 + 40, 4043 .hsync_end = 800 + 40 + 128, 4044 .htotal = 800 + 40 + 128 + 88, 4045 .vdisplay = 480, 4046 .vsync_start = 480 + 10, 4047 .vsync_end = 480 + 10 + 2, 4048 .vtotal = 480 + 10 + 2 + 33, 4049 }; 4050 4051 static const struct panel_desc tpk_f07a_0102 = { 4052 .modes = &tpk_f07a_0102_mode, 4053 .num_modes = 1, 4054 .size = { 4055 .width = 152, 4056 .height = 91, 4057 }, 4058 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4059 }; 4060 4061 static const struct drm_display_mode tpk_f10a_0102_mode = { 4062 .clock = 45000, 4063 .hdisplay = 1024, 4064 .hsync_start = 1024 + 176, 4065 .hsync_end = 1024 + 176 + 5, 4066 .htotal = 1024 + 176 + 5 + 88, 4067 .vdisplay = 600, 4068 .vsync_start = 600 + 20, 4069 .vsync_end = 600 + 20 + 5, 4070 .vtotal = 600 + 20 + 5 + 25, 4071 }; 4072 4073 static const struct panel_desc tpk_f10a_0102 = { 4074 .modes = &tpk_f10a_0102_mode, 4075 .num_modes = 1, 4076 .size = { 4077 .width = 223, 4078 .height = 125, 4079 }, 4080 }; 4081 4082 static const struct display_timing urt_umsh_8596md_timing = { 4083 .pixelclock = { 33260000, 33260000, 33260000 }, 4084 .hactive = { 800, 800, 800 }, 4085 .hfront_porch = { 41, 41, 41 }, 4086 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4087 .hsync_len = { 71, 128, 128 }, 4088 .vactive = { 480, 480, 480 }, 4089 .vfront_porch = { 10, 10, 10 }, 4090 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4091 .vsync_len = { 2, 2, 2 }, 4092 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4093 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4094 }; 4095 4096 static const struct panel_desc urt_umsh_8596md_lvds = { 4097 .timings = &urt_umsh_8596md_timing, 4098 .num_timings = 1, 4099 .bpc = 6, 4100 .size = { 4101 .width = 152, 4102 .height = 91, 4103 }, 4104 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4105 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4106 }; 4107 4108 static const struct panel_desc urt_umsh_8596md_parallel = { 4109 .timings = &urt_umsh_8596md_timing, 4110 .num_timings = 1, 4111 .bpc = 6, 4112 .size = { 4113 .width = 152, 4114 .height = 91, 4115 }, 4116 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4117 }; 4118 4119 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4120 .clock = 60000, 4121 .hdisplay = 1024, 4122 .hsync_start = 1024 + 160, 4123 .hsync_end = 1024 + 160 + 100, 4124 .htotal = 1024 + 160 + 100 + 60, 4125 .vdisplay = 600, 4126 .vsync_start = 600 + 12, 4127 .vsync_end = 600 + 12 + 10, 4128 .vtotal = 600 + 12 + 10 + 13, 4129 }; 4130 4131 static const struct panel_desc vivax_tpc9150_panel = { 4132 .modes = &vivax_tpc9150_panel_mode, 4133 .num_modes = 1, 4134 .bpc = 6, 4135 .size = { 4136 .width = 200, 4137 .height = 115, 4138 }, 4139 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4140 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4141 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4142 }; 4143 4144 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4145 .clock = 33333, 4146 .hdisplay = 800, 4147 .hsync_start = 800 + 210, 4148 .hsync_end = 800 + 210 + 20, 4149 .htotal = 800 + 210 + 20 + 46, 4150 .vdisplay = 480, 4151 .vsync_start = 480 + 22, 4152 .vsync_end = 480 + 22 + 10, 4153 .vtotal = 480 + 22 + 10 + 23, 4154 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4155 }; 4156 4157 static const struct panel_desc vl050_8048nt_c01 = { 4158 .modes = &vl050_8048nt_c01_mode, 4159 .num_modes = 1, 4160 .bpc = 8, 4161 .size = { 4162 .width = 120, 4163 .height = 76, 4164 }, 4165 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4166 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4167 }; 4168 4169 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4170 .clock = 6410, 4171 .hdisplay = 320, 4172 .hsync_start = 320 + 20, 4173 .hsync_end = 320 + 20 + 30, 4174 .htotal = 320 + 20 + 30 + 38, 4175 .vdisplay = 240, 4176 .vsync_start = 240 + 4, 4177 .vsync_end = 240 + 4 + 3, 4178 .vtotal = 240 + 4 + 3 + 15, 4179 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4180 }; 4181 4182 static const struct panel_desc winstar_wf35ltiacd = { 4183 .modes = &winstar_wf35ltiacd_mode, 4184 .num_modes = 1, 4185 .bpc = 8, 4186 .size = { 4187 .width = 70, 4188 .height = 53, 4189 }, 4190 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4191 }; 4192 4193 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4194 .clock = 51200, 4195 .hdisplay = 1024, 4196 .hsync_start = 1024 + 100, 4197 .hsync_end = 1024 + 100 + 100, 4198 .htotal = 1024 + 100 + 100 + 120, 4199 .vdisplay = 600, 4200 .vsync_start = 600 + 10, 4201 .vsync_end = 600 + 10 + 10, 4202 .vtotal = 600 + 10 + 10 + 15, 4203 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4204 }; 4205 4206 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4207 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4208 .num_modes = 1, 4209 .bpc = 8, 4210 .size = { 4211 .width = 154, 4212 .height = 90, 4213 }, 4214 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4215 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4216 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4217 }; 4218 4219 static const struct drm_display_mode arm_rtsm_mode[] = { 4220 { 4221 .clock = 65000, 4222 .hdisplay = 1024, 4223 .hsync_start = 1024 + 24, 4224 .hsync_end = 1024 + 24 + 136, 4225 .htotal = 1024 + 24 + 136 + 160, 4226 .vdisplay = 768, 4227 .vsync_start = 768 + 3, 4228 .vsync_end = 768 + 3 + 6, 4229 .vtotal = 768 + 3 + 6 + 29, 4230 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4231 }, 4232 }; 4233 4234 static const struct panel_desc arm_rtsm = { 4235 .modes = arm_rtsm_mode, 4236 .num_modes = 1, 4237 .bpc = 8, 4238 .size = { 4239 .width = 400, 4240 .height = 300, 4241 }, 4242 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4243 }; 4244 4245 static const struct of_device_id platform_of_match[] = { 4246 { 4247 .compatible = "ampire,am-1280800n3tzqw-t00h", 4248 .data = &ire_am_1280800n3tzqw_t00h, 4249 }, { 4250 .compatible = "ampire,am-480272h3tmqw-t01h", 4251 .data = &ire_am_480272h3tmqw_t01h, 4252 }, { 4253 .compatible = "ampire,am-800480l1tmqw-t00h", 4254 .data = &ire_am_800480l1tmqw_t00h, 4255 }, { 4256 .compatible = "ampire,am800480r3tmqwa1h", 4257 .data = &ire_am800480r3tmqwa1h, 4258 }, { 4259 .compatible = "ampire,am800600p5tmqw-tb8h", 4260 .data = &ire_am800600p5tmqwtb8h, 4261 }, { 4262 .compatible = "arm,rtsm-display", 4263 .data = &arm_rtsm, 4264 }, { 4265 .compatible = "armadeus,st0700-adapt", 4266 .data = &armadeus_st0700_adapt, 4267 }, { 4268 .compatible = "auo,b101aw03", 4269 .data = &auo_b101aw03, 4270 }, { 4271 .compatible = "auo,b101xtn01", 4272 .data = &auo_b101xtn01, 4273 }, { 4274 .compatible = "auo,b116xw03", 4275 .data = &auo_b116xw03, 4276 }, { 4277 .compatible = "auo,g070vvn01", 4278 .data = &auo_g070vvn01, 4279 }, { 4280 .compatible = "auo,g101evn010", 4281 .data = &auo_g101evn010, 4282 }, { 4283 .compatible = "auo,g104sn02", 4284 .data = &auo_g104sn02, 4285 }, { 4286 .compatible = "auo,g121ean01", 4287 .data = &auo_g121ean01, 4288 }, { 4289 .compatible = "auo,g133han01", 4290 .data = &auo_g133han01, 4291 }, { 4292 .compatible = "auo,g156xtn01", 4293 .data = &auo_g156xtn01, 4294 }, { 4295 .compatible = "auo,g185han01", 4296 .data = &auo_g185han01, 4297 }, { 4298 .compatible = "auo,g190ean01", 4299 .data = &auo_g190ean01, 4300 }, { 4301 .compatible = "auo,p320hvn03", 4302 .data = &auo_p320hvn03, 4303 }, { 4304 .compatible = "auo,t215hvn01", 4305 .data = &auo_t215hvn01, 4306 }, { 4307 .compatible = "avic,tm070ddh03", 4308 .data = &avic_tm070ddh03, 4309 }, { 4310 .compatible = "bananapi,s070wv20-ct16", 4311 .data = &bananapi_s070wv20_ct16, 4312 }, { 4313 .compatible = "boe,bp101wx1-100", 4314 .data = &boe_bp101wx1_100, 4315 }, { 4316 .compatible = "boe,ev121wxm-n10-1850", 4317 .data = &boe_ev121wxm_n10_1850, 4318 }, { 4319 .compatible = "boe,hv070wsa-100", 4320 .data = &boe_hv070wsa 4321 }, { 4322 .compatible = "cdtech,s043wq26h-ct7", 4323 .data = &cdtech_s043wq26h_ct7, 4324 }, { 4325 .compatible = "cdtech,s070pws19hp-fc21", 4326 .data = &cdtech_s070pws19hp_fc21, 4327 }, { 4328 .compatible = "cdtech,s070swv29hg-dc44", 4329 .data = &cdtech_s070swv29hg_dc44, 4330 }, { 4331 .compatible = "cdtech,s070wv95-ct16", 4332 .data = &cdtech_s070wv95_ct16, 4333 }, { 4334 .compatible = "chefree,ch101olhlwh-002", 4335 .data = &chefree_ch101olhlwh_002, 4336 }, { 4337 .compatible = "chunghwa,claa070wp03xg", 4338 .data = &chunghwa_claa070wp03xg, 4339 }, { 4340 .compatible = "chunghwa,claa101wa01a", 4341 .data = &chunghwa_claa101wa01a 4342 }, { 4343 .compatible = "chunghwa,claa101wb01", 4344 .data = &chunghwa_claa101wb01 4345 }, { 4346 .compatible = "dataimage,fg040346dsswbg04", 4347 .data = &dataimage_fg040346dsswbg04, 4348 }, { 4349 .compatible = "dataimage,fg1001l0dsswmg01", 4350 .data = &dataimage_fg1001l0dsswmg01, 4351 }, { 4352 .compatible = "dataimage,scf0700c48ggu18", 4353 .data = &dataimage_scf0700c48ggu18, 4354 }, { 4355 .compatible = "dlc,dlc0700yzg-1", 4356 .data = &dlc_dlc0700yzg_1, 4357 }, { 4358 .compatible = "dlc,dlc1010gig", 4359 .data = &dlc_dlc1010gig, 4360 }, { 4361 .compatible = "edt,et035012dm6", 4362 .data = &edt_et035012dm6, 4363 }, { 4364 .compatible = "edt,etm0350g0dh6", 4365 .data = &edt_etm0350g0dh6, 4366 }, { 4367 .compatible = "edt,etm043080dh6gp", 4368 .data = &edt_etm043080dh6gp, 4369 }, { 4370 .compatible = "edt,etm0430g0dh6", 4371 .data = &edt_etm0430g0dh6, 4372 }, { 4373 .compatible = "edt,et057090dhu", 4374 .data = &edt_et057090dhu, 4375 }, { 4376 .compatible = "edt,et070080dh6", 4377 .data = &edt_etm0700g0dh6, 4378 }, { 4379 .compatible = "edt,etm0700g0dh6", 4380 .data = &edt_etm0700g0dh6, 4381 }, { 4382 .compatible = "edt,etm0700g0bdh6", 4383 .data = &edt_etm0700g0bdh6, 4384 }, { 4385 .compatible = "edt,etm0700g0edh6", 4386 .data = &edt_etm0700g0bdh6, 4387 }, { 4388 .compatible = "edt,etml0700y5dha", 4389 .data = &edt_etml0700y5dha, 4390 }, { 4391 .compatible = "edt,etmv570g2dhu", 4392 .data = &edt_etmv570g2dhu, 4393 }, { 4394 .compatible = "eink,vb3300-kca", 4395 .data = &eink_vb3300_kca, 4396 }, { 4397 .compatible = "evervision,vgg644804", 4398 .data = &evervision_vgg644804, 4399 }, { 4400 .compatible = "evervision,vgg804821", 4401 .data = &evervision_vgg804821, 4402 }, { 4403 .compatible = "foxlink,fl500wvr00-a0t", 4404 .data = &foxlink_fl500wvr00_a0t, 4405 }, { 4406 .compatible = "frida,frd350h54004", 4407 .data = &frida_frd350h54004, 4408 }, { 4409 .compatible = "friendlyarm,hd702e", 4410 .data = &friendlyarm_hd702e, 4411 }, { 4412 .compatible = "giantplus,gpg482739qs5", 4413 .data = &giantplus_gpg482739qs5 4414 }, { 4415 .compatible = "giantplus,gpm940b0", 4416 .data = &giantplus_gpm940b0, 4417 }, { 4418 .compatible = "hannstar,hsd070pww1", 4419 .data = &hannstar_hsd070pww1, 4420 }, { 4421 .compatible = "hannstar,hsd100pxn1", 4422 .data = &hannstar_hsd100pxn1, 4423 }, { 4424 .compatible = "hannstar,hsd101pww2", 4425 .data = &hannstar_hsd101pww2, 4426 }, { 4427 .compatible = "hit,tx23d38vm0caa", 4428 .data = &hitachi_tx23d38vm0caa 4429 }, { 4430 .compatible = "innolux,at043tn24", 4431 .data = &innolux_at043tn24, 4432 }, { 4433 .compatible = "innolux,at070tn92", 4434 .data = &innolux_at070tn92, 4435 }, { 4436 .compatible = "innolux,g070ace-l01", 4437 .data = &innolux_g070ace_l01, 4438 }, { 4439 .compatible = "innolux,g070y2-l01", 4440 .data = &innolux_g070y2_l01, 4441 }, { 4442 .compatible = "innolux,g070y2-t02", 4443 .data = &innolux_g070y2_t02, 4444 }, { 4445 .compatible = "innolux,g101ice-l01", 4446 .data = &innolux_g101ice_l01 4447 }, { 4448 .compatible = "innolux,g121i1-l01", 4449 .data = &innolux_g121i1_l01 4450 }, { 4451 .compatible = "innolux,g121x1-l03", 4452 .data = &innolux_g121x1_l03, 4453 }, { 4454 .compatible = "innolux,g156hce-l01", 4455 .data = &innolux_g156hce_l01, 4456 }, { 4457 .compatible = "innolux,n156bge-l21", 4458 .data = &innolux_n156bge_l21, 4459 }, { 4460 .compatible = "innolux,zj070na-01p", 4461 .data = &innolux_zj070na_01p, 4462 }, { 4463 .compatible = "koe,tx14d24vm1bpa", 4464 .data = &koe_tx14d24vm1bpa, 4465 }, { 4466 .compatible = "koe,tx26d202vm0bwa", 4467 .data = &koe_tx26d202vm0bwa, 4468 }, { 4469 .compatible = "koe,tx31d200vm0baa", 4470 .data = &koe_tx31d200vm0baa, 4471 }, { 4472 .compatible = "kyo,tcg121xglp", 4473 .data = &kyo_tcg121xglp, 4474 }, { 4475 .compatible = "lemaker,bl035-rgb-002", 4476 .data = &lemaker_bl035_rgb_002, 4477 }, { 4478 .compatible = "lg,lb070wv8", 4479 .data = &lg_lb070wv8, 4480 }, { 4481 .compatible = "logicpd,type28", 4482 .data = &logicpd_type_28, 4483 }, { 4484 .compatible = "logictechno,lt161010-2nhc", 4485 .data = &logictechno_lt161010_2nh, 4486 }, { 4487 .compatible = "logictechno,lt161010-2nhr", 4488 .data = &logictechno_lt161010_2nh, 4489 }, { 4490 .compatible = "logictechno,lt170410-2whc", 4491 .data = &logictechno_lt170410_2whc, 4492 }, { 4493 .compatible = "logictechno,lttd800480070-l2rt", 4494 .data = &logictechno_lttd800480070_l2rt, 4495 }, { 4496 .compatible = "logictechno,lttd800480070-l6wh-rt", 4497 .data = &logictechno_lttd800480070_l6wh_rt, 4498 }, { 4499 .compatible = "mitsubishi,aa070mc01-ca1", 4500 .data = &mitsubishi_aa070mc01, 4501 }, { 4502 .compatible = "mitsubishi,aa084xe01", 4503 .data = &mitsubishi_aa084xe01, 4504 }, { 4505 .compatible = "multi-inno,mi0700s4t-6", 4506 .data = &multi_inno_mi0700s4t_6, 4507 }, { 4508 .compatible = "multi-inno,mi0800ft-9", 4509 .data = &multi_inno_mi0800ft_9, 4510 }, { 4511 .compatible = "multi-inno,mi1010ait-1cp", 4512 .data = &multi_inno_mi1010ait_1cp, 4513 }, { 4514 .compatible = "nec,nl12880bc20-05", 4515 .data = &nec_nl12880bc20_05, 4516 }, { 4517 .compatible = "nec,nl4827hc19-05b", 4518 .data = &nec_nl4827hc19_05b, 4519 }, { 4520 .compatible = "netron-dy,e231732", 4521 .data = &netron_dy_e231732, 4522 }, { 4523 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4524 .data = &newhaven_nhd_43_480272ef_atxl, 4525 }, { 4526 .compatible = "nlt,nl192108ac18-02d", 4527 .data = &nlt_nl192108ac18_02d, 4528 }, { 4529 .compatible = "nvd,9128", 4530 .data = &nvd_9128, 4531 }, { 4532 .compatible = "okaya,rs800480t-7x0gp", 4533 .data = &okaya_rs800480t_7x0gp, 4534 }, { 4535 .compatible = "olimex,lcd-olinuxino-43-ts", 4536 .data = &olimex_lcd_olinuxino_43ts, 4537 }, { 4538 .compatible = "ontat,yx700wv03", 4539 .data = &ontat_yx700wv03, 4540 }, { 4541 .compatible = "ortustech,com37h3m05dtc", 4542 .data = &ortustech_com37h3m, 4543 }, { 4544 .compatible = "ortustech,com37h3m99dtc", 4545 .data = &ortustech_com37h3m, 4546 }, { 4547 .compatible = "ortustech,com43h4m85ulc", 4548 .data = &ortustech_com43h4m85ulc, 4549 }, { 4550 .compatible = "osddisplays,osd070t1718-19ts", 4551 .data = &osddisplays_osd070t1718_19ts, 4552 }, { 4553 .compatible = "pda,91-00156-a0", 4554 .data = &pda_91_00156_a0, 4555 }, { 4556 .compatible = "powertip,ph800480t013-idf02", 4557 .data = &powertip_ph800480t013_idf02, 4558 }, { 4559 .compatible = "qiaodian,qd43003c0-40", 4560 .data = &qd43003c0_40, 4561 }, { 4562 .compatible = "qishenglong,gopher2b-lcd", 4563 .data = &qishenglong_gopher2b_lcd, 4564 }, { 4565 .compatible = "rocktech,rk043fn48h", 4566 .data = &rocktech_rk043fn48h, 4567 }, { 4568 .compatible = "rocktech,rk070er9427", 4569 .data = &rocktech_rk070er9427, 4570 }, { 4571 .compatible = "rocktech,rk101ii01d-ct", 4572 .data = &rocktech_rk101ii01d_ct, 4573 }, { 4574 .compatible = "samsung,ltl101al01", 4575 .data = &samsung_ltl101al01, 4576 }, { 4577 .compatible = "samsung,ltn101nt05", 4578 .data = &samsung_ltn101nt05, 4579 }, { 4580 .compatible = "satoz,sat050at40h12r2", 4581 .data = &satoz_sat050at40h12r2, 4582 }, { 4583 .compatible = "sharp,lq035q7db03", 4584 .data = &sharp_lq035q7db03, 4585 }, { 4586 .compatible = "sharp,lq070y3dg3b", 4587 .data = &sharp_lq070y3dg3b, 4588 }, { 4589 .compatible = "sharp,lq101k1ly04", 4590 .data = &sharp_lq101k1ly04, 4591 }, { 4592 .compatible = "sharp,ls020b1dd01d", 4593 .data = &sharp_ls020b1dd01d, 4594 }, { 4595 .compatible = "shelly,sca07010-bfn-lnn", 4596 .data = &shelly_sca07010_bfn_lnn, 4597 }, { 4598 .compatible = "starry,kr070pe2t", 4599 .data = &starry_kr070pe2t, 4600 }, { 4601 .compatible = "startek,kd070wvfpa", 4602 .data = &startek_kd070wvfpa, 4603 }, { 4604 .compatible = "team-source-display,tst043015cmhx", 4605 .data = &tsd_tst043015cmhx, 4606 }, { 4607 .compatible = "tfc,s9700rtwv43tr-01b", 4608 .data = &tfc_s9700rtwv43tr_01b, 4609 }, { 4610 .compatible = "tianma,tm070jdhg30", 4611 .data = &tianma_tm070jdhg30, 4612 }, { 4613 .compatible = "tianma,tm070jvhg33", 4614 .data = &tianma_tm070jvhg33, 4615 }, { 4616 .compatible = "tianma,tm070rvhg71", 4617 .data = &tianma_tm070rvhg71, 4618 }, { 4619 .compatible = "ti,nspire-cx-lcd-panel", 4620 .data = &ti_nspire_cx_lcd_panel, 4621 }, { 4622 .compatible = "ti,nspire-classic-lcd-panel", 4623 .data = &ti_nspire_classic_lcd_panel, 4624 }, { 4625 .compatible = "toshiba,lt089ac29000", 4626 .data = &toshiba_lt089ac29000, 4627 }, { 4628 .compatible = "tpk,f07a-0102", 4629 .data = &tpk_f07a_0102, 4630 }, { 4631 .compatible = "tpk,f10a-0102", 4632 .data = &tpk_f10a_0102, 4633 }, { 4634 .compatible = "urt,umsh-8596md-t", 4635 .data = &urt_umsh_8596md_parallel, 4636 }, { 4637 .compatible = "urt,umsh-8596md-1t", 4638 .data = &urt_umsh_8596md_parallel, 4639 }, { 4640 .compatible = "urt,umsh-8596md-7t", 4641 .data = &urt_umsh_8596md_parallel, 4642 }, { 4643 .compatible = "urt,umsh-8596md-11t", 4644 .data = &urt_umsh_8596md_lvds, 4645 }, { 4646 .compatible = "urt,umsh-8596md-19t", 4647 .data = &urt_umsh_8596md_lvds, 4648 }, { 4649 .compatible = "urt,umsh-8596md-20t", 4650 .data = &urt_umsh_8596md_parallel, 4651 }, { 4652 .compatible = "vivax,tpc9150-panel", 4653 .data = &vivax_tpc9150_panel, 4654 }, { 4655 .compatible = "vxt,vl050-8048nt-c01", 4656 .data = &vl050_8048nt_c01, 4657 }, { 4658 .compatible = "winstar,wf35ltiacd", 4659 .data = &winstar_wf35ltiacd, 4660 }, { 4661 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4662 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4663 }, { 4664 /* Must be the last entry */ 4665 .compatible = "panel-dpi", 4666 .data = &panel_dpi, 4667 }, { 4668 /* sentinel */ 4669 } 4670 }; 4671 MODULE_DEVICE_TABLE(of, platform_of_match); 4672 4673 static int panel_simple_platform_probe(struct platform_device *pdev) 4674 { 4675 const struct panel_desc *desc; 4676 4677 desc = of_device_get_match_data(&pdev->dev); 4678 if (!desc) 4679 return -ENODEV; 4680 4681 return panel_simple_probe(&pdev->dev, desc); 4682 } 4683 4684 static void panel_simple_platform_remove(struct platform_device *pdev) 4685 { 4686 panel_simple_remove(&pdev->dev); 4687 } 4688 4689 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4690 { 4691 panel_simple_shutdown(&pdev->dev); 4692 } 4693 4694 static const struct dev_pm_ops panel_simple_pm_ops = { 4695 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4696 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4697 pm_runtime_force_resume) 4698 }; 4699 4700 static struct platform_driver panel_simple_platform_driver = { 4701 .driver = { 4702 .name = "panel-simple", 4703 .of_match_table = platform_of_match, 4704 .pm = &panel_simple_pm_ops, 4705 }, 4706 .probe = panel_simple_platform_probe, 4707 .remove_new = panel_simple_platform_remove, 4708 .shutdown = panel_simple_platform_shutdown, 4709 }; 4710 4711 struct panel_desc_dsi { 4712 struct panel_desc desc; 4713 4714 unsigned long flags; 4715 enum mipi_dsi_pixel_format format; 4716 unsigned int lanes; 4717 }; 4718 4719 static const struct drm_display_mode auo_b080uan01_mode = { 4720 .clock = 154500, 4721 .hdisplay = 1200, 4722 .hsync_start = 1200 + 62, 4723 .hsync_end = 1200 + 62 + 4, 4724 .htotal = 1200 + 62 + 4 + 62, 4725 .vdisplay = 1920, 4726 .vsync_start = 1920 + 9, 4727 .vsync_end = 1920 + 9 + 2, 4728 .vtotal = 1920 + 9 + 2 + 8, 4729 }; 4730 4731 static const struct panel_desc_dsi auo_b080uan01 = { 4732 .desc = { 4733 .modes = &auo_b080uan01_mode, 4734 .num_modes = 1, 4735 .bpc = 8, 4736 .size = { 4737 .width = 108, 4738 .height = 272, 4739 }, 4740 .connector_type = DRM_MODE_CONNECTOR_DSI, 4741 }, 4742 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4743 .format = MIPI_DSI_FMT_RGB888, 4744 .lanes = 4, 4745 }; 4746 4747 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4748 .clock = 160000, 4749 .hdisplay = 1200, 4750 .hsync_start = 1200 + 120, 4751 .hsync_end = 1200 + 120 + 20, 4752 .htotal = 1200 + 120 + 20 + 21, 4753 .vdisplay = 1920, 4754 .vsync_start = 1920 + 21, 4755 .vsync_end = 1920 + 21 + 3, 4756 .vtotal = 1920 + 21 + 3 + 18, 4757 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4758 }; 4759 4760 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4761 .desc = { 4762 .modes = &boe_tv080wum_nl0_mode, 4763 .num_modes = 1, 4764 .size = { 4765 .width = 107, 4766 .height = 172, 4767 }, 4768 .connector_type = DRM_MODE_CONNECTOR_DSI, 4769 }, 4770 .flags = MIPI_DSI_MODE_VIDEO | 4771 MIPI_DSI_MODE_VIDEO_BURST | 4772 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4773 .format = MIPI_DSI_FMT_RGB888, 4774 .lanes = 4, 4775 }; 4776 4777 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4778 .clock = 71000, 4779 .hdisplay = 800, 4780 .hsync_start = 800 + 32, 4781 .hsync_end = 800 + 32 + 1, 4782 .htotal = 800 + 32 + 1 + 57, 4783 .vdisplay = 1280, 4784 .vsync_start = 1280 + 28, 4785 .vsync_end = 1280 + 28 + 1, 4786 .vtotal = 1280 + 28 + 1 + 14, 4787 }; 4788 4789 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4790 .desc = { 4791 .modes = &lg_ld070wx3_sl01_mode, 4792 .num_modes = 1, 4793 .bpc = 8, 4794 .size = { 4795 .width = 94, 4796 .height = 151, 4797 }, 4798 .connector_type = DRM_MODE_CONNECTOR_DSI, 4799 }, 4800 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4801 .format = MIPI_DSI_FMT_RGB888, 4802 .lanes = 4, 4803 }; 4804 4805 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4806 .clock = 67000, 4807 .hdisplay = 720, 4808 .hsync_start = 720 + 12, 4809 .hsync_end = 720 + 12 + 4, 4810 .htotal = 720 + 12 + 4 + 112, 4811 .vdisplay = 1280, 4812 .vsync_start = 1280 + 8, 4813 .vsync_end = 1280 + 8 + 4, 4814 .vtotal = 1280 + 8 + 4 + 12, 4815 }; 4816 4817 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4818 .desc = { 4819 .modes = &lg_lh500wx1_sd03_mode, 4820 .num_modes = 1, 4821 .bpc = 8, 4822 .size = { 4823 .width = 62, 4824 .height = 110, 4825 }, 4826 .connector_type = DRM_MODE_CONNECTOR_DSI, 4827 }, 4828 .flags = MIPI_DSI_MODE_VIDEO, 4829 .format = MIPI_DSI_FMT_RGB888, 4830 .lanes = 4, 4831 }; 4832 4833 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4834 .clock = 157200, 4835 .hdisplay = 1920, 4836 .hsync_start = 1920 + 154, 4837 .hsync_end = 1920 + 154 + 16, 4838 .htotal = 1920 + 154 + 16 + 32, 4839 .vdisplay = 1200, 4840 .vsync_start = 1200 + 17, 4841 .vsync_end = 1200 + 17 + 2, 4842 .vtotal = 1200 + 17 + 2 + 16, 4843 }; 4844 4845 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4846 .desc = { 4847 .modes = &panasonic_vvx10f004b00_mode, 4848 .num_modes = 1, 4849 .bpc = 8, 4850 .size = { 4851 .width = 217, 4852 .height = 136, 4853 }, 4854 .connector_type = DRM_MODE_CONNECTOR_DSI, 4855 }, 4856 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4857 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4858 .format = MIPI_DSI_FMT_RGB888, 4859 .lanes = 4, 4860 }; 4861 4862 static const struct drm_display_mode lg_acx467akm_7_mode = { 4863 .clock = 150000, 4864 .hdisplay = 1080, 4865 .hsync_start = 1080 + 2, 4866 .hsync_end = 1080 + 2 + 2, 4867 .htotal = 1080 + 2 + 2 + 2, 4868 .vdisplay = 1920, 4869 .vsync_start = 1920 + 2, 4870 .vsync_end = 1920 + 2 + 2, 4871 .vtotal = 1920 + 2 + 2 + 2, 4872 }; 4873 4874 static const struct panel_desc_dsi lg_acx467akm_7 = { 4875 .desc = { 4876 .modes = &lg_acx467akm_7_mode, 4877 .num_modes = 1, 4878 .bpc = 8, 4879 .size = { 4880 .width = 62, 4881 .height = 110, 4882 }, 4883 .connector_type = DRM_MODE_CONNECTOR_DSI, 4884 }, 4885 .flags = 0, 4886 .format = MIPI_DSI_FMT_RGB888, 4887 .lanes = 4, 4888 }; 4889 4890 static const struct drm_display_mode osd101t2045_53ts_mode = { 4891 .clock = 154500, 4892 .hdisplay = 1920, 4893 .hsync_start = 1920 + 112, 4894 .hsync_end = 1920 + 112 + 16, 4895 .htotal = 1920 + 112 + 16 + 32, 4896 .vdisplay = 1200, 4897 .vsync_start = 1200 + 16, 4898 .vsync_end = 1200 + 16 + 2, 4899 .vtotal = 1200 + 16 + 2 + 16, 4900 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4901 }; 4902 4903 static const struct panel_desc_dsi osd101t2045_53ts = { 4904 .desc = { 4905 .modes = &osd101t2045_53ts_mode, 4906 .num_modes = 1, 4907 .bpc = 8, 4908 .size = { 4909 .width = 217, 4910 .height = 136, 4911 }, 4912 .connector_type = DRM_MODE_CONNECTOR_DSI, 4913 }, 4914 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4915 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4916 MIPI_DSI_MODE_NO_EOT_PACKET, 4917 .format = MIPI_DSI_FMT_RGB888, 4918 .lanes = 4, 4919 }; 4920 4921 static const struct of_device_id dsi_of_match[] = { 4922 { 4923 .compatible = "auo,b080uan01", 4924 .data = &auo_b080uan01 4925 }, { 4926 .compatible = "boe,tv080wum-nl0", 4927 .data = &boe_tv080wum_nl0 4928 }, { 4929 .compatible = "lg,ld070wx3-sl01", 4930 .data = &lg_ld070wx3_sl01 4931 }, { 4932 .compatible = "lg,lh500wx1-sd03", 4933 .data = &lg_lh500wx1_sd03 4934 }, { 4935 .compatible = "panasonic,vvx10f004b00", 4936 .data = &panasonic_vvx10f004b00 4937 }, { 4938 .compatible = "lg,acx467akm-7", 4939 .data = &lg_acx467akm_7 4940 }, { 4941 .compatible = "osddisplays,osd101t2045-53ts", 4942 .data = &osd101t2045_53ts 4943 }, { 4944 /* sentinel */ 4945 } 4946 }; 4947 MODULE_DEVICE_TABLE(of, dsi_of_match); 4948 4949 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4950 { 4951 const struct panel_desc_dsi *desc; 4952 int err; 4953 4954 desc = of_device_get_match_data(&dsi->dev); 4955 if (!desc) 4956 return -ENODEV; 4957 4958 err = panel_simple_probe(&dsi->dev, &desc->desc); 4959 if (err < 0) 4960 return err; 4961 4962 dsi->mode_flags = desc->flags; 4963 dsi->format = desc->format; 4964 dsi->lanes = desc->lanes; 4965 4966 err = mipi_dsi_attach(dsi); 4967 if (err) { 4968 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4969 4970 drm_panel_remove(&panel->base); 4971 } 4972 4973 return err; 4974 } 4975 4976 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4977 { 4978 int err; 4979 4980 err = mipi_dsi_detach(dsi); 4981 if (err < 0) 4982 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4983 4984 panel_simple_remove(&dsi->dev); 4985 } 4986 4987 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4988 { 4989 panel_simple_shutdown(&dsi->dev); 4990 } 4991 4992 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4993 .driver = { 4994 .name = "panel-simple-dsi", 4995 .of_match_table = dsi_of_match, 4996 .pm = &panel_simple_pm_ops, 4997 }, 4998 .probe = panel_simple_dsi_probe, 4999 .remove = panel_simple_dsi_remove, 5000 .shutdown = panel_simple_dsi_shutdown, 5001 }; 5002 5003 static int __init panel_simple_init(void) 5004 { 5005 int err; 5006 5007 err = platform_driver_register(&panel_simple_platform_driver); 5008 if (err < 0) 5009 return err; 5010 5011 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5012 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5013 if (err < 0) 5014 goto err_did_platform_register; 5015 } 5016 5017 return 0; 5018 5019 err_did_platform_register: 5020 platform_driver_unregister(&panel_simple_platform_driver); 5021 5022 return err; 5023 } 5024 module_init(panel_simple_init); 5025 5026 static void __exit panel_simple_exit(void) 5027 { 5028 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5029 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5030 5031 platform_driver_unregister(&panel_simple_platform_driver); 5032 } 5033 module_exit(panel_simple_exit); 5034 5035 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5036 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5037 MODULE_LICENSE("GPL and additional rights"); 5038