1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_device.h> 30 #include <linux/of_platform.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/regulator/consumer.h> 34 35 #include <video/display_timing.h> 36 #include <video/of_display_timing.h> 37 #include <video/videomode.h> 38 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_device.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_mipi_dsi.h> 43 #include <drm/drm_panel.h> 44 #include <drm/drm_of.h> 45 46 /** 47 * struct panel_desc - Describes a simple panel. 48 */ 49 struct panel_desc { 50 /** 51 * @modes: Pointer to array of fixed modes appropriate for this panel. 52 * 53 * If only one mode then this can just be the address of the mode. 54 * NOTE: cannot be used with "timings" and also if this is specified 55 * then you cannot override the mode in the device tree. 56 */ 57 const struct drm_display_mode *modes; 58 59 /** @num_modes: Number of elements in modes array. */ 60 unsigned int num_modes; 61 62 /** 63 * @timings: Pointer to array of display timings 64 * 65 * NOTE: cannot be used with "modes" and also these will be used to 66 * validate a device tree override if one is present. 67 */ 68 const struct display_timing *timings; 69 70 /** @num_timings: Number of elements in timings array. */ 71 unsigned int num_timings; 72 73 /** @bpc: Bits per color. */ 74 unsigned int bpc; 75 76 /** @size: Structure containing the physical size of this panel. */ 77 struct { 78 /** 79 * @size.width: Width (in mm) of the active display area. 80 */ 81 unsigned int width; 82 83 /** 84 * @size.height: Height (in mm) of the active display area. 85 */ 86 unsigned int height; 87 } size; 88 89 /** @delay: Structure containing various delay values for this panel. */ 90 struct { 91 /** 92 * @delay.prepare: Time for the panel to become ready. 93 * 94 * The time (in milliseconds) that it takes for the panel to 95 * become ready and start receiving video data 96 */ 97 unsigned int prepare; 98 99 /** 100 * @delay.enable: Time for the panel to display a valid frame. 101 * 102 * The time (in milliseconds) that it takes for the panel to 103 * display the first valid frame after starting to receive 104 * video data. 105 */ 106 unsigned int enable; 107 108 /** 109 * @delay.disable: Time for the panel to turn the display off. 110 * 111 * The time (in milliseconds) that it takes for the panel to 112 * turn the display off (no content is visible). 113 */ 114 unsigned int disable; 115 116 /** 117 * @delay.unprepare: Time to power down completely. 118 * 119 * The time (in milliseconds) that it takes for the panel 120 * to power itself down completely. 121 * 122 * This time is used to prevent a future "prepare" from 123 * starting until at least this many milliseconds has passed. 124 * If at prepare time less time has passed since unprepare 125 * finished, the driver waits for the remaining time. 126 */ 127 unsigned int unprepare; 128 } delay; 129 130 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 131 u32 bus_format; 132 133 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 134 u32 bus_flags; 135 136 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 137 int connector_type; 138 }; 139 140 struct panel_desc_dsi { 141 struct panel_desc desc; 142 143 unsigned long flags; 144 enum mipi_dsi_pixel_format format; 145 unsigned int lanes; 146 }; 147 148 struct panel_simple { 149 struct drm_panel base; 150 151 ktime_t unprepared_time; 152 153 const struct panel_desc *desc; 154 155 struct regulator *supply; 156 struct i2c_adapter *ddc; 157 158 struct gpio_desc *enable_gpio; 159 160 const struct drm_edid *drm_edid; 161 162 struct drm_display_mode override_mode; 163 164 enum drm_panel_orientation orientation; 165 }; 166 167 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 168 { 169 return container_of(panel, struct panel_simple, base); 170 } 171 172 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 173 struct drm_connector *connector) 174 { 175 struct drm_display_mode *mode; 176 unsigned int i, num = 0; 177 178 for (i = 0; i < panel->desc->num_timings; i++) { 179 const struct display_timing *dt = &panel->desc->timings[i]; 180 struct videomode vm; 181 182 videomode_from_timing(dt, &vm); 183 mode = drm_mode_create(connector->dev); 184 if (!mode) { 185 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 186 dt->hactive.typ, dt->vactive.typ); 187 continue; 188 } 189 190 drm_display_mode_from_videomode(&vm, mode); 191 192 mode->type |= DRM_MODE_TYPE_DRIVER; 193 194 if (panel->desc->num_timings == 1) 195 mode->type |= DRM_MODE_TYPE_PREFERRED; 196 197 drm_mode_probed_add(connector, mode); 198 num++; 199 } 200 201 return num; 202 } 203 204 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 205 struct drm_connector *connector) 206 { 207 struct drm_display_mode *mode; 208 unsigned int i, num = 0; 209 210 for (i = 0; i < panel->desc->num_modes; i++) { 211 const struct drm_display_mode *m = &panel->desc->modes[i]; 212 213 mode = drm_mode_duplicate(connector->dev, m); 214 if (!mode) { 215 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 216 m->hdisplay, m->vdisplay, 217 drm_mode_vrefresh(m)); 218 continue; 219 } 220 221 mode->type |= DRM_MODE_TYPE_DRIVER; 222 223 if (panel->desc->num_modes == 1) 224 mode->type |= DRM_MODE_TYPE_PREFERRED; 225 226 drm_mode_set_name(mode); 227 228 drm_mode_probed_add(connector, mode); 229 num++; 230 } 231 232 return num; 233 } 234 235 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 236 struct drm_connector *connector) 237 { 238 struct drm_display_mode *mode; 239 bool has_override = panel->override_mode.type; 240 unsigned int num = 0; 241 242 if (!panel->desc) 243 return 0; 244 245 if (has_override) { 246 mode = drm_mode_duplicate(connector->dev, 247 &panel->override_mode); 248 if (mode) { 249 drm_mode_probed_add(connector, mode); 250 num = 1; 251 } else { 252 dev_err(panel->base.dev, "failed to add override mode\n"); 253 } 254 } 255 256 /* Only add timings if override was not there or failed to validate */ 257 if (num == 0 && panel->desc->num_timings) 258 num = panel_simple_get_timings_modes(panel, connector); 259 260 /* 261 * Only add fixed modes if timings/override added no mode. 262 * 263 * We should only ever have either the display timings specified 264 * or a fixed mode. Anything else is rather bogus. 265 */ 266 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 267 if (num == 0) 268 num = panel_simple_get_display_modes(panel, connector); 269 270 connector->display_info.bpc = panel->desc->bpc; 271 connector->display_info.width_mm = panel->desc->size.width; 272 connector->display_info.height_mm = panel->desc->size.height; 273 if (panel->desc->bus_format) 274 drm_display_info_set_bus_formats(&connector->display_info, 275 &panel->desc->bus_format, 1); 276 connector->display_info.bus_flags = panel->desc->bus_flags; 277 278 return num; 279 } 280 281 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 282 { 283 ktime_t now_ktime, min_ktime; 284 285 if (!min_ms) 286 return; 287 288 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 289 now_ktime = ktime_get_boottime(); 290 291 if (ktime_before(now_ktime, min_ktime)) 292 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 293 } 294 295 static int panel_simple_disable(struct drm_panel *panel) 296 { 297 struct panel_simple *p = to_panel_simple(panel); 298 299 if (p->desc->delay.disable) 300 msleep(p->desc->delay.disable); 301 302 return 0; 303 } 304 305 static int panel_simple_suspend(struct device *dev) 306 { 307 struct panel_simple *p = dev_get_drvdata(dev); 308 309 gpiod_set_value_cansleep(p->enable_gpio, 0); 310 regulator_disable(p->supply); 311 p->unprepared_time = ktime_get_boottime(); 312 313 drm_edid_free(p->drm_edid); 314 p->drm_edid = NULL; 315 316 return 0; 317 } 318 319 static int panel_simple_unprepare(struct drm_panel *panel) 320 { 321 int ret; 322 323 pm_runtime_mark_last_busy(panel->dev); 324 ret = pm_runtime_put_autosuspend(panel->dev); 325 if (ret < 0) 326 return ret; 327 328 return 0; 329 } 330 331 static int panel_simple_resume(struct device *dev) 332 { 333 struct panel_simple *p = dev_get_drvdata(dev); 334 int err; 335 336 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 337 338 err = regulator_enable(p->supply); 339 if (err < 0) { 340 dev_err(dev, "failed to enable supply: %d\n", err); 341 return err; 342 } 343 344 gpiod_set_value_cansleep(p->enable_gpio, 1); 345 346 if (p->desc->delay.prepare) 347 msleep(p->desc->delay.prepare); 348 349 return 0; 350 } 351 352 static int panel_simple_prepare(struct drm_panel *panel) 353 { 354 int ret; 355 356 ret = pm_runtime_get_sync(panel->dev); 357 if (ret < 0) { 358 pm_runtime_put_autosuspend(panel->dev); 359 return ret; 360 } 361 362 return 0; 363 } 364 365 static int panel_simple_enable(struct drm_panel *panel) 366 { 367 struct panel_simple *p = to_panel_simple(panel); 368 369 if (p->desc->delay.enable) 370 msleep(p->desc->delay.enable); 371 372 return 0; 373 } 374 375 static int panel_simple_get_modes(struct drm_panel *panel, 376 struct drm_connector *connector) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 int num = 0; 380 381 /* probe EDID if a DDC bus is available */ 382 if (p->ddc) { 383 pm_runtime_get_sync(panel->dev); 384 385 if (!p->drm_edid) 386 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 387 388 drm_edid_connector_update(connector, p->drm_edid); 389 390 num += drm_edid_connector_add_modes(connector); 391 392 pm_runtime_mark_last_busy(panel->dev); 393 pm_runtime_put_autosuspend(panel->dev); 394 } 395 396 /* add hard-coded panel modes */ 397 num += panel_simple_get_non_edid_modes(p, connector); 398 399 /* 400 * TODO: Remove once all drm drivers call 401 * drm_connector_set_orientation_from_panel() 402 */ 403 drm_connector_set_panel_orientation(connector, p->orientation); 404 405 return num; 406 } 407 408 static int panel_simple_get_timings(struct drm_panel *panel, 409 unsigned int num_timings, 410 struct display_timing *timings) 411 { 412 struct panel_simple *p = to_panel_simple(panel); 413 unsigned int i; 414 415 if (p->desc->num_timings < num_timings) 416 num_timings = p->desc->num_timings; 417 418 if (timings) 419 for (i = 0; i < num_timings; i++) 420 timings[i] = p->desc->timings[i]; 421 422 return p->desc->num_timings; 423 } 424 425 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 426 { 427 struct panel_simple *p = to_panel_simple(panel); 428 429 return p->orientation; 430 } 431 432 static const struct drm_panel_funcs panel_simple_funcs = { 433 .disable = panel_simple_disable, 434 .unprepare = panel_simple_unprepare, 435 .prepare = panel_simple_prepare, 436 .enable = panel_simple_enable, 437 .get_modes = panel_simple_get_modes, 438 .get_orientation = panel_simple_get_orientation, 439 .get_timings = panel_simple_get_timings, 440 }; 441 442 static struct panel_desc *panel_dpi_probe(struct device *dev) 443 { 444 struct display_timing *timing; 445 const struct device_node *np; 446 struct panel_desc *desc; 447 unsigned int bus_flags; 448 struct videomode vm; 449 int ret; 450 451 np = dev->of_node; 452 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 453 if (!desc) 454 return ERR_PTR(-ENOMEM); 455 456 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 457 if (!timing) 458 return ERR_PTR(-ENOMEM); 459 460 ret = of_get_display_timing(np, "panel-timing", timing); 461 if (ret < 0) { 462 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 463 np); 464 return ERR_PTR(ret); 465 } 466 467 desc->timings = timing; 468 desc->num_timings = 1; 469 470 of_property_read_u32(np, "width-mm", &desc->size.width); 471 of_property_read_u32(np, "height-mm", &desc->size.height); 472 473 /* Extract bus_flags from display_timing */ 474 bus_flags = 0; 475 vm.flags = timing->flags; 476 drm_bus_flags_from_videomode(&vm, &bus_flags); 477 desc->bus_flags = bus_flags; 478 479 /* We do not know the connector for the DT node, so guess it */ 480 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 481 482 return desc; 483 } 484 485 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 486 (to_check->field.typ >= bounds->field.min && \ 487 to_check->field.typ <= bounds->field.max) 488 static void panel_simple_parse_panel_timing_node(struct device *dev, 489 struct panel_simple *panel, 490 const struct display_timing *ot) 491 { 492 const struct panel_desc *desc = panel->desc; 493 struct videomode vm; 494 unsigned int i; 495 496 if (WARN_ON(desc->num_modes)) { 497 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 498 return; 499 } 500 if (WARN_ON(!desc->num_timings)) { 501 dev_err(dev, "Reject override mode: no timings specified\n"); 502 return; 503 } 504 505 for (i = 0; i < panel->desc->num_timings; i++) { 506 const struct display_timing *dt = &panel->desc->timings[i]; 507 508 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 512 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 513 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 514 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 515 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 516 continue; 517 518 if (ot->flags != dt->flags) 519 continue; 520 521 videomode_from_timing(ot, &vm); 522 drm_display_mode_from_videomode(&vm, &panel->override_mode); 523 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 524 DRM_MODE_TYPE_PREFERRED; 525 break; 526 } 527 528 if (WARN_ON(!panel->override_mode.type)) 529 dev_err(dev, "Reject override mode: No display_timing found\n"); 530 } 531 532 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 533 struct panel_simple *panel) 534 { 535 int ret, bpc; 536 537 ret = drm_of_lvds_get_data_mapping(dev->of_node); 538 if (ret < 0) { 539 if (ret == -EINVAL) 540 dev_warn(dev, "Ignore invalid data-mapping property\n"); 541 542 /* 543 * Ignore non-existing or malformatted property, fallback to 544 * default data-mapping, and return 0. 545 */ 546 return 0; 547 } 548 549 switch (ret) { 550 default: 551 WARN_ON(1); 552 fallthrough; 553 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 554 fallthrough; 555 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 556 bpc = 8; 557 break; 558 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 559 bpc = 6; 560 } 561 562 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 563 struct panel_desc *override_desc; 564 565 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 566 if (!override_desc) 567 return -ENOMEM; 568 569 override_desc->bus_format = ret; 570 override_desc->bpc = bpc; 571 panel->desc = override_desc; 572 } 573 574 return 0; 575 } 576 577 static const struct panel_desc *panel_simple_get_desc(struct device *dev) 578 { 579 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI) && 580 dev_is_mipi_dsi(dev)) { 581 const struct panel_desc_dsi *dsi_desc; 582 583 dsi_desc = of_device_get_match_data(dev); 584 if (!dsi_desc) 585 return ERR_PTR(-ENODEV); 586 587 return &dsi_desc->desc; 588 } 589 590 if (dev_is_platform(dev)) { 591 const struct panel_desc *desc; 592 593 desc = of_device_get_match_data(dev); 594 if (!desc) { 595 /* 596 * panel-dpi probes without a descriptor and 597 * panel_dpi_probe() will initialize one for us 598 * based on the device tree. 599 */ 600 if (of_device_is_compatible(dev->of_node, "panel-dpi")) 601 return panel_dpi_probe(dev); 602 else 603 return ERR_PTR(-ENODEV); 604 } 605 606 return desc; 607 } 608 609 return ERR_PTR(-ENODEV); 610 } 611 612 static struct panel_simple *panel_simple_probe(struct device *dev) 613 { 614 const struct panel_desc *desc; 615 struct panel_simple *panel; 616 struct display_timing dt; 617 struct device_node *ddc; 618 int connector_type; 619 u32 bus_flags; 620 int err; 621 622 desc = panel_simple_get_desc(dev); 623 if (IS_ERR(desc)) 624 return ERR_CAST(desc); 625 626 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 627 &panel_simple_funcs, desc->connector_type); 628 if (IS_ERR(panel)) 629 return ERR_CAST(panel); 630 631 panel->desc = desc; 632 633 panel->supply = devm_regulator_get(dev, "power"); 634 if (IS_ERR(panel->supply)) 635 return ERR_CAST(panel->supply); 636 637 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 638 GPIOD_OUT_LOW); 639 if (IS_ERR(panel->enable_gpio)) 640 return dev_err_cast_probe(dev, panel->enable_gpio, 641 "failed to request GPIO\n"); 642 643 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 644 if (err) { 645 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 646 return ERR_PTR(err); 647 } 648 649 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 650 if (ddc) { 651 panel->ddc = of_find_i2c_adapter_by_node(ddc); 652 of_node_put(ddc); 653 654 if (!panel->ddc) 655 return ERR_PTR(-EPROBE_DEFER); 656 } 657 658 if (!of_device_is_compatible(dev->of_node, "panel-dpi") && 659 !of_get_display_timing(dev->of_node, "panel-timing", &dt)) 660 panel_simple_parse_panel_timing_node(dev, panel, &dt); 661 662 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 663 /* Optional data-mapping property for overriding bus format */ 664 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 665 if (err) 666 goto free_ddc; 667 } 668 669 connector_type = desc->connector_type; 670 /* Catch common mistakes for panels. */ 671 switch (connector_type) { 672 case 0: 673 dev_warn(dev, "Specify missing connector_type\n"); 674 connector_type = DRM_MODE_CONNECTOR_DPI; 675 break; 676 case DRM_MODE_CONNECTOR_LVDS: 677 WARN_ON(desc->bus_flags & 678 ~(DRM_BUS_FLAG_DE_LOW | 679 DRM_BUS_FLAG_DE_HIGH | 680 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 681 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 682 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 683 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 684 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 685 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 686 desc->bpc != 6); 687 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 688 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 689 desc->bpc != 8); 690 break; 691 case DRM_MODE_CONNECTOR_eDP: 692 dev_warn(dev, "eDP panels moved to panel-edp\n"); 693 err = -EINVAL; 694 goto free_ddc; 695 case DRM_MODE_CONNECTOR_DSI: 696 if (desc->bpc != 6 && desc->bpc != 8) 697 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 698 break; 699 case DRM_MODE_CONNECTOR_DPI: 700 bus_flags = DRM_BUS_FLAG_DE_LOW | 701 DRM_BUS_FLAG_DE_HIGH | 702 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 703 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 704 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 705 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 706 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 707 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 708 if (desc->bus_flags & ~bus_flags) 709 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 710 if (!(desc->bus_flags & bus_flags)) 711 dev_warn(dev, "Specify missing bus_flags\n"); 712 if (desc->bus_format == 0) 713 dev_warn(dev, "Specify missing bus_format\n"); 714 if (desc->bpc != 6 && desc->bpc != 8) 715 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 716 break; 717 default: 718 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 719 connector_type = DRM_MODE_CONNECTOR_DPI; 720 break; 721 } 722 723 dev_set_drvdata(dev, panel); 724 725 /* 726 * We use runtime PM for prepare / unprepare since those power the panel 727 * on and off and those can be very slow operations. This is important 728 * to optimize powering the panel on briefly to read the EDID before 729 * fully enabling the panel. 730 */ 731 pm_runtime_enable(dev); 732 pm_runtime_set_autosuspend_delay(dev, 1000); 733 pm_runtime_use_autosuspend(dev); 734 735 err = drm_panel_of_backlight(&panel->base); 736 if (err) { 737 dev_err_probe(dev, err, "Could not find backlight\n"); 738 goto disable_pm_runtime; 739 } 740 741 drm_panel_add(&panel->base); 742 743 return panel; 744 745 disable_pm_runtime: 746 pm_runtime_dont_use_autosuspend(dev); 747 pm_runtime_disable(dev); 748 free_ddc: 749 if (panel->ddc) 750 put_device(&panel->ddc->dev); 751 752 return ERR_PTR(err); 753 } 754 755 static void panel_simple_shutdown(struct device *dev) 756 { 757 struct panel_simple *panel = dev_get_drvdata(dev); 758 759 /* 760 * NOTE: the following two calls don't really belong here. It is the 761 * responsibility of a correctly written DRM modeset driver to call 762 * drm_atomic_helper_shutdown() at shutdown time and that should 763 * cause the panel to be disabled / unprepared if needed. For now, 764 * however, we'll keep these calls due to the sheer number of 765 * different DRM modeset drivers used with panel-simple. Once we've 766 * confirmed that all DRM modeset drivers using this panel properly 767 * call drm_atomic_helper_shutdown() we can simply delete the two 768 * calls below. 769 * 770 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 771 * PANEL DRIVERS. 772 * 773 * FIXME: If we're still haven't figured out if all DRM modeset 774 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 775 * managed to make sure that DRM modeset drivers get their shutdown() 776 * callback before the panel's shutdown() callback (perhaps using 777 * device link), we could add a WARN_ON here to help move forward. 778 */ 779 if (panel->base.enabled) 780 drm_panel_disable(&panel->base); 781 if (panel->base.prepared) 782 drm_panel_unprepare(&panel->base); 783 } 784 785 static void panel_simple_remove(struct device *dev) 786 { 787 struct panel_simple *panel = dev_get_drvdata(dev); 788 789 drm_panel_remove(&panel->base); 790 panel_simple_shutdown(dev); 791 792 pm_runtime_dont_use_autosuspend(dev); 793 pm_runtime_disable(dev); 794 if (panel->ddc) 795 put_device(&panel->ddc->dev); 796 } 797 798 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 799 .clock = 71100, 800 .hdisplay = 1280, 801 .hsync_start = 1280 + 40, 802 .hsync_end = 1280 + 40 + 80, 803 .htotal = 1280 + 40 + 80 + 40, 804 .vdisplay = 800, 805 .vsync_start = 800 + 3, 806 .vsync_end = 800 + 3 + 10, 807 .vtotal = 800 + 3 + 10 + 10, 808 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 809 }; 810 811 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 812 .modes = &ire_am_1280800n3tzqw_t00h_mode, 813 .num_modes = 1, 814 .bpc = 8, 815 .size = { 816 .width = 217, 817 .height = 136, 818 }, 819 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 820 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 821 .connector_type = DRM_MODE_CONNECTOR_LVDS, 822 }; 823 824 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 825 .clock = 9000, 826 .hdisplay = 480, 827 .hsync_start = 480 + 2, 828 .hsync_end = 480 + 2 + 41, 829 .htotal = 480 + 2 + 41 + 2, 830 .vdisplay = 272, 831 .vsync_start = 272 + 2, 832 .vsync_end = 272 + 2 + 10, 833 .vtotal = 272 + 2 + 10 + 2, 834 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 835 }; 836 837 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 838 .modes = &ire_am_480272h3tmqw_t01h_mode, 839 .num_modes = 1, 840 .bpc = 8, 841 .size = { 842 .width = 99, 843 .height = 58, 844 }, 845 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 846 }; 847 848 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 849 .clock = 33333, 850 .hdisplay = 800, 851 .hsync_start = 800 + 0, 852 .hsync_end = 800 + 0 + 255, 853 .htotal = 800 + 0 + 255 + 0, 854 .vdisplay = 480, 855 .vsync_start = 480 + 2, 856 .vsync_end = 480 + 2 + 45, 857 .vtotal = 480 + 2 + 45 + 0, 858 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 859 }; 860 861 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 862 .pixelclock = { 29930000, 33260000, 36590000 }, 863 .hactive = { 800, 800, 800 }, 864 .hfront_porch = { 1, 40, 168 }, 865 .hback_porch = { 88, 88, 88 }, 866 .hsync_len = { 1, 128, 128 }, 867 .vactive = { 480, 480, 480 }, 868 .vfront_porch = { 1, 35, 37 }, 869 .vback_porch = { 8, 8, 8 }, 870 .vsync_len = { 1, 2, 2 }, 871 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 872 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 873 DISPLAY_FLAGS_SYNC_POSEDGE, 874 }; 875 876 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 877 .timings = &ire_am_800480l1tmqw_t00h_timing, 878 .num_timings = 1, 879 .bpc = 8, 880 .size = { 881 .width = 111, 882 .height = 67, 883 }, 884 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 885 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 886 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 887 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 888 .connector_type = DRM_MODE_CONNECTOR_DPI, 889 }; 890 891 static const struct panel_desc ampire_am800480r3tmqwa1h = { 892 .modes = &ire_am800480r3tmqwa1h_mode, 893 .num_modes = 1, 894 .bpc = 6, 895 .size = { 896 .width = 152, 897 .height = 91, 898 }, 899 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 900 }; 901 902 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 903 .pixelclock = { 34500000, 39600000, 50400000 }, 904 .hactive = { 800, 800, 800 }, 905 .hfront_porch = { 12, 112, 312 }, 906 .hback_porch = { 87, 87, 48 }, 907 .hsync_len = { 1, 1, 40 }, 908 .vactive = { 600, 600, 600 }, 909 .vfront_porch = { 1, 21, 61 }, 910 .vback_porch = { 38, 38, 19 }, 911 .vsync_len = { 1, 1, 20 }, 912 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 913 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 914 DISPLAY_FLAGS_SYNC_POSEDGE, 915 }; 916 917 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 918 .timings = &ire_am800600p5tmqw_tb8h_timing, 919 .num_timings = 1, 920 .bpc = 6, 921 .size = { 922 .width = 162, 923 .height = 122, 924 }, 925 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 926 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 927 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 928 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 929 .connector_type = DRM_MODE_CONNECTOR_DPI, 930 }; 931 932 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 933 .pixelclock = { 26400000, 33300000, 46800000 }, 934 .hactive = { 800, 800, 800 }, 935 .hfront_porch = { 16, 210, 354 }, 936 .hback_porch = { 45, 36, 6 }, 937 .hsync_len = { 1, 10, 40 }, 938 .vactive = { 480, 480, 480 }, 939 .vfront_porch = { 7, 22, 147 }, 940 .vback_porch = { 22, 13, 3 }, 941 .vsync_len = { 1, 10, 20 }, 942 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 943 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 944 }; 945 946 static const struct panel_desc armadeus_st0700_adapt = { 947 .timings = &santek_st0700i5y_rbslw_f_timing, 948 .num_timings = 1, 949 .bpc = 6, 950 .size = { 951 .width = 154, 952 .height = 86, 953 }, 954 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 955 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 956 }; 957 958 static const struct drm_display_mode auo_b101aw03_mode = { 959 .clock = 51450, 960 .hdisplay = 1024, 961 .hsync_start = 1024 + 156, 962 .hsync_end = 1024 + 156 + 8, 963 .htotal = 1024 + 156 + 8 + 156, 964 .vdisplay = 600, 965 .vsync_start = 600 + 16, 966 .vsync_end = 600 + 16 + 6, 967 .vtotal = 600 + 16 + 6 + 16, 968 }; 969 970 static const struct panel_desc auo_b101aw03 = { 971 .modes = &auo_b101aw03_mode, 972 .num_modes = 1, 973 .bpc = 6, 974 .size = { 975 .width = 223, 976 .height = 125, 977 }, 978 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 979 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 980 .connector_type = DRM_MODE_CONNECTOR_LVDS, 981 }; 982 983 static const struct drm_display_mode auo_b101xtn01_mode = { 984 .clock = 72000, 985 .hdisplay = 1366, 986 .hsync_start = 1366 + 20, 987 .hsync_end = 1366 + 20 + 70, 988 .htotal = 1366 + 20 + 70, 989 .vdisplay = 768, 990 .vsync_start = 768 + 14, 991 .vsync_end = 768 + 14 + 42, 992 .vtotal = 768 + 14 + 42, 993 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 994 }; 995 996 static const struct panel_desc auo_b101xtn01 = { 997 .modes = &auo_b101xtn01_mode, 998 .num_modes = 1, 999 .bpc = 6, 1000 .size = { 1001 .width = 223, 1002 .height = 125, 1003 }, 1004 }; 1005 1006 static const struct drm_display_mode auo_b116xw03_mode = { 1007 .clock = 70589, 1008 .hdisplay = 1366, 1009 .hsync_start = 1366 + 40, 1010 .hsync_end = 1366 + 40 + 40, 1011 .htotal = 1366 + 40 + 40 + 32, 1012 .vdisplay = 768, 1013 .vsync_start = 768 + 10, 1014 .vsync_end = 768 + 10 + 12, 1015 .vtotal = 768 + 10 + 12 + 6, 1016 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1017 }; 1018 1019 static const struct panel_desc auo_b116xw03 = { 1020 .modes = &auo_b116xw03_mode, 1021 .num_modes = 1, 1022 .bpc = 6, 1023 .size = { 1024 .width = 256, 1025 .height = 144, 1026 }, 1027 .delay = { 1028 .prepare = 1, 1029 .enable = 200, 1030 .disable = 200, 1031 .unprepare = 500, 1032 }, 1033 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1034 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1035 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1036 }; 1037 1038 static const struct display_timing auo_g070vvn01_timings = { 1039 .pixelclock = { 33300000, 34209000, 45000000 }, 1040 .hactive = { 800, 800, 800 }, 1041 .hfront_porch = { 20, 40, 200 }, 1042 .hback_porch = { 87, 40, 1 }, 1043 .hsync_len = { 1, 48, 87 }, 1044 .vactive = { 480, 480, 480 }, 1045 .vfront_porch = { 5, 13, 200 }, 1046 .vback_porch = { 31, 31, 29 }, 1047 .vsync_len = { 1, 1, 3 }, 1048 }; 1049 1050 static const struct panel_desc auo_g070vvn01 = { 1051 .timings = &auo_g070vvn01_timings, 1052 .num_timings = 1, 1053 .bpc = 8, 1054 .size = { 1055 .width = 152, 1056 .height = 91, 1057 }, 1058 .delay = { 1059 .prepare = 200, 1060 .enable = 50, 1061 .disable = 50, 1062 .unprepare = 1000, 1063 }, 1064 }; 1065 1066 static const struct display_timing auo_g101evn010_timing = { 1067 .pixelclock = { 64000000, 68930000, 85000000 }, 1068 .hactive = { 1280, 1280, 1280 }, 1069 .hfront_porch = { 8, 64, 256 }, 1070 .hback_porch = { 8, 64, 256 }, 1071 .hsync_len = { 40, 168, 767 }, 1072 .vactive = { 800, 800, 800 }, 1073 .vfront_porch = { 4, 8, 100 }, 1074 .vback_porch = { 4, 8, 100 }, 1075 .vsync_len = { 8, 16, 223 }, 1076 }; 1077 1078 static const struct panel_desc auo_g101evn010 = { 1079 .timings = &auo_g101evn010_timing, 1080 .num_timings = 1, 1081 .bpc = 6, 1082 .size = { 1083 .width = 216, 1084 .height = 135, 1085 }, 1086 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1087 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1088 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1089 }; 1090 1091 static const struct drm_display_mode auo_g104sn02_mode = { 1092 .clock = 40000, 1093 .hdisplay = 800, 1094 .hsync_start = 800 + 40, 1095 .hsync_end = 800 + 40 + 216, 1096 .htotal = 800 + 40 + 216 + 128, 1097 .vdisplay = 600, 1098 .vsync_start = 600 + 10, 1099 .vsync_end = 600 + 10 + 35, 1100 .vtotal = 600 + 10 + 35 + 2, 1101 }; 1102 1103 static const struct panel_desc auo_g104sn02 = { 1104 .modes = &auo_g104sn02_mode, 1105 .num_modes = 1, 1106 .bpc = 8, 1107 .size = { 1108 .width = 211, 1109 .height = 158, 1110 }, 1111 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1112 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1113 }; 1114 1115 static const struct drm_display_mode auo_g104stn01_mode = { 1116 .clock = 40000, 1117 .hdisplay = 800, 1118 .hsync_start = 800 + 40, 1119 .hsync_end = 800 + 40 + 88, 1120 .htotal = 800 + 40 + 88 + 128, 1121 .vdisplay = 600, 1122 .vsync_start = 600 + 1, 1123 .vsync_end = 600 + 1 + 23, 1124 .vtotal = 600 + 1 + 23 + 4, 1125 }; 1126 1127 static const struct panel_desc auo_g104stn01 = { 1128 .modes = &auo_g104stn01_mode, 1129 .num_modes = 1, 1130 .bpc = 8, 1131 .size = { 1132 .width = 211, 1133 .height = 158, 1134 }, 1135 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1136 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1137 }; 1138 1139 static const struct display_timing auo_g121ean01_timing = { 1140 .pixelclock = { 60000000, 74400000, 90000000 }, 1141 .hactive = { 1280, 1280, 1280 }, 1142 .hfront_porch = { 20, 50, 100 }, 1143 .hback_porch = { 20, 50, 100 }, 1144 .hsync_len = { 30, 100, 200 }, 1145 .vactive = { 800, 800, 800 }, 1146 .vfront_porch = { 2, 10, 25 }, 1147 .vback_porch = { 2, 10, 25 }, 1148 .vsync_len = { 4, 18, 50 }, 1149 }; 1150 1151 static const struct panel_desc auo_g121ean01 = { 1152 .timings = &auo_g121ean01_timing, 1153 .num_timings = 1, 1154 .bpc = 8, 1155 .size = { 1156 .width = 261, 1157 .height = 163, 1158 }, 1159 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1160 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1161 }; 1162 1163 static const struct display_timing auo_g133han01_timings = { 1164 .pixelclock = { 134000000, 141200000, 149000000 }, 1165 .hactive = { 1920, 1920, 1920 }, 1166 .hfront_porch = { 39, 58, 77 }, 1167 .hback_porch = { 59, 88, 117 }, 1168 .hsync_len = { 28, 42, 56 }, 1169 .vactive = { 1080, 1080, 1080 }, 1170 .vfront_porch = { 3, 8, 11 }, 1171 .vback_porch = { 5, 14, 19 }, 1172 .vsync_len = { 4, 14, 19 }, 1173 }; 1174 1175 static const struct panel_desc auo_g133han01 = { 1176 .timings = &auo_g133han01_timings, 1177 .num_timings = 1, 1178 .bpc = 8, 1179 .size = { 1180 .width = 293, 1181 .height = 165, 1182 }, 1183 .delay = { 1184 .prepare = 200, 1185 .enable = 50, 1186 .disable = 50, 1187 .unprepare = 1000, 1188 }, 1189 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1190 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1191 }; 1192 1193 static const struct display_timing auo_g156han04_timings = { 1194 .pixelclock = { 137000000, 141000000, 146000000 }, 1195 .hactive = { 1920, 1920, 1920 }, 1196 .hfront_porch = { 60, 60, 60 }, 1197 .hback_porch = { 90, 92, 111 }, 1198 .hsync_len = { 32, 32, 32 }, 1199 .vactive = { 1080, 1080, 1080 }, 1200 .vfront_porch = { 12, 12, 12 }, 1201 .vback_porch = { 24, 36, 56 }, 1202 .vsync_len = { 8, 8, 8 }, 1203 }; 1204 1205 static const struct panel_desc auo_g156han04 = { 1206 .timings = &auo_g156han04_timings, 1207 .num_timings = 1, 1208 .bpc = 8, 1209 .size = { 1210 .width = 344, 1211 .height = 194, 1212 }, 1213 .delay = { 1214 .prepare = 50, /* T2 */ 1215 .enable = 200, /* T3 */ 1216 .disable = 110, /* T10 */ 1217 .unprepare = 1000, /* T13 */ 1218 }, 1219 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1220 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1221 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1222 }; 1223 1224 static const struct drm_display_mode auo_g156xtn01_mode = { 1225 .clock = 76000, 1226 .hdisplay = 1366, 1227 .hsync_start = 1366 + 33, 1228 .hsync_end = 1366 + 33 + 67, 1229 .htotal = 1560, 1230 .vdisplay = 768, 1231 .vsync_start = 768 + 4, 1232 .vsync_end = 768 + 4 + 4, 1233 .vtotal = 806, 1234 }; 1235 1236 static const struct panel_desc auo_g156xtn01 = { 1237 .modes = &auo_g156xtn01_mode, 1238 .num_modes = 1, 1239 .bpc = 8, 1240 .size = { 1241 .width = 344, 1242 .height = 194, 1243 }, 1244 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1245 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1246 }; 1247 1248 static const struct display_timing auo_g185han01_timings = { 1249 .pixelclock = { 120000000, 144000000, 175000000 }, 1250 .hactive = { 1920, 1920, 1920 }, 1251 .hfront_porch = { 36, 120, 148 }, 1252 .hback_porch = { 24, 88, 108 }, 1253 .hsync_len = { 20, 48, 64 }, 1254 .vactive = { 1080, 1080, 1080 }, 1255 .vfront_porch = { 6, 10, 40 }, 1256 .vback_porch = { 2, 5, 20 }, 1257 .vsync_len = { 2, 5, 20 }, 1258 }; 1259 1260 static const struct panel_desc auo_g185han01 = { 1261 .timings = &auo_g185han01_timings, 1262 .num_timings = 1, 1263 .bpc = 8, 1264 .size = { 1265 .width = 409, 1266 .height = 230, 1267 }, 1268 .delay = { 1269 .prepare = 50, 1270 .enable = 200, 1271 .disable = 110, 1272 .unprepare = 1000, 1273 }, 1274 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1275 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1276 }; 1277 1278 static const struct display_timing auo_g190ean01_timings = { 1279 .pixelclock = { 90000000, 108000000, 135000000 }, 1280 .hactive = { 1280, 1280, 1280 }, 1281 .hfront_porch = { 126, 184, 1266 }, 1282 .hback_porch = { 84, 122, 844 }, 1283 .hsync_len = { 70, 102, 704 }, 1284 .vactive = { 1024, 1024, 1024 }, 1285 .vfront_porch = { 4, 26, 76 }, 1286 .vback_porch = { 2, 8, 25 }, 1287 .vsync_len = { 2, 8, 25 }, 1288 }; 1289 1290 static const struct panel_desc auo_g190ean01 = { 1291 .timings = &auo_g190ean01_timings, 1292 .num_timings = 1, 1293 .bpc = 8, 1294 .size = { 1295 .width = 376, 1296 .height = 301, 1297 }, 1298 .delay = { 1299 .prepare = 50, 1300 .enable = 200, 1301 .disable = 110, 1302 .unprepare = 1000, 1303 }, 1304 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1305 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1306 }; 1307 1308 static const struct display_timing auo_p238han01_timings = { 1309 .pixelclock = { 107400000, 142400000, 180000000 }, 1310 .hactive = { 1920, 1920, 1920 }, 1311 .hfront_porch = { 30, 70, 650 }, 1312 .hback_porch = { 30, 70, 650 }, 1313 .hsync_len = { 20, 40, 136 }, 1314 .vactive = { 1080, 1080, 1080 }, 1315 .vfront_porch = { 5, 19, 318 }, 1316 .vback_porch = { 5, 19, 318 }, 1317 .vsync_len = { 4, 12, 120 }, 1318 }; 1319 1320 static const struct panel_desc auo_p238han01 = { 1321 .timings = &auo_p238han01_timings, 1322 .num_timings = 1, 1323 .bpc = 8, 1324 .size = { 1325 .width = 527, 1326 .height = 296, 1327 }, 1328 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1329 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1330 }; 1331 1332 static const struct display_timing auo_p320hvn03_timings = { 1333 .pixelclock = { 106000000, 148500000, 164000000 }, 1334 .hactive = { 1920, 1920, 1920 }, 1335 .hfront_porch = { 25, 50, 130 }, 1336 .hback_porch = { 25, 50, 130 }, 1337 .hsync_len = { 20, 40, 105 }, 1338 .vactive = { 1080, 1080, 1080 }, 1339 .vfront_porch = { 8, 17, 150 }, 1340 .vback_porch = { 8, 17, 150 }, 1341 .vsync_len = { 4, 11, 100 }, 1342 }; 1343 1344 static const struct panel_desc auo_p320hvn03 = { 1345 .timings = &auo_p320hvn03_timings, 1346 .num_timings = 1, 1347 .bpc = 8, 1348 .size = { 1349 .width = 698, 1350 .height = 393, 1351 }, 1352 .delay = { 1353 .prepare = 1, 1354 .enable = 450, 1355 .unprepare = 500, 1356 }, 1357 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1358 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1359 }; 1360 1361 static const struct drm_display_mode auo_t215hvn01_mode = { 1362 .clock = 148800, 1363 .hdisplay = 1920, 1364 .hsync_start = 1920 + 88, 1365 .hsync_end = 1920 + 88 + 44, 1366 .htotal = 1920 + 88 + 44 + 148, 1367 .vdisplay = 1080, 1368 .vsync_start = 1080 + 4, 1369 .vsync_end = 1080 + 4 + 5, 1370 .vtotal = 1080 + 4 + 5 + 36, 1371 }; 1372 1373 static const struct panel_desc auo_t215hvn01 = { 1374 .modes = &auo_t215hvn01_mode, 1375 .num_modes = 1, 1376 .bpc = 8, 1377 .size = { 1378 .width = 430, 1379 .height = 270, 1380 }, 1381 .delay = { 1382 .disable = 5, 1383 .unprepare = 1000, 1384 }, 1385 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1386 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1387 }; 1388 1389 static const struct drm_display_mode avic_tm070ddh03_mode = { 1390 .clock = 51200, 1391 .hdisplay = 1024, 1392 .hsync_start = 1024 + 160, 1393 .hsync_end = 1024 + 160 + 4, 1394 .htotal = 1024 + 160 + 4 + 156, 1395 .vdisplay = 600, 1396 .vsync_start = 600 + 17, 1397 .vsync_end = 600 + 17 + 1, 1398 .vtotal = 600 + 17 + 1 + 17, 1399 }; 1400 1401 static const struct panel_desc avic_tm070ddh03 = { 1402 .modes = &avic_tm070ddh03_mode, 1403 .num_modes = 1, 1404 .bpc = 8, 1405 .size = { 1406 .width = 154, 1407 .height = 90, 1408 }, 1409 .delay = { 1410 .prepare = 20, 1411 .enable = 200, 1412 .disable = 200, 1413 }, 1414 }; 1415 1416 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1417 .clock = 30000, 1418 .hdisplay = 800, 1419 .hsync_start = 800 + 40, 1420 .hsync_end = 800 + 40 + 48, 1421 .htotal = 800 + 40 + 48 + 40, 1422 .vdisplay = 480, 1423 .vsync_start = 480 + 13, 1424 .vsync_end = 480 + 13 + 3, 1425 .vtotal = 480 + 13 + 3 + 29, 1426 }; 1427 1428 static const struct panel_desc bananapi_s070wv20_ct16 = { 1429 .modes = &bananapi_s070wv20_ct16_mode, 1430 .num_modes = 1, 1431 .bpc = 6, 1432 .size = { 1433 .width = 154, 1434 .height = 86, 1435 }, 1436 }; 1437 1438 static const struct display_timing boe_av101hdt_a10_timing = { 1439 .pixelclock = { 74210000, 75330000, 76780000, }, 1440 .hactive = { 1280, 1280, 1280, }, 1441 .hfront_porch = { 10, 42, 33, }, 1442 .hback_porch = { 10, 18, 33, }, 1443 .hsync_len = { 30, 10, 30, }, 1444 .vactive = { 720, 720, 720, }, 1445 .vfront_porch = { 200, 183, 200, }, 1446 .vback_porch = { 8, 8, 8, }, 1447 .vsync_len = { 2, 19, 2, }, 1448 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1449 }; 1450 1451 static const struct panel_desc boe_av101hdt_a10 = { 1452 .timings = &boe_av101hdt_a10_timing, 1453 .num_timings = 1, 1454 .bpc = 8, 1455 .size = { 1456 .width = 224, 1457 .height = 126, 1458 }, 1459 .delay = { 1460 .enable = 50, 1461 .disable = 50, 1462 }, 1463 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1464 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1465 }; 1466 1467 static const struct display_timing boe_av123z7m_n17_timing = { 1468 .pixelclock = { 86600000, 88000000, 90800000, }, 1469 .hactive = { 1920, 1920, 1920, }, 1470 .hfront_porch = { 10, 10, 10, }, 1471 .hback_porch = { 10, 10, 10, }, 1472 .hsync_len = { 9, 12, 25, }, 1473 .vactive = { 720, 720, 720, }, 1474 .vfront_porch = { 7, 10, 13, }, 1475 .vback_porch = { 7, 10, 13, }, 1476 .vsync_len = { 7, 11, 14, }, 1477 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1478 }; 1479 1480 static const struct panel_desc boe_av123z7m_n17 = { 1481 .timings = &boe_av123z7m_n17_timing, 1482 .bpc = 8, 1483 .num_timings = 1, 1484 .size = { 1485 .width = 292, 1486 .height = 110, 1487 }, 1488 .delay = { 1489 .prepare = 50, 1490 .disable = 50, 1491 }, 1492 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1493 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1494 }; 1495 1496 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1497 .clock = 78945, 1498 .hdisplay = 1280, 1499 .hsync_start = 1280 + 0, 1500 .hsync_end = 1280 + 0 + 2, 1501 .htotal = 1280 + 62 + 0 + 2, 1502 .vdisplay = 800, 1503 .vsync_start = 800 + 8, 1504 .vsync_end = 800 + 8 + 2, 1505 .vtotal = 800 + 6 + 8 + 2, 1506 }; 1507 1508 static const struct panel_desc boe_bp082wx1_100 = { 1509 .modes = &boe_bp101wx1_100_mode, 1510 .num_modes = 1, 1511 .bpc = 8, 1512 .size = { 1513 .width = 177, 1514 .height = 110, 1515 }, 1516 .delay = { 1517 .enable = 50, 1518 .disable = 50, 1519 }, 1520 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1521 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1522 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1523 }; 1524 1525 static const struct panel_desc boe_bp101wx1_100 = { 1526 .modes = &boe_bp101wx1_100_mode, 1527 .num_modes = 1, 1528 .bpc = 8, 1529 .size = { 1530 .width = 217, 1531 .height = 136, 1532 }, 1533 .delay = { 1534 .enable = 50, 1535 .disable = 50, 1536 }, 1537 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1538 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1539 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1540 }; 1541 1542 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1543 .pixelclock = { 69922000, 71000000, 72293000 }, 1544 .hactive = { 1280, 1280, 1280 }, 1545 .hfront_porch = { 48, 48, 48 }, 1546 .hback_porch = { 80, 80, 80 }, 1547 .hsync_len = { 32, 32, 32 }, 1548 .vactive = { 800, 800, 800 }, 1549 .vfront_porch = { 3, 3, 3 }, 1550 .vback_porch = { 14, 14, 14 }, 1551 .vsync_len = { 6, 6, 6 }, 1552 }; 1553 1554 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1555 .timings = &boe_ev121wxm_n10_1850_timing, 1556 .num_timings = 1, 1557 .bpc = 8, 1558 .size = { 1559 .width = 261, 1560 .height = 163, 1561 }, 1562 .delay = { 1563 .prepare = 9, 1564 .enable = 300, 1565 .unprepare = 300, 1566 .disable = 560, 1567 }, 1568 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1569 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1570 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1571 }; 1572 1573 static const struct drm_display_mode boe_hv070wsa_mode = { 1574 .clock = 42105, 1575 .hdisplay = 1024, 1576 .hsync_start = 1024 + 30, 1577 .hsync_end = 1024 + 30 + 30, 1578 .htotal = 1024 + 30 + 30 + 30, 1579 .vdisplay = 600, 1580 .vsync_start = 600 + 10, 1581 .vsync_end = 600 + 10 + 10, 1582 .vtotal = 600 + 10 + 10 + 10, 1583 }; 1584 1585 static const struct panel_desc boe_hv070wsa = { 1586 .modes = &boe_hv070wsa_mode, 1587 .num_modes = 1, 1588 .bpc = 8, 1589 .size = { 1590 .width = 154, 1591 .height = 90, 1592 }, 1593 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1594 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1595 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1596 }; 1597 1598 static const struct display_timing cct_cmt430b19n00_timing = { 1599 .pixelclock = { 8000000, 9000000, 12000000 }, 1600 .hactive = { 480, 480, 480 }, 1601 .hfront_porch = { 2, 8, 75 }, 1602 .hback_porch = { 3, 43, 43 }, 1603 .hsync_len = { 2, 4, 75 }, 1604 .vactive = { 272, 272, 272 }, 1605 .vfront_porch = { 2, 8, 37 }, 1606 .vback_porch = { 2, 12, 12 }, 1607 .vsync_len = { 2, 4, 37 }, 1608 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1609 }; 1610 1611 static const struct panel_desc cct_cmt430b19n00 = { 1612 .timings = &cct_cmt430b19n00_timing, 1613 .num_timings = 1, 1614 .bpc = 8, 1615 .size = { 1616 .width = 95, 1617 .height = 53, 1618 }, 1619 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1620 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1621 .connector_type = DRM_MODE_CONNECTOR_DPI, 1622 }; 1623 1624 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1625 .clock = 9000, 1626 .hdisplay = 480, 1627 .hsync_start = 480 + 5, 1628 .hsync_end = 480 + 5 + 5, 1629 .htotal = 480 + 5 + 5 + 40, 1630 .vdisplay = 272, 1631 .vsync_start = 272 + 8, 1632 .vsync_end = 272 + 8 + 8, 1633 .vtotal = 272 + 8 + 8 + 8, 1634 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1635 }; 1636 1637 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1638 .modes = &cdtech_s043wq26h_ct7_mode, 1639 .num_modes = 1, 1640 .bpc = 8, 1641 .size = { 1642 .width = 95, 1643 .height = 54, 1644 }, 1645 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1646 }; 1647 1648 /* S070PWS19HP-FC21 2017/04/22 */ 1649 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1650 .clock = 51200, 1651 .hdisplay = 1024, 1652 .hsync_start = 1024 + 160, 1653 .hsync_end = 1024 + 160 + 20, 1654 .htotal = 1024 + 160 + 20 + 140, 1655 .vdisplay = 600, 1656 .vsync_start = 600 + 12, 1657 .vsync_end = 600 + 12 + 3, 1658 .vtotal = 600 + 12 + 3 + 20, 1659 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1660 }; 1661 1662 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1663 .modes = &cdtech_s070pws19hp_fc21_mode, 1664 .num_modes = 1, 1665 .bpc = 6, 1666 .size = { 1667 .width = 154, 1668 .height = 86, 1669 }, 1670 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1671 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1672 .connector_type = DRM_MODE_CONNECTOR_DPI, 1673 }; 1674 1675 /* S070SWV29HG-DC44 2017/09/21 */ 1676 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1677 .clock = 33300, 1678 .hdisplay = 800, 1679 .hsync_start = 800 + 210, 1680 .hsync_end = 800 + 210 + 2, 1681 .htotal = 800 + 210 + 2 + 44, 1682 .vdisplay = 480, 1683 .vsync_start = 480 + 22, 1684 .vsync_end = 480 + 22 + 2, 1685 .vtotal = 480 + 22 + 2 + 21, 1686 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1687 }; 1688 1689 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1690 .modes = &cdtech_s070swv29hg_dc44_mode, 1691 .num_modes = 1, 1692 .bpc = 6, 1693 .size = { 1694 .width = 154, 1695 .height = 86, 1696 }, 1697 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1698 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1699 .connector_type = DRM_MODE_CONNECTOR_DPI, 1700 }; 1701 1702 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1703 .clock = 35000, 1704 .hdisplay = 800, 1705 .hsync_start = 800 + 40, 1706 .hsync_end = 800 + 40 + 40, 1707 .htotal = 800 + 40 + 40 + 48, 1708 .vdisplay = 480, 1709 .vsync_start = 480 + 29, 1710 .vsync_end = 480 + 29 + 13, 1711 .vtotal = 480 + 29 + 13 + 3, 1712 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1713 }; 1714 1715 static const struct panel_desc cdtech_s070wv95_ct16 = { 1716 .modes = &cdtech_s070wv95_ct16_mode, 1717 .num_modes = 1, 1718 .bpc = 8, 1719 .size = { 1720 .width = 154, 1721 .height = 85, 1722 }, 1723 }; 1724 1725 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1726 .pixelclock = { 68900000, 71100000, 73400000 }, 1727 .hactive = { 1280, 1280, 1280 }, 1728 .hfront_porch = { 65, 80, 95 }, 1729 .hback_porch = { 64, 79, 94 }, 1730 .hsync_len = { 1, 1, 1 }, 1731 .vactive = { 800, 800, 800 }, 1732 .vfront_porch = { 7, 11, 14 }, 1733 .vback_porch = { 7, 11, 14 }, 1734 .vsync_len = { 1, 1, 1 }, 1735 .flags = DISPLAY_FLAGS_DE_HIGH, 1736 }; 1737 1738 static const struct panel_desc chefree_ch101olhlwh_002 = { 1739 .timings = &chefree_ch101olhlwh_002_timing, 1740 .num_timings = 1, 1741 .bpc = 8, 1742 .size = { 1743 .width = 217, 1744 .height = 135, 1745 }, 1746 .delay = { 1747 .enable = 200, 1748 .disable = 200, 1749 }, 1750 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1751 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1752 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1753 }; 1754 1755 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1756 .clock = 66770, 1757 .hdisplay = 800, 1758 .hsync_start = 800 + 49, 1759 .hsync_end = 800 + 49 + 33, 1760 .htotal = 800 + 49 + 33 + 17, 1761 .vdisplay = 1280, 1762 .vsync_start = 1280 + 1, 1763 .vsync_end = 1280 + 1 + 7, 1764 .vtotal = 1280 + 1 + 7 + 15, 1765 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1766 }; 1767 1768 static const struct panel_desc chunghwa_claa070wp03xg = { 1769 .modes = &chunghwa_claa070wp03xg_mode, 1770 .num_modes = 1, 1771 .bpc = 6, 1772 .size = { 1773 .width = 94, 1774 .height = 150, 1775 }, 1776 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1777 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1778 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1779 }; 1780 1781 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1782 .clock = 72070, 1783 .hdisplay = 1366, 1784 .hsync_start = 1366 + 58, 1785 .hsync_end = 1366 + 58 + 58, 1786 .htotal = 1366 + 58 + 58 + 58, 1787 .vdisplay = 768, 1788 .vsync_start = 768 + 4, 1789 .vsync_end = 768 + 4 + 4, 1790 .vtotal = 768 + 4 + 4 + 4, 1791 }; 1792 1793 static const struct panel_desc chunghwa_claa101wa01a = { 1794 .modes = &chunghwa_claa101wa01a_mode, 1795 .num_modes = 1, 1796 .bpc = 6, 1797 .size = { 1798 .width = 220, 1799 .height = 120, 1800 }, 1801 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1802 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1803 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1804 }; 1805 1806 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1807 .clock = 69300, 1808 .hdisplay = 1366, 1809 .hsync_start = 1366 + 48, 1810 .hsync_end = 1366 + 48 + 32, 1811 .htotal = 1366 + 48 + 32 + 20, 1812 .vdisplay = 768, 1813 .vsync_start = 768 + 16, 1814 .vsync_end = 768 + 16 + 8, 1815 .vtotal = 768 + 16 + 8 + 16, 1816 }; 1817 1818 static const struct panel_desc chunghwa_claa101wb01 = { 1819 .modes = &chunghwa_claa101wb01_mode, 1820 .num_modes = 1, 1821 .bpc = 6, 1822 .size = { 1823 .width = 223, 1824 .height = 125, 1825 }, 1826 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1827 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1828 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1829 }; 1830 1831 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1832 .pixelclock = { 5000000, 9000000, 12000000 }, 1833 .hactive = { 480, 480, 480 }, 1834 .hfront_porch = { 12, 12, 12 }, 1835 .hback_porch = { 12, 12, 12 }, 1836 .hsync_len = { 21, 21, 21 }, 1837 .vactive = { 272, 272, 272 }, 1838 .vfront_porch = { 4, 4, 4 }, 1839 .vback_porch = { 4, 4, 4 }, 1840 .vsync_len = { 8, 8, 8 }, 1841 }; 1842 1843 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1844 .timings = &dataimage_fg040346dsswbg04_timing, 1845 .num_timings = 1, 1846 .bpc = 8, 1847 .size = { 1848 .width = 95, 1849 .height = 54, 1850 }, 1851 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1852 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1853 .connector_type = DRM_MODE_CONNECTOR_DPI, 1854 }; 1855 1856 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1857 .pixelclock = { 68900000, 71110000, 73400000 }, 1858 .hactive = { 1280, 1280, 1280 }, 1859 .vactive = { 800, 800, 800 }, 1860 .hback_porch = { 100, 100, 100 }, 1861 .hfront_porch = { 100, 100, 100 }, 1862 .vback_porch = { 5, 5, 5 }, 1863 .vfront_porch = { 5, 5, 5 }, 1864 .hsync_len = { 24, 24, 24 }, 1865 .vsync_len = { 3, 3, 3 }, 1866 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1867 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1868 }; 1869 1870 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1871 .timings = &dataimage_fg1001l0dsswmg01_timing, 1872 .num_timings = 1, 1873 .bpc = 8, 1874 .size = { 1875 .width = 217, 1876 .height = 136, 1877 }, 1878 }; 1879 1880 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1881 .clock = 33260, 1882 .hdisplay = 800, 1883 .hsync_start = 800 + 40, 1884 .hsync_end = 800 + 40 + 128, 1885 .htotal = 800 + 40 + 128 + 88, 1886 .vdisplay = 480, 1887 .vsync_start = 480 + 10, 1888 .vsync_end = 480 + 10 + 2, 1889 .vtotal = 480 + 10 + 2 + 33, 1890 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1891 }; 1892 1893 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1894 .modes = &dataimage_scf0700c48ggu18_mode, 1895 .num_modes = 1, 1896 .bpc = 8, 1897 .size = { 1898 .width = 152, 1899 .height = 91, 1900 }, 1901 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1902 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1903 }; 1904 1905 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1906 .pixelclock = { 45000000, 51200000, 57000000 }, 1907 .hactive = { 1024, 1024, 1024 }, 1908 .hfront_porch = { 100, 106, 113 }, 1909 .hback_porch = { 100, 106, 113 }, 1910 .hsync_len = { 100, 108, 114 }, 1911 .vactive = { 600, 600, 600 }, 1912 .vfront_porch = { 8, 11, 15 }, 1913 .vback_porch = { 8, 11, 15 }, 1914 .vsync_len = { 9, 13, 15 }, 1915 .flags = DISPLAY_FLAGS_DE_HIGH, 1916 }; 1917 1918 static const struct panel_desc dlc_dlc0700yzg_1 = { 1919 .timings = &dlc_dlc0700yzg_1_timing, 1920 .num_timings = 1, 1921 .bpc = 6, 1922 .size = { 1923 .width = 154, 1924 .height = 86, 1925 }, 1926 .delay = { 1927 .prepare = 30, 1928 .enable = 200, 1929 .disable = 200, 1930 }, 1931 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1932 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1933 }; 1934 1935 static const struct display_timing dlc_dlc1010gig_timing = { 1936 .pixelclock = { 68900000, 71100000, 73400000 }, 1937 .hactive = { 1280, 1280, 1280 }, 1938 .hfront_porch = { 43, 53, 63 }, 1939 .hback_porch = { 43, 53, 63 }, 1940 .hsync_len = { 44, 54, 64 }, 1941 .vactive = { 800, 800, 800 }, 1942 .vfront_porch = { 5, 8, 11 }, 1943 .vback_porch = { 5, 8, 11 }, 1944 .vsync_len = { 5, 7, 11 }, 1945 .flags = DISPLAY_FLAGS_DE_HIGH, 1946 }; 1947 1948 static const struct panel_desc dlc_dlc1010gig = { 1949 .timings = &dlc_dlc1010gig_timing, 1950 .num_timings = 1, 1951 .bpc = 8, 1952 .size = { 1953 .width = 216, 1954 .height = 135, 1955 }, 1956 .delay = { 1957 .prepare = 60, 1958 .enable = 150, 1959 .disable = 100, 1960 .unprepare = 60, 1961 }, 1962 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1963 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1964 }; 1965 1966 static const struct drm_display_mode edt_et035012dm6_mode = { 1967 .clock = 6500, 1968 .hdisplay = 320, 1969 .hsync_start = 320 + 20, 1970 .hsync_end = 320 + 20 + 30, 1971 .htotal = 320 + 20 + 68, 1972 .vdisplay = 240, 1973 .vsync_start = 240 + 4, 1974 .vsync_end = 240 + 4 + 4, 1975 .vtotal = 240 + 4 + 4 + 14, 1976 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1977 }; 1978 1979 static const struct panel_desc edt_et035012dm6 = { 1980 .modes = &edt_et035012dm6_mode, 1981 .num_modes = 1, 1982 .bpc = 8, 1983 .size = { 1984 .width = 70, 1985 .height = 52, 1986 }, 1987 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1988 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1989 }; 1990 1991 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1992 .clock = 6520, 1993 .hdisplay = 320, 1994 .hsync_start = 320 + 20, 1995 .hsync_end = 320 + 20 + 68, 1996 .htotal = 320 + 20 + 68, 1997 .vdisplay = 240, 1998 .vsync_start = 240 + 4, 1999 .vsync_end = 240 + 4 + 18, 2000 .vtotal = 240 + 4 + 18, 2001 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2002 }; 2003 2004 static const struct panel_desc edt_etm0350g0dh6 = { 2005 .modes = &edt_etm0350g0dh6_mode, 2006 .num_modes = 1, 2007 .bpc = 6, 2008 .size = { 2009 .width = 70, 2010 .height = 53, 2011 }, 2012 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2013 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2014 .connector_type = DRM_MODE_CONNECTOR_DPI, 2015 }; 2016 2017 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 2018 .clock = 10870, 2019 .hdisplay = 480, 2020 .hsync_start = 480 + 8, 2021 .hsync_end = 480 + 8 + 4, 2022 .htotal = 480 + 8 + 4 + 41, 2023 2024 /* 2025 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 2026 * fb_align 2027 */ 2028 2029 .vdisplay = 288, 2030 .vsync_start = 288 + 2, 2031 .vsync_end = 288 + 2 + 4, 2032 .vtotal = 288 + 2 + 4 + 10, 2033 }; 2034 2035 static const struct panel_desc edt_etm043080dh6gp = { 2036 .modes = &edt_etm043080dh6gp_mode, 2037 .num_modes = 1, 2038 .bpc = 8, 2039 .size = { 2040 .width = 100, 2041 .height = 65, 2042 }, 2043 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2044 .connector_type = DRM_MODE_CONNECTOR_DPI, 2045 }; 2046 2047 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 2048 .clock = 9000, 2049 .hdisplay = 480, 2050 .hsync_start = 480 + 2, 2051 .hsync_end = 480 + 2 + 41, 2052 .htotal = 480 + 2 + 41 + 2, 2053 .vdisplay = 272, 2054 .vsync_start = 272 + 2, 2055 .vsync_end = 272 + 2 + 10, 2056 .vtotal = 272 + 2 + 10 + 2, 2057 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2058 }; 2059 2060 static const struct panel_desc edt_etm0430g0dh6 = { 2061 .modes = &edt_etm0430g0dh6_mode, 2062 .num_modes = 1, 2063 .bpc = 6, 2064 .size = { 2065 .width = 95, 2066 .height = 54, 2067 }, 2068 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2069 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2070 .connector_type = DRM_MODE_CONNECTOR_DPI, 2071 }; 2072 2073 static const struct drm_display_mode edt_et057090dhu_mode = { 2074 .clock = 25175, 2075 .hdisplay = 640, 2076 .hsync_start = 640 + 16, 2077 .hsync_end = 640 + 16 + 30, 2078 .htotal = 640 + 16 + 30 + 114, 2079 .vdisplay = 480, 2080 .vsync_start = 480 + 10, 2081 .vsync_end = 480 + 10 + 3, 2082 .vtotal = 480 + 10 + 3 + 32, 2083 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2084 }; 2085 2086 static const struct panel_desc edt_et057090dhu = { 2087 .modes = &edt_et057090dhu_mode, 2088 .num_modes = 1, 2089 .bpc = 6, 2090 .size = { 2091 .width = 115, 2092 .height = 86, 2093 }, 2094 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2095 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2096 .connector_type = DRM_MODE_CONNECTOR_DPI, 2097 }; 2098 2099 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2100 .clock = 33260, 2101 .hdisplay = 800, 2102 .hsync_start = 800 + 40, 2103 .hsync_end = 800 + 40 + 128, 2104 .htotal = 800 + 40 + 128 + 88, 2105 .vdisplay = 480, 2106 .vsync_start = 480 + 10, 2107 .vsync_end = 480 + 10 + 2, 2108 .vtotal = 480 + 10 + 2 + 33, 2109 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2110 }; 2111 2112 static const struct panel_desc edt_etm0700g0dh6 = { 2113 .modes = &edt_etm0700g0dh6_mode, 2114 .num_modes = 1, 2115 .bpc = 6, 2116 .size = { 2117 .width = 152, 2118 .height = 91, 2119 }, 2120 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2121 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2122 .connector_type = DRM_MODE_CONNECTOR_DPI, 2123 }; 2124 2125 static const struct panel_desc edt_etm0700g0bdh6 = { 2126 .modes = &edt_etm0700g0dh6_mode, 2127 .num_modes = 1, 2128 .bpc = 6, 2129 .size = { 2130 .width = 152, 2131 .height = 91, 2132 }, 2133 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2134 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2135 .connector_type = DRM_MODE_CONNECTOR_DPI, 2136 }; 2137 2138 static const struct display_timing edt_etml0700y5dha_timing = { 2139 .pixelclock = { 40800000, 51200000, 67200000 }, 2140 .hactive = { 1024, 1024, 1024 }, 2141 .hfront_porch = { 30, 106, 125 }, 2142 .hback_porch = { 30, 106, 125 }, 2143 .hsync_len = { 30, 108, 126 }, 2144 .vactive = { 600, 600, 600 }, 2145 .vfront_porch = { 3, 12, 67}, 2146 .vback_porch = { 3, 12, 67 }, 2147 .vsync_len = { 4, 11, 66 }, 2148 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2149 DISPLAY_FLAGS_DE_HIGH, 2150 }; 2151 2152 static const struct panel_desc edt_etml0700y5dha = { 2153 .timings = &edt_etml0700y5dha_timing, 2154 .num_timings = 1, 2155 .bpc = 8, 2156 .size = { 2157 .width = 155, 2158 .height = 86, 2159 }, 2160 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2161 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2162 }; 2163 2164 static const struct display_timing edt_etml1010g3dra_timing = { 2165 .pixelclock = { 66300000, 72400000, 78900000 }, 2166 .hactive = { 1280, 1280, 1280 }, 2167 .hfront_porch = { 12, 72, 132 }, 2168 .hback_porch = { 86, 86, 86 }, 2169 .hsync_len = { 2, 2, 2 }, 2170 .vactive = { 800, 800, 800 }, 2171 .vfront_porch = { 1, 15, 49 }, 2172 .vback_porch = { 21, 21, 21 }, 2173 .vsync_len = { 2, 2, 2 }, 2174 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2175 DISPLAY_FLAGS_DE_HIGH, 2176 }; 2177 2178 static const struct panel_desc edt_etml1010g3dra = { 2179 .timings = &edt_etml1010g3dra_timing, 2180 .num_timings = 1, 2181 .bpc = 8, 2182 .size = { 2183 .width = 216, 2184 .height = 135, 2185 }, 2186 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2187 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2188 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2189 }; 2190 2191 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2192 .clock = 25175, 2193 .hdisplay = 640, 2194 .hsync_start = 640, 2195 .hsync_end = 640 + 16, 2196 .htotal = 640 + 16 + 30 + 114, 2197 .vdisplay = 480, 2198 .vsync_start = 480 + 10, 2199 .vsync_end = 480 + 10 + 3, 2200 .vtotal = 480 + 10 + 3 + 35, 2201 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2202 }; 2203 2204 static const struct panel_desc edt_etmv570g2dhu = { 2205 .modes = &edt_etmv570g2dhu_mode, 2206 .num_modes = 1, 2207 .bpc = 6, 2208 .size = { 2209 .width = 115, 2210 .height = 86, 2211 }, 2212 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2213 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2214 .connector_type = DRM_MODE_CONNECTOR_DPI, 2215 }; 2216 2217 static const struct display_timing eink_vb3300_kca_timing = { 2218 .pixelclock = { 40000000, 40000000, 40000000 }, 2219 .hactive = { 334, 334, 334 }, 2220 .hfront_porch = { 1, 1, 1 }, 2221 .hback_porch = { 1, 1, 1 }, 2222 .hsync_len = { 1, 1, 1 }, 2223 .vactive = { 1405, 1405, 1405 }, 2224 .vfront_porch = { 1, 1, 1 }, 2225 .vback_porch = { 1, 1, 1 }, 2226 .vsync_len = { 1, 1, 1 }, 2227 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2228 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2229 }; 2230 2231 static const struct panel_desc eink_vb3300_kca = { 2232 .timings = &eink_vb3300_kca_timing, 2233 .num_timings = 1, 2234 .bpc = 6, 2235 .size = { 2236 .width = 157, 2237 .height = 209, 2238 }, 2239 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2240 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2241 .connector_type = DRM_MODE_CONNECTOR_DPI, 2242 }; 2243 2244 static const struct display_timing evervision_vgg644804_timing = { 2245 .pixelclock = { 25175000, 25175000, 25175000 }, 2246 .hactive = { 640, 640, 640 }, 2247 .hfront_porch = { 16, 16, 16 }, 2248 .hback_porch = { 82, 114, 170 }, 2249 .hsync_len = { 5, 30, 30 }, 2250 .vactive = { 480, 480, 480 }, 2251 .vfront_porch = { 10, 10, 10 }, 2252 .vback_porch = { 30, 32, 34 }, 2253 .vsync_len = { 1, 3, 5 }, 2254 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2255 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2256 DISPLAY_FLAGS_SYNC_POSEDGE, 2257 }; 2258 2259 static const struct panel_desc evervision_vgg644804 = { 2260 .timings = &evervision_vgg644804_timing, 2261 .num_timings = 1, 2262 .bpc = 6, 2263 .size = { 2264 .width = 115, 2265 .height = 86, 2266 }, 2267 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2268 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2269 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2270 }; 2271 2272 static const struct display_timing evervision_vgg804821_timing = { 2273 .pixelclock = { 27600000, 33300000, 50000000 }, 2274 .hactive = { 800, 800, 800 }, 2275 .hfront_porch = { 40, 66, 70 }, 2276 .hback_porch = { 40, 67, 70 }, 2277 .hsync_len = { 40, 67, 70 }, 2278 .vactive = { 480, 480, 480 }, 2279 .vfront_porch = { 6, 10, 10 }, 2280 .vback_porch = { 7, 11, 11 }, 2281 .vsync_len = { 7, 11, 11 }, 2282 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2283 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2284 DISPLAY_FLAGS_SYNC_NEGEDGE, 2285 }; 2286 2287 static const struct panel_desc evervision_vgg804821 = { 2288 .timings = &evervision_vgg804821_timing, 2289 .num_timings = 1, 2290 .bpc = 8, 2291 .size = { 2292 .width = 108, 2293 .height = 64, 2294 }, 2295 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2296 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2297 }; 2298 2299 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2300 .clock = 32260, 2301 .hdisplay = 800, 2302 .hsync_start = 800 + 168, 2303 .hsync_end = 800 + 168 + 64, 2304 .htotal = 800 + 168 + 64 + 88, 2305 .vdisplay = 480, 2306 .vsync_start = 480 + 37, 2307 .vsync_end = 480 + 37 + 2, 2308 .vtotal = 480 + 37 + 2 + 8, 2309 }; 2310 2311 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2312 .modes = &foxlink_fl500wvr00_a0t_mode, 2313 .num_modes = 1, 2314 .bpc = 8, 2315 .size = { 2316 .width = 108, 2317 .height = 65, 2318 }, 2319 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2320 }; 2321 2322 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2323 { /* 60 Hz */ 2324 .clock = 6000, 2325 .hdisplay = 320, 2326 .hsync_start = 320 + 44, 2327 .hsync_end = 320 + 44 + 16, 2328 .htotal = 320 + 44 + 16 + 20, 2329 .vdisplay = 240, 2330 .vsync_start = 240 + 2, 2331 .vsync_end = 240 + 2 + 6, 2332 .vtotal = 240 + 2 + 6 + 2, 2333 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2334 }, 2335 { /* 50 Hz */ 2336 .clock = 5400, 2337 .hdisplay = 320, 2338 .hsync_start = 320 + 56, 2339 .hsync_end = 320 + 56 + 16, 2340 .htotal = 320 + 56 + 16 + 40, 2341 .vdisplay = 240, 2342 .vsync_start = 240 + 2, 2343 .vsync_end = 240 + 2 + 6, 2344 .vtotal = 240 + 2 + 6 + 2, 2345 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2346 }, 2347 }; 2348 2349 static const struct panel_desc frida_frd350h54004 = { 2350 .modes = frida_frd350h54004_modes, 2351 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2352 .bpc = 8, 2353 .size = { 2354 .width = 77, 2355 .height = 64, 2356 }, 2357 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2358 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2359 .connector_type = DRM_MODE_CONNECTOR_DPI, 2360 }; 2361 2362 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2363 .clock = 67185, 2364 .hdisplay = 800, 2365 .hsync_start = 800 + 20, 2366 .hsync_end = 800 + 20 + 24, 2367 .htotal = 800 + 20 + 24 + 20, 2368 .vdisplay = 1280, 2369 .vsync_start = 1280 + 4, 2370 .vsync_end = 1280 + 4 + 8, 2371 .vtotal = 1280 + 4 + 8 + 4, 2372 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2373 }; 2374 2375 static const struct panel_desc friendlyarm_hd702e = { 2376 .modes = &friendlyarm_hd702e_mode, 2377 .num_modes = 1, 2378 .size = { 2379 .width = 94, 2380 .height = 151, 2381 }, 2382 }; 2383 2384 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2385 .clock = 9000, 2386 .hdisplay = 480, 2387 .hsync_start = 480 + 5, 2388 .hsync_end = 480 + 5 + 1, 2389 .htotal = 480 + 5 + 1 + 40, 2390 .vdisplay = 272, 2391 .vsync_start = 272 + 8, 2392 .vsync_end = 272 + 8 + 1, 2393 .vtotal = 272 + 8 + 1 + 8, 2394 }; 2395 2396 static const struct panel_desc giantplus_gpg482739qs5 = { 2397 .modes = &giantplus_gpg482739qs5_mode, 2398 .num_modes = 1, 2399 .bpc = 8, 2400 .size = { 2401 .width = 95, 2402 .height = 54, 2403 }, 2404 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2405 }; 2406 2407 static const struct display_timing giantplus_gpm940b0_timing = { 2408 .pixelclock = { 13500000, 27000000, 27500000 }, 2409 .hactive = { 320, 320, 320 }, 2410 .hfront_porch = { 14, 686, 718 }, 2411 .hback_porch = { 50, 70, 255 }, 2412 .hsync_len = { 1, 1, 1 }, 2413 .vactive = { 240, 240, 240 }, 2414 .vfront_porch = { 1, 1, 179 }, 2415 .vback_porch = { 1, 21, 31 }, 2416 .vsync_len = { 1, 1, 6 }, 2417 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2418 }; 2419 2420 static const struct panel_desc giantplus_gpm940b0 = { 2421 .timings = &giantplus_gpm940b0_timing, 2422 .num_timings = 1, 2423 .bpc = 8, 2424 .size = { 2425 .width = 60, 2426 .height = 45, 2427 }, 2428 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2429 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2430 }; 2431 2432 static const struct display_timing hannstar_hsd070pww1_timing = { 2433 .pixelclock = { 64300000, 71100000, 82000000 }, 2434 .hactive = { 1280, 1280, 1280 }, 2435 .hfront_porch = { 1, 1, 10 }, 2436 .hback_porch = { 1, 1, 10 }, 2437 /* 2438 * According to the data sheet, the minimum horizontal blanking interval 2439 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2440 * minimum working horizontal blanking interval to be 60 clocks. 2441 */ 2442 .hsync_len = { 58, 158, 661 }, 2443 .vactive = { 800, 800, 800 }, 2444 .vfront_porch = { 1, 1, 10 }, 2445 .vback_porch = { 1, 1, 10 }, 2446 .vsync_len = { 1, 21, 203 }, 2447 .flags = DISPLAY_FLAGS_DE_HIGH, 2448 }; 2449 2450 static const struct panel_desc hannstar_hsd070pww1 = { 2451 .timings = &hannstar_hsd070pww1_timing, 2452 .num_timings = 1, 2453 .bpc = 6, 2454 .size = { 2455 .width = 151, 2456 .height = 94, 2457 }, 2458 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2459 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2460 }; 2461 2462 static const struct display_timing hannstar_hsd100pxn1_timing = { 2463 .pixelclock = { 55000000, 65000000, 75000000 }, 2464 .hactive = { 1024, 1024, 1024 }, 2465 .hfront_porch = { 40, 40, 40 }, 2466 .hback_porch = { 220, 220, 220 }, 2467 .hsync_len = { 20, 60, 100 }, 2468 .vactive = { 768, 768, 768 }, 2469 .vfront_porch = { 7, 7, 7 }, 2470 .vback_porch = { 21, 21, 21 }, 2471 .vsync_len = { 10, 10, 10 }, 2472 .flags = DISPLAY_FLAGS_DE_HIGH, 2473 }; 2474 2475 static const struct panel_desc hannstar_hsd100pxn1 = { 2476 .timings = &hannstar_hsd100pxn1_timing, 2477 .num_timings = 1, 2478 .bpc = 6, 2479 .size = { 2480 .width = 203, 2481 .height = 152, 2482 }, 2483 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2484 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2485 }; 2486 2487 static const struct display_timing hannstar_hsd101pww2_timing = { 2488 .pixelclock = { 64300000, 71100000, 82000000 }, 2489 .hactive = { 1280, 1280, 1280 }, 2490 .hfront_porch = { 1, 1, 10 }, 2491 .hback_porch = { 1, 1, 10 }, 2492 .hsync_len = { 58, 158, 661 }, 2493 .vactive = { 800, 800, 800 }, 2494 .vfront_porch = { 1, 1, 10 }, 2495 .vback_porch = { 1, 1, 10 }, 2496 .vsync_len = { 1, 21, 203 }, 2497 .flags = DISPLAY_FLAGS_DE_HIGH, 2498 }; 2499 2500 static const struct panel_desc hannstar_hsd101pww2 = { 2501 .timings = &hannstar_hsd101pww2_timing, 2502 .num_timings = 1, 2503 .bpc = 8, 2504 .size = { 2505 .width = 217, 2506 .height = 136, 2507 }, 2508 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2509 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2510 }; 2511 2512 static const struct display_timing hannstar_hsd156juw2_timing = { 2513 .pixelclock = { 66000000, 72800000, 80500000 }, 2514 .hactive = { 1920, 1920, 1920 }, 2515 .hfront_porch = { 20, 30, 30 }, 2516 .hback_porch = { 20, 30, 30 }, 2517 .hsync_len = { 50, 60, 90 }, 2518 .vactive = { 1080, 1080, 1080 }, 2519 .vfront_porch = { 1, 2, 4 }, 2520 .vback_porch = { 1, 2, 4 }, 2521 .vsync_len = { 3, 40, 80 }, 2522 .flags = DISPLAY_FLAGS_DE_HIGH, 2523 }; 2524 2525 static const struct panel_desc hannstar_hsd156juw2 = { 2526 .timings = &hannstar_hsd156juw2_timing, 2527 .num_timings = 1, 2528 .bpc = 8, 2529 .size = { 2530 .width = 344, 2531 .height = 194, 2532 }, 2533 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2534 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2535 }; 2536 2537 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2538 .clock = 33333, 2539 .hdisplay = 800, 2540 .hsync_start = 800 + 85, 2541 .hsync_end = 800 + 85 + 86, 2542 .htotal = 800 + 85 + 86 + 85, 2543 .vdisplay = 480, 2544 .vsync_start = 480 + 16, 2545 .vsync_end = 480 + 16 + 13, 2546 .vtotal = 480 + 16 + 13 + 16, 2547 }; 2548 2549 static const struct panel_desc hitachi_tx23d38vm0caa = { 2550 .modes = &hitachi_tx23d38vm0caa_mode, 2551 .num_modes = 1, 2552 .bpc = 6, 2553 .size = { 2554 .width = 195, 2555 .height = 117, 2556 }, 2557 .delay = { 2558 .enable = 160, 2559 .disable = 160, 2560 }, 2561 }; 2562 2563 static const struct drm_display_mode innolux_at043tn24_mode = { 2564 .clock = 9000, 2565 .hdisplay = 480, 2566 .hsync_start = 480 + 2, 2567 .hsync_end = 480 + 2 + 41, 2568 .htotal = 480 + 2 + 41 + 2, 2569 .vdisplay = 272, 2570 .vsync_start = 272 + 2, 2571 .vsync_end = 272 + 2 + 10, 2572 .vtotal = 272 + 2 + 10 + 2, 2573 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2574 }; 2575 2576 static const struct panel_desc innolux_at043tn24 = { 2577 .modes = &innolux_at043tn24_mode, 2578 .num_modes = 1, 2579 .bpc = 8, 2580 .size = { 2581 .width = 95, 2582 .height = 54, 2583 }, 2584 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2585 .connector_type = DRM_MODE_CONNECTOR_DPI, 2586 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2587 }; 2588 2589 static const struct drm_display_mode innolux_at070tn92_mode = { 2590 .clock = 33333, 2591 .hdisplay = 800, 2592 .hsync_start = 800 + 210, 2593 .hsync_end = 800 + 210 + 20, 2594 .htotal = 800 + 210 + 20 + 46, 2595 .vdisplay = 480, 2596 .vsync_start = 480 + 22, 2597 .vsync_end = 480 + 22 + 10, 2598 .vtotal = 480 + 22 + 23 + 10, 2599 }; 2600 2601 static const struct panel_desc innolux_at070tn92 = { 2602 .modes = &innolux_at070tn92_mode, 2603 .num_modes = 1, 2604 .size = { 2605 .width = 154, 2606 .height = 86, 2607 }, 2608 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2609 }; 2610 2611 static const struct display_timing innolux_g070ace_l01_timing = { 2612 .pixelclock = { 25200000, 35000000, 35700000 }, 2613 .hactive = { 800, 800, 800 }, 2614 .hfront_porch = { 30, 32, 87 }, 2615 .hback_porch = { 30, 32, 87 }, 2616 .hsync_len = { 1, 1, 1 }, 2617 .vactive = { 480, 480, 480 }, 2618 .vfront_porch = { 3, 3, 3 }, 2619 .vback_porch = { 13, 13, 13 }, 2620 .vsync_len = { 1, 1, 4 }, 2621 .flags = DISPLAY_FLAGS_DE_HIGH, 2622 }; 2623 2624 static const struct panel_desc innolux_g070ace_l01 = { 2625 .timings = &innolux_g070ace_l01_timing, 2626 .num_timings = 1, 2627 .bpc = 8, 2628 .size = { 2629 .width = 152, 2630 .height = 91, 2631 }, 2632 .delay = { 2633 .prepare = 10, 2634 .enable = 50, 2635 .disable = 50, 2636 .unprepare = 500, 2637 }, 2638 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2639 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2640 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2641 }; 2642 2643 static const struct display_timing innolux_g070y2_l01_timing = { 2644 .pixelclock = { 28000000, 29500000, 32000000 }, 2645 .hactive = { 800, 800, 800 }, 2646 .hfront_porch = { 61, 91, 141 }, 2647 .hback_porch = { 60, 90, 140 }, 2648 .hsync_len = { 12, 12, 12 }, 2649 .vactive = { 480, 480, 480 }, 2650 .vfront_porch = { 4, 9, 30 }, 2651 .vback_porch = { 4, 8, 28 }, 2652 .vsync_len = { 2, 2, 2 }, 2653 .flags = DISPLAY_FLAGS_DE_HIGH, 2654 }; 2655 2656 static const struct panel_desc innolux_g070y2_l01 = { 2657 .timings = &innolux_g070y2_l01_timing, 2658 .num_timings = 1, 2659 .bpc = 8, 2660 .size = { 2661 .width = 152, 2662 .height = 91, 2663 }, 2664 .delay = { 2665 .prepare = 10, 2666 .enable = 100, 2667 .disable = 100, 2668 .unprepare = 800, 2669 }, 2670 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2671 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2672 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2673 }; 2674 2675 static const struct display_timing innolux_g070ace_lh3_timing = { 2676 .pixelclock = { 25200000, 25400000, 35700000 }, 2677 .hactive = { 800, 800, 800 }, 2678 .hfront_porch = { 30, 32, 87 }, 2679 .hback_porch = { 29, 31, 86 }, 2680 .hsync_len = { 1, 1, 1 }, 2681 .vactive = { 480, 480, 480 }, 2682 .vfront_porch = { 4, 5, 65 }, 2683 .vback_porch = { 3, 4, 65 }, 2684 .vsync_len = { 1, 1, 1 }, 2685 .flags = DISPLAY_FLAGS_DE_HIGH, 2686 }; 2687 2688 static const struct panel_desc innolux_g070ace_lh3 = { 2689 .timings = &innolux_g070ace_lh3_timing, 2690 .num_timings = 1, 2691 .bpc = 8, 2692 .size = { 2693 .width = 152, 2694 .height = 91, 2695 }, 2696 .delay = { 2697 .prepare = 10, 2698 .enable = 450, 2699 .disable = 200, 2700 .unprepare = 510, 2701 }, 2702 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2703 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2704 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2705 }; 2706 2707 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2708 .clock = 33333, 2709 .hdisplay = 800, 2710 .hsync_start = 800 + 210, 2711 .hsync_end = 800 + 210 + 20, 2712 .htotal = 800 + 210 + 20 + 46, 2713 .vdisplay = 480, 2714 .vsync_start = 480 + 22, 2715 .vsync_end = 480 + 22 + 10, 2716 .vtotal = 480 + 22 + 23 + 10, 2717 }; 2718 2719 static const struct panel_desc innolux_g070y2_t02 = { 2720 .modes = &innolux_g070y2_t02_mode, 2721 .num_modes = 1, 2722 .bpc = 8, 2723 .size = { 2724 .width = 152, 2725 .height = 92, 2726 }, 2727 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2728 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2729 .connector_type = DRM_MODE_CONNECTOR_DPI, 2730 }; 2731 2732 static const struct display_timing innolux_g101ice_l01_timing = { 2733 .pixelclock = { 60400000, 71100000, 74700000 }, 2734 .hactive = { 1280, 1280, 1280 }, 2735 .hfront_porch = { 30, 60, 70 }, 2736 .hback_porch = { 30, 60, 70 }, 2737 .hsync_len = { 22, 40, 60 }, 2738 .vactive = { 800, 800, 800 }, 2739 .vfront_porch = { 3, 8, 14 }, 2740 .vback_porch = { 3, 8, 14 }, 2741 .vsync_len = { 4, 7, 12 }, 2742 .flags = DISPLAY_FLAGS_DE_HIGH, 2743 }; 2744 2745 static const struct panel_desc innolux_g101ice_l01 = { 2746 .timings = &innolux_g101ice_l01_timing, 2747 .num_timings = 1, 2748 .bpc = 8, 2749 .size = { 2750 .width = 217, 2751 .height = 135, 2752 }, 2753 .delay = { 2754 .enable = 200, 2755 .disable = 200, 2756 }, 2757 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2758 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2759 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2760 }; 2761 2762 static const struct display_timing innolux_g121i1_l01_timing = { 2763 .pixelclock = { 67450000, 71000000, 74550000 }, 2764 .hactive = { 1280, 1280, 1280 }, 2765 .hfront_porch = { 40, 80, 160 }, 2766 .hback_porch = { 39, 79, 159 }, 2767 .hsync_len = { 1, 1, 1 }, 2768 .vactive = { 800, 800, 800 }, 2769 .vfront_porch = { 5, 11, 100 }, 2770 .vback_porch = { 4, 11, 99 }, 2771 .vsync_len = { 1, 1, 1 }, 2772 }; 2773 2774 static const struct panel_desc innolux_g121i1_l01 = { 2775 .timings = &innolux_g121i1_l01_timing, 2776 .num_timings = 1, 2777 .bpc = 6, 2778 .size = { 2779 .width = 261, 2780 .height = 163, 2781 }, 2782 .delay = { 2783 .enable = 200, 2784 .disable = 20, 2785 }, 2786 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2787 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2788 }; 2789 2790 static const struct display_timing innolux_g121x1_l03_timings = { 2791 .pixelclock = { 57500000, 64900000, 74400000 }, 2792 .hactive = { 1024, 1024, 1024 }, 2793 .hfront_porch = { 90, 140, 190 }, 2794 .hback_porch = { 90, 140, 190 }, 2795 .hsync_len = { 36, 40, 60 }, 2796 .vactive = { 768, 768, 768 }, 2797 .vfront_porch = { 2, 15, 30 }, 2798 .vback_porch = { 2, 15, 30 }, 2799 .vsync_len = { 2, 8, 20 }, 2800 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2801 }; 2802 2803 static const struct panel_desc innolux_g121x1_l03 = { 2804 .timings = &innolux_g121x1_l03_timings, 2805 .num_timings = 1, 2806 .bpc = 6, 2807 .size = { 2808 .width = 246, 2809 .height = 185, 2810 }, 2811 .delay = { 2812 .enable = 200, 2813 .unprepare = 200, 2814 .disable = 400, 2815 }, 2816 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2817 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2818 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2819 }; 2820 2821 static const struct panel_desc innolux_g121xce_l01 = { 2822 .timings = &innolux_g121x1_l03_timings, 2823 .num_timings = 1, 2824 .bpc = 8, 2825 .size = { 2826 .width = 246, 2827 .height = 185, 2828 }, 2829 .delay = { 2830 .enable = 200, 2831 .unprepare = 200, 2832 .disable = 400, 2833 }, 2834 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2835 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2836 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2837 }; 2838 2839 static const struct display_timing innolux_g150xge_l05_timing = { 2840 .pixelclock = { 53350000, 65000000, 80000000 }, 2841 .hactive = { 1024, 1024, 1024 }, 2842 .hfront_porch = { 58, 160, 288 }, 2843 .hback_porch = { 58, 160, 288 }, 2844 .hsync_len = { 1, 1, 1 }, 2845 .vactive = { 768, 768, 768 }, 2846 .vfront_porch = { 6, 19, 216 }, 2847 .vback_porch = { 6, 19, 216 }, 2848 .vsync_len = { 1, 1, 1 }, 2849 .flags = DISPLAY_FLAGS_DE_HIGH, 2850 }; 2851 2852 static const struct panel_desc innolux_g150xge_l05 = { 2853 .timings = &innolux_g150xge_l05_timing, 2854 .num_timings = 1, 2855 .bpc = 8, 2856 .size = { 2857 .width = 304, 2858 .height = 228, 2859 }, 2860 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2861 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2862 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2863 }; 2864 2865 static const struct display_timing innolux_g156hce_l01_timings = { 2866 .pixelclock = { 120000000, 141860000, 150000000 }, 2867 .hactive = { 1920, 1920, 1920 }, 2868 .hfront_porch = { 80, 90, 100 }, 2869 .hback_porch = { 80, 90, 100 }, 2870 .hsync_len = { 20, 30, 30 }, 2871 .vactive = { 1080, 1080, 1080 }, 2872 .vfront_porch = { 3, 10, 20 }, 2873 .vback_porch = { 3, 10, 20 }, 2874 .vsync_len = { 4, 10, 10 }, 2875 }; 2876 2877 static const struct panel_desc innolux_g156hce_l01 = { 2878 .timings = &innolux_g156hce_l01_timings, 2879 .num_timings = 1, 2880 .bpc = 8, 2881 .size = { 2882 .width = 344, 2883 .height = 194, 2884 }, 2885 .delay = { 2886 .prepare = 1, /* T1+T2 */ 2887 .enable = 450, /* T5 */ 2888 .disable = 200, /* T6 */ 2889 .unprepare = 10, /* T3+T7 */ 2890 }, 2891 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2892 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2893 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2894 }; 2895 2896 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2897 .clock = 69300, 2898 .hdisplay = 1366, 2899 .hsync_start = 1366 + 16, 2900 .hsync_end = 1366 + 16 + 34, 2901 .htotal = 1366 + 16 + 34 + 50, 2902 .vdisplay = 768, 2903 .vsync_start = 768 + 2, 2904 .vsync_end = 768 + 2 + 6, 2905 .vtotal = 768 + 2 + 6 + 12, 2906 }; 2907 2908 static const struct panel_desc innolux_n156bge_l21 = { 2909 .modes = &innolux_n156bge_l21_mode, 2910 .num_modes = 1, 2911 .bpc = 6, 2912 .size = { 2913 .width = 344, 2914 .height = 193, 2915 }, 2916 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2917 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2918 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2919 }; 2920 2921 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2922 .clock = 51501, 2923 .hdisplay = 1024, 2924 .hsync_start = 1024 + 128, 2925 .hsync_end = 1024 + 128 + 64, 2926 .htotal = 1024 + 128 + 64 + 128, 2927 .vdisplay = 600, 2928 .vsync_start = 600 + 16, 2929 .vsync_end = 600 + 16 + 4, 2930 .vtotal = 600 + 16 + 4 + 16, 2931 }; 2932 2933 static const struct panel_desc innolux_zj070na_01p = { 2934 .modes = &innolux_zj070na_01p_mode, 2935 .num_modes = 1, 2936 .bpc = 6, 2937 .size = { 2938 .width = 154, 2939 .height = 90, 2940 }, 2941 }; 2942 2943 static const struct display_timing jutouch_jt101tm023_timing = { 2944 .pixelclock = { 66300000, 72400000, 78900000 }, 2945 .hactive = { 1280, 1280, 1280 }, 2946 .hfront_porch = { 12, 72, 132 }, 2947 .hback_porch = { 88, 88, 88 }, 2948 .hsync_len = { 10, 10, 48 }, 2949 .vactive = { 800, 800, 800 }, 2950 .vfront_porch = { 1, 15, 49 }, 2951 .vback_porch = { 23, 23, 23 }, 2952 .vsync_len = { 5, 6, 13 }, 2953 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2954 DISPLAY_FLAGS_DE_HIGH, 2955 }; 2956 2957 static const struct panel_desc jutouch_jt101tm023 = { 2958 .timings = &jutouch_jt101tm023_timing, 2959 .num_timings = 1, 2960 .bpc = 8, 2961 .size = { 2962 .width = 217, 2963 .height = 136, 2964 }, 2965 .delay = { 2966 .enable = 50, 2967 .disable = 50, 2968 }, 2969 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2970 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2971 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2972 }; 2973 2974 2975 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2976 .pixelclock = { 5580000, 5850000, 6200000 }, 2977 .hactive = { 320, 320, 320 }, 2978 .hfront_porch = { 30, 30, 30 }, 2979 .hback_porch = { 30, 30, 30 }, 2980 .hsync_len = { 1, 5, 17 }, 2981 .vactive = { 240, 240, 240 }, 2982 .vfront_porch = { 6, 6, 6 }, 2983 .vback_porch = { 5, 5, 5 }, 2984 .vsync_len = { 1, 2, 11 }, 2985 .flags = DISPLAY_FLAGS_DE_HIGH, 2986 }; 2987 2988 static const struct panel_desc koe_tx14d24vm1bpa = { 2989 .timings = &koe_tx14d24vm1bpa_timing, 2990 .num_timings = 1, 2991 .bpc = 6, 2992 .size = { 2993 .width = 115, 2994 .height = 86, 2995 }, 2996 }; 2997 2998 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2999 .pixelclock = { 151820000, 156720000, 159780000 }, 3000 .hactive = { 1920, 1920, 1920 }, 3001 .hfront_porch = { 105, 130, 142 }, 3002 .hback_porch = { 45, 70, 82 }, 3003 .hsync_len = { 30, 30, 30 }, 3004 .vactive = { 1200, 1200, 1200}, 3005 .vfront_porch = { 3, 5, 10 }, 3006 .vback_porch = { 2, 5, 10 }, 3007 .vsync_len = { 5, 5, 5 }, 3008 .flags = DISPLAY_FLAGS_DE_HIGH, 3009 }; 3010 3011 static const struct panel_desc koe_tx26d202vm0bwa = { 3012 .timings = &koe_tx26d202vm0bwa_timing, 3013 .num_timings = 1, 3014 .bpc = 8, 3015 .size = { 3016 .width = 217, 3017 .height = 136, 3018 }, 3019 .delay = { 3020 .prepare = 1000, 3021 .enable = 1000, 3022 .unprepare = 1000, 3023 .disable = 1000, 3024 }, 3025 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3026 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3027 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3028 }; 3029 3030 static const struct display_timing koe_tx31d200vm0baa_timing = { 3031 .pixelclock = { 39600000, 43200000, 48000000 }, 3032 .hactive = { 1280, 1280, 1280 }, 3033 .hfront_porch = { 16, 36, 56 }, 3034 .hback_porch = { 16, 36, 56 }, 3035 .hsync_len = { 8, 8, 8 }, 3036 .vactive = { 480, 480, 480 }, 3037 .vfront_porch = { 6, 21, 33 }, 3038 .vback_porch = { 6, 21, 33 }, 3039 .vsync_len = { 8, 8, 8 }, 3040 .flags = DISPLAY_FLAGS_DE_HIGH, 3041 }; 3042 3043 static const struct panel_desc koe_tx31d200vm0baa = { 3044 .timings = &koe_tx31d200vm0baa_timing, 3045 .num_timings = 1, 3046 .bpc = 6, 3047 .size = { 3048 .width = 292, 3049 .height = 109, 3050 }, 3051 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3052 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3053 }; 3054 3055 static const struct display_timing kyo_tcg121xglp_timing = { 3056 .pixelclock = { 52000000, 65000000, 71000000 }, 3057 .hactive = { 1024, 1024, 1024 }, 3058 .hfront_porch = { 2, 2, 2 }, 3059 .hback_porch = { 2, 2, 2 }, 3060 .hsync_len = { 86, 124, 244 }, 3061 .vactive = { 768, 768, 768 }, 3062 .vfront_porch = { 2, 2, 2 }, 3063 .vback_porch = { 2, 2, 2 }, 3064 .vsync_len = { 6, 34, 73 }, 3065 .flags = DISPLAY_FLAGS_DE_HIGH, 3066 }; 3067 3068 static const struct panel_desc kyo_tcg121xglp = { 3069 .timings = &kyo_tcg121xglp_timing, 3070 .num_timings = 1, 3071 .bpc = 8, 3072 .size = { 3073 .width = 246, 3074 .height = 184, 3075 }, 3076 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3077 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3078 }; 3079 3080 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 3081 .clock = 7000, 3082 .hdisplay = 320, 3083 .hsync_start = 320 + 20, 3084 .hsync_end = 320 + 20 + 30, 3085 .htotal = 320 + 20 + 30 + 38, 3086 .vdisplay = 240, 3087 .vsync_start = 240 + 4, 3088 .vsync_end = 240 + 4 + 3, 3089 .vtotal = 240 + 4 + 3 + 15, 3090 }; 3091 3092 static const struct panel_desc lemaker_bl035_rgb_002 = { 3093 .modes = &lemaker_bl035_rgb_002_mode, 3094 .num_modes = 1, 3095 .size = { 3096 .width = 70, 3097 .height = 52, 3098 }, 3099 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3100 .bus_flags = DRM_BUS_FLAG_DE_LOW, 3101 }; 3102 3103 static const struct display_timing lg_lb070wv8_timing = { 3104 .pixelclock = { 31950000, 33260000, 34600000 }, 3105 .hactive = { 800, 800, 800 }, 3106 .hfront_porch = { 88, 88, 88 }, 3107 .hback_porch = { 88, 88, 88 }, 3108 .hsync_len = { 80, 80, 80 }, 3109 .vactive = { 480, 480, 480 }, 3110 .vfront_porch = { 10, 10, 10 }, 3111 .vback_porch = { 10, 10, 10 }, 3112 .vsync_len = { 25, 25, 25 }, 3113 }; 3114 3115 static const struct panel_desc lg_lb070wv8 = { 3116 .timings = &lg_lb070wv8_timing, 3117 .num_timings = 1, 3118 .bpc = 8, 3119 .size = { 3120 .width = 151, 3121 .height = 91, 3122 }, 3123 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3124 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3125 }; 3126 3127 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 3128 .clock = 155127, 3129 .hdisplay = 1920, 3130 .hsync_start = 1920 + 128, 3131 .hsync_end = 1920 + 128 + 20, 3132 .htotal = 1920 + 128 + 20 + 12, 3133 .vdisplay = 1200, 3134 .vsync_start = 1200 + 19, 3135 .vsync_end = 1200 + 19 + 4, 3136 .vtotal = 1200 + 19 + 4 + 20, 3137 }; 3138 3139 static const struct panel_desc lincolntech_lcd185_101ct = { 3140 .modes = &lincolntech_lcd185_101ct_mode, 3141 .bpc = 8, 3142 .num_modes = 1, 3143 .size = { 3144 .width = 217, 3145 .height = 136, 3146 }, 3147 .delay = { 3148 .prepare = 50, 3149 .disable = 50, 3150 }, 3151 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3152 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3153 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3154 }; 3155 3156 static const struct display_timing logictechno_lt161010_2nh_timing = { 3157 .pixelclock = { 26400000, 33300000, 46800000 }, 3158 .hactive = { 800, 800, 800 }, 3159 .hfront_porch = { 16, 210, 354 }, 3160 .hback_porch = { 46, 46, 46 }, 3161 .hsync_len = { 1, 20, 40 }, 3162 .vactive = { 480, 480, 480 }, 3163 .vfront_porch = { 7, 22, 147 }, 3164 .vback_porch = { 23, 23, 23 }, 3165 .vsync_len = { 1, 10, 20 }, 3166 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3167 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3168 DISPLAY_FLAGS_SYNC_POSEDGE, 3169 }; 3170 3171 static const struct panel_desc logictechno_lt161010_2nh = { 3172 .timings = &logictechno_lt161010_2nh_timing, 3173 .num_timings = 1, 3174 .bpc = 6, 3175 .size = { 3176 .width = 154, 3177 .height = 86, 3178 }, 3179 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3180 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3181 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3182 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3183 .connector_type = DRM_MODE_CONNECTOR_DPI, 3184 }; 3185 3186 static const struct display_timing logictechno_lt170410_2whc_timing = { 3187 .pixelclock = { 68900000, 71100000, 73400000 }, 3188 .hactive = { 1280, 1280, 1280 }, 3189 .hfront_porch = { 23, 60, 71 }, 3190 .hback_porch = { 23, 60, 71 }, 3191 .hsync_len = { 15, 40, 47 }, 3192 .vactive = { 800, 800, 800 }, 3193 .vfront_porch = { 5, 7, 10 }, 3194 .vback_porch = { 5, 7, 10 }, 3195 .vsync_len = { 6, 9, 12 }, 3196 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3197 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3198 DISPLAY_FLAGS_SYNC_POSEDGE, 3199 }; 3200 3201 static const struct panel_desc logictechno_lt170410_2whc = { 3202 .timings = &logictechno_lt170410_2whc_timing, 3203 .num_timings = 1, 3204 .bpc = 8, 3205 .size = { 3206 .width = 217, 3207 .height = 136, 3208 }, 3209 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3210 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3211 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3212 }; 3213 3214 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3215 .clock = 33000, 3216 .hdisplay = 800, 3217 .hsync_start = 800 + 112, 3218 .hsync_end = 800 + 112 + 3, 3219 .htotal = 800 + 112 + 3 + 85, 3220 .vdisplay = 480, 3221 .vsync_start = 480 + 38, 3222 .vsync_end = 480 + 38 + 3, 3223 .vtotal = 480 + 38 + 3 + 29, 3224 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3225 }; 3226 3227 static const struct panel_desc logictechno_lttd800480070_l2rt = { 3228 .modes = &logictechno_lttd800480070_l2rt_mode, 3229 .num_modes = 1, 3230 .bpc = 8, 3231 .size = { 3232 .width = 154, 3233 .height = 86, 3234 }, 3235 .delay = { 3236 .prepare = 45, 3237 .enable = 100, 3238 .disable = 100, 3239 .unprepare = 45 3240 }, 3241 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3242 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3243 .connector_type = DRM_MODE_CONNECTOR_DPI, 3244 }; 3245 3246 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3247 .clock = 33000, 3248 .hdisplay = 800, 3249 .hsync_start = 800 + 154, 3250 .hsync_end = 800 + 154 + 3, 3251 .htotal = 800 + 154 + 3 + 43, 3252 .vdisplay = 480, 3253 .vsync_start = 480 + 47, 3254 .vsync_end = 480 + 47 + 3, 3255 .vtotal = 480 + 47 + 3 + 20, 3256 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3257 }; 3258 3259 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3260 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3261 .num_modes = 1, 3262 .bpc = 8, 3263 .size = { 3264 .width = 154, 3265 .height = 86, 3266 }, 3267 .delay = { 3268 .prepare = 45, 3269 .enable = 100, 3270 .disable = 100, 3271 .unprepare = 45 3272 }, 3273 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3274 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3275 .connector_type = DRM_MODE_CONNECTOR_DPI, 3276 }; 3277 3278 static const struct drm_display_mode logicpd_type_28_mode = { 3279 .clock = 9107, 3280 .hdisplay = 480, 3281 .hsync_start = 480 + 3, 3282 .hsync_end = 480 + 3 + 42, 3283 .htotal = 480 + 3 + 42 + 2, 3284 3285 .vdisplay = 272, 3286 .vsync_start = 272 + 2, 3287 .vsync_end = 272 + 2 + 11, 3288 .vtotal = 272 + 2 + 11 + 3, 3289 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3290 }; 3291 3292 static const struct panel_desc logicpd_type_28 = { 3293 .modes = &logicpd_type_28_mode, 3294 .num_modes = 1, 3295 .bpc = 8, 3296 .size = { 3297 .width = 105, 3298 .height = 67, 3299 }, 3300 .delay = { 3301 .prepare = 200, 3302 .enable = 200, 3303 .unprepare = 200, 3304 .disable = 200, 3305 }, 3306 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3307 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3308 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3309 .connector_type = DRM_MODE_CONNECTOR_DPI, 3310 }; 3311 3312 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3313 .clock = 150275, 3314 .hdisplay = 1920, 3315 .hsync_start = 1920 + 32, 3316 .hsync_end = 1920 + 32 + 52, 3317 .htotal = 1920 + 32 + 52 + 24, 3318 .vdisplay = 1200, 3319 .vsync_start = 1200 + 24, 3320 .vsync_end = 1200 + 24 + 8, 3321 .vtotal = 1200 + 24 + 8 + 3, 3322 }; 3323 3324 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3325 .modes = µtips_mf_101hiebcaf0_c_mode, 3326 .bpc = 8, 3327 .num_modes = 1, 3328 .size = { 3329 .width = 217, 3330 .height = 136, 3331 }, 3332 .delay = { 3333 .prepare = 50, 3334 .disable = 50, 3335 }, 3336 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3337 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3338 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3339 }; 3340 3341 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3342 .clock = 93301, 3343 .hdisplay = 1920, 3344 .hsync_start = 1920 + 72, 3345 .hsync_end = 1920 + 72 + 72, 3346 .htotal = 1920 + 72 + 72 + 72, 3347 .vdisplay = 720, 3348 .vsync_start = 720 + 3, 3349 .vsync_end = 720 + 3 + 3, 3350 .vtotal = 720 + 3 + 3 + 2, 3351 }; 3352 3353 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3354 .modes = µtips_mf_103hieb0ga0_mode, 3355 .bpc = 8, 3356 .num_modes = 1, 3357 .size = { 3358 .width = 244, 3359 .height = 92, 3360 }, 3361 .delay = { 3362 .prepare = 50, 3363 .disable = 50, 3364 }, 3365 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3366 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3367 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3368 }; 3369 3370 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3371 .clock = 30400, 3372 .hdisplay = 800, 3373 .hsync_start = 800 + 0, 3374 .hsync_end = 800 + 1, 3375 .htotal = 800 + 0 + 1 + 160, 3376 .vdisplay = 480, 3377 .vsync_start = 480 + 0, 3378 .vsync_end = 480 + 48 + 1, 3379 .vtotal = 480 + 48 + 1 + 0, 3380 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3381 }; 3382 3383 static const struct panel_desc mitsubishi_aa070mc01 = { 3384 .modes = &mitsubishi_aa070mc01_mode, 3385 .num_modes = 1, 3386 .bpc = 8, 3387 .size = { 3388 .width = 152, 3389 .height = 91, 3390 }, 3391 3392 .delay = { 3393 .enable = 200, 3394 .unprepare = 200, 3395 .disable = 400, 3396 }, 3397 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3398 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3399 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3400 }; 3401 3402 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3403 .clock = 56234, 3404 .hdisplay = 1024, 3405 .hsync_start = 1024 + 24, 3406 .hsync_end = 1024 + 24 + 63, 3407 .htotal = 1024 + 24 + 63 + 1, 3408 .vdisplay = 768, 3409 .vsync_start = 768 + 3, 3410 .vsync_end = 768 + 3 + 6, 3411 .vtotal = 768 + 3 + 6 + 1, 3412 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3413 }; 3414 3415 static const struct panel_desc mitsubishi_aa084xe01 = { 3416 .modes = &mitsubishi_aa084xe01_mode, 3417 .num_modes = 1, 3418 .bpc = 8, 3419 .size = { 3420 .width = 1024, 3421 .height = 768, 3422 }, 3423 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3424 .connector_type = DRM_MODE_CONNECTOR_DPI, 3425 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3426 }; 3427 3428 static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3429 .pixelclock = { 26400000, 33000000, 46800000 }, 3430 .hactive = { 800, 800, 800 }, 3431 .hfront_porch = { 16, 204, 354 }, 3432 .hback_porch = { 46, 46, 46 }, 3433 .hsync_len = { 1, 6, 40 }, 3434 .vactive = { 480, 480, 480 }, 3435 .vfront_porch = { 7, 22, 147 }, 3436 .vback_porch = { 23, 23, 23 }, 3437 .vsync_len = { 1, 3, 20 }, 3438 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3439 DISPLAY_FLAGS_DE_HIGH, 3440 }; 3441 3442 static const struct panel_desc multi_inno_mi0700a2t_30 = { 3443 .timings = &multi_inno_mi0700a2t_30_timing, 3444 .num_timings = 1, 3445 .bpc = 6, 3446 .size = { 3447 .width = 153, 3448 .height = 92, 3449 }, 3450 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3451 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3452 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3453 }; 3454 3455 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3456 .pixelclock = { 29000000, 33000000, 38000000 }, 3457 .hactive = { 800, 800, 800 }, 3458 .hfront_porch = { 180, 210, 240 }, 3459 .hback_porch = { 16, 16, 16 }, 3460 .hsync_len = { 30, 30, 30 }, 3461 .vactive = { 480, 480, 480 }, 3462 .vfront_porch = { 12, 22, 32 }, 3463 .vback_porch = { 10, 10, 10 }, 3464 .vsync_len = { 13, 13, 13 }, 3465 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3466 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3467 DISPLAY_FLAGS_SYNC_POSEDGE, 3468 }; 3469 3470 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3471 .timings = &multi_inno_mi0700s4t_6_timing, 3472 .num_timings = 1, 3473 .bpc = 8, 3474 .size = { 3475 .width = 154, 3476 .height = 86, 3477 }, 3478 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3479 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3480 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3481 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3482 .connector_type = DRM_MODE_CONNECTOR_DPI, 3483 }; 3484 3485 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3486 .pixelclock = { 32000000, 40000000, 50000000 }, 3487 .hactive = { 800, 800, 800 }, 3488 .hfront_porch = { 16, 210, 354 }, 3489 .hback_porch = { 6, 26, 45 }, 3490 .hsync_len = { 1, 20, 40 }, 3491 .vactive = { 600, 600, 600 }, 3492 .vfront_porch = { 1, 12, 77 }, 3493 .vback_porch = { 3, 13, 22 }, 3494 .vsync_len = { 1, 10, 20 }, 3495 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3496 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3497 DISPLAY_FLAGS_SYNC_POSEDGE, 3498 }; 3499 3500 static const struct panel_desc multi_inno_mi0800ft_9 = { 3501 .timings = &multi_inno_mi0800ft_9_timing, 3502 .num_timings = 1, 3503 .bpc = 8, 3504 .size = { 3505 .width = 162, 3506 .height = 122, 3507 }, 3508 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3509 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3510 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3511 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3512 .connector_type = DRM_MODE_CONNECTOR_DPI, 3513 }; 3514 3515 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3516 .pixelclock = { 68900000, 70000000, 73400000 }, 3517 .hactive = { 1280, 1280, 1280 }, 3518 .hfront_porch = { 30, 60, 71 }, 3519 .hback_porch = { 30, 60, 71 }, 3520 .hsync_len = { 10, 10, 48 }, 3521 .vactive = { 800, 800, 800 }, 3522 .vfront_porch = { 5, 10, 10 }, 3523 .vback_porch = { 5, 10, 10 }, 3524 .vsync_len = { 5, 6, 13 }, 3525 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3526 DISPLAY_FLAGS_DE_HIGH, 3527 }; 3528 3529 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3530 .timings = &multi_inno_mi1010ait_1cp_timing, 3531 .num_timings = 1, 3532 .bpc = 8, 3533 .size = { 3534 .width = 217, 3535 .height = 136, 3536 }, 3537 .delay = { 3538 .enable = 50, 3539 .disable = 50, 3540 }, 3541 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3542 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3543 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3544 }; 3545 3546 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3547 .pixelclock = { 40800000, 51200000, 67200000 }, 3548 .hactive = { 1024, 1024, 1024 }, 3549 .hfront_porch = { 30, 110, 130 }, 3550 .hback_porch = { 30, 110, 130 }, 3551 .hsync_len = { 30, 100, 116 }, 3552 .vactive = { 600, 600, 600 }, 3553 .vfront_porch = { 4, 13, 80 }, 3554 .vback_porch = { 4, 13, 80 }, 3555 .vsync_len = { 2, 9, 40 }, 3556 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3557 DISPLAY_FLAGS_DE_HIGH, 3558 }; 3559 3560 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3561 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3562 .num_timings = 1, 3563 .bpc = 6, 3564 .size = { 3565 .width = 260, 3566 .height = 162, 3567 }, 3568 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3569 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3570 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3571 }; 3572 3573 static const struct display_timing nec_nl12880bc20_05_timing = { 3574 .pixelclock = { 67000000, 71000000, 75000000 }, 3575 .hactive = { 1280, 1280, 1280 }, 3576 .hfront_porch = { 2, 30, 30 }, 3577 .hback_porch = { 6, 100, 100 }, 3578 .hsync_len = { 2, 30, 30 }, 3579 .vactive = { 800, 800, 800 }, 3580 .vfront_porch = { 5, 5, 5 }, 3581 .vback_porch = { 11, 11, 11 }, 3582 .vsync_len = { 7, 7, 7 }, 3583 }; 3584 3585 static const struct panel_desc nec_nl12880bc20_05 = { 3586 .timings = &nec_nl12880bc20_05_timing, 3587 .num_timings = 1, 3588 .bpc = 8, 3589 .size = { 3590 .width = 261, 3591 .height = 163, 3592 }, 3593 .delay = { 3594 .enable = 50, 3595 .disable = 50, 3596 }, 3597 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3598 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3599 }; 3600 3601 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3602 .clock = 10870, 3603 .hdisplay = 480, 3604 .hsync_start = 480 + 2, 3605 .hsync_end = 480 + 2 + 41, 3606 .htotal = 480 + 2 + 41 + 2, 3607 .vdisplay = 272, 3608 .vsync_start = 272 + 2, 3609 .vsync_end = 272 + 2 + 4, 3610 .vtotal = 272 + 2 + 4 + 2, 3611 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3612 }; 3613 3614 static const struct panel_desc nec_nl4827hc19_05b = { 3615 .modes = &nec_nl4827hc19_05b_mode, 3616 .num_modes = 1, 3617 .bpc = 8, 3618 .size = { 3619 .width = 95, 3620 .height = 54, 3621 }, 3622 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3623 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3624 }; 3625 3626 static const struct drm_display_mode netron_dy_e231732_mode = { 3627 .clock = 66000, 3628 .hdisplay = 1024, 3629 .hsync_start = 1024 + 160, 3630 .hsync_end = 1024 + 160 + 70, 3631 .htotal = 1024 + 160 + 70 + 90, 3632 .vdisplay = 600, 3633 .vsync_start = 600 + 127, 3634 .vsync_end = 600 + 127 + 20, 3635 .vtotal = 600 + 127 + 20 + 3, 3636 }; 3637 3638 static const struct panel_desc netron_dy_e231732 = { 3639 .modes = &netron_dy_e231732_mode, 3640 .num_modes = 1, 3641 .size = { 3642 .width = 154, 3643 .height = 87, 3644 }, 3645 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3646 }; 3647 3648 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3649 .clock = 9000, 3650 .hdisplay = 480, 3651 .hsync_start = 480 + 2, 3652 .hsync_end = 480 + 2 + 41, 3653 .htotal = 480 + 2 + 41 + 2, 3654 .vdisplay = 272, 3655 .vsync_start = 272 + 2, 3656 .vsync_end = 272 + 2 + 10, 3657 .vtotal = 272 + 2 + 10 + 2, 3658 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3659 }; 3660 3661 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3662 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3663 .num_modes = 1, 3664 .bpc = 8, 3665 .size = { 3666 .width = 95, 3667 .height = 54, 3668 }, 3669 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3670 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3671 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3672 .connector_type = DRM_MODE_CONNECTOR_DPI, 3673 }; 3674 3675 static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { 3676 .clock = 75400, 3677 .hdisplay = 1366, 3678 .hsync_start = 1366 + 14, 3679 .hsync_end = 1366 + 14 + 56, 3680 .htotal = 1366 + 14 + 56 + 64, 3681 .vdisplay = 768, 3682 .vsync_start = 768 + 1, 3683 .vsync_end = 768 + 1 + 3, 3684 .vtotal = 768 + 1 + 3 + 22, 3685 }; 3686 3687 static const struct panel_desc nlt_nl13676bc25_03f = { 3688 .modes = &nlt_nl13676bc25_03f_mode, 3689 .num_modes = 1, 3690 .bpc = 8, 3691 .size = { 3692 .width = 363, 3693 .height = 215, 3694 }, 3695 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3696 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3697 }; 3698 3699 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3700 .pixelclock = { 130000000, 148350000, 163000000 }, 3701 .hactive = { 1920, 1920, 1920 }, 3702 .hfront_porch = { 80, 100, 100 }, 3703 .hback_porch = { 100, 120, 120 }, 3704 .hsync_len = { 50, 60, 60 }, 3705 .vactive = { 1080, 1080, 1080 }, 3706 .vfront_porch = { 12, 30, 30 }, 3707 .vback_porch = { 4, 10, 10 }, 3708 .vsync_len = { 4, 5, 5 }, 3709 }; 3710 3711 static const struct panel_desc nlt_nl192108ac18_02d = { 3712 .timings = &nlt_nl192108ac18_02d_timing, 3713 .num_timings = 1, 3714 .bpc = 8, 3715 .size = { 3716 .width = 344, 3717 .height = 194, 3718 }, 3719 .delay = { 3720 .unprepare = 500, 3721 }, 3722 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3723 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3724 }; 3725 3726 static const struct drm_display_mode nvd_9128_mode = { 3727 .clock = 29500, 3728 .hdisplay = 800, 3729 .hsync_start = 800 + 130, 3730 .hsync_end = 800 + 130 + 98, 3731 .htotal = 800 + 0 + 130 + 98, 3732 .vdisplay = 480, 3733 .vsync_start = 480 + 10, 3734 .vsync_end = 480 + 10 + 50, 3735 .vtotal = 480 + 0 + 10 + 50, 3736 }; 3737 3738 static const struct panel_desc nvd_9128 = { 3739 .modes = &nvd_9128_mode, 3740 .num_modes = 1, 3741 .bpc = 8, 3742 .size = { 3743 .width = 156, 3744 .height = 88, 3745 }, 3746 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3747 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3748 }; 3749 3750 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3751 .pixelclock = { 30000000, 30000000, 40000000 }, 3752 .hactive = { 800, 800, 800 }, 3753 .hfront_porch = { 40, 40, 40 }, 3754 .hback_porch = { 40, 40, 40 }, 3755 .hsync_len = { 1, 48, 48 }, 3756 .vactive = { 480, 480, 480 }, 3757 .vfront_porch = { 13, 13, 13 }, 3758 .vback_porch = { 29, 29, 29 }, 3759 .vsync_len = { 3, 3, 3 }, 3760 .flags = DISPLAY_FLAGS_DE_HIGH, 3761 }; 3762 3763 static const struct panel_desc okaya_rs800480t_7x0gp = { 3764 .timings = &okaya_rs800480t_7x0gp_timing, 3765 .num_timings = 1, 3766 .bpc = 6, 3767 .size = { 3768 .width = 154, 3769 .height = 87, 3770 }, 3771 .delay = { 3772 .prepare = 41, 3773 .enable = 50, 3774 .unprepare = 41, 3775 .disable = 50, 3776 }, 3777 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3778 }; 3779 3780 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3781 .clock = 9000, 3782 .hdisplay = 480, 3783 .hsync_start = 480 + 5, 3784 .hsync_end = 480 + 5 + 30, 3785 .htotal = 480 + 5 + 30 + 10, 3786 .vdisplay = 272, 3787 .vsync_start = 272 + 8, 3788 .vsync_end = 272 + 8 + 5, 3789 .vtotal = 272 + 8 + 5 + 3, 3790 }; 3791 3792 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3793 .modes = &olimex_lcd_olinuxino_43ts_mode, 3794 .num_modes = 1, 3795 .size = { 3796 .width = 95, 3797 .height = 54, 3798 }, 3799 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3800 }; 3801 3802 static const struct drm_display_mode olimex_lcd_olinuxino_5cts_mode = { 3803 .clock = 33300, 3804 .hdisplay = 800, 3805 .hsync_start = 800 + 210, 3806 .hsync_end = 800 + 210 + 20, 3807 .htotal = 800 + 210 + 20 + 26, 3808 .vdisplay = 480, 3809 .vsync_start = 480 + 22, 3810 .vsync_end = 480 + 22 + 10, 3811 .vtotal = 480 + 22 + 10 + 13, 3812 }; 3813 3814 static const struct panel_desc olimex_lcd_olinuxino_5cts = { 3815 .modes = &olimex_lcd_olinuxino_5cts_mode, 3816 .num_modes = 1, 3817 .size = { 3818 .width = 154, 3819 .height = 86, 3820 }, 3821 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3822 }; 3823 3824 3825 static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 3826 .pixelclock = { 30000000, 30000000, 50000000 }, 3827 .hactive = { 800, 800, 800 }, 3828 .hfront_porch = { 1, 40, 255 }, 3829 .hback_porch = { 1, 40, 87 }, 3830 .hsync_len = { 1, 48, 87 }, 3831 .vactive = { 480, 480, 480 }, 3832 .vfront_porch = { 1, 13, 255 }, 3833 .vback_porch = { 1, 29, 29 }, 3834 .vsync_len = { 3, 3, 31 }, 3835 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3836 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3837 }; 3838 3839 static const struct panel_desc ontat_kd50g21_40nt_a1 = { 3840 .timings = &ontat_kd50g21_40nt_a1_timing, 3841 .num_timings = 1, 3842 .bpc = 8, 3843 .size = { 3844 .width = 108, 3845 .height = 65, 3846 }, 3847 .delay = { 3848 .prepare = 147, /* 5 VSDs */ 3849 .enable = 147, /* 5 VSDs */ 3850 .disable = 88, /* 3 VSDs */ 3851 .unprepare = 117, /* 4 VSDs */ 3852 }, 3853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3854 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3855 .connector_type = DRM_MODE_CONNECTOR_DPI, 3856 }; 3857 3858 /* 3859 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3860 * pixel clocks, but this is the timing that was being used in the Adafruit 3861 * installation instructions. 3862 */ 3863 static const struct drm_display_mode ontat_yx700wv03_mode = { 3864 .clock = 29500, 3865 .hdisplay = 800, 3866 .hsync_start = 824, 3867 .hsync_end = 896, 3868 .htotal = 992, 3869 .vdisplay = 480, 3870 .vsync_start = 483, 3871 .vsync_end = 493, 3872 .vtotal = 500, 3873 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3874 }; 3875 3876 /* 3877 * Specification at: 3878 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3879 */ 3880 static const struct panel_desc ontat_yx700wv03 = { 3881 .modes = &ontat_yx700wv03_mode, 3882 .num_modes = 1, 3883 .bpc = 8, 3884 .size = { 3885 .width = 154, 3886 .height = 83, 3887 }, 3888 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3889 }; 3890 3891 static const struct drm_display_mode ortustech_com37h3m_mode = { 3892 .clock = 22230, 3893 .hdisplay = 480, 3894 .hsync_start = 480 + 40, 3895 .hsync_end = 480 + 40 + 10, 3896 .htotal = 480 + 40 + 10 + 40, 3897 .vdisplay = 640, 3898 .vsync_start = 640 + 4, 3899 .vsync_end = 640 + 4 + 2, 3900 .vtotal = 640 + 4 + 2 + 4, 3901 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3902 }; 3903 3904 static const struct panel_desc ortustech_com37h3m = { 3905 .modes = &ortustech_com37h3m_mode, 3906 .num_modes = 1, 3907 .bpc = 8, 3908 .size = { 3909 .width = 56, /* 56.16mm */ 3910 .height = 75, /* 74.88mm */ 3911 }, 3912 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3913 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3914 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3915 }; 3916 3917 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3918 .clock = 25000, 3919 .hdisplay = 480, 3920 .hsync_start = 480 + 10, 3921 .hsync_end = 480 + 10 + 10, 3922 .htotal = 480 + 10 + 10 + 15, 3923 .vdisplay = 800, 3924 .vsync_start = 800 + 3, 3925 .vsync_end = 800 + 3 + 3, 3926 .vtotal = 800 + 3 + 3 + 3, 3927 }; 3928 3929 static const struct panel_desc ortustech_com43h4m85ulc = { 3930 .modes = &ortustech_com43h4m85ulc_mode, 3931 .num_modes = 1, 3932 .bpc = 6, 3933 .size = { 3934 .width = 56, 3935 .height = 93, 3936 }, 3937 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3938 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3939 .connector_type = DRM_MODE_CONNECTOR_DPI, 3940 }; 3941 3942 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3943 .clock = 33000, 3944 .hdisplay = 800, 3945 .hsync_start = 800 + 210, 3946 .hsync_end = 800 + 210 + 30, 3947 .htotal = 800 + 210 + 30 + 16, 3948 .vdisplay = 480, 3949 .vsync_start = 480 + 22, 3950 .vsync_end = 480 + 22 + 13, 3951 .vtotal = 480 + 22 + 13 + 10, 3952 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3953 }; 3954 3955 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3956 .modes = &osddisplays_osd070t1718_19ts_mode, 3957 .num_modes = 1, 3958 .bpc = 8, 3959 .size = { 3960 .width = 152, 3961 .height = 91, 3962 }, 3963 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3964 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3965 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3966 .connector_type = DRM_MODE_CONNECTOR_DPI, 3967 }; 3968 3969 static const struct drm_display_mode pda_91_00156_a0_mode = { 3970 .clock = 33300, 3971 .hdisplay = 800, 3972 .hsync_start = 800 + 1, 3973 .hsync_end = 800 + 1 + 64, 3974 .htotal = 800 + 1 + 64 + 64, 3975 .vdisplay = 480, 3976 .vsync_start = 480 + 1, 3977 .vsync_end = 480 + 1 + 23, 3978 .vtotal = 480 + 1 + 23 + 22, 3979 }; 3980 3981 static const struct panel_desc pda_91_00156_a0 = { 3982 .modes = &pda_91_00156_a0_mode, 3983 .num_modes = 1, 3984 .size = { 3985 .width = 152, 3986 .height = 91, 3987 }, 3988 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3989 }; 3990 3991 static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { 3992 .clock = 71150, 3993 .hdisplay = 1280, 3994 .hsync_start = 1280 + 48, 3995 .hsync_end = 1280 + 48 + 32, 3996 .htotal = 1280 + 48 + 32 + 80, 3997 .vdisplay = 800, 3998 .vsync_start = 800 + 9, 3999 .vsync_end = 800 + 9 + 8, 4000 .vtotal = 800 + 9 + 8 + 6, 4001 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4002 }; 4003 4004 static const struct panel_desc powertip_ph128800t004_zza01 = { 4005 .modes = &powertip_ph128800t004_zza01_mode, 4006 .num_modes = 1, 4007 .bpc = 8, 4008 .size = { 4009 .width = 216, 4010 .height = 135, 4011 }, 4012 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4013 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4014 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4015 }; 4016 4017 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 4018 .clock = 66500, 4019 .hdisplay = 1280, 4020 .hsync_start = 1280 + 12, 4021 .hsync_end = 1280 + 12 + 20, 4022 .htotal = 1280 + 12 + 20 + 56, 4023 .vdisplay = 800, 4024 .vsync_start = 800 + 1, 4025 .vsync_end = 800 + 1 + 3, 4026 .vtotal = 800 + 1 + 3 + 20, 4027 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4028 }; 4029 4030 static const struct panel_desc powertip_ph128800t006_zhc01 = { 4031 .modes = &powertip_ph128800t006_zhc01_mode, 4032 .num_modes = 1, 4033 .bpc = 8, 4034 .size = { 4035 .width = 216, 4036 .height = 135, 4037 }, 4038 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4039 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4040 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4041 }; 4042 4043 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 4044 .clock = 24750, 4045 .hdisplay = 800, 4046 .hsync_start = 800 + 54, 4047 .hsync_end = 800 + 54 + 2, 4048 .htotal = 800 + 54 + 2 + 44, 4049 .vdisplay = 480, 4050 .vsync_start = 480 + 49, 4051 .vsync_end = 480 + 49 + 2, 4052 .vtotal = 480 + 49 + 2 + 22, 4053 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4054 }; 4055 4056 static const struct panel_desc powertip_ph800480t013_idf02 = { 4057 .modes = &powertip_ph800480t013_idf02_mode, 4058 .num_modes = 1, 4059 .bpc = 8, 4060 .size = { 4061 .width = 152, 4062 .height = 91, 4063 }, 4064 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4065 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4066 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4067 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4068 .connector_type = DRM_MODE_CONNECTOR_DPI, 4069 }; 4070 4071 static const struct drm_display_mode primeview_pm070wl4_mode = { 4072 .clock = 32000, 4073 .hdisplay = 800, 4074 .hsync_start = 800 + 42, 4075 .hsync_end = 800 + 42 + 128, 4076 .htotal = 800 + 42 + 128 + 86, 4077 .vdisplay = 480, 4078 .vsync_start = 480 + 10, 4079 .vsync_end = 480 + 10 + 2, 4080 .vtotal = 480 + 10 + 2 + 33, 4081 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4082 }; 4083 4084 static const struct panel_desc primeview_pm070wl4 = { 4085 .modes = &primeview_pm070wl4_mode, 4086 .num_modes = 1, 4087 .bpc = 6, 4088 .size = { 4089 .width = 152, 4090 .height = 91, 4091 }, 4092 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4093 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4094 .connector_type = DRM_MODE_CONNECTOR_DPI, 4095 }; 4096 4097 static const struct drm_display_mode qd43003c0_40_mode = { 4098 .clock = 9000, 4099 .hdisplay = 480, 4100 .hsync_start = 480 + 8, 4101 .hsync_end = 480 + 8 + 4, 4102 .htotal = 480 + 8 + 4 + 39, 4103 .vdisplay = 272, 4104 .vsync_start = 272 + 4, 4105 .vsync_end = 272 + 4 + 10, 4106 .vtotal = 272 + 4 + 10 + 2, 4107 }; 4108 4109 static const struct panel_desc qd43003c0_40 = { 4110 .modes = &qd43003c0_40_mode, 4111 .num_modes = 1, 4112 .bpc = 8, 4113 .size = { 4114 .width = 95, 4115 .height = 53, 4116 }, 4117 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4118 }; 4119 4120 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 4121 { /* 60 Hz */ 4122 .clock = 10800, 4123 .hdisplay = 480, 4124 .hsync_start = 480 + 77, 4125 .hsync_end = 480 + 77 + 41, 4126 .htotal = 480 + 77 + 41 + 2, 4127 .vdisplay = 272, 4128 .vsync_start = 272 + 16, 4129 .vsync_end = 272 + 16 + 10, 4130 .vtotal = 272 + 16 + 10 + 2, 4131 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4132 }, 4133 { /* 50 Hz */ 4134 .clock = 10800, 4135 .hdisplay = 480, 4136 .hsync_start = 480 + 17, 4137 .hsync_end = 480 + 17 + 41, 4138 .htotal = 480 + 17 + 41 + 2, 4139 .vdisplay = 272, 4140 .vsync_start = 272 + 116, 4141 .vsync_end = 272 + 116 + 10, 4142 .vtotal = 272 + 116 + 10 + 2, 4143 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4144 }, 4145 }; 4146 4147 static const struct panel_desc qishenglong_gopher2b_lcd = { 4148 .modes = qishenglong_gopher2b_lcd_modes, 4149 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 4150 .bpc = 8, 4151 .size = { 4152 .width = 95, 4153 .height = 54, 4154 }, 4155 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4156 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4157 .connector_type = DRM_MODE_CONNECTOR_DPI, 4158 }; 4159 4160 static const struct display_timing raystar_rff500f_awh_dnn_timing = { 4161 .pixelclock = { 23000000, 25000000, 27000000 }, 4162 .hactive = { 800, 800, 800 }, 4163 .hback_porch = { 4, 8, 48 }, 4164 .hfront_porch = { 4, 8, 48 }, 4165 .hsync_len = { 2, 4, 8 }, 4166 .vactive = { 480, 480, 480 }, 4167 .vback_porch = { 4, 8, 12 }, 4168 .vfront_porch = { 4, 8, 12 }, 4169 .vsync_len = { 2, 4, 8 }, 4170 }; 4171 4172 static const struct panel_desc raystar_rff500f_awh_dnn = { 4173 .timings = &raystar_rff500f_awh_dnn_timing, 4174 .num_timings = 1, 4175 .bpc = 8, 4176 .size = { 4177 .width = 108, 4178 .height = 65, 4179 }, 4180 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4181 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4182 }; 4183 4184 static const struct display_timing rocktech_rk043fn48h_timing = { 4185 .pixelclock = { 6000000, 9000000, 12000000 }, 4186 .hactive = { 480, 480, 480 }, 4187 .hback_porch = { 8, 43, 43 }, 4188 .hfront_porch = { 2, 8, 10 }, 4189 .hsync_len = { 1, 1, 1 }, 4190 .vactive = { 272, 272, 272 }, 4191 .vback_porch = { 2, 12, 26 }, 4192 .vfront_porch = { 1, 4, 4 }, 4193 .vsync_len = { 1, 10, 10 }, 4194 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 4195 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4196 DISPLAY_FLAGS_SYNC_POSEDGE, 4197 }; 4198 4199 static const struct panel_desc rocktech_rk043fn48h = { 4200 .timings = &rocktech_rk043fn48h_timing, 4201 .num_timings = 1, 4202 .bpc = 8, 4203 .size = { 4204 .width = 95, 4205 .height = 54, 4206 }, 4207 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4208 .connector_type = DRM_MODE_CONNECTOR_DPI, 4209 }; 4210 4211 static const struct display_timing rocktech_rk070er9427_timing = { 4212 .pixelclock = { 26400000, 33300000, 46800000 }, 4213 .hactive = { 800, 800, 800 }, 4214 .hfront_porch = { 16, 210, 354 }, 4215 .hback_porch = { 46, 46, 46 }, 4216 .hsync_len = { 1, 1, 1 }, 4217 .vactive = { 480, 480, 480 }, 4218 .vfront_porch = { 7, 22, 147 }, 4219 .vback_porch = { 23, 23, 23 }, 4220 .vsync_len = { 1, 1, 1 }, 4221 .flags = DISPLAY_FLAGS_DE_HIGH, 4222 }; 4223 4224 static const struct panel_desc rocktech_rk070er9427 = { 4225 .timings = &rocktech_rk070er9427_timing, 4226 .num_timings = 1, 4227 .bpc = 6, 4228 .size = { 4229 .width = 154, 4230 .height = 86, 4231 }, 4232 .delay = { 4233 .prepare = 41, 4234 .enable = 50, 4235 .unprepare = 41, 4236 .disable = 50, 4237 }, 4238 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4239 }; 4240 4241 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4242 .clock = 71100, 4243 .hdisplay = 1280, 4244 .hsync_start = 1280 + 48, 4245 .hsync_end = 1280 + 48 + 32, 4246 .htotal = 1280 + 48 + 32 + 80, 4247 .vdisplay = 800, 4248 .vsync_start = 800 + 2, 4249 .vsync_end = 800 + 2 + 5, 4250 .vtotal = 800 + 2 + 5 + 16, 4251 }; 4252 4253 static const struct panel_desc rocktech_rk101ii01d_ct = { 4254 .modes = &rocktech_rk101ii01d_ct_mode, 4255 .bpc = 8, 4256 .num_modes = 1, 4257 .size = { 4258 .width = 217, 4259 .height = 136, 4260 }, 4261 .delay = { 4262 .prepare = 50, 4263 .disable = 50, 4264 }, 4265 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4266 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4267 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4268 }; 4269 4270 static const struct display_timing samsung_ltl101al01_timing = { 4271 .pixelclock = { 66663000, 66663000, 66663000 }, 4272 .hactive = { 1280, 1280, 1280 }, 4273 .hfront_porch = { 18, 18, 18 }, 4274 .hback_porch = { 36, 36, 36 }, 4275 .hsync_len = { 16, 16, 16 }, 4276 .vactive = { 800, 800, 800 }, 4277 .vfront_porch = { 4, 4, 4 }, 4278 .vback_porch = { 16, 16, 16 }, 4279 .vsync_len = { 3, 3, 3 }, 4280 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4281 }; 4282 4283 static const struct panel_desc samsung_ltl101al01 = { 4284 .timings = &samsung_ltl101al01_timing, 4285 .num_timings = 1, 4286 .bpc = 8, 4287 .size = { 4288 .width = 217, 4289 .height = 135, 4290 }, 4291 .delay = { 4292 .prepare = 40, 4293 .enable = 300, 4294 .disable = 200, 4295 .unprepare = 600, 4296 }, 4297 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4298 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4299 }; 4300 4301 static const struct display_timing samsung_ltl106al01_timing = { 4302 .pixelclock = { 71980000, 71980000, 71980000 }, 4303 .hactive = { 1366, 1366, 1366 }, 4304 .hfront_porch = { 56, 56, 56 }, 4305 .hback_porch = { 106, 106, 106 }, 4306 .hsync_len = { 14, 14, 14 }, 4307 .vactive = { 768, 768, 768 }, 4308 .vfront_porch = { 3, 3, 3 }, 4309 .vback_porch = { 6, 6, 6 }, 4310 .vsync_len = { 1, 1, 1 }, 4311 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4312 }; 4313 4314 static const struct panel_desc samsung_ltl106al01 = { 4315 .timings = &samsung_ltl106al01_timing, 4316 .num_timings = 1, 4317 .bpc = 8, 4318 .size = { 4319 .width = 235, 4320 .height = 132, 4321 }, 4322 .delay = { 4323 .prepare = 5, 4324 .enable = 10, 4325 .disable = 10, 4326 .unprepare = 5, 4327 }, 4328 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4329 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4330 }; 4331 4332 static const struct drm_display_mode samsung_ltn101nt05_mode = { 4333 .clock = 54030, 4334 .hdisplay = 1024, 4335 .hsync_start = 1024 + 24, 4336 .hsync_end = 1024 + 24 + 136, 4337 .htotal = 1024 + 24 + 136 + 160, 4338 .vdisplay = 600, 4339 .vsync_start = 600 + 3, 4340 .vsync_end = 600 + 3 + 6, 4341 .vtotal = 600 + 3 + 6 + 61, 4342 }; 4343 4344 static const struct panel_desc samsung_ltn101nt05 = { 4345 .modes = &samsung_ltn101nt05_mode, 4346 .num_modes = 1, 4347 .bpc = 6, 4348 .size = { 4349 .width = 223, 4350 .height = 125, 4351 }, 4352 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4353 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4354 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4355 }; 4356 4357 static const struct display_timing satoz_sat050at40h12r2_timing = { 4358 .pixelclock = {33300000, 33300000, 50000000}, 4359 .hactive = {800, 800, 800}, 4360 .hfront_porch = {16, 210, 354}, 4361 .hback_porch = {46, 46, 46}, 4362 .hsync_len = {1, 1, 40}, 4363 .vactive = {480, 480, 480}, 4364 .vfront_porch = {7, 22, 147}, 4365 .vback_porch = {23, 23, 23}, 4366 .vsync_len = {1, 1, 20}, 4367 }; 4368 4369 static const struct panel_desc satoz_sat050at40h12r2 = { 4370 .timings = &satoz_sat050at40h12r2_timing, 4371 .num_timings = 1, 4372 .bpc = 8, 4373 .size = { 4374 .width = 108, 4375 .height = 65, 4376 }, 4377 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4378 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4379 }; 4380 4381 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4382 .clock = 33260, 4383 .hdisplay = 800, 4384 .hsync_start = 800 + 64, 4385 .hsync_end = 800 + 64 + 128, 4386 .htotal = 800 + 64 + 128 + 64, 4387 .vdisplay = 480, 4388 .vsync_start = 480 + 8, 4389 .vsync_end = 480 + 8 + 2, 4390 .vtotal = 480 + 8 + 2 + 35, 4391 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4392 }; 4393 4394 static const struct panel_desc sharp_lq070y3dg3b = { 4395 .modes = &sharp_lq070y3dg3b_mode, 4396 .num_modes = 1, 4397 .bpc = 8, 4398 .size = { 4399 .width = 152, /* 152.4mm */ 4400 .height = 91, /* 91.4mm */ 4401 }, 4402 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4403 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4404 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4405 }; 4406 4407 static const struct drm_display_mode sharp_lq035q7db03_mode = { 4408 .clock = 5500, 4409 .hdisplay = 240, 4410 .hsync_start = 240 + 16, 4411 .hsync_end = 240 + 16 + 7, 4412 .htotal = 240 + 16 + 7 + 5, 4413 .vdisplay = 320, 4414 .vsync_start = 320 + 9, 4415 .vsync_end = 320 + 9 + 1, 4416 .vtotal = 320 + 9 + 1 + 7, 4417 }; 4418 4419 static const struct panel_desc sharp_lq035q7db03 = { 4420 .modes = &sharp_lq035q7db03_mode, 4421 .num_modes = 1, 4422 .bpc = 6, 4423 .size = { 4424 .width = 54, 4425 .height = 72, 4426 }, 4427 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4428 }; 4429 4430 static const struct display_timing sharp_lq101k1ly04_timing = { 4431 .pixelclock = { 60000000, 65000000, 80000000 }, 4432 .hactive = { 1280, 1280, 1280 }, 4433 .hfront_porch = { 20, 20, 20 }, 4434 .hback_porch = { 20, 20, 20 }, 4435 .hsync_len = { 10, 10, 10 }, 4436 .vactive = { 800, 800, 800 }, 4437 .vfront_porch = { 4, 4, 4 }, 4438 .vback_porch = { 4, 4, 4 }, 4439 .vsync_len = { 4, 4, 4 }, 4440 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4441 }; 4442 4443 static const struct panel_desc sharp_lq101k1ly04 = { 4444 .timings = &sharp_lq101k1ly04_timing, 4445 .num_timings = 1, 4446 .bpc = 8, 4447 .size = { 4448 .width = 217, 4449 .height = 136, 4450 }, 4451 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4452 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4453 }; 4454 4455 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4456 { /* 50 Hz */ 4457 .clock = 3000, 4458 .hdisplay = 240, 4459 .hsync_start = 240 + 58, 4460 .hsync_end = 240 + 58 + 1, 4461 .htotal = 240 + 58 + 1 + 1, 4462 .vdisplay = 160, 4463 .vsync_start = 160 + 24, 4464 .vsync_end = 160 + 24 + 10, 4465 .vtotal = 160 + 24 + 10 + 6, 4466 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4467 }, 4468 { /* 60 Hz */ 4469 .clock = 3000, 4470 .hdisplay = 240, 4471 .hsync_start = 240 + 8, 4472 .hsync_end = 240 + 8 + 1, 4473 .htotal = 240 + 8 + 1 + 1, 4474 .vdisplay = 160, 4475 .vsync_start = 160 + 24, 4476 .vsync_end = 160 + 24 + 10, 4477 .vtotal = 160 + 24 + 10 + 6, 4478 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4479 }, 4480 }; 4481 4482 static const struct panel_desc sharp_ls020b1dd01d = { 4483 .modes = sharp_ls020b1dd01d_modes, 4484 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4485 .bpc = 6, 4486 .size = { 4487 .width = 42, 4488 .height = 28, 4489 }, 4490 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4491 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4492 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4493 | DRM_BUS_FLAG_SHARP_SIGNALS, 4494 }; 4495 4496 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4497 .clock = 33300, 4498 .hdisplay = 800, 4499 .hsync_start = 800 + 1, 4500 .hsync_end = 800 + 1 + 64, 4501 .htotal = 800 + 1 + 64 + 64, 4502 .vdisplay = 480, 4503 .vsync_start = 480 + 1, 4504 .vsync_end = 480 + 1 + 23, 4505 .vtotal = 480 + 1 + 23 + 22, 4506 }; 4507 4508 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4509 .modes = &shelly_sca07010_bfn_lnn_mode, 4510 .num_modes = 1, 4511 .size = { 4512 .width = 152, 4513 .height = 91, 4514 }, 4515 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4516 }; 4517 4518 static const struct drm_display_mode starry_kr070pe2t_mode = { 4519 .clock = 33000, 4520 .hdisplay = 800, 4521 .hsync_start = 800 + 209, 4522 .hsync_end = 800 + 209 + 1, 4523 .htotal = 800 + 209 + 1 + 45, 4524 .vdisplay = 480, 4525 .vsync_start = 480 + 22, 4526 .vsync_end = 480 + 22 + 1, 4527 .vtotal = 480 + 22 + 1 + 22, 4528 }; 4529 4530 static const struct panel_desc starry_kr070pe2t = { 4531 .modes = &starry_kr070pe2t_mode, 4532 .num_modes = 1, 4533 .bpc = 8, 4534 .size = { 4535 .width = 152, 4536 .height = 86, 4537 }, 4538 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4539 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4540 .connector_type = DRM_MODE_CONNECTOR_DPI, 4541 }; 4542 4543 static const struct display_timing startek_kd070wvfpa_mode = { 4544 .pixelclock = { 25200000, 27200000, 30500000 }, 4545 .hactive = { 800, 800, 800 }, 4546 .hfront_porch = { 19, 44, 115 }, 4547 .hback_porch = { 5, 16, 101 }, 4548 .hsync_len = { 1, 2, 100 }, 4549 .vactive = { 480, 480, 480 }, 4550 .vfront_porch = { 5, 43, 67 }, 4551 .vback_porch = { 5, 5, 67 }, 4552 .vsync_len = { 1, 2, 66 }, 4553 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4554 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4555 DISPLAY_FLAGS_SYNC_POSEDGE, 4556 }; 4557 4558 static const struct panel_desc startek_kd070wvfpa = { 4559 .timings = &startek_kd070wvfpa_mode, 4560 .num_timings = 1, 4561 .bpc = 8, 4562 .size = { 4563 .width = 152, 4564 .height = 91, 4565 }, 4566 .delay = { 4567 .prepare = 20, 4568 .enable = 200, 4569 .disable = 200, 4570 }, 4571 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4572 .connector_type = DRM_MODE_CONNECTOR_DPI, 4573 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4574 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4575 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4576 }; 4577 4578 static const struct display_timing tsd_tst043015cmhx_timing = { 4579 .pixelclock = { 5000000, 9000000, 12000000 }, 4580 .hactive = { 480, 480, 480 }, 4581 .hfront_porch = { 4, 5, 65 }, 4582 .hback_porch = { 36, 40, 255 }, 4583 .hsync_len = { 1, 1, 1 }, 4584 .vactive = { 272, 272, 272 }, 4585 .vfront_porch = { 2, 8, 97 }, 4586 .vback_porch = { 3, 8, 31 }, 4587 .vsync_len = { 1, 1, 1 }, 4588 4589 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4590 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4591 }; 4592 4593 static const struct panel_desc tsd_tst043015cmhx = { 4594 .timings = &tsd_tst043015cmhx_timing, 4595 .num_timings = 1, 4596 .bpc = 8, 4597 .size = { 4598 .width = 105, 4599 .height = 67, 4600 }, 4601 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4602 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4603 }; 4604 4605 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4606 .clock = 30000, 4607 .hdisplay = 800, 4608 .hsync_start = 800 + 39, 4609 .hsync_end = 800 + 39 + 47, 4610 .htotal = 800 + 39 + 47 + 39, 4611 .vdisplay = 480, 4612 .vsync_start = 480 + 13, 4613 .vsync_end = 480 + 13 + 2, 4614 .vtotal = 480 + 13 + 2 + 29, 4615 }; 4616 4617 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4618 .modes = &tfc_s9700rtwv43tr_01b_mode, 4619 .num_modes = 1, 4620 .bpc = 8, 4621 .size = { 4622 .width = 155, 4623 .height = 90, 4624 }, 4625 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4626 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4627 }; 4628 4629 static const struct display_timing tianma_tm070jdhg30_timing = { 4630 .pixelclock = { 62600000, 68200000, 78100000 }, 4631 .hactive = { 1280, 1280, 1280 }, 4632 .hfront_porch = { 15, 64, 159 }, 4633 .hback_porch = { 5, 5, 5 }, 4634 .hsync_len = { 1, 1, 256 }, 4635 .vactive = { 800, 800, 800 }, 4636 .vfront_porch = { 3, 40, 99 }, 4637 .vback_porch = { 2, 2, 2 }, 4638 .vsync_len = { 1, 1, 128 }, 4639 .flags = DISPLAY_FLAGS_DE_HIGH, 4640 }; 4641 4642 static const struct panel_desc tianma_tm070jdhg30 = { 4643 .timings = &tianma_tm070jdhg30_timing, 4644 .num_timings = 1, 4645 .bpc = 8, 4646 .size = { 4647 .width = 151, 4648 .height = 95, 4649 }, 4650 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4651 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4652 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4653 }; 4654 4655 static const struct panel_desc tianma_tm070jvhg33 = { 4656 .timings = &tianma_tm070jdhg30_timing, 4657 .num_timings = 1, 4658 .bpc = 8, 4659 .size = { 4660 .width = 150, 4661 .height = 94, 4662 }, 4663 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4664 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4665 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4666 }; 4667 4668 /* 4669 * The TM070JDHG34-00 datasheet computes total blanking as back porch + 4670 * front porch, not including sync pulse width. This is for both H and 4671 * V. To make the total blanking and period correct, subtract the pulse 4672 * width from the front porch. 4673 * 4674 * This works well for the Min and Typ values, but for Max values the sync 4675 * pulse width is higher than back porch + front porch, so work around that 4676 * by reducing the Max sync length value to 1 and then treating the Max 4677 * porches as in the Min and Typ cases. 4678 * 4679 * Exact datasheet values are added as a comment where they differ from the 4680 * ones implemented for the above reason. 4681 * 4682 * The P0700WXF1MBAA datasheet is even less detailed, only listing period 4683 * and total blanking time, however the resulting values are the same as 4684 * the TM070JDHG34-00. 4685 */ 4686 static const struct display_timing tianma_tm070jdhg34_00_timing = { 4687 .pixelclock = { 68400000, 71900000, 78100000 }, 4688 .hactive = { 1280, 1280, 1280 }, 4689 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4690 .hback_porch = { 5, 5, 5 }, 4691 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4692 .vactive = { 800, 800, 800 }, 4693 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4694 .vback_porch = { 2, 2, 2 }, 4695 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4696 .flags = DISPLAY_FLAGS_DE_HIGH, 4697 }; 4698 4699 static const struct panel_desc tianma_tm070jdhg34_00 = { 4700 .timings = &tianma_tm070jdhg34_00_timing, 4701 .num_timings = 1, 4702 .bpc = 8, 4703 .size = { 4704 .width = 150, /* 149.76 */ 4705 .height = 94, /* 93.60 */ 4706 }, 4707 .delay = { 4708 .prepare = 15, /* Tp1 */ 4709 .enable = 150, /* Tp2 */ 4710 .disable = 150, /* Tp4 */ 4711 .unprepare = 120, /* Tp3 */ 4712 }, 4713 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4714 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4715 }; 4716 4717 static const struct panel_desc tianma_p0700wxf1mbaa = { 4718 .timings = &tianma_tm070jdhg34_00_timing, 4719 .num_timings = 1, 4720 .bpc = 8, 4721 .size = { 4722 .width = 150, /* 149.76 */ 4723 .height = 94, /* 93.60 */ 4724 }, 4725 .delay = { 4726 .prepare = 18, /* Tr + Tp1 */ 4727 .enable = 152, /* Tp2 + Tp5 */ 4728 .disable = 152, /* Tp6 + Tp4 */ 4729 .unprepare = 120, /* Tp3 */ 4730 }, 4731 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4732 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4733 }; 4734 4735 static const struct display_timing tianma_tm070rvhg71_timing = { 4736 .pixelclock = { 27700000, 29200000, 39600000 }, 4737 .hactive = { 800, 800, 800 }, 4738 .hfront_porch = { 12, 40, 212 }, 4739 .hback_porch = { 88, 88, 88 }, 4740 .hsync_len = { 1, 1, 40 }, 4741 .vactive = { 480, 480, 480 }, 4742 .vfront_porch = { 1, 13, 88 }, 4743 .vback_porch = { 32, 32, 32 }, 4744 .vsync_len = { 1, 1, 3 }, 4745 .flags = DISPLAY_FLAGS_DE_HIGH, 4746 }; 4747 4748 static const struct panel_desc tianma_tm070rvhg71 = { 4749 .timings = &tianma_tm070rvhg71_timing, 4750 .num_timings = 1, 4751 .bpc = 8, 4752 .size = { 4753 .width = 154, 4754 .height = 86, 4755 }, 4756 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4757 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4758 }; 4759 4760 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4761 { 4762 .clock = 10000, 4763 .hdisplay = 320, 4764 .hsync_start = 320 + 50, 4765 .hsync_end = 320 + 50 + 6, 4766 .htotal = 320 + 50 + 6 + 38, 4767 .vdisplay = 240, 4768 .vsync_start = 240 + 3, 4769 .vsync_end = 240 + 3 + 1, 4770 .vtotal = 240 + 3 + 1 + 17, 4771 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4772 }, 4773 }; 4774 4775 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4776 .modes = ti_nspire_cx_lcd_mode, 4777 .num_modes = 1, 4778 .bpc = 8, 4779 .size = { 4780 .width = 65, 4781 .height = 49, 4782 }, 4783 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4784 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4785 }; 4786 4787 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4788 { 4789 .clock = 10000, 4790 .hdisplay = 320, 4791 .hsync_start = 320 + 6, 4792 .hsync_end = 320 + 6 + 6, 4793 .htotal = 320 + 6 + 6 + 6, 4794 .vdisplay = 240, 4795 .vsync_start = 240 + 0, 4796 .vsync_end = 240 + 0 + 1, 4797 .vtotal = 240 + 0 + 1 + 0, 4798 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4799 }, 4800 }; 4801 4802 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4803 .modes = ti_nspire_classic_lcd_mode, 4804 .num_modes = 1, 4805 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4806 .bpc = 8, 4807 .size = { 4808 .width = 71, 4809 .height = 53, 4810 }, 4811 /* This is the grayscale bus format */ 4812 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4813 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4814 }; 4815 4816 static const struct display_timing topland_tian_g07017_01_timing = { 4817 .pixelclock = { 44900000, 51200000, 63000000 }, 4818 .hactive = { 1024, 1024, 1024 }, 4819 .hfront_porch = { 16, 160, 216 }, 4820 .hback_porch = { 160, 160, 160 }, 4821 .hsync_len = { 1, 1, 140 }, 4822 .vactive = { 600, 600, 600 }, 4823 .vfront_porch = { 1, 12, 127 }, 4824 .vback_porch = { 23, 23, 23 }, 4825 .vsync_len = { 1, 1, 20 }, 4826 }; 4827 4828 static const struct panel_desc topland_tian_g07017_01 = { 4829 .timings = &topland_tian_g07017_01_timing, 4830 .num_timings = 1, 4831 .bpc = 8, 4832 .size = { 4833 .width = 154, 4834 .height = 86, 4835 }, 4836 .delay = { 4837 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 4838 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 4839 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 4840 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 4841 }, 4842 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4843 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4844 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4845 }; 4846 4847 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4848 .clock = 79500, 4849 .hdisplay = 1280, 4850 .hsync_start = 1280 + 192, 4851 .hsync_end = 1280 + 192 + 128, 4852 .htotal = 1280 + 192 + 128 + 64, 4853 .vdisplay = 768, 4854 .vsync_start = 768 + 20, 4855 .vsync_end = 768 + 20 + 7, 4856 .vtotal = 768 + 20 + 7 + 3, 4857 }; 4858 4859 static const struct panel_desc toshiba_lt089ac29000 = { 4860 .modes = &toshiba_lt089ac29000_mode, 4861 .num_modes = 1, 4862 .size = { 4863 .width = 194, 4864 .height = 116, 4865 }, 4866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4867 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4868 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4869 }; 4870 4871 static const struct drm_display_mode tpk_f07a_0102_mode = { 4872 .clock = 33260, 4873 .hdisplay = 800, 4874 .hsync_start = 800 + 40, 4875 .hsync_end = 800 + 40 + 128, 4876 .htotal = 800 + 40 + 128 + 88, 4877 .vdisplay = 480, 4878 .vsync_start = 480 + 10, 4879 .vsync_end = 480 + 10 + 2, 4880 .vtotal = 480 + 10 + 2 + 33, 4881 }; 4882 4883 static const struct panel_desc tpk_f07a_0102 = { 4884 .modes = &tpk_f07a_0102_mode, 4885 .num_modes = 1, 4886 .size = { 4887 .width = 152, 4888 .height = 91, 4889 }, 4890 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4891 }; 4892 4893 static const struct drm_display_mode tpk_f10a_0102_mode = { 4894 .clock = 45000, 4895 .hdisplay = 1024, 4896 .hsync_start = 1024 + 176, 4897 .hsync_end = 1024 + 176 + 5, 4898 .htotal = 1024 + 176 + 5 + 88, 4899 .vdisplay = 600, 4900 .vsync_start = 600 + 20, 4901 .vsync_end = 600 + 20 + 5, 4902 .vtotal = 600 + 20 + 5 + 25, 4903 }; 4904 4905 static const struct panel_desc tpk_f10a_0102 = { 4906 .modes = &tpk_f10a_0102_mode, 4907 .num_modes = 1, 4908 .size = { 4909 .width = 223, 4910 .height = 125, 4911 }, 4912 }; 4913 4914 static const struct display_timing urt_umsh_8596md_timing = { 4915 .pixelclock = { 33260000, 33260000, 33260000 }, 4916 .hactive = { 800, 800, 800 }, 4917 .hfront_porch = { 41, 41, 41 }, 4918 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4919 .hsync_len = { 71, 128, 128 }, 4920 .vactive = { 480, 480, 480 }, 4921 .vfront_porch = { 10, 10, 10 }, 4922 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4923 .vsync_len = { 2, 2, 2 }, 4924 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4925 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4926 }; 4927 4928 static const struct panel_desc urt_umsh_8596md_lvds = { 4929 .timings = &urt_umsh_8596md_timing, 4930 .num_timings = 1, 4931 .bpc = 6, 4932 .size = { 4933 .width = 152, 4934 .height = 91, 4935 }, 4936 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4937 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4938 }; 4939 4940 static const struct panel_desc urt_umsh_8596md_parallel = { 4941 .timings = &urt_umsh_8596md_timing, 4942 .num_timings = 1, 4943 .bpc = 6, 4944 .size = { 4945 .width = 152, 4946 .height = 91, 4947 }, 4948 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4949 }; 4950 4951 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4952 .clock = 60000, 4953 .hdisplay = 1024, 4954 .hsync_start = 1024 + 160, 4955 .hsync_end = 1024 + 160 + 100, 4956 .htotal = 1024 + 160 + 100 + 60, 4957 .vdisplay = 600, 4958 .vsync_start = 600 + 12, 4959 .vsync_end = 600 + 12 + 10, 4960 .vtotal = 600 + 12 + 10 + 13, 4961 }; 4962 4963 static const struct panel_desc vivax_tpc9150_panel = { 4964 .modes = &vivax_tpc9150_panel_mode, 4965 .num_modes = 1, 4966 .bpc = 6, 4967 .size = { 4968 .width = 200, 4969 .height = 115, 4970 }, 4971 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4972 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4973 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4974 }; 4975 4976 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4977 .clock = 33333, 4978 .hdisplay = 800, 4979 .hsync_start = 800 + 210, 4980 .hsync_end = 800 + 210 + 20, 4981 .htotal = 800 + 210 + 20 + 46, 4982 .vdisplay = 480, 4983 .vsync_start = 480 + 22, 4984 .vsync_end = 480 + 22 + 10, 4985 .vtotal = 480 + 22 + 10 + 23, 4986 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4987 }; 4988 4989 static const struct panel_desc vl050_8048nt_c01 = { 4990 .modes = &vl050_8048nt_c01_mode, 4991 .num_modes = 1, 4992 .bpc = 8, 4993 .size = { 4994 .width = 120, 4995 .height = 76, 4996 }, 4997 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4998 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4999 }; 5000 5001 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 5002 .clock = 6410, 5003 .hdisplay = 320, 5004 .hsync_start = 320 + 20, 5005 .hsync_end = 320 + 20 + 30, 5006 .htotal = 320 + 20 + 30 + 38, 5007 .vdisplay = 240, 5008 .vsync_start = 240 + 4, 5009 .vsync_end = 240 + 4 + 3, 5010 .vtotal = 240 + 4 + 3 + 15, 5011 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5012 }; 5013 5014 static const struct panel_desc winstar_wf35ltiacd = { 5015 .modes = &winstar_wf35ltiacd_mode, 5016 .num_modes = 1, 5017 .bpc = 8, 5018 .size = { 5019 .width = 70, 5020 .height = 53, 5021 }, 5022 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5023 }; 5024 5025 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 5026 .clock = 51200, 5027 .hdisplay = 1024, 5028 .hsync_start = 1024 + 100, 5029 .hsync_end = 1024 + 100 + 100, 5030 .htotal = 1024 + 100 + 100 + 120, 5031 .vdisplay = 600, 5032 .vsync_start = 600 + 10, 5033 .vsync_end = 600 + 10 + 10, 5034 .vtotal = 600 + 10 + 10 + 15, 5035 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 5036 }; 5037 5038 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 5039 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 5040 .num_modes = 1, 5041 .bpc = 8, 5042 .size = { 5043 .width = 154, 5044 .height = 90, 5045 }, 5046 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5047 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5048 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5049 }; 5050 5051 static const struct drm_display_mode mchp_ac69t88a_mode = { 5052 .clock = 25000, 5053 .hdisplay = 800, 5054 .hsync_start = 800 + 88, 5055 .hsync_end = 800 + 88 + 5, 5056 .htotal = 800 + 88 + 5 + 40, 5057 .vdisplay = 480, 5058 .vsync_start = 480 + 23, 5059 .vsync_end = 480 + 23 + 5, 5060 .vtotal = 480 + 23 + 5 + 1, 5061 }; 5062 5063 static const struct panel_desc mchp_ac69t88a = { 5064 .modes = &mchp_ac69t88a_mode, 5065 .num_modes = 1, 5066 .bpc = 8, 5067 .size = { 5068 .width = 108, 5069 .height = 65, 5070 }, 5071 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5072 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 5073 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5074 }; 5075 5076 static const struct drm_display_mode arm_rtsm_mode[] = { 5077 { 5078 .clock = 65000, 5079 .hdisplay = 1024, 5080 .hsync_start = 1024 + 24, 5081 .hsync_end = 1024 + 24 + 136, 5082 .htotal = 1024 + 24 + 136 + 160, 5083 .vdisplay = 768, 5084 .vsync_start = 768 + 3, 5085 .vsync_end = 768 + 3 + 6, 5086 .vtotal = 768 + 3 + 6 + 29, 5087 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5088 }, 5089 }; 5090 5091 static const struct panel_desc arm_rtsm = { 5092 .modes = arm_rtsm_mode, 5093 .num_modes = 1, 5094 .bpc = 8, 5095 .size = { 5096 .width = 400, 5097 .height = 300, 5098 }, 5099 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5100 }; 5101 5102 static const struct of_device_id platform_of_match[] = { 5103 { 5104 .compatible = "ampire,am-1280800n3tzqw-t00h", 5105 .data = &ire_am_1280800n3tzqw_t00h, 5106 }, { 5107 .compatible = "ampire,am-480272h3tmqw-t01h", 5108 .data = &ire_am_480272h3tmqw_t01h, 5109 }, { 5110 .compatible = "ampire,am-800480l1tmqw-t00h", 5111 .data = &ire_am_800480l1tmqw_t00h, 5112 }, { 5113 .compatible = "ampire,am800480r3tmqwa1h", 5114 .data = &ire_am800480r3tmqwa1h, 5115 }, { 5116 .compatible = "ampire,am800600p5tmqw-tb8h", 5117 .data = &ire_am800600p5tmqwtb8h, 5118 }, { 5119 .compatible = "arm,rtsm-display", 5120 .data = &arm_rtsm, 5121 }, { 5122 .compatible = "armadeus,st0700-adapt", 5123 .data = &armadeus_st0700_adapt, 5124 }, { 5125 .compatible = "auo,b101aw03", 5126 .data = &auo_b101aw03, 5127 }, { 5128 .compatible = "auo,b101xtn01", 5129 .data = &auo_b101xtn01, 5130 }, { 5131 .compatible = "auo,b116xw03", 5132 .data = &auo_b116xw03, 5133 }, { 5134 .compatible = "auo,g070vvn01", 5135 .data = &auo_g070vvn01, 5136 }, { 5137 .compatible = "auo,g101evn010", 5138 .data = &auo_g101evn010, 5139 }, { 5140 .compatible = "auo,g104sn02", 5141 .data = &auo_g104sn02, 5142 }, { 5143 .compatible = "auo,g104stn01", 5144 .data = &auo_g104stn01, 5145 }, { 5146 .compatible = "auo,g121ean01", 5147 .data = &auo_g121ean01, 5148 }, { 5149 .compatible = "auo,g133han01", 5150 .data = &auo_g133han01, 5151 }, { 5152 .compatible = "auo,g156han04", 5153 .data = &auo_g156han04, 5154 }, { 5155 .compatible = "auo,g156xtn01", 5156 .data = &auo_g156xtn01, 5157 }, { 5158 .compatible = "auo,g185han01", 5159 .data = &auo_g185han01, 5160 }, { 5161 .compatible = "auo,g190ean01", 5162 .data = &auo_g190ean01, 5163 }, { 5164 .compatible = "auo,p238han01", 5165 .data = &auo_p238han01, 5166 }, { 5167 .compatible = "auo,p320hvn03", 5168 .data = &auo_p320hvn03, 5169 }, { 5170 .compatible = "auo,t215hvn01", 5171 .data = &auo_t215hvn01, 5172 }, { 5173 .compatible = "avic,tm070ddh03", 5174 .data = &avic_tm070ddh03, 5175 }, { 5176 .compatible = "bananapi,s070wv20-ct16", 5177 .data = &bananapi_s070wv20_ct16, 5178 }, { 5179 .compatible = "boe,av101hdt-a10", 5180 .data = &boe_av101hdt_a10, 5181 }, { 5182 .compatible = "boe,av123z7m-n17", 5183 .data = &boe_av123z7m_n17, 5184 }, { 5185 .compatible = "boe,bp082wx1-100", 5186 .data = &boe_bp082wx1_100, 5187 }, { 5188 .compatible = "boe,bp101wx1-100", 5189 .data = &boe_bp101wx1_100, 5190 }, { 5191 .compatible = "boe,ev121wxm-n10-1850", 5192 .data = &boe_ev121wxm_n10_1850, 5193 }, { 5194 .compatible = "boe,hv070wsa-100", 5195 .data = &boe_hv070wsa 5196 }, { 5197 .compatible = "cct,cmt430b19n00", 5198 .data = &cct_cmt430b19n00, 5199 }, { 5200 .compatible = "cdtech,s043wq26h-ct7", 5201 .data = &cdtech_s043wq26h_ct7, 5202 }, { 5203 .compatible = "cdtech,s070pws19hp-fc21", 5204 .data = &cdtech_s070pws19hp_fc21, 5205 }, { 5206 .compatible = "cdtech,s070swv29hg-dc44", 5207 .data = &cdtech_s070swv29hg_dc44, 5208 }, { 5209 .compatible = "cdtech,s070wv95-ct16", 5210 .data = &cdtech_s070wv95_ct16, 5211 }, { 5212 .compatible = "chefree,ch101olhlwh-002", 5213 .data = &chefree_ch101olhlwh_002, 5214 }, { 5215 .compatible = "chunghwa,claa070wp03xg", 5216 .data = &chunghwa_claa070wp03xg, 5217 }, { 5218 .compatible = "chunghwa,claa101wa01a", 5219 .data = &chunghwa_claa101wa01a 5220 }, { 5221 .compatible = "chunghwa,claa101wb01", 5222 .data = &chunghwa_claa101wb01 5223 }, { 5224 .compatible = "dataimage,fg040346dsswbg04", 5225 .data = &dataimage_fg040346dsswbg04, 5226 }, { 5227 .compatible = "dataimage,fg1001l0dsswmg01", 5228 .data = &dataimage_fg1001l0dsswmg01, 5229 }, { 5230 .compatible = "dataimage,scf0700c48ggu18", 5231 .data = &dataimage_scf0700c48ggu18, 5232 }, { 5233 .compatible = "dlc,dlc0700yzg-1", 5234 .data = &dlc_dlc0700yzg_1, 5235 }, { 5236 .compatible = "dlc,dlc1010gig", 5237 .data = &dlc_dlc1010gig, 5238 }, { 5239 .compatible = "edt,et035012dm6", 5240 .data = &edt_et035012dm6, 5241 }, { 5242 .compatible = "edt,etm0350g0dh6", 5243 .data = &edt_etm0350g0dh6, 5244 }, { 5245 .compatible = "edt,etm043080dh6gp", 5246 .data = &edt_etm043080dh6gp, 5247 }, { 5248 .compatible = "edt,etm0430g0dh6", 5249 .data = &edt_etm0430g0dh6, 5250 }, { 5251 .compatible = "edt,et057090dhu", 5252 .data = &edt_et057090dhu, 5253 }, { 5254 .compatible = "edt,et070080dh6", 5255 .data = &edt_etm0700g0dh6, 5256 }, { 5257 .compatible = "edt,etm0700g0dh6", 5258 .data = &edt_etm0700g0dh6, 5259 }, { 5260 .compatible = "edt,etm0700g0bdh6", 5261 .data = &edt_etm0700g0bdh6, 5262 }, { 5263 .compatible = "edt,etm0700g0edh6", 5264 .data = &edt_etm0700g0bdh6, 5265 }, { 5266 .compatible = "edt,etml0700y5dha", 5267 .data = &edt_etml0700y5dha, 5268 }, { 5269 .compatible = "edt,etml1010g3dra", 5270 .data = &edt_etml1010g3dra, 5271 }, { 5272 .compatible = "edt,etmv570g2dhu", 5273 .data = &edt_etmv570g2dhu, 5274 }, { 5275 .compatible = "eink,vb3300-kca", 5276 .data = &eink_vb3300_kca, 5277 }, { 5278 .compatible = "evervision,vgg644804", 5279 .data = &evervision_vgg644804, 5280 }, { 5281 .compatible = "evervision,vgg804821", 5282 .data = &evervision_vgg804821, 5283 }, { 5284 .compatible = "foxlink,fl500wvr00-a0t", 5285 .data = &foxlink_fl500wvr00_a0t, 5286 }, { 5287 .compatible = "frida,frd350h54004", 5288 .data = &frida_frd350h54004, 5289 }, { 5290 .compatible = "friendlyarm,hd702e", 5291 .data = &friendlyarm_hd702e, 5292 }, { 5293 .compatible = "giantplus,gpg482739qs5", 5294 .data = &giantplus_gpg482739qs5 5295 }, { 5296 .compatible = "giantplus,gpm940b0", 5297 .data = &giantplus_gpm940b0, 5298 }, { 5299 .compatible = "hannstar,hsd070pww1", 5300 .data = &hannstar_hsd070pww1, 5301 }, { 5302 .compatible = "hannstar,hsd100pxn1", 5303 .data = &hannstar_hsd100pxn1, 5304 }, { 5305 .compatible = "hannstar,hsd101pww2", 5306 .data = &hannstar_hsd101pww2, 5307 }, { 5308 .compatible = "hannstar,hsd156juw2", 5309 .data = &hannstar_hsd156juw2, 5310 }, { 5311 .compatible = "hit,tx23d38vm0caa", 5312 .data = &hitachi_tx23d38vm0caa 5313 }, { 5314 .compatible = "innolux,at043tn24", 5315 .data = &innolux_at043tn24, 5316 }, { 5317 .compatible = "innolux,at070tn92", 5318 .data = &innolux_at070tn92, 5319 }, { 5320 .compatible = "innolux,g070ace-l01", 5321 .data = &innolux_g070ace_l01, 5322 }, { 5323 .compatible = "innolux,g070ace-lh3", 5324 .data = &innolux_g070ace_lh3, 5325 }, { 5326 .compatible = "innolux,g070y2-l01", 5327 .data = &innolux_g070y2_l01, 5328 }, { 5329 .compatible = "innolux,g070y2-t02", 5330 .data = &innolux_g070y2_t02, 5331 }, { 5332 .compatible = "innolux,g101ice-l01", 5333 .data = &innolux_g101ice_l01 5334 }, { 5335 .compatible = "innolux,g121i1-l01", 5336 .data = &innolux_g121i1_l01 5337 }, { 5338 .compatible = "innolux,g121x1-l03", 5339 .data = &innolux_g121x1_l03, 5340 }, { 5341 .compatible = "innolux,g121xce-l01", 5342 .data = &innolux_g121xce_l01, 5343 }, { 5344 .compatible = "innolux,g150xge-l05", 5345 .data = &innolux_g150xge_l05, 5346 }, { 5347 .compatible = "innolux,g156hce-l01", 5348 .data = &innolux_g156hce_l01, 5349 }, { 5350 .compatible = "innolux,n156bge-l21", 5351 .data = &innolux_n156bge_l21, 5352 }, { 5353 .compatible = "innolux,zj070na-01p", 5354 .data = &innolux_zj070na_01p, 5355 }, { 5356 .compatible = "jutouch,jt101tm023", 5357 .data = &jutouch_jt101tm023, 5358 }, { 5359 .compatible = "koe,tx14d24vm1bpa", 5360 .data = &koe_tx14d24vm1bpa, 5361 }, { 5362 .compatible = "koe,tx26d202vm0bwa", 5363 .data = &koe_tx26d202vm0bwa, 5364 }, { 5365 .compatible = "koe,tx31d200vm0baa", 5366 .data = &koe_tx31d200vm0baa, 5367 }, { 5368 .compatible = "kyo,tcg121xglp", 5369 .data = &kyo_tcg121xglp, 5370 }, { 5371 .compatible = "lemaker,bl035-rgb-002", 5372 .data = &lemaker_bl035_rgb_002, 5373 }, { 5374 .compatible = "lg,lb070wv8", 5375 .data = &lg_lb070wv8, 5376 }, { 5377 .compatible = "lincolntech,lcd185-101ct", 5378 .data = &lincolntech_lcd185_101ct, 5379 }, { 5380 .compatible = "logicpd,type28", 5381 .data = &logicpd_type_28, 5382 }, { 5383 .compatible = "logictechno,lt161010-2nhc", 5384 .data = &logictechno_lt161010_2nh, 5385 }, { 5386 .compatible = "logictechno,lt161010-2nhr", 5387 .data = &logictechno_lt161010_2nh, 5388 }, { 5389 .compatible = "logictechno,lt170410-2whc", 5390 .data = &logictechno_lt170410_2whc, 5391 }, { 5392 .compatible = "logictechno,lttd800480070-l2rt", 5393 .data = &logictechno_lttd800480070_l2rt, 5394 }, { 5395 .compatible = "logictechno,lttd800480070-l6wh-rt", 5396 .data = &logictechno_lttd800480070_l6wh_rt, 5397 }, { 5398 .compatible = "microtips,mf-101hiebcaf0", 5399 .data = µtips_mf_101hiebcaf0_c, 5400 }, { 5401 .compatible = "microtips,mf-103hieb0ga0", 5402 .data = µtips_mf_103hieb0ga0, 5403 }, { 5404 .compatible = "mitsubishi,aa070mc01-ca1", 5405 .data = &mitsubishi_aa070mc01, 5406 }, { 5407 .compatible = "mitsubishi,aa084xe01", 5408 .data = &mitsubishi_aa084xe01, 5409 }, { 5410 .compatible = "multi-inno,mi0700a2t-30", 5411 .data = &multi_inno_mi0700a2t_30, 5412 }, { 5413 .compatible = "multi-inno,mi0700s4t-6", 5414 .data = &multi_inno_mi0700s4t_6, 5415 }, { 5416 .compatible = "multi-inno,mi0800ft-9", 5417 .data = &multi_inno_mi0800ft_9, 5418 }, { 5419 .compatible = "multi-inno,mi1010ait-1cp", 5420 .data = &multi_inno_mi1010ait_1cp, 5421 }, { 5422 .compatible = "multi-inno,mi1010z1t-1cp11", 5423 .data = &multi_inno_mi1010z1t_1cp11, 5424 }, { 5425 .compatible = "nec,nl12880bc20-05", 5426 .data = &nec_nl12880bc20_05, 5427 }, { 5428 .compatible = "nec,nl4827hc19-05b", 5429 .data = &nec_nl4827hc19_05b, 5430 }, { 5431 .compatible = "netron-dy,e231732", 5432 .data = &netron_dy_e231732, 5433 }, { 5434 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 5435 .data = &newhaven_nhd_43_480272ef_atxl, 5436 }, { 5437 .compatible = "nlt,nl13676bc25-03f", 5438 .data = &nlt_nl13676bc25_03f, 5439 }, { 5440 .compatible = "nlt,nl192108ac18-02d", 5441 .data = &nlt_nl192108ac18_02d, 5442 }, { 5443 .compatible = "nvd,9128", 5444 .data = &nvd_9128, 5445 }, { 5446 .compatible = "okaya,rs800480t-7x0gp", 5447 .data = &okaya_rs800480t_7x0gp, 5448 }, { 5449 .compatible = "olimex,lcd-olinuxino-43-ts", 5450 .data = &olimex_lcd_olinuxino_43ts, 5451 }, { 5452 .compatible = "olimex,lcd-olinuxino-5-cts", 5453 .data = &olimex_lcd_olinuxino_5cts, 5454 }, { 5455 .compatible = "ontat,kd50g21-40nt-a1", 5456 .data = &ontat_kd50g21_40nt_a1, 5457 }, { 5458 .compatible = "ontat,yx700wv03", 5459 .data = &ontat_yx700wv03, 5460 }, { 5461 .compatible = "ortustech,com37h3m05dtc", 5462 .data = &ortustech_com37h3m, 5463 }, { 5464 .compatible = "ortustech,com37h3m99dtc", 5465 .data = &ortustech_com37h3m, 5466 }, { 5467 .compatible = "ortustech,com43h4m85ulc", 5468 .data = &ortustech_com43h4m85ulc, 5469 }, { 5470 .compatible = "osddisplays,osd070t1718-19ts", 5471 .data = &osddisplays_osd070t1718_19ts, 5472 }, { 5473 .compatible = "pda,91-00156-a0", 5474 .data = &pda_91_00156_a0, 5475 }, { 5476 .compatible = "powertip,ph128800t004-zza01", 5477 .data = &powertip_ph128800t004_zza01, 5478 }, { 5479 .compatible = "powertip,ph128800t006-zhc01", 5480 .data = &powertip_ph128800t006_zhc01, 5481 }, { 5482 .compatible = "powertip,ph800480t013-idf02", 5483 .data = &powertip_ph800480t013_idf02, 5484 }, { 5485 .compatible = "primeview,pm070wl4", 5486 .data = &primeview_pm070wl4, 5487 }, { 5488 .compatible = "qiaodian,qd43003c0-40", 5489 .data = &qd43003c0_40, 5490 }, { 5491 .compatible = "qishenglong,gopher2b-lcd", 5492 .data = &qishenglong_gopher2b_lcd, 5493 }, { 5494 .compatible = "raystar,rff500f-awh-dnn", 5495 .data = &raystar_rff500f_awh_dnn, 5496 }, { 5497 .compatible = "rocktech,rk043fn48h", 5498 .data = &rocktech_rk043fn48h, 5499 }, { 5500 .compatible = "rocktech,rk070er9427", 5501 .data = &rocktech_rk070er9427, 5502 }, { 5503 .compatible = "rocktech,rk101ii01d-ct", 5504 .data = &rocktech_rk101ii01d_ct, 5505 }, { 5506 .compatible = "samsung,ltl101al01", 5507 .data = &samsung_ltl101al01, 5508 }, { 5509 .compatible = "samsung,ltl106al01", 5510 .data = &samsung_ltl106al01, 5511 }, { 5512 .compatible = "samsung,ltn101nt05", 5513 .data = &samsung_ltn101nt05, 5514 }, { 5515 .compatible = "satoz,sat050at40h12r2", 5516 .data = &satoz_sat050at40h12r2, 5517 }, { 5518 .compatible = "sharp,lq035q7db03", 5519 .data = &sharp_lq035q7db03, 5520 }, { 5521 .compatible = "sharp,lq070y3dg3b", 5522 .data = &sharp_lq070y3dg3b, 5523 }, { 5524 .compatible = "sharp,lq101k1ly04", 5525 .data = &sharp_lq101k1ly04, 5526 }, { 5527 .compatible = "sharp,ls020b1dd01d", 5528 .data = &sharp_ls020b1dd01d, 5529 }, { 5530 .compatible = "shelly,sca07010-bfn-lnn", 5531 .data = &shelly_sca07010_bfn_lnn, 5532 }, { 5533 .compatible = "starry,kr070pe2t", 5534 .data = &starry_kr070pe2t, 5535 }, { 5536 .compatible = "startek,kd070wvfpa", 5537 .data = &startek_kd070wvfpa, 5538 }, { 5539 .compatible = "team-source-display,tst043015cmhx", 5540 .data = &tsd_tst043015cmhx, 5541 }, { 5542 .compatible = "tfc,s9700rtwv43tr-01b", 5543 .data = &tfc_s9700rtwv43tr_01b, 5544 }, { 5545 .compatible = "tianma,p0700wxf1mbaa", 5546 .data = &tianma_p0700wxf1mbaa, 5547 }, { 5548 .compatible = "tianma,tm070jdhg30", 5549 .data = &tianma_tm070jdhg30, 5550 }, { 5551 .compatible = "tianma,tm070jdhg34-00", 5552 .data = &tianma_tm070jdhg34_00, 5553 }, { 5554 .compatible = "tianma,tm070jvhg33", 5555 .data = &tianma_tm070jvhg33, 5556 }, { 5557 .compatible = "tianma,tm070rvhg71", 5558 .data = &tianma_tm070rvhg71, 5559 }, { 5560 .compatible = "ti,nspire-cx-lcd-panel", 5561 .data = &ti_nspire_cx_lcd_panel, 5562 }, { 5563 .compatible = "ti,nspire-classic-lcd-panel", 5564 .data = &ti_nspire_classic_lcd_panel, 5565 }, { 5566 .compatible = "toshiba,lt089ac29000", 5567 .data = &toshiba_lt089ac29000, 5568 }, { 5569 .compatible = "topland,tian-g07017-01", 5570 .data = &topland_tian_g07017_01, 5571 }, { 5572 .compatible = "tpk,f07a-0102", 5573 .data = &tpk_f07a_0102, 5574 }, { 5575 .compatible = "tpk,f10a-0102", 5576 .data = &tpk_f10a_0102, 5577 }, { 5578 .compatible = "urt,umsh-8596md-t", 5579 .data = &urt_umsh_8596md_parallel, 5580 }, { 5581 .compatible = "urt,umsh-8596md-1t", 5582 .data = &urt_umsh_8596md_parallel, 5583 }, { 5584 .compatible = "urt,umsh-8596md-7t", 5585 .data = &urt_umsh_8596md_parallel, 5586 }, { 5587 .compatible = "urt,umsh-8596md-11t", 5588 .data = &urt_umsh_8596md_lvds, 5589 }, { 5590 .compatible = "urt,umsh-8596md-19t", 5591 .data = &urt_umsh_8596md_lvds, 5592 }, { 5593 .compatible = "urt,umsh-8596md-20t", 5594 .data = &urt_umsh_8596md_parallel, 5595 }, { 5596 .compatible = "vivax,tpc9150-panel", 5597 .data = &vivax_tpc9150_panel, 5598 }, { 5599 .compatible = "vxt,vl050-8048nt-c01", 5600 .data = &vl050_8048nt_c01, 5601 }, { 5602 .compatible = "winstar,wf35ltiacd", 5603 .data = &winstar_wf35ltiacd, 5604 }, { 5605 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 5606 .data = &yes_optoelectronics_ytc700tlag_05_201c, 5607 }, { 5608 .compatible = "microchip,ac69t88a", 5609 .data = &mchp_ac69t88a, 5610 }, { 5611 /* Must be the last entry */ 5612 .compatible = "panel-dpi", 5613 5614 /* 5615 * Explicitly NULL, the panel_desc structure will be 5616 * allocated by panel_dpi_probe(). 5617 */ 5618 .data = NULL, 5619 }, { 5620 /* sentinel */ 5621 } 5622 }; 5623 MODULE_DEVICE_TABLE(of, platform_of_match); 5624 5625 static int panel_simple_platform_probe(struct platform_device *pdev) 5626 { 5627 struct panel_simple *panel; 5628 5629 panel = panel_simple_probe(&pdev->dev); 5630 if (IS_ERR(panel)) 5631 return PTR_ERR(panel); 5632 5633 return 0; 5634 } 5635 5636 static void panel_simple_platform_remove(struct platform_device *pdev) 5637 { 5638 panel_simple_remove(&pdev->dev); 5639 } 5640 5641 static void panel_simple_platform_shutdown(struct platform_device *pdev) 5642 { 5643 panel_simple_shutdown(&pdev->dev); 5644 } 5645 5646 static const struct dev_pm_ops panel_simple_pm_ops = { 5647 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 5648 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5649 pm_runtime_force_resume) 5650 }; 5651 5652 static struct platform_driver panel_simple_platform_driver = { 5653 .driver = { 5654 .name = "panel-simple", 5655 .of_match_table = platform_of_match, 5656 .pm = &panel_simple_pm_ops, 5657 }, 5658 .probe = panel_simple_platform_probe, 5659 .remove = panel_simple_platform_remove, 5660 .shutdown = panel_simple_platform_shutdown, 5661 }; 5662 5663 static const struct drm_display_mode auo_b080uan01_mode = { 5664 .clock = 154500, 5665 .hdisplay = 1200, 5666 .hsync_start = 1200 + 62, 5667 .hsync_end = 1200 + 62 + 4, 5668 .htotal = 1200 + 62 + 4 + 62, 5669 .vdisplay = 1920, 5670 .vsync_start = 1920 + 9, 5671 .vsync_end = 1920 + 9 + 2, 5672 .vtotal = 1920 + 9 + 2 + 8, 5673 }; 5674 5675 static const struct panel_desc_dsi auo_b080uan01 = { 5676 .desc = { 5677 .modes = &auo_b080uan01_mode, 5678 .num_modes = 1, 5679 .bpc = 8, 5680 .size = { 5681 .width = 108, 5682 .height = 272, 5683 }, 5684 .connector_type = DRM_MODE_CONNECTOR_DSI, 5685 }, 5686 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5687 .format = MIPI_DSI_FMT_RGB888, 5688 .lanes = 4, 5689 }; 5690 5691 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5692 .clock = 160000, 5693 .hdisplay = 1200, 5694 .hsync_start = 1200 + 120, 5695 .hsync_end = 1200 + 120 + 20, 5696 .htotal = 1200 + 120 + 20 + 21, 5697 .vdisplay = 1920, 5698 .vsync_start = 1920 + 21, 5699 .vsync_end = 1920 + 21 + 3, 5700 .vtotal = 1920 + 21 + 3 + 18, 5701 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5702 }; 5703 5704 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5705 .desc = { 5706 .modes = &boe_tv080wum_nl0_mode, 5707 .num_modes = 1, 5708 .size = { 5709 .width = 107, 5710 .height = 172, 5711 }, 5712 .connector_type = DRM_MODE_CONNECTOR_DSI, 5713 }, 5714 .flags = MIPI_DSI_MODE_VIDEO | 5715 MIPI_DSI_MODE_VIDEO_BURST | 5716 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5717 .format = MIPI_DSI_FMT_RGB888, 5718 .lanes = 4, 5719 }; 5720 5721 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5722 .clock = 67000, 5723 .hdisplay = 720, 5724 .hsync_start = 720 + 12, 5725 .hsync_end = 720 + 12 + 4, 5726 .htotal = 720 + 12 + 4 + 112, 5727 .vdisplay = 1280, 5728 .vsync_start = 1280 + 8, 5729 .vsync_end = 1280 + 8 + 4, 5730 .vtotal = 1280 + 8 + 4 + 12, 5731 }; 5732 5733 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5734 .desc = { 5735 .modes = &lg_lh500wx1_sd03_mode, 5736 .num_modes = 1, 5737 .bpc = 8, 5738 .size = { 5739 .width = 62, 5740 .height = 110, 5741 }, 5742 .connector_type = DRM_MODE_CONNECTOR_DSI, 5743 }, 5744 .flags = MIPI_DSI_MODE_VIDEO, 5745 .format = MIPI_DSI_FMT_RGB888, 5746 .lanes = 4, 5747 }; 5748 5749 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5750 .clock = 157200, 5751 .hdisplay = 1920, 5752 .hsync_start = 1920 + 154, 5753 .hsync_end = 1920 + 154 + 16, 5754 .htotal = 1920 + 154 + 16 + 32, 5755 .vdisplay = 1200, 5756 .vsync_start = 1200 + 17, 5757 .vsync_end = 1200 + 17 + 2, 5758 .vtotal = 1200 + 17 + 2 + 16, 5759 }; 5760 5761 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5762 .desc = { 5763 .modes = &panasonic_vvx10f004b00_mode, 5764 .num_modes = 1, 5765 .bpc = 8, 5766 .size = { 5767 .width = 217, 5768 .height = 136, 5769 }, 5770 .connector_type = DRM_MODE_CONNECTOR_DSI, 5771 }, 5772 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5773 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5774 .format = MIPI_DSI_FMT_RGB888, 5775 .lanes = 4, 5776 }; 5777 5778 static const struct drm_display_mode lg_acx467akm_7_mode = { 5779 .clock = 150000, 5780 .hdisplay = 1080, 5781 .hsync_start = 1080 + 2, 5782 .hsync_end = 1080 + 2 + 2, 5783 .htotal = 1080 + 2 + 2 + 2, 5784 .vdisplay = 1920, 5785 .vsync_start = 1920 + 2, 5786 .vsync_end = 1920 + 2 + 2, 5787 .vtotal = 1920 + 2 + 2 + 2, 5788 }; 5789 5790 static const struct panel_desc_dsi lg_acx467akm_7 = { 5791 .desc = { 5792 .modes = &lg_acx467akm_7_mode, 5793 .num_modes = 1, 5794 .bpc = 8, 5795 .size = { 5796 .width = 62, 5797 .height = 110, 5798 }, 5799 .connector_type = DRM_MODE_CONNECTOR_DSI, 5800 }, 5801 .flags = 0, 5802 .format = MIPI_DSI_FMT_RGB888, 5803 .lanes = 4, 5804 }; 5805 5806 static const struct drm_display_mode osd101t2045_53ts_mode = { 5807 .clock = 154500, 5808 .hdisplay = 1920, 5809 .hsync_start = 1920 + 112, 5810 .hsync_end = 1920 + 112 + 16, 5811 .htotal = 1920 + 112 + 16 + 32, 5812 .vdisplay = 1200, 5813 .vsync_start = 1200 + 16, 5814 .vsync_end = 1200 + 16 + 2, 5815 .vtotal = 1200 + 16 + 2 + 16, 5816 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5817 }; 5818 5819 static const struct panel_desc_dsi osd101t2045_53ts = { 5820 .desc = { 5821 .modes = &osd101t2045_53ts_mode, 5822 .num_modes = 1, 5823 .bpc = 8, 5824 .size = { 5825 .width = 217, 5826 .height = 136, 5827 }, 5828 .connector_type = DRM_MODE_CONNECTOR_DSI, 5829 }, 5830 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5831 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5832 MIPI_DSI_MODE_NO_EOT_PACKET, 5833 .format = MIPI_DSI_FMT_RGB888, 5834 .lanes = 4, 5835 }; 5836 5837 static const struct of_device_id dsi_of_match[] = { 5838 { 5839 .compatible = "auo,b080uan01", 5840 .data = &auo_b080uan01 5841 }, { 5842 .compatible = "boe,tv080wum-nl0", 5843 .data = &boe_tv080wum_nl0 5844 }, { 5845 .compatible = "lg,lh500wx1-sd03", 5846 .data = &lg_lh500wx1_sd03 5847 }, { 5848 .compatible = "panasonic,vvx10f004b00", 5849 .data = &panasonic_vvx10f004b00 5850 }, { 5851 .compatible = "lg,acx467akm-7", 5852 .data = &lg_acx467akm_7 5853 }, { 5854 .compatible = "osddisplays,osd101t2045-53ts", 5855 .data = &osd101t2045_53ts 5856 }, { 5857 /* sentinel */ 5858 } 5859 }; 5860 MODULE_DEVICE_TABLE(of, dsi_of_match); 5861 5862 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5863 { 5864 const struct panel_desc_dsi *desc; 5865 struct panel_simple *panel; 5866 int err; 5867 5868 panel = panel_simple_probe(&dsi->dev); 5869 if (IS_ERR(panel)) 5870 return PTR_ERR(panel); 5871 5872 desc = container_of(panel->desc, struct panel_desc_dsi, desc); 5873 dsi->mode_flags = desc->flags; 5874 dsi->format = desc->format; 5875 dsi->lanes = desc->lanes; 5876 5877 err = mipi_dsi_attach(dsi); 5878 if (err) { 5879 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5880 5881 drm_panel_remove(&panel->base); 5882 } 5883 5884 return err; 5885 } 5886 5887 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5888 { 5889 int err; 5890 5891 err = mipi_dsi_detach(dsi); 5892 if (err < 0) 5893 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5894 5895 panel_simple_remove(&dsi->dev); 5896 } 5897 5898 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5899 { 5900 panel_simple_shutdown(&dsi->dev); 5901 } 5902 5903 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5904 .driver = { 5905 .name = "panel-simple-dsi", 5906 .of_match_table = dsi_of_match, 5907 .pm = &panel_simple_pm_ops, 5908 }, 5909 .probe = panel_simple_dsi_probe, 5910 .remove = panel_simple_dsi_remove, 5911 .shutdown = panel_simple_dsi_shutdown, 5912 }; 5913 5914 static int __init panel_simple_init(void) 5915 { 5916 int err; 5917 5918 err = platform_driver_register(&panel_simple_platform_driver); 5919 if (err < 0) 5920 return err; 5921 5922 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5923 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5924 if (err < 0) 5925 goto err_did_platform_register; 5926 } 5927 5928 return 0; 5929 5930 err_did_platform_register: 5931 platform_driver_unregister(&panel_simple_platform_driver); 5932 5933 return err; 5934 } 5935 module_init(panel_simple_init); 5936 5937 static void __exit panel_simple_exit(void) 5938 { 5939 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5940 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5941 5942 platform_driver_unregister(&panel_simple_platform_driver); 5943 } 5944 module_exit(panel_simple_exit); 5945 5946 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5947 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5948 MODULE_LICENSE("GPL and additional rights"); 5949