1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_device.h> 30 #include <linux/of_platform.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/regulator/consumer.h> 34 35 #include <video/display_timing.h> 36 #include <video/of_display_timing.h> 37 #include <video/videomode.h> 38 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_device.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_mipi_dsi.h> 43 #include <drm/drm_panel.h> 44 #include <drm/drm_of.h> 45 46 /** 47 * struct panel_desc - Describes a simple panel. 48 */ 49 struct panel_desc { 50 /** 51 * @modes: Pointer to array of fixed modes appropriate for this panel. 52 * 53 * If only one mode then this can just be the address of the mode. 54 * NOTE: cannot be used with "timings" and also if this is specified 55 * then you cannot override the mode in the device tree. 56 */ 57 const struct drm_display_mode *modes; 58 59 /** @num_modes: Number of elements in modes array. */ 60 unsigned int num_modes; 61 62 /** 63 * @timings: Pointer to array of display timings 64 * 65 * NOTE: cannot be used with "modes" and also these will be used to 66 * validate a device tree override if one is present. 67 */ 68 const struct display_timing *timings; 69 70 /** @num_timings: Number of elements in timings array. */ 71 unsigned int num_timings; 72 73 /** @bpc: Bits per color. */ 74 unsigned int bpc; 75 76 /** @size: Structure containing the physical size of this panel. */ 77 struct { 78 /** 79 * @size.width: Width (in mm) of the active display area. 80 */ 81 unsigned int width; 82 83 /** 84 * @size.height: Height (in mm) of the active display area. 85 */ 86 unsigned int height; 87 } size; 88 89 /** @delay: Structure containing various delay values for this panel. */ 90 struct { 91 /** 92 * @delay.prepare: Time for the panel to become ready. 93 * 94 * The time (in milliseconds) that it takes for the panel to 95 * become ready and start receiving video data 96 */ 97 unsigned int prepare; 98 99 /** 100 * @delay.enable: Time for the panel to display a valid frame. 101 * 102 * The time (in milliseconds) that it takes for the panel to 103 * display the first valid frame after starting to receive 104 * video data. 105 */ 106 unsigned int enable; 107 108 /** 109 * @delay.disable: Time for the panel to turn the display off. 110 * 111 * The time (in milliseconds) that it takes for the panel to 112 * turn the display off (no content is visible). 113 */ 114 unsigned int disable; 115 116 /** 117 * @delay.unprepare: Time to power down completely. 118 * 119 * The time (in milliseconds) that it takes for the panel 120 * to power itself down completely. 121 * 122 * This time is used to prevent a future "prepare" from 123 * starting until at least this many milliseconds has passed. 124 * If at prepare time less time has passed since unprepare 125 * finished, the driver waits for the remaining time. 126 */ 127 unsigned int unprepare; 128 } delay; 129 130 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 131 u32 bus_format; 132 133 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 134 u32 bus_flags; 135 136 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 137 int connector_type; 138 }; 139 140 struct panel_desc_dsi { 141 struct panel_desc desc; 142 143 unsigned long flags; 144 enum mipi_dsi_pixel_format format; 145 unsigned int lanes; 146 }; 147 148 struct panel_simple { 149 struct drm_panel base; 150 151 ktime_t unprepared_time; 152 153 const struct panel_desc *desc; 154 155 struct regulator *supply; 156 struct i2c_adapter *ddc; 157 158 struct gpio_desc *enable_gpio; 159 160 const struct drm_edid *drm_edid; 161 162 struct drm_display_mode override_mode; 163 164 enum drm_panel_orientation orientation; 165 }; 166 167 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 168 { 169 return container_of(panel, struct panel_simple, base); 170 } 171 172 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 173 struct drm_connector *connector) 174 { 175 struct drm_display_mode *mode; 176 unsigned int i, num = 0; 177 178 for (i = 0; i < panel->desc->num_timings; i++) { 179 const struct display_timing *dt = &panel->desc->timings[i]; 180 struct videomode vm; 181 182 videomode_from_timing(dt, &vm); 183 mode = drm_mode_create(connector->dev); 184 if (!mode) { 185 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 186 dt->hactive.typ, dt->vactive.typ); 187 continue; 188 } 189 190 drm_display_mode_from_videomode(&vm, mode); 191 192 mode->type |= DRM_MODE_TYPE_DRIVER; 193 194 if (panel->desc->num_timings == 1) 195 mode->type |= DRM_MODE_TYPE_PREFERRED; 196 197 drm_mode_probed_add(connector, mode); 198 num++; 199 } 200 201 return num; 202 } 203 204 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 205 struct drm_connector *connector) 206 { 207 struct drm_display_mode *mode; 208 unsigned int i, num = 0; 209 210 for (i = 0; i < panel->desc->num_modes; i++) { 211 const struct drm_display_mode *m = &panel->desc->modes[i]; 212 213 mode = drm_mode_duplicate(connector->dev, m); 214 if (!mode) { 215 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 216 m->hdisplay, m->vdisplay, 217 drm_mode_vrefresh(m)); 218 continue; 219 } 220 221 mode->type |= DRM_MODE_TYPE_DRIVER; 222 223 if (panel->desc->num_modes == 1) 224 mode->type |= DRM_MODE_TYPE_PREFERRED; 225 226 drm_mode_set_name(mode); 227 228 drm_mode_probed_add(connector, mode); 229 num++; 230 } 231 232 return num; 233 } 234 235 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 236 struct drm_connector *connector) 237 { 238 struct drm_display_mode *mode; 239 bool has_override = panel->override_mode.type; 240 unsigned int num = 0; 241 242 if (!panel->desc) 243 return 0; 244 245 if (has_override) { 246 mode = drm_mode_duplicate(connector->dev, 247 &panel->override_mode); 248 if (mode) { 249 drm_mode_probed_add(connector, mode); 250 num = 1; 251 } else { 252 dev_err(panel->base.dev, "failed to add override mode\n"); 253 } 254 } 255 256 /* Only add timings if override was not there or failed to validate */ 257 if (num == 0 && panel->desc->num_timings) 258 num = panel_simple_get_timings_modes(panel, connector); 259 260 /* 261 * Only add fixed modes if timings/override added no mode. 262 * 263 * We should only ever have either the display timings specified 264 * or a fixed mode. Anything else is rather bogus. 265 */ 266 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 267 if (num == 0) 268 num = panel_simple_get_display_modes(panel, connector); 269 270 connector->display_info.bpc = panel->desc->bpc; 271 connector->display_info.width_mm = panel->desc->size.width; 272 connector->display_info.height_mm = panel->desc->size.height; 273 if (panel->desc->bus_format) 274 drm_display_info_set_bus_formats(&connector->display_info, 275 &panel->desc->bus_format, 1); 276 connector->display_info.bus_flags = panel->desc->bus_flags; 277 278 return num; 279 } 280 281 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 282 { 283 ktime_t now_ktime, min_ktime; 284 285 if (!min_ms) 286 return; 287 288 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 289 now_ktime = ktime_get_boottime(); 290 291 if (ktime_before(now_ktime, min_ktime)) 292 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 293 } 294 295 static int panel_simple_disable(struct drm_panel *panel) 296 { 297 struct panel_simple *p = to_panel_simple(panel); 298 299 if (p->desc->delay.disable) 300 msleep(p->desc->delay.disable); 301 302 return 0; 303 } 304 305 static int panel_simple_suspend(struct device *dev) 306 { 307 struct panel_simple *p = dev_get_drvdata(dev); 308 309 gpiod_set_value_cansleep(p->enable_gpio, 0); 310 regulator_disable(p->supply); 311 p->unprepared_time = ktime_get_boottime(); 312 313 drm_edid_free(p->drm_edid); 314 p->drm_edid = NULL; 315 316 return 0; 317 } 318 319 static int panel_simple_unprepare(struct drm_panel *panel) 320 { 321 int ret; 322 323 pm_runtime_mark_last_busy(panel->dev); 324 ret = pm_runtime_put_autosuspend(panel->dev); 325 if (ret < 0) 326 return ret; 327 328 return 0; 329 } 330 331 static int panel_simple_resume(struct device *dev) 332 { 333 struct panel_simple *p = dev_get_drvdata(dev); 334 int err; 335 336 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 337 338 err = regulator_enable(p->supply); 339 if (err < 0) { 340 dev_err(dev, "failed to enable supply: %d\n", err); 341 return err; 342 } 343 344 gpiod_set_value_cansleep(p->enable_gpio, 1); 345 346 if (p->desc->delay.prepare) 347 msleep(p->desc->delay.prepare); 348 349 return 0; 350 } 351 352 static int panel_simple_prepare(struct drm_panel *panel) 353 { 354 int ret; 355 356 ret = pm_runtime_get_sync(panel->dev); 357 if (ret < 0) { 358 pm_runtime_put_autosuspend(panel->dev); 359 return ret; 360 } 361 362 return 0; 363 } 364 365 static int panel_simple_enable(struct drm_panel *panel) 366 { 367 struct panel_simple *p = to_panel_simple(panel); 368 369 if (p->desc->delay.enable) 370 msleep(p->desc->delay.enable); 371 372 return 0; 373 } 374 375 static int panel_simple_get_modes(struct drm_panel *panel, 376 struct drm_connector *connector) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 int num = 0; 380 381 /* probe EDID if a DDC bus is available */ 382 if (p->ddc) { 383 pm_runtime_get_sync(panel->dev); 384 385 if (!p->drm_edid) 386 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 387 388 drm_edid_connector_update(connector, p->drm_edid); 389 390 num += drm_edid_connector_add_modes(connector); 391 392 pm_runtime_mark_last_busy(panel->dev); 393 pm_runtime_put_autosuspend(panel->dev); 394 } 395 396 /* add hard-coded panel modes */ 397 num += panel_simple_get_non_edid_modes(p, connector); 398 399 /* 400 * TODO: Remove once all drm drivers call 401 * drm_connector_set_orientation_from_panel() 402 */ 403 drm_connector_set_panel_orientation(connector, p->orientation); 404 405 return num; 406 } 407 408 static int panel_simple_get_timings(struct drm_panel *panel, 409 unsigned int num_timings, 410 struct display_timing *timings) 411 { 412 struct panel_simple *p = to_panel_simple(panel); 413 unsigned int i; 414 415 if (p->desc->num_timings < num_timings) 416 num_timings = p->desc->num_timings; 417 418 if (timings) 419 for (i = 0; i < num_timings; i++) 420 timings[i] = p->desc->timings[i]; 421 422 return p->desc->num_timings; 423 } 424 425 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 426 { 427 struct panel_simple *p = to_panel_simple(panel); 428 429 return p->orientation; 430 } 431 432 static const struct drm_panel_funcs panel_simple_funcs = { 433 .disable = panel_simple_disable, 434 .unprepare = panel_simple_unprepare, 435 .prepare = panel_simple_prepare, 436 .enable = panel_simple_enable, 437 .get_modes = panel_simple_get_modes, 438 .get_orientation = panel_simple_get_orientation, 439 .get_timings = panel_simple_get_timings, 440 }; 441 442 static struct panel_desc *panel_dpi_probe(struct device *dev) 443 { 444 struct display_timing *timing; 445 const struct device_node *np; 446 struct panel_desc *desc; 447 unsigned int bus_flags; 448 struct videomode vm; 449 int ret; 450 451 np = dev->of_node; 452 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 453 if (!desc) 454 return ERR_PTR(-ENOMEM); 455 456 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 457 if (!timing) 458 return ERR_PTR(-ENOMEM); 459 460 ret = of_get_display_timing(np, "panel-timing", timing); 461 if (ret < 0) { 462 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 463 np); 464 return ERR_PTR(ret); 465 } 466 467 desc->timings = timing; 468 desc->num_timings = 1; 469 470 of_property_read_u32(np, "width-mm", &desc->size.width); 471 of_property_read_u32(np, "height-mm", &desc->size.height); 472 473 /* Extract bus_flags from display_timing */ 474 bus_flags = 0; 475 vm.flags = timing->flags; 476 drm_bus_flags_from_videomode(&vm, &bus_flags); 477 desc->bus_flags = bus_flags; 478 479 /* We do not know the connector for the DT node, so guess it */ 480 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 481 482 return desc; 483 } 484 485 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 486 (to_check->field.typ >= bounds->field.min && \ 487 to_check->field.typ <= bounds->field.max) 488 static void panel_simple_parse_panel_timing_node(struct device *dev, 489 struct panel_simple *panel, 490 const struct display_timing *ot) 491 { 492 const struct panel_desc *desc = panel->desc; 493 struct videomode vm; 494 unsigned int i; 495 496 if (WARN_ON(desc->num_modes)) { 497 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 498 return; 499 } 500 if (WARN_ON(!desc->num_timings)) { 501 dev_err(dev, "Reject override mode: no timings specified\n"); 502 return; 503 } 504 505 for (i = 0; i < panel->desc->num_timings; i++) { 506 const struct display_timing *dt = &panel->desc->timings[i]; 507 508 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 512 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 513 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 514 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 515 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 516 continue; 517 518 if (ot->flags != dt->flags) 519 continue; 520 521 videomode_from_timing(ot, &vm); 522 drm_display_mode_from_videomode(&vm, &panel->override_mode); 523 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 524 DRM_MODE_TYPE_PREFERRED; 525 break; 526 } 527 528 if (WARN_ON(!panel->override_mode.type)) 529 dev_err(dev, "Reject override mode: No display_timing found\n"); 530 } 531 532 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 533 struct panel_simple *panel) 534 { 535 int ret, bpc; 536 537 ret = drm_of_lvds_get_data_mapping(dev->of_node); 538 if (ret < 0) { 539 if (ret == -EINVAL) 540 dev_warn(dev, "Ignore invalid data-mapping property\n"); 541 542 /* 543 * Ignore non-existing or malformatted property, fallback to 544 * default data-mapping, and return 0. 545 */ 546 return 0; 547 } 548 549 switch (ret) { 550 default: 551 WARN_ON(1); 552 fallthrough; 553 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 554 fallthrough; 555 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 556 bpc = 8; 557 break; 558 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 559 bpc = 6; 560 } 561 562 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 563 struct panel_desc *override_desc; 564 565 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 566 if (!override_desc) 567 return -ENOMEM; 568 569 override_desc->bus_format = ret; 570 override_desc->bpc = bpc; 571 panel->desc = override_desc; 572 } 573 574 return 0; 575 } 576 577 static const struct panel_desc *panel_simple_get_desc(struct device *dev) 578 { 579 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI) && 580 dev_is_mipi_dsi(dev)) { 581 const struct panel_desc_dsi *dsi_desc; 582 583 dsi_desc = of_device_get_match_data(dev); 584 if (!dsi_desc) 585 return ERR_PTR(-ENODEV); 586 587 return &dsi_desc->desc; 588 } 589 590 if (dev_is_platform(dev)) { 591 const struct panel_desc *desc; 592 593 desc = of_device_get_match_data(dev); 594 if (!desc) { 595 /* 596 * panel-dpi probes without a descriptor and 597 * panel_dpi_probe() will initialize one for us 598 * based on the device tree. 599 */ 600 if (of_device_is_compatible(dev->of_node, "panel-dpi")) 601 return panel_dpi_probe(dev); 602 else 603 return ERR_PTR(-ENODEV); 604 } 605 606 return desc; 607 } 608 609 return ERR_PTR(-ENODEV); 610 } 611 612 static struct panel_simple *panel_simple_probe(struct device *dev) 613 { 614 const struct panel_desc *desc; 615 struct panel_simple *panel; 616 struct display_timing dt; 617 struct device_node *ddc; 618 int connector_type; 619 u32 bus_flags; 620 int err; 621 622 desc = panel_simple_get_desc(dev); 623 if (IS_ERR(desc)) 624 return ERR_CAST(desc); 625 626 connector_type = desc->connector_type; 627 /* Catch common mistakes for panels. */ 628 switch (connector_type) { 629 case 0: 630 dev_warn(dev, "Specify missing connector_type\n"); 631 connector_type = DRM_MODE_CONNECTOR_DPI; 632 break; 633 case DRM_MODE_CONNECTOR_LVDS: 634 WARN_ON(desc->bus_flags & 635 ~(DRM_BUS_FLAG_DE_LOW | 636 DRM_BUS_FLAG_DE_HIGH | 637 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 638 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 639 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 640 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 641 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 642 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 643 desc->bpc != 6); 644 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 645 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 646 desc->bpc != 8); 647 break; 648 case DRM_MODE_CONNECTOR_eDP: 649 dev_warn(dev, "eDP panels moved to panel-edp\n"); 650 return ERR_PTR(-EINVAL); 651 case DRM_MODE_CONNECTOR_DSI: 652 if (desc->bpc != 6 && desc->bpc != 8) 653 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 654 break; 655 case DRM_MODE_CONNECTOR_DPI: 656 bus_flags = DRM_BUS_FLAG_DE_LOW | 657 DRM_BUS_FLAG_DE_HIGH | 658 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 659 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 660 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 661 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 662 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 663 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 664 if (desc->bus_flags & ~bus_flags) 665 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 666 if (!(desc->bus_flags & bus_flags)) 667 dev_warn(dev, "Specify missing bus_flags\n"); 668 if (desc->bus_format == 0) 669 dev_warn(dev, "Specify missing bus_format\n"); 670 if (desc->bpc != 6 && desc->bpc != 8) 671 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 672 break; 673 default: 674 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 675 connector_type = DRM_MODE_CONNECTOR_DPI; 676 break; 677 } 678 679 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 680 &panel_simple_funcs, connector_type); 681 if (IS_ERR(panel)) 682 return ERR_CAST(panel); 683 684 panel->desc = desc; 685 686 panel->supply = devm_regulator_get(dev, "power"); 687 if (IS_ERR(panel->supply)) 688 return ERR_CAST(panel->supply); 689 690 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 691 GPIOD_OUT_LOW); 692 if (IS_ERR(panel->enable_gpio)) 693 return dev_err_cast_probe(dev, panel->enable_gpio, 694 "failed to request GPIO\n"); 695 696 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 697 if (err) { 698 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 699 return ERR_PTR(err); 700 } 701 702 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 703 if (ddc) { 704 panel->ddc = of_find_i2c_adapter_by_node(ddc); 705 of_node_put(ddc); 706 707 if (!panel->ddc) 708 return ERR_PTR(-EPROBE_DEFER); 709 } 710 711 if (!of_device_is_compatible(dev->of_node, "panel-dpi") && 712 !of_get_display_timing(dev->of_node, "panel-timing", &dt)) 713 panel_simple_parse_panel_timing_node(dev, panel, &dt); 714 715 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 716 /* Optional data-mapping property for overriding bus format */ 717 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 718 if (err) 719 goto free_ddc; 720 } 721 722 dev_set_drvdata(dev, panel); 723 724 /* 725 * We use runtime PM for prepare / unprepare since those power the panel 726 * on and off and those can be very slow operations. This is important 727 * to optimize powering the panel on briefly to read the EDID before 728 * fully enabling the panel. 729 */ 730 pm_runtime_enable(dev); 731 pm_runtime_set_autosuspend_delay(dev, 1000); 732 pm_runtime_use_autosuspend(dev); 733 734 err = drm_panel_of_backlight(&panel->base); 735 if (err) { 736 dev_err_probe(dev, err, "Could not find backlight\n"); 737 goto disable_pm_runtime; 738 } 739 740 drm_panel_add(&panel->base); 741 742 return panel; 743 744 disable_pm_runtime: 745 pm_runtime_dont_use_autosuspend(dev); 746 pm_runtime_disable(dev); 747 free_ddc: 748 if (panel->ddc) 749 put_device(&panel->ddc->dev); 750 751 return ERR_PTR(err); 752 } 753 754 static void panel_simple_shutdown(struct device *dev) 755 { 756 struct panel_simple *panel = dev_get_drvdata(dev); 757 758 /* 759 * NOTE: the following two calls don't really belong here. It is the 760 * responsibility of a correctly written DRM modeset driver to call 761 * drm_atomic_helper_shutdown() at shutdown time and that should 762 * cause the panel to be disabled / unprepared if needed. For now, 763 * however, we'll keep these calls due to the sheer number of 764 * different DRM modeset drivers used with panel-simple. Once we've 765 * confirmed that all DRM modeset drivers using this panel properly 766 * call drm_atomic_helper_shutdown() we can simply delete the two 767 * calls below. 768 * 769 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 770 * PANEL DRIVERS. 771 * 772 * FIXME: If we're still haven't figured out if all DRM modeset 773 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 774 * managed to make sure that DRM modeset drivers get their shutdown() 775 * callback before the panel's shutdown() callback (perhaps using 776 * device link), we could add a WARN_ON here to help move forward. 777 */ 778 if (panel->base.enabled) 779 drm_panel_disable(&panel->base); 780 if (panel->base.prepared) 781 drm_panel_unprepare(&panel->base); 782 } 783 784 static void panel_simple_remove(struct device *dev) 785 { 786 struct panel_simple *panel = dev_get_drvdata(dev); 787 788 drm_panel_remove(&panel->base); 789 panel_simple_shutdown(dev); 790 791 pm_runtime_dont_use_autosuspend(dev); 792 pm_runtime_disable(dev); 793 if (panel->ddc) 794 put_device(&panel->ddc->dev); 795 } 796 797 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 798 .clock = 71100, 799 .hdisplay = 1280, 800 .hsync_start = 1280 + 40, 801 .hsync_end = 1280 + 40 + 80, 802 .htotal = 1280 + 40 + 80 + 40, 803 .vdisplay = 800, 804 .vsync_start = 800 + 3, 805 .vsync_end = 800 + 3 + 10, 806 .vtotal = 800 + 3 + 10 + 10, 807 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 808 }; 809 810 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 811 .modes = &ire_am_1280800n3tzqw_t00h_mode, 812 .num_modes = 1, 813 .bpc = 8, 814 .size = { 815 .width = 217, 816 .height = 136, 817 }, 818 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 819 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 820 .connector_type = DRM_MODE_CONNECTOR_LVDS, 821 }; 822 823 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 824 .clock = 9000, 825 .hdisplay = 480, 826 .hsync_start = 480 + 2, 827 .hsync_end = 480 + 2 + 41, 828 .htotal = 480 + 2 + 41 + 2, 829 .vdisplay = 272, 830 .vsync_start = 272 + 2, 831 .vsync_end = 272 + 2 + 10, 832 .vtotal = 272 + 2 + 10 + 2, 833 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 834 }; 835 836 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 837 .modes = &ire_am_480272h3tmqw_t01h_mode, 838 .num_modes = 1, 839 .bpc = 8, 840 .size = { 841 .width = 99, 842 .height = 58, 843 }, 844 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 845 }; 846 847 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 848 .clock = 33333, 849 .hdisplay = 800, 850 .hsync_start = 800 + 0, 851 .hsync_end = 800 + 0 + 255, 852 .htotal = 800 + 0 + 255 + 0, 853 .vdisplay = 480, 854 .vsync_start = 480 + 2, 855 .vsync_end = 480 + 2 + 45, 856 .vtotal = 480 + 2 + 45 + 0, 857 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 858 }; 859 860 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 861 .pixelclock = { 29930000, 33260000, 36590000 }, 862 .hactive = { 800, 800, 800 }, 863 .hfront_porch = { 1, 40, 168 }, 864 .hback_porch = { 88, 88, 88 }, 865 .hsync_len = { 1, 128, 128 }, 866 .vactive = { 480, 480, 480 }, 867 .vfront_porch = { 1, 35, 37 }, 868 .vback_porch = { 8, 8, 8 }, 869 .vsync_len = { 1, 2, 2 }, 870 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 871 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 872 DISPLAY_FLAGS_SYNC_POSEDGE, 873 }; 874 875 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 876 .timings = &ire_am_800480l1tmqw_t00h_timing, 877 .num_timings = 1, 878 .bpc = 8, 879 .size = { 880 .width = 111, 881 .height = 67, 882 }, 883 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 884 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 885 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 886 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 887 .connector_type = DRM_MODE_CONNECTOR_DPI, 888 }; 889 890 static const struct panel_desc ampire_am800480r3tmqwa1h = { 891 .modes = &ire_am800480r3tmqwa1h_mode, 892 .num_modes = 1, 893 .bpc = 6, 894 .size = { 895 .width = 152, 896 .height = 91, 897 }, 898 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 899 }; 900 901 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 902 .pixelclock = { 34500000, 39600000, 50400000 }, 903 .hactive = { 800, 800, 800 }, 904 .hfront_porch = { 12, 112, 312 }, 905 .hback_porch = { 87, 87, 48 }, 906 .hsync_len = { 1, 1, 40 }, 907 .vactive = { 600, 600, 600 }, 908 .vfront_porch = { 1, 21, 61 }, 909 .vback_porch = { 38, 38, 19 }, 910 .vsync_len = { 1, 1, 20 }, 911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 913 DISPLAY_FLAGS_SYNC_POSEDGE, 914 }; 915 916 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 917 .timings = &ire_am800600p5tmqw_tb8h_timing, 918 .num_timings = 1, 919 .bpc = 6, 920 .size = { 921 .width = 162, 922 .height = 122, 923 }, 924 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 925 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 926 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 927 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 928 .connector_type = DRM_MODE_CONNECTOR_DPI, 929 }; 930 931 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 932 .pixelclock = { 26400000, 33300000, 46800000 }, 933 .hactive = { 800, 800, 800 }, 934 .hfront_porch = { 16, 210, 354 }, 935 .hback_porch = { 45, 36, 6 }, 936 .hsync_len = { 1, 10, 40 }, 937 .vactive = { 480, 480, 480 }, 938 .vfront_porch = { 7, 22, 147 }, 939 .vback_porch = { 22, 13, 3 }, 940 .vsync_len = { 1, 10, 20 }, 941 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 942 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 943 }; 944 945 static const struct panel_desc armadeus_st0700_adapt = { 946 .timings = &santek_st0700i5y_rbslw_f_timing, 947 .num_timings = 1, 948 .bpc = 6, 949 .size = { 950 .width = 154, 951 .height = 86, 952 }, 953 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 954 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 955 }; 956 957 static const struct drm_display_mode auo_b101aw03_mode = { 958 .clock = 51450, 959 .hdisplay = 1024, 960 .hsync_start = 1024 + 156, 961 .hsync_end = 1024 + 156 + 8, 962 .htotal = 1024 + 156 + 8 + 156, 963 .vdisplay = 600, 964 .vsync_start = 600 + 16, 965 .vsync_end = 600 + 16 + 6, 966 .vtotal = 600 + 16 + 6 + 16, 967 }; 968 969 static const struct panel_desc auo_b101aw03 = { 970 .modes = &auo_b101aw03_mode, 971 .num_modes = 1, 972 .bpc = 6, 973 .size = { 974 .width = 223, 975 .height = 125, 976 }, 977 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 978 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 979 .connector_type = DRM_MODE_CONNECTOR_LVDS, 980 }; 981 982 static const struct drm_display_mode auo_b101xtn01_mode = { 983 .clock = 72000, 984 .hdisplay = 1366, 985 .hsync_start = 1366 + 20, 986 .hsync_end = 1366 + 20 + 70, 987 .htotal = 1366 + 20 + 70, 988 .vdisplay = 768, 989 .vsync_start = 768 + 14, 990 .vsync_end = 768 + 14 + 42, 991 .vtotal = 768 + 14 + 42, 992 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 993 }; 994 995 static const struct panel_desc auo_b101xtn01 = { 996 .modes = &auo_b101xtn01_mode, 997 .num_modes = 1, 998 .bpc = 6, 999 .size = { 1000 .width = 223, 1001 .height = 125, 1002 }, 1003 }; 1004 1005 static const struct drm_display_mode auo_b116xw03_mode = { 1006 .clock = 70589, 1007 .hdisplay = 1366, 1008 .hsync_start = 1366 + 40, 1009 .hsync_end = 1366 + 40 + 40, 1010 .htotal = 1366 + 40 + 40 + 32, 1011 .vdisplay = 768, 1012 .vsync_start = 768 + 10, 1013 .vsync_end = 768 + 10 + 12, 1014 .vtotal = 768 + 10 + 12 + 6, 1015 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1016 }; 1017 1018 static const struct panel_desc auo_b116xw03 = { 1019 .modes = &auo_b116xw03_mode, 1020 .num_modes = 1, 1021 .bpc = 6, 1022 .size = { 1023 .width = 256, 1024 .height = 144, 1025 }, 1026 .delay = { 1027 .prepare = 1, 1028 .enable = 200, 1029 .disable = 200, 1030 .unprepare = 500, 1031 }, 1032 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1033 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1034 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1035 }; 1036 1037 static const struct display_timing auo_g070vvn01_timings = { 1038 .pixelclock = { 33300000, 34209000, 45000000 }, 1039 .hactive = { 800, 800, 800 }, 1040 .hfront_porch = { 20, 40, 200 }, 1041 .hback_porch = { 87, 40, 1 }, 1042 .hsync_len = { 1, 48, 87 }, 1043 .vactive = { 480, 480, 480 }, 1044 .vfront_porch = { 5, 13, 200 }, 1045 .vback_porch = { 31, 31, 29 }, 1046 .vsync_len = { 1, 1, 3 }, 1047 }; 1048 1049 static const struct panel_desc auo_g070vvn01 = { 1050 .timings = &auo_g070vvn01_timings, 1051 .num_timings = 1, 1052 .bpc = 8, 1053 .size = { 1054 .width = 152, 1055 .height = 91, 1056 }, 1057 .delay = { 1058 .prepare = 200, 1059 .enable = 50, 1060 .disable = 50, 1061 .unprepare = 1000, 1062 }, 1063 }; 1064 1065 static const struct display_timing auo_g101evn010_timing = { 1066 .pixelclock = { 64000000, 68930000, 85000000 }, 1067 .hactive = { 1280, 1280, 1280 }, 1068 .hfront_porch = { 8, 64, 256 }, 1069 .hback_porch = { 8, 64, 256 }, 1070 .hsync_len = { 40, 168, 767 }, 1071 .vactive = { 800, 800, 800 }, 1072 .vfront_porch = { 4, 8, 100 }, 1073 .vback_porch = { 4, 8, 100 }, 1074 .vsync_len = { 8, 16, 223 }, 1075 }; 1076 1077 static const struct panel_desc auo_g101evn010 = { 1078 .timings = &auo_g101evn010_timing, 1079 .num_timings = 1, 1080 .bpc = 6, 1081 .size = { 1082 .width = 216, 1083 .height = 135, 1084 }, 1085 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1086 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1087 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1088 }; 1089 1090 static const struct drm_display_mode auo_g104sn02_mode = { 1091 .clock = 40000, 1092 .hdisplay = 800, 1093 .hsync_start = 800 + 40, 1094 .hsync_end = 800 + 40 + 216, 1095 .htotal = 800 + 40 + 216 + 128, 1096 .vdisplay = 600, 1097 .vsync_start = 600 + 10, 1098 .vsync_end = 600 + 10 + 35, 1099 .vtotal = 600 + 10 + 35 + 2, 1100 }; 1101 1102 static const struct panel_desc auo_g104sn02 = { 1103 .modes = &auo_g104sn02_mode, 1104 .num_modes = 1, 1105 .bpc = 8, 1106 .size = { 1107 .width = 211, 1108 .height = 158, 1109 }, 1110 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1111 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1112 }; 1113 1114 static const struct drm_display_mode auo_g104stn01_mode = { 1115 .clock = 40000, 1116 .hdisplay = 800, 1117 .hsync_start = 800 + 40, 1118 .hsync_end = 800 + 40 + 88, 1119 .htotal = 800 + 40 + 88 + 128, 1120 .vdisplay = 600, 1121 .vsync_start = 600 + 1, 1122 .vsync_end = 600 + 1 + 23, 1123 .vtotal = 600 + 1 + 23 + 4, 1124 }; 1125 1126 static const struct panel_desc auo_g104stn01 = { 1127 .modes = &auo_g104stn01_mode, 1128 .num_modes = 1, 1129 .bpc = 8, 1130 .size = { 1131 .width = 211, 1132 .height = 158, 1133 }, 1134 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1135 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1136 }; 1137 1138 static const struct display_timing auo_g121ean01_timing = { 1139 .pixelclock = { 60000000, 74400000, 90000000 }, 1140 .hactive = { 1280, 1280, 1280 }, 1141 .hfront_porch = { 20, 50, 100 }, 1142 .hback_porch = { 20, 50, 100 }, 1143 .hsync_len = { 30, 100, 200 }, 1144 .vactive = { 800, 800, 800 }, 1145 .vfront_porch = { 2, 10, 25 }, 1146 .vback_porch = { 2, 10, 25 }, 1147 .vsync_len = { 4, 18, 50 }, 1148 }; 1149 1150 static const struct panel_desc auo_g121ean01 = { 1151 .timings = &auo_g121ean01_timing, 1152 .num_timings = 1, 1153 .bpc = 8, 1154 .size = { 1155 .width = 261, 1156 .height = 163, 1157 }, 1158 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1159 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1160 }; 1161 1162 static const struct display_timing auo_g133han01_timings = { 1163 .pixelclock = { 134000000, 141200000, 149000000 }, 1164 .hactive = { 1920, 1920, 1920 }, 1165 .hfront_porch = { 39, 58, 77 }, 1166 .hback_porch = { 59, 88, 117 }, 1167 .hsync_len = { 28, 42, 56 }, 1168 .vactive = { 1080, 1080, 1080 }, 1169 .vfront_porch = { 3, 8, 11 }, 1170 .vback_porch = { 5, 14, 19 }, 1171 .vsync_len = { 4, 14, 19 }, 1172 }; 1173 1174 static const struct panel_desc auo_g133han01 = { 1175 .timings = &auo_g133han01_timings, 1176 .num_timings = 1, 1177 .bpc = 8, 1178 .size = { 1179 .width = 293, 1180 .height = 165, 1181 }, 1182 .delay = { 1183 .prepare = 200, 1184 .enable = 50, 1185 .disable = 50, 1186 .unprepare = 1000, 1187 }, 1188 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1189 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1190 }; 1191 1192 static const struct display_timing auo_g156han04_timings = { 1193 .pixelclock = { 137000000, 141000000, 146000000 }, 1194 .hactive = { 1920, 1920, 1920 }, 1195 .hfront_porch = { 60, 60, 60 }, 1196 .hback_porch = { 90, 92, 111 }, 1197 .hsync_len = { 32, 32, 32 }, 1198 .vactive = { 1080, 1080, 1080 }, 1199 .vfront_porch = { 12, 12, 12 }, 1200 .vback_porch = { 24, 36, 56 }, 1201 .vsync_len = { 8, 8, 8 }, 1202 }; 1203 1204 static const struct panel_desc auo_g156han04 = { 1205 .timings = &auo_g156han04_timings, 1206 .num_timings = 1, 1207 .bpc = 8, 1208 .size = { 1209 .width = 344, 1210 .height = 194, 1211 }, 1212 .delay = { 1213 .prepare = 50, /* T2 */ 1214 .enable = 200, /* T3 */ 1215 .disable = 110, /* T10 */ 1216 .unprepare = 1000, /* T13 */ 1217 }, 1218 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1219 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1220 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1221 }; 1222 1223 static const struct drm_display_mode auo_g156xtn01_mode = { 1224 .clock = 76000, 1225 .hdisplay = 1366, 1226 .hsync_start = 1366 + 33, 1227 .hsync_end = 1366 + 33 + 67, 1228 .htotal = 1560, 1229 .vdisplay = 768, 1230 .vsync_start = 768 + 4, 1231 .vsync_end = 768 + 4 + 4, 1232 .vtotal = 806, 1233 }; 1234 1235 static const struct panel_desc auo_g156xtn01 = { 1236 .modes = &auo_g156xtn01_mode, 1237 .num_modes = 1, 1238 .bpc = 8, 1239 .size = { 1240 .width = 344, 1241 .height = 194, 1242 }, 1243 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1244 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1245 }; 1246 1247 static const struct display_timing auo_g185han01_timings = { 1248 .pixelclock = { 120000000, 144000000, 175000000 }, 1249 .hactive = { 1920, 1920, 1920 }, 1250 .hfront_porch = { 36, 120, 148 }, 1251 .hback_porch = { 24, 88, 108 }, 1252 .hsync_len = { 20, 48, 64 }, 1253 .vactive = { 1080, 1080, 1080 }, 1254 .vfront_porch = { 6, 10, 40 }, 1255 .vback_porch = { 2, 5, 20 }, 1256 .vsync_len = { 2, 5, 20 }, 1257 }; 1258 1259 static const struct panel_desc auo_g185han01 = { 1260 .timings = &auo_g185han01_timings, 1261 .num_timings = 1, 1262 .bpc = 8, 1263 .size = { 1264 .width = 409, 1265 .height = 230, 1266 }, 1267 .delay = { 1268 .prepare = 50, 1269 .enable = 200, 1270 .disable = 110, 1271 .unprepare = 1000, 1272 }, 1273 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1274 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1275 }; 1276 1277 static const struct display_timing auo_g190ean01_timings = { 1278 .pixelclock = { 90000000, 108000000, 135000000 }, 1279 .hactive = { 1280, 1280, 1280 }, 1280 .hfront_porch = { 126, 184, 1266 }, 1281 .hback_porch = { 84, 122, 844 }, 1282 .hsync_len = { 70, 102, 704 }, 1283 .vactive = { 1024, 1024, 1024 }, 1284 .vfront_porch = { 4, 26, 76 }, 1285 .vback_porch = { 2, 8, 25 }, 1286 .vsync_len = { 2, 8, 25 }, 1287 }; 1288 1289 static const struct panel_desc auo_g190ean01 = { 1290 .timings = &auo_g190ean01_timings, 1291 .num_timings = 1, 1292 .bpc = 8, 1293 .size = { 1294 .width = 376, 1295 .height = 301, 1296 }, 1297 .delay = { 1298 .prepare = 30, 1299 .enable = 200, 1300 .disable = 110, 1301 .unprepare = 1000, 1302 }, 1303 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1304 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1305 }; 1306 1307 static const struct display_timing auo_p238han01_timings = { 1308 .pixelclock = { 107400000, 142400000, 180000000 }, 1309 .hactive = { 1920, 1920, 1920 }, 1310 .hfront_porch = { 30, 70, 650 }, 1311 .hback_porch = { 30, 70, 650 }, 1312 .hsync_len = { 20, 40, 136 }, 1313 .vactive = { 1080, 1080, 1080 }, 1314 .vfront_porch = { 5, 19, 318 }, 1315 .vback_porch = { 5, 19, 318 }, 1316 .vsync_len = { 4, 12, 120 }, 1317 }; 1318 1319 static const struct panel_desc auo_p238han01 = { 1320 .timings = &auo_p238han01_timings, 1321 .num_timings = 1, 1322 .bpc = 8, 1323 .size = { 1324 .width = 527, 1325 .height = 296, 1326 }, 1327 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1328 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1329 }; 1330 1331 static const struct display_timing auo_p320hvn03_timings = { 1332 .pixelclock = { 106000000, 148500000, 164000000 }, 1333 .hactive = { 1920, 1920, 1920 }, 1334 .hfront_porch = { 25, 50, 130 }, 1335 .hback_porch = { 25, 50, 130 }, 1336 .hsync_len = { 20, 40, 105 }, 1337 .vactive = { 1080, 1080, 1080 }, 1338 .vfront_porch = { 8, 17, 150 }, 1339 .vback_porch = { 8, 17, 150 }, 1340 .vsync_len = { 4, 11, 100 }, 1341 }; 1342 1343 static const struct panel_desc auo_p320hvn03 = { 1344 .timings = &auo_p320hvn03_timings, 1345 .num_timings = 1, 1346 .bpc = 8, 1347 .size = { 1348 .width = 698, 1349 .height = 393, 1350 }, 1351 .delay = { 1352 .prepare = 1, 1353 .enable = 450, 1354 .unprepare = 500, 1355 }, 1356 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1357 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1358 }; 1359 1360 static const struct drm_display_mode auo_t215hvn01_mode = { 1361 .clock = 148800, 1362 .hdisplay = 1920, 1363 .hsync_start = 1920 + 88, 1364 .hsync_end = 1920 + 88 + 44, 1365 .htotal = 1920 + 88 + 44 + 148, 1366 .vdisplay = 1080, 1367 .vsync_start = 1080 + 4, 1368 .vsync_end = 1080 + 4 + 5, 1369 .vtotal = 1080 + 4 + 5 + 36, 1370 }; 1371 1372 static const struct panel_desc auo_t215hvn01 = { 1373 .modes = &auo_t215hvn01_mode, 1374 .num_modes = 1, 1375 .bpc = 8, 1376 .size = { 1377 .width = 430, 1378 .height = 270, 1379 }, 1380 .delay = { 1381 .disable = 5, 1382 .unprepare = 1000, 1383 }, 1384 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1385 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1386 }; 1387 1388 static const struct drm_display_mode avic_tm070ddh03_mode = { 1389 .clock = 51200, 1390 .hdisplay = 1024, 1391 .hsync_start = 1024 + 160, 1392 .hsync_end = 1024 + 160 + 4, 1393 .htotal = 1024 + 160 + 4 + 156, 1394 .vdisplay = 600, 1395 .vsync_start = 600 + 17, 1396 .vsync_end = 600 + 17 + 1, 1397 .vtotal = 600 + 17 + 1 + 17, 1398 }; 1399 1400 static const struct panel_desc avic_tm070ddh03 = { 1401 .modes = &avic_tm070ddh03_mode, 1402 .num_modes = 1, 1403 .bpc = 8, 1404 .size = { 1405 .width = 154, 1406 .height = 90, 1407 }, 1408 .delay = { 1409 .prepare = 20, 1410 .enable = 200, 1411 .disable = 200, 1412 }, 1413 }; 1414 1415 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1416 .clock = 30000, 1417 .hdisplay = 800, 1418 .hsync_start = 800 + 40, 1419 .hsync_end = 800 + 40 + 48, 1420 .htotal = 800 + 40 + 48 + 40, 1421 .vdisplay = 480, 1422 .vsync_start = 480 + 13, 1423 .vsync_end = 480 + 13 + 3, 1424 .vtotal = 480 + 13 + 3 + 29, 1425 }; 1426 1427 static const struct panel_desc bananapi_s070wv20_ct16 = { 1428 .modes = &bananapi_s070wv20_ct16_mode, 1429 .num_modes = 1, 1430 .bpc = 6, 1431 .size = { 1432 .width = 154, 1433 .height = 86, 1434 }, 1435 }; 1436 1437 static const struct display_timing boe_av101hdt_a10_timing = { 1438 .pixelclock = { 74210000, 75330000, 76780000, }, 1439 .hactive = { 1280, 1280, 1280, }, 1440 .hfront_porch = { 10, 42, 33, }, 1441 .hback_porch = { 10, 18, 33, }, 1442 .hsync_len = { 30, 10, 30, }, 1443 .vactive = { 720, 720, 720, }, 1444 .vfront_porch = { 200, 183, 200, }, 1445 .vback_porch = { 8, 8, 8, }, 1446 .vsync_len = { 2, 19, 2, }, 1447 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1448 }; 1449 1450 static const struct panel_desc boe_av101hdt_a10 = { 1451 .timings = &boe_av101hdt_a10_timing, 1452 .num_timings = 1, 1453 .bpc = 8, 1454 .size = { 1455 .width = 224, 1456 .height = 126, 1457 }, 1458 .delay = { 1459 .enable = 50, 1460 .disable = 50, 1461 }, 1462 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1463 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1464 }; 1465 1466 static const struct display_timing boe_av123z7m_n17_timing = { 1467 .pixelclock = { 86600000, 88000000, 90800000, }, 1468 .hactive = { 1920, 1920, 1920, }, 1469 .hfront_porch = { 10, 10, 10, }, 1470 .hback_porch = { 10, 10, 10, }, 1471 .hsync_len = { 9, 12, 25, }, 1472 .vactive = { 720, 720, 720, }, 1473 .vfront_porch = { 7, 10, 13, }, 1474 .vback_porch = { 7, 10, 13, }, 1475 .vsync_len = { 7, 11, 14, }, 1476 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1477 }; 1478 1479 static const struct panel_desc boe_av123z7m_n17 = { 1480 .timings = &boe_av123z7m_n17_timing, 1481 .bpc = 8, 1482 .num_timings = 1, 1483 .size = { 1484 .width = 292, 1485 .height = 110, 1486 }, 1487 .delay = { 1488 .prepare = 50, 1489 .disable = 50, 1490 }, 1491 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1492 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1493 }; 1494 1495 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1496 .clock = 78945, 1497 .hdisplay = 1280, 1498 .hsync_start = 1280 + 0, 1499 .hsync_end = 1280 + 0 + 2, 1500 .htotal = 1280 + 62 + 0 + 2, 1501 .vdisplay = 800, 1502 .vsync_start = 800 + 8, 1503 .vsync_end = 800 + 8 + 2, 1504 .vtotal = 800 + 6 + 8 + 2, 1505 }; 1506 1507 static const struct panel_desc boe_bp082wx1_100 = { 1508 .modes = &boe_bp101wx1_100_mode, 1509 .num_modes = 1, 1510 .bpc = 8, 1511 .size = { 1512 .width = 177, 1513 .height = 110, 1514 }, 1515 .delay = { 1516 .enable = 50, 1517 .disable = 50, 1518 }, 1519 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1520 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1521 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1522 }; 1523 1524 static const struct panel_desc boe_bp101wx1_100 = { 1525 .modes = &boe_bp101wx1_100_mode, 1526 .num_modes = 1, 1527 .bpc = 8, 1528 .size = { 1529 .width = 217, 1530 .height = 136, 1531 }, 1532 .delay = { 1533 .enable = 50, 1534 .disable = 50, 1535 }, 1536 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1537 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1538 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1539 }; 1540 1541 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1542 .pixelclock = { 69922000, 71000000, 72293000 }, 1543 .hactive = { 1280, 1280, 1280 }, 1544 .hfront_porch = { 48, 48, 48 }, 1545 .hback_porch = { 80, 80, 80 }, 1546 .hsync_len = { 32, 32, 32 }, 1547 .vactive = { 800, 800, 800 }, 1548 .vfront_porch = { 3, 3, 3 }, 1549 .vback_porch = { 14, 14, 14 }, 1550 .vsync_len = { 6, 6, 6 }, 1551 }; 1552 1553 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1554 .timings = &boe_ev121wxm_n10_1850_timing, 1555 .num_timings = 1, 1556 .bpc = 8, 1557 .size = { 1558 .width = 261, 1559 .height = 163, 1560 }, 1561 .delay = { 1562 .prepare = 9, 1563 .enable = 300, 1564 .unprepare = 300, 1565 .disable = 560, 1566 }, 1567 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1568 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1569 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1570 }; 1571 1572 static const struct drm_display_mode boe_hv070wsa_mode = { 1573 .clock = 42105, 1574 .hdisplay = 1024, 1575 .hsync_start = 1024 + 30, 1576 .hsync_end = 1024 + 30 + 30, 1577 .htotal = 1024 + 30 + 30 + 30, 1578 .vdisplay = 600, 1579 .vsync_start = 600 + 10, 1580 .vsync_end = 600 + 10 + 10, 1581 .vtotal = 600 + 10 + 10 + 10, 1582 }; 1583 1584 static const struct panel_desc boe_hv070wsa = { 1585 .modes = &boe_hv070wsa_mode, 1586 .num_modes = 1, 1587 .bpc = 8, 1588 .size = { 1589 .width = 154, 1590 .height = 90, 1591 }, 1592 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1593 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1594 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1595 }; 1596 1597 static const struct display_timing cct_cmt430b19n00_timing = { 1598 .pixelclock = { 8000000, 9000000, 12000000 }, 1599 .hactive = { 480, 480, 480 }, 1600 .hfront_porch = { 2, 8, 75 }, 1601 .hback_porch = { 3, 43, 43 }, 1602 .hsync_len = { 2, 4, 75 }, 1603 .vactive = { 272, 272, 272 }, 1604 .vfront_porch = { 2, 8, 37 }, 1605 .vback_porch = { 2, 12, 12 }, 1606 .vsync_len = { 2, 4, 37 }, 1607 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1608 }; 1609 1610 static const struct panel_desc cct_cmt430b19n00 = { 1611 .timings = &cct_cmt430b19n00_timing, 1612 .num_timings = 1, 1613 .bpc = 8, 1614 .size = { 1615 .width = 95, 1616 .height = 53, 1617 }, 1618 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1619 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1620 .connector_type = DRM_MODE_CONNECTOR_DPI, 1621 }; 1622 1623 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1624 .clock = 9000, 1625 .hdisplay = 480, 1626 .hsync_start = 480 + 5, 1627 .hsync_end = 480 + 5 + 5, 1628 .htotal = 480 + 5 + 5 + 40, 1629 .vdisplay = 272, 1630 .vsync_start = 272 + 8, 1631 .vsync_end = 272 + 8 + 8, 1632 .vtotal = 272 + 8 + 8 + 8, 1633 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1634 }; 1635 1636 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1637 .modes = &cdtech_s043wq26h_ct7_mode, 1638 .num_modes = 1, 1639 .bpc = 8, 1640 .size = { 1641 .width = 95, 1642 .height = 54, 1643 }, 1644 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1645 }; 1646 1647 /* S070PWS19HP-FC21 2017/04/22 */ 1648 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1649 .clock = 51200, 1650 .hdisplay = 1024, 1651 .hsync_start = 1024 + 160, 1652 .hsync_end = 1024 + 160 + 20, 1653 .htotal = 1024 + 160 + 20 + 140, 1654 .vdisplay = 600, 1655 .vsync_start = 600 + 12, 1656 .vsync_end = 600 + 12 + 3, 1657 .vtotal = 600 + 12 + 3 + 20, 1658 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1659 }; 1660 1661 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1662 .modes = &cdtech_s070pws19hp_fc21_mode, 1663 .num_modes = 1, 1664 .bpc = 6, 1665 .size = { 1666 .width = 154, 1667 .height = 86, 1668 }, 1669 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1670 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1671 .connector_type = DRM_MODE_CONNECTOR_DPI, 1672 }; 1673 1674 /* S070SWV29HG-DC44 2017/09/21 */ 1675 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1676 .clock = 33300, 1677 .hdisplay = 800, 1678 .hsync_start = 800 + 210, 1679 .hsync_end = 800 + 210 + 2, 1680 .htotal = 800 + 210 + 2 + 44, 1681 .vdisplay = 480, 1682 .vsync_start = 480 + 22, 1683 .vsync_end = 480 + 22 + 2, 1684 .vtotal = 480 + 22 + 2 + 21, 1685 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1686 }; 1687 1688 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1689 .modes = &cdtech_s070swv29hg_dc44_mode, 1690 .num_modes = 1, 1691 .bpc = 6, 1692 .size = { 1693 .width = 154, 1694 .height = 86, 1695 }, 1696 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1697 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1698 .connector_type = DRM_MODE_CONNECTOR_DPI, 1699 }; 1700 1701 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1702 .clock = 35000, 1703 .hdisplay = 800, 1704 .hsync_start = 800 + 40, 1705 .hsync_end = 800 + 40 + 40, 1706 .htotal = 800 + 40 + 40 + 48, 1707 .vdisplay = 480, 1708 .vsync_start = 480 + 29, 1709 .vsync_end = 480 + 29 + 13, 1710 .vtotal = 480 + 29 + 13 + 3, 1711 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1712 }; 1713 1714 static const struct panel_desc cdtech_s070wv95_ct16 = { 1715 .modes = &cdtech_s070wv95_ct16_mode, 1716 .num_modes = 1, 1717 .bpc = 8, 1718 .size = { 1719 .width = 154, 1720 .height = 85, 1721 }, 1722 }; 1723 1724 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1725 .pixelclock = { 68900000, 71100000, 73400000 }, 1726 .hactive = { 1280, 1280, 1280 }, 1727 .hfront_porch = { 65, 80, 95 }, 1728 .hback_porch = { 64, 79, 94 }, 1729 .hsync_len = { 1, 1, 1 }, 1730 .vactive = { 800, 800, 800 }, 1731 .vfront_porch = { 7, 11, 14 }, 1732 .vback_porch = { 7, 11, 14 }, 1733 .vsync_len = { 1, 1, 1 }, 1734 .flags = DISPLAY_FLAGS_DE_HIGH, 1735 }; 1736 1737 static const struct panel_desc chefree_ch101olhlwh_002 = { 1738 .timings = &chefree_ch101olhlwh_002_timing, 1739 .num_timings = 1, 1740 .bpc = 8, 1741 .size = { 1742 .width = 217, 1743 .height = 135, 1744 }, 1745 .delay = { 1746 .enable = 200, 1747 .disable = 200, 1748 }, 1749 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1750 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1751 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1752 }; 1753 1754 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1755 .clock = 66770, 1756 .hdisplay = 800, 1757 .hsync_start = 800 + 49, 1758 .hsync_end = 800 + 49 + 33, 1759 .htotal = 800 + 49 + 33 + 17, 1760 .vdisplay = 1280, 1761 .vsync_start = 1280 + 1, 1762 .vsync_end = 1280 + 1 + 7, 1763 .vtotal = 1280 + 1 + 7 + 15, 1764 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1765 }; 1766 1767 static const struct panel_desc chunghwa_claa070wp03xg = { 1768 .modes = &chunghwa_claa070wp03xg_mode, 1769 .num_modes = 1, 1770 .bpc = 6, 1771 .size = { 1772 .width = 94, 1773 .height = 150, 1774 }, 1775 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1776 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1777 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1778 }; 1779 1780 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1781 .clock = 72070, 1782 .hdisplay = 1366, 1783 .hsync_start = 1366 + 58, 1784 .hsync_end = 1366 + 58 + 58, 1785 .htotal = 1366 + 58 + 58 + 58, 1786 .vdisplay = 768, 1787 .vsync_start = 768 + 4, 1788 .vsync_end = 768 + 4 + 4, 1789 .vtotal = 768 + 4 + 4 + 4, 1790 }; 1791 1792 static const struct panel_desc chunghwa_claa101wa01a = { 1793 .modes = &chunghwa_claa101wa01a_mode, 1794 .num_modes = 1, 1795 .bpc = 6, 1796 .size = { 1797 .width = 220, 1798 .height = 120, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1802 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1803 }; 1804 1805 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1806 .clock = 69300, 1807 .hdisplay = 1366, 1808 .hsync_start = 1366 + 48, 1809 .hsync_end = 1366 + 48 + 32, 1810 .htotal = 1366 + 48 + 32 + 20, 1811 .vdisplay = 768, 1812 .vsync_start = 768 + 16, 1813 .vsync_end = 768 + 16 + 8, 1814 .vtotal = 768 + 16 + 8 + 16, 1815 }; 1816 1817 static const struct panel_desc chunghwa_claa101wb01 = { 1818 .modes = &chunghwa_claa101wb01_mode, 1819 .num_modes = 1, 1820 .bpc = 6, 1821 .size = { 1822 .width = 223, 1823 .height = 125, 1824 }, 1825 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1826 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1827 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1828 }; 1829 1830 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1831 .pixelclock = { 5000000, 9000000, 12000000 }, 1832 .hactive = { 480, 480, 480 }, 1833 .hfront_porch = { 12, 12, 12 }, 1834 .hback_porch = { 12, 12, 12 }, 1835 .hsync_len = { 21, 21, 21 }, 1836 .vactive = { 272, 272, 272 }, 1837 .vfront_porch = { 4, 4, 4 }, 1838 .vback_porch = { 4, 4, 4 }, 1839 .vsync_len = { 8, 8, 8 }, 1840 }; 1841 1842 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1843 .timings = &dataimage_fg040346dsswbg04_timing, 1844 .num_timings = 1, 1845 .bpc = 8, 1846 .size = { 1847 .width = 95, 1848 .height = 54, 1849 }, 1850 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1851 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1852 .connector_type = DRM_MODE_CONNECTOR_DPI, 1853 }; 1854 1855 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1856 .pixelclock = { 68900000, 71110000, 73400000 }, 1857 .hactive = { 1280, 1280, 1280 }, 1858 .vactive = { 800, 800, 800 }, 1859 .hback_porch = { 100, 100, 100 }, 1860 .hfront_porch = { 100, 100, 100 }, 1861 .vback_porch = { 5, 5, 5 }, 1862 .vfront_porch = { 5, 5, 5 }, 1863 .hsync_len = { 24, 24, 24 }, 1864 .vsync_len = { 3, 3, 3 }, 1865 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1866 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1867 }; 1868 1869 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1870 .timings = &dataimage_fg1001l0dsswmg01_timing, 1871 .num_timings = 1, 1872 .bpc = 8, 1873 .size = { 1874 .width = 217, 1875 .height = 136, 1876 }, 1877 }; 1878 1879 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1880 .clock = 33260, 1881 .hdisplay = 800, 1882 .hsync_start = 800 + 40, 1883 .hsync_end = 800 + 40 + 128, 1884 .htotal = 800 + 40 + 128 + 88, 1885 .vdisplay = 480, 1886 .vsync_start = 480 + 10, 1887 .vsync_end = 480 + 10 + 2, 1888 .vtotal = 480 + 10 + 2 + 33, 1889 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1890 }; 1891 1892 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1893 .modes = &dataimage_scf0700c48ggu18_mode, 1894 .num_modes = 1, 1895 .bpc = 8, 1896 .size = { 1897 .width = 152, 1898 .height = 91, 1899 }, 1900 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1901 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1902 .connector_type = DRM_MODE_CONNECTOR_DPI, 1903 }; 1904 1905 static const struct display_timing displaytech_dt050btft_pts_timing = { 1906 /* The TYP pixel clock are recalculated from tV * tH * 60 Hz */ 1907 .pixelclock = { 30000000, 33264000, 50000000 }, 1908 .hactive = { 800, 800, 800 }, 1909 .hfront_porch = { 16, 210, 354 }, 1910 /* Datasheet Figure 3 indicates, that tHPW is part of tHBP */ 1911 .hback_porch = { 41, 26, 6 }, 1912 .hsync_len = { 1, 20, 40 }, 1913 .vactive = { 480, 480, 480 }, 1914 .vfront_porch = { 7, 22, 147 }, 1915 /* Datasheet Figure 2 indicates, that tVPW is part of tVBP */ 1916 .vback_porch = { 22, 13, 3 }, 1917 .vsync_len = { 1, 10, 20 }, 1918 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1919 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1920 DISPLAY_FLAGS_SYNC_POSEDGE, 1921 }; 1922 1923 static const struct panel_desc displaytech_dt050btft_pts = { 1924 .timings = &displaytech_dt050btft_pts_timing, 1925 .num_timings = 1, 1926 .bpc = 8, 1927 .size = { 1928 .width = 108, 1929 .height = 65, 1930 }, 1931 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1932 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 1933 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 1934 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 1935 .connector_type = DRM_MODE_CONNECTOR_DPI, 1936 }; 1937 1938 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1939 .pixelclock = { 45000000, 51200000, 57000000 }, 1940 .hactive = { 1024, 1024, 1024 }, 1941 .hfront_porch = { 100, 106, 113 }, 1942 .hback_porch = { 100, 106, 113 }, 1943 .hsync_len = { 100, 108, 114 }, 1944 .vactive = { 600, 600, 600 }, 1945 .vfront_porch = { 8, 11, 15 }, 1946 .vback_porch = { 8, 11, 15 }, 1947 .vsync_len = { 9, 13, 15 }, 1948 .flags = DISPLAY_FLAGS_DE_HIGH, 1949 }; 1950 1951 static const struct panel_desc dlc_dlc0700yzg_1 = { 1952 .timings = &dlc_dlc0700yzg_1_timing, 1953 .num_timings = 1, 1954 .bpc = 6, 1955 .size = { 1956 .width = 154, 1957 .height = 86, 1958 }, 1959 .delay = { 1960 .prepare = 30, 1961 .enable = 200, 1962 .disable = 200, 1963 }, 1964 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1965 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1966 }; 1967 1968 static const struct display_timing dlc_dlc1010gig_timing = { 1969 .pixelclock = { 68900000, 71100000, 73400000 }, 1970 .hactive = { 1280, 1280, 1280 }, 1971 .hfront_porch = { 43, 53, 63 }, 1972 .hback_porch = { 43, 53, 63 }, 1973 .hsync_len = { 44, 54, 64 }, 1974 .vactive = { 800, 800, 800 }, 1975 .vfront_porch = { 5, 8, 11 }, 1976 .vback_porch = { 5, 8, 11 }, 1977 .vsync_len = { 5, 7, 11 }, 1978 .flags = DISPLAY_FLAGS_DE_HIGH, 1979 }; 1980 1981 static const struct panel_desc dlc_dlc1010gig = { 1982 .timings = &dlc_dlc1010gig_timing, 1983 .num_timings = 1, 1984 .bpc = 8, 1985 .size = { 1986 .width = 216, 1987 .height = 135, 1988 }, 1989 .delay = { 1990 .prepare = 60, 1991 .enable = 150, 1992 .disable = 100, 1993 .unprepare = 60, 1994 }, 1995 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1996 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1997 }; 1998 1999 static const struct drm_display_mode edt_et035012dm6_mode = { 2000 .clock = 6500, 2001 .hdisplay = 320, 2002 .hsync_start = 320 + 20, 2003 .hsync_end = 320 + 20 + 30, 2004 .htotal = 320 + 20 + 68, 2005 .vdisplay = 240, 2006 .vsync_start = 240 + 4, 2007 .vsync_end = 240 + 4 + 4, 2008 .vtotal = 240 + 4 + 4 + 14, 2009 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2010 }; 2011 2012 static const struct panel_desc edt_et035012dm6 = { 2013 .modes = &edt_et035012dm6_mode, 2014 .num_modes = 1, 2015 .bpc = 8, 2016 .size = { 2017 .width = 70, 2018 .height = 52, 2019 }, 2020 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2021 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2022 }; 2023 2024 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 2025 .clock = 6520, 2026 .hdisplay = 320, 2027 .hsync_start = 320 + 20, 2028 .hsync_end = 320 + 20 + 68, 2029 .htotal = 320 + 20 + 68, 2030 .vdisplay = 240, 2031 .vsync_start = 240 + 4, 2032 .vsync_end = 240 + 4 + 18, 2033 .vtotal = 240 + 4 + 18, 2034 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2035 }; 2036 2037 static const struct panel_desc edt_etm0350g0dh6 = { 2038 .modes = &edt_etm0350g0dh6_mode, 2039 .num_modes = 1, 2040 .bpc = 6, 2041 .size = { 2042 .width = 70, 2043 .height = 53, 2044 }, 2045 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2046 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2047 .connector_type = DRM_MODE_CONNECTOR_DPI, 2048 }; 2049 2050 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 2051 .clock = 10870, 2052 .hdisplay = 480, 2053 .hsync_start = 480 + 8, 2054 .hsync_end = 480 + 8 + 4, 2055 .htotal = 480 + 8 + 4 + 41, 2056 2057 /* 2058 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 2059 * fb_align 2060 */ 2061 2062 .vdisplay = 288, 2063 .vsync_start = 288 + 2, 2064 .vsync_end = 288 + 2 + 4, 2065 .vtotal = 288 + 2 + 4 + 10, 2066 }; 2067 2068 static const struct panel_desc edt_etm043080dh6gp = { 2069 .modes = &edt_etm043080dh6gp_mode, 2070 .num_modes = 1, 2071 .bpc = 8, 2072 .size = { 2073 .width = 100, 2074 .height = 65, 2075 }, 2076 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2077 .connector_type = DRM_MODE_CONNECTOR_DPI, 2078 }; 2079 2080 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 2081 .clock = 9000, 2082 .hdisplay = 480, 2083 .hsync_start = 480 + 2, 2084 .hsync_end = 480 + 2 + 41, 2085 .htotal = 480 + 2 + 41 + 2, 2086 .vdisplay = 272, 2087 .vsync_start = 272 + 2, 2088 .vsync_end = 272 + 2 + 10, 2089 .vtotal = 272 + 2 + 10 + 2, 2090 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2091 }; 2092 2093 static const struct panel_desc edt_etm0430g0dh6 = { 2094 .modes = &edt_etm0430g0dh6_mode, 2095 .num_modes = 1, 2096 .bpc = 6, 2097 .size = { 2098 .width = 95, 2099 .height = 54, 2100 }, 2101 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2102 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2103 .connector_type = DRM_MODE_CONNECTOR_DPI, 2104 }; 2105 2106 static const struct drm_display_mode edt_et057090dhu_mode = { 2107 .clock = 25175, 2108 .hdisplay = 640, 2109 .hsync_start = 640 + 16, 2110 .hsync_end = 640 + 16 + 30, 2111 .htotal = 640 + 16 + 30 + 114, 2112 .vdisplay = 480, 2113 .vsync_start = 480 + 10, 2114 .vsync_end = 480 + 10 + 3, 2115 .vtotal = 480 + 10 + 3 + 32, 2116 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2117 }; 2118 2119 static const struct panel_desc edt_et057090dhu = { 2120 .modes = &edt_et057090dhu_mode, 2121 .num_modes = 1, 2122 .bpc = 6, 2123 .size = { 2124 .width = 115, 2125 .height = 86, 2126 }, 2127 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2128 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2129 .connector_type = DRM_MODE_CONNECTOR_DPI, 2130 }; 2131 2132 static const struct display_timing edt_et057023udba_timing = { 2133 .pixelclock = { 23200000, 24190000, 39640000 }, 2134 .hactive = { 640, 640, 640 }, 2135 .hfront_porch = { 20, 40, 200 }, 2136 .hback_porch = { 87, 40, 1 }, 2137 .hsync_len = { 1, 48, 87 }, 2138 .vactive = { 480, 480, 480 }, 2139 .vfront_porch = { 5, 13, 200 }, 2140 .vback_porch = { 31, 31, 29 }, 2141 .vsync_len = { 1, 1, 3 }, 2142 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2143 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2144 DISPLAY_FLAGS_SYNC_POSEDGE, 2145 }; 2146 2147 static const struct panel_desc edt_et057023udba = { 2148 .timings = &edt_et057023udba_timing, 2149 .num_timings = 1, 2150 .bpc = 8, 2151 .size = { 2152 .width = 115, 2153 .height = 86, 2154 }, 2155 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2156 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2157 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2158 .connector_type = DRM_MODE_CONNECTOR_DPI, 2159 }; 2160 2161 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2162 .clock = 33260, 2163 .hdisplay = 800, 2164 .hsync_start = 800 + 40, 2165 .hsync_end = 800 + 40 + 128, 2166 .htotal = 800 + 40 + 128 + 88, 2167 .vdisplay = 480, 2168 .vsync_start = 480 + 10, 2169 .vsync_end = 480 + 10 + 2, 2170 .vtotal = 480 + 10 + 2 + 33, 2171 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2172 }; 2173 2174 static const struct panel_desc edt_etm0700g0dh6 = { 2175 .modes = &edt_etm0700g0dh6_mode, 2176 .num_modes = 1, 2177 .bpc = 6, 2178 .size = { 2179 .width = 152, 2180 .height = 91, 2181 }, 2182 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2183 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2184 .connector_type = DRM_MODE_CONNECTOR_DPI, 2185 }; 2186 2187 static const struct panel_desc edt_etm0700g0bdh6 = { 2188 .modes = &edt_etm0700g0dh6_mode, 2189 .num_modes = 1, 2190 .bpc = 6, 2191 .size = { 2192 .width = 152, 2193 .height = 91, 2194 }, 2195 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2196 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2197 .connector_type = DRM_MODE_CONNECTOR_DPI, 2198 }; 2199 2200 static const struct display_timing edt_etml0700y5dha_timing = { 2201 .pixelclock = { 40800000, 51200000, 67200000 }, 2202 .hactive = { 1024, 1024, 1024 }, 2203 .hfront_porch = { 30, 106, 125 }, 2204 .hback_porch = { 30, 106, 125 }, 2205 .hsync_len = { 30, 108, 126 }, 2206 .vactive = { 600, 600, 600 }, 2207 .vfront_porch = { 3, 12, 67}, 2208 .vback_porch = { 3, 12, 67 }, 2209 .vsync_len = { 4, 11, 66 }, 2210 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2211 DISPLAY_FLAGS_DE_HIGH, 2212 }; 2213 2214 static const struct panel_desc edt_etml0700y5dha = { 2215 .timings = &edt_etml0700y5dha_timing, 2216 .num_timings = 1, 2217 .bpc = 8, 2218 .size = { 2219 .width = 155, 2220 .height = 86, 2221 }, 2222 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2223 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2224 }; 2225 2226 static const struct display_timing edt_etml1010g3dra_timing = { 2227 .pixelclock = { 66300000, 72400000, 78900000 }, 2228 .hactive = { 1280, 1280, 1280 }, 2229 .hfront_porch = { 12, 72, 132 }, 2230 .hback_porch = { 86, 86, 86 }, 2231 .hsync_len = { 2, 2, 2 }, 2232 .vactive = { 800, 800, 800 }, 2233 .vfront_porch = { 1, 15, 49 }, 2234 .vback_porch = { 21, 21, 21 }, 2235 .vsync_len = { 2, 2, 2 }, 2236 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2237 DISPLAY_FLAGS_DE_HIGH, 2238 }; 2239 2240 static const struct panel_desc edt_etml1010g3dra = { 2241 .timings = &edt_etml1010g3dra_timing, 2242 .num_timings = 1, 2243 .bpc = 8, 2244 .size = { 2245 .width = 216, 2246 .height = 135, 2247 }, 2248 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2249 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2250 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2251 }; 2252 2253 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2254 .clock = 25175, 2255 .hdisplay = 640, 2256 .hsync_start = 640, 2257 .hsync_end = 640 + 16, 2258 .htotal = 640 + 16 + 30 + 114, 2259 .vdisplay = 480, 2260 .vsync_start = 480 + 10, 2261 .vsync_end = 480 + 10 + 3, 2262 .vtotal = 480 + 10 + 3 + 35, 2263 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2264 }; 2265 2266 static const struct panel_desc edt_etmv570g2dhu = { 2267 .modes = &edt_etmv570g2dhu_mode, 2268 .num_modes = 1, 2269 .bpc = 6, 2270 .size = { 2271 .width = 115, 2272 .height = 86, 2273 }, 2274 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2275 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2276 .connector_type = DRM_MODE_CONNECTOR_DPI, 2277 }; 2278 2279 static const struct display_timing eink_vb3300_kca_timing = { 2280 .pixelclock = { 40000000, 40000000, 40000000 }, 2281 .hactive = { 334, 334, 334 }, 2282 .hfront_porch = { 1, 1, 1 }, 2283 .hback_porch = { 1, 1, 1 }, 2284 .hsync_len = { 1, 1, 1 }, 2285 .vactive = { 1405, 1405, 1405 }, 2286 .vfront_porch = { 1, 1, 1 }, 2287 .vback_porch = { 1, 1, 1 }, 2288 .vsync_len = { 1, 1, 1 }, 2289 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2290 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2291 }; 2292 2293 static const struct panel_desc eink_vb3300_kca = { 2294 .timings = &eink_vb3300_kca_timing, 2295 .num_timings = 1, 2296 .bpc = 6, 2297 .size = { 2298 .width = 157, 2299 .height = 209, 2300 }, 2301 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2302 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2303 .connector_type = DRM_MODE_CONNECTOR_DPI, 2304 }; 2305 2306 static const struct display_timing evervision_vgg644804_timing = { 2307 .pixelclock = { 25175000, 25175000, 25175000 }, 2308 .hactive = { 640, 640, 640 }, 2309 .hfront_porch = { 16, 16, 16 }, 2310 .hback_porch = { 82, 114, 170 }, 2311 .hsync_len = { 5, 30, 30 }, 2312 .vactive = { 480, 480, 480 }, 2313 .vfront_porch = { 10, 10, 10 }, 2314 .vback_porch = { 30, 32, 34 }, 2315 .vsync_len = { 1, 3, 5 }, 2316 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2317 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2318 DISPLAY_FLAGS_SYNC_POSEDGE, 2319 }; 2320 2321 static const struct panel_desc evervision_vgg644804 = { 2322 .timings = &evervision_vgg644804_timing, 2323 .num_timings = 1, 2324 .bpc = 6, 2325 .size = { 2326 .width = 115, 2327 .height = 86, 2328 }, 2329 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2330 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2331 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2332 }; 2333 2334 static const struct display_timing evervision_vgg804821_timing = { 2335 .pixelclock = { 27600000, 33300000, 50000000 }, 2336 .hactive = { 800, 800, 800 }, 2337 .hfront_porch = { 40, 66, 70 }, 2338 .hback_porch = { 40, 67, 70 }, 2339 .hsync_len = { 40, 67, 70 }, 2340 .vactive = { 480, 480, 480 }, 2341 .vfront_porch = { 6, 10, 10 }, 2342 .vback_porch = { 7, 11, 11 }, 2343 .vsync_len = { 7, 11, 11 }, 2344 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2345 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2346 DISPLAY_FLAGS_SYNC_NEGEDGE, 2347 }; 2348 2349 static const struct panel_desc evervision_vgg804821 = { 2350 .timings = &evervision_vgg804821_timing, 2351 .num_timings = 1, 2352 .bpc = 8, 2353 .size = { 2354 .width = 108, 2355 .height = 64, 2356 }, 2357 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2358 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2359 }; 2360 2361 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2362 .clock = 32260, 2363 .hdisplay = 800, 2364 .hsync_start = 800 + 168, 2365 .hsync_end = 800 + 168 + 64, 2366 .htotal = 800 + 168 + 64 + 88, 2367 .vdisplay = 480, 2368 .vsync_start = 480 + 37, 2369 .vsync_end = 480 + 37 + 2, 2370 .vtotal = 480 + 37 + 2 + 8, 2371 }; 2372 2373 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2374 .modes = &foxlink_fl500wvr00_a0t_mode, 2375 .num_modes = 1, 2376 .bpc = 8, 2377 .size = { 2378 .width = 108, 2379 .height = 65, 2380 }, 2381 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2382 }; 2383 2384 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2385 { /* 60 Hz */ 2386 .clock = 6000, 2387 .hdisplay = 320, 2388 .hsync_start = 320 + 44, 2389 .hsync_end = 320 + 44 + 16, 2390 .htotal = 320 + 44 + 16 + 20, 2391 .vdisplay = 240, 2392 .vsync_start = 240 + 2, 2393 .vsync_end = 240 + 2 + 6, 2394 .vtotal = 240 + 2 + 6 + 2, 2395 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2396 }, 2397 { /* 50 Hz */ 2398 .clock = 5400, 2399 .hdisplay = 320, 2400 .hsync_start = 320 + 56, 2401 .hsync_end = 320 + 56 + 16, 2402 .htotal = 320 + 56 + 16 + 40, 2403 .vdisplay = 240, 2404 .vsync_start = 240 + 2, 2405 .vsync_end = 240 + 2 + 6, 2406 .vtotal = 240 + 2 + 6 + 2, 2407 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2408 }, 2409 }; 2410 2411 static const struct panel_desc frida_frd350h54004 = { 2412 .modes = frida_frd350h54004_modes, 2413 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2414 .bpc = 8, 2415 .size = { 2416 .width = 77, 2417 .height = 64, 2418 }, 2419 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2420 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2421 .connector_type = DRM_MODE_CONNECTOR_DPI, 2422 }; 2423 2424 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2425 .clock = 9000, 2426 .hdisplay = 480, 2427 .hsync_start = 480 + 5, 2428 .hsync_end = 480 + 5 + 1, 2429 .htotal = 480 + 5 + 1 + 40, 2430 .vdisplay = 272, 2431 .vsync_start = 272 + 8, 2432 .vsync_end = 272 + 8 + 1, 2433 .vtotal = 272 + 8 + 1 + 8, 2434 }; 2435 2436 static const struct panel_desc giantplus_gpg482739qs5 = { 2437 .modes = &giantplus_gpg482739qs5_mode, 2438 .num_modes = 1, 2439 .bpc = 8, 2440 .size = { 2441 .width = 95, 2442 .height = 54, 2443 }, 2444 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2445 }; 2446 2447 static const struct display_timing giantplus_gpm940b0_timing = { 2448 .pixelclock = { 13500000, 27000000, 27500000 }, 2449 .hactive = { 320, 320, 320 }, 2450 .hfront_porch = { 14, 686, 718 }, 2451 .hback_porch = { 50, 70, 255 }, 2452 .hsync_len = { 1, 1, 1 }, 2453 .vactive = { 240, 240, 240 }, 2454 .vfront_porch = { 1, 1, 179 }, 2455 .vback_porch = { 1, 21, 31 }, 2456 .vsync_len = { 1, 1, 6 }, 2457 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2458 }; 2459 2460 static const struct panel_desc giantplus_gpm940b0 = { 2461 .timings = &giantplus_gpm940b0_timing, 2462 .num_timings = 1, 2463 .bpc = 8, 2464 .size = { 2465 .width = 60, 2466 .height = 45, 2467 }, 2468 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2469 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2470 }; 2471 2472 static const struct display_timing hannstar_hsd070pww1_timing = { 2473 .pixelclock = { 64300000, 71100000, 82000000 }, 2474 .hactive = { 1280, 1280, 1280 }, 2475 .hfront_porch = { 1, 1, 10 }, 2476 .hback_porch = { 1, 1, 10 }, 2477 /* 2478 * According to the data sheet, the minimum horizontal blanking interval 2479 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2480 * minimum working horizontal blanking interval to be 60 clocks. 2481 */ 2482 .hsync_len = { 58, 158, 661 }, 2483 .vactive = { 800, 800, 800 }, 2484 .vfront_porch = { 1, 1, 10 }, 2485 .vback_porch = { 1, 1, 10 }, 2486 .vsync_len = { 1, 21, 203 }, 2487 .flags = DISPLAY_FLAGS_DE_HIGH, 2488 }; 2489 2490 static const struct panel_desc hannstar_hsd070pww1 = { 2491 .timings = &hannstar_hsd070pww1_timing, 2492 .num_timings = 1, 2493 .bpc = 6, 2494 .size = { 2495 .width = 151, 2496 .height = 94, 2497 }, 2498 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2499 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2500 }; 2501 2502 static const struct display_timing hannstar_hsd100pxn1_timing = { 2503 .pixelclock = { 55000000, 65000000, 75000000 }, 2504 .hactive = { 1024, 1024, 1024 }, 2505 .hfront_porch = { 40, 40, 40 }, 2506 .hback_porch = { 220, 220, 220 }, 2507 .hsync_len = { 20, 60, 100 }, 2508 .vactive = { 768, 768, 768 }, 2509 .vfront_porch = { 7, 7, 7 }, 2510 .vback_porch = { 21, 21, 21 }, 2511 .vsync_len = { 10, 10, 10 }, 2512 .flags = DISPLAY_FLAGS_DE_HIGH, 2513 }; 2514 2515 static const struct panel_desc hannstar_hsd100pxn1 = { 2516 .timings = &hannstar_hsd100pxn1_timing, 2517 .num_timings = 1, 2518 .bpc = 6, 2519 .size = { 2520 .width = 203, 2521 .height = 152, 2522 }, 2523 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2524 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2525 }; 2526 2527 static const struct display_timing hannstar_hsd101pww2_timing = { 2528 .pixelclock = { 64300000, 71100000, 82000000 }, 2529 .hactive = { 1280, 1280, 1280 }, 2530 .hfront_porch = { 1, 1, 10 }, 2531 .hback_porch = { 1, 1, 10 }, 2532 .hsync_len = { 58, 158, 661 }, 2533 .vactive = { 800, 800, 800 }, 2534 .vfront_porch = { 1, 1, 10 }, 2535 .vback_porch = { 1, 1, 10 }, 2536 .vsync_len = { 1, 21, 203 }, 2537 .flags = DISPLAY_FLAGS_DE_HIGH, 2538 }; 2539 2540 static const struct panel_desc hannstar_hsd101pww2 = { 2541 .timings = &hannstar_hsd101pww2_timing, 2542 .num_timings = 1, 2543 .bpc = 8, 2544 .size = { 2545 .width = 217, 2546 .height = 136, 2547 }, 2548 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2549 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2550 }; 2551 2552 static const struct display_timing hannstar_hsd156juw2_timing = { 2553 .pixelclock = { 66000000, 72800000, 80500000 }, 2554 .hactive = { 1920, 1920, 1920 }, 2555 .hfront_porch = { 20, 30, 30 }, 2556 .hback_porch = { 20, 30, 30 }, 2557 .hsync_len = { 50, 60, 90 }, 2558 .vactive = { 1080, 1080, 1080 }, 2559 .vfront_porch = { 1, 2, 4 }, 2560 .vback_porch = { 1, 2, 4 }, 2561 .vsync_len = { 3, 40, 80 }, 2562 .flags = DISPLAY_FLAGS_DE_HIGH, 2563 }; 2564 2565 static const struct panel_desc hannstar_hsd156juw2 = { 2566 .timings = &hannstar_hsd156juw2_timing, 2567 .num_timings = 1, 2568 .bpc = 8, 2569 .size = { 2570 .width = 344, 2571 .height = 194, 2572 }, 2573 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2574 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2575 }; 2576 2577 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2578 .clock = 33333, 2579 .hdisplay = 800, 2580 .hsync_start = 800 + 85, 2581 .hsync_end = 800 + 85 + 86, 2582 .htotal = 800 + 85 + 86 + 85, 2583 .vdisplay = 480, 2584 .vsync_start = 480 + 16, 2585 .vsync_end = 480 + 16 + 13, 2586 .vtotal = 480 + 16 + 13 + 16, 2587 }; 2588 2589 static const struct panel_desc hitachi_tx23d38vm0caa = { 2590 .modes = &hitachi_tx23d38vm0caa_mode, 2591 .num_modes = 1, 2592 .bpc = 6, 2593 .size = { 2594 .width = 195, 2595 .height = 117, 2596 }, 2597 .delay = { 2598 .enable = 160, 2599 .disable = 160, 2600 }, 2601 }; 2602 2603 static const struct drm_display_mode innolux_at043tn24_mode = { 2604 .clock = 9000, 2605 .hdisplay = 480, 2606 .hsync_start = 480 + 2, 2607 .hsync_end = 480 + 2 + 41, 2608 .htotal = 480 + 2 + 41 + 2, 2609 .vdisplay = 272, 2610 .vsync_start = 272 + 2, 2611 .vsync_end = 272 + 2 + 10, 2612 .vtotal = 272 + 2 + 10 + 2, 2613 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2614 }; 2615 2616 static const struct panel_desc innolux_at043tn24 = { 2617 .modes = &innolux_at043tn24_mode, 2618 .num_modes = 1, 2619 .bpc = 8, 2620 .size = { 2621 .width = 95, 2622 .height = 54, 2623 }, 2624 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2625 .connector_type = DRM_MODE_CONNECTOR_DPI, 2626 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2627 }; 2628 2629 static const struct drm_display_mode innolux_at070tn92_mode = { 2630 .clock = 33333, 2631 .hdisplay = 800, 2632 .hsync_start = 800 + 210, 2633 .hsync_end = 800 + 210 + 20, 2634 .htotal = 800 + 210 + 20 + 46, 2635 .vdisplay = 480, 2636 .vsync_start = 480 + 22, 2637 .vsync_end = 480 + 22 + 10, 2638 .vtotal = 480 + 22 + 23 + 10, 2639 }; 2640 2641 static const struct panel_desc innolux_at070tn92 = { 2642 .modes = &innolux_at070tn92_mode, 2643 .num_modes = 1, 2644 .size = { 2645 .width = 154, 2646 .height = 86, 2647 }, 2648 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2649 }; 2650 2651 static const struct display_timing innolux_g070ace_l01_timing = { 2652 .pixelclock = { 25200000, 35000000, 35700000 }, 2653 .hactive = { 800, 800, 800 }, 2654 .hfront_porch = { 30, 32, 87 }, 2655 .hback_porch = { 30, 32, 87 }, 2656 .hsync_len = { 1, 1, 1 }, 2657 .vactive = { 480, 480, 480 }, 2658 .vfront_porch = { 3, 3, 3 }, 2659 .vback_porch = { 13, 13, 13 }, 2660 .vsync_len = { 1, 1, 4 }, 2661 .flags = DISPLAY_FLAGS_DE_HIGH, 2662 }; 2663 2664 static const struct panel_desc innolux_g070ace_l01 = { 2665 .timings = &innolux_g070ace_l01_timing, 2666 .num_timings = 1, 2667 .bpc = 8, 2668 .size = { 2669 .width = 152, 2670 .height = 91, 2671 }, 2672 .delay = { 2673 .prepare = 10, 2674 .enable = 50, 2675 .disable = 50, 2676 .unprepare = 500, 2677 }, 2678 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2679 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2680 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2681 }; 2682 2683 static const struct display_timing innolux_g070y2_l01_timing = { 2684 .pixelclock = { 28000000, 29500000, 32000000 }, 2685 .hactive = { 800, 800, 800 }, 2686 .hfront_porch = { 61, 91, 141 }, 2687 .hback_porch = { 60, 90, 140 }, 2688 .hsync_len = { 12, 12, 12 }, 2689 .vactive = { 480, 480, 480 }, 2690 .vfront_porch = { 4, 9, 30 }, 2691 .vback_porch = { 4, 8, 28 }, 2692 .vsync_len = { 2, 2, 2 }, 2693 .flags = DISPLAY_FLAGS_DE_HIGH, 2694 }; 2695 2696 static const struct panel_desc innolux_g070y2_l01 = { 2697 .timings = &innolux_g070y2_l01_timing, 2698 .num_timings = 1, 2699 .bpc = 8, 2700 .size = { 2701 .width = 152, 2702 .height = 91, 2703 }, 2704 .delay = { 2705 .prepare = 10, 2706 .enable = 100, 2707 .disable = 100, 2708 .unprepare = 800, 2709 }, 2710 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2711 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2712 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2713 }; 2714 2715 static const struct display_timing innolux_g070ace_lh3_timing = { 2716 .pixelclock = { 25200000, 25400000, 35700000 }, 2717 .hactive = { 800, 800, 800 }, 2718 .hfront_porch = { 30, 32, 87 }, 2719 .hback_porch = { 29, 31, 86 }, 2720 .hsync_len = { 1, 1, 1 }, 2721 .vactive = { 480, 480, 480 }, 2722 .vfront_porch = { 4, 5, 65 }, 2723 .vback_porch = { 3, 4, 65 }, 2724 .vsync_len = { 1, 1, 1 }, 2725 .flags = DISPLAY_FLAGS_DE_HIGH, 2726 }; 2727 2728 static const struct panel_desc innolux_g070ace_lh3 = { 2729 .timings = &innolux_g070ace_lh3_timing, 2730 .num_timings = 1, 2731 .bpc = 8, 2732 .size = { 2733 .width = 152, 2734 .height = 91, 2735 }, 2736 .delay = { 2737 .prepare = 10, 2738 .enable = 450, 2739 .disable = 200, 2740 .unprepare = 510, 2741 }, 2742 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2743 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2744 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2745 }; 2746 2747 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2748 .clock = 33333, 2749 .hdisplay = 800, 2750 .hsync_start = 800 + 210, 2751 .hsync_end = 800 + 210 + 20, 2752 .htotal = 800 + 210 + 20 + 46, 2753 .vdisplay = 480, 2754 .vsync_start = 480 + 22, 2755 .vsync_end = 480 + 22 + 10, 2756 .vtotal = 480 + 22 + 23 + 10, 2757 }; 2758 2759 static const struct panel_desc innolux_g070y2_t02 = { 2760 .modes = &innolux_g070y2_t02_mode, 2761 .num_modes = 1, 2762 .bpc = 8, 2763 .size = { 2764 .width = 152, 2765 .height = 92, 2766 }, 2767 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2768 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2769 .connector_type = DRM_MODE_CONNECTOR_DPI, 2770 }; 2771 2772 static const struct display_timing innolux_g101ice_l01_timing = { 2773 .pixelclock = { 60400000, 71100000, 74700000 }, 2774 .hactive = { 1280, 1280, 1280 }, 2775 .hfront_porch = { 30, 60, 70 }, 2776 .hback_porch = { 30, 60, 70 }, 2777 .hsync_len = { 22, 40, 60 }, 2778 .vactive = { 800, 800, 800 }, 2779 .vfront_porch = { 3, 8, 14 }, 2780 .vback_porch = { 3, 8, 14 }, 2781 .vsync_len = { 4, 7, 12 }, 2782 .flags = DISPLAY_FLAGS_DE_HIGH, 2783 }; 2784 2785 static const struct panel_desc innolux_g101ice_l01 = { 2786 .timings = &innolux_g101ice_l01_timing, 2787 .num_timings = 1, 2788 .bpc = 8, 2789 .size = { 2790 .width = 217, 2791 .height = 135, 2792 }, 2793 .delay = { 2794 .enable = 200, 2795 .disable = 200, 2796 }, 2797 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2798 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2799 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2800 }; 2801 2802 static const struct display_timing innolux_g121i1_l01_timing = { 2803 .pixelclock = { 67450000, 71000000, 74550000 }, 2804 .hactive = { 1280, 1280, 1280 }, 2805 .hfront_porch = { 40, 80, 160 }, 2806 .hback_porch = { 39, 79, 159 }, 2807 .hsync_len = { 1, 1, 1 }, 2808 .vactive = { 800, 800, 800 }, 2809 .vfront_porch = { 5, 11, 100 }, 2810 .vback_porch = { 4, 11, 99 }, 2811 .vsync_len = { 1, 1, 1 }, 2812 }; 2813 2814 static const struct panel_desc innolux_g121i1_l01 = { 2815 .timings = &innolux_g121i1_l01_timing, 2816 .num_timings = 1, 2817 .bpc = 6, 2818 .size = { 2819 .width = 261, 2820 .height = 163, 2821 }, 2822 .delay = { 2823 .enable = 200, 2824 .disable = 20, 2825 }, 2826 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2827 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2828 }; 2829 2830 static const struct display_timing innolux_g121x1_l03_timings = { 2831 .pixelclock = { 57500000, 64900000, 74400000 }, 2832 .hactive = { 1024, 1024, 1024 }, 2833 .hfront_porch = { 90, 140, 190 }, 2834 .hback_porch = { 90, 140, 190 }, 2835 .hsync_len = { 36, 40, 60 }, 2836 .vactive = { 768, 768, 768 }, 2837 .vfront_porch = { 2, 15, 30 }, 2838 .vback_porch = { 2, 15, 30 }, 2839 .vsync_len = { 2, 8, 20 }, 2840 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2841 }; 2842 2843 static const struct panel_desc innolux_g121x1_l03 = { 2844 .timings = &innolux_g121x1_l03_timings, 2845 .num_timings = 1, 2846 .bpc = 6, 2847 .size = { 2848 .width = 246, 2849 .height = 185, 2850 }, 2851 .delay = { 2852 .enable = 200, 2853 .unprepare = 200, 2854 .disable = 400, 2855 }, 2856 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2857 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2858 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2859 }; 2860 2861 static const struct panel_desc innolux_g121xce_l01 = { 2862 .timings = &innolux_g121x1_l03_timings, 2863 .num_timings = 1, 2864 .bpc = 8, 2865 .size = { 2866 .width = 246, 2867 .height = 185, 2868 }, 2869 .delay = { 2870 .enable = 200, 2871 .unprepare = 200, 2872 .disable = 400, 2873 }, 2874 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2875 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2876 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2877 }; 2878 2879 static const struct display_timing innolux_g150xge_l05_timing = { 2880 .pixelclock = { 53350000, 65000000, 80000000 }, 2881 .hactive = { 1024, 1024, 1024 }, 2882 .hfront_porch = { 58, 160, 288 }, 2883 .hback_porch = { 58, 160, 288 }, 2884 .hsync_len = { 1, 1, 1 }, 2885 .vactive = { 768, 768, 768 }, 2886 .vfront_porch = { 6, 19, 216 }, 2887 .vback_porch = { 6, 19, 216 }, 2888 .vsync_len = { 1, 1, 1 }, 2889 .flags = DISPLAY_FLAGS_DE_HIGH, 2890 }; 2891 2892 static const struct panel_desc innolux_g150xge_l05 = { 2893 .timings = &innolux_g150xge_l05_timing, 2894 .num_timings = 1, 2895 .bpc = 8, 2896 .size = { 2897 .width = 304, 2898 .height = 228, 2899 }, 2900 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2901 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2902 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2903 }; 2904 2905 static const struct display_timing innolux_g156hce_l01_timings = { 2906 .pixelclock = { 120000000, 141860000, 150000000 }, 2907 .hactive = { 1920, 1920, 1920 }, 2908 .hfront_porch = { 80, 90, 100 }, 2909 .hback_porch = { 80, 90, 100 }, 2910 .hsync_len = { 20, 30, 30 }, 2911 .vactive = { 1080, 1080, 1080 }, 2912 .vfront_porch = { 3, 10, 20 }, 2913 .vback_porch = { 3, 10, 20 }, 2914 .vsync_len = { 4, 10, 10 }, 2915 }; 2916 2917 static const struct panel_desc innolux_g156hce_l01 = { 2918 .timings = &innolux_g156hce_l01_timings, 2919 .num_timings = 1, 2920 .bpc = 8, 2921 .size = { 2922 .width = 344, 2923 .height = 194, 2924 }, 2925 .delay = { 2926 .prepare = 1, /* T1+T2 */ 2927 .enable = 450, /* T5 */ 2928 .disable = 200, /* T6 */ 2929 .unprepare = 10, /* T3+T7 */ 2930 }, 2931 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2932 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2933 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2934 }; 2935 2936 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2937 .clock = 69300, 2938 .hdisplay = 1366, 2939 .hsync_start = 1366 + 16, 2940 .hsync_end = 1366 + 16 + 34, 2941 .htotal = 1366 + 16 + 34 + 50, 2942 .vdisplay = 768, 2943 .vsync_start = 768 + 2, 2944 .vsync_end = 768 + 2 + 6, 2945 .vtotal = 768 + 2 + 6 + 12, 2946 }; 2947 2948 static const struct panel_desc innolux_n156bge_l21 = { 2949 .modes = &innolux_n156bge_l21_mode, 2950 .num_modes = 1, 2951 .bpc = 6, 2952 .size = { 2953 .width = 344, 2954 .height = 193, 2955 }, 2956 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2957 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2958 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2959 }; 2960 2961 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2962 .clock = 51501, 2963 .hdisplay = 1024, 2964 .hsync_start = 1024 + 128, 2965 .hsync_end = 1024 + 128 + 64, 2966 .htotal = 1024 + 128 + 64 + 128, 2967 .vdisplay = 600, 2968 .vsync_start = 600 + 16, 2969 .vsync_end = 600 + 16 + 4, 2970 .vtotal = 600 + 16 + 4 + 16, 2971 }; 2972 2973 static const struct panel_desc innolux_zj070na_01p = { 2974 .modes = &innolux_zj070na_01p_mode, 2975 .num_modes = 1, 2976 .bpc = 6, 2977 .size = { 2978 .width = 154, 2979 .height = 90, 2980 }, 2981 }; 2982 2983 static const struct display_timing jutouch_jt070tm041_timing = { 2984 .pixelclock = { 40800000, 51200000, 67200000 }, 2985 .hactive = { 1024, 1024, 1024 }, 2986 .hfront_porch = { 16, 160, 216 }, 2987 .hback_porch = { 160, 160, 160 }, 2988 .hsync_len = { 1, 1, 140 }, 2989 .vactive = { 600, 600, 600 }, 2990 .vfront_porch = { 1, 12, 127 }, 2991 .vback_porch = { 23, 23, 23 }, 2992 .vsync_len = { 1, 1, 20 }, 2993 }; 2994 2995 static const struct panel_desc jutouch_jt070tm041 = { 2996 .timings = &jutouch_jt070tm041_timing, 2997 .num_timings = 1, 2998 .bpc = 8, 2999 .size = { 3000 .width = 154, 3001 .height = 86, 3002 }, 3003 .delay = { 3004 .enable = 50, 3005 .disable = 50, 3006 }, 3007 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3008 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3009 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3010 }; 3011 3012 static const struct display_timing jutouch_jt101tm023_timing = { 3013 .pixelclock = { 66300000, 72400000, 78900000 }, 3014 .hactive = { 1280, 1280, 1280 }, 3015 .hfront_porch = { 12, 72, 132 }, 3016 .hback_porch = { 88, 88, 88 }, 3017 .hsync_len = { 10, 10, 48 }, 3018 .vactive = { 800, 800, 800 }, 3019 .vfront_porch = { 1, 15, 49 }, 3020 .vback_porch = { 23, 23, 23 }, 3021 .vsync_len = { 5, 6, 13 }, 3022 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3023 DISPLAY_FLAGS_DE_HIGH, 3024 }; 3025 3026 static const struct panel_desc jutouch_jt101tm023 = { 3027 .timings = &jutouch_jt101tm023_timing, 3028 .num_timings = 1, 3029 .bpc = 8, 3030 .size = { 3031 .width = 217, 3032 .height = 136, 3033 }, 3034 .delay = { 3035 .enable = 50, 3036 .disable = 50, 3037 }, 3038 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3039 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3040 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3041 }; 3042 3043 3044 static const struct display_timing koe_tx14d24vm1bpa_timing = { 3045 .pixelclock = { 5580000, 5850000, 6200000 }, 3046 .hactive = { 320, 320, 320 }, 3047 .hfront_porch = { 30, 30, 30 }, 3048 .hback_porch = { 30, 30, 30 }, 3049 .hsync_len = { 1, 5, 17 }, 3050 .vactive = { 240, 240, 240 }, 3051 .vfront_porch = { 6, 6, 6 }, 3052 .vback_porch = { 5, 5, 5 }, 3053 .vsync_len = { 1, 2, 11 }, 3054 .flags = DISPLAY_FLAGS_DE_HIGH, 3055 }; 3056 3057 static const struct panel_desc koe_tx14d24vm1bpa = { 3058 .timings = &koe_tx14d24vm1bpa_timing, 3059 .num_timings = 1, 3060 .bpc = 6, 3061 .size = { 3062 .width = 115, 3063 .height = 86, 3064 }, 3065 }; 3066 3067 static const struct display_timing koe_tx26d202vm0bwa_timing = { 3068 .pixelclock = { 151820000, 156720000, 159780000 }, 3069 .hactive = { 1920, 1920, 1920 }, 3070 .hfront_porch = { 105, 130, 142 }, 3071 .hback_porch = { 45, 70, 82 }, 3072 .hsync_len = { 30, 30, 30 }, 3073 .vactive = { 1200, 1200, 1200}, 3074 .vfront_porch = { 3, 5, 10 }, 3075 .vback_porch = { 2, 5, 10 }, 3076 .vsync_len = { 5, 5, 5 }, 3077 .flags = DISPLAY_FLAGS_DE_HIGH, 3078 }; 3079 3080 static const struct panel_desc koe_tx26d202vm0bwa = { 3081 .timings = &koe_tx26d202vm0bwa_timing, 3082 .num_timings = 1, 3083 .bpc = 8, 3084 .size = { 3085 .width = 217, 3086 .height = 136, 3087 }, 3088 .delay = { 3089 .prepare = 1000, 3090 .enable = 1000, 3091 .unprepare = 1000, 3092 .disable = 1000, 3093 }, 3094 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3095 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3096 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3097 }; 3098 3099 static const struct display_timing koe_tx31d200vm0baa_timing = { 3100 .pixelclock = { 39600000, 43200000, 48000000 }, 3101 .hactive = { 1280, 1280, 1280 }, 3102 .hfront_porch = { 16, 36, 56 }, 3103 .hback_porch = { 16, 36, 56 }, 3104 .hsync_len = { 8, 8, 8 }, 3105 .vactive = { 480, 480, 480 }, 3106 .vfront_porch = { 6, 21, 33 }, 3107 .vback_porch = { 6, 21, 33 }, 3108 .vsync_len = { 8, 8, 8 }, 3109 .flags = DISPLAY_FLAGS_DE_HIGH, 3110 }; 3111 3112 static const struct panel_desc koe_tx31d200vm0baa = { 3113 .timings = &koe_tx31d200vm0baa_timing, 3114 .num_timings = 1, 3115 .bpc = 6, 3116 .size = { 3117 .width = 292, 3118 .height = 109, 3119 }, 3120 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3121 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3122 }; 3123 3124 static const struct display_timing kyo_tcg121xglp_timing = { 3125 .pixelclock = { 52000000, 65000000, 71000000 }, 3126 .hactive = { 1024, 1024, 1024 }, 3127 .hfront_porch = { 2, 2, 2 }, 3128 .hback_porch = { 2, 2, 2 }, 3129 .hsync_len = { 86, 124, 244 }, 3130 .vactive = { 768, 768, 768 }, 3131 .vfront_porch = { 2, 2, 2 }, 3132 .vback_porch = { 2, 2, 2 }, 3133 .vsync_len = { 6, 34, 73 }, 3134 .flags = DISPLAY_FLAGS_DE_HIGH, 3135 }; 3136 3137 static const struct panel_desc kyo_tcg121xglp = { 3138 .timings = &kyo_tcg121xglp_timing, 3139 .num_timings = 1, 3140 .bpc = 8, 3141 .size = { 3142 .width = 246, 3143 .height = 184, 3144 }, 3145 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3146 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3147 }; 3148 3149 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 3150 .clock = 7000, 3151 .hdisplay = 320, 3152 .hsync_start = 320 + 20, 3153 .hsync_end = 320 + 20 + 30, 3154 .htotal = 320 + 20 + 30 + 38, 3155 .vdisplay = 240, 3156 .vsync_start = 240 + 4, 3157 .vsync_end = 240 + 4 + 3, 3158 .vtotal = 240 + 4 + 3 + 15, 3159 }; 3160 3161 static const struct panel_desc lemaker_bl035_rgb_002 = { 3162 .modes = &lemaker_bl035_rgb_002_mode, 3163 .num_modes = 1, 3164 .size = { 3165 .width = 70, 3166 .height = 52, 3167 }, 3168 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3169 .bus_flags = DRM_BUS_FLAG_DE_LOW, 3170 }; 3171 3172 static const struct display_timing lg_lb070wv8_timing = { 3173 .pixelclock = { 31950000, 33260000, 34600000 }, 3174 .hactive = { 800, 800, 800 }, 3175 .hfront_porch = { 88, 88, 88 }, 3176 .hback_porch = { 88, 88, 88 }, 3177 .hsync_len = { 80, 80, 80 }, 3178 .vactive = { 480, 480, 480 }, 3179 .vfront_porch = { 10, 10, 10 }, 3180 .vback_porch = { 10, 10, 10 }, 3181 .vsync_len = { 25, 25, 25 }, 3182 }; 3183 3184 static const struct panel_desc lg_lb070wv8 = { 3185 .timings = &lg_lb070wv8_timing, 3186 .num_timings = 1, 3187 .bpc = 8, 3188 .size = { 3189 .width = 151, 3190 .height = 91, 3191 }, 3192 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3193 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3194 }; 3195 3196 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 3197 .clock = 155127, 3198 .hdisplay = 1920, 3199 .hsync_start = 1920 + 128, 3200 .hsync_end = 1920 + 128 + 20, 3201 .htotal = 1920 + 128 + 20 + 12, 3202 .vdisplay = 1200, 3203 .vsync_start = 1200 + 19, 3204 .vsync_end = 1200 + 19 + 4, 3205 .vtotal = 1200 + 19 + 4 + 20, 3206 }; 3207 3208 static const struct panel_desc lincolntech_lcd185_101ct = { 3209 .modes = &lincolntech_lcd185_101ct_mode, 3210 .bpc = 8, 3211 .num_modes = 1, 3212 .size = { 3213 .width = 217, 3214 .height = 136, 3215 }, 3216 .delay = { 3217 .prepare = 50, 3218 .disable = 50, 3219 }, 3220 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3221 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3222 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3223 }; 3224 3225 static const struct display_timing logictechno_lt161010_2nh_timing = { 3226 .pixelclock = { 26400000, 33300000, 46800000 }, 3227 .hactive = { 800, 800, 800 }, 3228 .hfront_porch = { 16, 210, 354 }, 3229 .hback_porch = { 46, 46, 46 }, 3230 .hsync_len = { 1, 20, 40 }, 3231 .vactive = { 480, 480, 480 }, 3232 .vfront_porch = { 7, 22, 147 }, 3233 .vback_porch = { 23, 23, 23 }, 3234 .vsync_len = { 1, 10, 20 }, 3235 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3236 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3237 DISPLAY_FLAGS_SYNC_POSEDGE, 3238 }; 3239 3240 static const struct panel_desc logictechno_lt161010_2nh = { 3241 .timings = &logictechno_lt161010_2nh_timing, 3242 .num_timings = 1, 3243 .bpc = 6, 3244 .size = { 3245 .width = 154, 3246 .height = 86, 3247 }, 3248 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3249 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3250 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3251 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3252 .connector_type = DRM_MODE_CONNECTOR_DPI, 3253 }; 3254 3255 static const struct display_timing logictechno_lt170410_2whc_timing = { 3256 .pixelclock = { 68900000, 71100000, 73400000 }, 3257 .hactive = { 1280, 1280, 1280 }, 3258 .hfront_porch = { 23, 60, 71 }, 3259 .hback_porch = { 23, 60, 71 }, 3260 .hsync_len = { 15, 40, 47 }, 3261 .vactive = { 800, 800, 800 }, 3262 .vfront_porch = { 5, 7, 10 }, 3263 .vback_porch = { 5, 7, 10 }, 3264 .vsync_len = { 6, 9, 12 }, 3265 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3266 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3267 DISPLAY_FLAGS_SYNC_POSEDGE, 3268 }; 3269 3270 static const struct panel_desc logictechno_lt170410_2whc = { 3271 .timings = &logictechno_lt170410_2whc_timing, 3272 .num_timings = 1, 3273 .bpc = 8, 3274 .size = { 3275 .width = 217, 3276 .height = 136, 3277 }, 3278 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3279 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3280 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3281 }; 3282 3283 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3284 .clock = 33000, 3285 .hdisplay = 800, 3286 .hsync_start = 800 + 112, 3287 .hsync_end = 800 + 112 + 3, 3288 .htotal = 800 + 112 + 3 + 85, 3289 .vdisplay = 480, 3290 .vsync_start = 480 + 38, 3291 .vsync_end = 480 + 38 + 3, 3292 .vtotal = 480 + 38 + 3 + 29, 3293 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3294 }; 3295 3296 static const struct panel_desc logictechno_lttd800480070_l2rt = { 3297 .modes = &logictechno_lttd800480070_l2rt_mode, 3298 .num_modes = 1, 3299 .bpc = 8, 3300 .size = { 3301 .width = 154, 3302 .height = 86, 3303 }, 3304 .delay = { 3305 .prepare = 45, 3306 .enable = 100, 3307 .disable = 100, 3308 .unprepare = 45 3309 }, 3310 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3311 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3312 .connector_type = DRM_MODE_CONNECTOR_DPI, 3313 }; 3314 3315 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3316 .clock = 33000, 3317 .hdisplay = 800, 3318 .hsync_start = 800 + 154, 3319 .hsync_end = 800 + 154 + 3, 3320 .htotal = 800 + 154 + 3 + 43, 3321 .vdisplay = 480, 3322 .vsync_start = 480 + 47, 3323 .vsync_end = 480 + 47 + 3, 3324 .vtotal = 480 + 47 + 3 + 20, 3325 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3326 }; 3327 3328 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3329 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3330 .num_modes = 1, 3331 .bpc = 8, 3332 .size = { 3333 .width = 154, 3334 .height = 86, 3335 }, 3336 .delay = { 3337 .prepare = 45, 3338 .enable = 100, 3339 .disable = 100, 3340 .unprepare = 45 3341 }, 3342 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3343 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3344 .connector_type = DRM_MODE_CONNECTOR_DPI, 3345 }; 3346 3347 static const struct drm_display_mode logicpd_type_28_mode = { 3348 .clock = 9107, 3349 .hdisplay = 480, 3350 .hsync_start = 480 + 3, 3351 .hsync_end = 480 + 3 + 42, 3352 .htotal = 480 + 3 + 42 + 2, 3353 3354 .vdisplay = 272, 3355 .vsync_start = 272 + 2, 3356 .vsync_end = 272 + 2 + 11, 3357 .vtotal = 272 + 2 + 11 + 3, 3358 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3359 }; 3360 3361 static const struct panel_desc logicpd_type_28 = { 3362 .modes = &logicpd_type_28_mode, 3363 .num_modes = 1, 3364 .bpc = 8, 3365 .size = { 3366 .width = 105, 3367 .height = 67, 3368 }, 3369 .delay = { 3370 .prepare = 200, 3371 .enable = 200, 3372 .unprepare = 200, 3373 .disable = 200, 3374 }, 3375 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3376 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3377 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3378 .connector_type = DRM_MODE_CONNECTOR_DPI, 3379 }; 3380 3381 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3382 .clock = 150275, 3383 .hdisplay = 1920, 3384 .hsync_start = 1920 + 32, 3385 .hsync_end = 1920 + 32 + 52, 3386 .htotal = 1920 + 32 + 52 + 24, 3387 .vdisplay = 1200, 3388 .vsync_start = 1200 + 24, 3389 .vsync_end = 1200 + 24 + 8, 3390 .vtotal = 1200 + 24 + 8 + 3, 3391 }; 3392 3393 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3394 .modes = µtips_mf_101hiebcaf0_c_mode, 3395 .bpc = 8, 3396 .num_modes = 1, 3397 .size = { 3398 .width = 217, 3399 .height = 136, 3400 }, 3401 .delay = { 3402 .prepare = 50, 3403 .disable = 50, 3404 }, 3405 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3406 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3407 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3408 }; 3409 3410 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3411 .clock = 93301, 3412 .hdisplay = 1920, 3413 .hsync_start = 1920 + 72, 3414 .hsync_end = 1920 + 72 + 72, 3415 .htotal = 1920 + 72 + 72 + 72, 3416 .vdisplay = 720, 3417 .vsync_start = 720 + 3, 3418 .vsync_end = 720 + 3 + 3, 3419 .vtotal = 720 + 3 + 3 + 2, 3420 }; 3421 3422 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3423 .modes = µtips_mf_103hieb0ga0_mode, 3424 .bpc = 8, 3425 .num_modes = 1, 3426 .size = { 3427 .width = 244, 3428 .height = 92, 3429 }, 3430 .delay = { 3431 .prepare = 50, 3432 .disable = 50, 3433 }, 3434 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3435 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3436 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3437 }; 3438 3439 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3440 .clock = 30400, 3441 .hdisplay = 800, 3442 .hsync_start = 800 + 0, 3443 .hsync_end = 800 + 1, 3444 .htotal = 800 + 0 + 1 + 160, 3445 .vdisplay = 480, 3446 .vsync_start = 480 + 0, 3447 .vsync_end = 480 + 48 + 1, 3448 .vtotal = 480 + 48 + 1 + 0, 3449 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3450 }; 3451 3452 static const struct panel_desc mitsubishi_aa070mc01 = { 3453 .modes = &mitsubishi_aa070mc01_mode, 3454 .num_modes = 1, 3455 .bpc = 8, 3456 .size = { 3457 .width = 152, 3458 .height = 91, 3459 }, 3460 3461 .delay = { 3462 .enable = 200, 3463 .unprepare = 200, 3464 .disable = 400, 3465 }, 3466 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3467 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3468 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3469 }; 3470 3471 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3472 .clock = 56234, 3473 .hdisplay = 1024, 3474 .hsync_start = 1024 + 24, 3475 .hsync_end = 1024 + 24 + 63, 3476 .htotal = 1024 + 24 + 63 + 1, 3477 .vdisplay = 768, 3478 .vsync_start = 768 + 3, 3479 .vsync_end = 768 + 3 + 6, 3480 .vtotal = 768 + 3 + 6 + 1, 3481 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3482 }; 3483 3484 static const struct panel_desc mitsubishi_aa084xe01 = { 3485 .modes = &mitsubishi_aa084xe01_mode, 3486 .num_modes = 1, 3487 .bpc = 8, 3488 .size = { 3489 .width = 1024, 3490 .height = 768, 3491 }, 3492 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3493 .connector_type = DRM_MODE_CONNECTOR_DPI, 3494 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3495 }; 3496 3497 static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3498 .pixelclock = { 26400000, 33000000, 46800000 }, 3499 .hactive = { 800, 800, 800 }, 3500 .hfront_porch = { 16, 204, 354 }, 3501 .hback_porch = { 46, 46, 46 }, 3502 .hsync_len = { 1, 6, 40 }, 3503 .vactive = { 480, 480, 480 }, 3504 .vfront_porch = { 7, 22, 147 }, 3505 .vback_porch = { 23, 23, 23 }, 3506 .vsync_len = { 1, 3, 20 }, 3507 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3508 DISPLAY_FLAGS_DE_HIGH, 3509 }; 3510 3511 static const struct panel_desc multi_inno_mi0700a2t_30 = { 3512 .timings = &multi_inno_mi0700a2t_30_timing, 3513 .num_timings = 1, 3514 .bpc = 6, 3515 .size = { 3516 .width = 153, 3517 .height = 92, 3518 }, 3519 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3520 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3521 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3522 }; 3523 3524 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3525 .pixelclock = { 29000000, 33000000, 38000000 }, 3526 .hactive = { 800, 800, 800 }, 3527 .hfront_porch = { 180, 210, 240 }, 3528 .hback_porch = { 16, 16, 16 }, 3529 .hsync_len = { 30, 30, 30 }, 3530 .vactive = { 480, 480, 480 }, 3531 .vfront_porch = { 12, 22, 32 }, 3532 .vback_porch = { 10, 10, 10 }, 3533 .vsync_len = { 13, 13, 13 }, 3534 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3535 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3536 DISPLAY_FLAGS_SYNC_POSEDGE, 3537 }; 3538 3539 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3540 .timings = &multi_inno_mi0700s4t_6_timing, 3541 .num_timings = 1, 3542 .bpc = 8, 3543 .size = { 3544 .width = 154, 3545 .height = 86, 3546 }, 3547 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3548 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3549 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3550 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3551 .connector_type = DRM_MODE_CONNECTOR_DPI, 3552 }; 3553 3554 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3555 .pixelclock = { 32000000, 40000000, 50000000 }, 3556 .hactive = { 800, 800, 800 }, 3557 .hfront_porch = { 16, 210, 354 }, 3558 .hback_porch = { 6, 26, 45 }, 3559 .hsync_len = { 1, 20, 40 }, 3560 .vactive = { 600, 600, 600 }, 3561 .vfront_porch = { 1, 12, 77 }, 3562 .vback_porch = { 3, 13, 22 }, 3563 .vsync_len = { 1, 10, 20 }, 3564 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3565 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3566 DISPLAY_FLAGS_SYNC_POSEDGE, 3567 }; 3568 3569 static const struct panel_desc multi_inno_mi0800ft_9 = { 3570 .timings = &multi_inno_mi0800ft_9_timing, 3571 .num_timings = 1, 3572 .bpc = 8, 3573 .size = { 3574 .width = 162, 3575 .height = 122, 3576 }, 3577 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3578 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3579 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3580 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3581 .connector_type = DRM_MODE_CONNECTOR_DPI, 3582 }; 3583 3584 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3585 .pixelclock = { 68900000, 70000000, 73400000 }, 3586 .hactive = { 1280, 1280, 1280 }, 3587 .hfront_porch = { 30, 60, 71 }, 3588 .hback_porch = { 30, 60, 71 }, 3589 .hsync_len = { 10, 10, 48 }, 3590 .vactive = { 800, 800, 800 }, 3591 .vfront_porch = { 5, 10, 10 }, 3592 .vback_porch = { 5, 10, 10 }, 3593 .vsync_len = { 5, 6, 13 }, 3594 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3595 DISPLAY_FLAGS_DE_HIGH, 3596 }; 3597 3598 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3599 .timings = &multi_inno_mi1010ait_1cp_timing, 3600 .num_timings = 1, 3601 .bpc = 8, 3602 .size = { 3603 .width = 217, 3604 .height = 136, 3605 }, 3606 .delay = { 3607 .enable = 50, 3608 .disable = 50, 3609 }, 3610 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3611 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3612 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3613 }; 3614 3615 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3616 .pixelclock = { 40800000, 51200000, 67200000 }, 3617 .hactive = { 1024, 1024, 1024 }, 3618 .hfront_porch = { 30, 110, 130 }, 3619 .hback_porch = { 30, 110, 130 }, 3620 .hsync_len = { 30, 100, 116 }, 3621 .vactive = { 600, 600, 600 }, 3622 .vfront_porch = { 4, 13, 80 }, 3623 .vback_porch = { 4, 13, 80 }, 3624 .vsync_len = { 2, 9, 40 }, 3625 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3626 DISPLAY_FLAGS_DE_HIGH, 3627 }; 3628 3629 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3630 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3631 .num_timings = 1, 3632 .bpc = 6, 3633 .size = { 3634 .width = 260, 3635 .height = 162, 3636 }, 3637 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3638 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3639 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3640 }; 3641 3642 static const struct display_timing nec_nl12880bc20_05_timing = { 3643 .pixelclock = { 67000000, 71000000, 75000000 }, 3644 .hactive = { 1280, 1280, 1280 }, 3645 .hfront_porch = { 2, 30, 30 }, 3646 .hback_porch = { 6, 100, 100 }, 3647 .hsync_len = { 2, 30, 30 }, 3648 .vactive = { 800, 800, 800 }, 3649 .vfront_porch = { 5, 5, 5 }, 3650 .vback_porch = { 11, 11, 11 }, 3651 .vsync_len = { 7, 7, 7 }, 3652 }; 3653 3654 static const struct panel_desc nec_nl12880bc20_05 = { 3655 .timings = &nec_nl12880bc20_05_timing, 3656 .num_timings = 1, 3657 .bpc = 8, 3658 .size = { 3659 .width = 261, 3660 .height = 163, 3661 }, 3662 .delay = { 3663 .enable = 50, 3664 .disable = 50, 3665 }, 3666 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3667 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3668 }; 3669 3670 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3671 .clock = 10870, 3672 .hdisplay = 480, 3673 .hsync_start = 480 + 2, 3674 .hsync_end = 480 + 2 + 41, 3675 .htotal = 480 + 2 + 41 + 2, 3676 .vdisplay = 272, 3677 .vsync_start = 272 + 2, 3678 .vsync_end = 272 + 2 + 4, 3679 .vtotal = 272 + 2 + 4 + 2, 3680 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3681 }; 3682 3683 static const struct panel_desc nec_nl4827hc19_05b = { 3684 .modes = &nec_nl4827hc19_05b_mode, 3685 .num_modes = 1, 3686 .bpc = 8, 3687 .size = { 3688 .width = 95, 3689 .height = 54, 3690 }, 3691 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3692 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3693 }; 3694 3695 static const struct drm_display_mode netron_dy_e231732_mode = { 3696 .clock = 66000, 3697 .hdisplay = 1024, 3698 .hsync_start = 1024 + 160, 3699 .hsync_end = 1024 + 160 + 70, 3700 .htotal = 1024 + 160 + 70 + 90, 3701 .vdisplay = 600, 3702 .vsync_start = 600 + 127, 3703 .vsync_end = 600 + 127 + 20, 3704 .vtotal = 600 + 127 + 20 + 3, 3705 }; 3706 3707 static const struct panel_desc netron_dy_e231732 = { 3708 .modes = &netron_dy_e231732_mode, 3709 .num_modes = 1, 3710 .size = { 3711 .width = 154, 3712 .height = 87, 3713 }, 3714 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3715 }; 3716 3717 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3718 .clock = 9000, 3719 .hdisplay = 480, 3720 .hsync_start = 480 + 2, 3721 .hsync_end = 480 + 2 + 41, 3722 .htotal = 480 + 2 + 41 + 2, 3723 .vdisplay = 272, 3724 .vsync_start = 272 + 2, 3725 .vsync_end = 272 + 2 + 10, 3726 .vtotal = 272 + 2 + 10 + 2, 3727 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3728 }; 3729 3730 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3731 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3732 .num_modes = 1, 3733 .bpc = 8, 3734 .size = { 3735 .width = 95, 3736 .height = 54, 3737 }, 3738 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3739 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3740 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3741 .connector_type = DRM_MODE_CONNECTOR_DPI, 3742 }; 3743 3744 static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { 3745 .clock = 75400, 3746 .hdisplay = 1366, 3747 .hsync_start = 1366 + 14, 3748 .hsync_end = 1366 + 14 + 56, 3749 .htotal = 1366 + 14 + 56 + 64, 3750 .vdisplay = 768, 3751 .vsync_start = 768 + 1, 3752 .vsync_end = 768 + 1 + 3, 3753 .vtotal = 768 + 1 + 3 + 22, 3754 }; 3755 3756 static const struct panel_desc nlt_nl13676bc25_03f = { 3757 .modes = &nlt_nl13676bc25_03f_mode, 3758 .num_modes = 1, 3759 .bpc = 8, 3760 .size = { 3761 .width = 363, 3762 .height = 215, 3763 }, 3764 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3765 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3766 }; 3767 3768 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3769 .pixelclock = { 130000000, 148350000, 163000000 }, 3770 .hactive = { 1920, 1920, 1920 }, 3771 .hfront_porch = { 80, 100, 100 }, 3772 .hback_porch = { 100, 120, 120 }, 3773 .hsync_len = { 50, 60, 60 }, 3774 .vactive = { 1080, 1080, 1080 }, 3775 .vfront_porch = { 12, 30, 30 }, 3776 .vback_porch = { 4, 10, 10 }, 3777 .vsync_len = { 4, 5, 5 }, 3778 }; 3779 3780 static const struct panel_desc nlt_nl192108ac18_02d = { 3781 .timings = &nlt_nl192108ac18_02d_timing, 3782 .num_timings = 1, 3783 .bpc = 8, 3784 .size = { 3785 .width = 344, 3786 .height = 194, 3787 }, 3788 .delay = { 3789 .unprepare = 500, 3790 }, 3791 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3792 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3793 }; 3794 3795 static const struct drm_display_mode nvd_9128_mode = { 3796 .clock = 29500, 3797 .hdisplay = 800, 3798 .hsync_start = 800 + 130, 3799 .hsync_end = 800 + 130 + 98, 3800 .htotal = 800 + 0 + 130 + 98, 3801 .vdisplay = 480, 3802 .vsync_start = 480 + 10, 3803 .vsync_end = 480 + 10 + 50, 3804 .vtotal = 480 + 0 + 10 + 50, 3805 }; 3806 3807 static const struct panel_desc nvd_9128 = { 3808 .modes = &nvd_9128_mode, 3809 .num_modes = 1, 3810 .bpc = 8, 3811 .size = { 3812 .width = 156, 3813 .height = 88, 3814 }, 3815 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3816 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3817 }; 3818 3819 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3820 .pixelclock = { 30000000, 30000000, 40000000 }, 3821 .hactive = { 800, 800, 800 }, 3822 .hfront_porch = { 40, 40, 40 }, 3823 .hback_porch = { 40, 40, 40 }, 3824 .hsync_len = { 1, 48, 48 }, 3825 .vactive = { 480, 480, 480 }, 3826 .vfront_porch = { 13, 13, 13 }, 3827 .vback_porch = { 29, 29, 29 }, 3828 .vsync_len = { 3, 3, 3 }, 3829 .flags = DISPLAY_FLAGS_DE_HIGH, 3830 }; 3831 3832 static const struct panel_desc okaya_rs800480t_7x0gp = { 3833 .timings = &okaya_rs800480t_7x0gp_timing, 3834 .num_timings = 1, 3835 .bpc = 6, 3836 .size = { 3837 .width = 154, 3838 .height = 87, 3839 }, 3840 .delay = { 3841 .prepare = 41, 3842 .enable = 50, 3843 .unprepare = 41, 3844 .disable = 50, 3845 }, 3846 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3847 }; 3848 3849 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3850 .clock = 9000, 3851 .hdisplay = 480, 3852 .hsync_start = 480 + 5, 3853 .hsync_end = 480 + 5 + 30, 3854 .htotal = 480 + 5 + 30 + 10, 3855 .vdisplay = 272, 3856 .vsync_start = 272 + 8, 3857 .vsync_end = 272 + 8 + 5, 3858 .vtotal = 272 + 8 + 5 + 3, 3859 }; 3860 3861 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3862 .modes = &olimex_lcd_olinuxino_43ts_mode, 3863 .num_modes = 1, 3864 .size = { 3865 .width = 95, 3866 .height = 54, 3867 }, 3868 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3869 }; 3870 3871 static const struct drm_display_mode olimex_lcd_olinuxino_5cts_mode = { 3872 .clock = 33300, 3873 .hdisplay = 800, 3874 .hsync_start = 800 + 210, 3875 .hsync_end = 800 + 210 + 20, 3876 .htotal = 800 + 210 + 20 + 26, 3877 .vdisplay = 480, 3878 .vsync_start = 480 + 22, 3879 .vsync_end = 480 + 22 + 10, 3880 .vtotal = 480 + 22 + 10 + 13, 3881 }; 3882 3883 static const struct panel_desc olimex_lcd_olinuxino_5cts = { 3884 .modes = &olimex_lcd_olinuxino_5cts_mode, 3885 .num_modes = 1, 3886 .size = { 3887 .width = 154, 3888 .height = 86, 3889 }, 3890 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3891 }; 3892 3893 3894 static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 3895 .pixelclock = { 30000000, 30000000, 50000000 }, 3896 .hactive = { 800, 800, 800 }, 3897 .hfront_porch = { 1, 40, 255 }, 3898 .hback_porch = { 1, 40, 87 }, 3899 .hsync_len = { 1, 48, 87 }, 3900 .vactive = { 480, 480, 480 }, 3901 .vfront_porch = { 1, 13, 255 }, 3902 .vback_porch = { 1, 29, 29 }, 3903 .vsync_len = { 3, 3, 31 }, 3904 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3905 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3906 }; 3907 3908 static const struct panel_desc ontat_kd50g21_40nt_a1 = { 3909 .timings = &ontat_kd50g21_40nt_a1_timing, 3910 .num_timings = 1, 3911 .bpc = 8, 3912 .size = { 3913 .width = 108, 3914 .height = 65, 3915 }, 3916 .delay = { 3917 .prepare = 147, /* 5 VSDs */ 3918 .enable = 147, /* 5 VSDs */ 3919 .disable = 88, /* 3 VSDs */ 3920 .unprepare = 117, /* 4 VSDs */ 3921 }, 3922 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3923 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3924 .connector_type = DRM_MODE_CONNECTOR_DPI, 3925 }; 3926 3927 /* 3928 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3929 * pixel clocks, but this is the timing that was being used in the Adafruit 3930 * installation instructions. 3931 */ 3932 static const struct drm_display_mode ontat_yx700wv03_mode = { 3933 .clock = 29500, 3934 .hdisplay = 800, 3935 .hsync_start = 824, 3936 .hsync_end = 896, 3937 .htotal = 992, 3938 .vdisplay = 480, 3939 .vsync_start = 483, 3940 .vsync_end = 493, 3941 .vtotal = 500, 3942 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3943 }; 3944 3945 /* 3946 * Specification at: 3947 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3948 */ 3949 static const struct panel_desc ontat_yx700wv03 = { 3950 .modes = &ontat_yx700wv03_mode, 3951 .num_modes = 1, 3952 .bpc = 8, 3953 .size = { 3954 .width = 154, 3955 .height = 83, 3956 }, 3957 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3958 }; 3959 3960 static const struct drm_display_mode ortustech_com37h3m_mode = { 3961 .clock = 22230, 3962 .hdisplay = 480, 3963 .hsync_start = 480 + 40, 3964 .hsync_end = 480 + 40 + 10, 3965 .htotal = 480 + 40 + 10 + 40, 3966 .vdisplay = 640, 3967 .vsync_start = 640 + 4, 3968 .vsync_end = 640 + 4 + 2, 3969 .vtotal = 640 + 4 + 2 + 4, 3970 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3971 }; 3972 3973 static const struct panel_desc ortustech_com37h3m = { 3974 .modes = &ortustech_com37h3m_mode, 3975 .num_modes = 1, 3976 .bpc = 8, 3977 .size = { 3978 .width = 56, /* 56.16mm */ 3979 .height = 75, /* 74.88mm */ 3980 }, 3981 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3982 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3983 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3984 }; 3985 3986 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3987 .clock = 25000, 3988 .hdisplay = 480, 3989 .hsync_start = 480 + 10, 3990 .hsync_end = 480 + 10 + 10, 3991 .htotal = 480 + 10 + 10 + 15, 3992 .vdisplay = 800, 3993 .vsync_start = 800 + 3, 3994 .vsync_end = 800 + 3 + 3, 3995 .vtotal = 800 + 3 + 3 + 3, 3996 }; 3997 3998 static const struct panel_desc ortustech_com43h4m85ulc = { 3999 .modes = &ortustech_com43h4m85ulc_mode, 4000 .num_modes = 1, 4001 .bpc = 6, 4002 .size = { 4003 .width = 56, 4004 .height = 93, 4005 }, 4006 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4007 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4008 .connector_type = DRM_MODE_CONNECTOR_DPI, 4009 }; 4010 4011 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 4012 .clock = 33000, 4013 .hdisplay = 800, 4014 .hsync_start = 800 + 210, 4015 .hsync_end = 800 + 210 + 30, 4016 .htotal = 800 + 210 + 30 + 16, 4017 .vdisplay = 480, 4018 .vsync_start = 480 + 22, 4019 .vsync_end = 480 + 22 + 13, 4020 .vtotal = 480 + 22 + 13 + 10, 4021 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4022 }; 4023 4024 static const struct panel_desc osddisplays_osd070t1718_19ts = { 4025 .modes = &osddisplays_osd070t1718_19ts_mode, 4026 .num_modes = 1, 4027 .bpc = 8, 4028 .size = { 4029 .width = 152, 4030 .height = 91, 4031 }, 4032 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4033 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 4034 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4035 .connector_type = DRM_MODE_CONNECTOR_DPI, 4036 }; 4037 4038 static const struct drm_display_mode pda_91_00156_a0_mode = { 4039 .clock = 33300, 4040 .hdisplay = 800, 4041 .hsync_start = 800 + 1, 4042 .hsync_end = 800 + 1 + 64, 4043 .htotal = 800 + 1 + 64 + 64, 4044 .vdisplay = 480, 4045 .vsync_start = 480 + 1, 4046 .vsync_end = 480 + 1 + 23, 4047 .vtotal = 480 + 1 + 23 + 22, 4048 }; 4049 4050 static const struct panel_desc pda_91_00156_a0 = { 4051 .modes = &pda_91_00156_a0_mode, 4052 .num_modes = 1, 4053 .size = { 4054 .width = 152, 4055 .height = 91, 4056 }, 4057 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4058 }; 4059 4060 static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { 4061 .clock = 71150, 4062 .hdisplay = 1280, 4063 .hsync_start = 1280 + 48, 4064 .hsync_end = 1280 + 48 + 32, 4065 .htotal = 1280 + 48 + 32 + 80, 4066 .vdisplay = 800, 4067 .vsync_start = 800 + 9, 4068 .vsync_end = 800 + 9 + 8, 4069 .vtotal = 800 + 9 + 8 + 6, 4070 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4071 }; 4072 4073 static const struct panel_desc powertip_ph128800t004_zza01 = { 4074 .modes = &powertip_ph128800t004_zza01_mode, 4075 .num_modes = 1, 4076 .bpc = 8, 4077 .size = { 4078 .width = 216, 4079 .height = 135, 4080 }, 4081 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4082 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4083 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4084 }; 4085 4086 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 4087 .clock = 66500, 4088 .hdisplay = 1280, 4089 .hsync_start = 1280 + 12, 4090 .hsync_end = 1280 + 12 + 20, 4091 .htotal = 1280 + 12 + 20 + 56, 4092 .vdisplay = 800, 4093 .vsync_start = 800 + 1, 4094 .vsync_end = 800 + 1 + 3, 4095 .vtotal = 800 + 1 + 3 + 20, 4096 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4097 }; 4098 4099 static const struct panel_desc powertip_ph128800t006_zhc01 = { 4100 .modes = &powertip_ph128800t006_zhc01_mode, 4101 .num_modes = 1, 4102 .bpc = 8, 4103 .size = { 4104 .width = 216, 4105 .height = 135, 4106 }, 4107 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4108 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4109 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4110 }; 4111 4112 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 4113 .clock = 24750, 4114 .hdisplay = 800, 4115 .hsync_start = 800 + 54, 4116 .hsync_end = 800 + 54 + 2, 4117 .htotal = 800 + 54 + 2 + 44, 4118 .vdisplay = 480, 4119 .vsync_start = 480 + 49, 4120 .vsync_end = 480 + 49 + 2, 4121 .vtotal = 480 + 49 + 2 + 22, 4122 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4123 }; 4124 4125 static const struct panel_desc powertip_ph800480t013_idf02 = { 4126 .modes = &powertip_ph800480t013_idf02_mode, 4127 .num_modes = 1, 4128 .bpc = 8, 4129 .size = { 4130 .width = 152, 4131 .height = 91, 4132 }, 4133 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4134 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4135 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4136 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4137 .connector_type = DRM_MODE_CONNECTOR_DPI, 4138 }; 4139 4140 static const struct drm_display_mode powertip_ph800480t032_zhc19_mode = { 4141 .clock = 27200, 4142 .hdisplay = 800, 4143 .hsync_start = 800 + 52, 4144 .hsync_end = 800 + 52 + 2, 4145 .htotal = 800 + 52 + 2 + 44, 4146 .vdisplay = 480, 4147 .vsync_start = 480 + 7, 4148 .vsync_end = 480 + 7 + 2, 4149 .vtotal = 480 + 7 + 2 + 2, 4150 }; 4151 4152 static const struct panel_desc powertip_ph800480t032_zhc19 = { 4153 .modes = &powertip_ph800480t032_zhc19_mode, 4154 .num_modes = 1, 4155 .bpc = 8, 4156 .size = { 4157 .width = 152, 4158 .height = 91, 4159 }, 4160 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4161 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4162 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4163 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4164 .connector_type = DRM_MODE_CONNECTOR_DPI, 4165 }; 4166 4167 static const struct drm_display_mode primeview_pm070wl4_mode = { 4168 .clock = 32000, 4169 .hdisplay = 800, 4170 .hsync_start = 800 + 42, 4171 .hsync_end = 800 + 42 + 128, 4172 .htotal = 800 + 42 + 128 + 86, 4173 .vdisplay = 480, 4174 .vsync_start = 480 + 10, 4175 .vsync_end = 480 + 10 + 2, 4176 .vtotal = 480 + 10 + 2 + 33, 4177 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4178 }; 4179 4180 static const struct panel_desc primeview_pm070wl4 = { 4181 .modes = &primeview_pm070wl4_mode, 4182 .num_modes = 1, 4183 .bpc = 6, 4184 .size = { 4185 .width = 152, 4186 .height = 91, 4187 }, 4188 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4189 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4190 .connector_type = DRM_MODE_CONNECTOR_DPI, 4191 }; 4192 4193 static const struct drm_display_mode qd43003c0_40_mode = { 4194 .clock = 9000, 4195 .hdisplay = 480, 4196 .hsync_start = 480 + 8, 4197 .hsync_end = 480 + 8 + 4, 4198 .htotal = 480 + 8 + 4 + 39, 4199 .vdisplay = 272, 4200 .vsync_start = 272 + 4, 4201 .vsync_end = 272 + 4 + 10, 4202 .vtotal = 272 + 4 + 10 + 2, 4203 }; 4204 4205 static const struct panel_desc qd43003c0_40 = { 4206 .modes = &qd43003c0_40_mode, 4207 .num_modes = 1, 4208 .bpc = 8, 4209 .size = { 4210 .width = 95, 4211 .height = 53, 4212 }, 4213 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4214 }; 4215 4216 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 4217 { /* 60 Hz */ 4218 .clock = 10800, 4219 .hdisplay = 480, 4220 .hsync_start = 480 + 77, 4221 .hsync_end = 480 + 77 + 41, 4222 .htotal = 480 + 77 + 41 + 2, 4223 .vdisplay = 272, 4224 .vsync_start = 272 + 16, 4225 .vsync_end = 272 + 16 + 10, 4226 .vtotal = 272 + 16 + 10 + 2, 4227 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4228 }, 4229 { /* 50 Hz */ 4230 .clock = 10800, 4231 .hdisplay = 480, 4232 .hsync_start = 480 + 17, 4233 .hsync_end = 480 + 17 + 41, 4234 .htotal = 480 + 17 + 41 + 2, 4235 .vdisplay = 272, 4236 .vsync_start = 272 + 116, 4237 .vsync_end = 272 + 116 + 10, 4238 .vtotal = 272 + 116 + 10 + 2, 4239 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4240 }, 4241 }; 4242 4243 static const struct panel_desc qishenglong_gopher2b_lcd = { 4244 .modes = qishenglong_gopher2b_lcd_modes, 4245 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 4246 .bpc = 8, 4247 .size = { 4248 .width = 95, 4249 .height = 54, 4250 }, 4251 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4252 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4253 .connector_type = DRM_MODE_CONNECTOR_DPI, 4254 }; 4255 4256 static const struct display_timing raystar_rff500f_awh_dnn_timing = { 4257 .pixelclock = { 23000000, 25000000, 27000000 }, 4258 .hactive = { 800, 800, 800 }, 4259 .hback_porch = { 4, 8, 48 }, 4260 .hfront_porch = { 4, 8, 48 }, 4261 .hsync_len = { 2, 4, 8 }, 4262 .vactive = { 480, 480, 480 }, 4263 .vback_porch = { 4, 8, 12 }, 4264 .vfront_porch = { 4, 8, 12 }, 4265 .vsync_len = { 2, 4, 8 }, 4266 }; 4267 4268 static const struct panel_desc raystar_rff500f_awh_dnn = { 4269 .timings = &raystar_rff500f_awh_dnn_timing, 4270 .num_timings = 1, 4271 .bpc = 8, 4272 .size = { 4273 .width = 108, 4274 .height = 65, 4275 }, 4276 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4277 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4278 }; 4279 4280 static const struct display_timing rocktech_rk043fn48h_timing = { 4281 .pixelclock = { 6000000, 9000000, 12000000 }, 4282 .hactive = { 480, 480, 480 }, 4283 .hback_porch = { 8, 43, 43 }, 4284 .hfront_porch = { 2, 8, 10 }, 4285 .hsync_len = { 1, 1, 1 }, 4286 .vactive = { 272, 272, 272 }, 4287 .vback_porch = { 2, 12, 26 }, 4288 .vfront_porch = { 1, 4, 4 }, 4289 .vsync_len = { 1, 10, 10 }, 4290 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 4291 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4292 DISPLAY_FLAGS_SYNC_POSEDGE, 4293 }; 4294 4295 static const struct panel_desc rocktech_rk043fn48h = { 4296 .timings = &rocktech_rk043fn48h_timing, 4297 .num_timings = 1, 4298 .bpc = 8, 4299 .size = { 4300 .width = 95, 4301 .height = 54, 4302 }, 4303 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4304 .connector_type = DRM_MODE_CONNECTOR_DPI, 4305 }; 4306 4307 static const struct display_timing rocktech_rk070er9427_timing = { 4308 .pixelclock = { 26400000, 33300000, 46800000 }, 4309 .hactive = { 800, 800, 800 }, 4310 .hfront_porch = { 16, 210, 354 }, 4311 .hback_porch = { 46, 46, 46 }, 4312 .hsync_len = { 1, 1, 1 }, 4313 .vactive = { 480, 480, 480 }, 4314 .vfront_porch = { 7, 22, 147 }, 4315 .vback_porch = { 23, 23, 23 }, 4316 .vsync_len = { 1, 1, 1 }, 4317 .flags = DISPLAY_FLAGS_DE_HIGH, 4318 }; 4319 4320 static const struct panel_desc rocktech_rk070er9427 = { 4321 .timings = &rocktech_rk070er9427_timing, 4322 .num_timings = 1, 4323 .bpc = 6, 4324 .size = { 4325 .width = 154, 4326 .height = 86, 4327 }, 4328 .delay = { 4329 .prepare = 41, 4330 .enable = 50, 4331 .unprepare = 41, 4332 .disable = 50, 4333 }, 4334 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4335 }; 4336 4337 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4338 .clock = 71100, 4339 .hdisplay = 1280, 4340 .hsync_start = 1280 + 48, 4341 .hsync_end = 1280 + 48 + 32, 4342 .htotal = 1280 + 48 + 32 + 80, 4343 .vdisplay = 800, 4344 .vsync_start = 800 + 2, 4345 .vsync_end = 800 + 2 + 5, 4346 .vtotal = 800 + 2 + 5 + 16, 4347 }; 4348 4349 static const struct panel_desc rocktech_rk101ii01d_ct = { 4350 .modes = &rocktech_rk101ii01d_ct_mode, 4351 .bpc = 8, 4352 .num_modes = 1, 4353 .size = { 4354 .width = 217, 4355 .height = 136, 4356 }, 4357 .delay = { 4358 .prepare = 50, 4359 .disable = 50, 4360 }, 4361 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4362 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4363 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4364 }; 4365 4366 static const struct display_timing samsung_ltl101al01_timing = { 4367 .pixelclock = { 66663000, 66663000, 66663000 }, 4368 .hactive = { 1280, 1280, 1280 }, 4369 .hfront_porch = { 18, 18, 18 }, 4370 .hback_porch = { 36, 36, 36 }, 4371 .hsync_len = { 16, 16, 16 }, 4372 .vactive = { 800, 800, 800 }, 4373 .vfront_porch = { 4, 4, 4 }, 4374 .vback_porch = { 16, 16, 16 }, 4375 .vsync_len = { 3, 3, 3 }, 4376 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4377 }; 4378 4379 static const struct panel_desc samsung_ltl101al01 = { 4380 .timings = &samsung_ltl101al01_timing, 4381 .num_timings = 1, 4382 .bpc = 8, 4383 .size = { 4384 .width = 217, 4385 .height = 135, 4386 }, 4387 .delay = { 4388 .prepare = 40, 4389 .enable = 300, 4390 .disable = 200, 4391 .unprepare = 600, 4392 }, 4393 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4394 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4395 }; 4396 4397 static const struct display_timing samsung_ltl106al01_timing = { 4398 .pixelclock = { 71980000, 71980000, 71980000 }, 4399 .hactive = { 1366, 1366, 1366 }, 4400 .hfront_porch = { 56, 56, 56 }, 4401 .hback_porch = { 106, 106, 106 }, 4402 .hsync_len = { 14, 14, 14 }, 4403 .vactive = { 768, 768, 768 }, 4404 .vfront_porch = { 3, 3, 3 }, 4405 .vback_porch = { 6, 6, 6 }, 4406 .vsync_len = { 1, 1, 1 }, 4407 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4408 }; 4409 4410 static const struct panel_desc samsung_ltl106al01 = { 4411 .timings = &samsung_ltl106al01_timing, 4412 .num_timings = 1, 4413 .bpc = 8, 4414 .size = { 4415 .width = 235, 4416 .height = 132, 4417 }, 4418 .delay = { 4419 .prepare = 5, 4420 .enable = 10, 4421 .disable = 10, 4422 .unprepare = 5, 4423 }, 4424 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4425 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4426 }; 4427 4428 static const struct drm_display_mode samsung_ltn101nt05_mode = { 4429 .clock = 54030, 4430 .hdisplay = 1024, 4431 .hsync_start = 1024 + 24, 4432 .hsync_end = 1024 + 24 + 136, 4433 .htotal = 1024 + 24 + 136 + 160, 4434 .vdisplay = 600, 4435 .vsync_start = 600 + 3, 4436 .vsync_end = 600 + 3 + 6, 4437 .vtotal = 600 + 3 + 6 + 61, 4438 }; 4439 4440 static const struct panel_desc samsung_ltn101nt05 = { 4441 .modes = &samsung_ltn101nt05_mode, 4442 .num_modes = 1, 4443 .bpc = 6, 4444 .size = { 4445 .width = 223, 4446 .height = 125, 4447 }, 4448 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4449 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4450 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4451 }; 4452 4453 static const struct display_timing satoz_sat050at40h12r2_timing = { 4454 .pixelclock = {33300000, 33300000, 50000000}, 4455 .hactive = {800, 800, 800}, 4456 .hfront_porch = {16, 210, 354}, 4457 .hback_porch = {46, 46, 46}, 4458 .hsync_len = {1, 1, 40}, 4459 .vactive = {480, 480, 480}, 4460 .vfront_porch = {7, 22, 147}, 4461 .vback_porch = {23, 23, 23}, 4462 .vsync_len = {1, 1, 20}, 4463 }; 4464 4465 static const struct panel_desc satoz_sat050at40h12r2 = { 4466 .timings = &satoz_sat050at40h12r2_timing, 4467 .num_timings = 1, 4468 .bpc = 8, 4469 .size = { 4470 .width = 108, 4471 .height = 65, 4472 }, 4473 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4474 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4475 }; 4476 4477 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4478 .clock = 33260, 4479 .hdisplay = 800, 4480 .hsync_start = 800 + 64, 4481 .hsync_end = 800 + 64 + 128, 4482 .htotal = 800 + 64 + 128 + 64, 4483 .vdisplay = 480, 4484 .vsync_start = 480 + 8, 4485 .vsync_end = 480 + 8 + 2, 4486 .vtotal = 480 + 8 + 2 + 35, 4487 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4488 }; 4489 4490 static const struct panel_desc sharp_lq070y3dg3b = { 4491 .modes = &sharp_lq070y3dg3b_mode, 4492 .num_modes = 1, 4493 .bpc = 8, 4494 .size = { 4495 .width = 152, /* 152.4mm */ 4496 .height = 91, /* 91.4mm */ 4497 }, 4498 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4499 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4500 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4501 }; 4502 4503 static const struct drm_display_mode sharp_lq035q7db03_mode = { 4504 .clock = 5500, 4505 .hdisplay = 240, 4506 .hsync_start = 240 + 16, 4507 .hsync_end = 240 + 16 + 7, 4508 .htotal = 240 + 16 + 7 + 5, 4509 .vdisplay = 320, 4510 .vsync_start = 320 + 9, 4511 .vsync_end = 320 + 9 + 1, 4512 .vtotal = 320 + 9 + 1 + 7, 4513 }; 4514 4515 static const struct panel_desc sharp_lq035q7db03 = { 4516 .modes = &sharp_lq035q7db03_mode, 4517 .num_modes = 1, 4518 .bpc = 6, 4519 .size = { 4520 .width = 54, 4521 .height = 72, 4522 }, 4523 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4524 }; 4525 4526 static const struct display_timing sharp_lq101k1ly04_timing = { 4527 .pixelclock = { 60000000, 65000000, 80000000 }, 4528 .hactive = { 1280, 1280, 1280 }, 4529 .hfront_porch = { 20, 20, 20 }, 4530 .hback_porch = { 20, 20, 20 }, 4531 .hsync_len = { 10, 10, 10 }, 4532 .vactive = { 800, 800, 800 }, 4533 .vfront_porch = { 4, 4, 4 }, 4534 .vback_porch = { 4, 4, 4 }, 4535 .vsync_len = { 4, 4, 4 }, 4536 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4537 }; 4538 4539 static const struct panel_desc sharp_lq101k1ly04 = { 4540 .timings = &sharp_lq101k1ly04_timing, 4541 .num_timings = 1, 4542 .bpc = 8, 4543 .size = { 4544 .width = 217, 4545 .height = 136, 4546 }, 4547 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4548 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4549 }; 4550 4551 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4552 { /* 50 Hz */ 4553 .clock = 3000, 4554 .hdisplay = 240, 4555 .hsync_start = 240 + 58, 4556 .hsync_end = 240 + 58 + 1, 4557 .htotal = 240 + 58 + 1 + 1, 4558 .vdisplay = 160, 4559 .vsync_start = 160 + 24, 4560 .vsync_end = 160 + 24 + 10, 4561 .vtotal = 160 + 24 + 10 + 6, 4562 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4563 }, 4564 { /* 60 Hz */ 4565 .clock = 3000, 4566 .hdisplay = 240, 4567 .hsync_start = 240 + 8, 4568 .hsync_end = 240 + 8 + 1, 4569 .htotal = 240 + 8 + 1 + 1, 4570 .vdisplay = 160, 4571 .vsync_start = 160 + 24, 4572 .vsync_end = 160 + 24 + 10, 4573 .vtotal = 160 + 24 + 10 + 6, 4574 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4575 }, 4576 }; 4577 4578 static const struct panel_desc sharp_ls020b1dd01d = { 4579 .modes = sharp_ls020b1dd01d_modes, 4580 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4581 .bpc = 6, 4582 .size = { 4583 .width = 42, 4584 .height = 28, 4585 }, 4586 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4587 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4588 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4589 | DRM_BUS_FLAG_SHARP_SIGNALS, 4590 }; 4591 4592 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4593 .clock = 33300, 4594 .hdisplay = 800, 4595 .hsync_start = 800 + 1, 4596 .hsync_end = 800 + 1 + 64, 4597 .htotal = 800 + 1 + 64 + 64, 4598 .vdisplay = 480, 4599 .vsync_start = 480 + 1, 4600 .vsync_end = 480 + 1 + 23, 4601 .vtotal = 480 + 1 + 23 + 22, 4602 }; 4603 4604 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4605 .modes = &shelly_sca07010_bfn_lnn_mode, 4606 .num_modes = 1, 4607 .size = { 4608 .width = 152, 4609 .height = 91, 4610 }, 4611 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4612 }; 4613 4614 static const struct drm_display_mode starry_kr070pe2t_mode = { 4615 .clock = 33000, 4616 .hdisplay = 800, 4617 .hsync_start = 800 + 209, 4618 .hsync_end = 800 + 209 + 1, 4619 .htotal = 800 + 209 + 1 + 45, 4620 .vdisplay = 480, 4621 .vsync_start = 480 + 22, 4622 .vsync_end = 480 + 22 + 1, 4623 .vtotal = 480 + 22 + 1 + 22, 4624 }; 4625 4626 static const struct panel_desc starry_kr070pe2t = { 4627 .modes = &starry_kr070pe2t_mode, 4628 .num_modes = 1, 4629 .bpc = 8, 4630 .size = { 4631 .width = 152, 4632 .height = 86, 4633 }, 4634 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4635 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4636 .connector_type = DRM_MODE_CONNECTOR_DPI, 4637 }; 4638 4639 static const struct display_timing startek_kd070hdfld092_timing = { 4640 .pixelclock = { 40800000, 51200000, 67200000 }, 4641 .hactive = { 1024, 1024, 1024 }, 4642 .hfront_porch = { 40, 160, 216 }, 4643 .hback_porch = { 30, 140, 140 }, 4644 .hsync_len = { 20, 20, 20 }, 4645 .vactive = { 600, 600, 600 }, 4646 .vfront_porch = { 2, 12, 177 }, 4647 .vback_porch = { 5, 20, 20 }, 4648 .vsync_len = { 3, 3, 3 }, 4649 .flags = DISPLAY_FLAGS_DE_HIGH, 4650 }; 4651 4652 static const struct panel_desc startek_kd070hdfld092 = { 4653 .timings = &startek_kd070hdfld092_timing, 4654 .num_timings = 1, 4655 .bpc = 8, 4656 .size = { 4657 .width = 154, 4658 .height = 86, 4659 }, 4660 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4661 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4662 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4663 }; 4664 4665 static const struct display_timing startek_kd070wvfpa_mode = { 4666 .pixelclock = { 25200000, 27200000, 30500000 }, 4667 .hactive = { 800, 800, 800 }, 4668 .hfront_porch = { 19, 44, 115 }, 4669 .hback_porch = { 5, 16, 101 }, 4670 .hsync_len = { 1, 2, 100 }, 4671 .vactive = { 480, 480, 480 }, 4672 .vfront_porch = { 5, 43, 67 }, 4673 .vback_porch = { 5, 5, 67 }, 4674 .vsync_len = { 1, 2, 66 }, 4675 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4676 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4677 DISPLAY_FLAGS_SYNC_POSEDGE, 4678 }; 4679 4680 static const struct panel_desc startek_kd070wvfpa = { 4681 .timings = &startek_kd070wvfpa_mode, 4682 .num_timings = 1, 4683 .bpc = 8, 4684 .size = { 4685 .width = 152, 4686 .height = 91, 4687 }, 4688 .delay = { 4689 .prepare = 20, 4690 .enable = 200, 4691 .disable = 200, 4692 }, 4693 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4694 .connector_type = DRM_MODE_CONNECTOR_DPI, 4695 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4696 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4697 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4698 }; 4699 4700 static const struct display_timing tsd_tst043015cmhx_timing = { 4701 .pixelclock = { 5000000, 9000000, 12000000 }, 4702 .hactive = { 480, 480, 480 }, 4703 .hfront_porch = { 4, 5, 65 }, 4704 .hback_porch = { 36, 40, 255 }, 4705 .hsync_len = { 1, 1, 1 }, 4706 .vactive = { 272, 272, 272 }, 4707 .vfront_porch = { 2, 8, 97 }, 4708 .vback_porch = { 3, 8, 31 }, 4709 .vsync_len = { 1, 1, 1 }, 4710 4711 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4712 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4713 }; 4714 4715 static const struct panel_desc tsd_tst043015cmhx = { 4716 .timings = &tsd_tst043015cmhx_timing, 4717 .num_timings = 1, 4718 .bpc = 8, 4719 .size = { 4720 .width = 105, 4721 .height = 67, 4722 }, 4723 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4724 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4725 }; 4726 4727 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4728 .clock = 30000, 4729 .hdisplay = 800, 4730 .hsync_start = 800 + 39, 4731 .hsync_end = 800 + 39 + 47, 4732 .htotal = 800 + 39 + 47 + 39, 4733 .vdisplay = 480, 4734 .vsync_start = 480 + 13, 4735 .vsync_end = 480 + 13 + 2, 4736 .vtotal = 480 + 13 + 2 + 29, 4737 }; 4738 4739 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4740 .modes = &tfc_s9700rtwv43tr_01b_mode, 4741 .num_modes = 1, 4742 .bpc = 8, 4743 .size = { 4744 .width = 155, 4745 .height = 90, 4746 }, 4747 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4748 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4749 }; 4750 4751 static const struct display_timing tianma_tm070jdhg30_timing = { 4752 .pixelclock = { 62600000, 68200000, 78100000 }, 4753 .hactive = { 1280, 1280, 1280 }, 4754 .hfront_porch = { 15, 64, 159 }, 4755 .hback_porch = { 5, 5, 5 }, 4756 .hsync_len = { 1, 1, 256 }, 4757 .vactive = { 800, 800, 800 }, 4758 .vfront_porch = { 3, 40, 99 }, 4759 .vback_porch = { 2, 2, 2 }, 4760 .vsync_len = { 1, 1, 128 }, 4761 .flags = DISPLAY_FLAGS_DE_HIGH, 4762 }; 4763 4764 static const struct panel_desc tianma_tm070jdhg30 = { 4765 .timings = &tianma_tm070jdhg30_timing, 4766 .num_timings = 1, 4767 .bpc = 8, 4768 .size = { 4769 .width = 151, 4770 .height = 95, 4771 }, 4772 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4773 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4774 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4775 }; 4776 4777 static const struct panel_desc tianma_tm070jvhg33 = { 4778 .timings = &tianma_tm070jdhg30_timing, 4779 .num_timings = 1, 4780 .bpc = 8, 4781 .size = { 4782 .width = 150, 4783 .height = 94, 4784 }, 4785 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4786 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4787 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4788 }; 4789 4790 /* 4791 * The TM070JDHG34-00 datasheet computes total blanking as back porch + 4792 * front porch, not including sync pulse width. This is for both H and 4793 * V. To make the total blanking and period correct, subtract the pulse 4794 * width from the front porch. 4795 * 4796 * This works well for the Min and Typ values, but for Max values the sync 4797 * pulse width is higher than back porch + front porch, so work around that 4798 * by reducing the Max sync length value to 1 and then treating the Max 4799 * porches as in the Min and Typ cases. 4800 * 4801 * Exact datasheet values are added as a comment where they differ from the 4802 * ones implemented for the above reason. 4803 * 4804 * The P0700WXF1MBAA datasheet is even less detailed, only listing period 4805 * and total blanking time, however the resulting values are the same as 4806 * the TM070JDHG34-00. 4807 */ 4808 static const struct display_timing tianma_tm070jdhg34_00_timing = { 4809 .pixelclock = { 68400000, 71900000, 78100000 }, 4810 .hactive = { 1280, 1280, 1280 }, 4811 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4812 .hback_porch = { 5, 5, 5 }, 4813 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4814 .vactive = { 800, 800, 800 }, 4815 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4816 .vback_porch = { 2, 2, 2 }, 4817 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4818 .flags = DISPLAY_FLAGS_DE_HIGH, 4819 }; 4820 4821 static const struct panel_desc tianma_tm070jdhg34_00 = { 4822 .timings = &tianma_tm070jdhg34_00_timing, 4823 .num_timings = 1, 4824 .bpc = 8, 4825 .size = { 4826 .width = 150, /* 149.76 */ 4827 .height = 94, /* 93.60 */ 4828 }, 4829 .delay = { 4830 .prepare = 15, /* Tp1 */ 4831 .enable = 150, /* Tp2 */ 4832 .disable = 150, /* Tp4 */ 4833 .unprepare = 120, /* Tp3 */ 4834 }, 4835 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4836 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4837 }; 4838 4839 static const struct panel_desc tianma_p0700wxf1mbaa = { 4840 .timings = &tianma_tm070jdhg34_00_timing, 4841 .num_timings = 1, 4842 .bpc = 8, 4843 .size = { 4844 .width = 150, /* 149.76 */ 4845 .height = 94, /* 93.60 */ 4846 }, 4847 .delay = { 4848 .prepare = 18, /* Tr + Tp1 */ 4849 .enable = 152, /* Tp2 + Tp5 */ 4850 .disable = 152, /* Tp6 + Tp4 */ 4851 .unprepare = 120, /* Tp3 */ 4852 }, 4853 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4854 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4855 }; 4856 4857 static const struct display_timing tianma_tm070rvhg71_timing = { 4858 .pixelclock = { 27700000, 29200000, 39600000 }, 4859 .hactive = { 800, 800, 800 }, 4860 .hfront_porch = { 12, 40, 212 }, 4861 .hback_porch = { 88, 88, 88 }, 4862 .hsync_len = { 1, 1, 40 }, 4863 .vactive = { 480, 480, 480 }, 4864 .vfront_porch = { 1, 13, 88 }, 4865 .vback_porch = { 32, 32, 32 }, 4866 .vsync_len = { 1, 1, 3 }, 4867 .flags = DISPLAY_FLAGS_DE_HIGH, 4868 }; 4869 4870 static const struct panel_desc tianma_tm070rvhg71 = { 4871 .timings = &tianma_tm070rvhg71_timing, 4872 .num_timings = 1, 4873 .bpc = 8, 4874 .size = { 4875 .width = 154, 4876 .height = 86, 4877 }, 4878 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4879 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4880 }; 4881 4882 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4883 { 4884 .clock = 10000, 4885 .hdisplay = 320, 4886 .hsync_start = 320 + 50, 4887 .hsync_end = 320 + 50 + 6, 4888 .htotal = 320 + 50 + 6 + 38, 4889 .vdisplay = 240, 4890 .vsync_start = 240 + 3, 4891 .vsync_end = 240 + 3 + 1, 4892 .vtotal = 240 + 3 + 1 + 17, 4893 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4894 }, 4895 }; 4896 4897 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4898 .modes = ti_nspire_cx_lcd_mode, 4899 .num_modes = 1, 4900 .bpc = 8, 4901 .size = { 4902 .width = 65, 4903 .height = 49, 4904 }, 4905 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4906 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4907 }; 4908 4909 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4910 { 4911 .clock = 10000, 4912 .hdisplay = 320, 4913 .hsync_start = 320 + 6, 4914 .hsync_end = 320 + 6 + 6, 4915 .htotal = 320 + 6 + 6 + 6, 4916 .vdisplay = 240, 4917 .vsync_start = 240 + 0, 4918 .vsync_end = 240 + 0 + 1, 4919 .vtotal = 240 + 0 + 1 + 0, 4920 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4921 }, 4922 }; 4923 4924 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4925 .modes = ti_nspire_classic_lcd_mode, 4926 .num_modes = 1, 4927 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4928 .bpc = 8, 4929 .size = { 4930 .width = 71, 4931 .height = 53, 4932 }, 4933 /* This is the grayscale bus format */ 4934 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4935 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4936 }; 4937 4938 static const struct display_timing topland_tian_g07017_01_timing = { 4939 .pixelclock = { 44900000, 51200000, 63000000 }, 4940 .hactive = { 1024, 1024, 1024 }, 4941 .hfront_porch = { 16, 160, 216 }, 4942 .hback_porch = { 160, 160, 160 }, 4943 .hsync_len = { 1, 1, 140 }, 4944 .vactive = { 600, 600, 600 }, 4945 .vfront_porch = { 1, 12, 127 }, 4946 .vback_porch = { 23, 23, 23 }, 4947 .vsync_len = { 1, 1, 20 }, 4948 }; 4949 4950 static const struct panel_desc topland_tian_g07017_01 = { 4951 .timings = &topland_tian_g07017_01_timing, 4952 .num_timings = 1, 4953 .bpc = 8, 4954 .size = { 4955 .width = 154, 4956 .height = 86, 4957 }, 4958 .delay = { 4959 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 4960 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 4961 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 4962 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 4963 }, 4964 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4965 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4966 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4967 }; 4968 4969 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4970 .clock = 79500, 4971 .hdisplay = 1280, 4972 .hsync_start = 1280 + 192, 4973 .hsync_end = 1280 + 192 + 128, 4974 .htotal = 1280 + 192 + 128 + 64, 4975 .vdisplay = 768, 4976 .vsync_start = 768 + 20, 4977 .vsync_end = 768 + 20 + 7, 4978 .vtotal = 768 + 20 + 7 + 3, 4979 }; 4980 4981 static const struct panel_desc toshiba_lt089ac29000 = { 4982 .modes = &toshiba_lt089ac29000_mode, 4983 .num_modes = 1, 4984 .size = { 4985 .width = 194, 4986 .height = 116, 4987 }, 4988 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4989 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4990 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4991 }; 4992 4993 static const struct drm_display_mode tpk_f07a_0102_mode = { 4994 .clock = 33260, 4995 .hdisplay = 800, 4996 .hsync_start = 800 + 40, 4997 .hsync_end = 800 + 40 + 128, 4998 .htotal = 800 + 40 + 128 + 88, 4999 .vdisplay = 480, 5000 .vsync_start = 480 + 10, 5001 .vsync_end = 480 + 10 + 2, 5002 .vtotal = 480 + 10 + 2 + 33, 5003 }; 5004 5005 static const struct panel_desc tpk_f07a_0102 = { 5006 .modes = &tpk_f07a_0102_mode, 5007 .num_modes = 1, 5008 .size = { 5009 .width = 152, 5010 .height = 91, 5011 }, 5012 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 5013 }; 5014 5015 static const struct drm_display_mode tpk_f10a_0102_mode = { 5016 .clock = 45000, 5017 .hdisplay = 1024, 5018 .hsync_start = 1024 + 176, 5019 .hsync_end = 1024 + 176 + 5, 5020 .htotal = 1024 + 176 + 5 + 88, 5021 .vdisplay = 600, 5022 .vsync_start = 600 + 20, 5023 .vsync_end = 600 + 20 + 5, 5024 .vtotal = 600 + 20 + 5 + 25, 5025 }; 5026 5027 static const struct panel_desc tpk_f10a_0102 = { 5028 .modes = &tpk_f10a_0102_mode, 5029 .num_modes = 1, 5030 .size = { 5031 .width = 223, 5032 .height = 125, 5033 }, 5034 }; 5035 5036 static const struct display_timing urt_umsh_8596md_timing = { 5037 .pixelclock = { 33260000, 33260000, 33260000 }, 5038 .hactive = { 800, 800, 800 }, 5039 .hfront_porch = { 41, 41, 41 }, 5040 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 5041 .hsync_len = { 71, 128, 128 }, 5042 .vactive = { 480, 480, 480 }, 5043 .vfront_porch = { 10, 10, 10 }, 5044 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 5045 .vsync_len = { 2, 2, 2 }, 5046 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 5047 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 5048 }; 5049 5050 static const struct panel_desc urt_umsh_8596md_lvds = { 5051 .timings = &urt_umsh_8596md_timing, 5052 .num_timings = 1, 5053 .bpc = 6, 5054 .size = { 5055 .width = 152, 5056 .height = 91, 5057 }, 5058 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 5059 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5060 }; 5061 5062 static const struct panel_desc urt_umsh_8596md_parallel = { 5063 .timings = &urt_umsh_8596md_timing, 5064 .num_timings = 1, 5065 .bpc = 6, 5066 .size = { 5067 .width = 152, 5068 .height = 91, 5069 }, 5070 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 5071 }; 5072 5073 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 5074 .clock = 60000, 5075 .hdisplay = 1024, 5076 .hsync_start = 1024 + 160, 5077 .hsync_end = 1024 + 160 + 100, 5078 .htotal = 1024 + 160 + 100 + 60, 5079 .vdisplay = 600, 5080 .vsync_start = 600 + 12, 5081 .vsync_end = 600 + 12 + 10, 5082 .vtotal = 600 + 12 + 10 + 13, 5083 }; 5084 5085 static const struct panel_desc vivax_tpc9150_panel = { 5086 .modes = &vivax_tpc9150_panel_mode, 5087 .num_modes = 1, 5088 .bpc = 6, 5089 .size = { 5090 .width = 200, 5091 .height = 115, 5092 }, 5093 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 5094 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5095 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5096 }; 5097 5098 static const struct drm_display_mode vl050_8048nt_c01_mode = { 5099 .clock = 33333, 5100 .hdisplay = 800, 5101 .hsync_start = 800 + 210, 5102 .hsync_end = 800 + 210 + 20, 5103 .htotal = 800 + 210 + 20 + 46, 5104 .vdisplay = 480, 5105 .vsync_start = 480 + 22, 5106 .vsync_end = 480 + 22 + 10, 5107 .vtotal = 480 + 22 + 10 + 23, 5108 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5109 }; 5110 5111 static const struct panel_desc vl050_8048nt_c01 = { 5112 .modes = &vl050_8048nt_c01_mode, 5113 .num_modes = 1, 5114 .bpc = 8, 5115 .size = { 5116 .width = 120, 5117 .height = 76, 5118 }, 5119 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5120 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 5121 }; 5122 5123 static const struct drm_display_mode waveshare_28_lcd_mode = { 5124 .clock = 50000, 5125 .hdisplay = 480, 5126 .hsync_start = 480 + 150, 5127 .hsync_end = 480 + 150 + 50, 5128 .htotal = 480 + 150 + 50 + 150, 5129 .vdisplay = 640, 5130 .vsync_start = 640 + 150, 5131 .vsync_end = 640 + 150 + 50, 5132 .vtotal = 640 + 150 + 50 + 150, 5133 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5134 }; 5135 5136 static const struct panel_desc waveshare_28_lcd_panel = { 5137 .modes = &waveshare_28_lcd_mode, 5138 .num_modes = 1, 5139 .bpc = 8, 5140 .size = { 5141 .width = 44, 5142 .height = 58, 5143 }, 5144 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5145 .connector_type = DRM_MODE_CONNECTOR_DPI, 5146 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5147 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5148 }; 5149 5150 static const struct drm_display_mode waveshare_34_lcd_c_mode = { 5151 .clock = 50000, 5152 .hdisplay = 800, 5153 .hsync_start = 800 + 32, 5154 .hsync_end = 800 + 32 + 6, 5155 .htotal = 800 + 32 + 6 + 120, 5156 .vdisplay = 800, 5157 .vsync_start = 800 + 8, 5158 .vsync_end = 800 + 8 + 4, 5159 .vtotal = 800 + 8 + 4 + 16, 5160 }; 5161 5162 static const struct panel_desc waveshare_34_lcd_c_panel = { 5163 .modes = &waveshare_34_lcd_c_mode, 5164 .num_modes = 1, 5165 .bpc = 8, 5166 .size = { 5167 .width = 88, 5168 .height = 88, 5169 }, 5170 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5171 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5172 }; 5173 5174 static const struct drm_display_mode waveshare_40_lcd_mode = { 5175 .clock = 50000, 5176 .hdisplay = 480, 5177 .hsync_start = 480 + 150, 5178 .hsync_end = 480 + 150 + 100, 5179 .htotal = 480 + 150 + 100 + 150, 5180 .vdisplay = 800, 5181 .vsync_start = 800 + 20, 5182 .vsync_end = 800 + 20 + 100, 5183 .vtotal = 800 + 20 + 100 + 20, 5184 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5185 }; 5186 5187 static const struct panel_desc waveshare_40_lcd_panel = { 5188 .modes = &waveshare_40_lcd_mode, 5189 .num_modes = 1, 5190 .bpc = 8, 5191 .size = { 5192 .width = 52, 5193 .height = 87, 5194 }, 5195 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5196 .connector_type = DRM_MODE_CONNECTOR_DPI, 5197 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5198 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5199 }; 5200 5201 static const struct drm_display_mode waveshare_40_lcd_c_mode = { 5202 .clock = 50000, 5203 .hdisplay = 720, 5204 .hsync_start = 720 + 32, 5205 .hsync_end = 720 + 32 + 200, 5206 .htotal = 720 + 32 + 200 + 120, 5207 .vdisplay = 720, 5208 .vsync_start = 720 + 8, 5209 .vsync_end = 720 + 8 + 4, 5210 .vtotal = 720 + 8 + 4 + 16, 5211 }; 5212 5213 static const struct panel_desc waveshare_40_lcd_c_panel = { 5214 .modes = &waveshare_40_lcd_c_mode, 5215 .num_modes = 1, 5216 .bpc = 8, 5217 .size = { 5218 .width = 102, 5219 .height = 102, 5220 }, 5221 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5222 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5223 }; 5224 5225 static const struct drm_display_mode waveshare_50_lcd_c_mode = { 5226 .clock = 50000, 5227 .hdisplay = 1024, 5228 .hsync_start = 1024 + 100, 5229 .hsync_end = 1024 + 100 + 100, 5230 .htotal = 1024 + 100 + 100 + 100, 5231 .vdisplay = 600, 5232 .vsync_start = 600 + 10, 5233 .vsync_end = 600 + 10 + 10, 5234 .vtotal = 600 + 10 + 10 + 10, 5235 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5236 }; 5237 5238 static const struct panel_desc waveshare_50_lcd_c_panel = { 5239 .modes = &waveshare_50_lcd_c_mode, 5240 .num_modes = 1, 5241 .bpc = 8, 5242 .size = { 5243 .width = 109, 5244 .height = 66, 5245 }, 5246 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5247 .connector_type = DRM_MODE_CONNECTOR_DPI, 5248 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5249 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5250 }; 5251 5252 static const struct drm_display_mode waveshare_50_lcd_d_mode = { 5253 .clock = 83333, 5254 .hdisplay = 720, 5255 .hsync_start = 720 + 100, 5256 .hsync_end = 720 + 100 + 80, 5257 .htotal = 720 + 100 + 80 + 100, 5258 .vdisplay = 1280, 5259 .vsync_start = 1280 + 20, 5260 .vsync_end = 1280 + 20 + 20, 5261 .vtotal = 1280 + 20 + 20 + 20, 5262 }; 5263 5264 static const struct panel_desc waveshare_50_lcd_d_panel = { 5265 .modes = &waveshare_50_lcd_d_mode, 5266 .num_modes = 1, 5267 .bpc = 8, 5268 .size = { 5269 .width = 62, 5270 .height = 110, 5271 }, 5272 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5273 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5274 }; 5275 5276 static const struct drm_display_mode waveshare_625_lcd_mode = { 5277 .clock = 83333, 5278 .hdisplay = 720, 5279 .hsync_start = 720 + 50, 5280 .hsync_end = 720 + 50 + 50, 5281 .htotal = 720 + 50 + 50 + 50, 5282 .vdisplay = 1560, 5283 .vsync_start = 1560 + 20, 5284 .vsync_end = 1560 + 20 + 20, 5285 .vtotal = 1560 + 20 + 20 + 20, 5286 }; 5287 5288 static const struct panel_desc waveshare_625_lcd_panel = { 5289 .modes = &waveshare_625_lcd_mode, 5290 .num_modes = 1, 5291 .bpc = 8, 5292 .size = { 5293 .width = 66, 5294 .height = 144, 5295 }, 5296 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5297 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5298 }; 5299 5300 static const struct panel_desc waveshare_70_lcd_c_panel = { 5301 .modes = &waveshare_50_lcd_c_mode, 5302 .num_modes = 1, 5303 .bpc = 8, 5304 .size = { 5305 .width = 155, 5306 .height = 87, 5307 }, 5308 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5309 .connector_type = DRM_MODE_CONNECTOR_DPI, 5310 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5311 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5312 }; 5313 5314 static const struct drm_display_mode waveshare_80_lcd_c_mode; 5315 static const struct panel_desc waveshare_70_lcd_e_panel = { 5316 .modes = &waveshare_80_lcd_c_mode, 5317 .num_modes = 1, 5318 .bpc = 8, 5319 .size = { 5320 .width = 152, 5321 .height = 95, 5322 }, 5323 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5324 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5325 }; 5326 5327 static const struct drm_display_mode waveshare_70_lcd_h_mode = { 5328 .clock = 83333, 5329 .hdisplay = 1280, 5330 .hsync_start = 1280 + 64, 5331 .hsync_end = 1280 + 64 + 64, 5332 .htotal = 1280 + 64 + 64 + 64, 5333 .vdisplay = 720, 5334 .vsync_start = 720 + 64, 5335 .vsync_end = 720 + 64 + 64, 5336 .vtotal = 720 + 64 + 64 + 64, 5337 }; 5338 5339 static const struct panel_desc waveshare_70_lcd_h_panel = { 5340 .modes = &waveshare_70_lcd_h_mode, 5341 .num_modes = 1, 5342 .bpc = 8, 5343 .size = { 5344 .width = 155, 5345 .height = 88, 5346 }, 5347 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5348 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5349 }; 5350 5351 static const struct drm_display_mode waveshare_79_lcd_mode = { 5352 .clock = 50000, 5353 .hdisplay = 400, 5354 .hsync_start = 400 + 40, 5355 .hsync_end = 400 + 40 + 30, 5356 .htotal = 400 + 40 + 30 + 40, 5357 .vdisplay = 1280, 5358 .vsync_start = 1280 + 20, 5359 .vsync_end = 1280 + 20 + 10, 5360 .vtotal = 1280 + 20 + 10 + 20, 5361 }; 5362 5363 static const struct panel_desc waveshare_79_lcd_panel = { 5364 .modes = &waveshare_79_lcd_mode, 5365 .num_modes = 1, 5366 .bpc = 8, 5367 .size = { 5368 .width = 60, 5369 .height = 191, 5370 }, 5371 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5372 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5373 }; 5374 5375 static const struct drm_display_mode waveshare_80_lcd_c_mode = { 5376 .clock = 83333, 5377 .hdisplay = 1280, 5378 .hsync_start = 1280 + 156, 5379 .hsync_end = 1280 + 156 + 20, 5380 .htotal = 1280 + 156 + 20 + 40, 5381 .vdisplay = 800, 5382 .vsync_start = 800 + 40, 5383 .vsync_end = 800 + 40 + 48, 5384 .vtotal = 800 + 40 + 48 + 40, 5385 }; 5386 5387 static const struct panel_desc waveshare_80_lcd_c_panel = { 5388 .modes = &waveshare_80_lcd_c_mode, 5389 .num_modes = 1, 5390 .bpc = 8, 5391 .size = { 5392 .width = 173, 5393 .height = 108, 5394 }, 5395 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5396 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5397 }; 5398 5399 static const struct drm_display_mode waveshare_88_lcd_mode = { 5400 .clock = 83333, 5401 .hdisplay = 480, 5402 .hsync_start = 480 + 50, 5403 .hsync_end = 480 + 50 + 50, 5404 .htotal = 480 + 50 + 50 + 50, 5405 .vdisplay = 1920, 5406 .vsync_start = 1920 + 20, 5407 .vsync_end = 1920 + 20 + 20, 5408 .vtotal = 1920 + 20 + 20 + 20, 5409 }; 5410 5411 static const struct panel_desc waveshare_88_lcd_panel = { 5412 .modes = &waveshare_88_lcd_mode, 5413 .num_modes = 1, 5414 .bpc = 8, 5415 .size = { 5416 .width = 56, 5417 .height = 220, 5418 }, 5419 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5420 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5421 }; 5422 5423 static const struct panel_desc waveshare_101_lcd_c_panel = { 5424 .modes = &waveshare_80_lcd_c_mode, 5425 .num_modes = 1, 5426 .bpc = 8, 5427 .size = { 5428 .width = 217, 5429 .height = 136, 5430 }, 5431 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5432 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5433 }; 5434 5435 static const struct drm_display_mode waveshare_119_lcd_mode = { 5436 .clock = 50000, 5437 .hdisplay = 320, 5438 .hsync_start = 320 + 60, 5439 .hsync_end = 320 + 60 + 60, 5440 .htotal = 320 + 60 + 60 + 60, 5441 .vdisplay = 1480, 5442 .vsync_start = 1480 + 60, 5443 .vsync_end = 1480 + 60 + 60, 5444 .vtotal = 1480 + 60 + 60 + 60, 5445 }; 5446 5447 static const struct panel_desc waveshare_119_lcd_panel = { 5448 .modes = &waveshare_119_lcd_mode, 5449 .num_modes = 1, 5450 .bpc = 8, 5451 .size = { 5452 .width = 58, 5453 .height = 268, 5454 }, 5455 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5456 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5457 }; 5458 5459 static const struct drm_display_mode waveshare_133inch_mode = { 5460 .clock = 148500, 5461 .hdisplay = 1920, 5462 .hsync_start = 1920 + 88, 5463 .hsync_end = 1920 + 88 + 44, 5464 .htotal = 1920 + 88 + 44 + 148, 5465 .vdisplay = 1080, 5466 .vsync_start = 1080 + 4, 5467 .vsync_end = 1080 + 4 + 5, 5468 .vtotal = 1080 + 4 + 5 + 36, 5469 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5470 }; 5471 5472 static const struct panel_desc waveshare_133inch = { 5473 .modes = &waveshare_133inch_mode, 5474 .num_modes = 1, 5475 .bpc = 8, 5476 .size = { 5477 .width = 293, 5478 .height = 163, 5479 }, 5480 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5481 .connector_type = DRM_MODE_CONNECTOR_DPI, 5482 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5483 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5484 }; 5485 5486 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 5487 .clock = 6410, 5488 .hdisplay = 320, 5489 .hsync_start = 320 + 20, 5490 .hsync_end = 320 + 20 + 30, 5491 .htotal = 320 + 20 + 30 + 38, 5492 .vdisplay = 240, 5493 .vsync_start = 240 + 4, 5494 .vsync_end = 240 + 4 + 3, 5495 .vtotal = 240 + 4 + 3 + 15, 5496 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5497 }; 5498 5499 static const struct panel_desc winstar_wf35ltiacd = { 5500 .modes = &winstar_wf35ltiacd_mode, 5501 .num_modes = 1, 5502 .bpc = 8, 5503 .size = { 5504 .width = 70, 5505 .height = 53, 5506 }, 5507 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5508 }; 5509 5510 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 5511 .clock = 51200, 5512 .hdisplay = 1024, 5513 .hsync_start = 1024 + 100, 5514 .hsync_end = 1024 + 100 + 100, 5515 .htotal = 1024 + 100 + 100 + 120, 5516 .vdisplay = 600, 5517 .vsync_start = 600 + 10, 5518 .vsync_end = 600 + 10 + 10, 5519 .vtotal = 600 + 10 + 10 + 15, 5520 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 5521 }; 5522 5523 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 5524 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 5525 .num_modes = 1, 5526 .bpc = 8, 5527 .size = { 5528 .width = 154, 5529 .height = 90, 5530 }, 5531 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5532 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5533 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5534 }; 5535 5536 static const struct drm_display_mode mchp_ac69t88a_mode = { 5537 .clock = 25000, 5538 .hdisplay = 800, 5539 .hsync_start = 800 + 88, 5540 .hsync_end = 800 + 88 + 5, 5541 .htotal = 800 + 88 + 5 + 40, 5542 .vdisplay = 480, 5543 .vsync_start = 480 + 23, 5544 .vsync_end = 480 + 23 + 5, 5545 .vtotal = 480 + 23 + 5 + 1, 5546 }; 5547 5548 static const struct panel_desc mchp_ac69t88a = { 5549 .modes = &mchp_ac69t88a_mode, 5550 .num_modes = 1, 5551 .bpc = 8, 5552 .size = { 5553 .width = 108, 5554 .height = 65, 5555 }, 5556 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5557 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 5558 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5559 }; 5560 5561 static const struct drm_display_mode arm_rtsm_mode[] = { 5562 { 5563 .clock = 65000, 5564 .hdisplay = 1024, 5565 .hsync_start = 1024 + 24, 5566 .hsync_end = 1024 + 24 + 136, 5567 .htotal = 1024 + 24 + 136 + 160, 5568 .vdisplay = 768, 5569 .vsync_start = 768 + 3, 5570 .vsync_end = 768 + 3 + 6, 5571 .vtotal = 768 + 3 + 6 + 29, 5572 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5573 }, 5574 }; 5575 5576 static const struct panel_desc arm_rtsm = { 5577 .modes = arm_rtsm_mode, 5578 .num_modes = 1, 5579 .bpc = 8, 5580 .size = { 5581 .width = 400, 5582 .height = 300, 5583 }, 5584 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5585 }; 5586 5587 static const struct of_device_id platform_of_match[] = { 5588 { 5589 .compatible = "ampire,am-1280800n3tzqw-t00h", 5590 .data = &ire_am_1280800n3tzqw_t00h, 5591 }, { 5592 .compatible = "ampire,am-480272h3tmqw-t01h", 5593 .data = &ire_am_480272h3tmqw_t01h, 5594 }, { 5595 .compatible = "ampire,am-800480l1tmqw-t00h", 5596 .data = &ire_am_800480l1tmqw_t00h, 5597 }, { 5598 .compatible = "ampire,am800480r3tmqwa1h", 5599 .data = &ire_am800480r3tmqwa1h, 5600 }, { 5601 .compatible = "ampire,am800600p5tmqw-tb8h", 5602 .data = &ire_am800600p5tmqwtb8h, 5603 }, { 5604 .compatible = "arm,rtsm-display", 5605 .data = &arm_rtsm, 5606 }, { 5607 .compatible = "armadeus,st0700-adapt", 5608 .data = &armadeus_st0700_adapt, 5609 }, { 5610 .compatible = "auo,b101aw03", 5611 .data = &auo_b101aw03, 5612 }, { 5613 .compatible = "auo,b101xtn01", 5614 .data = &auo_b101xtn01, 5615 }, { 5616 .compatible = "auo,b116xw03", 5617 .data = &auo_b116xw03, 5618 }, { 5619 .compatible = "auo,g070vvn01", 5620 .data = &auo_g070vvn01, 5621 }, { 5622 .compatible = "auo,g101evn010", 5623 .data = &auo_g101evn010, 5624 }, { 5625 .compatible = "auo,g104sn02", 5626 .data = &auo_g104sn02, 5627 }, { 5628 .compatible = "auo,g104stn01", 5629 .data = &auo_g104stn01, 5630 }, { 5631 .compatible = "auo,g121ean01", 5632 .data = &auo_g121ean01, 5633 }, { 5634 .compatible = "auo,g133han01", 5635 .data = &auo_g133han01, 5636 }, { 5637 .compatible = "auo,g156han04", 5638 .data = &auo_g156han04, 5639 }, { 5640 .compatible = "auo,g156xtn01", 5641 .data = &auo_g156xtn01, 5642 }, { 5643 .compatible = "auo,g185han01", 5644 .data = &auo_g185han01, 5645 }, { 5646 .compatible = "auo,g190ean01", 5647 .data = &auo_g190ean01, 5648 }, { 5649 .compatible = "auo,p238han01", 5650 .data = &auo_p238han01, 5651 }, { 5652 .compatible = "auo,p320hvn03", 5653 .data = &auo_p320hvn03, 5654 }, { 5655 .compatible = "auo,t215hvn01", 5656 .data = &auo_t215hvn01, 5657 }, { 5658 .compatible = "avic,tm070ddh03", 5659 .data = &avic_tm070ddh03, 5660 }, { 5661 .compatible = "bananapi,s070wv20-ct16", 5662 .data = &bananapi_s070wv20_ct16, 5663 }, { 5664 .compatible = "boe,av101hdt-a10", 5665 .data = &boe_av101hdt_a10, 5666 }, { 5667 .compatible = "boe,av123z7m-n17", 5668 .data = &boe_av123z7m_n17, 5669 }, { 5670 .compatible = "boe,bp082wx1-100", 5671 .data = &boe_bp082wx1_100, 5672 }, { 5673 .compatible = "boe,bp101wx1-100", 5674 .data = &boe_bp101wx1_100, 5675 }, { 5676 .compatible = "boe,ev121wxm-n10-1850", 5677 .data = &boe_ev121wxm_n10_1850, 5678 }, { 5679 .compatible = "boe,hv070wsa-100", 5680 .data = &boe_hv070wsa 5681 }, { 5682 .compatible = "cct,cmt430b19n00", 5683 .data = &cct_cmt430b19n00, 5684 }, { 5685 .compatible = "cdtech,s043wq26h-ct7", 5686 .data = &cdtech_s043wq26h_ct7, 5687 }, { 5688 .compatible = "cdtech,s070pws19hp-fc21", 5689 .data = &cdtech_s070pws19hp_fc21, 5690 }, { 5691 .compatible = "cdtech,s070swv29hg-dc44", 5692 .data = &cdtech_s070swv29hg_dc44, 5693 }, { 5694 .compatible = "cdtech,s070wv95-ct16", 5695 .data = &cdtech_s070wv95_ct16, 5696 }, { 5697 .compatible = "chefree,ch101olhlwh-002", 5698 .data = &chefree_ch101olhlwh_002, 5699 }, { 5700 .compatible = "chunghwa,claa070wp03xg", 5701 .data = &chunghwa_claa070wp03xg, 5702 }, { 5703 .compatible = "chunghwa,claa101wa01a", 5704 .data = &chunghwa_claa101wa01a 5705 }, { 5706 .compatible = "chunghwa,claa101wb01", 5707 .data = &chunghwa_claa101wb01 5708 }, { 5709 .compatible = "dataimage,fg040346dsswbg04", 5710 .data = &dataimage_fg040346dsswbg04, 5711 }, { 5712 .compatible = "dataimage,fg1001l0dsswmg01", 5713 .data = &dataimage_fg1001l0dsswmg01, 5714 }, { 5715 .compatible = "dataimage,scf0700c48ggu18", 5716 .data = &dataimage_scf0700c48ggu18, 5717 }, { 5718 .compatible = "displaytech,dt050btft-pts", 5719 .data = &displaytech_dt050btft_pts, 5720 }, { 5721 .compatible = "dlc,dlc0700yzg-1", 5722 .data = &dlc_dlc0700yzg_1, 5723 }, { 5724 .compatible = "dlc,dlc1010gig", 5725 .data = &dlc_dlc1010gig, 5726 }, { 5727 .compatible = "edt,et035012dm6", 5728 .data = &edt_et035012dm6, 5729 }, { 5730 .compatible = "edt,etm0350g0dh6", 5731 .data = &edt_etm0350g0dh6, 5732 }, { 5733 .compatible = "edt,etm043080dh6gp", 5734 .data = &edt_etm043080dh6gp, 5735 }, { 5736 .compatible = "edt,etm0430g0dh6", 5737 .data = &edt_etm0430g0dh6, 5738 }, { 5739 .compatible = "edt,et057023udba", 5740 .data = &edt_et057023udba, 5741 }, { 5742 .compatible = "edt,et057090dhu", 5743 .data = &edt_et057090dhu, 5744 }, { 5745 .compatible = "edt,et070080dh6", 5746 .data = &edt_etm0700g0dh6, 5747 }, { 5748 .compatible = "edt,etm0700g0dh6", 5749 .data = &edt_etm0700g0dh6, 5750 }, { 5751 .compatible = "edt,etm0700g0bdh6", 5752 .data = &edt_etm0700g0bdh6, 5753 }, { 5754 .compatible = "edt,etm0700g0edh6", 5755 .data = &edt_etm0700g0bdh6, 5756 }, { 5757 .compatible = "edt,etml0700y5dha", 5758 .data = &edt_etml0700y5dha, 5759 }, { 5760 .compatible = "edt,etml1010g3dra", 5761 .data = &edt_etml1010g3dra, 5762 }, { 5763 .compatible = "edt,etmv570g2dhu", 5764 .data = &edt_etmv570g2dhu, 5765 }, { 5766 .compatible = "eink,vb3300-kca", 5767 .data = &eink_vb3300_kca, 5768 }, { 5769 .compatible = "evervision,vgg644804", 5770 .data = &evervision_vgg644804, 5771 }, { 5772 .compatible = "evervision,vgg804821", 5773 .data = &evervision_vgg804821, 5774 }, { 5775 .compatible = "foxlink,fl500wvr00-a0t", 5776 .data = &foxlink_fl500wvr00_a0t, 5777 }, { 5778 .compatible = "frida,frd350h54004", 5779 .data = &frida_frd350h54004, 5780 }, { 5781 .compatible = "giantplus,gpg482739qs5", 5782 .data = &giantplus_gpg482739qs5 5783 }, { 5784 .compatible = "giantplus,gpm940b0", 5785 .data = &giantplus_gpm940b0, 5786 }, { 5787 .compatible = "hannstar,hsd070pww1", 5788 .data = &hannstar_hsd070pww1, 5789 }, { 5790 .compatible = "hannstar,hsd100pxn1", 5791 .data = &hannstar_hsd100pxn1, 5792 }, { 5793 .compatible = "hannstar,hsd101pww2", 5794 .data = &hannstar_hsd101pww2, 5795 }, { 5796 .compatible = "hannstar,hsd156juw2", 5797 .data = &hannstar_hsd156juw2, 5798 }, { 5799 .compatible = "hit,tx23d38vm0caa", 5800 .data = &hitachi_tx23d38vm0caa 5801 }, { 5802 .compatible = "innolux,at043tn24", 5803 .data = &innolux_at043tn24, 5804 }, { 5805 .compatible = "innolux,at070tn92", 5806 .data = &innolux_at070tn92, 5807 }, { 5808 .compatible = "innolux,g070ace-l01", 5809 .data = &innolux_g070ace_l01, 5810 }, { 5811 .compatible = "innolux,g070ace-lh3", 5812 .data = &innolux_g070ace_lh3, 5813 }, { 5814 .compatible = "innolux,g070y2-l01", 5815 .data = &innolux_g070y2_l01, 5816 }, { 5817 .compatible = "innolux,g070y2-t02", 5818 .data = &innolux_g070y2_t02, 5819 }, { 5820 .compatible = "innolux,g101ice-l01", 5821 .data = &innolux_g101ice_l01 5822 }, { 5823 .compatible = "innolux,g121i1-l01", 5824 .data = &innolux_g121i1_l01 5825 }, { 5826 .compatible = "innolux,g121x1-l03", 5827 .data = &innolux_g121x1_l03, 5828 }, { 5829 .compatible = "innolux,g121xce-l01", 5830 .data = &innolux_g121xce_l01, 5831 }, { 5832 .compatible = "innolux,g150xge-l05", 5833 .data = &innolux_g150xge_l05, 5834 }, { 5835 .compatible = "innolux,g156hce-l01", 5836 .data = &innolux_g156hce_l01, 5837 }, { 5838 .compatible = "innolux,n156bge-l21", 5839 .data = &innolux_n156bge_l21, 5840 }, { 5841 .compatible = "innolux,zj070na-01p", 5842 .data = &innolux_zj070na_01p, 5843 }, { 5844 .compatible = "jutouch,jt070tm041", 5845 .data = &jutouch_jt070tm041, 5846 }, { 5847 .compatible = "jutouch,jt101tm023", 5848 .data = &jutouch_jt101tm023, 5849 }, { 5850 .compatible = "koe,tx14d24vm1bpa", 5851 .data = &koe_tx14d24vm1bpa, 5852 }, { 5853 .compatible = "koe,tx26d202vm0bwa", 5854 .data = &koe_tx26d202vm0bwa, 5855 }, { 5856 .compatible = "koe,tx31d200vm0baa", 5857 .data = &koe_tx31d200vm0baa, 5858 }, { 5859 .compatible = "kyo,tcg121xglp", 5860 .data = &kyo_tcg121xglp, 5861 }, { 5862 .compatible = "lemaker,bl035-rgb-002", 5863 .data = &lemaker_bl035_rgb_002, 5864 }, { 5865 .compatible = "lg,lb070wv8", 5866 .data = &lg_lb070wv8, 5867 }, { 5868 .compatible = "lincolntech,lcd185-101ct", 5869 .data = &lincolntech_lcd185_101ct, 5870 }, { 5871 .compatible = "logicpd,type28", 5872 .data = &logicpd_type_28, 5873 }, { 5874 .compatible = "logictechno,lt161010-2nhc", 5875 .data = &logictechno_lt161010_2nh, 5876 }, { 5877 .compatible = "logictechno,lt161010-2nhr", 5878 .data = &logictechno_lt161010_2nh, 5879 }, { 5880 .compatible = "logictechno,lt170410-2whc", 5881 .data = &logictechno_lt170410_2whc, 5882 }, { 5883 .compatible = "logictechno,lttd800480070-l2rt", 5884 .data = &logictechno_lttd800480070_l2rt, 5885 }, { 5886 .compatible = "logictechno,lttd800480070-l6wh-rt", 5887 .data = &logictechno_lttd800480070_l6wh_rt, 5888 }, { 5889 .compatible = "microtips,mf-101hiebcaf0", 5890 .data = µtips_mf_101hiebcaf0_c, 5891 }, { 5892 .compatible = "microtips,mf-103hieb0ga0", 5893 .data = µtips_mf_103hieb0ga0, 5894 }, { 5895 .compatible = "mitsubishi,aa070mc01-ca1", 5896 .data = &mitsubishi_aa070mc01, 5897 }, { 5898 .compatible = "mitsubishi,aa084xe01", 5899 .data = &mitsubishi_aa084xe01, 5900 }, { 5901 .compatible = "multi-inno,mi0700a2t-30", 5902 .data = &multi_inno_mi0700a2t_30, 5903 }, { 5904 .compatible = "multi-inno,mi0700s4t-6", 5905 .data = &multi_inno_mi0700s4t_6, 5906 }, { 5907 .compatible = "multi-inno,mi0800ft-9", 5908 .data = &multi_inno_mi0800ft_9, 5909 }, { 5910 .compatible = "multi-inno,mi1010ait-1cp", 5911 .data = &multi_inno_mi1010ait_1cp, 5912 }, { 5913 .compatible = "multi-inno,mi1010z1t-1cp11", 5914 .data = &multi_inno_mi1010z1t_1cp11, 5915 }, { 5916 .compatible = "nec,nl12880bc20-05", 5917 .data = &nec_nl12880bc20_05, 5918 }, { 5919 .compatible = "nec,nl4827hc19-05b", 5920 .data = &nec_nl4827hc19_05b, 5921 }, { 5922 .compatible = "netron-dy,e231732", 5923 .data = &netron_dy_e231732, 5924 }, { 5925 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 5926 .data = &newhaven_nhd_43_480272ef_atxl, 5927 }, { 5928 .compatible = "nlt,nl13676bc25-03f", 5929 .data = &nlt_nl13676bc25_03f, 5930 }, { 5931 .compatible = "nlt,nl192108ac18-02d", 5932 .data = &nlt_nl192108ac18_02d, 5933 }, { 5934 .compatible = "nvd,9128", 5935 .data = &nvd_9128, 5936 }, { 5937 .compatible = "okaya,rs800480t-7x0gp", 5938 .data = &okaya_rs800480t_7x0gp, 5939 }, { 5940 .compatible = "olimex,lcd-olinuxino-43-ts", 5941 .data = &olimex_lcd_olinuxino_43ts, 5942 }, { 5943 .compatible = "olimex,lcd-olinuxino-5-cts", 5944 .data = &olimex_lcd_olinuxino_5cts, 5945 }, { 5946 .compatible = "ontat,kd50g21-40nt-a1", 5947 .data = &ontat_kd50g21_40nt_a1, 5948 }, { 5949 .compatible = "ontat,yx700wv03", 5950 .data = &ontat_yx700wv03, 5951 }, { 5952 .compatible = "ortustech,com37h3m05dtc", 5953 .data = &ortustech_com37h3m, 5954 }, { 5955 .compatible = "ortustech,com37h3m99dtc", 5956 .data = &ortustech_com37h3m, 5957 }, { 5958 .compatible = "ortustech,com43h4m85ulc", 5959 .data = &ortustech_com43h4m85ulc, 5960 }, { 5961 .compatible = "osddisplays,osd070t1718-19ts", 5962 .data = &osddisplays_osd070t1718_19ts, 5963 }, { 5964 .compatible = "pda,91-00156-a0", 5965 .data = &pda_91_00156_a0, 5966 }, { 5967 .compatible = "powertip,ph128800t004-zza01", 5968 .data = &powertip_ph128800t004_zza01, 5969 }, { 5970 .compatible = "powertip,ph128800t006-zhc01", 5971 .data = &powertip_ph128800t006_zhc01, 5972 }, { 5973 .compatible = "powertip,ph800480t013-idf02", 5974 .data = &powertip_ph800480t013_idf02, 5975 }, { 5976 .compatible = "powertip,ph800480t032-zhc19", 5977 .data = &powertip_ph800480t032_zhc19, 5978 }, { 5979 .compatible = "primeview,pm070wl4", 5980 .data = &primeview_pm070wl4, 5981 }, { 5982 .compatible = "qiaodian,qd43003c0-40", 5983 .data = &qd43003c0_40, 5984 }, { 5985 .compatible = "qishenglong,gopher2b-lcd", 5986 .data = &qishenglong_gopher2b_lcd, 5987 }, { 5988 .compatible = "raystar,rff500f-awh-dnn", 5989 .data = &raystar_rff500f_awh_dnn, 5990 }, { 5991 .compatible = "rocktech,rk043fn48h", 5992 .data = &rocktech_rk043fn48h, 5993 }, { 5994 .compatible = "rocktech,rk070er9427", 5995 .data = &rocktech_rk070er9427, 5996 }, { 5997 .compatible = "rocktech,rk101ii01d-ct", 5998 .data = &rocktech_rk101ii01d_ct, 5999 }, { 6000 .compatible = "samsung,ltl101al01", 6001 .data = &samsung_ltl101al01, 6002 }, { 6003 .compatible = "samsung,ltl106al01", 6004 .data = &samsung_ltl106al01, 6005 }, { 6006 .compatible = "samsung,ltn101nt05", 6007 .data = &samsung_ltn101nt05, 6008 }, { 6009 .compatible = "satoz,sat050at40h12r2", 6010 .data = &satoz_sat050at40h12r2, 6011 }, { 6012 .compatible = "sharp,lq035q7db03", 6013 .data = &sharp_lq035q7db03, 6014 }, { 6015 .compatible = "sharp,lq070y3dg3b", 6016 .data = &sharp_lq070y3dg3b, 6017 }, { 6018 .compatible = "sharp,lq101k1ly04", 6019 .data = &sharp_lq101k1ly04, 6020 }, { 6021 .compatible = "sharp,ls020b1dd01d", 6022 .data = &sharp_ls020b1dd01d, 6023 }, { 6024 .compatible = "shelly,sca07010-bfn-lnn", 6025 .data = &shelly_sca07010_bfn_lnn, 6026 }, { 6027 .compatible = "starry,kr070pe2t", 6028 .data = &starry_kr070pe2t, 6029 }, { 6030 .compatible = "startek,kd070hdfld092", 6031 .data = &startek_kd070hdfld092, 6032 }, { 6033 .compatible = "startek,kd070wvfpa", 6034 .data = &startek_kd070wvfpa, 6035 }, { 6036 .compatible = "team-source-display,tst043015cmhx", 6037 .data = &tsd_tst043015cmhx, 6038 }, { 6039 .compatible = "tfc,s9700rtwv43tr-01b", 6040 .data = &tfc_s9700rtwv43tr_01b, 6041 }, { 6042 .compatible = "tianma,p0700wxf1mbaa", 6043 .data = &tianma_p0700wxf1mbaa, 6044 }, { 6045 .compatible = "tianma,tm050rdh03", 6046 .data = &ontat_kd50g21_40nt_a1, 6047 }, { 6048 .compatible = "tianma,tm070jdhg30", 6049 .data = &tianma_tm070jdhg30, 6050 }, { 6051 .compatible = "tianma,tm070jdhg34-00", 6052 .data = &tianma_tm070jdhg34_00, 6053 }, { 6054 .compatible = "tianma,tm070jvhg33", 6055 .data = &tianma_tm070jvhg33, 6056 }, { 6057 .compatible = "tianma,tm070rvhg71", 6058 .data = &tianma_tm070rvhg71, 6059 }, { 6060 .compatible = "ti,nspire-cx-lcd-panel", 6061 .data = &ti_nspire_cx_lcd_panel, 6062 }, { 6063 .compatible = "ti,nspire-classic-lcd-panel", 6064 .data = &ti_nspire_classic_lcd_panel, 6065 }, { 6066 .compatible = "toshiba,lt089ac29000", 6067 .data = &toshiba_lt089ac29000, 6068 }, { 6069 .compatible = "topland,tian-g07017-01", 6070 .data = &topland_tian_g07017_01, 6071 }, { 6072 .compatible = "tpk,f07a-0102", 6073 .data = &tpk_f07a_0102, 6074 }, { 6075 .compatible = "tpk,f10a-0102", 6076 .data = &tpk_f10a_0102, 6077 }, { 6078 .compatible = "urt,umsh-8596md-t", 6079 .data = &urt_umsh_8596md_parallel, 6080 }, { 6081 .compatible = "urt,umsh-8596md-1t", 6082 .data = &urt_umsh_8596md_parallel, 6083 }, { 6084 .compatible = "urt,umsh-8596md-7t", 6085 .data = &urt_umsh_8596md_parallel, 6086 }, { 6087 .compatible = "urt,umsh-8596md-11t", 6088 .data = &urt_umsh_8596md_lvds, 6089 }, { 6090 .compatible = "urt,umsh-8596md-19t", 6091 .data = &urt_umsh_8596md_lvds, 6092 }, { 6093 .compatible = "urt,umsh-8596md-20t", 6094 .data = &urt_umsh_8596md_parallel, 6095 }, { 6096 .compatible = "vivax,tpc9150-panel", 6097 .data = &vivax_tpc9150_panel, 6098 }, { 6099 .compatible = "vxt,vl050-8048nt-c01", 6100 .data = &vl050_8048nt_c01, 6101 }, { 6102 .compatible = "waveshare,2.8inch-panel", 6103 .data = &waveshare_28_lcd_panel 6104 }, { 6105 .compatible = "waveshare,3.4inch-c-panel", 6106 .data = &waveshare_34_lcd_c_panel 6107 }, { 6108 .compatible = "waveshare,4.0inch-panel", 6109 .data = &waveshare_40_lcd_panel 6110 }, { 6111 .compatible = "waveshare,4.0inch-c-panel", 6112 .data = &waveshare_40_lcd_c_panel 6113 }, { 6114 .compatible = "waveshare,5.0inch-c-panel", 6115 .data = &waveshare_50_lcd_c_panel 6116 }, { 6117 .compatible = "waveshare,5.0inch-d-panel", 6118 .data = &waveshare_50_lcd_d_panel 6119 }, { 6120 .compatible = "waveshare,6.25inch-panel", 6121 .data = &waveshare_625_lcd_panel 6122 }, { 6123 .compatible = "waveshare,7.0inch-c-panel", 6124 .data = &waveshare_70_lcd_c_panel 6125 }, { 6126 .compatible = "waveshare,7.0inch-e-panel", 6127 .data = &waveshare_70_lcd_e_panel 6128 }, { 6129 .compatible = "waveshare,7.0inch-h-panel", 6130 .data = &waveshare_70_lcd_h_panel 6131 }, { 6132 .compatible = "waveshare,7.9inch-panel", 6133 .data = &waveshare_79_lcd_panel 6134 }, { 6135 .compatible = "waveshare,8.0inch-c-panel", 6136 .data = &waveshare_80_lcd_c_panel 6137 }, { 6138 .compatible = "waveshare,8.8inch-panel", 6139 .data = &waveshare_88_lcd_panel 6140 }, { 6141 .compatible = "waveshare,10.1inch-c-panel", 6142 .data = &waveshare_101_lcd_c_panel 6143 }, { 6144 .compatible = "waveshare,11.9inch-panel", 6145 .data = &waveshare_119_lcd_panel 6146 }, { 6147 .compatible = "waveshare,13.3inch-panel", 6148 .data = &waveshare_133inch, 6149 }, { 6150 .compatible = "winstar,wf35ltiacd", 6151 .data = &winstar_wf35ltiacd, 6152 }, { 6153 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 6154 .data = &yes_optoelectronics_ytc700tlag_05_201c, 6155 }, { 6156 .compatible = "microchip,ac69t88a", 6157 .data = &mchp_ac69t88a, 6158 }, { 6159 /* Must be the last entry */ 6160 .compatible = "panel-dpi", 6161 6162 /* 6163 * Explicitly NULL, the panel_desc structure will be 6164 * allocated by panel_dpi_probe(). 6165 */ 6166 .data = NULL, 6167 }, { 6168 /* sentinel */ 6169 } 6170 }; 6171 MODULE_DEVICE_TABLE(of, platform_of_match); 6172 6173 static int panel_simple_platform_probe(struct platform_device *pdev) 6174 { 6175 struct panel_simple *panel; 6176 6177 panel = panel_simple_probe(&pdev->dev); 6178 if (IS_ERR(panel)) 6179 return PTR_ERR(panel); 6180 6181 return 0; 6182 } 6183 6184 static void panel_simple_platform_remove(struct platform_device *pdev) 6185 { 6186 panel_simple_remove(&pdev->dev); 6187 } 6188 6189 static void panel_simple_platform_shutdown(struct platform_device *pdev) 6190 { 6191 panel_simple_shutdown(&pdev->dev); 6192 } 6193 6194 static const struct dev_pm_ops panel_simple_pm_ops = { 6195 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 6196 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 6197 pm_runtime_force_resume) 6198 }; 6199 6200 static struct platform_driver panel_simple_platform_driver = { 6201 .driver = { 6202 .name = "panel-simple", 6203 .of_match_table = platform_of_match, 6204 .pm = &panel_simple_pm_ops, 6205 }, 6206 .probe = panel_simple_platform_probe, 6207 .remove = panel_simple_platform_remove, 6208 .shutdown = panel_simple_platform_shutdown, 6209 }; 6210 6211 static const struct drm_display_mode auo_b080uan01_mode = { 6212 .clock = 154500, 6213 .hdisplay = 1200, 6214 .hsync_start = 1200 + 62, 6215 .hsync_end = 1200 + 62 + 4, 6216 .htotal = 1200 + 62 + 4 + 62, 6217 .vdisplay = 1920, 6218 .vsync_start = 1920 + 9, 6219 .vsync_end = 1920 + 9 + 2, 6220 .vtotal = 1920 + 9 + 2 + 8, 6221 }; 6222 6223 static const struct panel_desc_dsi auo_b080uan01 = { 6224 .desc = { 6225 .modes = &auo_b080uan01_mode, 6226 .num_modes = 1, 6227 .bpc = 8, 6228 .size = { 6229 .width = 108, 6230 .height = 272, 6231 }, 6232 .connector_type = DRM_MODE_CONNECTOR_DSI, 6233 }, 6234 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 6235 .format = MIPI_DSI_FMT_RGB888, 6236 .lanes = 4, 6237 }; 6238 6239 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 6240 .clock = 160000, 6241 .hdisplay = 1200, 6242 .hsync_start = 1200 + 120, 6243 .hsync_end = 1200 + 120 + 20, 6244 .htotal = 1200 + 120 + 20 + 21, 6245 .vdisplay = 1920, 6246 .vsync_start = 1920 + 21, 6247 .vsync_end = 1920 + 21 + 3, 6248 .vtotal = 1920 + 21 + 3 + 18, 6249 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 6250 }; 6251 6252 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 6253 .desc = { 6254 .modes = &boe_tv080wum_nl0_mode, 6255 .num_modes = 1, 6256 .size = { 6257 .width = 107, 6258 .height = 172, 6259 }, 6260 .connector_type = DRM_MODE_CONNECTOR_DSI, 6261 }, 6262 .flags = MIPI_DSI_MODE_VIDEO | 6263 MIPI_DSI_MODE_VIDEO_BURST | 6264 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 6265 .format = MIPI_DSI_FMT_RGB888, 6266 .lanes = 4, 6267 }; 6268 6269 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 6270 .clock = 67000, 6271 .hdisplay = 720, 6272 .hsync_start = 720 + 12, 6273 .hsync_end = 720 + 12 + 4, 6274 .htotal = 720 + 12 + 4 + 112, 6275 .vdisplay = 1280, 6276 .vsync_start = 1280 + 8, 6277 .vsync_end = 1280 + 8 + 4, 6278 .vtotal = 1280 + 8 + 4 + 12, 6279 }; 6280 6281 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 6282 .desc = { 6283 .modes = &lg_lh500wx1_sd03_mode, 6284 .num_modes = 1, 6285 .bpc = 8, 6286 .size = { 6287 .width = 62, 6288 .height = 110, 6289 }, 6290 .connector_type = DRM_MODE_CONNECTOR_DSI, 6291 }, 6292 .flags = MIPI_DSI_MODE_VIDEO, 6293 .format = MIPI_DSI_FMT_RGB888, 6294 .lanes = 4, 6295 }; 6296 6297 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 6298 .clock = 157200, 6299 .hdisplay = 1920, 6300 .hsync_start = 1920 + 154, 6301 .hsync_end = 1920 + 154 + 16, 6302 .htotal = 1920 + 154 + 16 + 32, 6303 .vdisplay = 1200, 6304 .vsync_start = 1200 + 17, 6305 .vsync_end = 1200 + 17 + 2, 6306 .vtotal = 1200 + 17 + 2 + 16, 6307 }; 6308 6309 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 6310 .desc = { 6311 .modes = &panasonic_vvx10f004b00_mode, 6312 .num_modes = 1, 6313 .bpc = 8, 6314 .size = { 6315 .width = 217, 6316 .height = 136, 6317 }, 6318 .connector_type = DRM_MODE_CONNECTOR_DSI, 6319 }, 6320 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 6321 MIPI_DSI_CLOCK_NON_CONTINUOUS, 6322 .format = MIPI_DSI_FMT_RGB888, 6323 .lanes = 4, 6324 }; 6325 6326 static const struct drm_display_mode lg_acx467akm_7_mode = { 6327 .clock = 150000, 6328 .hdisplay = 1080, 6329 .hsync_start = 1080 + 2, 6330 .hsync_end = 1080 + 2 + 2, 6331 .htotal = 1080 + 2 + 2 + 2, 6332 .vdisplay = 1920, 6333 .vsync_start = 1920 + 2, 6334 .vsync_end = 1920 + 2 + 2, 6335 .vtotal = 1920 + 2 + 2 + 2, 6336 }; 6337 6338 static const struct panel_desc_dsi lg_acx467akm_7 = { 6339 .desc = { 6340 .modes = &lg_acx467akm_7_mode, 6341 .num_modes = 1, 6342 .bpc = 8, 6343 .size = { 6344 .width = 62, 6345 .height = 110, 6346 }, 6347 .connector_type = DRM_MODE_CONNECTOR_DSI, 6348 }, 6349 .flags = 0, 6350 .format = MIPI_DSI_FMT_RGB888, 6351 .lanes = 4, 6352 }; 6353 6354 static const struct drm_display_mode osd101t2045_53ts_mode = { 6355 .clock = 154500, 6356 .hdisplay = 1920, 6357 .hsync_start = 1920 + 112, 6358 .hsync_end = 1920 + 112 + 16, 6359 .htotal = 1920 + 112 + 16 + 32, 6360 .vdisplay = 1200, 6361 .vsync_start = 1200 + 16, 6362 .vsync_end = 1200 + 16 + 2, 6363 .vtotal = 1200 + 16 + 2 + 16, 6364 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 6365 }; 6366 6367 static const struct panel_desc_dsi osd101t2045_53ts = { 6368 .desc = { 6369 .modes = &osd101t2045_53ts_mode, 6370 .num_modes = 1, 6371 .bpc = 8, 6372 .size = { 6373 .width = 217, 6374 .height = 136, 6375 }, 6376 .connector_type = DRM_MODE_CONNECTOR_DSI, 6377 }, 6378 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 6379 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 6380 MIPI_DSI_MODE_NO_EOT_PACKET, 6381 .format = MIPI_DSI_FMT_RGB888, 6382 .lanes = 4, 6383 }; 6384 6385 static const struct drm_display_mode tsd_tst070wsbe_196c_mode = { 6386 .clock = 52477, 6387 .hdisplay = 1024, 6388 .hsync_start = 1024 + 160, 6389 .hsync_end = 1024 + 160 + 12, 6390 .htotal = 1024 + 160 + 160 + 12, 6391 .vdisplay = 600, 6392 .vsync_start = 600 + 12, 6393 .vsync_end = 600 + 12 + 10, 6394 .vtotal = 600 + 12 + 10 + 23, 6395 }; 6396 6397 static const struct panel_desc_dsi tsd_tst070wsbe_196c = { 6398 .desc = { 6399 .modes = &tsd_tst070wsbe_196c_mode, 6400 .num_modes = 1, 6401 .bpc = 8, 6402 .size = { 6403 .width = 190, 6404 .height = 121, 6405 }, 6406 .delay = { 6407 .prepare = 20, 6408 }, 6409 .connector_type = DRM_MODE_CONNECTOR_DSI, 6410 }, 6411 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM | 6412 MIPI_DSI_MODE_VIDEO_BURST | 6413 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 6414 .format = MIPI_DSI_FMT_RGB888, 6415 .lanes = 4, 6416 }; 6417 6418 static const struct of_device_id dsi_of_match[] = { 6419 { 6420 .compatible = "auo,b080uan01", 6421 .data = &auo_b080uan01 6422 }, { 6423 .compatible = "boe,tv080wum-nl0", 6424 .data = &boe_tv080wum_nl0 6425 }, { 6426 .compatible = "lg,lh500wx1-sd03", 6427 .data = &lg_lh500wx1_sd03 6428 }, { 6429 .compatible = "panasonic,vvx10f004b00", 6430 .data = &panasonic_vvx10f004b00 6431 }, { 6432 .compatible = "lg,acx467akm-7", 6433 .data = &lg_acx467akm_7 6434 }, { 6435 .compatible = "osddisplays,osd101t2045-53ts", 6436 .data = &osd101t2045_53ts 6437 }, { 6438 .compatible = "team-source-display,tst070wsbe-196c", 6439 .data = &tsd_tst070wsbe_196c 6440 }, { 6441 /* sentinel */ 6442 } 6443 }; 6444 MODULE_DEVICE_TABLE(of, dsi_of_match); 6445 6446 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 6447 { 6448 const struct panel_desc_dsi *desc; 6449 struct panel_simple *panel; 6450 int err; 6451 6452 panel = panel_simple_probe(&dsi->dev); 6453 if (IS_ERR(panel)) 6454 return PTR_ERR(panel); 6455 6456 desc = container_of(panel->desc, struct panel_desc_dsi, desc); 6457 dsi->mode_flags = desc->flags; 6458 dsi->format = desc->format; 6459 dsi->lanes = desc->lanes; 6460 6461 err = mipi_dsi_attach(dsi); 6462 if (err) { 6463 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 6464 6465 drm_panel_remove(&panel->base); 6466 } 6467 6468 return err; 6469 } 6470 6471 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 6472 { 6473 int err; 6474 6475 err = mipi_dsi_detach(dsi); 6476 if (err < 0) 6477 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 6478 6479 panel_simple_remove(&dsi->dev); 6480 } 6481 6482 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 6483 { 6484 panel_simple_shutdown(&dsi->dev); 6485 } 6486 6487 static struct mipi_dsi_driver panel_simple_dsi_driver = { 6488 .driver = { 6489 .name = "panel-simple-dsi", 6490 .of_match_table = dsi_of_match, 6491 .pm = &panel_simple_pm_ops, 6492 }, 6493 .probe = panel_simple_dsi_probe, 6494 .remove = panel_simple_dsi_remove, 6495 .shutdown = panel_simple_dsi_shutdown, 6496 }; 6497 6498 static int __init panel_simple_init(void) 6499 { 6500 int err; 6501 6502 err = platform_driver_register(&panel_simple_platform_driver); 6503 if (err < 0) 6504 return err; 6505 6506 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 6507 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 6508 if (err < 0) 6509 goto err_did_platform_register; 6510 } 6511 6512 return 0; 6513 6514 err_did_platform_register: 6515 platform_driver_unregister(&panel_simple_platform_driver); 6516 6517 return err; 6518 } 6519 module_init(panel_simple_init); 6520 6521 static void __exit panel_simple_exit(void) 6522 { 6523 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 6524 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 6525 6526 platform_driver_unregister(&panel_simple_platform_driver); 6527 } 6528 module_exit(panel_simple_exit); 6529 6530 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 6531 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 6532 MODULE_LICENSE("GPL and additional rights"); 6533