1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_device.h> 30 #include <linux/of_platform.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/regulator/consumer.h> 34 35 #include <video/display_timing.h> 36 #include <video/of_display_timing.h> 37 #include <video/videomode.h> 38 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_device.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_mipi_dsi.h> 43 #include <drm/drm_panel.h> 44 #include <drm/drm_of.h> 45 46 /** 47 * struct panel_desc - Describes a simple panel. 48 */ 49 struct panel_desc { 50 /** 51 * @modes: Pointer to array of fixed modes appropriate for this panel. 52 * 53 * If only one mode then this can just be the address of the mode. 54 * NOTE: cannot be used with "timings" and also if this is specified 55 * then you cannot override the mode in the device tree. 56 */ 57 const struct drm_display_mode *modes; 58 59 /** @num_modes: Number of elements in modes array. */ 60 unsigned int num_modes; 61 62 /** 63 * @timings: Pointer to array of display timings 64 * 65 * NOTE: cannot be used with "modes" and also these will be used to 66 * validate a device tree override if one is present. 67 */ 68 const struct display_timing *timings; 69 70 /** @num_timings: Number of elements in timings array. */ 71 unsigned int num_timings; 72 73 /** @bpc: Bits per color. */ 74 unsigned int bpc; 75 76 /** @size: Structure containing the physical size of this panel. */ 77 struct { 78 /** 79 * @size.width: Width (in mm) of the active display area. 80 */ 81 unsigned int width; 82 83 /** 84 * @size.height: Height (in mm) of the active display area. 85 */ 86 unsigned int height; 87 } size; 88 89 /** @delay: Structure containing various delay values for this panel. */ 90 struct { 91 /** 92 * @delay.prepare: Time for the panel to become ready. 93 * 94 * The time (in milliseconds) that it takes for the panel to 95 * become ready and start receiving video data 96 */ 97 unsigned int prepare; 98 99 /** 100 * @delay.enable: Time for the panel to display a valid frame. 101 * 102 * The time (in milliseconds) that it takes for the panel to 103 * display the first valid frame after starting to receive 104 * video data. 105 */ 106 unsigned int enable; 107 108 /** 109 * @delay.disable: Time for the panel to turn the display off. 110 * 111 * The time (in milliseconds) that it takes for the panel to 112 * turn the display off (no content is visible). 113 */ 114 unsigned int disable; 115 116 /** 117 * @delay.unprepare: Time to power down completely. 118 * 119 * The time (in milliseconds) that it takes for the panel 120 * to power itself down completely. 121 * 122 * This time is used to prevent a future "prepare" from 123 * starting until at least this many milliseconds has passed. 124 * If at prepare time less time has passed since unprepare 125 * finished, the driver waits for the remaining time. 126 */ 127 unsigned int unprepare; 128 } delay; 129 130 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 131 u32 bus_format; 132 133 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 134 u32 bus_flags; 135 136 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 137 int connector_type; 138 }; 139 140 struct panel_desc_dsi { 141 struct panel_desc desc; 142 143 unsigned long flags; 144 enum mipi_dsi_pixel_format format; 145 unsigned int lanes; 146 }; 147 148 struct panel_simple { 149 struct drm_panel base; 150 151 ktime_t unprepared_time; 152 153 const struct panel_desc *desc; 154 155 struct regulator *supply; 156 struct i2c_adapter *ddc; 157 158 struct gpio_desc *enable_gpio; 159 160 const struct drm_edid *drm_edid; 161 162 struct drm_display_mode override_mode; 163 164 enum drm_panel_orientation orientation; 165 }; 166 167 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 168 { 169 return container_of(panel, struct panel_simple, base); 170 } 171 172 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 173 struct drm_connector *connector) 174 { 175 struct drm_display_mode *mode; 176 unsigned int i, num = 0; 177 178 for (i = 0; i < panel->desc->num_timings; i++) { 179 const struct display_timing *dt = &panel->desc->timings[i]; 180 struct videomode vm; 181 182 videomode_from_timing(dt, &vm); 183 mode = drm_mode_create(connector->dev); 184 if (!mode) { 185 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 186 dt->hactive.typ, dt->vactive.typ); 187 continue; 188 } 189 190 drm_display_mode_from_videomode(&vm, mode); 191 192 mode->type |= DRM_MODE_TYPE_DRIVER; 193 194 if (panel->desc->num_timings == 1) 195 mode->type |= DRM_MODE_TYPE_PREFERRED; 196 197 drm_mode_probed_add(connector, mode); 198 num++; 199 } 200 201 return num; 202 } 203 204 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 205 struct drm_connector *connector) 206 { 207 struct drm_display_mode *mode; 208 unsigned int i, num = 0; 209 210 for (i = 0; i < panel->desc->num_modes; i++) { 211 const struct drm_display_mode *m = &panel->desc->modes[i]; 212 213 mode = drm_mode_duplicate(connector->dev, m); 214 if (!mode) { 215 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 216 m->hdisplay, m->vdisplay, 217 drm_mode_vrefresh(m)); 218 continue; 219 } 220 221 mode->type |= DRM_MODE_TYPE_DRIVER; 222 223 if (panel->desc->num_modes == 1) 224 mode->type |= DRM_MODE_TYPE_PREFERRED; 225 226 drm_mode_set_name(mode); 227 228 drm_mode_probed_add(connector, mode); 229 num++; 230 } 231 232 return num; 233 } 234 235 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 236 struct drm_connector *connector) 237 { 238 struct drm_display_mode *mode; 239 bool has_override = panel->override_mode.type; 240 unsigned int num = 0; 241 242 if (!panel->desc) 243 return 0; 244 245 if (has_override) { 246 mode = drm_mode_duplicate(connector->dev, 247 &panel->override_mode); 248 if (mode) { 249 drm_mode_probed_add(connector, mode); 250 num = 1; 251 } else { 252 dev_err(panel->base.dev, "failed to add override mode\n"); 253 } 254 } 255 256 /* Only add timings if override was not there or failed to validate */ 257 if (num == 0 && panel->desc->num_timings) 258 num = panel_simple_get_timings_modes(panel, connector); 259 260 /* 261 * Only add fixed modes if timings/override added no mode. 262 * 263 * We should only ever have either the display timings specified 264 * or a fixed mode. Anything else is rather bogus. 265 */ 266 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 267 if (num == 0) 268 num = panel_simple_get_display_modes(panel, connector); 269 270 connector->display_info.bpc = panel->desc->bpc; 271 connector->display_info.width_mm = panel->desc->size.width; 272 connector->display_info.height_mm = panel->desc->size.height; 273 if (panel->desc->bus_format) 274 drm_display_info_set_bus_formats(&connector->display_info, 275 &panel->desc->bus_format, 1); 276 connector->display_info.bus_flags = panel->desc->bus_flags; 277 278 return num; 279 } 280 281 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 282 { 283 ktime_t now_ktime, min_ktime; 284 285 if (!min_ms) 286 return; 287 288 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 289 now_ktime = ktime_get_boottime(); 290 291 if (ktime_before(now_ktime, min_ktime)) 292 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 293 } 294 295 static int panel_simple_disable(struct drm_panel *panel) 296 { 297 struct panel_simple *p = to_panel_simple(panel); 298 299 if (p->desc->delay.disable) 300 msleep(p->desc->delay.disable); 301 302 return 0; 303 } 304 305 static int panel_simple_suspend(struct device *dev) 306 { 307 struct panel_simple *p = dev_get_drvdata(dev); 308 309 gpiod_set_value_cansleep(p->enable_gpio, 0); 310 regulator_disable(p->supply); 311 p->unprepared_time = ktime_get_boottime(); 312 313 drm_edid_free(p->drm_edid); 314 p->drm_edid = NULL; 315 316 return 0; 317 } 318 319 static int panel_simple_unprepare(struct drm_panel *panel) 320 { 321 int ret; 322 323 pm_runtime_mark_last_busy(panel->dev); 324 ret = pm_runtime_put_autosuspend(panel->dev); 325 if (ret < 0) 326 return ret; 327 328 return 0; 329 } 330 331 static int panel_simple_resume(struct device *dev) 332 { 333 struct panel_simple *p = dev_get_drvdata(dev); 334 int err; 335 336 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 337 338 err = regulator_enable(p->supply); 339 if (err < 0) { 340 dev_err(dev, "failed to enable supply: %d\n", err); 341 return err; 342 } 343 344 gpiod_set_value_cansleep(p->enable_gpio, 1); 345 346 if (p->desc->delay.prepare) 347 msleep(p->desc->delay.prepare); 348 349 return 0; 350 } 351 352 static int panel_simple_prepare(struct drm_panel *panel) 353 { 354 int ret; 355 356 ret = pm_runtime_get_sync(panel->dev); 357 if (ret < 0) { 358 pm_runtime_put_autosuspend(panel->dev); 359 return ret; 360 } 361 362 return 0; 363 } 364 365 static int panel_simple_enable(struct drm_panel *panel) 366 { 367 struct panel_simple *p = to_panel_simple(panel); 368 369 if (p->desc->delay.enable) 370 msleep(p->desc->delay.enable); 371 372 return 0; 373 } 374 375 static int panel_simple_get_modes(struct drm_panel *panel, 376 struct drm_connector *connector) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 int num = 0; 380 381 /* probe EDID if a DDC bus is available */ 382 if (p->ddc) { 383 pm_runtime_get_sync(panel->dev); 384 385 if (!p->drm_edid) 386 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 387 388 drm_edid_connector_update(connector, p->drm_edid); 389 390 num += drm_edid_connector_add_modes(connector); 391 392 pm_runtime_mark_last_busy(panel->dev); 393 pm_runtime_put_autosuspend(panel->dev); 394 } 395 396 /* add hard-coded panel modes */ 397 num += panel_simple_get_non_edid_modes(p, connector); 398 399 /* 400 * TODO: Remove once all drm drivers call 401 * drm_connector_set_orientation_from_panel() 402 */ 403 drm_connector_set_panel_orientation(connector, p->orientation); 404 405 return num; 406 } 407 408 static int panel_simple_get_timings(struct drm_panel *panel, 409 unsigned int num_timings, 410 struct display_timing *timings) 411 { 412 struct panel_simple *p = to_panel_simple(panel); 413 unsigned int i; 414 415 if (p->desc->num_timings < num_timings) 416 num_timings = p->desc->num_timings; 417 418 if (timings) 419 for (i = 0; i < num_timings; i++) 420 timings[i] = p->desc->timings[i]; 421 422 return p->desc->num_timings; 423 } 424 425 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 426 { 427 struct panel_simple *p = to_panel_simple(panel); 428 429 return p->orientation; 430 } 431 432 static const struct drm_panel_funcs panel_simple_funcs = { 433 .disable = panel_simple_disable, 434 .unprepare = panel_simple_unprepare, 435 .prepare = panel_simple_prepare, 436 .enable = panel_simple_enable, 437 .get_modes = panel_simple_get_modes, 438 .get_orientation = panel_simple_get_orientation, 439 .get_timings = panel_simple_get_timings, 440 }; 441 442 static struct panel_desc *panel_dpi_probe(struct device *dev) 443 { 444 struct display_timing *timing; 445 const struct device_node *np; 446 struct panel_desc *desc; 447 unsigned int bus_flags; 448 struct videomode vm; 449 int ret; 450 451 np = dev->of_node; 452 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 453 if (!desc) 454 return ERR_PTR(-ENOMEM); 455 456 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 457 if (!timing) 458 return ERR_PTR(-ENOMEM); 459 460 ret = of_get_display_timing(np, "panel-timing", timing); 461 if (ret < 0) { 462 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 463 np); 464 return ERR_PTR(ret); 465 } 466 467 desc->timings = timing; 468 desc->num_timings = 1; 469 470 of_property_read_u32(np, "width-mm", &desc->size.width); 471 of_property_read_u32(np, "height-mm", &desc->size.height); 472 473 /* Extract bus_flags from display_timing */ 474 bus_flags = 0; 475 vm.flags = timing->flags; 476 drm_bus_flags_from_videomode(&vm, &bus_flags); 477 desc->bus_flags = bus_flags; 478 479 /* We do not know the connector for the DT node, so guess it */ 480 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 481 482 return desc; 483 } 484 485 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 486 (to_check->field.typ >= bounds->field.min && \ 487 to_check->field.typ <= bounds->field.max) 488 static void panel_simple_parse_panel_timing_node(struct device *dev, 489 struct panel_simple *panel, 490 const struct display_timing *ot) 491 { 492 const struct panel_desc *desc = panel->desc; 493 struct videomode vm; 494 unsigned int i; 495 496 if (WARN_ON(desc->num_modes)) { 497 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 498 return; 499 } 500 if (WARN_ON(!desc->num_timings)) { 501 dev_err(dev, "Reject override mode: no timings specified\n"); 502 return; 503 } 504 505 for (i = 0; i < panel->desc->num_timings; i++) { 506 const struct display_timing *dt = &panel->desc->timings[i]; 507 508 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 512 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 513 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 514 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 515 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 516 continue; 517 518 if (ot->flags != dt->flags) 519 continue; 520 521 videomode_from_timing(ot, &vm); 522 drm_display_mode_from_videomode(&vm, &panel->override_mode); 523 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 524 DRM_MODE_TYPE_PREFERRED; 525 break; 526 } 527 528 if (WARN_ON(!panel->override_mode.type)) 529 dev_err(dev, "Reject override mode: No display_timing found\n"); 530 } 531 532 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 533 struct panel_simple *panel) 534 { 535 int ret, bpc; 536 537 ret = drm_of_lvds_get_data_mapping(dev->of_node); 538 if (ret < 0) { 539 if (ret == -EINVAL) 540 dev_warn(dev, "Ignore invalid data-mapping property\n"); 541 542 /* 543 * Ignore non-existing or malformatted property, fallback to 544 * default data-mapping, and return 0. 545 */ 546 return 0; 547 } 548 549 switch (ret) { 550 default: 551 WARN_ON(1); 552 fallthrough; 553 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 554 fallthrough; 555 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 556 bpc = 8; 557 break; 558 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 559 bpc = 6; 560 } 561 562 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 563 struct panel_desc *override_desc; 564 565 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 566 if (!override_desc) 567 return -ENOMEM; 568 569 override_desc->bus_format = ret; 570 override_desc->bpc = bpc; 571 panel->desc = override_desc; 572 } 573 574 return 0; 575 } 576 577 static const struct panel_desc *panel_simple_get_desc(struct device *dev) 578 { 579 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI) && 580 dev_is_mipi_dsi(dev)) { 581 const struct panel_desc_dsi *dsi_desc; 582 583 dsi_desc = of_device_get_match_data(dev); 584 if (!dsi_desc) 585 return ERR_PTR(-ENODEV); 586 587 return &dsi_desc->desc; 588 } 589 590 if (dev_is_platform(dev)) { 591 const struct panel_desc *desc; 592 593 desc = of_device_get_match_data(dev); 594 if (!desc) { 595 /* 596 * panel-dpi probes without a descriptor and 597 * panel_dpi_probe() will initialize one for us 598 * based on the device tree. 599 */ 600 if (of_device_is_compatible(dev->of_node, "panel-dpi")) 601 return panel_dpi_probe(dev); 602 else 603 return ERR_PTR(-ENODEV); 604 } 605 606 return desc; 607 } 608 609 return ERR_PTR(-ENODEV); 610 } 611 612 static struct panel_simple *panel_simple_probe(struct device *dev) 613 { 614 const struct panel_desc *desc; 615 struct panel_simple *panel; 616 struct display_timing dt; 617 struct device_node *ddc; 618 int connector_type; 619 u32 bus_flags; 620 int err; 621 622 desc = panel_simple_get_desc(dev); 623 if (IS_ERR(desc)) 624 return ERR_CAST(desc); 625 626 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 627 &panel_simple_funcs, desc->connector_type); 628 if (IS_ERR(panel)) 629 return ERR_CAST(panel); 630 631 panel->desc = desc; 632 633 panel->supply = devm_regulator_get(dev, "power"); 634 if (IS_ERR(panel->supply)) 635 return ERR_CAST(panel->supply); 636 637 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 638 GPIOD_OUT_LOW); 639 if (IS_ERR(panel->enable_gpio)) 640 return dev_err_cast_probe(dev, panel->enable_gpio, 641 "failed to request GPIO\n"); 642 643 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 644 if (err) { 645 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 646 return ERR_PTR(err); 647 } 648 649 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 650 if (ddc) { 651 panel->ddc = of_find_i2c_adapter_by_node(ddc); 652 of_node_put(ddc); 653 654 if (!panel->ddc) 655 return ERR_PTR(-EPROBE_DEFER); 656 } 657 658 if (!of_device_is_compatible(dev->of_node, "panel-dpi") && 659 !of_get_display_timing(dev->of_node, "panel-timing", &dt)) 660 panel_simple_parse_panel_timing_node(dev, panel, &dt); 661 662 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 663 /* Optional data-mapping property for overriding bus format */ 664 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 665 if (err) 666 goto free_ddc; 667 } 668 669 connector_type = desc->connector_type; 670 /* Catch common mistakes for panels. */ 671 switch (connector_type) { 672 case 0: 673 dev_warn(dev, "Specify missing connector_type\n"); 674 connector_type = DRM_MODE_CONNECTOR_DPI; 675 break; 676 case DRM_MODE_CONNECTOR_LVDS: 677 WARN_ON(desc->bus_flags & 678 ~(DRM_BUS_FLAG_DE_LOW | 679 DRM_BUS_FLAG_DE_HIGH | 680 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 681 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 682 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 683 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 684 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 685 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 686 desc->bpc != 6); 687 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 688 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 689 desc->bpc != 8); 690 break; 691 case DRM_MODE_CONNECTOR_eDP: 692 dev_warn(dev, "eDP panels moved to panel-edp\n"); 693 err = -EINVAL; 694 goto free_ddc; 695 case DRM_MODE_CONNECTOR_DSI: 696 if (desc->bpc != 6 && desc->bpc != 8) 697 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 698 break; 699 case DRM_MODE_CONNECTOR_DPI: 700 bus_flags = DRM_BUS_FLAG_DE_LOW | 701 DRM_BUS_FLAG_DE_HIGH | 702 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 703 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 704 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 705 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 706 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 707 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 708 if (desc->bus_flags & ~bus_flags) 709 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 710 if (!(desc->bus_flags & bus_flags)) 711 dev_warn(dev, "Specify missing bus_flags\n"); 712 if (desc->bus_format == 0) 713 dev_warn(dev, "Specify missing bus_format\n"); 714 if (desc->bpc != 6 && desc->bpc != 8) 715 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 716 break; 717 default: 718 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 719 connector_type = DRM_MODE_CONNECTOR_DPI; 720 break; 721 } 722 723 dev_set_drvdata(dev, panel); 724 725 /* 726 * We use runtime PM for prepare / unprepare since those power the panel 727 * on and off and those can be very slow operations. This is important 728 * to optimize powering the panel on briefly to read the EDID before 729 * fully enabling the panel. 730 */ 731 pm_runtime_enable(dev); 732 pm_runtime_set_autosuspend_delay(dev, 1000); 733 pm_runtime_use_autosuspend(dev); 734 735 err = drm_panel_of_backlight(&panel->base); 736 if (err) { 737 dev_err_probe(dev, err, "Could not find backlight\n"); 738 goto disable_pm_runtime; 739 } 740 741 drm_panel_add(&panel->base); 742 743 return panel; 744 745 disable_pm_runtime: 746 pm_runtime_dont_use_autosuspend(dev); 747 pm_runtime_disable(dev); 748 free_ddc: 749 if (panel->ddc) 750 put_device(&panel->ddc->dev); 751 752 return ERR_PTR(err); 753 } 754 755 static void panel_simple_shutdown(struct device *dev) 756 { 757 struct panel_simple *panel = dev_get_drvdata(dev); 758 759 /* 760 * NOTE: the following two calls don't really belong here. It is the 761 * responsibility of a correctly written DRM modeset driver to call 762 * drm_atomic_helper_shutdown() at shutdown time and that should 763 * cause the panel to be disabled / unprepared if needed. For now, 764 * however, we'll keep these calls due to the sheer number of 765 * different DRM modeset drivers used with panel-simple. Once we've 766 * confirmed that all DRM modeset drivers using this panel properly 767 * call drm_atomic_helper_shutdown() we can simply delete the two 768 * calls below. 769 * 770 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 771 * PANEL DRIVERS. 772 * 773 * FIXME: If we're still haven't figured out if all DRM modeset 774 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 775 * managed to make sure that DRM modeset drivers get their shutdown() 776 * callback before the panel's shutdown() callback (perhaps using 777 * device link), we could add a WARN_ON here to help move forward. 778 */ 779 if (panel->base.enabled) 780 drm_panel_disable(&panel->base); 781 if (panel->base.prepared) 782 drm_panel_unprepare(&panel->base); 783 } 784 785 static void panel_simple_remove(struct device *dev) 786 { 787 struct panel_simple *panel = dev_get_drvdata(dev); 788 789 drm_panel_remove(&panel->base); 790 panel_simple_shutdown(dev); 791 792 pm_runtime_dont_use_autosuspend(dev); 793 pm_runtime_disable(dev); 794 if (panel->ddc) 795 put_device(&panel->ddc->dev); 796 } 797 798 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 799 .clock = 71100, 800 .hdisplay = 1280, 801 .hsync_start = 1280 + 40, 802 .hsync_end = 1280 + 40 + 80, 803 .htotal = 1280 + 40 + 80 + 40, 804 .vdisplay = 800, 805 .vsync_start = 800 + 3, 806 .vsync_end = 800 + 3 + 10, 807 .vtotal = 800 + 3 + 10 + 10, 808 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 809 }; 810 811 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 812 .modes = &ire_am_1280800n3tzqw_t00h_mode, 813 .num_modes = 1, 814 .bpc = 8, 815 .size = { 816 .width = 217, 817 .height = 136, 818 }, 819 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 820 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 821 .connector_type = DRM_MODE_CONNECTOR_LVDS, 822 }; 823 824 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 825 .clock = 9000, 826 .hdisplay = 480, 827 .hsync_start = 480 + 2, 828 .hsync_end = 480 + 2 + 41, 829 .htotal = 480 + 2 + 41 + 2, 830 .vdisplay = 272, 831 .vsync_start = 272 + 2, 832 .vsync_end = 272 + 2 + 10, 833 .vtotal = 272 + 2 + 10 + 2, 834 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 835 }; 836 837 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 838 .modes = &ire_am_480272h3tmqw_t01h_mode, 839 .num_modes = 1, 840 .bpc = 8, 841 .size = { 842 .width = 99, 843 .height = 58, 844 }, 845 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 846 }; 847 848 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 849 .clock = 33333, 850 .hdisplay = 800, 851 .hsync_start = 800 + 0, 852 .hsync_end = 800 + 0 + 255, 853 .htotal = 800 + 0 + 255 + 0, 854 .vdisplay = 480, 855 .vsync_start = 480 + 2, 856 .vsync_end = 480 + 2 + 45, 857 .vtotal = 480 + 2 + 45 + 0, 858 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 859 }; 860 861 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 862 .pixelclock = { 29930000, 33260000, 36590000 }, 863 .hactive = { 800, 800, 800 }, 864 .hfront_porch = { 1, 40, 168 }, 865 .hback_porch = { 88, 88, 88 }, 866 .hsync_len = { 1, 128, 128 }, 867 .vactive = { 480, 480, 480 }, 868 .vfront_porch = { 1, 35, 37 }, 869 .vback_porch = { 8, 8, 8 }, 870 .vsync_len = { 1, 2, 2 }, 871 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 872 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 873 DISPLAY_FLAGS_SYNC_POSEDGE, 874 }; 875 876 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 877 .timings = &ire_am_800480l1tmqw_t00h_timing, 878 .num_timings = 1, 879 .bpc = 8, 880 .size = { 881 .width = 111, 882 .height = 67, 883 }, 884 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 885 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 886 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 887 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 888 .connector_type = DRM_MODE_CONNECTOR_DPI, 889 }; 890 891 static const struct panel_desc ampire_am800480r3tmqwa1h = { 892 .modes = &ire_am800480r3tmqwa1h_mode, 893 .num_modes = 1, 894 .bpc = 6, 895 .size = { 896 .width = 152, 897 .height = 91, 898 }, 899 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 900 }; 901 902 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 903 .pixelclock = { 34500000, 39600000, 50400000 }, 904 .hactive = { 800, 800, 800 }, 905 .hfront_porch = { 12, 112, 312 }, 906 .hback_porch = { 87, 87, 48 }, 907 .hsync_len = { 1, 1, 40 }, 908 .vactive = { 600, 600, 600 }, 909 .vfront_porch = { 1, 21, 61 }, 910 .vback_porch = { 38, 38, 19 }, 911 .vsync_len = { 1, 1, 20 }, 912 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 913 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 914 DISPLAY_FLAGS_SYNC_POSEDGE, 915 }; 916 917 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 918 .timings = &ire_am800600p5tmqw_tb8h_timing, 919 .num_timings = 1, 920 .bpc = 6, 921 .size = { 922 .width = 162, 923 .height = 122, 924 }, 925 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 926 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 927 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 928 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 929 .connector_type = DRM_MODE_CONNECTOR_DPI, 930 }; 931 932 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 933 .pixelclock = { 26400000, 33300000, 46800000 }, 934 .hactive = { 800, 800, 800 }, 935 .hfront_porch = { 16, 210, 354 }, 936 .hback_porch = { 45, 36, 6 }, 937 .hsync_len = { 1, 10, 40 }, 938 .vactive = { 480, 480, 480 }, 939 .vfront_porch = { 7, 22, 147 }, 940 .vback_porch = { 22, 13, 3 }, 941 .vsync_len = { 1, 10, 20 }, 942 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 943 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 944 }; 945 946 static const struct panel_desc armadeus_st0700_adapt = { 947 .timings = &santek_st0700i5y_rbslw_f_timing, 948 .num_timings = 1, 949 .bpc = 6, 950 .size = { 951 .width = 154, 952 .height = 86, 953 }, 954 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 955 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 956 }; 957 958 static const struct drm_display_mode auo_b101aw03_mode = { 959 .clock = 51450, 960 .hdisplay = 1024, 961 .hsync_start = 1024 + 156, 962 .hsync_end = 1024 + 156 + 8, 963 .htotal = 1024 + 156 + 8 + 156, 964 .vdisplay = 600, 965 .vsync_start = 600 + 16, 966 .vsync_end = 600 + 16 + 6, 967 .vtotal = 600 + 16 + 6 + 16, 968 }; 969 970 static const struct panel_desc auo_b101aw03 = { 971 .modes = &auo_b101aw03_mode, 972 .num_modes = 1, 973 .bpc = 6, 974 .size = { 975 .width = 223, 976 .height = 125, 977 }, 978 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 979 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 980 .connector_type = DRM_MODE_CONNECTOR_LVDS, 981 }; 982 983 static const struct drm_display_mode auo_b101xtn01_mode = { 984 .clock = 72000, 985 .hdisplay = 1366, 986 .hsync_start = 1366 + 20, 987 .hsync_end = 1366 + 20 + 70, 988 .htotal = 1366 + 20 + 70, 989 .vdisplay = 768, 990 .vsync_start = 768 + 14, 991 .vsync_end = 768 + 14 + 42, 992 .vtotal = 768 + 14 + 42, 993 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 994 }; 995 996 static const struct panel_desc auo_b101xtn01 = { 997 .modes = &auo_b101xtn01_mode, 998 .num_modes = 1, 999 .bpc = 6, 1000 .size = { 1001 .width = 223, 1002 .height = 125, 1003 }, 1004 }; 1005 1006 static const struct drm_display_mode auo_b116xw03_mode = { 1007 .clock = 70589, 1008 .hdisplay = 1366, 1009 .hsync_start = 1366 + 40, 1010 .hsync_end = 1366 + 40 + 40, 1011 .htotal = 1366 + 40 + 40 + 32, 1012 .vdisplay = 768, 1013 .vsync_start = 768 + 10, 1014 .vsync_end = 768 + 10 + 12, 1015 .vtotal = 768 + 10 + 12 + 6, 1016 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1017 }; 1018 1019 static const struct panel_desc auo_b116xw03 = { 1020 .modes = &auo_b116xw03_mode, 1021 .num_modes = 1, 1022 .bpc = 6, 1023 .size = { 1024 .width = 256, 1025 .height = 144, 1026 }, 1027 .delay = { 1028 .prepare = 1, 1029 .enable = 200, 1030 .disable = 200, 1031 .unprepare = 500, 1032 }, 1033 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1034 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1035 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1036 }; 1037 1038 static const struct display_timing auo_g070vvn01_timings = { 1039 .pixelclock = { 33300000, 34209000, 45000000 }, 1040 .hactive = { 800, 800, 800 }, 1041 .hfront_porch = { 20, 40, 200 }, 1042 .hback_porch = { 87, 40, 1 }, 1043 .hsync_len = { 1, 48, 87 }, 1044 .vactive = { 480, 480, 480 }, 1045 .vfront_porch = { 5, 13, 200 }, 1046 .vback_porch = { 31, 31, 29 }, 1047 .vsync_len = { 1, 1, 3 }, 1048 }; 1049 1050 static const struct panel_desc auo_g070vvn01 = { 1051 .timings = &auo_g070vvn01_timings, 1052 .num_timings = 1, 1053 .bpc = 8, 1054 .size = { 1055 .width = 152, 1056 .height = 91, 1057 }, 1058 .delay = { 1059 .prepare = 200, 1060 .enable = 50, 1061 .disable = 50, 1062 .unprepare = 1000, 1063 }, 1064 }; 1065 1066 static const struct display_timing auo_g101evn010_timing = { 1067 .pixelclock = { 64000000, 68930000, 85000000 }, 1068 .hactive = { 1280, 1280, 1280 }, 1069 .hfront_porch = { 8, 64, 256 }, 1070 .hback_porch = { 8, 64, 256 }, 1071 .hsync_len = { 40, 168, 767 }, 1072 .vactive = { 800, 800, 800 }, 1073 .vfront_porch = { 4, 8, 100 }, 1074 .vback_porch = { 4, 8, 100 }, 1075 .vsync_len = { 8, 16, 223 }, 1076 }; 1077 1078 static const struct panel_desc auo_g101evn010 = { 1079 .timings = &auo_g101evn010_timing, 1080 .num_timings = 1, 1081 .bpc = 6, 1082 .size = { 1083 .width = 216, 1084 .height = 135, 1085 }, 1086 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1087 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1088 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1089 }; 1090 1091 static const struct drm_display_mode auo_g104sn02_mode = { 1092 .clock = 40000, 1093 .hdisplay = 800, 1094 .hsync_start = 800 + 40, 1095 .hsync_end = 800 + 40 + 216, 1096 .htotal = 800 + 40 + 216 + 128, 1097 .vdisplay = 600, 1098 .vsync_start = 600 + 10, 1099 .vsync_end = 600 + 10 + 35, 1100 .vtotal = 600 + 10 + 35 + 2, 1101 }; 1102 1103 static const struct panel_desc auo_g104sn02 = { 1104 .modes = &auo_g104sn02_mode, 1105 .num_modes = 1, 1106 .bpc = 8, 1107 .size = { 1108 .width = 211, 1109 .height = 158, 1110 }, 1111 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1112 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1113 }; 1114 1115 static const struct drm_display_mode auo_g104stn01_mode = { 1116 .clock = 40000, 1117 .hdisplay = 800, 1118 .hsync_start = 800 + 40, 1119 .hsync_end = 800 + 40 + 88, 1120 .htotal = 800 + 40 + 88 + 128, 1121 .vdisplay = 600, 1122 .vsync_start = 600 + 1, 1123 .vsync_end = 600 + 1 + 23, 1124 .vtotal = 600 + 1 + 23 + 4, 1125 }; 1126 1127 static const struct panel_desc auo_g104stn01 = { 1128 .modes = &auo_g104stn01_mode, 1129 .num_modes = 1, 1130 .bpc = 8, 1131 .size = { 1132 .width = 211, 1133 .height = 158, 1134 }, 1135 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1136 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1137 }; 1138 1139 static const struct display_timing auo_g121ean01_timing = { 1140 .pixelclock = { 60000000, 74400000, 90000000 }, 1141 .hactive = { 1280, 1280, 1280 }, 1142 .hfront_porch = { 20, 50, 100 }, 1143 .hback_porch = { 20, 50, 100 }, 1144 .hsync_len = { 30, 100, 200 }, 1145 .vactive = { 800, 800, 800 }, 1146 .vfront_porch = { 2, 10, 25 }, 1147 .vback_porch = { 2, 10, 25 }, 1148 .vsync_len = { 4, 18, 50 }, 1149 }; 1150 1151 static const struct panel_desc auo_g121ean01 = { 1152 .timings = &auo_g121ean01_timing, 1153 .num_timings = 1, 1154 .bpc = 8, 1155 .size = { 1156 .width = 261, 1157 .height = 163, 1158 }, 1159 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1160 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1161 }; 1162 1163 static const struct display_timing auo_g133han01_timings = { 1164 .pixelclock = { 134000000, 141200000, 149000000 }, 1165 .hactive = { 1920, 1920, 1920 }, 1166 .hfront_porch = { 39, 58, 77 }, 1167 .hback_porch = { 59, 88, 117 }, 1168 .hsync_len = { 28, 42, 56 }, 1169 .vactive = { 1080, 1080, 1080 }, 1170 .vfront_porch = { 3, 8, 11 }, 1171 .vback_porch = { 5, 14, 19 }, 1172 .vsync_len = { 4, 14, 19 }, 1173 }; 1174 1175 static const struct panel_desc auo_g133han01 = { 1176 .timings = &auo_g133han01_timings, 1177 .num_timings = 1, 1178 .bpc = 8, 1179 .size = { 1180 .width = 293, 1181 .height = 165, 1182 }, 1183 .delay = { 1184 .prepare = 200, 1185 .enable = 50, 1186 .disable = 50, 1187 .unprepare = 1000, 1188 }, 1189 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1190 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1191 }; 1192 1193 static const struct display_timing auo_g156han04_timings = { 1194 .pixelclock = { 137000000, 141000000, 146000000 }, 1195 .hactive = { 1920, 1920, 1920 }, 1196 .hfront_porch = { 60, 60, 60 }, 1197 .hback_porch = { 90, 92, 111 }, 1198 .hsync_len = { 32, 32, 32 }, 1199 .vactive = { 1080, 1080, 1080 }, 1200 .vfront_porch = { 12, 12, 12 }, 1201 .vback_porch = { 24, 36, 56 }, 1202 .vsync_len = { 8, 8, 8 }, 1203 }; 1204 1205 static const struct panel_desc auo_g156han04 = { 1206 .timings = &auo_g156han04_timings, 1207 .num_timings = 1, 1208 .bpc = 8, 1209 .size = { 1210 .width = 344, 1211 .height = 194, 1212 }, 1213 .delay = { 1214 .prepare = 50, /* T2 */ 1215 .enable = 200, /* T3 */ 1216 .disable = 110, /* T10 */ 1217 .unprepare = 1000, /* T13 */ 1218 }, 1219 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1220 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1221 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1222 }; 1223 1224 static const struct drm_display_mode auo_g156xtn01_mode = { 1225 .clock = 76000, 1226 .hdisplay = 1366, 1227 .hsync_start = 1366 + 33, 1228 .hsync_end = 1366 + 33 + 67, 1229 .htotal = 1560, 1230 .vdisplay = 768, 1231 .vsync_start = 768 + 4, 1232 .vsync_end = 768 + 4 + 4, 1233 .vtotal = 806, 1234 }; 1235 1236 static const struct panel_desc auo_g156xtn01 = { 1237 .modes = &auo_g156xtn01_mode, 1238 .num_modes = 1, 1239 .bpc = 8, 1240 .size = { 1241 .width = 344, 1242 .height = 194, 1243 }, 1244 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1245 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1246 }; 1247 1248 static const struct display_timing auo_g185han01_timings = { 1249 .pixelclock = { 120000000, 144000000, 175000000 }, 1250 .hactive = { 1920, 1920, 1920 }, 1251 .hfront_porch = { 36, 120, 148 }, 1252 .hback_porch = { 24, 88, 108 }, 1253 .hsync_len = { 20, 48, 64 }, 1254 .vactive = { 1080, 1080, 1080 }, 1255 .vfront_porch = { 6, 10, 40 }, 1256 .vback_porch = { 2, 5, 20 }, 1257 .vsync_len = { 2, 5, 20 }, 1258 }; 1259 1260 static const struct panel_desc auo_g185han01 = { 1261 .timings = &auo_g185han01_timings, 1262 .num_timings = 1, 1263 .bpc = 8, 1264 .size = { 1265 .width = 409, 1266 .height = 230, 1267 }, 1268 .delay = { 1269 .prepare = 50, 1270 .enable = 200, 1271 .disable = 110, 1272 .unprepare = 1000, 1273 }, 1274 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1275 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1276 }; 1277 1278 static const struct display_timing auo_g190ean01_timings = { 1279 .pixelclock = { 90000000, 108000000, 135000000 }, 1280 .hactive = { 1280, 1280, 1280 }, 1281 .hfront_porch = { 126, 184, 1266 }, 1282 .hback_porch = { 84, 122, 844 }, 1283 .hsync_len = { 70, 102, 704 }, 1284 .vactive = { 1024, 1024, 1024 }, 1285 .vfront_porch = { 4, 26, 76 }, 1286 .vback_porch = { 2, 8, 25 }, 1287 .vsync_len = { 2, 8, 25 }, 1288 }; 1289 1290 static const struct panel_desc auo_g190ean01 = { 1291 .timings = &auo_g190ean01_timings, 1292 .num_timings = 1, 1293 .bpc = 8, 1294 .size = { 1295 .width = 376, 1296 .height = 301, 1297 }, 1298 .delay = { 1299 .prepare = 50, 1300 .enable = 200, 1301 .disable = 110, 1302 .unprepare = 1000, 1303 }, 1304 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1305 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1306 }; 1307 1308 static const struct display_timing auo_p320hvn03_timings = { 1309 .pixelclock = { 106000000, 148500000, 164000000 }, 1310 .hactive = { 1920, 1920, 1920 }, 1311 .hfront_porch = { 25, 50, 130 }, 1312 .hback_porch = { 25, 50, 130 }, 1313 .hsync_len = { 20, 40, 105 }, 1314 .vactive = { 1080, 1080, 1080 }, 1315 .vfront_porch = { 8, 17, 150 }, 1316 .vback_porch = { 8, 17, 150 }, 1317 .vsync_len = { 4, 11, 100 }, 1318 }; 1319 1320 static const struct panel_desc auo_p320hvn03 = { 1321 .timings = &auo_p320hvn03_timings, 1322 .num_timings = 1, 1323 .bpc = 8, 1324 .size = { 1325 .width = 698, 1326 .height = 393, 1327 }, 1328 .delay = { 1329 .prepare = 1, 1330 .enable = 450, 1331 .unprepare = 500, 1332 }, 1333 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1334 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1335 }; 1336 1337 static const struct drm_display_mode auo_t215hvn01_mode = { 1338 .clock = 148800, 1339 .hdisplay = 1920, 1340 .hsync_start = 1920 + 88, 1341 .hsync_end = 1920 + 88 + 44, 1342 .htotal = 1920 + 88 + 44 + 148, 1343 .vdisplay = 1080, 1344 .vsync_start = 1080 + 4, 1345 .vsync_end = 1080 + 4 + 5, 1346 .vtotal = 1080 + 4 + 5 + 36, 1347 }; 1348 1349 static const struct panel_desc auo_t215hvn01 = { 1350 .modes = &auo_t215hvn01_mode, 1351 .num_modes = 1, 1352 .bpc = 8, 1353 .size = { 1354 .width = 430, 1355 .height = 270, 1356 }, 1357 .delay = { 1358 .disable = 5, 1359 .unprepare = 1000, 1360 }, 1361 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1362 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1363 }; 1364 1365 static const struct drm_display_mode avic_tm070ddh03_mode = { 1366 .clock = 51200, 1367 .hdisplay = 1024, 1368 .hsync_start = 1024 + 160, 1369 .hsync_end = 1024 + 160 + 4, 1370 .htotal = 1024 + 160 + 4 + 156, 1371 .vdisplay = 600, 1372 .vsync_start = 600 + 17, 1373 .vsync_end = 600 + 17 + 1, 1374 .vtotal = 600 + 17 + 1 + 17, 1375 }; 1376 1377 static const struct panel_desc avic_tm070ddh03 = { 1378 .modes = &avic_tm070ddh03_mode, 1379 .num_modes = 1, 1380 .bpc = 8, 1381 .size = { 1382 .width = 154, 1383 .height = 90, 1384 }, 1385 .delay = { 1386 .prepare = 20, 1387 .enable = 200, 1388 .disable = 200, 1389 }, 1390 }; 1391 1392 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1393 .clock = 30000, 1394 .hdisplay = 800, 1395 .hsync_start = 800 + 40, 1396 .hsync_end = 800 + 40 + 48, 1397 .htotal = 800 + 40 + 48 + 40, 1398 .vdisplay = 480, 1399 .vsync_start = 480 + 13, 1400 .vsync_end = 480 + 13 + 3, 1401 .vtotal = 480 + 13 + 3 + 29, 1402 }; 1403 1404 static const struct panel_desc bananapi_s070wv20_ct16 = { 1405 .modes = &bananapi_s070wv20_ct16_mode, 1406 .num_modes = 1, 1407 .bpc = 6, 1408 .size = { 1409 .width = 154, 1410 .height = 86, 1411 }, 1412 }; 1413 1414 static const struct display_timing boe_av101hdt_a10_timing = { 1415 .pixelclock = { 74210000, 75330000, 76780000, }, 1416 .hactive = { 1280, 1280, 1280, }, 1417 .hfront_porch = { 10, 42, 33, }, 1418 .hback_porch = { 10, 18, 33, }, 1419 .hsync_len = { 30, 10, 30, }, 1420 .vactive = { 720, 720, 720, }, 1421 .vfront_porch = { 200, 183, 200, }, 1422 .vback_porch = { 8, 8, 8, }, 1423 .vsync_len = { 2, 19, 2, }, 1424 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1425 }; 1426 1427 static const struct panel_desc boe_av101hdt_a10 = { 1428 .timings = &boe_av101hdt_a10_timing, 1429 .num_timings = 1, 1430 .bpc = 8, 1431 .size = { 1432 .width = 224, 1433 .height = 126, 1434 }, 1435 .delay = { 1436 .enable = 50, 1437 .disable = 50, 1438 }, 1439 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1440 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1441 }; 1442 1443 static const struct display_timing boe_av123z7m_n17_timing = { 1444 .pixelclock = { 86600000, 88000000, 90800000, }, 1445 .hactive = { 1920, 1920, 1920, }, 1446 .hfront_porch = { 10, 10, 10, }, 1447 .hback_porch = { 10, 10, 10, }, 1448 .hsync_len = { 9, 12, 25, }, 1449 .vactive = { 720, 720, 720, }, 1450 .vfront_porch = { 7, 10, 13, }, 1451 .vback_porch = { 7, 10, 13, }, 1452 .vsync_len = { 7, 11, 14, }, 1453 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1454 }; 1455 1456 static const struct panel_desc boe_av123z7m_n17 = { 1457 .timings = &boe_av123z7m_n17_timing, 1458 .bpc = 8, 1459 .num_timings = 1, 1460 .size = { 1461 .width = 292, 1462 .height = 110, 1463 }, 1464 .delay = { 1465 .prepare = 50, 1466 .disable = 50, 1467 }, 1468 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1469 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1470 }; 1471 1472 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1473 .clock = 78945, 1474 .hdisplay = 1280, 1475 .hsync_start = 1280 + 0, 1476 .hsync_end = 1280 + 0 + 2, 1477 .htotal = 1280 + 62 + 0 + 2, 1478 .vdisplay = 800, 1479 .vsync_start = 800 + 8, 1480 .vsync_end = 800 + 8 + 2, 1481 .vtotal = 800 + 6 + 8 + 2, 1482 }; 1483 1484 static const struct panel_desc boe_bp082wx1_100 = { 1485 .modes = &boe_bp101wx1_100_mode, 1486 .num_modes = 1, 1487 .bpc = 8, 1488 .size = { 1489 .width = 177, 1490 .height = 110, 1491 }, 1492 .delay = { 1493 .enable = 50, 1494 .disable = 50, 1495 }, 1496 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1497 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1498 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1499 }; 1500 1501 static const struct panel_desc boe_bp101wx1_100 = { 1502 .modes = &boe_bp101wx1_100_mode, 1503 .num_modes = 1, 1504 .bpc = 8, 1505 .size = { 1506 .width = 217, 1507 .height = 136, 1508 }, 1509 .delay = { 1510 .enable = 50, 1511 .disable = 50, 1512 }, 1513 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1514 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1515 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1516 }; 1517 1518 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1519 .pixelclock = { 69922000, 71000000, 72293000 }, 1520 .hactive = { 1280, 1280, 1280 }, 1521 .hfront_porch = { 48, 48, 48 }, 1522 .hback_porch = { 80, 80, 80 }, 1523 .hsync_len = { 32, 32, 32 }, 1524 .vactive = { 800, 800, 800 }, 1525 .vfront_porch = { 3, 3, 3 }, 1526 .vback_porch = { 14, 14, 14 }, 1527 .vsync_len = { 6, 6, 6 }, 1528 }; 1529 1530 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1531 .timings = &boe_ev121wxm_n10_1850_timing, 1532 .num_timings = 1, 1533 .bpc = 8, 1534 .size = { 1535 .width = 261, 1536 .height = 163, 1537 }, 1538 .delay = { 1539 .prepare = 9, 1540 .enable = 300, 1541 .unprepare = 300, 1542 .disable = 560, 1543 }, 1544 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1545 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1546 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1547 }; 1548 1549 static const struct drm_display_mode boe_hv070wsa_mode = { 1550 .clock = 42105, 1551 .hdisplay = 1024, 1552 .hsync_start = 1024 + 30, 1553 .hsync_end = 1024 + 30 + 30, 1554 .htotal = 1024 + 30 + 30 + 30, 1555 .vdisplay = 600, 1556 .vsync_start = 600 + 10, 1557 .vsync_end = 600 + 10 + 10, 1558 .vtotal = 600 + 10 + 10 + 10, 1559 }; 1560 1561 static const struct panel_desc boe_hv070wsa = { 1562 .modes = &boe_hv070wsa_mode, 1563 .num_modes = 1, 1564 .bpc = 8, 1565 .size = { 1566 .width = 154, 1567 .height = 90, 1568 }, 1569 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1570 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1571 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1572 }; 1573 1574 static const struct display_timing cct_cmt430b19n00_timing = { 1575 .pixelclock = { 8000000, 9000000, 12000000 }, 1576 .hactive = { 480, 480, 480 }, 1577 .hfront_porch = { 2, 8, 75 }, 1578 .hback_porch = { 3, 43, 43 }, 1579 .hsync_len = { 2, 4, 75 }, 1580 .vactive = { 272, 272, 272 }, 1581 .vfront_porch = { 2, 8, 37 }, 1582 .vback_porch = { 2, 12, 12 }, 1583 .vsync_len = { 2, 4, 37 }, 1584 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1585 }; 1586 1587 static const struct panel_desc cct_cmt430b19n00 = { 1588 .timings = &cct_cmt430b19n00_timing, 1589 .num_timings = 1, 1590 .bpc = 8, 1591 .size = { 1592 .width = 95, 1593 .height = 53, 1594 }, 1595 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1596 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1597 .connector_type = DRM_MODE_CONNECTOR_DPI, 1598 }; 1599 1600 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1601 .clock = 9000, 1602 .hdisplay = 480, 1603 .hsync_start = 480 + 5, 1604 .hsync_end = 480 + 5 + 5, 1605 .htotal = 480 + 5 + 5 + 40, 1606 .vdisplay = 272, 1607 .vsync_start = 272 + 8, 1608 .vsync_end = 272 + 8 + 8, 1609 .vtotal = 272 + 8 + 8 + 8, 1610 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1611 }; 1612 1613 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1614 .modes = &cdtech_s043wq26h_ct7_mode, 1615 .num_modes = 1, 1616 .bpc = 8, 1617 .size = { 1618 .width = 95, 1619 .height = 54, 1620 }, 1621 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1622 }; 1623 1624 /* S070PWS19HP-FC21 2017/04/22 */ 1625 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1626 .clock = 51200, 1627 .hdisplay = 1024, 1628 .hsync_start = 1024 + 160, 1629 .hsync_end = 1024 + 160 + 20, 1630 .htotal = 1024 + 160 + 20 + 140, 1631 .vdisplay = 600, 1632 .vsync_start = 600 + 12, 1633 .vsync_end = 600 + 12 + 3, 1634 .vtotal = 600 + 12 + 3 + 20, 1635 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1636 }; 1637 1638 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1639 .modes = &cdtech_s070pws19hp_fc21_mode, 1640 .num_modes = 1, 1641 .bpc = 6, 1642 .size = { 1643 .width = 154, 1644 .height = 86, 1645 }, 1646 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1647 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1648 .connector_type = DRM_MODE_CONNECTOR_DPI, 1649 }; 1650 1651 /* S070SWV29HG-DC44 2017/09/21 */ 1652 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1653 .clock = 33300, 1654 .hdisplay = 800, 1655 .hsync_start = 800 + 210, 1656 .hsync_end = 800 + 210 + 2, 1657 .htotal = 800 + 210 + 2 + 44, 1658 .vdisplay = 480, 1659 .vsync_start = 480 + 22, 1660 .vsync_end = 480 + 22 + 2, 1661 .vtotal = 480 + 22 + 2 + 21, 1662 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1663 }; 1664 1665 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1666 .modes = &cdtech_s070swv29hg_dc44_mode, 1667 .num_modes = 1, 1668 .bpc = 6, 1669 .size = { 1670 .width = 154, 1671 .height = 86, 1672 }, 1673 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1674 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1675 .connector_type = DRM_MODE_CONNECTOR_DPI, 1676 }; 1677 1678 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1679 .clock = 35000, 1680 .hdisplay = 800, 1681 .hsync_start = 800 + 40, 1682 .hsync_end = 800 + 40 + 40, 1683 .htotal = 800 + 40 + 40 + 48, 1684 .vdisplay = 480, 1685 .vsync_start = 480 + 29, 1686 .vsync_end = 480 + 29 + 13, 1687 .vtotal = 480 + 29 + 13 + 3, 1688 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1689 }; 1690 1691 static const struct panel_desc cdtech_s070wv95_ct16 = { 1692 .modes = &cdtech_s070wv95_ct16_mode, 1693 .num_modes = 1, 1694 .bpc = 8, 1695 .size = { 1696 .width = 154, 1697 .height = 85, 1698 }, 1699 }; 1700 1701 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1702 .pixelclock = { 68900000, 71100000, 73400000 }, 1703 .hactive = { 1280, 1280, 1280 }, 1704 .hfront_porch = { 65, 80, 95 }, 1705 .hback_porch = { 64, 79, 94 }, 1706 .hsync_len = { 1, 1, 1 }, 1707 .vactive = { 800, 800, 800 }, 1708 .vfront_porch = { 7, 11, 14 }, 1709 .vback_porch = { 7, 11, 14 }, 1710 .vsync_len = { 1, 1, 1 }, 1711 .flags = DISPLAY_FLAGS_DE_HIGH, 1712 }; 1713 1714 static const struct panel_desc chefree_ch101olhlwh_002 = { 1715 .timings = &chefree_ch101olhlwh_002_timing, 1716 .num_timings = 1, 1717 .bpc = 8, 1718 .size = { 1719 .width = 217, 1720 .height = 135, 1721 }, 1722 .delay = { 1723 .enable = 200, 1724 .disable = 200, 1725 }, 1726 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1727 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1728 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1729 }; 1730 1731 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1732 .clock = 66770, 1733 .hdisplay = 800, 1734 .hsync_start = 800 + 49, 1735 .hsync_end = 800 + 49 + 33, 1736 .htotal = 800 + 49 + 33 + 17, 1737 .vdisplay = 1280, 1738 .vsync_start = 1280 + 1, 1739 .vsync_end = 1280 + 1 + 7, 1740 .vtotal = 1280 + 1 + 7 + 15, 1741 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1742 }; 1743 1744 static const struct panel_desc chunghwa_claa070wp03xg = { 1745 .modes = &chunghwa_claa070wp03xg_mode, 1746 .num_modes = 1, 1747 .bpc = 6, 1748 .size = { 1749 .width = 94, 1750 .height = 150, 1751 }, 1752 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1753 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1754 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1755 }; 1756 1757 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1758 .clock = 72070, 1759 .hdisplay = 1366, 1760 .hsync_start = 1366 + 58, 1761 .hsync_end = 1366 + 58 + 58, 1762 .htotal = 1366 + 58 + 58 + 58, 1763 .vdisplay = 768, 1764 .vsync_start = 768 + 4, 1765 .vsync_end = 768 + 4 + 4, 1766 .vtotal = 768 + 4 + 4 + 4, 1767 }; 1768 1769 static const struct panel_desc chunghwa_claa101wa01a = { 1770 .modes = &chunghwa_claa101wa01a_mode, 1771 .num_modes = 1, 1772 .bpc = 6, 1773 .size = { 1774 .width = 220, 1775 .height = 120, 1776 }, 1777 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1778 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1779 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1780 }; 1781 1782 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1783 .clock = 69300, 1784 .hdisplay = 1366, 1785 .hsync_start = 1366 + 48, 1786 .hsync_end = 1366 + 48 + 32, 1787 .htotal = 1366 + 48 + 32 + 20, 1788 .vdisplay = 768, 1789 .vsync_start = 768 + 16, 1790 .vsync_end = 768 + 16 + 8, 1791 .vtotal = 768 + 16 + 8 + 16, 1792 }; 1793 1794 static const struct panel_desc chunghwa_claa101wb01 = { 1795 .modes = &chunghwa_claa101wb01_mode, 1796 .num_modes = 1, 1797 .bpc = 6, 1798 .size = { 1799 .width = 223, 1800 .height = 125, 1801 }, 1802 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1803 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1804 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1805 }; 1806 1807 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1808 .pixelclock = { 5000000, 9000000, 12000000 }, 1809 .hactive = { 480, 480, 480 }, 1810 .hfront_porch = { 12, 12, 12 }, 1811 .hback_porch = { 12, 12, 12 }, 1812 .hsync_len = { 21, 21, 21 }, 1813 .vactive = { 272, 272, 272 }, 1814 .vfront_porch = { 4, 4, 4 }, 1815 .vback_porch = { 4, 4, 4 }, 1816 .vsync_len = { 8, 8, 8 }, 1817 }; 1818 1819 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1820 .timings = &dataimage_fg040346dsswbg04_timing, 1821 .num_timings = 1, 1822 .bpc = 8, 1823 .size = { 1824 .width = 95, 1825 .height = 54, 1826 }, 1827 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1828 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1829 .connector_type = DRM_MODE_CONNECTOR_DPI, 1830 }; 1831 1832 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1833 .pixelclock = { 68900000, 71110000, 73400000 }, 1834 .hactive = { 1280, 1280, 1280 }, 1835 .vactive = { 800, 800, 800 }, 1836 .hback_porch = { 100, 100, 100 }, 1837 .hfront_porch = { 100, 100, 100 }, 1838 .vback_porch = { 5, 5, 5 }, 1839 .vfront_porch = { 5, 5, 5 }, 1840 .hsync_len = { 24, 24, 24 }, 1841 .vsync_len = { 3, 3, 3 }, 1842 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1843 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1844 }; 1845 1846 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1847 .timings = &dataimage_fg1001l0dsswmg01_timing, 1848 .num_timings = 1, 1849 .bpc = 8, 1850 .size = { 1851 .width = 217, 1852 .height = 136, 1853 }, 1854 }; 1855 1856 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1857 .clock = 33260, 1858 .hdisplay = 800, 1859 .hsync_start = 800 + 40, 1860 .hsync_end = 800 + 40 + 128, 1861 .htotal = 800 + 40 + 128 + 88, 1862 .vdisplay = 480, 1863 .vsync_start = 480 + 10, 1864 .vsync_end = 480 + 10 + 2, 1865 .vtotal = 480 + 10 + 2 + 33, 1866 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1867 }; 1868 1869 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1870 .modes = &dataimage_scf0700c48ggu18_mode, 1871 .num_modes = 1, 1872 .bpc = 8, 1873 .size = { 1874 .width = 152, 1875 .height = 91, 1876 }, 1877 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1878 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1879 }; 1880 1881 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1882 .pixelclock = { 45000000, 51200000, 57000000 }, 1883 .hactive = { 1024, 1024, 1024 }, 1884 .hfront_porch = { 100, 106, 113 }, 1885 .hback_porch = { 100, 106, 113 }, 1886 .hsync_len = { 100, 108, 114 }, 1887 .vactive = { 600, 600, 600 }, 1888 .vfront_porch = { 8, 11, 15 }, 1889 .vback_porch = { 8, 11, 15 }, 1890 .vsync_len = { 9, 13, 15 }, 1891 .flags = DISPLAY_FLAGS_DE_HIGH, 1892 }; 1893 1894 static const struct panel_desc dlc_dlc0700yzg_1 = { 1895 .timings = &dlc_dlc0700yzg_1_timing, 1896 .num_timings = 1, 1897 .bpc = 6, 1898 .size = { 1899 .width = 154, 1900 .height = 86, 1901 }, 1902 .delay = { 1903 .prepare = 30, 1904 .enable = 200, 1905 .disable = 200, 1906 }, 1907 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1908 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1909 }; 1910 1911 static const struct display_timing dlc_dlc1010gig_timing = { 1912 .pixelclock = { 68900000, 71100000, 73400000 }, 1913 .hactive = { 1280, 1280, 1280 }, 1914 .hfront_porch = { 43, 53, 63 }, 1915 .hback_porch = { 43, 53, 63 }, 1916 .hsync_len = { 44, 54, 64 }, 1917 .vactive = { 800, 800, 800 }, 1918 .vfront_porch = { 5, 8, 11 }, 1919 .vback_porch = { 5, 8, 11 }, 1920 .vsync_len = { 5, 7, 11 }, 1921 .flags = DISPLAY_FLAGS_DE_HIGH, 1922 }; 1923 1924 static const struct panel_desc dlc_dlc1010gig = { 1925 .timings = &dlc_dlc1010gig_timing, 1926 .num_timings = 1, 1927 .bpc = 8, 1928 .size = { 1929 .width = 216, 1930 .height = 135, 1931 }, 1932 .delay = { 1933 .prepare = 60, 1934 .enable = 150, 1935 .disable = 100, 1936 .unprepare = 60, 1937 }, 1938 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1939 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1940 }; 1941 1942 static const struct drm_display_mode edt_et035012dm6_mode = { 1943 .clock = 6500, 1944 .hdisplay = 320, 1945 .hsync_start = 320 + 20, 1946 .hsync_end = 320 + 20 + 30, 1947 .htotal = 320 + 20 + 68, 1948 .vdisplay = 240, 1949 .vsync_start = 240 + 4, 1950 .vsync_end = 240 + 4 + 4, 1951 .vtotal = 240 + 4 + 4 + 14, 1952 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1953 }; 1954 1955 static const struct panel_desc edt_et035012dm6 = { 1956 .modes = &edt_et035012dm6_mode, 1957 .num_modes = 1, 1958 .bpc = 8, 1959 .size = { 1960 .width = 70, 1961 .height = 52, 1962 }, 1963 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1964 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1965 }; 1966 1967 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1968 .clock = 6520, 1969 .hdisplay = 320, 1970 .hsync_start = 320 + 20, 1971 .hsync_end = 320 + 20 + 68, 1972 .htotal = 320 + 20 + 68, 1973 .vdisplay = 240, 1974 .vsync_start = 240 + 4, 1975 .vsync_end = 240 + 4 + 18, 1976 .vtotal = 240 + 4 + 18, 1977 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1978 }; 1979 1980 static const struct panel_desc edt_etm0350g0dh6 = { 1981 .modes = &edt_etm0350g0dh6_mode, 1982 .num_modes = 1, 1983 .bpc = 6, 1984 .size = { 1985 .width = 70, 1986 .height = 53, 1987 }, 1988 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1989 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1990 .connector_type = DRM_MODE_CONNECTOR_DPI, 1991 }; 1992 1993 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1994 .clock = 10870, 1995 .hdisplay = 480, 1996 .hsync_start = 480 + 8, 1997 .hsync_end = 480 + 8 + 4, 1998 .htotal = 480 + 8 + 4 + 41, 1999 2000 /* 2001 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 2002 * fb_align 2003 */ 2004 2005 .vdisplay = 288, 2006 .vsync_start = 288 + 2, 2007 .vsync_end = 288 + 2 + 4, 2008 .vtotal = 288 + 2 + 4 + 10, 2009 }; 2010 2011 static const struct panel_desc edt_etm043080dh6gp = { 2012 .modes = &edt_etm043080dh6gp_mode, 2013 .num_modes = 1, 2014 .bpc = 8, 2015 .size = { 2016 .width = 100, 2017 .height = 65, 2018 }, 2019 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2020 .connector_type = DRM_MODE_CONNECTOR_DPI, 2021 }; 2022 2023 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 2024 .clock = 9000, 2025 .hdisplay = 480, 2026 .hsync_start = 480 + 2, 2027 .hsync_end = 480 + 2 + 41, 2028 .htotal = 480 + 2 + 41 + 2, 2029 .vdisplay = 272, 2030 .vsync_start = 272 + 2, 2031 .vsync_end = 272 + 2 + 10, 2032 .vtotal = 272 + 2 + 10 + 2, 2033 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2034 }; 2035 2036 static const struct panel_desc edt_etm0430g0dh6 = { 2037 .modes = &edt_etm0430g0dh6_mode, 2038 .num_modes = 1, 2039 .bpc = 6, 2040 .size = { 2041 .width = 95, 2042 .height = 54, 2043 }, 2044 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2045 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2046 .connector_type = DRM_MODE_CONNECTOR_DPI, 2047 }; 2048 2049 static const struct drm_display_mode edt_et057090dhu_mode = { 2050 .clock = 25175, 2051 .hdisplay = 640, 2052 .hsync_start = 640 + 16, 2053 .hsync_end = 640 + 16 + 30, 2054 .htotal = 640 + 16 + 30 + 114, 2055 .vdisplay = 480, 2056 .vsync_start = 480 + 10, 2057 .vsync_end = 480 + 10 + 3, 2058 .vtotal = 480 + 10 + 3 + 32, 2059 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2060 }; 2061 2062 static const struct panel_desc edt_et057090dhu = { 2063 .modes = &edt_et057090dhu_mode, 2064 .num_modes = 1, 2065 .bpc = 6, 2066 .size = { 2067 .width = 115, 2068 .height = 86, 2069 }, 2070 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2071 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2072 .connector_type = DRM_MODE_CONNECTOR_DPI, 2073 }; 2074 2075 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2076 .clock = 33260, 2077 .hdisplay = 800, 2078 .hsync_start = 800 + 40, 2079 .hsync_end = 800 + 40 + 128, 2080 .htotal = 800 + 40 + 128 + 88, 2081 .vdisplay = 480, 2082 .vsync_start = 480 + 10, 2083 .vsync_end = 480 + 10 + 2, 2084 .vtotal = 480 + 10 + 2 + 33, 2085 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2086 }; 2087 2088 static const struct panel_desc edt_etm0700g0dh6 = { 2089 .modes = &edt_etm0700g0dh6_mode, 2090 .num_modes = 1, 2091 .bpc = 6, 2092 .size = { 2093 .width = 152, 2094 .height = 91, 2095 }, 2096 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2097 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2098 .connector_type = DRM_MODE_CONNECTOR_DPI, 2099 }; 2100 2101 static const struct panel_desc edt_etm0700g0bdh6 = { 2102 .modes = &edt_etm0700g0dh6_mode, 2103 .num_modes = 1, 2104 .bpc = 6, 2105 .size = { 2106 .width = 152, 2107 .height = 91, 2108 }, 2109 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2110 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2111 .connector_type = DRM_MODE_CONNECTOR_DPI, 2112 }; 2113 2114 static const struct display_timing edt_etml0700y5dha_timing = { 2115 .pixelclock = { 40800000, 51200000, 67200000 }, 2116 .hactive = { 1024, 1024, 1024 }, 2117 .hfront_porch = { 30, 106, 125 }, 2118 .hback_porch = { 30, 106, 125 }, 2119 .hsync_len = { 30, 108, 126 }, 2120 .vactive = { 600, 600, 600 }, 2121 .vfront_porch = { 3, 12, 67}, 2122 .vback_porch = { 3, 12, 67 }, 2123 .vsync_len = { 4, 11, 66 }, 2124 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2125 DISPLAY_FLAGS_DE_HIGH, 2126 }; 2127 2128 static const struct panel_desc edt_etml0700y5dha = { 2129 .timings = &edt_etml0700y5dha_timing, 2130 .num_timings = 1, 2131 .bpc = 8, 2132 .size = { 2133 .width = 155, 2134 .height = 86, 2135 }, 2136 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2137 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2138 }; 2139 2140 static const struct display_timing edt_etml1010g3dra_timing = { 2141 .pixelclock = { 66300000, 72400000, 78900000 }, 2142 .hactive = { 1280, 1280, 1280 }, 2143 .hfront_porch = { 12, 72, 132 }, 2144 .hback_porch = { 86, 86, 86 }, 2145 .hsync_len = { 2, 2, 2 }, 2146 .vactive = { 800, 800, 800 }, 2147 .vfront_porch = { 1, 15, 49 }, 2148 .vback_porch = { 21, 21, 21 }, 2149 .vsync_len = { 2, 2, 2 }, 2150 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2151 DISPLAY_FLAGS_DE_HIGH, 2152 }; 2153 2154 static const struct panel_desc edt_etml1010g3dra = { 2155 .timings = &edt_etml1010g3dra_timing, 2156 .num_timings = 1, 2157 .bpc = 8, 2158 .size = { 2159 .width = 216, 2160 .height = 135, 2161 }, 2162 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2163 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2164 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2165 }; 2166 2167 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2168 .clock = 25175, 2169 .hdisplay = 640, 2170 .hsync_start = 640, 2171 .hsync_end = 640 + 16, 2172 .htotal = 640 + 16 + 30 + 114, 2173 .vdisplay = 480, 2174 .vsync_start = 480 + 10, 2175 .vsync_end = 480 + 10 + 3, 2176 .vtotal = 480 + 10 + 3 + 35, 2177 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2178 }; 2179 2180 static const struct panel_desc edt_etmv570g2dhu = { 2181 .modes = &edt_etmv570g2dhu_mode, 2182 .num_modes = 1, 2183 .bpc = 6, 2184 .size = { 2185 .width = 115, 2186 .height = 86, 2187 }, 2188 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2189 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2190 .connector_type = DRM_MODE_CONNECTOR_DPI, 2191 }; 2192 2193 static const struct display_timing eink_vb3300_kca_timing = { 2194 .pixelclock = { 40000000, 40000000, 40000000 }, 2195 .hactive = { 334, 334, 334 }, 2196 .hfront_porch = { 1, 1, 1 }, 2197 .hback_porch = { 1, 1, 1 }, 2198 .hsync_len = { 1, 1, 1 }, 2199 .vactive = { 1405, 1405, 1405 }, 2200 .vfront_porch = { 1, 1, 1 }, 2201 .vback_porch = { 1, 1, 1 }, 2202 .vsync_len = { 1, 1, 1 }, 2203 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2204 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2205 }; 2206 2207 static const struct panel_desc eink_vb3300_kca = { 2208 .timings = &eink_vb3300_kca_timing, 2209 .num_timings = 1, 2210 .bpc = 6, 2211 .size = { 2212 .width = 157, 2213 .height = 209, 2214 }, 2215 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2216 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2217 .connector_type = DRM_MODE_CONNECTOR_DPI, 2218 }; 2219 2220 static const struct display_timing evervision_vgg644804_timing = { 2221 .pixelclock = { 25175000, 25175000, 25175000 }, 2222 .hactive = { 640, 640, 640 }, 2223 .hfront_porch = { 16, 16, 16 }, 2224 .hback_porch = { 82, 114, 170 }, 2225 .hsync_len = { 5, 30, 30 }, 2226 .vactive = { 480, 480, 480 }, 2227 .vfront_porch = { 10, 10, 10 }, 2228 .vback_porch = { 30, 32, 34 }, 2229 .vsync_len = { 1, 3, 5 }, 2230 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2231 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2232 DISPLAY_FLAGS_SYNC_POSEDGE, 2233 }; 2234 2235 static const struct panel_desc evervision_vgg644804 = { 2236 .timings = &evervision_vgg644804_timing, 2237 .num_timings = 1, 2238 .bpc = 6, 2239 .size = { 2240 .width = 115, 2241 .height = 86, 2242 }, 2243 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2244 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2245 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2246 }; 2247 2248 static const struct display_timing evervision_vgg804821_timing = { 2249 .pixelclock = { 27600000, 33300000, 50000000 }, 2250 .hactive = { 800, 800, 800 }, 2251 .hfront_porch = { 40, 66, 70 }, 2252 .hback_porch = { 40, 67, 70 }, 2253 .hsync_len = { 40, 67, 70 }, 2254 .vactive = { 480, 480, 480 }, 2255 .vfront_porch = { 6, 10, 10 }, 2256 .vback_porch = { 7, 11, 11 }, 2257 .vsync_len = { 7, 11, 11 }, 2258 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2259 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2260 DISPLAY_FLAGS_SYNC_NEGEDGE, 2261 }; 2262 2263 static const struct panel_desc evervision_vgg804821 = { 2264 .timings = &evervision_vgg804821_timing, 2265 .num_timings = 1, 2266 .bpc = 8, 2267 .size = { 2268 .width = 108, 2269 .height = 64, 2270 }, 2271 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2272 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2273 }; 2274 2275 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2276 .clock = 32260, 2277 .hdisplay = 800, 2278 .hsync_start = 800 + 168, 2279 .hsync_end = 800 + 168 + 64, 2280 .htotal = 800 + 168 + 64 + 88, 2281 .vdisplay = 480, 2282 .vsync_start = 480 + 37, 2283 .vsync_end = 480 + 37 + 2, 2284 .vtotal = 480 + 37 + 2 + 8, 2285 }; 2286 2287 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2288 .modes = &foxlink_fl500wvr00_a0t_mode, 2289 .num_modes = 1, 2290 .bpc = 8, 2291 .size = { 2292 .width = 108, 2293 .height = 65, 2294 }, 2295 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2296 }; 2297 2298 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2299 { /* 60 Hz */ 2300 .clock = 6000, 2301 .hdisplay = 320, 2302 .hsync_start = 320 + 44, 2303 .hsync_end = 320 + 44 + 16, 2304 .htotal = 320 + 44 + 16 + 20, 2305 .vdisplay = 240, 2306 .vsync_start = 240 + 2, 2307 .vsync_end = 240 + 2 + 6, 2308 .vtotal = 240 + 2 + 6 + 2, 2309 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2310 }, 2311 { /* 50 Hz */ 2312 .clock = 5400, 2313 .hdisplay = 320, 2314 .hsync_start = 320 + 56, 2315 .hsync_end = 320 + 56 + 16, 2316 .htotal = 320 + 56 + 16 + 40, 2317 .vdisplay = 240, 2318 .vsync_start = 240 + 2, 2319 .vsync_end = 240 + 2 + 6, 2320 .vtotal = 240 + 2 + 6 + 2, 2321 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2322 }, 2323 }; 2324 2325 static const struct panel_desc frida_frd350h54004 = { 2326 .modes = frida_frd350h54004_modes, 2327 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2328 .bpc = 8, 2329 .size = { 2330 .width = 77, 2331 .height = 64, 2332 }, 2333 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2334 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2335 .connector_type = DRM_MODE_CONNECTOR_DPI, 2336 }; 2337 2338 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2339 .clock = 67185, 2340 .hdisplay = 800, 2341 .hsync_start = 800 + 20, 2342 .hsync_end = 800 + 20 + 24, 2343 .htotal = 800 + 20 + 24 + 20, 2344 .vdisplay = 1280, 2345 .vsync_start = 1280 + 4, 2346 .vsync_end = 1280 + 4 + 8, 2347 .vtotal = 1280 + 4 + 8 + 4, 2348 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2349 }; 2350 2351 static const struct panel_desc friendlyarm_hd702e = { 2352 .modes = &friendlyarm_hd702e_mode, 2353 .num_modes = 1, 2354 .size = { 2355 .width = 94, 2356 .height = 151, 2357 }, 2358 }; 2359 2360 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2361 .clock = 9000, 2362 .hdisplay = 480, 2363 .hsync_start = 480 + 5, 2364 .hsync_end = 480 + 5 + 1, 2365 .htotal = 480 + 5 + 1 + 40, 2366 .vdisplay = 272, 2367 .vsync_start = 272 + 8, 2368 .vsync_end = 272 + 8 + 1, 2369 .vtotal = 272 + 8 + 1 + 8, 2370 }; 2371 2372 static const struct panel_desc giantplus_gpg482739qs5 = { 2373 .modes = &giantplus_gpg482739qs5_mode, 2374 .num_modes = 1, 2375 .bpc = 8, 2376 .size = { 2377 .width = 95, 2378 .height = 54, 2379 }, 2380 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2381 }; 2382 2383 static const struct display_timing giantplus_gpm940b0_timing = { 2384 .pixelclock = { 13500000, 27000000, 27500000 }, 2385 .hactive = { 320, 320, 320 }, 2386 .hfront_porch = { 14, 686, 718 }, 2387 .hback_porch = { 50, 70, 255 }, 2388 .hsync_len = { 1, 1, 1 }, 2389 .vactive = { 240, 240, 240 }, 2390 .vfront_porch = { 1, 1, 179 }, 2391 .vback_porch = { 1, 21, 31 }, 2392 .vsync_len = { 1, 1, 6 }, 2393 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2394 }; 2395 2396 static const struct panel_desc giantplus_gpm940b0 = { 2397 .timings = &giantplus_gpm940b0_timing, 2398 .num_timings = 1, 2399 .bpc = 8, 2400 .size = { 2401 .width = 60, 2402 .height = 45, 2403 }, 2404 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2405 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2406 }; 2407 2408 static const struct display_timing hannstar_hsd070pww1_timing = { 2409 .pixelclock = { 64300000, 71100000, 82000000 }, 2410 .hactive = { 1280, 1280, 1280 }, 2411 .hfront_porch = { 1, 1, 10 }, 2412 .hback_porch = { 1, 1, 10 }, 2413 /* 2414 * According to the data sheet, the minimum horizontal blanking interval 2415 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2416 * minimum working horizontal blanking interval to be 60 clocks. 2417 */ 2418 .hsync_len = { 58, 158, 661 }, 2419 .vactive = { 800, 800, 800 }, 2420 .vfront_porch = { 1, 1, 10 }, 2421 .vback_porch = { 1, 1, 10 }, 2422 .vsync_len = { 1, 21, 203 }, 2423 .flags = DISPLAY_FLAGS_DE_HIGH, 2424 }; 2425 2426 static const struct panel_desc hannstar_hsd070pww1 = { 2427 .timings = &hannstar_hsd070pww1_timing, 2428 .num_timings = 1, 2429 .bpc = 6, 2430 .size = { 2431 .width = 151, 2432 .height = 94, 2433 }, 2434 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2435 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2436 }; 2437 2438 static const struct display_timing hannstar_hsd100pxn1_timing = { 2439 .pixelclock = { 55000000, 65000000, 75000000 }, 2440 .hactive = { 1024, 1024, 1024 }, 2441 .hfront_porch = { 40, 40, 40 }, 2442 .hback_porch = { 220, 220, 220 }, 2443 .hsync_len = { 20, 60, 100 }, 2444 .vactive = { 768, 768, 768 }, 2445 .vfront_porch = { 7, 7, 7 }, 2446 .vback_porch = { 21, 21, 21 }, 2447 .vsync_len = { 10, 10, 10 }, 2448 .flags = DISPLAY_FLAGS_DE_HIGH, 2449 }; 2450 2451 static const struct panel_desc hannstar_hsd100pxn1 = { 2452 .timings = &hannstar_hsd100pxn1_timing, 2453 .num_timings = 1, 2454 .bpc = 6, 2455 .size = { 2456 .width = 203, 2457 .height = 152, 2458 }, 2459 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2460 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2461 }; 2462 2463 static const struct display_timing hannstar_hsd101pww2_timing = { 2464 .pixelclock = { 64300000, 71100000, 82000000 }, 2465 .hactive = { 1280, 1280, 1280 }, 2466 .hfront_porch = { 1, 1, 10 }, 2467 .hback_porch = { 1, 1, 10 }, 2468 .hsync_len = { 58, 158, 661 }, 2469 .vactive = { 800, 800, 800 }, 2470 .vfront_porch = { 1, 1, 10 }, 2471 .vback_porch = { 1, 1, 10 }, 2472 .vsync_len = { 1, 21, 203 }, 2473 .flags = DISPLAY_FLAGS_DE_HIGH, 2474 }; 2475 2476 static const struct panel_desc hannstar_hsd101pww2 = { 2477 .timings = &hannstar_hsd101pww2_timing, 2478 .num_timings = 1, 2479 .bpc = 8, 2480 .size = { 2481 .width = 217, 2482 .height = 136, 2483 }, 2484 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2485 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2486 }; 2487 2488 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2489 .clock = 33333, 2490 .hdisplay = 800, 2491 .hsync_start = 800 + 85, 2492 .hsync_end = 800 + 85 + 86, 2493 .htotal = 800 + 85 + 86 + 85, 2494 .vdisplay = 480, 2495 .vsync_start = 480 + 16, 2496 .vsync_end = 480 + 16 + 13, 2497 .vtotal = 480 + 16 + 13 + 16, 2498 }; 2499 2500 static const struct panel_desc hitachi_tx23d38vm0caa = { 2501 .modes = &hitachi_tx23d38vm0caa_mode, 2502 .num_modes = 1, 2503 .bpc = 6, 2504 .size = { 2505 .width = 195, 2506 .height = 117, 2507 }, 2508 .delay = { 2509 .enable = 160, 2510 .disable = 160, 2511 }, 2512 }; 2513 2514 static const struct drm_display_mode innolux_at043tn24_mode = { 2515 .clock = 9000, 2516 .hdisplay = 480, 2517 .hsync_start = 480 + 2, 2518 .hsync_end = 480 + 2 + 41, 2519 .htotal = 480 + 2 + 41 + 2, 2520 .vdisplay = 272, 2521 .vsync_start = 272 + 2, 2522 .vsync_end = 272 + 2 + 10, 2523 .vtotal = 272 + 2 + 10 + 2, 2524 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2525 }; 2526 2527 static const struct panel_desc innolux_at043tn24 = { 2528 .modes = &innolux_at043tn24_mode, 2529 .num_modes = 1, 2530 .bpc = 8, 2531 .size = { 2532 .width = 95, 2533 .height = 54, 2534 }, 2535 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2536 .connector_type = DRM_MODE_CONNECTOR_DPI, 2537 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2538 }; 2539 2540 static const struct drm_display_mode innolux_at070tn92_mode = { 2541 .clock = 33333, 2542 .hdisplay = 800, 2543 .hsync_start = 800 + 210, 2544 .hsync_end = 800 + 210 + 20, 2545 .htotal = 800 + 210 + 20 + 46, 2546 .vdisplay = 480, 2547 .vsync_start = 480 + 22, 2548 .vsync_end = 480 + 22 + 10, 2549 .vtotal = 480 + 22 + 23 + 10, 2550 }; 2551 2552 static const struct panel_desc innolux_at070tn92 = { 2553 .modes = &innolux_at070tn92_mode, 2554 .num_modes = 1, 2555 .size = { 2556 .width = 154, 2557 .height = 86, 2558 }, 2559 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2560 }; 2561 2562 static const struct display_timing innolux_g070ace_l01_timing = { 2563 .pixelclock = { 25200000, 35000000, 35700000 }, 2564 .hactive = { 800, 800, 800 }, 2565 .hfront_porch = { 30, 32, 87 }, 2566 .hback_porch = { 30, 32, 87 }, 2567 .hsync_len = { 1, 1, 1 }, 2568 .vactive = { 480, 480, 480 }, 2569 .vfront_porch = { 3, 3, 3 }, 2570 .vback_porch = { 13, 13, 13 }, 2571 .vsync_len = { 1, 1, 4 }, 2572 .flags = DISPLAY_FLAGS_DE_HIGH, 2573 }; 2574 2575 static const struct panel_desc innolux_g070ace_l01 = { 2576 .timings = &innolux_g070ace_l01_timing, 2577 .num_timings = 1, 2578 .bpc = 8, 2579 .size = { 2580 .width = 152, 2581 .height = 91, 2582 }, 2583 .delay = { 2584 .prepare = 10, 2585 .enable = 50, 2586 .disable = 50, 2587 .unprepare = 500, 2588 }, 2589 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2590 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2591 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2592 }; 2593 2594 static const struct display_timing innolux_g070y2_l01_timing = { 2595 .pixelclock = { 28000000, 29500000, 32000000 }, 2596 .hactive = { 800, 800, 800 }, 2597 .hfront_porch = { 61, 91, 141 }, 2598 .hback_porch = { 60, 90, 140 }, 2599 .hsync_len = { 12, 12, 12 }, 2600 .vactive = { 480, 480, 480 }, 2601 .vfront_porch = { 4, 9, 30 }, 2602 .vback_porch = { 4, 8, 28 }, 2603 .vsync_len = { 2, 2, 2 }, 2604 .flags = DISPLAY_FLAGS_DE_HIGH, 2605 }; 2606 2607 static const struct panel_desc innolux_g070y2_l01 = { 2608 .timings = &innolux_g070y2_l01_timing, 2609 .num_timings = 1, 2610 .bpc = 8, 2611 .size = { 2612 .width = 152, 2613 .height = 91, 2614 }, 2615 .delay = { 2616 .prepare = 10, 2617 .enable = 100, 2618 .disable = 100, 2619 .unprepare = 800, 2620 }, 2621 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2622 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2623 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2624 }; 2625 2626 static const struct display_timing innolux_g070ace_lh3_timing = { 2627 .pixelclock = { 25200000, 25400000, 35700000 }, 2628 .hactive = { 800, 800, 800 }, 2629 .hfront_porch = { 30, 32, 87 }, 2630 .hback_porch = { 29, 31, 86 }, 2631 .hsync_len = { 1, 1, 1 }, 2632 .vactive = { 480, 480, 480 }, 2633 .vfront_porch = { 4, 5, 65 }, 2634 .vback_porch = { 3, 4, 65 }, 2635 .vsync_len = { 1, 1, 1 }, 2636 .flags = DISPLAY_FLAGS_DE_HIGH, 2637 }; 2638 2639 static const struct panel_desc innolux_g070ace_lh3 = { 2640 .timings = &innolux_g070ace_lh3_timing, 2641 .num_timings = 1, 2642 .bpc = 8, 2643 .size = { 2644 .width = 152, 2645 .height = 91, 2646 }, 2647 .delay = { 2648 .prepare = 10, 2649 .enable = 450, 2650 .disable = 200, 2651 .unprepare = 510, 2652 }, 2653 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2654 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2655 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2656 }; 2657 2658 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2659 .clock = 33333, 2660 .hdisplay = 800, 2661 .hsync_start = 800 + 210, 2662 .hsync_end = 800 + 210 + 20, 2663 .htotal = 800 + 210 + 20 + 46, 2664 .vdisplay = 480, 2665 .vsync_start = 480 + 22, 2666 .vsync_end = 480 + 22 + 10, 2667 .vtotal = 480 + 22 + 23 + 10, 2668 }; 2669 2670 static const struct panel_desc innolux_g070y2_t02 = { 2671 .modes = &innolux_g070y2_t02_mode, 2672 .num_modes = 1, 2673 .bpc = 8, 2674 .size = { 2675 .width = 152, 2676 .height = 92, 2677 }, 2678 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2679 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2680 .connector_type = DRM_MODE_CONNECTOR_DPI, 2681 }; 2682 2683 static const struct display_timing innolux_g101ice_l01_timing = { 2684 .pixelclock = { 60400000, 71100000, 74700000 }, 2685 .hactive = { 1280, 1280, 1280 }, 2686 .hfront_porch = { 30, 60, 70 }, 2687 .hback_porch = { 30, 60, 70 }, 2688 .hsync_len = { 22, 40, 60 }, 2689 .vactive = { 800, 800, 800 }, 2690 .vfront_porch = { 3, 8, 14 }, 2691 .vback_porch = { 3, 8, 14 }, 2692 .vsync_len = { 4, 7, 12 }, 2693 .flags = DISPLAY_FLAGS_DE_HIGH, 2694 }; 2695 2696 static const struct panel_desc innolux_g101ice_l01 = { 2697 .timings = &innolux_g101ice_l01_timing, 2698 .num_timings = 1, 2699 .bpc = 8, 2700 .size = { 2701 .width = 217, 2702 .height = 135, 2703 }, 2704 .delay = { 2705 .enable = 200, 2706 .disable = 200, 2707 }, 2708 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2709 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2710 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2711 }; 2712 2713 static const struct display_timing innolux_g121i1_l01_timing = { 2714 .pixelclock = { 67450000, 71000000, 74550000 }, 2715 .hactive = { 1280, 1280, 1280 }, 2716 .hfront_porch = { 40, 80, 160 }, 2717 .hback_porch = { 39, 79, 159 }, 2718 .hsync_len = { 1, 1, 1 }, 2719 .vactive = { 800, 800, 800 }, 2720 .vfront_porch = { 5, 11, 100 }, 2721 .vback_porch = { 4, 11, 99 }, 2722 .vsync_len = { 1, 1, 1 }, 2723 }; 2724 2725 static const struct panel_desc innolux_g121i1_l01 = { 2726 .timings = &innolux_g121i1_l01_timing, 2727 .num_timings = 1, 2728 .bpc = 6, 2729 .size = { 2730 .width = 261, 2731 .height = 163, 2732 }, 2733 .delay = { 2734 .enable = 200, 2735 .disable = 20, 2736 }, 2737 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2738 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2739 }; 2740 2741 static const struct display_timing innolux_g121x1_l03_timings = { 2742 .pixelclock = { 57500000, 64900000, 74400000 }, 2743 .hactive = { 1024, 1024, 1024 }, 2744 .hfront_porch = { 90, 140, 190 }, 2745 .hback_porch = { 90, 140, 190 }, 2746 .hsync_len = { 36, 40, 60 }, 2747 .vactive = { 768, 768, 768 }, 2748 .vfront_porch = { 2, 15, 30 }, 2749 .vback_porch = { 2, 15, 30 }, 2750 .vsync_len = { 2, 8, 20 }, 2751 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2752 }; 2753 2754 static const struct panel_desc innolux_g121x1_l03 = { 2755 .timings = &innolux_g121x1_l03_timings, 2756 .num_timings = 1, 2757 .bpc = 6, 2758 .size = { 2759 .width = 246, 2760 .height = 185, 2761 }, 2762 .delay = { 2763 .enable = 200, 2764 .unprepare = 200, 2765 .disable = 400, 2766 }, 2767 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2768 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2769 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2770 }; 2771 2772 static const struct panel_desc innolux_g121xce_l01 = { 2773 .timings = &innolux_g121x1_l03_timings, 2774 .num_timings = 1, 2775 .bpc = 8, 2776 .size = { 2777 .width = 246, 2778 .height = 185, 2779 }, 2780 .delay = { 2781 .enable = 200, 2782 .unprepare = 200, 2783 .disable = 400, 2784 }, 2785 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2786 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2787 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2788 }; 2789 2790 static const struct display_timing innolux_g156hce_l01_timings = { 2791 .pixelclock = { 120000000, 141860000, 150000000 }, 2792 .hactive = { 1920, 1920, 1920 }, 2793 .hfront_porch = { 80, 90, 100 }, 2794 .hback_porch = { 80, 90, 100 }, 2795 .hsync_len = { 20, 30, 30 }, 2796 .vactive = { 1080, 1080, 1080 }, 2797 .vfront_porch = { 3, 10, 20 }, 2798 .vback_porch = { 3, 10, 20 }, 2799 .vsync_len = { 4, 10, 10 }, 2800 }; 2801 2802 static const struct panel_desc innolux_g156hce_l01 = { 2803 .timings = &innolux_g156hce_l01_timings, 2804 .num_timings = 1, 2805 .bpc = 8, 2806 .size = { 2807 .width = 344, 2808 .height = 194, 2809 }, 2810 .delay = { 2811 .prepare = 1, /* T1+T2 */ 2812 .enable = 450, /* T5 */ 2813 .disable = 200, /* T6 */ 2814 .unprepare = 10, /* T3+T7 */ 2815 }, 2816 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2817 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2818 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2819 }; 2820 2821 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2822 .clock = 69300, 2823 .hdisplay = 1366, 2824 .hsync_start = 1366 + 16, 2825 .hsync_end = 1366 + 16 + 34, 2826 .htotal = 1366 + 16 + 34 + 50, 2827 .vdisplay = 768, 2828 .vsync_start = 768 + 2, 2829 .vsync_end = 768 + 2 + 6, 2830 .vtotal = 768 + 2 + 6 + 12, 2831 }; 2832 2833 static const struct panel_desc innolux_n156bge_l21 = { 2834 .modes = &innolux_n156bge_l21_mode, 2835 .num_modes = 1, 2836 .bpc = 6, 2837 .size = { 2838 .width = 344, 2839 .height = 193, 2840 }, 2841 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2842 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2843 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2844 }; 2845 2846 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2847 .clock = 51501, 2848 .hdisplay = 1024, 2849 .hsync_start = 1024 + 128, 2850 .hsync_end = 1024 + 128 + 64, 2851 .htotal = 1024 + 128 + 64 + 128, 2852 .vdisplay = 600, 2853 .vsync_start = 600 + 16, 2854 .vsync_end = 600 + 16 + 4, 2855 .vtotal = 600 + 16 + 4 + 16, 2856 }; 2857 2858 static const struct panel_desc innolux_zj070na_01p = { 2859 .modes = &innolux_zj070na_01p_mode, 2860 .num_modes = 1, 2861 .bpc = 6, 2862 .size = { 2863 .width = 154, 2864 .height = 90, 2865 }, 2866 }; 2867 2868 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2869 .pixelclock = { 5580000, 5850000, 6200000 }, 2870 .hactive = { 320, 320, 320 }, 2871 .hfront_porch = { 30, 30, 30 }, 2872 .hback_porch = { 30, 30, 30 }, 2873 .hsync_len = { 1, 5, 17 }, 2874 .vactive = { 240, 240, 240 }, 2875 .vfront_porch = { 6, 6, 6 }, 2876 .vback_porch = { 5, 5, 5 }, 2877 .vsync_len = { 1, 2, 11 }, 2878 .flags = DISPLAY_FLAGS_DE_HIGH, 2879 }; 2880 2881 static const struct panel_desc koe_tx14d24vm1bpa = { 2882 .timings = &koe_tx14d24vm1bpa_timing, 2883 .num_timings = 1, 2884 .bpc = 6, 2885 .size = { 2886 .width = 115, 2887 .height = 86, 2888 }, 2889 }; 2890 2891 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2892 .pixelclock = { 151820000, 156720000, 159780000 }, 2893 .hactive = { 1920, 1920, 1920 }, 2894 .hfront_porch = { 105, 130, 142 }, 2895 .hback_porch = { 45, 70, 82 }, 2896 .hsync_len = { 30, 30, 30 }, 2897 .vactive = { 1200, 1200, 1200}, 2898 .vfront_porch = { 3, 5, 10 }, 2899 .vback_porch = { 2, 5, 10 }, 2900 .vsync_len = { 5, 5, 5 }, 2901 .flags = DISPLAY_FLAGS_DE_HIGH, 2902 }; 2903 2904 static const struct panel_desc koe_tx26d202vm0bwa = { 2905 .timings = &koe_tx26d202vm0bwa_timing, 2906 .num_timings = 1, 2907 .bpc = 8, 2908 .size = { 2909 .width = 217, 2910 .height = 136, 2911 }, 2912 .delay = { 2913 .prepare = 1000, 2914 .enable = 1000, 2915 .unprepare = 1000, 2916 .disable = 1000, 2917 }, 2918 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2919 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2920 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2921 }; 2922 2923 static const struct display_timing koe_tx31d200vm0baa_timing = { 2924 .pixelclock = { 39600000, 43200000, 48000000 }, 2925 .hactive = { 1280, 1280, 1280 }, 2926 .hfront_porch = { 16, 36, 56 }, 2927 .hback_porch = { 16, 36, 56 }, 2928 .hsync_len = { 8, 8, 8 }, 2929 .vactive = { 480, 480, 480 }, 2930 .vfront_porch = { 6, 21, 33 }, 2931 .vback_porch = { 6, 21, 33 }, 2932 .vsync_len = { 8, 8, 8 }, 2933 .flags = DISPLAY_FLAGS_DE_HIGH, 2934 }; 2935 2936 static const struct panel_desc koe_tx31d200vm0baa = { 2937 .timings = &koe_tx31d200vm0baa_timing, 2938 .num_timings = 1, 2939 .bpc = 6, 2940 .size = { 2941 .width = 292, 2942 .height = 109, 2943 }, 2944 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2945 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2946 }; 2947 2948 static const struct display_timing kyo_tcg121xglp_timing = { 2949 .pixelclock = { 52000000, 65000000, 71000000 }, 2950 .hactive = { 1024, 1024, 1024 }, 2951 .hfront_porch = { 2, 2, 2 }, 2952 .hback_porch = { 2, 2, 2 }, 2953 .hsync_len = { 86, 124, 244 }, 2954 .vactive = { 768, 768, 768 }, 2955 .vfront_porch = { 2, 2, 2 }, 2956 .vback_porch = { 2, 2, 2 }, 2957 .vsync_len = { 6, 34, 73 }, 2958 .flags = DISPLAY_FLAGS_DE_HIGH, 2959 }; 2960 2961 static const struct panel_desc kyo_tcg121xglp = { 2962 .timings = &kyo_tcg121xglp_timing, 2963 .num_timings = 1, 2964 .bpc = 8, 2965 .size = { 2966 .width = 246, 2967 .height = 184, 2968 }, 2969 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2970 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2971 }; 2972 2973 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2974 .clock = 7000, 2975 .hdisplay = 320, 2976 .hsync_start = 320 + 20, 2977 .hsync_end = 320 + 20 + 30, 2978 .htotal = 320 + 20 + 30 + 38, 2979 .vdisplay = 240, 2980 .vsync_start = 240 + 4, 2981 .vsync_end = 240 + 4 + 3, 2982 .vtotal = 240 + 4 + 3 + 15, 2983 }; 2984 2985 static const struct panel_desc lemaker_bl035_rgb_002 = { 2986 .modes = &lemaker_bl035_rgb_002_mode, 2987 .num_modes = 1, 2988 .size = { 2989 .width = 70, 2990 .height = 52, 2991 }, 2992 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2993 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2994 }; 2995 2996 static const struct display_timing lg_lb070wv8_timing = { 2997 .pixelclock = { 31950000, 33260000, 34600000 }, 2998 .hactive = { 800, 800, 800 }, 2999 .hfront_porch = { 88, 88, 88 }, 3000 .hback_porch = { 88, 88, 88 }, 3001 .hsync_len = { 80, 80, 80 }, 3002 .vactive = { 480, 480, 480 }, 3003 .vfront_porch = { 10, 10, 10 }, 3004 .vback_porch = { 10, 10, 10 }, 3005 .vsync_len = { 25, 25, 25 }, 3006 }; 3007 3008 static const struct panel_desc lg_lb070wv8 = { 3009 .timings = &lg_lb070wv8_timing, 3010 .num_timings = 1, 3011 .bpc = 8, 3012 .size = { 3013 .width = 151, 3014 .height = 91, 3015 }, 3016 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3017 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3018 }; 3019 3020 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 3021 .clock = 155127, 3022 .hdisplay = 1920, 3023 .hsync_start = 1920 + 128, 3024 .hsync_end = 1920 + 128 + 20, 3025 .htotal = 1920 + 128 + 20 + 12, 3026 .vdisplay = 1200, 3027 .vsync_start = 1200 + 19, 3028 .vsync_end = 1200 + 19 + 4, 3029 .vtotal = 1200 + 19 + 4 + 20, 3030 }; 3031 3032 static const struct panel_desc lincolntech_lcd185_101ct = { 3033 .modes = &lincolntech_lcd185_101ct_mode, 3034 .bpc = 8, 3035 .num_modes = 1, 3036 .size = { 3037 .width = 217, 3038 .height = 136, 3039 }, 3040 .delay = { 3041 .prepare = 50, 3042 .disable = 50, 3043 }, 3044 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3045 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3046 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3047 }; 3048 3049 static const struct display_timing logictechno_lt161010_2nh_timing = { 3050 .pixelclock = { 26400000, 33300000, 46800000 }, 3051 .hactive = { 800, 800, 800 }, 3052 .hfront_porch = { 16, 210, 354 }, 3053 .hback_porch = { 46, 46, 46 }, 3054 .hsync_len = { 1, 20, 40 }, 3055 .vactive = { 480, 480, 480 }, 3056 .vfront_porch = { 7, 22, 147 }, 3057 .vback_porch = { 23, 23, 23 }, 3058 .vsync_len = { 1, 10, 20 }, 3059 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3060 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3061 DISPLAY_FLAGS_SYNC_POSEDGE, 3062 }; 3063 3064 static const struct panel_desc logictechno_lt161010_2nh = { 3065 .timings = &logictechno_lt161010_2nh_timing, 3066 .num_timings = 1, 3067 .bpc = 6, 3068 .size = { 3069 .width = 154, 3070 .height = 86, 3071 }, 3072 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3073 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3074 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3075 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3076 .connector_type = DRM_MODE_CONNECTOR_DPI, 3077 }; 3078 3079 static const struct display_timing logictechno_lt170410_2whc_timing = { 3080 .pixelclock = { 68900000, 71100000, 73400000 }, 3081 .hactive = { 1280, 1280, 1280 }, 3082 .hfront_porch = { 23, 60, 71 }, 3083 .hback_porch = { 23, 60, 71 }, 3084 .hsync_len = { 15, 40, 47 }, 3085 .vactive = { 800, 800, 800 }, 3086 .vfront_porch = { 5, 7, 10 }, 3087 .vback_porch = { 5, 7, 10 }, 3088 .vsync_len = { 6, 9, 12 }, 3089 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3090 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3091 DISPLAY_FLAGS_SYNC_POSEDGE, 3092 }; 3093 3094 static const struct panel_desc logictechno_lt170410_2whc = { 3095 .timings = &logictechno_lt170410_2whc_timing, 3096 .num_timings = 1, 3097 .bpc = 8, 3098 .size = { 3099 .width = 217, 3100 .height = 136, 3101 }, 3102 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3103 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3104 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3105 }; 3106 3107 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3108 .clock = 33000, 3109 .hdisplay = 800, 3110 .hsync_start = 800 + 112, 3111 .hsync_end = 800 + 112 + 3, 3112 .htotal = 800 + 112 + 3 + 85, 3113 .vdisplay = 480, 3114 .vsync_start = 480 + 38, 3115 .vsync_end = 480 + 38 + 3, 3116 .vtotal = 480 + 38 + 3 + 29, 3117 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3118 }; 3119 3120 static const struct panel_desc logictechno_lttd800480070_l2rt = { 3121 .modes = &logictechno_lttd800480070_l2rt_mode, 3122 .num_modes = 1, 3123 .bpc = 8, 3124 .size = { 3125 .width = 154, 3126 .height = 86, 3127 }, 3128 .delay = { 3129 .prepare = 45, 3130 .enable = 100, 3131 .disable = 100, 3132 .unprepare = 45 3133 }, 3134 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3135 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3136 .connector_type = DRM_MODE_CONNECTOR_DPI, 3137 }; 3138 3139 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3140 .clock = 33000, 3141 .hdisplay = 800, 3142 .hsync_start = 800 + 154, 3143 .hsync_end = 800 + 154 + 3, 3144 .htotal = 800 + 154 + 3 + 43, 3145 .vdisplay = 480, 3146 .vsync_start = 480 + 47, 3147 .vsync_end = 480 + 47 + 3, 3148 .vtotal = 480 + 47 + 3 + 20, 3149 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3150 }; 3151 3152 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3153 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3154 .num_modes = 1, 3155 .bpc = 8, 3156 .size = { 3157 .width = 154, 3158 .height = 86, 3159 }, 3160 .delay = { 3161 .prepare = 45, 3162 .enable = 100, 3163 .disable = 100, 3164 .unprepare = 45 3165 }, 3166 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3167 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3168 .connector_type = DRM_MODE_CONNECTOR_DPI, 3169 }; 3170 3171 static const struct drm_display_mode logicpd_type_28_mode = { 3172 .clock = 9107, 3173 .hdisplay = 480, 3174 .hsync_start = 480 + 3, 3175 .hsync_end = 480 + 3 + 42, 3176 .htotal = 480 + 3 + 42 + 2, 3177 3178 .vdisplay = 272, 3179 .vsync_start = 272 + 2, 3180 .vsync_end = 272 + 2 + 11, 3181 .vtotal = 272 + 2 + 11 + 3, 3182 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3183 }; 3184 3185 static const struct panel_desc logicpd_type_28 = { 3186 .modes = &logicpd_type_28_mode, 3187 .num_modes = 1, 3188 .bpc = 8, 3189 .size = { 3190 .width = 105, 3191 .height = 67, 3192 }, 3193 .delay = { 3194 .prepare = 200, 3195 .enable = 200, 3196 .unprepare = 200, 3197 .disable = 200, 3198 }, 3199 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3200 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3201 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3202 .connector_type = DRM_MODE_CONNECTOR_DPI, 3203 }; 3204 3205 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3206 .clock = 150275, 3207 .hdisplay = 1920, 3208 .hsync_start = 1920 + 32, 3209 .hsync_end = 1920 + 32 + 52, 3210 .htotal = 1920 + 32 + 52 + 24, 3211 .vdisplay = 1200, 3212 .vsync_start = 1200 + 24, 3213 .vsync_end = 1200 + 24 + 8, 3214 .vtotal = 1200 + 24 + 8 + 3, 3215 }; 3216 3217 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3218 .modes = µtips_mf_101hiebcaf0_c_mode, 3219 .bpc = 8, 3220 .num_modes = 1, 3221 .size = { 3222 .width = 217, 3223 .height = 136, 3224 }, 3225 .delay = { 3226 .prepare = 50, 3227 .disable = 50, 3228 }, 3229 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3230 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3231 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3232 }; 3233 3234 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3235 .clock = 93301, 3236 .hdisplay = 1920, 3237 .hsync_start = 1920 + 72, 3238 .hsync_end = 1920 + 72 + 72, 3239 .htotal = 1920 + 72 + 72 + 72, 3240 .vdisplay = 720, 3241 .vsync_start = 720 + 3, 3242 .vsync_end = 720 + 3 + 3, 3243 .vtotal = 720 + 3 + 3 + 2, 3244 }; 3245 3246 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3247 .modes = µtips_mf_103hieb0ga0_mode, 3248 .bpc = 8, 3249 .num_modes = 1, 3250 .size = { 3251 .width = 244, 3252 .height = 92, 3253 }, 3254 .delay = { 3255 .prepare = 50, 3256 .disable = 50, 3257 }, 3258 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3259 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3260 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3261 }; 3262 3263 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3264 .clock = 30400, 3265 .hdisplay = 800, 3266 .hsync_start = 800 + 0, 3267 .hsync_end = 800 + 1, 3268 .htotal = 800 + 0 + 1 + 160, 3269 .vdisplay = 480, 3270 .vsync_start = 480 + 0, 3271 .vsync_end = 480 + 48 + 1, 3272 .vtotal = 480 + 48 + 1 + 0, 3273 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3274 }; 3275 3276 static const struct panel_desc mitsubishi_aa070mc01 = { 3277 .modes = &mitsubishi_aa070mc01_mode, 3278 .num_modes = 1, 3279 .bpc = 8, 3280 .size = { 3281 .width = 152, 3282 .height = 91, 3283 }, 3284 3285 .delay = { 3286 .enable = 200, 3287 .unprepare = 200, 3288 .disable = 400, 3289 }, 3290 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3291 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3292 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3293 }; 3294 3295 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3296 .clock = 56234, 3297 .hdisplay = 1024, 3298 .hsync_start = 1024 + 24, 3299 .hsync_end = 1024 + 24 + 63, 3300 .htotal = 1024 + 24 + 63 + 1, 3301 .vdisplay = 768, 3302 .vsync_start = 768 + 3, 3303 .vsync_end = 768 + 3 + 6, 3304 .vtotal = 768 + 3 + 6 + 1, 3305 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3306 }; 3307 3308 static const struct panel_desc mitsubishi_aa084xe01 = { 3309 .modes = &mitsubishi_aa084xe01_mode, 3310 .num_modes = 1, 3311 .bpc = 8, 3312 .size = { 3313 .width = 1024, 3314 .height = 768, 3315 }, 3316 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3317 .connector_type = DRM_MODE_CONNECTOR_DPI, 3318 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3319 }; 3320 3321 static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3322 .pixelclock = { 26400000, 33000000, 46800000 }, 3323 .hactive = { 800, 800, 800 }, 3324 .hfront_porch = { 16, 204, 354 }, 3325 .hback_porch = { 46, 46, 46 }, 3326 .hsync_len = { 1, 6, 40 }, 3327 .vactive = { 480, 480, 480 }, 3328 .vfront_porch = { 7, 22, 147 }, 3329 .vback_porch = { 23, 23, 23 }, 3330 .vsync_len = { 1, 3, 20 }, 3331 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3332 DISPLAY_FLAGS_DE_HIGH, 3333 }; 3334 3335 static const struct panel_desc multi_inno_mi0700a2t_30 = { 3336 .timings = &multi_inno_mi0700a2t_30_timing, 3337 .num_timings = 1, 3338 .bpc = 6, 3339 .size = { 3340 .width = 153, 3341 .height = 92, 3342 }, 3343 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3344 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3345 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3346 }; 3347 3348 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3349 .pixelclock = { 29000000, 33000000, 38000000 }, 3350 .hactive = { 800, 800, 800 }, 3351 .hfront_porch = { 180, 210, 240 }, 3352 .hback_porch = { 16, 16, 16 }, 3353 .hsync_len = { 30, 30, 30 }, 3354 .vactive = { 480, 480, 480 }, 3355 .vfront_porch = { 12, 22, 32 }, 3356 .vback_porch = { 10, 10, 10 }, 3357 .vsync_len = { 13, 13, 13 }, 3358 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3359 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3360 DISPLAY_FLAGS_SYNC_POSEDGE, 3361 }; 3362 3363 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3364 .timings = &multi_inno_mi0700s4t_6_timing, 3365 .num_timings = 1, 3366 .bpc = 8, 3367 .size = { 3368 .width = 154, 3369 .height = 86, 3370 }, 3371 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3372 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3373 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3374 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3375 .connector_type = DRM_MODE_CONNECTOR_DPI, 3376 }; 3377 3378 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3379 .pixelclock = { 32000000, 40000000, 50000000 }, 3380 .hactive = { 800, 800, 800 }, 3381 .hfront_porch = { 16, 210, 354 }, 3382 .hback_porch = { 6, 26, 45 }, 3383 .hsync_len = { 1, 20, 40 }, 3384 .vactive = { 600, 600, 600 }, 3385 .vfront_porch = { 1, 12, 77 }, 3386 .vback_porch = { 3, 13, 22 }, 3387 .vsync_len = { 1, 10, 20 }, 3388 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3389 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3390 DISPLAY_FLAGS_SYNC_POSEDGE, 3391 }; 3392 3393 static const struct panel_desc multi_inno_mi0800ft_9 = { 3394 .timings = &multi_inno_mi0800ft_9_timing, 3395 .num_timings = 1, 3396 .bpc = 8, 3397 .size = { 3398 .width = 162, 3399 .height = 122, 3400 }, 3401 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3402 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3403 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3404 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3405 .connector_type = DRM_MODE_CONNECTOR_DPI, 3406 }; 3407 3408 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3409 .pixelclock = { 68900000, 70000000, 73400000 }, 3410 .hactive = { 1280, 1280, 1280 }, 3411 .hfront_porch = { 30, 60, 71 }, 3412 .hback_porch = { 30, 60, 71 }, 3413 .hsync_len = { 10, 10, 48 }, 3414 .vactive = { 800, 800, 800 }, 3415 .vfront_porch = { 5, 10, 10 }, 3416 .vback_porch = { 5, 10, 10 }, 3417 .vsync_len = { 5, 6, 13 }, 3418 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3419 DISPLAY_FLAGS_DE_HIGH, 3420 }; 3421 3422 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3423 .timings = &multi_inno_mi1010ait_1cp_timing, 3424 .num_timings = 1, 3425 .bpc = 8, 3426 .size = { 3427 .width = 217, 3428 .height = 136, 3429 }, 3430 .delay = { 3431 .enable = 50, 3432 .disable = 50, 3433 }, 3434 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3435 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3436 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3437 }; 3438 3439 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3440 .pixelclock = { 40800000, 51200000, 67200000 }, 3441 .hactive = { 1024, 1024, 1024 }, 3442 .hfront_porch = { 30, 110, 130 }, 3443 .hback_porch = { 30, 110, 130 }, 3444 .hsync_len = { 30, 100, 116 }, 3445 .vactive = { 600, 600, 600 }, 3446 .vfront_porch = { 4, 13, 80 }, 3447 .vback_porch = { 4, 13, 80 }, 3448 .vsync_len = { 2, 9, 40 }, 3449 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3450 DISPLAY_FLAGS_DE_HIGH, 3451 }; 3452 3453 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3454 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3455 .num_timings = 1, 3456 .bpc = 6, 3457 .size = { 3458 .width = 260, 3459 .height = 162, 3460 }, 3461 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3462 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3463 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3464 }; 3465 3466 static const struct display_timing nec_nl12880bc20_05_timing = { 3467 .pixelclock = { 67000000, 71000000, 75000000 }, 3468 .hactive = { 1280, 1280, 1280 }, 3469 .hfront_porch = { 2, 30, 30 }, 3470 .hback_porch = { 6, 100, 100 }, 3471 .hsync_len = { 2, 30, 30 }, 3472 .vactive = { 800, 800, 800 }, 3473 .vfront_porch = { 5, 5, 5 }, 3474 .vback_porch = { 11, 11, 11 }, 3475 .vsync_len = { 7, 7, 7 }, 3476 }; 3477 3478 static const struct panel_desc nec_nl12880bc20_05 = { 3479 .timings = &nec_nl12880bc20_05_timing, 3480 .num_timings = 1, 3481 .bpc = 8, 3482 .size = { 3483 .width = 261, 3484 .height = 163, 3485 }, 3486 .delay = { 3487 .enable = 50, 3488 .disable = 50, 3489 }, 3490 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3491 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3492 }; 3493 3494 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3495 .clock = 10870, 3496 .hdisplay = 480, 3497 .hsync_start = 480 + 2, 3498 .hsync_end = 480 + 2 + 41, 3499 .htotal = 480 + 2 + 41 + 2, 3500 .vdisplay = 272, 3501 .vsync_start = 272 + 2, 3502 .vsync_end = 272 + 2 + 4, 3503 .vtotal = 272 + 2 + 4 + 2, 3504 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3505 }; 3506 3507 static const struct panel_desc nec_nl4827hc19_05b = { 3508 .modes = &nec_nl4827hc19_05b_mode, 3509 .num_modes = 1, 3510 .bpc = 8, 3511 .size = { 3512 .width = 95, 3513 .height = 54, 3514 }, 3515 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3516 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3517 }; 3518 3519 static const struct drm_display_mode netron_dy_e231732_mode = { 3520 .clock = 66000, 3521 .hdisplay = 1024, 3522 .hsync_start = 1024 + 160, 3523 .hsync_end = 1024 + 160 + 70, 3524 .htotal = 1024 + 160 + 70 + 90, 3525 .vdisplay = 600, 3526 .vsync_start = 600 + 127, 3527 .vsync_end = 600 + 127 + 20, 3528 .vtotal = 600 + 127 + 20 + 3, 3529 }; 3530 3531 static const struct panel_desc netron_dy_e231732 = { 3532 .modes = &netron_dy_e231732_mode, 3533 .num_modes = 1, 3534 .size = { 3535 .width = 154, 3536 .height = 87, 3537 }, 3538 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3539 }; 3540 3541 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3542 .clock = 9000, 3543 .hdisplay = 480, 3544 .hsync_start = 480 + 2, 3545 .hsync_end = 480 + 2 + 41, 3546 .htotal = 480 + 2 + 41 + 2, 3547 .vdisplay = 272, 3548 .vsync_start = 272 + 2, 3549 .vsync_end = 272 + 2 + 10, 3550 .vtotal = 272 + 2 + 10 + 2, 3551 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3552 }; 3553 3554 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3555 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3556 .num_modes = 1, 3557 .bpc = 8, 3558 .size = { 3559 .width = 95, 3560 .height = 54, 3561 }, 3562 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3563 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3564 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3565 .connector_type = DRM_MODE_CONNECTOR_DPI, 3566 }; 3567 3568 static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { 3569 .clock = 75400, 3570 .hdisplay = 1366, 3571 .hsync_start = 1366 + 14, 3572 .hsync_end = 1366 + 14 + 56, 3573 .htotal = 1366 + 14 + 56 + 64, 3574 .vdisplay = 768, 3575 .vsync_start = 768 + 1, 3576 .vsync_end = 768 + 1 + 3, 3577 .vtotal = 768 + 1 + 3 + 22, 3578 }; 3579 3580 static const struct panel_desc nlt_nl13676bc25_03f = { 3581 .modes = &nlt_nl13676bc25_03f_mode, 3582 .num_modes = 1, 3583 .bpc = 8, 3584 .size = { 3585 .width = 363, 3586 .height = 215, 3587 }, 3588 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3589 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3590 }; 3591 3592 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3593 .pixelclock = { 130000000, 148350000, 163000000 }, 3594 .hactive = { 1920, 1920, 1920 }, 3595 .hfront_porch = { 80, 100, 100 }, 3596 .hback_porch = { 100, 120, 120 }, 3597 .hsync_len = { 50, 60, 60 }, 3598 .vactive = { 1080, 1080, 1080 }, 3599 .vfront_porch = { 12, 30, 30 }, 3600 .vback_porch = { 4, 10, 10 }, 3601 .vsync_len = { 4, 5, 5 }, 3602 }; 3603 3604 static const struct panel_desc nlt_nl192108ac18_02d = { 3605 .timings = &nlt_nl192108ac18_02d_timing, 3606 .num_timings = 1, 3607 .bpc = 8, 3608 .size = { 3609 .width = 344, 3610 .height = 194, 3611 }, 3612 .delay = { 3613 .unprepare = 500, 3614 }, 3615 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3616 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3617 }; 3618 3619 static const struct drm_display_mode nvd_9128_mode = { 3620 .clock = 29500, 3621 .hdisplay = 800, 3622 .hsync_start = 800 + 130, 3623 .hsync_end = 800 + 130 + 98, 3624 .htotal = 800 + 0 + 130 + 98, 3625 .vdisplay = 480, 3626 .vsync_start = 480 + 10, 3627 .vsync_end = 480 + 10 + 50, 3628 .vtotal = 480 + 0 + 10 + 50, 3629 }; 3630 3631 static const struct panel_desc nvd_9128 = { 3632 .modes = &nvd_9128_mode, 3633 .num_modes = 1, 3634 .bpc = 8, 3635 .size = { 3636 .width = 156, 3637 .height = 88, 3638 }, 3639 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3640 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3641 }; 3642 3643 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3644 .pixelclock = { 30000000, 30000000, 40000000 }, 3645 .hactive = { 800, 800, 800 }, 3646 .hfront_porch = { 40, 40, 40 }, 3647 .hback_porch = { 40, 40, 40 }, 3648 .hsync_len = { 1, 48, 48 }, 3649 .vactive = { 480, 480, 480 }, 3650 .vfront_porch = { 13, 13, 13 }, 3651 .vback_porch = { 29, 29, 29 }, 3652 .vsync_len = { 3, 3, 3 }, 3653 .flags = DISPLAY_FLAGS_DE_HIGH, 3654 }; 3655 3656 static const struct panel_desc okaya_rs800480t_7x0gp = { 3657 .timings = &okaya_rs800480t_7x0gp_timing, 3658 .num_timings = 1, 3659 .bpc = 6, 3660 .size = { 3661 .width = 154, 3662 .height = 87, 3663 }, 3664 .delay = { 3665 .prepare = 41, 3666 .enable = 50, 3667 .unprepare = 41, 3668 .disable = 50, 3669 }, 3670 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3671 }; 3672 3673 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3674 .clock = 9000, 3675 .hdisplay = 480, 3676 .hsync_start = 480 + 5, 3677 .hsync_end = 480 + 5 + 30, 3678 .htotal = 480 + 5 + 30 + 10, 3679 .vdisplay = 272, 3680 .vsync_start = 272 + 8, 3681 .vsync_end = 272 + 8 + 5, 3682 .vtotal = 272 + 8 + 5 + 3, 3683 }; 3684 3685 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3686 .modes = &olimex_lcd_olinuxino_43ts_mode, 3687 .num_modes = 1, 3688 .size = { 3689 .width = 95, 3690 .height = 54, 3691 }, 3692 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3693 }; 3694 3695 static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 3696 .pixelclock = { 30000000, 30000000, 50000000 }, 3697 .hactive = { 800, 800, 800 }, 3698 .hfront_porch = { 1, 40, 255 }, 3699 .hback_porch = { 1, 40, 87 }, 3700 .hsync_len = { 1, 48, 87 }, 3701 .vactive = { 480, 480, 480 }, 3702 .vfront_porch = { 1, 13, 255 }, 3703 .vback_porch = { 1, 29, 29 }, 3704 .vsync_len = { 3, 3, 31 }, 3705 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3706 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3707 }; 3708 3709 static const struct panel_desc ontat_kd50g21_40nt_a1 = { 3710 .timings = &ontat_kd50g21_40nt_a1_timing, 3711 .num_timings = 1, 3712 .bpc = 8, 3713 .size = { 3714 .width = 108, 3715 .height = 65, 3716 }, 3717 .delay = { 3718 .prepare = 147, /* 5 VSDs */ 3719 .enable = 147, /* 5 VSDs */ 3720 .disable = 88, /* 3 VSDs */ 3721 .unprepare = 117, /* 4 VSDs */ 3722 }, 3723 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3724 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3725 .connector_type = DRM_MODE_CONNECTOR_DPI, 3726 }; 3727 3728 /* 3729 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3730 * pixel clocks, but this is the timing that was being used in the Adafruit 3731 * installation instructions. 3732 */ 3733 static const struct drm_display_mode ontat_yx700wv03_mode = { 3734 .clock = 29500, 3735 .hdisplay = 800, 3736 .hsync_start = 824, 3737 .hsync_end = 896, 3738 .htotal = 992, 3739 .vdisplay = 480, 3740 .vsync_start = 483, 3741 .vsync_end = 493, 3742 .vtotal = 500, 3743 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3744 }; 3745 3746 /* 3747 * Specification at: 3748 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3749 */ 3750 static const struct panel_desc ontat_yx700wv03 = { 3751 .modes = &ontat_yx700wv03_mode, 3752 .num_modes = 1, 3753 .bpc = 8, 3754 .size = { 3755 .width = 154, 3756 .height = 83, 3757 }, 3758 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3759 }; 3760 3761 static const struct drm_display_mode ortustech_com37h3m_mode = { 3762 .clock = 22230, 3763 .hdisplay = 480, 3764 .hsync_start = 480 + 40, 3765 .hsync_end = 480 + 40 + 10, 3766 .htotal = 480 + 40 + 10 + 40, 3767 .vdisplay = 640, 3768 .vsync_start = 640 + 4, 3769 .vsync_end = 640 + 4 + 2, 3770 .vtotal = 640 + 4 + 2 + 4, 3771 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3772 }; 3773 3774 static const struct panel_desc ortustech_com37h3m = { 3775 .modes = &ortustech_com37h3m_mode, 3776 .num_modes = 1, 3777 .bpc = 8, 3778 .size = { 3779 .width = 56, /* 56.16mm */ 3780 .height = 75, /* 74.88mm */ 3781 }, 3782 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3783 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3784 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3785 }; 3786 3787 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3788 .clock = 25000, 3789 .hdisplay = 480, 3790 .hsync_start = 480 + 10, 3791 .hsync_end = 480 + 10 + 10, 3792 .htotal = 480 + 10 + 10 + 15, 3793 .vdisplay = 800, 3794 .vsync_start = 800 + 3, 3795 .vsync_end = 800 + 3 + 3, 3796 .vtotal = 800 + 3 + 3 + 3, 3797 }; 3798 3799 static const struct panel_desc ortustech_com43h4m85ulc = { 3800 .modes = &ortustech_com43h4m85ulc_mode, 3801 .num_modes = 1, 3802 .bpc = 6, 3803 .size = { 3804 .width = 56, 3805 .height = 93, 3806 }, 3807 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3808 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3809 .connector_type = DRM_MODE_CONNECTOR_DPI, 3810 }; 3811 3812 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3813 .clock = 33000, 3814 .hdisplay = 800, 3815 .hsync_start = 800 + 210, 3816 .hsync_end = 800 + 210 + 30, 3817 .htotal = 800 + 210 + 30 + 16, 3818 .vdisplay = 480, 3819 .vsync_start = 480 + 22, 3820 .vsync_end = 480 + 22 + 13, 3821 .vtotal = 480 + 22 + 13 + 10, 3822 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3823 }; 3824 3825 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3826 .modes = &osddisplays_osd070t1718_19ts_mode, 3827 .num_modes = 1, 3828 .bpc = 8, 3829 .size = { 3830 .width = 152, 3831 .height = 91, 3832 }, 3833 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3834 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3835 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3836 .connector_type = DRM_MODE_CONNECTOR_DPI, 3837 }; 3838 3839 static const struct drm_display_mode pda_91_00156_a0_mode = { 3840 .clock = 33300, 3841 .hdisplay = 800, 3842 .hsync_start = 800 + 1, 3843 .hsync_end = 800 + 1 + 64, 3844 .htotal = 800 + 1 + 64 + 64, 3845 .vdisplay = 480, 3846 .vsync_start = 480 + 1, 3847 .vsync_end = 480 + 1 + 23, 3848 .vtotal = 480 + 1 + 23 + 22, 3849 }; 3850 3851 static const struct panel_desc pda_91_00156_a0 = { 3852 .modes = &pda_91_00156_a0_mode, 3853 .num_modes = 1, 3854 .size = { 3855 .width = 152, 3856 .height = 91, 3857 }, 3858 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3859 }; 3860 3861 static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { 3862 .clock = 71150, 3863 .hdisplay = 1280, 3864 .hsync_start = 1280 + 48, 3865 .hsync_end = 1280 + 48 + 32, 3866 .htotal = 1280 + 48 + 32 + 80, 3867 .vdisplay = 800, 3868 .vsync_start = 800 + 9, 3869 .vsync_end = 800 + 9 + 8, 3870 .vtotal = 800 + 9 + 8 + 6, 3871 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3872 }; 3873 3874 static const struct panel_desc powertip_ph128800t004_zza01 = { 3875 .modes = &powertip_ph128800t004_zza01_mode, 3876 .num_modes = 1, 3877 .bpc = 8, 3878 .size = { 3879 .width = 216, 3880 .height = 135, 3881 }, 3882 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3883 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3884 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3885 }; 3886 3887 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 3888 .clock = 66500, 3889 .hdisplay = 1280, 3890 .hsync_start = 1280 + 12, 3891 .hsync_end = 1280 + 12 + 20, 3892 .htotal = 1280 + 12 + 20 + 56, 3893 .vdisplay = 800, 3894 .vsync_start = 800 + 1, 3895 .vsync_end = 800 + 1 + 3, 3896 .vtotal = 800 + 1 + 3 + 20, 3897 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3898 }; 3899 3900 static const struct panel_desc powertip_ph128800t006_zhc01 = { 3901 .modes = &powertip_ph128800t006_zhc01_mode, 3902 .num_modes = 1, 3903 .bpc = 8, 3904 .size = { 3905 .width = 216, 3906 .height = 135, 3907 }, 3908 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3909 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3910 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3911 }; 3912 3913 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3914 .clock = 24750, 3915 .hdisplay = 800, 3916 .hsync_start = 800 + 54, 3917 .hsync_end = 800 + 54 + 2, 3918 .htotal = 800 + 54 + 2 + 44, 3919 .vdisplay = 480, 3920 .vsync_start = 480 + 49, 3921 .vsync_end = 480 + 49 + 2, 3922 .vtotal = 480 + 49 + 2 + 22, 3923 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3924 }; 3925 3926 static const struct panel_desc powertip_ph800480t013_idf02 = { 3927 .modes = &powertip_ph800480t013_idf02_mode, 3928 .num_modes = 1, 3929 .bpc = 8, 3930 .size = { 3931 .width = 152, 3932 .height = 91, 3933 }, 3934 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3935 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3936 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3937 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3938 .connector_type = DRM_MODE_CONNECTOR_DPI, 3939 }; 3940 3941 static const struct drm_display_mode primeview_pm070wl4_mode = { 3942 .clock = 32000, 3943 .hdisplay = 800, 3944 .hsync_start = 800 + 42, 3945 .hsync_end = 800 + 42 + 128, 3946 .htotal = 800 + 42 + 128 + 86, 3947 .vdisplay = 480, 3948 .vsync_start = 480 + 10, 3949 .vsync_end = 480 + 10 + 2, 3950 .vtotal = 480 + 10 + 2 + 33, 3951 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3952 }; 3953 3954 static const struct panel_desc primeview_pm070wl4 = { 3955 .modes = &primeview_pm070wl4_mode, 3956 .num_modes = 1, 3957 .bpc = 6, 3958 .size = { 3959 .width = 152, 3960 .height = 91, 3961 }, 3962 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3963 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3964 .connector_type = DRM_MODE_CONNECTOR_DPI, 3965 }; 3966 3967 static const struct drm_display_mode qd43003c0_40_mode = { 3968 .clock = 9000, 3969 .hdisplay = 480, 3970 .hsync_start = 480 + 8, 3971 .hsync_end = 480 + 8 + 4, 3972 .htotal = 480 + 8 + 4 + 39, 3973 .vdisplay = 272, 3974 .vsync_start = 272 + 4, 3975 .vsync_end = 272 + 4 + 10, 3976 .vtotal = 272 + 4 + 10 + 2, 3977 }; 3978 3979 static const struct panel_desc qd43003c0_40 = { 3980 .modes = &qd43003c0_40_mode, 3981 .num_modes = 1, 3982 .bpc = 8, 3983 .size = { 3984 .width = 95, 3985 .height = 53, 3986 }, 3987 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3988 }; 3989 3990 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3991 { /* 60 Hz */ 3992 .clock = 10800, 3993 .hdisplay = 480, 3994 .hsync_start = 480 + 77, 3995 .hsync_end = 480 + 77 + 41, 3996 .htotal = 480 + 77 + 41 + 2, 3997 .vdisplay = 272, 3998 .vsync_start = 272 + 16, 3999 .vsync_end = 272 + 16 + 10, 4000 .vtotal = 272 + 16 + 10 + 2, 4001 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4002 }, 4003 { /* 50 Hz */ 4004 .clock = 10800, 4005 .hdisplay = 480, 4006 .hsync_start = 480 + 17, 4007 .hsync_end = 480 + 17 + 41, 4008 .htotal = 480 + 17 + 41 + 2, 4009 .vdisplay = 272, 4010 .vsync_start = 272 + 116, 4011 .vsync_end = 272 + 116 + 10, 4012 .vtotal = 272 + 116 + 10 + 2, 4013 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4014 }, 4015 }; 4016 4017 static const struct panel_desc qishenglong_gopher2b_lcd = { 4018 .modes = qishenglong_gopher2b_lcd_modes, 4019 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 4020 .bpc = 8, 4021 .size = { 4022 .width = 95, 4023 .height = 54, 4024 }, 4025 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4026 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4027 .connector_type = DRM_MODE_CONNECTOR_DPI, 4028 }; 4029 4030 static const struct display_timing rocktech_rk043fn48h_timing = { 4031 .pixelclock = { 6000000, 9000000, 12000000 }, 4032 .hactive = { 480, 480, 480 }, 4033 .hback_porch = { 8, 43, 43 }, 4034 .hfront_porch = { 2, 8, 10 }, 4035 .hsync_len = { 1, 1, 1 }, 4036 .vactive = { 272, 272, 272 }, 4037 .vback_porch = { 2, 12, 26 }, 4038 .vfront_porch = { 1, 4, 4 }, 4039 .vsync_len = { 1, 10, 10 }, 4040 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 4041 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4042 DISPLAY_FLAGS_SYNC_POSEDGE, 4043 }; 4044 4045 static const struct panel_desc rocktech_rk043fn48h = { 4046 .timings = &rocktech_rk043fn48h_timing, 4047 .num_timings = 1, 4048 .bpc = 8, 4049 .size = { 4050 .width = 95, 4051 .height = 54, 4052 }, 4053 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4054 .connector_type = DRM_MODE_CONNECTOR_DPI, 4055 }; 4056 4057 static const struct display_timing rocktech_rk070er9427_timing = { 4058 .pixelclock = { 26400000, 33300000, 46800000 }, 4059 .hactive = { 800, 800, 800 }, 4060 .hfront_porch = { 16, 210, 354 }, 4061 .hback_porch = { 46, 46, 46 }, 4062 .hsync_len = { 1, 1, 1 }, 4063 .vactive = { 480, 480, 480 }, 4064 .vfront_porch = { 7, 22, 147 }, 4065 .vback_porch = { 23, 23, 23 }, 4066 .vsync_len = { 1, 1, 1 }, 4067 .flags = DISPLAY_FLAGS_DE_HIGH, 4068 }; 4069 4070 static const struct panel_desc rocktech_rk070er9427 = { 4071 .timings = &rocktech_rk070er9427_timing, 4072 .num_timings = 1, 4073 .bpc = 6, 4074 .size = { 4075 .width = 154, 4076 .height = 86, 4077 }, 4078 .delay = { 4079 .prepare = 41, 4080 .enable = 50, 4081 .unprepare = 41, 4082 .disable = 50, 4083 }, 4084 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4085 }; 4086 4087 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4088 .clock = 71100, 4089 .hdisplay = 1280, 4090 .hsync_start = 1280 + 48, 4091 .hsync_end = 1280 + 48 + 32, 4092 .htotal = 1280 + 48 + 32 + 80, 4093 .vdisplay = 800, 4094 .vsync_start = 800 + 2, 4095 .vsync_end = 800 + 2 + 5, 4096 .vtotal = 800 + 2 + 5 + 16, 4097 }; 4098 4099 static const struct panel_desc rocktech_rk101ii01d_ct = { 4100 .modes = &rocktech_rk101ii01d_ct_mode, 4101 .bpc = 8, 4102 .num_modes = 1, 4103 .size = { 4104 .width = 217, 4105 .height = 136, 4106 }, 4107 .delay = { 4108 .prepare = 50, 4109 .disable = 50, 4110 }, 4111 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4112 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4113 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4114 }; 4115 4116 static const struct display_timing samsung_ltl101al01_timing = { 4117 .pixelclock = { 66663000, 66663000, 66663000 }, 4118 .hactive = { 1280, 1280, 1280 }, 4119 .hfront_porch = { 18, 18, 18 }, 4120 .hback_porch = { 36, 36, 36 }, 4121 .hsync_len = { 16, 16, 16 }, 4122 .vactive = { 800, 800, 800 }, 4123 .vfront_porch = { 4, 4, 4 }, 4124 .vback_porch = { 16, 16, 16 }, 4125 .vsync_len = { 3, 3, 3 }, 4126 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4127 }; 4128 4129 static const struct panel_desc samsung_ltl101al01 = { 4130 .timings = &samsung_ltl101al01_timing, 4131 .num_timings = 1, 4132 .bpc = 8, 4133 .size = { 4134 .width = 217, 4135 .height = 135, 4136 }, 4137 .delay = { 4138 .prepare = 40, 4139 .enable = 300, 4140 .disable = 200, 4141 .unprepare = 600, 4142 }, 4143 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4144 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4145 }; 4146 4147 static const struct drm_display_mode samsung_ltn101nt05_mode = { 4148 .clock = 54030, 4149 .hdisplay = 1024, 4150 .hsync_start = 1024 + 24, 4151 .hsync_end = 1024 + 24 + 136, 4152 .htotal = 1024 + 24 + 136 + 160, 4153 .vdisplay = 600, 4154 .vsync_start = 600 + 3, 4155 .vsync_end = 600 + 3 + 6, 4156 .vtotal = 600 + 3 + 6 + 61, 4157 }; 4158 4159 static const struct panel_desc samsung_ltn101nt05 = { 4160 .modes = &samsung_ltn101nt05_mode, 4161 .num_modes = 1, 4162 .bpc = 6, 4163 .size = { 4164 .width = 223, 4165 .height = 125, 4166 }, 4167 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4168 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4169 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4170 }; 4171 4172 static const struct display_timing satoz_sat050at40h12r2_timing = { 4173 .pixelclock = {33300000, 33300000, 50000000}, 4174 .hactive = {800, 800, 800}, 4175 .hfront_porch = {16, 210, 354}, 4176 .hback_porch = {46, 46, 46}, 4177 .hsync_len = {1, 1, 40}, 4178 .vactive = {480, 480, 480}, 4179 .vfront_porch = {7, 22, 147}, 4180 .vback_porch = {23, 23, 23}, 4181 .vsync_len = {1, 1, 20}, 4182 }; 4183 4184 static const struct panel_desc satoz_sat050at40h12r2 = { 4185 .timings = &satoz_sat050at40h12r2_timing, 4186 .num_timings = 1, 4187 .bpc = 8, 4188 .size = { 4189 .width = 108, 4190 .height = 65, 4191 }, 4192 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4193 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4194 }; 4195 4196 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4197 .clock = 33260, 4198 .hdisplay = 800, 4199 .hsync_start = 800 + 64, 4200 .hsync_end = 800 + 64 + 128, 4201 .htotal = 800 + 64 + 128 + 64, 4202 .vdisplay = 480, 4203 .vsync_start = 480 + 8, 4204 .vsync_end = 480 + 8 + 2, 4205 .vtotal = 480 + 8 + 2 + 35, 4206 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4207 }; 4208 4209 static const struct panel_desc sharp_lq070y3dg3b = { 4210 .modes = &sharp_lq070y3dg3b_mode, 4211 .num_modes = 1, 4212 .bpc = 8, 4213 .size = { 4214 .width = 152, /* 152.4mm */ 4215 .height = 91, /* 91.4mm */ 4216 }, 4217 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4218 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4219 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4220 }; 4221 4222 static const struct drm_display_mode sharp_lq035q7db03_mode = { 4223 .clock = 5500, 4224 .hdisplay = 240, 4225 .hsync_start = 240 + 16, 4226 .hsync_end = 240 + 16 + 7, 4227 .htotal = 240 + 16 + 7 + 5, 4228 .vdisplay = 320, 4229 .vsync_start = 320 + 9, 4230 .vsync_end = 320 + 9 + 1, 4231 .vtotal = 320 + 9 + 1 + 7, 4232 }; 4233 4234 static const struct panel_desc sharp_lq035q7db03 = { 4235 .modes = &sharp_lq035q7db03_mode, 4236 .num_modes = 1, 4237 .bpc = 6, 4238 .size = { 4239 .width = 54, 4240 .height = 72, 4241 }, 4242 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4243 }; 4244 4245 static const struct display_timing sharp_lq101k1ly04_timing = { 4246 .pixelclock = { 60000000, 65000000, 80000000 }, 4247 .hactive = { 1280, 1280, 1280 }, 4248 .hfront_porch = { 20, 20, 20 }, 4249 .hback_porch = { 20, 20, 20 }, 4250 .hsync_len = { 10, 10, 10 }, 4251 .vactive = { 800, 800, 800 }, 4252 .vfront_porch = { 4, 4, 4 }, 4253 .vback_porch = { 4, 4, 4 }, 4254 .vsync_len = { 4, 4, 4 }, 4255 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4256 }; 4257 4258 static const struct panel_desc sharp_lq101k1ly04 = { 4259 .timings = &sharp_lq101k1ly04_timing, 4260 .num_timings = 1, 4261 .bpc = 8, 4262 .size = { 4263 .width = 217, 4264 .height = 136, 4265 }, 4266 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4267 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4268 }; 4269 4270 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4271 { /* 50 Hz */ 4272 .clock = 3000, 4273 .hdisplay = 240, 4274 .hsync_start = 240 + 58, 4275 .hsync_end = 240 + 58 + 1, 4276 .htotal = 240 + 58 + 1 + 1, 4277 .vdisplay = 160, 4278 .vsync_start = 160 + 24, 4279 .vsync_end = 160 + 24 + 10, 4280 .vtotal = 160 + 24 + 10 + 6, 4281 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4282 }, 4283 { /* 60 Hz */ 4284 .clock = 3000, 4285 .hdisplay = 240, 4286 .hsync_start = 240 + 8, 4287 .hsync_end = 240 + 8 + 1, 4288 .htotal = 240 + 8 + 1 + 1, 4289 .vdisplay = 160, 4290 .vsync_start = 160 + 24, 4291 .vsync_end = 160 + 24 + 10, 4292 .vtotal = 160 + 24 + 10 + 6, 4293 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4294 }, 4295 }; 4296 4297 static const struct panel_desc sharp_ls020b1dd01d = { 4298 .modes = sharp_ls020b1dd01d_modes, 4299 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4300 .bpc = 6, 4301 .size = { 4302 .width = 42, 4303 .height = 28, 4304 }, 4305 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4306 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4307 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4308 | DRM_BUS_FLAG_SHARP_SIGNALS, 4309 }; 4310 4311 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4312 .clock = 33300, 4313 .hdisplay = 800, 4314 .hsync_start = 800 + 1, 4315 .hsync_end = 800 + 1 + 64, 4316 .htotal = 800 + 1 + 64 + 64, 4317 .vdisplay = 480, 4318 .vsync_start = 480 + 1, 4319 .vsync_end = 480 + 1 + 23, 4320 .vtotal = 480 + 1 + 23 + 22, 4321 }; 4322 4323 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4324 .modes = &shelly_sca07010_bfn_lnn_mode, 4325 .num_modes = 1, 4326 .size = { 4327 .width = 152, 4328 .height = 91, 4329 }, 4330 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4331 }; 4332 4333 static const struct drm_display_mode starry_kr070pe2t_mode = { 4334 .clock = 33000, 4335 .hdisplay = 800, 4336 .hsync_start = 800 + 209, 4337 .hsync_end = 800 + 209 + 1, 4338 .htotal = 800 + 209 + 1 + 45, 4339 .vdisplay = 480, 4340 .vsync_start = 480 + 22, 4341 .vsync_end = 480 + 22 + 1, 4342 .vtotal = 480 + 22 + 1 + 22, 4343 }; 4344 4345 static const struct panel_desc starry_kr070pe2t = { 4346 .modes = &starry_kr070pe2t_mode, 4347 .num_modes = 1, 4348 .bpc = 8, 4349 .size = { 4350 .width = 152, 4351 .height = 86, 4352 }, 4353 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4354 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4355 .connector_type = DRM_MODE_CONNECTOR_DPI, 4356 }; 4357 4358 static const struct display_timing startek_kd070wvfpa_mode = { 4359 .pixelclock = { 25200000, 27200000, 30500000 }, 4360 .hactive = { 800, 800, 800 }, 4361 .hfront_porch = { 19, 44, 115 }, 4362 .hback_porch = { 5, 16, 101 }, 4363 .hsync_len = { 1, 2, 100 }, 4364 .vactive = { 480, 480, 480 }, 4365 .vfront_porch = { 5, 43, 67 }, 4366 .vback_porch = { 5, 5, 67 }, 4367 .vsync_len = { 1, 2, 66 }, 4368 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4369 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4370 DISPLAY_FLAGS_SYNC_POSEDGE, 4371 }; 4372 4373 static const struct panel_desc startek_kd070wvfpa = { 4374 .timings = &startek_kd070wvfpa_mode, 4375 .num_timings = 1, 4376 .bpc = 8, 4377 .size = { 4378 .width = 152, 4379 .height = 91, 4380 }, 4381 .delay = { 4382 .prepare = 20, 4383 .enable = 200, 4384 .disable = 200, 4385 }, 4386 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4387 .connector_type = DRM_MODE_CONNECTOR_DPI, 4388 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4389 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4390 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4391 }; 4392 4393 static const struct display_timing tsd_tst043015cmhx_timing = { 4394 .pixelclock = { 5000000, 9000000, 12000000 }, 4395 .hactive = { 480, 480, 480 }, 4396 .hfront_porch = { 4, 5, 65 }, 4397 .hback_porch = { 36, 40, 255 }, 4398 .hsync_len = { 1, 1, 1 }, 4399 .vactive = { 272, 272, 272 }, 4400 .vfront_porch = { 2, 8, 97 }, 4401 .vback_porch = { 3, 8, 31 }, 4402 .vsync_len = { 1, 1, 1 }, 4403 4404 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4405 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4406 }; 4407 4408 static const struct panel_desc tsd_tst043015cmhx = { 4409 .timings = &tsd_tst043015cmhx_timing, 4410 .num_timings = 1, 4411 .bpc = 8, 4412 .size = { 4413 .width = 105, 4414 .height = 67, 4415 }, 4416 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4417 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4418 }; 4419 4420 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4421 .clock = 30000, 4422 .hdisplay = 800, 4423 .hsync_start = 800 + 39, 4424 .hsync_end = 800 + 39 + 47, 4425 .htotal = 800 + 39 + 47 + 39, 4426 .vdisplay = 480, 4427 .vsync_start = 480 + 13, 4428 .vsync_end = 480 + 13 + 2, 4429 .vtotal = 480 + 13 + 2 + 29, 4430 }; 4431 4432 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4433 .modes = &tfc_s9700rtwv43tr_01b_mode, 4434 .num_modes = 1, 4435 .bpc = 8, 4436 .size = { 4437 .width = 155, 4438 .height = 90, 4439 }, 4440 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4441 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4442 }; 4443 4444 static const struct display_timing tianma_tm070jdhg30_timing = { 4445 .pixelclock = { 62600000, 68200000, 78100000 }, 4446 .hactive = { 1280, 1280, 1280 }, 4447 .hfront_porch = { 15, 64, 159 }, 4448 .hback_porch = { 5, 5, 5 }, 4449 .hsync_len = { 1, 1, 256 }, 4450 .vactive = { 800, 800, 800 }, 4451 .vfront_porch = { 3, 40, 99 }, 4452 .vback_porch = { 2, 2, 2 }, 4453 .vsync_len = { 1, 1, 128 }, 4454 .flags = DISPLAY_FLAGS_DE_HIGH, 4455 }; 4456 4457 static const struct panel_desc tianma_tm070jdhg30 = { 4458 .timings = &tianma_tm070jdhg30_timing, 4459 .num_timings = 1, 4460 .bpc = 8, 4461 .size = { 4462 .width = 151, 4463 .height = 95, 4464 }, 4465 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4466 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4467 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4468 }; 4469 4470 static const struct panel_desc tianma_tm070jvhg33 = { 4471 .timings = &tianma_tm070jdhg30_timing, 4472 .num_timings = 1, 4473 .bpc = 8, 4474 .size = { 4475 .width = 150, 4476 .height = 94, 4477 }, 4478 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4479 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4480 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4481 }; 4482 4483 /* 4484 * The TM070JDHG34-00 datasheet computes total blanking as back porch + 4485 * front porch, not including sync pulse width. This is for both H and 4486 * V. To make the total blanking and period correct, subtract the pulse 4487 * width from the front porch. 4488 * 4489 * This works well for the Min and Typ values, but for Max values the sync 4490 * pulse width is higher than back porch + front porch, so work around that 4491 * by reducing the Max sync length value to 1 and then treating the Max 4492 * porches as in the Min and Typ cases. 4493 * 4494 * Exact datasheet values are added as a comment where they differ from the 4495 * ones implemented for the above reason. 4496 * 4497 * The P0700WXF1MBAA datasheet is even less detailed, only listing period 4498 * and total blanking time, however the resulting values are the same as 4499 * the TM070JDHG34-00. 4500 */ 4501 static const struct display_timing tianma_tm070jdhg34_00_timing = { 4502 .pixelclock = { 68400000, 71900000, 78100000 }, 4503 .hactive = { 1280, 1280, 1280 }, 4504 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4505 .hback_porch = { 5, 5, 5 }, 4506 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4507 .vactive = { 800, 800, 800 }, 4508 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4509 .vback_porch = { 2, 2, 2 }, 4510 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4511 .flags = DISPLAY_FLAGS_DE_HIGH, 4512 }; 4513 4514 static const struct panel_desc tianma_tm070jdhg34_00 = { 4515 .timings = &tianma_tm070jdhg34_00_timing, 4516 .num_timings = 1, 4517 .bpc = 8, 4518 .size = { 4519 .width = 150, /* 149.76 */ 4520 .height = 94, /* 93.60 */ 4521 }, 4522 .delay = { 4523 .prepare = 15, /* Tp1 */ 4524 .enable = 150, /* Tp2 */ 4525 .disable = 150, /* Tp4 */ 4526 .unprepare = 120, /* Tp3 */ 4527 }, 4528 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4529 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4530 }; 4531 4532 static const struct panel_desc tianma_p0700wxf1mbaa = { 4533 .timings = &tianma_tm070jdhg34_00_timing, 4534 .num_timings = 1, 4535 .bpc = 8, 4536 .size = { 4537 .width = 150, /* 149.76 */ 4538 .height = 94, /* 93.60 */ 4539 }, 4540 .delay = { 4541 .prepare = 18, /* Tr + Tp1 */ 4542 .enable = 152, /* Tp2 + Tp5 */ 4543 .disable = 152, /* Tp6 + Tp4 */ 4544 .unprepare = 120, /* Tp3 */ 4545 }, 4546 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4547 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4548 }; 4549 4550 static const struct display_timing tianma_tm070rvhg71_timing = { 4551 .pixelclock = { 27700000, 29200000, 39600000 }, 4552 .hactive = { 800, 800, 800 }, 4553 .hfront_porch = { 12, 40, 212 }, 4554 .hback_porch = { 88, 88, 88 }, 4555 .hsync_len = { 1, 1, 40 }, 4556 .vactive = { 480, 480, 480 }, 4557 .vfront_porch = { 1, 13, 88 }, 4558 .vback_porch = { 32, 32, 32 }, 4559 .vsync_len = { 1, 1, 3 }, 4560 .flags = DISPLAY_FLAGS_DE_HIGH, 4561 }; 4562 4563 static const struct panel_desc tianma_tm070rvhg71 = { 4564 .timings = &tianma_tm070rvhg71_timing, 4565 .num_timings = 1, 4566 .bpc = 8, 4567 .size = { 4568 .width = 154, 4569 .height = 86, 4570 }, 4571 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4572 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4573 }; 4574 4575 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4576 { 4577 .clock = 10000, 4578 .hdisplay = 320, 4579 .hsync_start = 320 + 50, 4580 .hsync_end = 320 + 50 + 6, 4581 .htotal = 320 + 50 + 6 + 38, 4582 .vdisplay = 240, 4583 .vsync_start = 240 + 3, 4584 .vsync_end = 240 + 3 + 1, 4585 .vtotal = 240 + 3 + 1 + 17, 4586 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4587 }, 4588 }; 4589 4590 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4591 .modes = ti_nspire_cx_lcd_mode, 4592 .num_modes = 1, 4593 .bpc = 8, 4594 .size = { 4595 .width = 65, 4596 .height = 49, 4597 }, 4598 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4599 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4600 }; 4601 4602 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4603 { 4604 .clock = 10000, 4605 .hdisplay = 320, 4606 .hsync_start = 320 + 6, 4607 .hsync_end = 320 + 6 + 6, 4608 .htotal = 320 + 6 + 6 + 6, 4609 .vdisplay = 240, 4610 .vsync_start = 240 + 0, 4611 .vsync_end = 240 + 0 + 1, 4612 .vtotal = 240 + 0 + 1 + 0, 4613 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4614 }, 4615 }; 4616 4617 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4618 .modes = ti_nspire_classic_lcd_mode, 4619 .num_modes = 1, 4620 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4621 .bpc = 8, 4622 .size = { 4623 .width = 71, 4624 .height = 53, 4625 }, 4626 /* This is the grayscale bus format */ 4627 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4628 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4629 }; 4630 4631 static const struct display_timing topland_tian_g07017_01_timing = { 4632 .pixelclock = { 44900000, 51200000, 63000000 }, 4633 .hactive = { 1024, 1024, 1024 }, 4634 .hfront_porch = { 16, 160, 216 }, 4635 .hback_porch = { 160, 160, 160 }, 4636 .hsync_len = { 1, 1, 140 }, 4637 .vactive = { 600, 600, 600 }, 4638 .vfront_porch = { 1, 12, 127 }, 4639 .vback_porch = { 23, 23, 23 }, 4640 .vsync_len = { 1, 1, 20 }, 4641 }; 4642 4643 static const struct panel_desc topland_tian_g07017_01 = { 4644 .timings = &topland_tian_g07017_01_timing, 4645 .num_timings = 1, 4646 .bpc = 8, 4647 .size = { 4648 .width = 154, 4649 .height = 86, 4650 }, 4651 .delay = { 4652 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 4653 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 4654 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 4655 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 4656 }, 4657 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4658 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4659 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4660 }; 4661 4662 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4663 .clock = 79500, 4664 .hdisplay = 1280, 4665 .hsync_start = 1280 + 192, 4666 .hsync_end = 1280 + 192 + 128, 4667 .htotal = 1280 + 192 + 128 + 64, 4668 .vdisplay = 768, 4669 .vsync_start = 768 + 20, 4670 .vsync_end = 768 + 20 + 7, 4671 .vtotal = 768 + 20 + 7 + 3, 4672 }; 4673 4674 static const struct panel_desc toshiba_lt089ac29000 = { 4675 .modes = &toshiba_lt089ac29000_mode, 4676 .num_modes = 1, 4677 .size = { 4678 .width = 194, 4679 .height = 116, 4680 }, 4681 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4682 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4683 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4684 }; 4685 4686 static const struct drm_display_mode tpk_f07a_0102_mode = { 4687 .clock = 33260, 4688 .hdisplay = 800, 4689 .hsync_start = 800 + 40, 4690 .hsync_end = 800 + 40 + 128, 4691 .htotal = 800 + 40 + 128 + 88, 4692 .vdisplay = 480, 4693 .vsync_start = 480 + 10, 4694 .vsync_end = 480 + 10 + 2, 4695 .vtotal = 480 + 10 + 2 + 33, 4696 }; 4697 4698 static const struct panel_desc tpk_f07a_0102 = { 4699 .modes = &tpk_f07a_0102_mode, 4700 .num_modes = 1, 4701 .size = { 4702 .width = 152, 4703 .height = 91, 4704 }, 4705 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4706 }; 4707 4708 static const struct drm_display_mode tpk_f10a_0102_mode = { 4709 .clock = 45000, 4710 .hdisplay = 1024, 4711 .hsync_start = 1024 + 176, 4712 .hsync_end = 1024 + 176 + 5, 4713 .htotal = 1024 + 176 + 5 + 88, 4714 .vdisplay = 600, 4715 .vsync_start = 600 + 20, 4716 .vsync_end = 600 + 20 + 5, 4717 .vtotal = 600 + 20 + 5 + 25, 4718 }; 4719 4720 static const struct panel_desc tpk_f10a_0102 = { 4721 .modes = &tpk_f10a_0102_mode, 4722 .num_modes = 1, 4723 .size = { 4724 .width = 223, 4725 .height = 125, 4726 }, 4727 }; 4728 4729 static const struct display_timing urt_umsh_8596md_timing = { 4730 .pixelclock = { 33260000, 33260000, 33260000 }, 4731 .hactive = { 800, 800, 800 }, 4732 .hfront_porch = { 41, 41, 41 }, 4733 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4734 .hsync_len = { 71, 128, 128 }, 4735 .vactive = { 480, 480, 480 }, 4736 .vfront_porch = { 10, 10, 10 }, 4737 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4738 .vsync_len = { 2, 2, 2 }, 4739 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4740 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4741 }; 4742 4743 static const struct panel_desc urt_umsh_8596md_lvds = { 4744 .timings = &urt_umsh_8596md_timing, 4745 .num_timings = 1, 4746 .bpc = 6, 4747 .size = { 4748 .width = 152, 4749 .height = 91, 4750 }, 4751 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4752 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4753 }; 4754 4755 static const struct panel_desc urt_umsh_8596md_parallel = { 4756 .timings = &urt_umsh_8596md_timing, 4757 .num_timings = 1, 4758 .bpc = 6, 4759 .size = { 4760 .width = 152, 4761 .height = 91, 4762 }, 4763 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4764 }; 4765 4766 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4767 .clock = 60000, 4768 .hdisplay = 1024, 4769 .hsync_start = 1024 + 160, 4770 .hsync_end = 1024 + 160 + 100, 4771 .htotal = 1024 + 160 + 100 + 60, 4772 .vdisplay = 600, 4773 .vsync_start = 600 + 12, 4774 .vsync_end = 600 + 12 + 10, 4775 .vtotal = 600 + 12 + 10 + 13, 4776 }; 4777 4778 static const struct panel_desc vivax_tpc9150_panel = { 4779 .modes = &vivax_tpc9150_panel_mode, 4780 .num_modes = 1, 4781 .bpc = 6, 4782 .size = { 4783 .width = 200, 4784 .height = 115, 4785 }, 4786 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4787 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4788 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4789 }; 4790 4791 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4792 .clock = 33333, 4793 .hdisplay = 800, 4794 .hsync_start = 800 + 210, 4795 .hsync_end = 800 + 210 + 20, 4796 .htotal = 800 + 210 + 20 + 46, 4797 .vdisplay = 480, 4798 .vsync_start = 480 + 22, 4799 .vsync_end = 480 + 22 + 10, 4800 .vtotal = 480 + 22 + 10 + 23, 4801 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4802 }; 4803 4804 static const struct panel_desc vl050_8048nt_c01 = { 4805 .modes = &vl050_8048nt_c01_mode, 4806 .num_modes = 1, 4807 .bpc = 8, 4808 .size = { 4809 .width = 120, 4810 .height = 76, 4811 }, 4812 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4813 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4814 }; 4815 4816 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4817 .clock = 6410, 4818 .hdisplay = 320, 4819 .hsync_start = 320 + 20, 4820 .hsync_end = 320 + 20 + 30, 4821 .htotal = 320 + 20 + 30 + 38, 4822 .vdisplay = 240, 4823 .vsync_start = 240 + 4, 4824 .vsync_end = 240 + 4 + 3, 4825 .vtotal = 240 + 4 + 3 + 15, 4826 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4827 }; 4828 4829 static const struct panel_desc winstar_wf35ltiacd = { 4830 .modes = &winstar_wf35ltiacd_mode, 4831 .num_modes = 1, 4832 .bpc = 8, 4833 .size = { 4834 .width = 70, 4835 .height = 53, 4836 }, 4837 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4838 }; 4839 4840 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4841 .clock = 51200, 4842 .hdisplay = 1024, 4843 .hsync_start = 1024 + 100, 4844 .hsync_end = 1024 + 100 + 100, 4845 .htotal = 1024 + 100 + 100 + 120, 4846 .vdisplay = 600, 4847 .vsync_start = 600 + 10, 4848 .vsync_end = 600 + 10 + 10, 4849 .vtotal = 600 + 10 + 10 + 15, 4850 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4851 }; 4852 4853 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4854 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4855 .num_modes = 1, 4856 .bpc = 8, 4857 .size = { 4858 .width = 154, 4859 .height = 90, 4860 }, 4861 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4862 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4863 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4864 }; 4865 4866 static const struct drm_display_mode mchp_ac69t88a_mode = { 4867 .clock = 25000, 4868 .hdisplay = 800, 4869 .hsync_start = 800 + 88, 4870 .hsync_end = 800 + 88 + 5, 4871 .htotal = 800 + 88 + 5 + 40, 4872 .vdisplay = 480, 4873 .vsync_start = 480 + 23, 4874 .vsync_end = 480 + 23 + 5, 4875 .vtotal = 480 + 23 + 5 + 1, 4876 }; 4877 4878 static const struct panel_desc mchp_ac69t88a = { 4879 .modes = &mchp_ac69t88a_mode, 4880 .num_modes = 1, 4881 .bpc = 8, 4882 .size = { 4883 .width = 108, 4884 .height = 65, 4885 }, 4886 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4887 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4888 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4889 }; 4890 4891 static const struct drm_display_mode arm_rtsm_mode[] = { 4892 { 4893 .clock = 65000, 4894 .hdisplay = 1024, 4895 .hsync_start = 1024 + 24, 4896 .hsync_end = 1024 + 24 + 136, 4897 .htotal = 1024 + 24 + 136 + 160, 4898 .vdisplay = 768, 4899 .vsync_start = 768 + 3, 4900 .vsync_end = 768 + 3 + 6, 4901 .vtotal = 768 + 3 + 6 + 29, 4902 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4903 }, 4904 }; 4905 4906 static const struct panel_desc arm_rtsm = { 4907 .modes = arm_rtsm_mode, 4908 .num_modes = 1, 4909 .bpc = 8, 4910 .size = { 4911 .width = 400, 4912 .height = 300, 4913 }, 4914 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4915 }; 4916 4917 static const struct of_device_id platform_of_match[] = { 4918 { 4919 .compatible = "ampire,am-1280800n3tzqw-t00h", 4920 .data = &ire_am_1280800n3tzqw_t00h, 4921 }, { 4922 .compatible = "ampire,am-480272h3tmqw-t01h", 4923 .data = &ire_am_480272h3tmqw_t01h, 4924 }, { 4925 .compatible = "ampire,am-800480l1tmqw-t00h", 4926 .data = &ire_am_800480l1tmqw_t00h, 4927 }, { 4928 .compatible = "ampire,am800480r3tmqwa1h", 4929 .data = &ire_am800480r3tmqwa1h, 4930 }, { 4931 .compatible = "ampire,am800600p5tmqw-tb8h", 4932 .data = &ire_am800600p5tmqwtb8h, 4933 }, { 4934 .compatible = "arm,rtsm-display", 4935 .data = &arm_rtsm, 4936 }, { 4937 .compatible = "armadeus,st0700-adapt", 4938 .data = &armadeus_st0700_adapt, 4939 }, { 4940 .compatible = "auo,b101aw03", 4941 .data = &auo_b101aw03, 4942 }, { 4943 .compatible = "auo,b101xtn01", 4944 .data = &auo_b101xtn01, 4945 }, { 4946 .compatible = "auo,b116xw03", 4947 .data = &auo_b116xw03, 4948 }, { 4949 .compatible = "auo,g070vvn01", 4950 .data = &auo_g070vvn01, 4951 }, { 4952 .compatible = "auo,g101evn010", 4953 .data = &auo_g101evn010, 4954 }, { 4955 .compatible = "auo,g104sn02", 4956 .data = &auo_g104sn02, 4957 }, { 4958 .compatible = "auo,g104stn01", 4959 .data = &auo_g104stn01, 4960 }, { 4961 .compatible = "auo,g121ean01", 4962 .data = &auo_g121ean01, 4963 }, { 4964 .compatible = "auo,g133han01", 4965 .data = &auo_g133han01, 4966 }, { 4967 .compatible = "auo,g156han04", 4968 .data = &auo_g156han04, 4969 }, { 4970 .compatible = "auo,g156xtn01", 4971 .data = &auo_g156xtn01, 4972 }, { 4973 .compatible = "auo,g185han01", 4974 .data = &auo_g185han01, 4975 }, { 4976 .compatible = "auo,g190ean01", 4977 .data = &auo_g190ean01, 4978 }, { 4979 .compatible = "auo,p320hvn03", 4980 .data = &auo_p320hvn03, 4981 }, { 4982 .compatible = "auo,t215hvn01", 4983 .data = &auo_t215hvn01, 4984 }, { 4985 .compatible = "avic,tm070ddh03", 4986 .data = &avic_tm070ddh03, 4987 }, { 4988 .compatible = "bananapi,s070wv20-ct16", 4989 .data = &bananapi_s070wv20_ct16, 4990 }, { 4991 .compatible = "boe,av101hdt-a10", 4992 .data = &boe_av101hdt_a10, 4993 }, { 4994 .compatible = "boe,av123z7m-n17", 4995 .data = &boe_av123z7m_n17, 4996 }, { 4997 .compatible = "boe,bp082wx1-100", 4998 .data = &boe_bp082wx1_100, 4999 }, { 5000 .compatible = "boe,bp101wx1-100", 5001 .data = &boe_bp101wx1_100, 5002 }, { 5003 .compatible = "boe,ev121wxm-n10-1850", 5004 .data = &boe_ev121wxm_n10_1850, 5005 }, { 5006 .compatible = "boe,hv070wsa-100", 5007 .data = &boe_hv070wsa 5008 }, { 5009 .compatible = "cct,cmt430b19n00", 5010 .data = &cct_cmt430b19n00, 5011 }, { 5012 .compatible = "cdtech,s043wq26h-ct7", 5013 .data = &cdtech_s043wq26h_ct7, 5014 }, { 5015 .compatible = "cdtech,s070pws19hp-fc21", 5016 .data = &cdtech_s070pws19hp_fc21, 5017 }, { 5018 .compatible = "cdtech,s070swv29hg-dc44", 5019 .data = &cdtech_s070swv29hg_dc44, 5020 }, { 5021 .compatible = "cdtech,s070wv95-ct16", 5022 .data = &cdtech_s070wv95_ct16, 5023 }, { 5024 .compatible = "chefree,ch101olhlwh-002", 5025 .data = &chefree_ch101olhlwh_002, 5026 }, { 5027 .compatible = "chunghwa,claa070wp03xg", 5028 .data = &chunghwa_claa070wp03xg, 5029 }, { 5030 .compatible = "chunghwa,claa101wa01a", 5031 .data = &chunghwa_claa101wa01a 5032 }, { 5033 .compatible = "chunghwa,claa101wb01", 5034 .data = &chunghwa_claa101wb01 5035 }, { 5036 .compatible = "dataimage,fg040346dsswbg04", 5037 .data = &dataimage_fg040346dsswbg04, 5038 }, { 5039 .compatible = "dataimage,fg1001l0dsswmg01", 5040 .data = &dataimage_fg1001l0dsswmg01, 5041 }, { 5042 .compatible = "dataimage,scf0700c48ggu18", 5043 .data = &dataimage_scf0700c48ggu18, 5044 }, { 5045 .compatible = "dlc,dlc0700yzg-1", 5046 .data = &dlc_dlc0700yzg_1, 5047 }, { 5048 .compatible = "dlc,dlc1010gig", 5049 .data = &dlc_dlc1010gig, 5050 }, { 5051 .compatible = "edt,et035012dm6", 5052 .data = &edt_et035012dm6, 5053 }, { 5054 .compatible = "edt,etm0350g0dh6", 5055 .data = &edt_etm0350g0dh6, 5056 }, { 5057 .compatible = "edt,etm043080dh6gp", 5058 .data = &edt_etm043080dh6gp, 5059 }, { 5060 .compatible = "edt,etm0430g0dh6", 5061 .data = &edt_etm0430g0dh6, 5062 }, { 5063 .compatible = "edt,et057090dhu", 5064 .data = &edt_et057090dhu, 5065 }, { 5066 .compatible = "edt,et070080dh6", 5067 .data = &edt_etm0700g0dh6, 5068 }, { 5069 .compatible = "edt,etm0700g0dh6", 5070 .data = &edt_etm0700g0dh6, 5071 }, { 5072 .compatible = "edt,etm0700g0bdh6", 5073 .data = &edt_etm0700g0bdh6, 5074 }, { 5075 .compatible = "edt,etm0700g0edh6", 5076 .data = &edt_etm0700g0bdh6, 5077 }, { 5078 .compatible = "edt,etml0700y5dha", 5079 .data = &edt_etml0700y5dha, 5080 }, { 5081 .compatible = "edt,etml1010g3dra", 5082 .data = &edt_etml1010g3dra, 5083 }, { 5084 .compatible = "edt,etmv570g2dhu", 5085 .data = &edt_etmv570g2dhu, 5086 }, { 5087 .compatible = "eink,vb3300-kca", 5088 .data = &eink_vb3300_kca, 5089 }, { 5090 .compatible = "evervision,vgg644804", 5091 .data = &evervision_vgg644804, 5092 }, { 5093 .compatible = "evervision,vgg804821", 5094 .data = &evervision_vgg804821, 5095 }, { 5096 .compatible = "foxlink,fl500wvr00-a0t", 5097 .data = &foxlink_fl500wvr00_a0t, 5098 }, { 5099 .compatible = "frida,frd350h54004", 5100 .data = &frida_frd350h54004, 5101 }, { 5102 .compatible = "friendlyarm,hd702e", 5103 .data = &friendlyarm_hd702e, 5104 }, { 5105 .compatible = "giantplus,gpg482739qs5", 5106 .data = &giantplus_gpg482739qs5 5107 }, { 5108 .compatible = "giantplus,gpm940b0", 5109 .data = &giantplus_gpm940b0, 5110 }, { 5111 .compatible = "hannstar,hsd070pww1", 5112 .data = &hannstar_hsd070pww1, 5113 }, { 5114 .compatible = "hannstar,hsd100pxn1", 5115 .data = &hannstar_hsd100pxn1, 5116 }, { 5117 .compatible = "hannstar,hsd101pww2", 5118 .data = &hannstar_hsd101pww2, 5119 }, { 5120 .compatible = "hit,tx23d38vm0caa", 5121 .data = &hitachi_tx23d38vm0caa 5122 }, { 5123 .compatible = "innolux,at043tn24", 5124 .data = &innolux_at043tn24, 5125 }, { 5126 .compatible = "innolux,at070tn92", 5127 .data = &innolux_at070tn92, 5128 }, { 5129 .compatible = "innolux,g070ace-l01", 5130 .data = &innolux_g070ace_l01, 5131 }, { 5132 .compatible = "innolux,g070ace-lh3", 5133 .data = &innolux_g070ace_lh3, 5134 }, { 5135 .compatible = "innolux,g070y2-l01", 5136 .data = &innolux_g070y2_l01, 5137 }, { 5138 .compatible = "innolux,g070y2-t02", 5139 .data = &innolux_g070y2_t02, 5140 }, { 5141 .compatible = "innolux,g101ice-l01", 5142 .data = &innolux_g101ice_l01 5143 }, { 5144 .compatible = "innolux,g121i1-l01", 5145 .data = &innolux_g121i1_l01 5146 }, { 5147 .compatible = "innolux,g121x1-l03", 5148 .data = &innolux_g121x1_l03, 5149 }, { 5150 .compatible = "innolux,g121xce-l01", 5151 .data = &innolux_g121xce_l01, 5152 }, { 5153 .compatible = "innolux,g156hce-l01", 5154 .data = &innolux_g156hce_l01, 5155 }, { 5156 .compatible = "innolux,n156bge-l21", 5157 .data = &innolux_n156bge_l21, 5158 }, { 5159 .compatible = "innolux,zj070na-01p", 5160 .data = &innolux_zj070na_01p, 5161 }, { 5162 .compatible = "koe,tx14d24vm1bpa", 5163 .data = &koe_tx14d24vm1bpa, 5164 }, { 5165 .compatible = "koe,tx26d202vm0bwa", 5166 .data = &koe_tx26d202vm0bwa, 5167 }, { 5168 .compatible = "koe,tx31d200vm0baa", 5169 .data = &koe_tx31d200vm0baa, 5170 }, { 5171 .compatible = "kyo,tcg121xglp", 5172 .data = &kyo_tcg121xglp, 5173 }, { 5174 .compatible = "lemaker,bl035-rgb-002", 5175 .data = &lemaker_bl035_rgb_002, 5176 }, { 5177 .compatible = "lg,lb070wv8", 5178 .data = &lg_lb070wv8, 5179 }, { 5180 .compatible = "lincolntech,lcd185-101ct", 5181 .data = &lincolntech_lcd185_101ct, 5182 }, { 5183 .compatible = "logicpd,type28", 5184 .data = &logicpd_type_28, 5185 }, { 5186 .compatible = "logictechno,lt161010-2nhc", 5187 .data = &logictechno_lt161010_2nh, 5188 }, { 5189 .compatible = "logictechno,lt161010-2nhr", 5190 .data = &logictechno_lt161010_2nh, 5191 }, { 5192 .compatible = "logictechno,lt170410-2whc", 5193 .data = &logictechno_lt170410_2whc, 5194 }, { 5195 .compatible = "logictechno,lttd800480070-l2rt", 5196 .data = &logictechno_lttd800480070_l2rt, 5197 }, { 5198 .compatible = "logictechno,lttd800480070-l6wh-rt", 5199 .data = &logictechno_lttd800480070_l6wh_rt, 5200 }, { 5201 .compatible = "microtips,mf-101hiebcaf0", 5202 .data = µtips_mf_101hiebcaf0_c, 5203 }, { 5204 .compatible = "microtips,mf-103hieb0ga0", 5205 .data = µtips_mf_103hieb0ga0, 5206 }, { 5207 .compatible = "mitsubishi,aa070mc01-ca1", 5208 .data = &mitsubishi_aa070mc01, 5209 }, { 5210 .compatible = "mitsubishi,aa084xe01", 5211 .data = &mitsubishi_aa084xe01, 5212 }, { 5213 .compatible = "multi-inno,mi0700a2t-30", 5214 .data = &multi_inno_mi0700a2t_30, 5215 }, { 5216 .compatible = "multi-inno,mi0700s4t-6", 5217 .data = &multi_inno_mi0700s4t_6, 5218 }, { 5219 .compatible = "multi-inno,mi0800ft-9", 5220 .data = &multi_inno_mi0800ft_9, 5221 }, { 5222 .compatible = "multi-inno,mi1010ait-1cp", 5223 .data = &multi_inno_mi1010ait_1cp, 5224 }, { 5225 .compatible = "multi-inno,mi1010z1t-1cp11", 5226 .data = &multi_inno_mi1010z1t_1cp11, 5227 }, { 5228 .compatible = "nec,nl12880bc20-05", 5229 .data = &nec_nl12880bc20_05, 5230 }, { 5231 .compatible = "nec,nl4827hc19-05b", 5232 .data = &nec_nl4827hc19_05b, 5233 }, { 5234 .compatible = "netron-dy,e231732", 5235 .data = &netron_dy_e231732, 5236 }, { 5237 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 5238 .data = &newhaven_nhd_43_480272ef_atxl, 5239 }, { 5240 .compatible = "nlt,nl13676bc25-03f", 5241 .data = &nlt_nl13676bc25_03f, 5242 }, { 5243 .compatible = "nlt,nl192108ac18-02d", 5244 .data = &nlt_nl192108ac18_02d, 5245 }, { 5246 .compatible = "nvd,9128", 5247 .data = &nvd_9128, 5248 }, { 5249 .compatible = "okaya,rs800480t-7x0gp", 5250 .data = &okaya_rs800480t_7x0gp, 5251 }, { 5252 .compatible = "olimex,lcd-olinuxino-43-ts", 5253 .data = &olimex_lcd_olinuxino_43ts, 5254 }, { 5255 .compatible = "ontat,kd50g21-40nt-a1", 5256 .data = &ontat_kd50g21_40nt_a1, 5257 }, { 5258 .compatible = "ontat,yx700wv03", 5259 .data = &ontat_yx700wv03, 5260 }, { 5261 .compatible = "ortustech,com37h3m05dtc", 5262 .data = &ortustech_com37h3m, 5263 }, { 5264 .compatible = "ortustech,com37h3m99dtc", 5265 .data = &ortustech_com37h3m, 5266 }, { 5267 .compatible = "ortustech,com43h4m85ulc", 5268 .data = &ortustech_com43h4m85ulc, 5269 }, { 5270 .compatible = "osddisplays,osd070t1718-19ts", 5271 .data = &osddisplays_osd070t1718_19ts, 5272 }, { 5273 .compatible = "pda,91-00156-a0", 5274 .data = &pda_91_00156_a0, 5275 }, { 5276 .compatible = "powertip,ph128800t004-zza01", 5277 .data = &powertip_ph128800t004_zza01, 5278 }, { 5279 .compatible = "powertip,ph128800t006-zhc01", 5280 .data = &powertip_ph128800t006_zhc01, 5281 }, { 5282 .compatible = "powertip,ph800480t013-idf02", 5283 .data = &powertip_ph800480t013_idf02, 5284 }, { 5285 .compatible = "primeview,pm070wl4", 5286 .data = &primeview_pm070wl4, 5287 }, { 5288 .compatible = "qiaodian,qd43003c0-40", 5289 .data = &qd43003c0_40, 5290 }, { 5291 .compatible = "qishenglong,gopher2b-lcd", 5292 .data = &qishenglong_gopher2b_lcd, 5293 }, { 5294 .compatible = "rocktech,rk043fn48h", 5295 .data = &rocktech_rk043fn48h, 5296 }, { 5297 .compatible = "rocktech,rk070er9427", 5298 .data = &rocktech_rk070er9427, 5299 }, { 5300 .compatible = "rocktech,rk101ii01d-ct", 5301 .data = &rocktech_rk101ii01d_ct, 5302 }, { 5303 .compatible = "samsung,ltl101al01", 5304 .data = &samsung_ltl101al01, 5305 }, { 5306 .compatible = "samsung,ltn101nt05", 5307 .data = &samsung_ltn101nt05, 5308 }, { 5309 .compatible = "satoz,sat050at40h12r2", 5310 .data = &satoz_sat050at40h12r2, 5311 }, { 5312 .compatible = "sharp,lq035q7db03", 5313 .data = &sharp_lq035q7db03, 5314 }, { 5315 .compatible = "sharp,lq070y3dg3b", 5316 .data = &sharp_lq070y3dg3b, 5317 }, { 5318 .compatible = "sharp,lq101k1ly04", 5319 .data = &sharp_lq101k1ly04, 5320 }, { 5321 .compatible = "sharp,ls020b1dd01d", 5322 .data = &sharp_ls020b1dd01d, 5323 }, { 5324 .compatible = "shelly,sca07010-bfn-lnn", 5325 .data = &shelly_sca07010_bfn_lnn, 5326 }, { 5327 .compatible = "starry,kr070pe2t", 5328 .data = &starry_kr070pe2t, 5329 }, { 5330 .compatible = "startek,kd070wvfpa", 5331 .data = &startek_kd070wvfpa, 5332 }, { 5333 .compatible = "team-source-display,tst043015cmhx", 5334 .data = &tsd_tst043015cmhx, 5335 }, { 5336 .compatible = "tfc,s9700rtwv43tr-01b", 5337 .data = &tfc_s9700rtwv43tr_01b, 5338 }, { 5339 .compatible = "tianma,p0700wxf1mbaa", 5340 .data = &tianma_p0700wxf1mbaa, 5341 }, { 5342 .compatible = "tianma,tm070jdhg30", 5343 .data = &tianma_tm070jdhg30, 5344 }, { 5345 .compatible = "tianma,tm070jdhg34-00", 5346 .data = &tianma_tm070jdhg34_00, 5347 }, { 5348 .compatible = "tianma,tm070jvhg33", 5349 .data = &tianma_tm070jvhg33, 5350 }, { 5351 .compatible = "tianma,tm070rvhg71", 5352 .data = &tianma_tm070rvhg71, 5353 }, { 5354 .compatible = "ti,nspire-cx-lcd-panel", 5355 .data = &ti_nspire_cx_lcd_panel, 5356 }, { 5357 .compatible = "ti,nspire-classic-lcd-panel", 5358 .data = &ti_nspire_classic_lcd_panel, 5359 }, { 5360 .compatible = "toshiba,lt089ac29000", 5361 .data = &toshiba_lt089ac29000, 5362 }, { 5363 .compatible = "topland,tian-g07017-01", 5364 .data = &topland_tian_g07017_01, 5365 }, { 5366 .compatible = "tpk,f07a-0102", 5367 .data = &tpk_f07a_0102, 5368 }, { 5369 .compatible = "tpk,f10a-0102", 5370 .data = &tpk_f10a_0102, 5371 }, { 5372 .compatible = "urt,umsh-8596md-t", 5373 .data = &urt_umsh_8596md_parallel, 5374 }, { 5375 .compatible = "urt,umsh-8596md-1t", 5376 .data = &urt_umsh_8596md_parallel, 5377 }, { 5378 .compatible = "urt,umsh-8596md-7t", 5379 .data = &urt_umsh_8596md_parallel, 5380 }, { 5381 .compatible = "urt,umsh-8596md-11t", 5382 .data = &urt_umsh_8596md_lvds, 5383 }, { 5384 .compatible = "urt,umsh-8596md-19t", 5385 .data = &urt_umsh_8596md_lvds, 5386 }, { 5387 .compatible = "urt,umsh-8596md-20t", 5388 .data = &urt_umsh_8596md_parallel, 5389 }, { 5390 .compatible = "vivax,tpc9150-panel", 5391 .data = &vivax_tpc9150_panel, 5392 }, { 5393 .compatible = "vxt,vl050-8048nt-c01", 5394 .data = &vl050_8048nt_c01, 5395 }, { 5396 .compatible = "winstar,wf35ltiacd", 5397 .data = &winstar_wf35ltiacd, 5398 }, { 5399 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 5400 .data = &yes_optoelectronics_ytc700tlag_05_201c, 5401 }, { 5402 .compatible = "microchip,ac69t88a", 5403 .data = &mchp_ac69t88a, 5404 }, { 5405 /* Must be the last entry */ 5406 .compatible = "panel-dpi", 5407 5408 /* 5409 * Explicitly NULL, the panel_desc structure will be 5410 * allocated by panel_dpi_probe(). 5411 */ 5412 .data = NULL, 5413 }, { 5414 /* sentinel */ 5415 } 5416 }; 5417 MODULE_DEVICE_TABLE(of, platform_of_match); 5418 5419 static int panel_simple_platform_probe(struct platform_device *pdev) 5420 { 5421 struct panel_simple *panel; 5422 5423 panel = panel_simple_probe(&pdev->dev); 5424 if (IS_ERR(panel)) 5425 return PTR_ERR(panel); 5426 5427 return 0; 5428 } 5429 5430 static void panel_simple_platform_remove(struct platform_device *pdev) 5431 { 5432 panel_simple_remove(&pdev->dev); 5433 } 5434 5435 static void panel_simple_platform_shutdown(struct platform_device *pdev) 5436 { 5437 panel_simple_shutdown(&pdev->dev); 5438 } 5439 5440 static const struct dev_pm_ops panel_simple_pm_ops = { 5441 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 5442 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5443 pm_runtime_force_resume) 5444 }; 5445 5446 static struct platform_driver panel_simple_platform_driver = { 5447 .driver = { 5448 .name = "panel-simple", 5449 .of_match_table = platform_of_match, 5450 .pm = &panel_simple_pm_ops, 5451 }, 5452 .probe = panel_simple_platform_probe, 5453 .remove = panel_simple_platform_remove, 5454 .shutdown = panel_simple_platform_shutdown, 5455 }; 5456 5457 static const struct drm_display_mode auo_b080uan01_mode = { 5458 .clock = 154500, 5459 .hdisplay = 1200, 5460 .hsync_start = 1200 + 62, 5461 .hsync_end = 1200 + 62 + 4, 5462 .htotal = 1200 + 62 + 4 + 62, 5463 .vdisplay = 1920, 5464 .vsync_start = 1920 + 9, 5465 .vsync_end = 1920 + 9 + 2, 5466 .vtotal = 1920 + 9 + 2 + 8, 5467 }; 5468 5469 static const struct panel_desc_dsi auo_b080uan01 = { 5470 .desc = { 5471 .modes = &auo_b080uan01_mode, 5472 .num_modes = 1, 5473 .bpc = 8, 5474 .size = { 5475 .width = 108, 5476 .height = 272, 5477 }, 5478 .connector_type = DRM_MODE_CONNECTOR_DSI, 5479 }, 5480 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5481 .format = MIPI_DSI_FMT_RGB888, 5482 .lanes = 4, 5483 }; 5484 5485 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5486 .clock = 160000, 5487 .hdisplay = 1200, 5488 .hsync_start = 1200 + 120, 5489 .hsync_end = 1200 + 120 + 20, 5490 .htotal = 1200 + 120 + 20 + 21, 5491 .vdisplay = 1920, 5492 .vsync_start = 1920 + 21, 5493 .vsync_end = 1920 + 21 + 3, 5494 .vtotal = 1920 + 21 + 3 + 18, 5495 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5496 }; 5497 5498 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5499 .desc = { 5500 .modes = &boe_tv080wum_nl0_mode, 5501 .num_modes = 1, 5502 .size = { 5503 .width = 107, 5504 .height = 172, 5505 }, 5506 .connector_type = DRM_MODE_CONNECTOR_DSI, 5507 }, 5508 .flags = MIPI_DSI_MODE_VIDEO | 5509 MIPI_DSI_MODE_VIDEO_BURST | 5510 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5511 .format = MIPI_DSI_FMT_RGB888, 5512 .lanes = 4, 5513 }; 5514 5515 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 5516 .clock = 71000, 5517 .hdisplay = 800, 5518 .hsync_start = 800 + 32, 5519 .hsync_end = 800 + 32 + 1, 5520 .htotal = 800 + 32 + 1 + 57, 5521 .vdisplay = 1280, 5522 .vsync_start = 1280 + 28, 5523 .vsync_end = 1280 + 28 + 1, 5524 .vtotal = 1280 + 28 + 1 + 14, 5525 }; 5526 5527 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 5528 .desc = { 5529 .modes = &lg_ld070wx3_sl01_mode, 5530 .num_modes = 1, 5531 .bpc = 8, 5532 .size = { 5533 .width = 94, 5534 .height = 151, 5535 }, 5536 .connector_type = DRM_MODE_CONNECTOR_DSI, 5537 }, 5538 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5539 .format = MIPI_DSI_FMT_RGB888, 5540 .lanes = 4, 5541 }; 5542 5543 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5544 .clock = 67000, 5545 .hdisplay = 720, 5546 .hsync_start = 720 + 12, 5547 .hsync_end = 720 + 12 + 4, 5548 .htotal = 720 + 12 + 4 + 112, 5549 .vdisplay = 1280, 5550 .vsync_start = 1280 + 8, 5551 .vsync_end = 1280 + 8 + 4, 5552 .vtotal = 1280 + 8 + 4 + 12, 5553 }; 5554 5555 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5556 .desc = { 5557 .modes = &lg_lh500wx1_sd03_mode, 5558 .num_modes = 1, 5559 .bpc = 8, 5560 .size = { 5561 .width = 62, 5562 .height = 110, 5563 }, 5564 .connector_type = DRM_MODE_CONNECTOR_DSI, 5565 }, 5566 .flags = MIPI_DSI_MODE_VIDEO, 5567 .format = MIPI_DSI_FMT_RGB888, 5568 .lanes = 4, 5569 }; 5570 5571 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5572 .clock = 157200, 5573 .hdisplay = 1920, 5574 .hsync_start = 1920 + 154, 5575 .hsync_end = 1920 + 154 + 16, 5576 .htotal = 1920 + 154 + 16 + 32, 5577 .vdisplay = 1200, 5578 .vsync_start = 1200 + 17, 5579 .vsync_end = 1200 + 17 + 2, 5580 .vtotal = 1200 + 17 + 2 + 16, 5581 }; 5582 5583 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5584 .desc = { 5585 .modes = &panasonic_vvx10f004b00_mode, 5586 .num_modes = 1, 5587 .bpc = 8, 5588 .size = { 5589 .width = 217, 5590 .height = 136, 5591 }, 5592 .connector_type = DRM_MODE_CONNECTOR_DSI, 5593 }, 5594 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5595 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5596 .format = MIPI_DSI_FMT_RGB888, 5597 .lanes = 4, 5598 }; 5599 5600 static const struct drm_display_mode lg_acx467akm_7_mode = { 5601 .clock = 150000, 5602 .hdisplay = 1080, 5603 .hsync_start = 1080 + 2, 5604 .hsync_end = 1080 + 2 + 2, 5605 .htotal = 1080 + 2 + 2 + 2, 5606 .vdisplay = 1920, 5607 .vsync_start = 1920 + 2, 5608 .vsync_end = 1920 + 2 + 2, 5609 .vtotal = 1920 + 2 + 2 + 2, 5610 }; 5611 5612 static const struct panel_desc_dsi lg_acx467akm_7 = { 5613 .desc = { 5614 .modes = &lg_acx467akm_7_mode, 5615 .num_modes = 1, 5616 .bpc = 8, 5617 .size = { 5618 .width = 62, 5619 .height = 110, 5620 }, 5621 .connector_type = DRM_MODE_CONNECTOR_DSI, 5622 }, 5623 .flags = 0, 5624 .format = MIPI_DSI_FMT_RGB888, 5625 .lanes = 4, 5626 }; 5627 5628 static const struct drm_display_mode osd101t2045_53ts_mode = { 5629 .clock = 154500, 5630 .hdisplay = 1920, 5631 .hsync_start = 1920 + 112, 5632 .hsync_end = 1920 + 112 + 16, 5633 .htotal = 1920 + 112 + 16 + 32, 5634 .vdisplay = 1200, 5635 .vsync_start = 1200 + 16, 5636 .vsync_end = 1200 + 16 + 2, 5637 .vtotal = 1200 + 16 + 2 + 16, 5638 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5639 }; 5640 5641 static const struct panel_desc_dsi osd101t2045_53ts = { 5642 .desc = { 5643 .modes = &osd101t2045_53ts_mode, 5644 .num_modes = 1, 5645 .bpc = 8, 5646 .size = { 5647 .width = 217, 5648 .height = 136, 5649 }, 5650 .connector_type = DRM_MODE_CONNECTOR_DSI, 5651 }, 5652 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5653 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5654 MIPI_DSI_MODE_NO_EOT_PACKET, 5655 .format = MIPI_DSI_FMT_RGB888, 5656 .lanes = 4, 5657 }; 5658 5659 static const struct of_device_id dsi_of_match[] = { 5660 { 5661 .compatible = "auo,b080uan01", 5662 .data = &auo_b080uan01 5663 }, { 5664 .compatible = "boe,tv080wum-nl0", 5665 .data = &boe_tv080wum_nl0 5666 }, { 5667 .compatible = "lg,ld070wx3-sl01", 5668 .data = &lg_ld070wx3_sl01 5669 }, { 5670 .compatible = "lg,lh500wx1-sd03", 5671 .data = &lg_lh500wx1_sd03 5672 }, { 5673 .compatible = "panasonic,vvx10f004b00", 5674 .data = &panasonic_vvx10f004b00 5675 }, { 5676 .compatible = "lg,acx467akm-7", 5677 .data = &lg_acx467akm_7 5678 }, { 5679 .compatible = "osddisplays,osd101t2045-53ts", 5680 .data = &osd101t2045_53ts 5681 }, { 5682 /* sentinel */ 5683 } 5684 }; 5685 MODULE_DEVICE_TABLE(of, dsi_of_match); 5686 5687 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5688 { 5689 const struct panel_desc_dsi *desc; 5690 struct panel_simple *panel; 5691 int err; 5692 5693 panel = panel_simple_probe(&dsi->dev); 5694 if (IS_ERR(panel)) 5695 return PTR_ERR(panel); 5696 5697 desc = container_of(panel->desc, struct panel_desc_dsi, desc); 5698 dsi->mode_flags = desc->flags; 5699 dsi->format = desc->format; 5700 dsi->lanes = desc->lanes; 5701 5702 err = mipi_dsi_attach(dsi); 5703 if (err) { 5704 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5705 5706 drm_panel_remove(&panel->base); 5707 } 5708 5709 return err; 5710 } 5711 5712 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5713 { 5714 int err; 5715 5716 err = mipi_dsi_detach(dsi); 5717 if (err < 0) 5718 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5719 5720 panel_simple_remove(&dsi->dev); 5721 } 5722 5723 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5724 { 5725 panel_simple_shutdown(&dsi->dev); 5726 } 5727 5728 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5729 .driver = { 5730 .name = "panel-simple-dsi", 5731 .of_match_table = dsi_of_match, 5732 .pm = &panel_simple_pm_ops, 5733 }, 5734 .probe = panel_simple_dsi_probe, 5735 .remove = panel_simple_dsi_remove, 5736 .shutdown = panel_simple_dsi_shutdown, 5737 }; 5738 5739 static int __init panel_simple_init(void) 5740 { 5741 int err; 5742 5743 err = platform_driver_register(&panel_simple_platform_driver); 5744 if (err < 0) 5745 return err; 5746 5747 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5748 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5749 if (err < 0) 5750 goto err_did_platform_register; 5751 } 5752 5753 return 0; 5754 5755 err_did_platform_register: 5756 platform_driver_unregister(&panel_simple_platform_driver); 5757 5758 return err; 5759 } 5760 module_init(panel_simple_init); 5761 5762 static void __exit panel_simple_exit(void) 5763 { 5764 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5765 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5766 5767 platform_driver_unregister(&panel_simple_platform_driver); 5768 } 5769 module_exit(panel_simple_exit); 5770 5771 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5772 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5773 MODULE_LICENSE("GPL and additional rights"); 5774