1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/backlight.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regulator/consumer.h> 30 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_panel.h> 35 36 #include <video/display_timing.h> 37 #include <video/videomode.h> 38 39 struct panel_desc { 40 const struct drm_display_mode *modes; 41 unsigned int num_modes; 42 const struct display_timing *timings; 43 unsigned int num_timings; 44 45 unsigned int bpc; 46 47 /** 48 * @width: width (in millimeters) of the panel's active display area 49 * @height: height (in millimeters) of the panel's active display area 50 */ 51 struct { 52 unsigned int width; 53 unsigned int height; 54 } size; 55 56 /** 57 * @prepare: the time (in milliseconds) that it takes for the panel to 58 * become ready and start receiving video data 59 * @enable: the time (in milliseconds) that it takes for the panel to 60 * display the first valid frame after starting to receive 61 * video data 62 * @disable: the time (in milliseconds) that it takes for the panel to 63 * turn the display off (no content is visible) 64 * @unprepare: the time (in milliseconds) that it takes for the panel 65 * to power itself down completely 66 */ 67 struct { 68 unsigned int prepare; 69 unsigned int enable; 70 unsigned int disable; 71 unsigned int unprepare; 72 } delay; 73 74 u32 bus_format; 75 u32 bus_flags; 76 }; 77 78 struct panel_simple { 79 struct drm_panel base; 80 bool prepared; 81 bool enabled; 82 83 const struct panel_desc *desc; 84 85 struct backlight_device *backlight; 86 struct regulator *supply; 87 struct i2c_adapter *ddc; 88 89 struct gpio_desc *enable_gpio; 90 }; 91 92 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 93 { 94 return container_of(panel, struct panel_simple, base); 95 } 96 97 static int panel_simple_get_fixed_modes(struct panel_simple *panel) 98 { 99 struct drm_connector *connector = panel->base.connector; 100 struct drm_device *drm = panel->base.drm; 101 struct drm_display_mode *mode; 102 unsigned int i, num = 0; 103 104 if (!panel->desc) 105 return 0; 106 107 for (i = 0; i < panel->desc->num_timings; i++) { 108 const struct display_timing *dt = &panel->desc->timings[i]; 109 struct videomode vm; 110 111 videomode_from_timing(dt, &vm); 112 mode = drm_mode_create(drm); 113 if (!mode) { 114 dev_err(drm->dev, "failed to add mode %ux%u\n", 115 dt->hactive.typ, dt->vactive.typ); 116 continue; 117 } 118 119 drm_display_mode_from_videomode(&vm, mode); 120 121 mode->type |= DRM_MODE_TYPE_DRIVER; 122 123 if (panel->desc->num_timings == 1) 124 mode->type |= DRM_MODE_TYPE_PREFERRED; 125 126 drm_mode_probed_add(connector, mode); 127 num++; 128 } 129 130 for (i = 0; i < panel->desc->num_modes; i++) { 131 const struct drm_display_mode *m = &panel->desc->modes[i]; 132 133 mode = drm_mode_duplicate(drm, m); 134 if (!mode) { 135 dev_err(drm->dev, "failed to add mode %ux%u@%u\n", 136 m->hdisplay, m->vdisplay, m->vrefresh); 137 continue; 138 } 139 140 mode->type |= DRM_MODE_TYPE_DRIVER; 141 142 if (panel->desc->num_modes == 1) 143 mode->type |= DRM_MODE_TYPE_PREFERRED; 144 145 drm_mode_set_name(mode); 146 147 drm_mode_probed_add(connector, mode); 148 num++; 149 } 150 151 connector->display_info.bpc = panel->desc->bpc; 152 connector->display_info.width_mm = panel->desc->size.width; 153 connector->display_info.height_mm = panel->desc->size.height; 154 if (panel->desc->bus_format) 155 drm_display_info_set_bus_formats(&connector->display_info, 156 &panel->desc->bus_format, 1); 157 connector->display_info.bus_flags = panel->desc->bus_flags; 158 159 return num; 160 } 161 162 static int panel_simple_disable(struct drm_panel *panel) 163 { 164 struct panel_simple *p = to_panel_simple(panel); 165 166 if (!p->enabled) 167 return 0; 168 169 if (p->backlight) { 170 p->backlight->props.power = FB_BLANK_POWERDOWN; 171 p->backlight->props.state |= BL_CORE_FBBLANK; 172 backlight_update_status(p->backlight); 173 } 174 175 if (p->desc->delay.disable) 176 msleep(p->desc->delay.disable); 177 178 p->enabled = false; 179 180 return 0; 181 } 182 183 static int panel_simple_unprepare(struct drm_panel *panel) 184 { 185 struct panel_simple *p = to_panel_simple(panel); 186 187 if (!p->prepared) 188 return 0; 189 190 gpiod_set_value_cansleep(p->enable_gpio, 0); 191 192 regulator_disable(p->supply); 193 194 if (p->desc->delay.unprepare) 195 msleep(p->desc->delay.unprepare); 196 197 p->prepared = false; 198 199 return 0; 200 } 201 202 static int panel_simple_prepare(struct drm_panel *panel) 203 { 204 struct panel_simple *p = to_panel_simple(panel); 205 int err; 206 207 if (p->prepared) 208 return 0; 209 210 err = regulator_enable(p->supply); 211 if (err < 0) { 212 dev_err(panel->dev, "failed to enable supply: %d\n", err); 213 return err; 214 } 215 216 gpiod_set_value_cansleep(p->enable_gpio, 1); 217 218 if (p->desc->delay.prepare) 219 msleep(p->desc->delay.prepare); 220 221 p->prepared = true; 222 223 return 0; 224 } 225 226 static int panel_simple_enable(struct drm_panel *panel) 227 { 228 struct panel_simple *p = to_panel_simple(panel); 229 230 if (p->enabled) 231 return 0; 232 233 if (p->desc->delay.enable) 234 msleep(p->desc->delay.enable); 235 236 if (p->backlight) { 237 p->backlight->props.state &= ~BL_CORE_FBBLANK; 238 p->backlight->props.power = FB_BLANK_UNBLANK; 239 backlight_update_status(p->backlight); 240 } 241 242 p->enabled = true; 243 244 return 0; 245 } 246 247 static int panel_simple_get_modes(struct drm_panel *panel) 248 { 249 struct panel_simple *p = to_panel_simple(panel); 250 int num = 0; 251 252 /* probe EDID if a DDC bus is available */ 253 if (p->ddc) { 254 struct edid *edid = drm_get_edid(panel->connector, p->ddc); 255 drm_connector_update_edid_property(panel->connector, edid); 256 if (edid) { 257 num += drm_add_edid_modes(panel->connector, edid); 258 kfree(edid); 259 } 260 } 261 262 /* add hard-coded panel modes */ 263 num += panel_simple_get_fixed_modes(p); 264 265 return num; 266 } 267 268 static int panel_simple_get_timings(struct drm_panel *panel, 269 unsigned int num_timings, 270 struct display_timing *timings) 271 { 272 struct panel_simple *p = to_panel_simple(panel); 273 unsigned int i; 274 275 if (p->desc->num_timings < num_timings) 276 num_timings = p->desc->num_timings; 277 278 if (timings) 279 for (i = 0; i < num_timings; i++) 280 timings[i] = p->desc->timings[i]; 281 282 return p->desc->num_timings; 283 } 284 285 static const struct drm_panel_funcs panel_simple_funcs = { 286 .disable = panel_simple_disable, 287 .unprepare = panel_simple_unprepare, 288 .prepare = panel_simple_prepare, 289 .enable = panel_simple_enable, 290 .get_modes = panel_simple_get_modes, 291 .get_timings = panel_simple_get_timings, 292 }; 293 294 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 295 { 296 struct device_node *backlight, *ddc; 297 struct panel_simple *panel; 298 int err; 299 300 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 301 if (!panel) 302 return -ENOMEM; 303 304 panel->enabled = false; 305 panel->prepared = false; 306 panel->desc = desc; 307 308 panel->supply = devm_regulator_get(dev, "power"); 309 if (IS_ERR(panel->supply)) 310 return PTR_ERR(panel->supply); 311 312 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 313 GPIOD_OUT_LOW); 314 if (IS_ERR(panel->enable_gpio)) { 315 err = PTR_ERR(panel->enable_gpio); 316 if (err != -EPROBE_DEFER) 317 dev_err(dev, "failed to request GPIO: %d\n", err); 318 return err; 319 } 320 321 backlight = of_parse_phandle(dev->of_node, "backlight", 0); 322 if (backlight) { 323 panel->backlight = of_find_backlight_by_node(backlight); 324 of_node_put(backlight); 325 326 if (!panel->backlight) 327 return -EPROBE_DEFER; 328 } 329 330 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 331 if (ddc) { 332 panel->ddc = of_find_i2c_adapter_by_node(ddc); 333 of_node_put(ddc); 334 335 if (!panel->ddc) { 336 err = -EPROBE_DEFER; 337 goto free_backlight; 338 } 339 } 340 341 drm_panel_init(&panel->base); 342 panel->base.dev = dev; 343 panel->base.funcs = &panel_simple_funcs; 344 345 err = drm_panel_add(&panel->base); 346 if (err < 0) 347 goto free_ddc; 348 349 dev_set_drvdata(dev, panel); 350 351 return 0; 352 353 free_ddc: 354 if (panel->ddc) 355 put_device(&panel->ddc->dev); 356 free_backlight: 357 if (panel->backlight) 358 put_device(&panel->backlight->dev); 359 360 return err; 361 } 362 363 static int panel_simple_remove(struct device *dev) 364 { 365 struct panel_simple *panel = dev_get_drvdata(dev); 366 367 drm_panel_remove(&panel->base); 368 369 panel_simple_disable(&panel->base); 370 panel_simple_unprepare(&panel->base); 371 372 if (panel->ddc) 373 put_device(&panel->ddc->dev); 374 375 if (panel->backlight) 376 put_device(&panel->backlight->dev); 377 378 return 0; 379 } 380 381 static void panel_simple_shutdown(struct device *dev) 382 { 383 struct panel_simple *panel = dev_get_drvdata(dev); 384 385 panel_simple_disable(&panel->base); 386 panel_simple_unprepare(&panel->base); 387 } 388 389 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 390 .clock = 9000, 391 .hdisplay = 480, 392 .hsync_start = 480 + 2, 393 .hsync_end = 480 + 2 + 41, 394 .htotal = 480 + 2 + 41 + 2, 395 .vdisplay = 272, 396 .vsync_start = 272 + 2, 397 .vsync_end = 272 + 2 + 10, 398 .vtotal = 272 + 2 + 10 + 2, 399 .vrefresh = 60, 400 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 401 }; 402 403 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 404 .modes = &ire_am_480272h3tmqw_t01h_mode, 405 .num_modes = 1, 406 .bpc = 8, 407 .size = { 408 .width = 105, 409 .height = 67, 410 }, 411 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 412 }; 413 414 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 415 .clock = 33333, 416 .hdisplay = 800, 417 .hsync_start = 800 + 0, 418 .hsync_end = 800 + 0 + 255, 419 .htotal = 800 + 0 + 255 + 0, 420 .vdisplay = 480, 421 .vsync_start = 480 + 2, 422 .vsync_end = 480 + 2 + 45, 423 .vtotal = 480 + 2 + 45 + 0, 424 .vrefresh = 60, 425 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 426 }; 427 428 static const struct panel_desc ampire_am800480r3tmqwa1h = { 429 .modes = &ire_am800480r3tmqwa1h_mode, 430 .num_modes = 1, 431 .bpc = 6, 432 .size = { 433 .width = 152, 434 .height = 91, 435 }, 436 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 437 }; 438 439 static const struct drm_display_mode auo_b101aw03_mode = { 440 .clock = 51450, 441 .hdisplay = 1024, 442 .hsync_start = 1024 + 156, 443 .hsync_end = 1024 + 156 + 8, 444 .htotal = 1024 + 156 + 8 + 156, 445 .vdisplay = 600, 446 .vsync_start = 600 + 16, 447 .vsync_end = 600 + 16 + 6, 448 .vtotal = 600 + 16 + 6 + 16, 449 .vrefresh = 60, 450 }; 451 452 static const struct panel_desc auo_b101aw03 = { 453 .modes = &auo_b101aw03_mode, 454 .num_modes = 1, 455 .bpc = 6, 456 .size = { 457 .width = 223, 458 .height = 125, 459 }, 460 }; 461 462 static const struct drm_display_mode auo_b101ean01_mode = { 463 .clock = 72500, 464 .hdisplay = 1280, 465 .hsync_start = 1280 + 119, 466 .hsync_end = 1280 + 119 + 32, 467 .htotal = 1280 + 119 + 32 + 21, 468 .vdisplay = 800, 469 .vsync_start = 800 + 4, 470 .vsync_end = 800 + 4 + 20, 471 .vtotal = 800 + 4 + 20 + 8, 472 .vrefresh = 60, 473 }; 474 475 static const struct panel_desc auo_b101ean01 = { 476 .modes = &auo_b101ean01_mode, 477 .num_modes = 1, 478 .bpc = 6, 479 .size = { 480 .width = 217, 481 .height = 136, 482 }, 483 }; 484 485 static const struct drm_display_mode auo_b101xtn01_mode = { 486 .clock = 72000, 487 .hdisplay = 1366, 488 .hsync_start = 1366 + 20, 489 .hsync_end = 1366 + 20 + 70, 490 .htotal = 1366 + 20 + 70, 491 .vdisplay = 768, 492 .vsync_start = 768 + 14, 493 .vsync_end = 768 + 14 + 42, 494 .vtotal = 768 + 14 + 42, 495 .vrefresh = 60, 496 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 497 }; 498 499 static const struct panel_desc auo_b101xtn01 = { 500 .modes = &auo_b101xtn01_mode, 501 .num_modes = 1, 502 .bpc = 6, 503 .size = { 504 .width = 223, 505 .height = 125, 506 }, 507 }; 508 509 static const struct drm_display_mode auo_b116xw03_mode = { 510 .clock = 70589, 511 .hdisplay = 1366, 512 .hsync_start = 1366 + 40, 513 .hsync_end = 1366 + 40 + 40, 514 .htotal = 1366 + 40 + 40 + 32, 515 .vdisplay = 768, 516 .vsync_start = 768 + 10, 517 .vsync_end = 768 + 10 + 12, 518 .vtotal = 768 + 10 + 12 + 6, 519 .vrefresh = 60, 520 }; 521 522 static const struct panel_desc auo_b116xw03 = { 523 .modes = &auo_b116xw03_mode, 524 .num_modes = 1, 525 .bpc = 6, 526 .size = { 527 .width = 256, 528 .height = 144, 529 }, 530 }; 531 532 static const struct drm_display_mode auo_b133xtn01_mode = { 533 .clock = 69500, 534 .hdisplay = 1366, 535 .hsync_start = 1366 + 48, 536 .hsync_end = 1366 + 48 + 32, 537 .htotal = 1366 + 48 + 32 + 20, 538 .vdisplay = 768, 539 .vsync_start = 768 + 3, 540 .vsync_end = 768 + 3 + 6, 541 .vtotal = 768 + 3 + 6 + 13, 542 .vrefresh = 60, 543 }; 544 545 static const struct panel_desc auo_b133xtn01 = { 546 .modes = &auo_b133xtn01_mode, 547 .num_modes = 1, 548 .bpc = 6, 549 .size = { 550 .width = 293, 551 .height = 165, 552 }, 553 }; 554 555 static const struct drm_display_mode auo_b133htn01_mode = { 556 .clock = 150660, 557 .hdisplay = 1920, 558 .hsync_start = 1920 + 172, 559 .hsync_end = 1920 + 172 + 80, 560 .htotal = 1920 + 172 + 80 + 60, 561 .vdisplay = 1080, 562 .vsync_start = 1080 + 25, 563 .vsync_end = 1080 + 25 + 10, 564 .vtotal = 1080 + 25 + 10 + 10, 565 .vrefresh = 60, 566 }; 567 568 static const struct panel_desc auo_b133htn01 = { 569 .modes = &auo_b133htn01_mode, 570 .num_modes = 1, 571 .bpc = 6, 572 .size = { 573 .width = 293, 574 .height = 165, 575 }, 576 .delay = { 577 .prepare = 105, 578 .enable = 20, 579 .unprepare = 50, 580 }, 581 }; 582 583 static const struct display_timing auo_g070vvn01_timings = { 584 .pixelclock = { 33300000, 34209000, 45000000 }, 585 .hactive = { 800, 800, 800 }, 586 .hfront_porch = { 20, 40, 200 }, 587 .hback_porch = { 87, 40, 1 }, 588 .hsync_len = { 1, 48, 87 }, 589 .vactive = { 480, 480, 480 }, 590 .vfront_porch = { 5, 13, 200 }, 591 .vback_porch = { 31, 31, 29 }, 592 .vsync_len = { 1, 1, 3 }, 593 }; 594 595 static const struct panel_desc auo_g070vvn01 = { 596 .timings = &auo_g070vvn01_timings, 597 .num_timings = 1, 598 .bpc = 8, 599 .size = { 600 .width = 152, 601 .height = 91, 602 }, 603 .delay = { 604 .prepare = 200, 605 .enable = 50, 606 .disable = 50, 607 .unprepare = 1000, 608 }, 609 }; 610 611 static const struct drm_display_mode auo_g104sn02_mode = { 612 .clock = 40000, 613 .hdisplay = 800, 614 .hsync_start = 800 + 40, 615 .hsync_end = 800 + 40 + 216, 616 .htotal = 800 + 40 + 216 + 128, 617 .vdisplay = 600, 618 .vsync_start = 600 + 10, 619 .vsync_end = 600 + 10 + 35, 620 .vtotal = 600 + 10 + 35 + 2, 621 .vrefresh = 60, 622 }; 623 624 static const struct panel_desc auo_g104sn02 = { 625 .modes = &auo_g104sn02_mode, 626 .num_modes = 1, 627 .bpc = 8, 628 .size = { 629 .width = 211, 630 .height = 158, 631 }, 632 }; 633 634 static const struct display_timing auo_g133han01_timings = { 635 .pixelclock = { 134000000, 141200000, 149000000 }, 636 .hactive = { 1920, 1920, 1920 }, 637 .hfront_porch = { 39, 58, 77 }, 638 .hback_porch = { 59, 88, 117 }, 639 .hsync_len = { 28, 42, 56 }, 640 .vactive = { 1080, 1080, 1080 }, 641 .vfront_porch = { 3, 8, 11 }, 642 .vback_porch = { 5, 14, 19 }, 643 .vsync_len = { 4, 14, 19 }, 644 }; 645 646 static const struct panel_desc auo_g133han01 = { 647 .timings = &auo_g133han01_timings, 648 .num_timings = 1, 649 .bpc = 8, 650 .size = { 651 .width = 293, 652 .height = 165, 653 }, 654 .delay = { 655 .prepare = 200, 656 .enable = 50, 657 .disable = 50, 658 .unprepare = 1000, 659 }, 660 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 661 }; 662 663 static const struct display_timing auo_g185han01_timings = { 664 .pixelclock = { 120000000, 144000000, 175000000 }, 665 .hactive = { 1920, 1920, 1920 }, 666 .hfront_porch = { 18, 60, 74 }, 667 .hback_porch = { 12, 44, 54 }, 668 .hsync_len = { 10, 24, 32 }, 669 .vactive = { 1080, 1080, 1080 }, 670 .vfront_porch = { 6, 10, 40 }, 671 .vback_porch = { 2, 5, 20 }, 672 .vsync_len = { 2, 5, 20 }, 673 }; 674 675 static const struct panel_desc auo_g185han01 = { 676 .timings = &auo_g185han01_timings, 677 .num_timings = 1, 678 .bpc = 8, 679 .size = { 680 .width = 409, 681 .height = 230, 682 }, 683 .delay = { 684 .prepare = 50, 685 .enable = 200, 686 .disable = 110, 687 .unprepare = 1000, 688 }, 689 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 690 }; 691 692 static const struct display_timing auo_p320hvn03_timings = { 693 .pixelclock = { 106000000, 148500000, 164000000 }, 694 .hactive = { 1920, 1920, 1920 }, 695 .hfront_porch = { 25, 50, 130 }, 696 .hback_porch = { 25, 50, 130 }, 697 .hsync_len = { 20, 40, 105 }, 698 .vactive = { 1080, 1080, 1080 }, 699 .vfront_porch = { 8, 17, 150 }, 700 .vback_porch = { 8, 17, 150 }, 701 .vsync_len = { 4, 11, 100 }, 702 }; 703 704 static const struct panel_desc auo_p320hvn03 = { 705 .timings = &auo_p320hvn03_timings, 706 .num_timings = 1, 707 .bpc = 8, 708 .size = { 709 .width = 698, 710 .height = 393, 711 }, 712 .delay = { 713 .prepare = 1, 714 .enable = 450, 715 .unprepare = 500, 716 }, 717 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 718 }; 719 720 static const struct drm_display_mode auo_t215hvn01_mode = { 721 .clock = 148800, 722 .hdisplay = 1920, 723 .hsync_start = 1920 + 88, 724 .hsync_end = 1920 + 88 + 44, 725 .htotal = 1920 + 88 + 44 + 148, 726 .vdisplay = 1080, 727 .vsync_start = 1080 + 4, 728 .vsync_end = 1080 + 4 + 5, 729 .vtotal = 1080 + 4 + 5 + 36, 730 .vrefresh = 60, 731 }; 732 733 static const struct panel_desc auo_t215hvn01 = { 734 .modes = &auo_t215hvn01_mode, 735 .num_modes = 1, 736 .bpc = 8, 737 .size = { 738 .width = 430, 739 .height = 270, 740 }, 741 .delay = { 742 .disable = 5, 743 .unprepare = 1000, 744 } 745 }; 746 747 static const struct drm_display_mode avic_tm070ddh03_mode = { 748 .clock = 51200, 749 .hdisplay = 1024, 750 .hsync_start = 1024 + 160, 751 .hsync_end = 1024 + 160 + 4, 752 .htotal = 1024 + 160 + 4 + 156, 753 .vdisplay = 600, 754 .vsync_start = 600 + 17, 755 .vsync_end = 600 + 17 + 1, 756 .vtotal = 600 + 17 + 1 + 17, 757 .vrefresh = 60, 758 }; 759 760 static const struct panel_desc avic_tm070ddh03 = { 761 .modes = &avic_tm070ddh03_mode, 762 .num_modes = 1, 763 .bpc = 8, 764 .size = { 765 .width = 154, 766 .height = 90, 767 }, 768 .delay = { 769 .prepare = 20, 770 .enable = 200, 771 .disable = 200, 772 }, 773 }; 774 775 static const struct drm_display_mode boe_hv070wsa_mode = { 776 .clock = 40800, 777 .hdisplay = 1024, 778 .hsync_start = 1024 + 90, 779 .hsync_end = 1024 + 90 + 90, 780 .htotal = 1024 + 90 + 90 + 90, 781 .vdisplay = 600, 782 .vsync_start = 600 + 3, 783 .vsync_end = 600 + 3 + 4, 784 .vtotal = 600 + 3 + 4 + 3, 785 .vrefresh = 60, 786 }; 787 788 static const struct panel_desc boe_hv070wsa = { 789 .modes = &boe_hv070wsa_mode, 790 .num_modes = 1, 791 .size = { 792 .width = 154, 793 .height = 90, 794 }, 795 }; 796 797 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 798 { 799 .clock = 71900, 800 .hdisplay = 1280, 801 .hsync_start = 1280 + 48, 802 .hsync_end = 1280 + 48 + 32, 803 .htotal = 1280 + 48 + 32 + 80, 804 .vdisplay = 800, 805 .vsync_start = 800 + 3, 806 .vsync_end = 800 + 3 + 5, 807 .vtotal = 800 + 3 + 5 + 24, 808 .vrefresh = 60, 809 }, 810 { 811 .clock = 57500, 812 .hdisplay = 1280, 813 .hsync_start = 1280 + 48, 814 .hsync_end = 1280 + 48 + 32, 815 .htotal = 1280 + 48 + 32 + 80, 816 .vdisplay = 800, 817 .vsync_start = 800 + 3, 818 .vsync_end = 800 + 3 + 5, 819 .vtotal = 800 + 3 + 5 + 24, 820 .vrefresh = 48, 821 }, 822 }; 823 824 static const struct panel_desc boe_nv101wxmn51 = { 825 .modes = boe_nv101wxmn51_modes, 826 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 827 .bpc = 8, 828 .size = { 829 .width = 217, 830 .height = 136, 831 }, 832 .delay = { 833 .prepare = 210, 834 .enable = 50, 835 .unprepare = 160, 836 }, 837 }; 838 839 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 840 .clock = 66770, 841 .hdisplay = 800, 842 .hsync_start = 800 + 49, 843 .hsync_end = 800 + 49 + 33, 844 .htotal = 800 + 49 + 33 + 17, 845 .vdisplay = 1280, 846 .vsync_start = 1280 + 1, 847 .vsync_end = 1280 + 1 + 7, 848 .vtotal = 1280 + 1 + 7 + 15, 849 .vrefresh = 60, 850 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 851 }; 852 853 static const struct panel_desc chunghwa_claa070wp03xg = { 854 .modes = &chunghwa_claa070wp03xg_mode, 855 .num_modes = 1, 856 .bpc = 6, 857 .size = { 858 .width = 94, 859 .height = 150, 860 }, 861 }; 862 863 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 864 .clock = 72070, 865 .hdisplay = 1366, 866 .hsync_start = 1366 + 58, 867 .hsync_end = 1366 + 58 + 58, 868 .htotal = 1366 + 58 + 58 + 58, 869 .vdisplay = 768, 870 .vsync_start = 768 + 4, 871 .vsync_end = 768 + 4 + 4, 872 .vtotal = 768 + 4 + 4 + 4, 873 .vrefresh = 60, 874 }; 875 876 static const struct panel_desc chunghwa_claa101wa01a = { 877 .modes = &chunghwa_claa101wa01a_mode, 878 .num_modes = 1, 879 .bpc = 6, 880 .size = { 881 .width = 220, 882 .height = 120, 883 }, 884 }; 885 886 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 887 .clock = 69300, 888 .hdisplay = 1366, 889 .hsync_start = 1366 + 48, 890 .hsync_end = 1366 + 48 + 32, 891 .htotal = 1366 + 48 + 32 + 20, 892 .vdisplay = 768, 893 .vsync_start = 768 + 16, 894 .vsync_end = 768 + 16 + 8, 895 .vtotal = 768 + 16 + 8 + 16, 896 .vrefresh = 60, 897 }; 898 899 static const struct panel_desc chunghwa_claa101wb01 = { 900 .modes = &chunghwa_claa101wb01_mode, 901 .num_modes = 1, 902 .bpc = 6, 903 .size = { 904 .width = 223, 905 .height = 125, 906 }, 907 }; 908 909 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 910 .clock = 33260, 911 .hdisplay = 800, 912 .hsync_start = 800 + 40, 913 .hsync_end = 800 + 40 + 128, 914 .htotal = 800 + 40 + 128 + 88, 915 .vdisplay = 480, 916 .vsync_start = 480 + 10, 917 .vsync_end = 480 + 10 + 2, 918 .vtotal = 480 + 10 + 2 + 33, 919 .vrefresh = 60, 920 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 921 }; 922 923 static const struct panel_desc dataimage_scf0700c48ggu18 = { 924 .modes = &dataimage_scf0700c48ggu18_mode, 925 .num_modes = 1, 926 .bpc = 8, 927 .size = { 928 .width = 152, 929 .height = 91, 930 }, 931 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 932 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 933 }; 934 935 static const struct display_timing dlc_dlc0700yzg_1_timing = { 936 .pixelclock = { 45000000, 51200000, 57000000 }, 937 .hactive = { 1024, 1024, 1024 }, 938 .hfront_porch = { 100, 106, 113 }, 939 .hback_porch = { 100, 106, 113 }, 940 .hsync_len = { 100, 108, 114 }, 941 .vactive = { 600, 600, 600 }, 942 .vfront_porch = { 8, 11, 15 }, 943 .vback_porch = { 8, 11, 15 }, 944 .vsync_len = { 9, 13, 15 }, 945 .flags = DISPLAY_FLAGS_DE_HIGH, 946 }; 947 948 static const struct panel_desc dlc_dlc0700yzg_1 = { 949 .timings = &dlc_dlc0700yzg_1_timing, 950 .num_timings = 1, 951 .bpc = 6, 952 .size = { 953 .width = 154, 954 .height = 86, 955 }, 956 .delay = { 957 .prepare = 30, 958 .enable = 200, 959 .disable = 200, 960 }, 961 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 962 }; 963 964 static const struct drm_display_mode edt_et057090dhu_mode = { 965 .clock = 25175, 966 .hdisplay = 640, 967 .hsync_start = 640 + 16, 968 .hsync_end = 640 + 16 + 30, 969 .htotal = 640 + 16 + 30 + 114, 970 .vdisplay = 480, 971 .vsync_start = 480 + 10, 972 .vsync_end = 480 + 10 + 3, 973 .vtotal = 480 + 10 + 3 + 32, 974 .vrefresh = 60, 975 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 976 }; 977 978 static const struct panel_desc edt_et057090dhu = { 979 .modes = &edt_et057090dhu_mode, 980 .num_modes = 1, 981 .bpc = 6, 982 .size = { 983 .width = 115, 984 .height = 86, 985 }, 986 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 987 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 988 }; 989 990 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 991 .clock = 33260, 992 .hdisplay = 800, 993 .hsync_start = 800 + 40, 994 .hsync_end = 800 + 40 + 128, 995 .htotal = 800 + 40 + 128 + 88, 996 .vdisplay = 480, 997 .vsync_start = 480 + 10, 998 .vsync_end = 480 + 10 + 2, 999 .vtotal = 480 + 10 + 2 + 33, 1000 .vrefresh = 60, 1001 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1002 }; 1003 1004 static const struct panel_desc edt_etm0700g0dh6 = { 1005 .modes = &edt_etm0700g0dh6_mode, 1006 .num_modes = 1, 1007 .bpc = 6, 1008 .size = { 1009 .width = 152, 1010 .height = 91, 1011 }, 1012 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1013 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE, 1014 }; 1015 1016 static const struct panel_desc edt_etm0700g0bdh6 = { 1017 .modes = &edt_etm0700g0dh6_mode, 1018 .num_modes = 1, 1019 .bpc = 6, 1020 .size = { 1021 .width = 152, 1022 .height = 91, 1023 }, 1024 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1025 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1026 }; 1027 1028 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1029 .clock = 32260, 1030 .hdisplay = 800, 1031 .hsync_start = 800 + 168, 1032 .hsync_end = 800 + 168 + 64, 1033 .htotal = 800 + 168 + 64 + 88, 1034 .vdisplay = 480, 1035 .vsync_start = 480 + 37, 1036 .vsync_end = 480 + 37 + 2, 1037 .vtotal = 480 + 37 + 2 + 8, 1038 .vrefresh = 60, 1039 }; 1040 1041 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1042 .modes = &foxlink_fl500wvr00_a0t_mode, 1043 .num_modes = 1, 1044 .bpc = 8, 1045 .size = { 1046 .width = 108, 1047 .height = 65, 1048 }, 1049 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1050 }; 1051 1052 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1053 .clock = 9000, 1054 .hdisplay = 480, 1055 .hsync_start = 480 + 5, 1056 .hsync_end = 480 + 5 + 1, 1057 .htotal = 480 + 5 + 1 + 40, 1058 .vdisplay = 272, 1059 .vsync_start = 272 + 8, 1060 .vsync_end = 272 + 8 + 1, 1061 .vtotal = 272 + 8 + 1 + 8, 1062 .vrefresh = 60, 1063 }; 1064 1065 static const struct panel_desc giantplus_gpg482739qs5 = { 1066 .modes = &giantplus_gpg482739qs5_mode, 1067 .num_modes = 1, 1068 .bpc = 8, 1069 .size = { 1070 .width = 95, 1071 .height = 54, 1072 }, 1073 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1074 }; 1075 1076 static const struct display_timing hannstar_hsd070pww1_timing = { 1077 .pixelclock = { 64300000, 71100000, 82000000 }, 1078 .hactive = { 1280, 1280, 1280 }, 1079 .hfront_porch = { 1, 1, 10 }, 1080 .hback_porch = { 1, 1, 10 }, 1081 /* 1082 * According to the data sheet, the minimum horizontal blanking interval 1083 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1084 * minimum working horizontal blanking interval to be 60 clocks. 1085 */ 1086 .hsync_len = { 58, 158, 661 }, 1087 .vactive = { 800, 800, 800 }, 1088 .vfront_porch = { 1, 1, 10 }, 1089 .vback_porch = { 1, 1, 10 }, 1090 .vsync_len = { 1, 21, 203 }, 1091 .flags = DISPLAY_FLAGS_DE_HIGH, 1092 }; 1093 1094 static const struct panel_desc hannstar_hsd070pww1 = { 1095 .timings = &hannstar_hsd070pww1_timing, 1096 .num_timings = 1, 1097 .bpc = 6, 1098 .size = { 1099 .width = 151, 1100 .height = 94, 1101 }, 1102 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1103 }; 1104 1105 static const struct display_timing hannstar_hsd100pxn1_timing = { 1106 .pixelclock = { 55000000, 65000000, 75000000 }, 1107 .hactive = { 1024, 1024, 1024 }, 1108 .hfront_porch = { 40, 40, 40 }, 1109 .hback_porch = { 220, 220, 220 }, 1110 .hsync_len = { 20, 60, 100 }, 1111 .vactive = { 768, 768, 768 }, 1112 .vfront_porch = { 7, 7, 7 }, 1113 .vback_porch = { 21, 21, 21 }, 1114 .vsync_len = { 10, 10, 10 }, 1115 .flags = DISPLAY_FLAGS_DE_HIGH, 1116 }; 1117 1118 static const struct panel_desc hannstar_hsd100pxn1 = { 1119 .timings = &hannstar_hsd100pxn1_timing, 1120 .num_timings = 1, 1121 .bpc = 6, 1122 .size = { 1123 .width = 203, 1124 .height = 152, 1125 }, 1126 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1127 }; 1128 1129 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1130 .clock = 33333, 1131 .hdisplay = 800, 1132 .hsync_start = 800 + 85, 1133 .hsync_end = 800 + 85 + 86, 1134 .htotal = 800 + 85 + 86 + 85, 1135 .vdisplay = 480, 1136 .vsync_start = 480 + 16, 1137 .vsync_end = 480 + 16 + 13, 1138 .vtotal = 480 + 16 + 13 + 16, 1139 .vrefresh = 60, 1140 }; 1141 1142 static const struct panel_desc hitachi_tx23d38vm0caa = { 1143 .modes = &hitachi_tx23d38vm0caa_mode, 1144 .num_modes = 1, 1145 .bpc = 6, 1146 .size = { 1147 .width = 195, 1148 .height = 117, 1149 }, 1150 .delay = { 1151 .enable = 160, 1152 .disable = 160, 1153 }, 1154 }; 1155 1156 static const struct drm_display_mode innolux_at043tn24_mode = { 1157 .clock = 9000, 1158 .hdisplay = 480, 1159 .hsync_start = 480 + 2, 1160 .hsync_end = 480 + 2 + 41, 1161 .htotal = 480 + 2 + 41 + 2, 1162 .vdisplay = 272, 1163 .vsync_start = 272 + 2, 1164 .vsync_end = 272 + 2 + 10, 1165 .vtotal = 272 + 2 + 10 + 2, 1166 .vrefresh = 60, 1167 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1168 }; 1169 1170 static const struct panel_desc innolux_at043tn24 = { 1171 .modes = &innolux_at043tn24_mode, 1172 .num_modes = 1, 1173 .bpc = 8, 1174 .size = { 1175 .width = 95, 1176 .height = 54, 1177 }, 1178 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1179 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1180 }; 1181 1182 static const struct drm_display_mode innolux_at070tn92_mode = { 1183 .clock = 33333, 1184 .hdisplay = 800, 1185 .hsync_start = 800 + 210, 1186 .hsync_end = 800 + 210 + 20, 1187 .htotal = 800 + 210 + 20 + 46, 1188 .vdisplay = 480, 1189 .vsync_start = 480 + 22, 1190 .vsync_end = 480 + 22 + 10, 1191 .vtotal = 480 + 22 + 23 + 10, 1192 .vrefresh = 60, 1193 }; 1194 1195 static const struct panel_desc innolux_at070tn92 = { 1196 .modes = &innolux_at070tn92_mode, 1197 .num_modes = 1, 1198 .size = { 1199 .width = 154, 1200 .height = 86, 1201 }, 1202 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1203 }; 1204 1205 static const struct display_timing innolux_g070y2_l01_timing = { 1206 .pixelclock = { 28000000, 29500000, 32000000 }, 1207 .hactive = { 800, 800, 800 }, 1208 .hfront_porch = { 61, 91, 141 }, 1209 .hback_porch = { 60, 90, 140 }, 1210 .hsync_len = { 12, 12, 12 }, 1211 .vactive = { 480, 480, 480 }, 1212 .vfront_porch = { 4, 9, 30 }, 1213 .vback_porch = { 4, 8, 28 }, 1214 .vsync_len = { 2, 2, 2 }, 1215 .flags = DISPLAY_FLAGS_DE_HIGH, 1216 }; 1217 1218 static const struct panel_desc innolux_g070y2_l01 = { 1219 .timings = &innolux_g070y2_l01_timing, 1220 .num_timings = 1, 1221 .bpc = 6, 1222 .size = { 1223 .width = 152, 1224 .height = 91, 1225 }, 1226 .delay = { 1227 .prepare = 10, 1228 .enable = 100, 1229 .disable = 100, 1230 .unprepare = 800, 1231 }, 1232 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1233 }; 1234 1235 static const struct display_timing innolux_g101ice_l01_timing = { 1236 .pixelclock = { 60400000, 71100000, 74700000 }, 1237 .hactive = { 1280, 1280, 1280 }, 1238 .hfront_porch = { 41, 80, 100 }, 1239 .hback_porch = { 40, 79, 99 }, 1240 .hsync_len = { 1, 1, 1 }, 1241 .vactive = { 800, 800, 800 }, 1242 .vfront_porch = { 5, 11, 14 }, 1243 .vback_porch = { 4, 11, 14 }, 1244 .vsync_len = { 1, 1, 1 }, 1245 .flags = DISPLAY_FLAGS_DE_HIGH, 1246 }; 1247 1248 static const struct panel_desc innolux_g101ice_l01 = { 1249 .timings = &innolux_g101ice_l01_timing, 1250 .num_timings = 1, 1251 .bpc = 8, 1252 .size = { 1253 .width = 217, 1254 .height = 135, 1255 }, 1256 .delay = { 1257 .enable = 200, 1258 .disable = 200, 1259 }, 1260 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1261 }; 1262 1263 static const struct display_timing innolux_g121i1_l01_timing = { 1264 .pixelclock = { 67450000, 71000000, 74550000 }, 1265 .hactive = { 1280, 1280, 1280 }, 1266 .hfront_porch = { 40, 80, 160 }, 1267 .hback_porch = { 39, 79, 159 }, 1268 .hsync_len = { 1, 1, 1 }, 1269 .vactive = { 800, 800, 800 }, 1270 .vfront_porch = { 5, 11, 100 }, 1271 .vback_porch = { 4, 11, 99 }, 1272 .vsync_len = { 1, 1, 1 }, 1273 }; 1274 1275 static const struct panel_desc innolux_g121i1_l01 = { 1276 .timings = &innolux_g121i1_l01_timing, 1277 .num_timings = 1, 1278 .bpc = 6, 1279 .size = { 1280 .width = 261, 1281 .height = 163, 1282 }, 1283 .delay = { 1284 .enable = 200, 1285 .disable = 20, 1286 }, 1287 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1288 }; 1289 1290 static const struct drm_display_mode innolux_g121x1_l03_mode = { 1291 .clock = 65000, 1292 .hdisplay = 1024, 1293 .hsync_start = 1024 + 0, 1294 .hsync_end = 1024 + 1, 1295 .htotal = 1024 + 0 + 1 + 320, 1296 .vdisplay = 768, 1297 .vsync_start = 768 + 38, 1298 .vsync_end = 768 + 38 + 1, 1299 .vtotal = 768 + 38 + 1 + 0, 1300 .vrefresh = 60, 1301 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1302 }; 1303 1304 static const struct panel_desc innolux_g121x1_l03 = { 1305 .modes = &innolux_g121x1_l03_mode, 1306 .num_modes = 1, 1307 .bpc = 6, 1308 .size = { 1309 .width = 246, 1310 .height = 185, 1311 }, 1312 .delay = { 1313 .enable = 200, 1314 .unprepare = 200, 1315 .disable = 400, 1316 }, 1317 }; 1318 1319 static const struct drm_display_mode innolux_n116bge_mode = { 1320 .clock = 76420, 1321 .hdisplay = 1366, 1322 .hsync_start = 1366 + 136, 1323 .hsync_end = 1366 + 136 + 30, 1324 .htotal = 1366 + 136 + 30 + 60, 1325 .vdisplay = 768, 1326 .vsync_start = 768 + 8, 1327 .vsync_end = 768 + 8 + 12, 1328 .vtotal = 768 + 8 + 12 + 12, 1329 .vrefresh = 60, 1330 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1331 }; 1332 1333 static const struct panel_desc innolux_n116bge = { 1334 .modes = &innolux_n116bge_mode, 1335 .num_modes = 1, 1336 .bpc = 6, 1337 .size = { 1338 .width = 256, 1339 .height = 144, 1340 }, 1341 }; 1342 1343 static const struct drm_display_mode innolux_n156bge_l21_mode = { 1344 .clock = 69300, 1345 .hdisplay = 1366, 1346 .hsync_start = 1366 + 16, 1347 .hsync_end = 1366 + 16 + 34, 1348 .htotal = 1366 + 16 + 34 + 50, 1349 .vdisplay = 768, 1350 .vsync_start = 768 + 2, 1351 .vsync_end = 768 + 2 + 6, 1352 .vtotal = 768 + 2 + 6 + 12, 1353 .vrefresh = 60, 1354 }; 1355 1356 static const struct panel_desc innolux_n156bge_l21 = { 1357 .modes = &innolux_n156bge_l21_mode, 1358 .num_modes = 1, 1359 .bpc = 6, 1360 .size = { 1361 .width = 344, 1362 .height = 193, 1363 }, 1364 }; 1365 1366 static const struct drm_display_mode innolux_tv123wam_mode = { 1367 .clock = 206016, 1368 .hdisplay = 2160, 1369 .hsync_start = 2160 + 48, 1370 .hsync_end = 2160 + 48 + 32, 1371 .htotal = 2160 + 48 + 32 + 80, 1372 .vdisplay = 1440, 1373 .vsync_start = 1440 + 3, 1374 .vsync_end = 1440 + 3 + 10, 1375 .vtotal = 1440 + 3 + 10 + 27, 1376 .vrefresh = 60, 1377 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 1378 }; 1379 1380 static const struct panel_desc innolux_tv123wam = { 1381 .modes = &innolux_tv123wam_mode, 1382 .num_modes = 1, 1383 .bpc = 8, 1384 .size = { 1385 .width = 259, 1386 .height = 173, 1387 }, 1388 }; 1389 1390 static const struct drm_display_mode innolux_zj070na_01p_mode = { 1391 .clock = 51501, 1392 .hdisplay = 1024, 1393 .hsync_start = 1024 + 128, 1394 .hsync_end = 1024 + 128 + 64, 1395 .htotal = 1024 + 128 + 64 + 128, 1396 .vdisplay = 600, 1397 .vsync_start = 600 + 16, 1398 .vsync_end = 600 + 16 + 4, 1399 .vtotal = 600 + 16 + 4 + 16, 1400 .vrefresh = 60, 1401 }; 1402 1403 static const struct panel_desc innolux_zj070na_01p = { 1404 .modes = &innolux_zj070na_01p_mode, 1405 .num_modes = 1, 1406 .bpc = 6, 1407 .size = { 1408 .width = 154, 1409 .height = 90, 1410 }, 1411 }; 1412 1413 static const struct display_timing koe_tx31d200vm0baa_timing = { 1414 .pixelclock = { 39600000, 43200000, 48000000 }, 1415 .hactive = { 1280, 1280, 1280 }, 1416 .hfront_porch = { 16, 36, 56 }, 1417 .hback_porch = { 16, 36, 56 }, 1418 .hsync_len = { 8, 8, 8 }, 1419 .vactive = { 480, 480, 480 }, 1420 .vfront_porch = { 6, 21, 33 }, 1421 .vback_porch = { 6, 21, 33 }, 1422 .vsync_len = { 8, 8, 8 }, 1423 .flags = DISPLAY_FLAGS_DE_HIGH, 1424 }; 1425 1426 static const struct panel_desc koe_tx31d200vm0baa = { 1427 .timings = &koe_tx31d200vm0baa_timing, 1428 .num_timings = 1, 1429 .bpc = 6, 1430 .size = { 1431 .width = 292, 1432 .height = 109, 1433 }, 1434 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1435 }; 1436 1437 static const struct display_timing kyo_tcg121xglp_timing = { 1438 .pixelclock = { 52000000, 65000000, 71000000 }, 1439 .hactive = { 1024, 1024, 1024 }, 1440 .hfront_porch = { 2, 2, 2 }, 1441 .hback_porch = { 2, 2, 2 }, 1442 .hsync_len = { 86, 124, 244 }, 1443 .vactive = { 768, 768, 768 }, 1444 .vfront_porch = { 2, 2, 2 }, 1445 .vback_porch = { 2, 2, 2 }, 1446 .vsync_len = { 6, 34, 73 }, 1447 .flags = DISPLAY_FLAGS_DE_HIGH, 1448 }; 1449 1450 static const struct panel_desc kyo_tcg121xglp = { 1451 .timings = &kyo_tcg121xglp_timing, 1452 .num_timings = 1, 1453 .bpc = 8, 1454 .size = { 1455 .width = 246, 1456 .height = 184, 1457 }, 1458 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1459 }; 1460 1461 static const struct drm_display_mode lg_lb070wv8_mode = { 1462 .clock = 33246, 1463 .hdisplay = 800, 1464 .hsync_start = 800 + 88, 1465 .hsync_end = 800 + 88 + 80, 1466 .htotal = 800 + 88 + 80 + 88, 1467 .vdisplay = 480, 1468 .vsync_start = 480 + 10, 1469 .vsync_end = 480 + 10 + 25, 1470 .vtotal = 480 + 10 + 25 + 10, 1471 .vrefresh = 60, 1472 }; 1473 1474 static const struct panel_desc lg_lb070wv8 = { 1475 .modes = &lg_lb070wv8_mode, 1476 .num_modes = 1, 1477 .bpc = 16, 1478 .size = { 1479 .width = 151, 1480 .height = 91, 1481 }, 1482 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1483 }; 1484 1485 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 1486 .clock = 200000, 1487 .hdisplay = 1536, 1488 .hsync_start = 1536 + 12, 1489 .hsync_end = 1536 + 12 + 16, 1490 .htotal = 1536 + 12 + 16 + 48, 1491 .vdisplay = 2048, 1492 .vsync_start = 2048 + 8, 1493 .vsync_end = 2048 + 8 + 4, 1494 .vtotal = 2048 + 8 + 4 + 8, 1495 .vrefresh = 60, 1496 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1497 }; 1498 1499 static const struct panel_desc lg_lp079qx1_sp0v = { 1500 .modes = &lg_lp079qx1_sp0v_mode, 1501 .num_modes = 1, 1502 .size = { 1503 .width = 129, 1504 .height = 171, 1505 }, 1506 }; 1507 1508 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 1509 .clock = 205210, 1510 .hdisplay = 2048, 1511 .hsync_start = 2048 + 150, 1512 .hsync_end = 2048 + 150 + 5, 1513 .htotal = 2048 + 150 + 5 + 5, 1514 .vdisplay = 1536, 1515 .vsync_start = 1536 + 3, 1516 .vsync_end = 1536 + 3 + 1, 1517 .vtotal = 1536 + 3 + 1 + 9, 1518 .vrefresh = 60, 1519 }; 1520 1521 static const struct panel_desc lg_lp097qx1_spa1 = { 1522 .modes = &lg_lp097qx1_spa1_mode, 1523 .num_modes = 1, 1524 .size = { 1525 .width = 208, 1526 .height = 147, 1527 }, 1528 }; 1529 1530 static const struct drm_display_mode lg_lp120up1_mode = { 1531 .clock = 162300, 1532 .hdisplay = 1920, 1533 .hsync_start = 1920 + 40, 1534 .hsync_end = 1920 + 40 + 40, 1535 .htotal = 1920 + 40 + 40+ 80, 1536 .vdisplay = 1280, 1537 .vsync_start = 1280 + 4, 1538 .vsync_end = 1280 + 4 + 4, 1539 .vtotal = 1280 + 4 + 4 + 12, 1540 .vrefresh = 60, 1541 }; 1542 1543 static const struct panel_desc lg_lp120up1 = { 1544 .modes = &lg_lp120up1_mode, 1545 .num_modes = 1, 1546 .bpc = 8, 1547 .size = { 1548 .width = 267, 1549 .height = 183, 1550 }, 1551 }; 1552 1553 static const struct drm_display_mode lg_lp129qe_mode = { 1554 .clock = 285250, 1555 .hdisplay = 2560, 1556 .hsync_start = 2560 + 48, 1557 .hsync_end = 2560 + 48 + 32, 1558 .htotal = 2560 + 48 + 32 + 80, 1559 .vdisplay = 1700, 1560 .vsync_start = 1700 + 3, 1561 .vsync_end = 1700 + 3 + 10, 1562 .vtotal = 1700 + 3 + 10 + 36, 1563 .vrefresh = 60, 1564 }; 1565 1566 static const struct panel_desc lg_lp129qe = { 1567 .modes = &lg_lp129qe_mode, 1568 .num_modes = 1, 1569 .bpc = 8, 1570 .size = { 1571 .width = 272, 1572 .height = 181, 1573 }, 1574 }; 1575 1576 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 1577 .clock = 30400, 1578 .hdisplay = 800, 1579 .hsync_start = 800 + 0, 1580 .hsync_end = 800 + 1, 1581 .htotal = 800 + 0 + 1 + 160, 1582 .vdisplay = 480, 1583 .vsync_start = 480 + 0, 1584 .vsync_end = 480 + 48 + 1, 1585 .vtotal = 480 + 48 + 1 + 0, 1586 .vrefresh = 60, 1587 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1588 }; 1589 1590 static const struct panel_desc mitsubishi_aa070mc01 = { 1591 .modes = &mitsubishi_aa070mc01_mode, 1592 .num_modes = 1, 1593 .bpc = 8, 1594 .size = { 1595 .width = 152, 1596 .height = 91, 1597 }, 1598 1599 .delay = { 1600 .enable = 200, 1601 .unprepare = 200, 1602 .disable = 400, 1603 }, 1604 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1605 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1606 }; 1607 1608 static const struct display_timing nec_nl12880bc20_05_timing = { 1609 .pixelclock = { 67000000, 71000000, 75000000 }, 1610 .hactive = { 1280, 1280, 1280 }, 1611 .hfront_porch = { 2, 30, 30 }, 1612 .hback_porch = { 6, 100, 100 }, 1613 .hsync_len = { 2, 30, 30 }, 1614 .vactive = { 800, 800, 800 }, 1615 .vfront_porch = { 5, 5, 5 }, 1616 .vback_porch = { 11, 11, 11 }, 1617 .vsync_len = { 7, 7, 7 }, 1618 }; 1619 1620 static const struct panel_desc nec_nl12880bc20_05 = { 1621 .timings = &nec_nl12880bc20_05_timing, 1622 .num_timings = 1, 1623 .bpc = 8, 1624 .size = { 1625 .width = 261, 1626 .height = 163, 1627 }, 1628 .delay = { 1629 .enable = 50, 1630 .disable = 50, 1631 }, 1632 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1633 }; 1634 1635 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 1636 .clock = 10870, 1637 .hdisplay = 480, 1638 .hsync_start = 480 + 2, 1639 .hsync_end = 480 + 2 + 41, 1640 .htotal = 480 + 2 + 41 + 2, 1641 .vdisplay = 272, 1642 .vsync_start = 272 + 2, 1643 .vsync_end = 272 + 2 + 4, 1644 .vtotal = 272 + 2 + 4 + 2, 1645 .vrefresh = 74, 1646 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1647 }; 1648 1649 static const struct panel_desc nec_nl4827hc19_05b = { 1650 .modes = &nec_nl4827hc19_05b_mode, 1651 .num_modes = 1, 1652 .bpc = 8, 1653 .size = { 1654 .width = 95, 1655 .height = 54, 1656 }, 1657 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1658 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 1659 }; 1660 1661 static const struct drm_display_mode netron_dy_e231732_mode = { 1662 .clock = 66000, 1663 .hdisplay = 1024, 1664 .hsync_start = 1024 + 160, 1665 .hsync_end = 1024 + 160 + 70, 1666 .htotal = 1024 + 160 + 70 + 90, 1667 .vdisplay = 600, 1668 .vsync_start = 600 + 127, 1669 .vsync_end = 600 + 127 + 20, 1670 .vtotal = 600 + 127 + 20 + 3, 1671 .vrefresh = 60, 1672 }; 1673 1674 static const struct panel_desc netron_dy_e231732 = { 1675 .modes = &netron_dy_e231732_mode, 1676 .num_modes = 1, 1677 .size = { 1678 .width = 154, 1679 .height = 87, 1680 }, 1681 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1682 }; 1683 1684 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 1685 .clock = 9000, 1686 .hdisplay = 480, 1687 .hsync_start = 480 + 2, 1688 .hsync_end = 480 + 2 + 41, 1689 .htotal = 480 + 2 + 41 + 2, 1690 .vdisplay = 272, 1691 .vsync_start = 272 + 2, 1692 .vsync_end = 272 + 2 + 10, 1693 .vtotal = 272 + 2 + 10 + 2, 1694 .vrefresh = 60, 1695 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1696 }; 1697 1698 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 1699 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 1700 .num_modes = 1, 1701 .bpc = 8, 1702 .size = { 1703 .width = 95, 1704 .height = 54, 1705 }, 1706 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1707 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE | 1708 DRM_BUS_FLAG_SYNC_POSEDGE, 1709 }; 1710 1711 static const struct display_timing nlt_nl192108ac18_02d_timing = { 1712 .pixelclock = { 130000000, 148350000, 163000000 }, 1713 .hactive = { 1920, 1920, 1920 }, 1714 .hfront_porch = { 80, 100, 100 }, 1715 .hback_porch = { 100, 120, 120 }, 1716 .hsync_len = { 50, 60, 60 }, 1717 .vactive = { 1080, 1080, 1080 }, 1718 .vfront_porch = { 12, 30, 30 }, 1719 .vback_porch = { 4, 10, 10 }, 1720 .vsync_len = { 4, 5, 5 }, 1721 }; 1722 1723 static const struct panel_desc nlt_nl192108ac18_02d = { 1724 .timings = &nlt_nl192108ac18_02d_timing, 1725 .num_timings = 1, 1726 .bpc = 8, 1727 .size = { 1728 .width = 344, 1729 .height = 194, 1730 }, 1731 .delay = { 1732 .unprepare = 500, 1733 }, 1734 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1735 }; 1736 1737 static const struct drm_display_mode nvd_9128_mode = { 1738 .clock = 29500, 1739 .hdisplay = 800, 1740 .hsync_start = 800 + 130, 1741 .hsync_end = 800 + 130 + 98, 1742 .htotal = 800 + 0 + 130 + 98, 1743 .vdisplay = 480, 1744 .vsync_start = 480 + 10, 1745 .vsync_end = 480 + 10 + 50, 1746 .vtotal = 480 + 0 + 10 + 50, 1747 }; 1748 1749 static const struct panel_desc nvd_9128 = { 1750 .modes = &nvd_9128_mode, 1751 .num_modes = 1, 1752 .bpc = 8, 1753 .size = { 1754 .width = 156, 1755 .height = 88, 1756 }, 1757 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1758 }; 1759 1760 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 1761 .pixelclock = { 30000000, 30000000, 40000000 }, 1762 .hactive = { 800, 800, 800 }, 1763 .hfront_porch = { 40, 40, 40 }, 1764 .hback_porch = { 40, 40, 40 }, 1765 .hsync_len = { 1, 48, 48 }, 1766 .vactive = { 480, 480, 480 }, 1767 .vfront_porch = { 13, 13, 13 }, 1768 .vback_porch = { 29, 29, 29 }, 1769 .vsync_len = { 3, 3, 3 }, 1770 .flags = DISPLAY_FLAGS_DE_HIGH, 1771 }; 1772 1773 static const struct panel_desc okaya_rs800480t_7x0gp = { 1774 .timings = &okaya_rs800480t_7x0gp_timing, 1775 .num_timings = 1, 1776 .bpc = 6, 1777 .size = { 1778 .width = 154, 1779 .height = 87, 1780 }, 1781 .delay = { 1782 .prepare = 41, 1783 .enable = 50, 1784 .unprepare = 41, 1785 .disable = 50, 1786 }, 1787 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1788 }; 1789 1790 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 1791 .clock = 9000, 1792 .hdisplay = 480, 1793 .hsync_start = 480 + 5, 1794 .hsync_end = 480 + 5 + 30, 1795 .htotal = 480 + 5 + 30 + 10, 1796 .vdisplay = 272, 1797 .vsync_start = 272 + 8, 1798 .vsync_end = 272 + 8 + 5, 1799 .vtotal = 272 + 8 + 5 + 3, 1800 .vrefresh = 60, 1801 }; 1802 1803 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 1804 .modes = &olimex_lcd_olinuxino_43ts_mode, 1805 .num_modes = 1, 1806 .size = { 1807 .width = 95, 1808 .height = 54, 1809 }, 1810 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1811 }; 1812 1813 /* 1814 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 1815 * pixel clocks, but this is the timing that was being used in the Adafruit 1816 * installation instructions. 1817 */ 1818 static const struct drm_display_mode ontat_yx700wv03_mode = { 1819 .clock = 29500, 1820 .hdisplay = 800, 1821 .hsync_start = 824, 1822 .hsync_end = 896, 1823 .htotal = 992, 1824 .vdisplay = 480, 1825 .vsync_start = 483, 1826 .vsync_end = 493, 1827 .vtotal = 500, 1828 .vrefresh = 60, 1829 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1830 }; 1831 1832 /* 1833 * Specification at: 1834 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 1835 */ 1836 static const struct panel_desc ontat_yx700wv03 = { 1837 .modes = &ontat_yx700wv03_mode, 1838 .num_modes = 1, 1839 .bpc = 8, 1840 .size = { 1841 .width = 154, 1842 .height = 83, 1843 }, 1844 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1845 }; 1846 1847 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 1848 .clock = 25000, 1849 .hdisplay = 480, 1850 .hsync_start = 480 + 10, 1851 .hsync_end = 480 + 10 + 10, 1852 .htotal = 480 + 10 + 10 + 15, 1853 .vdisplay = 800, 1854 .vsync_start = 800 + 3, 1855 .vsync_end = 800 + 3 + 3, 1856 .vtotal = 800 + 3 + 3 + 3, 1857 .vrefresh = 60, 1858 }; 1859 1860 static const struct panel_desc ortustech_com43h4m85ulc = { 1861 .modes = &ortustech_com43h4m85ulc_mode, 1862 .num_modes = 1, 1863 .bpc = 8, 1864 .size = { 1865 .width = 56, 1866 .height = 93, 1867 }, 1868 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1869 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 1870 }; 1871 1872 static const struct drm_display_mode qd43003c0_40_mode = { 1873 .clock = 9000, 1874 .hdisplay = 480, 1875 .hsync_start = 480 + 8, 1876 .hsync_end = 480 + 8 + 4, 1877 .htotal = 480 + 8 + 4 + 39, 1878 .vdisplay = 272, 1879 .vsync_start = 272 + 4, 1880 .vsync_end = 272 + 4 + 10, 1881 .vtotal = 272 + 4 + 10 + 2, 1882 .vrefresh = 60, 1883 }; 1884 1885 static const struct panel_desc qd43003c0_40 = { 1886 .modes = &qd43003c0_40_mode, 1887 .num_modes = 1, 1888 .bpc = 8, 1889 .size = { 1890 .width = 95, 1891 .height = 53, 1892 }, 1893 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1894 }; 1895 1896 static const struct display_timing rocktech_rk070er9427_timing = { 1897 .pixelclock = { 26400000, 33300000, 46800000 }, 1898 .hactive = { 800, 800, 800 }, 1899 .hfront_porch = { 16, 210, 354 }, 1900 .hback_porch = { 46, 46, 46 }, 1901 .hsync_len = { 1, 1, 1 }, 1902 .vactive = { 480, 480, 480 }, 1903 .vfront_porch = { 7, 22, 147 }, 1904 .vback_porch = { 23, 23, 23 }, 1905 .vsync_len = { 1, 1, 1 }, 1906 .flags = DISPLAY_FLAGS_DE_HIGH, 1907 }; 1908 1909 static const struct panel_desc rocktech_rk070er9427 = { 1910 .timings = &rocktech_rk070er9427_timing, 1911 .num_timings = 1, 1912 .bpc = 6, 1913 .size = { 1914 .width = 154, 1915 .height = 86, 1916 }, 1917 .delay = { 1918 .prepare = 41, 1919 .enable = 50, 1920 .unprepare = 41, 1921 .disable = 50, 1922 }, 1923 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1924 }; 1925 1926 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 1927 .clock = 271560, 1928 .hdisplay = 2560, 1929 .hsync_start = 2560 + 48, 1930 .hsync_end = 2560 + 48 + 32, 1931 .htotal = 2560 + 48 + 32 + 80, 1932 .vdisplay = 1600, 1933 .vsync_start = 1600 + 2, 1934 .vsync_end = 1600 + 2 + 5, 1935 .vtotal = 1600 + 2 + 5 + 57, 1936 .vrefresh = 60, 1937 }; 1938 1939 static const struct panel_desc samsung_lsn122dl01_c01 = { 1940 .modes = &samsung_lsn122dl01_c01_mode, 1941 .num_modes = 1, 1942 .size = { 1943 .width = 263, 1944 .height = 164, 1945 }, 1946 }; 1947 1948 static const struct drm_display_mode samsung_ltn101nt05_mode = { 1949 .clock = 54030, 1950 .hdisplay = 1024, 1951 .hsync_start = 1024 + 24, 1952 .hsync_end = 1024 + 24 + 136, 1953 .htotal = 1024 + 24 + 136 + 160, 1954 .vdisplay = 600, 1955 .vsync_start = 600 + 3, 1956 .vsync_end = 600 + 3 + 6, 1957 .vtotal = 600 + 3 + 6 + 61, 1958 .vrefresh = 60, 1959 }; 1960 1961 static const struct panel_desc samsung_ltn101nt05 = { 1962 .modes = &samsung_ltn101nt05_mode, 1963 .num_modes = 1, 1964 .bpc = 6, 1965 .size = { 1966 .width = 223, 1967 .height = 125, 1968 }, 1969 }; 1970 1971 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 1972 .clock = 76300, 1973 .hdisplay = 1366, 1974 .hsync_start = 1366 + 64, 1975 .hsync_end = 1366 + 64 + 48, 1976 .htotal = 1366 + 64 + 48 + 128, 1977 .vdisplay = 768, 1978 .vsync_start = 768 + 2, 1979 .vsync_end = 768 + 2 + 5, 1980 .vtotal = 768 + 2 + 5 + 17, 1981 .vrefresh = 60, 1982 }; 1983 1984 static const struct panel_desc samsung_ltn140at29_301 = { 1985 .modes = &samsung_ltn140at29_301_mode, 1986 .num_modes = 1, 1987 .bpc = 6, 1988 .size = { 1989 .width = 320, 1990 .height = 187, 1991 }, 1992 }; 1993 1994 static const struct drm_display_mode sharp_lq035q7db03_mode = { 1995 .clock = 5500, 1996 .hdisplay = 240, 1997 .hsync_start = 240 + 16, 1998 .hsync_end = 240 + 16 + 7, 1999 .htotal = 240 + 16 + 7 + 5, 2000 .vdisplay = 320, 2001 .vsync_start = 320 + 9, 2002 .vsync_end = 320 + 9 + 1, 2003 .vtotal = 320 + 9 + 1 + 7, 2004 .vrefresh = 60, 2005 }; 2006 2007 static const struct panel_desc sharp_lq035q7db03 = { 2008 .modes = &sharp_lq035q7db03_mode, 2009 .num_modes = 1, 2010 .bpc = 6, 2011 .size = { 2012 .width = 54, 2013 .height = 72, 2014 }, 2015 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2016 }; 2017 2018 static const struct display_timing sharp_lq101k1ly04_timing = { 2019 .pixelclock = { 60000000, 65000000, 80000000 }, 2020 .hactive = { 1280, 1280, 1280 }, 2021 .hfront_porch = { 20, 20, 20 }, 2022 .hback_porch = { 20, 20, 20 }, 2023 .hsync_len = { 10, 10, 10 }, 2024 .vactive = { 800, 800, 800 }, 2025 .vfront_porch = { 4, 4, 4 }, 2026 .vback_porch = { 4, 4, 4 }, 2027 .vsync_len = { 4, 4, 4 }, 2028 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 2029 }; 2030 2031 static const struct panel_desc sharp_lq101k1ly04 = { 2032 .timings = &sharp_lq101k1ly04_timing, 2033 .num_timings = 1, 2034 .bpc = 8, 2035 .size = { 2036 .width = 217, 2037 .height = 136, 2038 }, 2039 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 2040 }; 2041 2042 static const struct display_timing sharp_lq123p1jx31_timing = { 2043 .pixelclock = { 252750000, 252750000, 266604720 }, 2044 .hactive = { 2400, 2400, 2400 }, 2045 .hfront_porch = { 48, 48, 48 }, 2046 .hback_porch = { 80, 80, 84 }, 2047 .hsync_len = { 32, 32, 32 }, 2048 .vactive = { 1600, 1600, 1600 }, 2049 .vfront_porch = { 3, 3, 3 }, 2050 .vback_porch = { 33, 33, 120 }, 2051 .vsync_len = { 10, 10, 10 }, 2052 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2053 }; 2054 2055 static const struct panel_desc sharp_lq123p1jx31 = { 2056 .timings = &sharp_lq123p1jx31_timing, 2057 .num_timings = 1, 2058 .bpc = 8, 2059 .size = { 2060 .width = 259, 2061 .height = 173, 2062 }, 2063 .delay = { 2064 .prepare = 110, 2065 .enable = 50, 2066 .unprepare = 550, 2067 }, 2068 }; 2069 2070 static const struct drm_display_mode sharp_lq150x1lg11_mode = { 2071 .clock = 71100, 2072 .hdisplay = 1024, 2073 .hsync_start = 1024 + 168, 2074 .hsync_end = 1024 + 168 + 64, 2075 .htotal = 1024 + 168 + 64 + 88, 2076 .vdisplay = 768, 2077 .vsync_start = 768 + 37, 2078 .vsync_end = 768 + 37 + 2, 2079 .vtotal = 768 + 37 + 2 + 8, 2080 .vrefresh = 60, 2081 }; 2082 2083 static const struct panel_desc sharp_lq150x1lg11 = { 2084 .modes = &sharp_lq150x1lg11_mode, 2085 .num_modes = 1, 2086 .bpc = 6, 2087 .size = { 2088 .width = 304, 2089 .height = 228, 2090 }, 2091 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 2092 }; 2093 2094 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 2095 .clock = 33300, 2096 .hdisplay = 800, 2097 .hsync_start = 800 + 1, 2098 .hsync_end = 800 + 1 + 64, 2099 .htotal = 800 + 1 + 64 + 64, 2100 .vdisplay = 480, 2101 .vsync_start = 480 + 1, 2102 .vsync_end = 480 + 1 + 23, 2103 .vtotal = 480 + 1 + 23 + 22, 2104 .vrefresh = 60, 2105 }; 2106 2107 static const struct panel_desc shelly_sca07010_bfn_lnn = { 2108 .modes = &shelly_sca07010_bfn_lnn_mode, 2109 .num_modes = 1, 2110 .size = { 2111 .width = 152, 2112 .height = 91, 2113 }, 2114 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2115 }; 2116 2117 static const struct drm_display_mode starry_kr122ea0sra_mode = { 2118 .clock = 147000, 2119 .hdisplay = 1920, 2120 .hsync_start = 1920 + 16, 2121 .hsync_end = 1920 + 16 + 16, 2122 .htotal = 1920 + 16 + 16 + 32, 2123 .vdisplay = 1200, 2124 .vsync_start = 1200 + 15, 2125 .vsync_end = 1200 + 15 + 2, 2126 .vtotal = 1200 + 15 + 2 + 18, 2127 .vrefresh = 60, 2128 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2129 }; 2130 2131 static const struct panel_desc starry_kr122ea0sra = { 2132 .modes = &starry_kr122ea0sra_mode, 2133 .num_modes = 1, 2134 .size = { 2135 .width = 263, 2136 .height = 164, 2137 }, 2138 .delay = { 2139 .prepare = 10 + 200, 2140 .enable = 50, 2141 .unprepare = 10 + 500, 2142 }, 2143 }; 2144 2145 static const struct display_timing tianma_tm070jdhg30_timing = { 2146 .pixelclock = { 62600000, 68200000, 78100000 }, 2147 .hactive = { 1280, 1280, 1280 }, 2148 .hfront_porch = { 15, 64, 159 }, 2149 .hback_porch = { 5, 5, 5 }, 2150 .hsync_len = { 1, 1, 256 }, 2151 .vactive = { 800, 800, 800 }, 2152 .vfront_porch = { 3, 40, 99 }, 2153 .vback_porch = { 2, 2, 2 }, 2154 .vsync_len = { 1, 1, 128 }, 2155 .flags = DISPLAY_FLAGS_DE_HIGH, 2156 }; 2157 2158 static const struct panel_desc tianma_tm070jdhg30 = { 2159 .timings = &tianma_tm070jdhg30_timing, 2160 .num_timings = 1, 2161 .bpc = 8, 2162 .size = { 2163 .width = 151, 2164 .height = 95, 2165 }, 2166 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2167 }; 2168 2169 static const struct display_timing tianma_tm070rvhg71_timing = { 2170 .pixelclock = { 27700000, 29200000, 39600000 }, 2171 .hactive = { 800, 800, 800 }, 2172 .hfront_porch = { 12, 40, 212 }, 2173 .hback_porch = { 88, 88, 88 }, 2174 .hsync_len = { 1, 1, 40 }, 2175 .vactive = { 480, 480, 480 }, 2176 .vfront_porch = { 1, 13, 88 }, 2177 .vback_porch = { 32, 32, 32 }, 2178 .vsync_len = { 1, 1, 3 }, 2179 .flags = DISPLAY_FLAGS_DE_HIGH, 2180 }; 2181 2182 static const struct panel_desc tianma_tm070rvhg71 = { 2183 .timings = &tianma_tm070rvhg71_timing, 2184 .num_timings = 1, 2185 .bpc = 8, 2186 .size = { 2187 .width = 154, 2188 .height = 86, 2189 }, 2190 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2191 }; 2192 2193 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 2194 .clock = 79500, 2195 .hdisplay = 1280, 2196 .hsync_start = 1280 + 192, 2197 .hsync_end = 1280 + 192 + 128, 2198 .htotal = 1280 + 192 + 128 + 64, 2199 .vdisplay = 768, 2200 .vsync_start = 768 + 20, 2201 .vsync_end = 768 + 20 + 7, 2202 .vtotal = 768 + 20 + 7 + 3, 2203 .vrefresh = 60, 2204 }; 2205 2206 static const struct panel_desc toshiba_lt089ac29000 = { 2207 .modes = &toshiba_lt089ac29000_mode, 2208 .num_modes = 1, 2209 .size = { 2210 .width = 194, 2211 .height = 116, 2212 }, 2213 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2214 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, 2215 }; 2216 2217 static const struct drm_display_mode tpk_f07a_0102_mode = { 2218 .clock = 33260, 2219 .hdisplay = 800, 2220 .hsync_start = 800 + 40, 2221 .hsync_end = 800 + 40 + 128, 2222 .htotal = 800 + 40 + 128 + 88, 2223 .vdisplay = 480, 2224 .vsync_start = 480 + 10, 2225 .vsync_end = 480 + 10 + 2, 2226 .vtotal = 480 + 10 + 2 + 33, 2227 .vrefresh = 60, 2228 }; 2229 2230 static const struct panel_desc tpk_f07a_0102 = { 2231 .modes = &tpk_f07a_0102_mode, 2232 .num_modes = 1, 2233 .size = { 2234 .width = 152, 2235 .height = 91, 2236 }, 2237 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, 2238 }; 2239 2240 static const struct drm_display_mode tpk_f10a_0102_mode = { 2241 .clock = 45000, 2242 .hdisplay = 1024, 2243 .hsync_start = 1024 + 176, 2244 .hsync_end = 1024 + 176 + 5, 2245 .htotal = 1024 + 176 + 5 + 88, 2246 .vdisplay = 600, 2247 .vsync_start = 600 + 20, 2248 .vsync_end = 600 + 20 + 5, 2249 .vtotal = 600 + 20 + 5 + 25, 2250 .vrefresh = 60, 2251 }; 2252 2253 static const struct panel_desc tpk_f10a_0102 = { 2254 .modes = &tpk_f10a_0102_mode, 2255 .num_modes = 1, 2256 .size = { 2257 .width = 223, 2258 .height = 125, 2259 }, 2260 }; 2261 2262 static const struct display_timing urt_umsh_8596md_timing = { 2263 .pixelclock = { 33260000, 33260000, 33260000 }, 2264 .hactive = { 800, 800, 800 }, 2265 .hfront_porch = { 41, 41, 41 }, 2266 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 2267 .hsync_len = { 71, 128, 128 }, 2268 .vactive = { 480, 480, 480 }, 2269 .vfront_porch = { 10, 10, 10 }, 2270 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 2271 .vsync_len = { 2, 2, 2 }, 2272 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2273 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2274 }; 2275 2276 static const struct panel_desc urt_umsh_8596md_lvds = { 2277 .timings = &urt_umsh_8596md_timing, 2278 .num_timings = 1, 2279 .bpc = 6, 2280 .size = { 2281 .width = 152, 2282 .height = 91, 2283 }, 2284 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2285 }; 2286 2287 static const struct panel_desc urt_umsh_8596md_parallel = { 2288 .timings = &urt_umsh_8596md_timing, 2289 .num_timings = 1, 2290 .bpc = 6, 2291 .size = { 2292 .width = 152, 2293 .height = 91, 2294 }, 2295 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2296 }; 2297 2298 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 2299 .clock = 6410, 2300 .hdisplay = 320, 2301 .hsync_start = 320 + 20, 2302 .hsync_end = 320 + 20 + 30, 2303 .htotal = 320 + 20 + 30 + 38, 2304 .vdisplay = 240, 2305 .vsync_start = 240 + 4, 2306 .vsync_end = 240 + 4 + 3, 2307 .vtotal = 240 + 4 + 3 + 15, 2308 .vrefresh = 60, 2309 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2310 }; 2311 2312 static const struct panel_desc winstar_wf35ltiacd = { 2313 .modes = &winstar_wf35ltiacd_mode, 2314 .num_modes = 1, 2315 .bpc = 8, 2316 .size = { 2317 .width = 70, 2318 .height = 53, 2319 }, 2320 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2321 }; 2322 2323 static const struct of_device_id platform_of_match[] = { 2324 { 2325 .compatible = "ampire,am-480272h3tmqw-t01h", 2326 .data = &ire_am_480272h3tmqw_t01h, 2327 }, { 2328 .compatible = "ampire,am800480r3tmqwa1h", 2329 .data = &ire_am800480r3tmqwa1h, 2330 }, { 2331 .compatible = "auo,b101aw03", 2332 .data = &auo_b101aw03, 2333 }, { 2334 .compatible = "auo,b101ean01", 2335 .data = &auo_b101ean01, 2336 }, { 2337 .compatible = "auo,b101xtn01", 2338 .data = &auo_b101xtn01, 2339 }, { 2340 .compatible = "auo,b116xw03", 2341 .data = &auo_b116xw03, 2342 }, { 2343 .compatible = "auo,b133htn01", 2344 .data = &auo_b133htn01, 2345 }, { 2346 .compatible = "auo,b133xtn01", 2347 .data = &auo_b133xtn01, 2348 }, { 2349 .compatible = "auo,g070vvn01", 2350 .data = &auo_g070vvn01, 2351 }, { 2352 .compatible = "auo,g104sn02", 2353 .data = &auo_g104sn02, 2354 }, { 2355 .compatible = "auo,g133han01", 2356 .data = &auo_g133han01, 2357 }, { 2358 .compatible = "auo,g185han01", 2359 .data = &auo_g185han01, 2360 }, { 2361 .compatible = "auo,p320hvn03", 2362 .data = &auo_p320hvn03, 2363 }, { 2364 .compatible = "auo,t215hvn01", 2365 .data = &auo_t215hvn01, 2366 }, { 2367 .compatible = "avic,tm070ddh03", 2368 .data = &avic_tm070ddh03, 2369 }, { 2370 .compatible = "boe,hv070wsa-100", 2371 .data = &boe_hv070wsa 2372 }, { 2373 .compatible = "boe,nv101wxmn51", 2374 .data = &boe_nv101wxmn51, 2375 }, { 2376 .compatible = "chunghwa,claa070wp03xg", 2377 .data = &chunghwa_claa070wp03xg, 2378 }, { 2379 .compatible = "chunghwa,claa101wa01a", 2380 .data = &chunghwa_claa101wa01a 2381 }, { 2382 .compatible = "chunghwa,claa101wb01", 2383 .data = &chunghwa_claa101wb01 2384 }, { 2385 .compatible = "dataimage,scf0700c48ggu18", 2386 .data = &dataimage_scf0700c48ggu18, 2387 }, { 2388 .compatible = "dlc,dlc0700yzg-1", 2389 .data = &dlc_dlc0700yzg_1, 2390 }, { 2391 .compatible = "edt,et057090dhu", 2392 .data = &edt_et057090dhu, 2393 }, { 2394 .compatible = "edt,et070080dh6", 2395 .data = &edt_etm0700g0dh6, 2396 }, { 2397 .compatible = "edt,etm0700g0dh6", 2398 .data = &edt_etm0700g0dh6, 2399 }, { 2400 .compatible = "edt,etm0700g0bdh6", 2401 .data = &edt_etm0700g0bdh6, 2402 }, { 2403 .compatible = "edt,etm0700g0edh6", 2404 .data = &edt_etm0700g0bdh6, 2405 }, { 2406 .compatible = "foxlink,fl500wvr00-a0t", 2407 .data = &foxlink_fl500wvr00_a0t, 2408 }, { 2409 .compatible = "giantplus,gpg482739qs5", 2410 .data = &giantplus_gpg482739qs5 2411 }, { 2412 .compatible = "hannstar,hsd070pww1", 2413 .data = &hannstar_hsd070pww1, 2414 }, { 2415 .compatible = "hannstar,hsd100pxn1", 2416 .data = &hannstar_hsd100pxn1, 2417 }, { 2418 .compatible = "hit,tx23d38vm0caa", 2419 .data = &hitachi_tx23d38vm0caa 2420 }, { 2421 .compatible = "innolux,at043tn24", 2422 .data = &innolux_at043tn24, 2423 }, { 2424 .compatible = "innolux,at070tn92", 2425 .data = &innolux_at070tn92, 2426 }, { 2427 .compatible = "innolux,g070y2-l01", 2428 .data = &innolux_g070y2_l01, 2429 }, { 2430 .compatible = "innolux,g101ice-l01", 2431 .data = &innolux_g101ice_l01 2432 }, { 2433 .compatible = "innolux,g121i1-l01", 2434 .data = &innolux_g121i1_l01 2435 }, { 2436 .compatible = "innolux,g121x1-l03", 2437 .data = &innolux_g121x1_l03, 2438 }, { 2439 .compatible = "innolux,n116bge", 2440 .data = &innolux_n116bge, 2441 }, { 2442 .compatible = "innolux,n156bge-l21", 2443 .data = &innolux_n156bge_l21, 2444 }, { 2445 .compatible = "innolux,tv123wam", 2446 .data = &innolux_tv123wam, 2447 }, { 2448 .compatible = "innolux,zj070na-01p", 2449 .data = &innolux_zj070na_01p, 2450 }, { 2451 .compatible = "koe,tx31d200vm0baa", 2452 .data = &koe_tx31d200vm0baa, 2453 }, { 2454 .compatible = "kyo,tcg121xglp", 2455 .data = &kyo_tcg121xglp, 2456 }, { 2457 .compatible = "lg,lb070wv8", 2458 .data = &lg_lb070wv8, 2459 }, { 2460 .compatible = "lg,lp079qx1-sp0v", 2461 .data = &lg_lp079qx1_sp0v, 2462 }, { 2463 .compatible = "lg,lp097qx1-spa1", 2464 .data = &lg_lp097qx1_spa1, 2465 }, { 2466 .compatible = "lg,lp120up1", 2467 .data = &lg_lp120up1, 2468 }, { 2469 .compatible = "lg,lp129qe", 2470 .data = &lg_lp129qe, 2471 }, { 2472 .compatible = "mitsubishi,aa070mc01-ca1", 2473 .data = &mitsubishi_aa070mc01, 2474 }, { 2475 .compatible = "nec,nl12880bc20-05", 2476 .data = &nec_nl12880bc20_05, 2477 }, { 2478 .compatible = "nec,nl4827hc19-05b", 2479 .data = &nec_nl4827hc19_05b, 2480 }, { 2481 .compatible = "netron-dy,e231732", 2482 .data = &netron_dy_e231732, 2483 }, { 2484 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 2485 .data = &newhaven_nhd_43_480272ef_atxl, 2486 }, { 2487 .compatible = "nlt,nl192108ac18-02d", 2488 .data = &nlt_nl192108ac18_02d, 2489 }, { 2490 .compatible = "nvd,9128", 2491 .data = &nvd_9128, 2492 }, { 2493 .compatible = "okaya,rs800480t-7x0gp", 2494 .data = &okaya_rs800480t_7x0gp, 2495 }, { 2496 .compatible = "olimex,lcd-olinuxino-43-ts", 2497 .data = &olimex_lcd_olinuxino_43ts, 2498 }, { 2499 .compatible = "ontat,yx700wv03", 2500 .data = &ontat_yx700wv03, 2501 }, { 2502 .compatible = "ortustech,com43h4m85ulc", 2503 .data = &ortustech_com43h4m85ulc, 2504 }, { 2505 .compatible = "qiaodian,qd43003c0-40", 2506 .data = &qd43003c0_40, 2507 }, { 2508 .compatible = "rocktech,rk070er9427", 2509 .data = &rocktech_rk070er9427, 2510 }, { 2511 .compatible = "samsung,lsn122dl01-c01", 2512 .data = &samsung_lsn122dl01_c01, 2513 }, { 2514 .compatible = "samsung,ltn101nt05", 2515 .data = &samsung_ltn101nt05, 2516 }, { 2517 .compatible = "samsung,ltn140at29-301", 2518 .data = &samsung_ltn140at29_301, 2519 }, { 2520 .compatible = "sharp,lq035q7db03", 2521 .data = &sharp_lq035q7db03, 2522 }, { 2523 .compatible = "sharp,lq101k1ly04", 2524 .data = &sharp_lq101k1ly04, 2525 }, { 2526 .compatible = "sharp,lq123p1jx31", 2527 .data = &sharp_lq123p1jx31, 2528 }, { 2529 .compatible = "sharp,lq150x1lg11", 2530 .data = &sharp_lq150x1lg11, 2531 }, { 2532 .compatible = "shelly,sca07010-bfn-lnn", 2533 .data = &shelly_sca07010_bfn_lnn, 2534 }, { 2535 .compatible = "starry,kr122ea0sra", 2536 .data = &starry_kr122ea0sra, 2537 }, { 2538 .compatible = "tianma,tm070jdhg30", 2539 .data = &tianma_tm070jdhg30, 2540 }, { 2541 .compatible = "tianma,tm070rvhg71", 2542 .data = &tianma_tm070rvhg71, 2543 }, { 2544 .compatible = "toshiba,lt089ac29000", 2545 .data = &toshiba_lt089ac29000, 2546 }, { 2547 .compatible = "tpk,f07a-0102", 2548 .data = &tpk_f07a_0102, 2549 }, { 2550 .compatible = "tpk,f10a-0102", 2551 .data = &tpk_f10a_0102, 2552 }, { 2553 .compatible = "urt,umsh-8596md-t", 2554 .data = &urt_umsh_8596md_parallel, 2555 }, { 2556 .compatible = "urt,umsh-8596md-1t", 2557 .data = &urt_umsh_8596md_parallel, 2558 }, { 2559 .compatible = "urt,umsh-8596md-7t", 2560 .data = &urt_umsh_8596md_parallel, 2561 }, { 2562 .compatible = "urt,umsh-8596md-11t", 2563 .data = &urt_umsh_8596md_lvds, 2564 }, { 2565 .compatible = "urt,umsh-8596md-19t", 2566 .data = &urt_umsh_8596md_lvds, 2567 }, { 2568 .compatible = "urt,umsh-8596md-20t", 2569 .data = &urt_umsh_8596md_parallel, 2570 }, { 2571 .compatible = "winstar,wf35ltiacd", 2572 .data = &winstar_wf35ltiacd, 2573 }, { 2574 /* sentinel */ 2575 } 2576 }; 2577 MODULE_DEVICE_TABLE(of, platform_of_match); 2578 2579 static int panel_simple_platform_probe(struct platform_device *pdev) 2580 { 2581 const struct of_device_id *id; 2582 2583 id = of_match_node(platform_of_match, pdev->dev.of_node); 2584 if (!id) 2585 return -ENODEV; 2586 2587 return panel_simple_probe(&pdev->dev, id->data); 2588 } 2589 2590 static int panel_simple_platform_remove(struct platform_device *pdev) 2591 { 2592 return panel_simple_remove(&pdev->dev); 2593 } 2594 2595 static void panel_simple_platform_shutdown(struct platform_device *pdev) 2596 { 2597 panel_simple_shutdown(&pdev->dev); 2598 } 2599 2600 static struct platform_driver panel_simple_platform_driver = { 2601 .driver = { 2602 .name = "panel-simple", 2603 .of_match_table = platform_of_match, 2604 }, 2605 .probe = panel_simple_platform_probe, 2606 .remove = panel_simple_platform_remove, 2607 .shutdown = panel_simple_platform_shutdown, 2608 }; 2609 2610 struct panel_desc_dsi { 2611 struct panel_desc desc; 2612 2613 unsigned long flags; 2614 enum mipi_dsi_pixel_format format; 2615 unsigned int lanes; 2616 }; 2617 2618 static const struct drm_display_mode auo_b080uan01_mode = { 2619 .clock = 154500, 2620 .hdisplay = 1200, 2621 .hsync_start = 1200 + 62, 2622 .hsync_end = 1200 + 62 + 4, 2623 .htotal = 1200 + 62 + 4 + 62, 2624 .vdisplay = 1920, 2625 .vsync_start = 1920 + 9, 2626 .vsync_end = 1920 + 9 + 2, 2627 .vtotal = 1920 + 9 + 2 + 8, 2628 .vrefresh = 60, 2629 }; 2630 2631 static const struct panel_desc_dsi auo_b080uan01 = { 2632 .desc = { 2633 .modes = &auo_b080uan01_mode, 2634 .num_modes = 1, 2635 .bpc = 8, 2636 .size = { 2637 .width = 108, 2638 .height = 272, 2639 }, 2640 }, 2641 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2642 .format = MIPI_DSI_FMT_RGB888, 2643 .lanes = 4, 2644 }; 2645 2646 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 2647 .clock = 160000, 2648 .hdisplay = 1200, 2649 .hsync_start = 1200 + 120, 2650 .hsync_end = 1200 + 120 + 20, 2651 .htotal = 1200 + 120 + 20 + 21, 2652 .vdisplay = 1920, 2653 .vsync_start = 1920 + 21, 2654 .vsync_end = 1920 + 21 + 3, 2655 .vtotal = 1920 + 21 + 3 + 18, 2656 .vrefresh = 60, 2657 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2658 }; 2659 2660 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 2661 .desc = { 2662 .modes = &boe_tv080wum_nl0_mode, 2663 .num_modes = 1, 2664 .size = { 2665 .width = 107, 2666 .height = 172, 2667 }, 2668 }, 2669 .flags = MIPI_DSI_MODE_VIDEO | 2670 MIPI_DSI_MODE_VIDEO_BURST | 2671 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 2672 .format = MIPI_DSI_FMT_RGB888, 2673 .lanes = 4, 2674 }; 2675 2676 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 2677 .clock = 71000, 2678 .hdisplay = 800, 2679 .hsync_start = 800 + 32, 2680 .hsync_end = 800 + 32 + 1, 2681 .htotal = 800 + 32 + 1 + 57, 2682 .vdisplay = 1280, 2683 .vsync_start = 1280 + 28, 2684 .vsync_end = 1280 + 28 + 1, 2685 .vtotal = 1280 + 28 + 1 + 14, 2686 .vrefresh = 60, 2687 }; 2688 2689 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 2690 .desc = { 2691 .modes = &lg_ld070wx3_sl01_mode, 2692 .num_modes = 1, 2693 .bpc = 8, 2694 .size = { 2695 .width = 94, 2696 .height = 151, 2697 }, 2698 }, 2699 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 2700 .format = MIPI_DSI_FMT_RGB888, 2701 .lanes = 4, 2702 }; 2703 2704 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 2705 .clock = 67000, 2706 .hdisplay = 720, 2707 .hsync_start = 720 + 12, 2708 .hsync_end = 720 + 12 + 4, 2709 .htotal = 720 + 12 + 4 + 112, 2710 .vdisplay = 1280, 2711 .vsync_start = 1280 + 8, 2712 .vsync_end = 1280 + 8 + 4, 2713 .vtotal = 1280 + 8 + 4 + 12, 2714 .vrefresh = 60, 2715 }; 2716 2717 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 2718 .desc = { 2719 .modes = &lg_lh500wx1_sd03_mode, 2720 .num_modes = 1, 2721 .bpc = 8, 2722 .size = { 2723 .width = 62, 2724 .height = 110, 2725 }, 2726 }, 2727 .flags = MIPI_DSI_MODE_VIDEO, 2728 .format = MIPI_DSI_FMT_RGB888, 2729 .lanes = 4, 2730 }; 2731 2732 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 2733 .clock = 157200, 2734 .hdisplay = 1920, 2735 .hsync_start = 1920 + 154, 2736 .hsync_end = 1920 + 154 + 16, 2737 .htotal = 1920 + 154 + 16 + 32, 2738 .vdisplay = 1200, 2739 .vsync_start = 1200 + 17, 2740 .vsync_end = 1200 + 17 + 2, 2741 .vtotal = 1200 + 17 + 2 + 16, 2742 .vrefresh = 60, 2743 }; 2744 2745 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 2746 .desc = { 2747 .modes = &panasonic_vvx10f004b00_mode, 2748 .num_modes = 1, 2749 .bpc = 8, 2750 .size = { 2751 .width = 217, 2752 .height = 136, 2753 }, 2754 }, 2755 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 2756 MIPI_DSI_CLOCK_NON_CONTINUOUS, 2757 .format = MIPI_DSI_FMT_RGB888, 2758 .lanes = 4, 2759 }; 2760 2761 static const struct of_device_id dsi_of_match[] = { 2762 { 2763 .compatible = "auo,b080uan01", 2764 .data = &auo_b080uan01 2765 }, { 2766 .compatible = "boe,tv080wum-nl0", 2767 .data = &boe_tv080wum_nl0 2768 }, { 2769 .compatible = "lg,ld070wx3-sl01", 2770 .data = &lg_ld070wx3_sl01 2771 }, { 2772 .compatible = "lg,lh500wx1-sd03", 2773 .data = &lg_lh500wx1_sd03 2774 }, { 2775 .compatible = "panasonic,vvx10f004b00", 2776 .data = &panasonic_vvx10f004b00 2777 }, { 2778 /* sentinel */ 2779 } 2780 }; 2781 MODULE_DEVICE_TABLE(of, dsi_of_match); 2782 2783 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 2784 { 2785 const struct panel_desc_dsi *desc; 2786 const struct of_device_id *id; 2787 int err; 2788 2789 id = of_match_node(dsi_of_match, dsi->dev.of_node); 2790 if (!id) 2791 return -ENODEV; 2792 2793 desc = id->data; 2794 2795 err = panel_simple_probe(&dsi->dev, &desc->desc); 2796 if (err < 0) 2797 return err; 2798 2799 dsi->mode_flags = desc->flags; 2800 dsi->format = desc->format; 2801 dsi->lanes = desc->lanes; 2802 2803 return mipi_dsi_attach(dsi); 2804 } 2805 2806 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 2807 { 2808 int err; 2809 2810 err = mipi_dsi_detach(dsi); 2811 if (err < 0) 2812 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 2813 2814 return panel_simple_remove(&dsi->dev); 2815 } 2816 2817 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 2818 { 2819 panel_simple_shutdown(&dsi->dev); 2820 } 2821 2822 static struct mipi_dsi_driver panel_simple_dsi_driver = { 2823 .driver = { 2824 .name = "panel-simple-dsi", 2825 .of_match_table = dsi_of_match, 2826 }, 2827 .probe = panel_simple_dsi_probe, 2828 .remove = panel_simple_dsi_remove, 2829 .shutdown = panel_simple_dsi_shutdown, 2830 }; 2831 2832 static int __init panel_simple_init(void) 2833 { 2834 int err; 2835 2836 err = platform_driver_register(&panel_simple_platform_driver); 2837 if (err < 0) 2838 return err; 2839 2840 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 2841 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 2842 if (err < 0) 2843 return err; 2844 } 2845 2846 return 0; 2847 } 2848 module_init(panel_simple_init); 2849 2850 static void __exit panel_simple_exit(void) 2851 { 2852 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 2853 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 2854 2855 platform_driver_unregister(&panel_simple_platform_driver); 2856 } 2857 module_exit(panel_simple_exit); 2858 2859 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 2860 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 2861 MODULE_LICENSE("GPL and additional rights"); 2862