1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 44 /** 45 * struct panel_desc - Describes a simple panel. 46 */ 47 struct panel_desc { 48 /** 49 * @modes: Pointer to array of fixed modes appropriate for this panel. 50 * 51 * If only one mode then this can just be the address of the mode. 52 * NOTE: cannot be used with "timings" and also if this is specified 53 * then you cannot override the mode in the device tree. 54 */ 55 const struct drm_display_mode *modes; 56 57 /** @num_modes: Number of elements in modes array. */ 58 unsigned int num_modes; 59 60 /** 61 * @timings: Pointer to array of display timings 62 * 63 * NOTE: cannot be used with "modes" and also these will be used to 64 * validate a device tree override if one is present. 65 */ 66 const struct display_timing *timings; 67 68 /** @num_timings: Number of elements in timings array. */ 69 unsigned int num_timings; 70 71 /** @bpc: Bits per color. */ 72 unsigned int bpc; 73 74 /** @size: Structure containing the physical size of this panel. */ 75 struct { 76 /** 77 * @size.width: Width (in mm) of the active display area. 78 */ 79 unsigned int width; 80 81 /** 82 * @size.height: Height (in mm) of the active display area. 83 */ 84 unsigned int height; 85 } size; 86 87 /** @delay: Structure containing various delay values for this panel. */ 88 struct { 89 /** 90 * @delay.prepare: Time for the panel to become ready. 91 * 92 * The time (in milliseconds) that it takes for the panel to 93 * become ready and start receiving video data 94 */ 95 unsigned int prepare; 96 97 /** 98 * @delay.enable: Time for the panel to display a valid frame. 99 * 100 * The time (in milliseconds) that it takes for the panel to 101 * display the first valid frame after starting to receive 102 * video data. 103 */ 104 unsigned int enable; 105 106 /** 107 * @delay.disable: Time for the panel to turn the display off. 108 * 109 * The time (in milliseconds) that it takes for the panel to 110 * turn the display off (no content is visible). 111 */ 112 unsigned int disable; 113 114 /** 115 * @delay.unprepare: Time to power down completely. 116 * 117 * The time (in milliseconds) that it takes for the panel 118 * to power itself down completely. 119 * 120 * This time is used to prevent a future "prepare" from 121 * starting until at least this many milliseconds has passed. 122 * If at prepare time less time has passed since unprepare 123 * finished, the driver waits for the remaining time. 124 */ 125 unsigned int unprepare; 126 } delay; 127 128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 129 u32 bus_format; 130 131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 132 u32 bus_flags; 133 134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 135 int connector_type; 136 }; 137 138 struct panel_simple { 139 struct drm_panel base; 140 bool enabled; 141 142 bool prepared; 143 144 ktime_t prepared_time; 145 ktime_t unprepared_time; 146 147 const struct panel_desc *desc; 148 149 struct regulator *supply; 150 struct i2c_adapter *ddc; 151 152 struct gpio_desc *enable_gpio; 153 154 struct edid *edid; 155 156 struct drm_display_mode override_mode; 157 158 enum drm_panel_orientation orientation; 159 }; 160 161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 162 { 163 return container_of(panel, struct panel_simple, base); 164 } 165 166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 167 struct drm_connector *connector) 168 { 169 struct drm_display_mode *mode; 170 unsigned int i, num = 0; 171 172 for (i = 0; i < panel->desc->num_timings; i++) { 173 const struct display_timing *dt = &panel->desc->timings[i]; 174 struct videomode vm; 175 176 videomode_from_timing(dt, &vm); 177 mode = drm_mode_create(connector->dev); 178 if (!mode) { 179 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 180 dt->hactive.typ, dt->vactive.typ); 181 continue; 182 } 183 184 drm_display_mode_from_videomode(&vm, mode); 185 186 mode->type |= DRM_MODE_TYPE_DRIVER; 187 188 if (panel->desc->num_timings == 1) 189 mode->type |= DRM_MODE_TYPE_PREFERRED; 190 191 drm_mode_probed_add(connector, mode); 192 num++; 193 } 194 195 return num; 196 } 197 198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 199 struct drm_connector *connector) 200 { 201 struct drm_display_mode *mode; 202 unsigned int i, num = 0; 203 204 for (i = 0; i < panel->desc->num_modes; i++) { 205 const struct drm_display_mode *m = &panel->desc->modes[i]; 206 207 mode = drm_mode_duplicate(connector->dev, m); 208 if (!mode) { 209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 210 m->hdisplay, m->vdisplay, 211 drm_mode_vrefresh(m)); 212 continue; 213 } 214 215 mode->type |= DRM_MODE_TYPE_DRIVER; 216 217 if (panel->desc->num_modes == 1) 218 mode->type |= DRM_MODE_TYPE_PREFERRED; 219 220 drm_mode_set_name(mode); 221 222 drm_mode_probed_add(connector, mode); 223 num++; 224 } 225 226 return num; 227 } 228 229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 230 struct drm_connector *connector) 231 { 232 struct drm_display_mode *mode; 233 bool has_override = panel->override_mode.type; 234 unsigned int num = 0; 235 236 if (!panel->desc) 237 return 0; 238 239 if (has_override) { 240 mode = drm_mode_duplicate(connector->dev, 241 &panel->override_mode); 242 if (mode) { 243 drm_mode_probed_add(connector, mode); 244 num = 1; 245 } else { 246 dev_err(panel->base.dev, "failed to add override mode\n"); 247 } 248 } 249 250 /* Only add timings if override was not there or failed to validate */ 251 if (num == 0 && panel->desc->num_timings) 252 num = panel_simple_get_timings_modes(panel, connector); 253 254 /* 255 * Only add fixed modes if timings/override added no mode. 256 * 257 * We should only ever have either the display timings specified 258 * or a fixed mode. Anything else is rather bogus. 259 */ 260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 261 if (num == 0) 262 num = panel_simple_get_display_modes(panel, connector); 263 264 connector->display_info.bpc = panel->desc->bpc; 265 connector->display_info.width_mm = panel->desc->size.width; 266 connector->display_info.height_mm = panel->desc->size.height; 267 if (panel->desc->bus_format) 268 drm_display_info_set_bus_formats(&connector->display_info, 269 &panel->desc->bus_format, 1); 270 connector->display_info.bus_flags = panel->desc->bus_flags; 271 272 return num; 273 } 274 275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 276 { 277 ktime_t now_ktime, min_ktime; 278 279 if (!min_ms) 280 return; 281 282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 283 now_ktime = ktime_get(); 284 285 if (ktime_before(now_ktime, min_ktime)) 286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 287 } 288 289 static int panel_simple_disable(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 293 if (!p->enabled) 294 return 0; 295 296 if (p->desc->delay.disable) 297 msleep(p->desc->delay.disable); 298 299 p->enabled = false; 300 301 return 0; 302 } 303 304 static int panel_simple_suspend(struct device *dev) 305 { 306 struct panel_simple *p = dev_get_drvdata(dev); 307 308 gpiod_set_value_cansleep(p->enable_gpio, 0); 309 regulator_disable(p->supply); 310 p->unprepared_time = ktime_get(); 311 312 kfree(p->edid); 313 p->edid = NULL; 314 315 return 0; 316 } 317 318 static int panel_simple_unprepare(struct drm_panel *panel) 319 { 320 struct panel_simple *p = to_panel_simple(panel); 321 int ret; 322 323 /* Unpreparing when already unprepared is a no-op */ 324 if (!p->prepared) 325 return 0; 326 327 pm_runtime_mark_last_busy(panel->dev); 328 ret = pm_runtime_put_autosuspend(panel->dev); 329 if (ret < 0) 330 return ret; 331 p->prepared = false; 332 333 return 0; 334 } 335 336 static int panel_simple_resume(struct device *dev) 337 { 338 struct panel_simple *p = dev_get_drvdata(dev); 339 int err; 340 341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 342 343 err = regulator_enable(p->supply); 344 if (err < 0) { 345 dev_err(dev, "failed to enable supply: %d\n", err); 346 return err; 347 } 348 349 gpiod_set_value_cansleep(p->enable_gpio, 1); 350 351 if (p->desc->delay.prepare) 352 msleep(p->desc->delay.prepare); 353 354 p->prepared_time = ktime_get(); 355 356 return 0; 357 } 358 359 static int panel_simple_prepare(struct drm_panel *panel) 360 { 361 struct panel_simple *p = to_panel_simple(panel); 362 int ret; 363 364 /* Preparing when already prepared is a no-op */ 365 if (p->prepared) 366 return 0; 367 368 ret = pm_runtime_get_sync(panel->dev); 369 if (ret < 0) { 370 pm_runtime_put_autosuspend(panel->dev); 371 return ret; 372 } 373 374 p->prepared = true; 375 376 return 0; 377 } 378 379 static int panel_simple_enable(struct drm_panel *panel) 380 { 381 struct panel_simple *p = to_panel_simple(panel); 382 383 if (p->enabled) 384 return 0; 385 386 if (p->desc->delay.enable) 387 msleep(p->desc->delay.enable); 388 389 p->enabled = true; 390 391 return 0; 392 } 393 394 static int panel_simple_get_modes(struct drm_panel *panel, 395 struct drm_connector *connector) 396 { 397 struct panel_simple *p = to_panel_simple(panel); 398 int num = 0; 399 400 /* probe EDID if a DDC bus is available */ 401 if (p->ddc) { 402 pm_runtime_get_sync(panel->dev); 403 404 if (!p->edid) 405 p->edid = drm_get_edid(connector, p->ddc); 406 407 if (p->edid) 408 num += drm_add_edid_modes(connector, p->edid); 409 410 pm_runtime_mark_last_busy(panel->dev); 411 pm_runtime_put_autosuspend(panel->dev); 412 } 413 414 /* add hard-coded panel modes */ 415 num += panel_simple_get_non_edid_modes(p, connector); 416 417 /* 418 * TODO: Remove once all drm drivers call 419 * drm_connector_set_orientation_from_panel() 420 */ 421 drm_connector_set_panel_orientation(connector, p->orientation); 422 423 return num; 424 } 425 426 static int panel_simple_get_timings(struct drm_panel *panel, 427 unsigned int num_timings, 428 struct display_timing *timings) 429 { 430 struct panel_simple *p = to_panel_simple(panel); 431 unsigned int i; 432 433 if (p->desc->num_timings < num_timings) 434 num_timings = p->desc->num_timings; 435 436 if (timings) 437 for (i = 0; i < num_timings; i++) 438 timings[i] = p->desc->timings[i]; 439 440 return p->desc->num_timings; 441 } 442 443 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 444 { 445 struct panel_simple *p = to_panel_simple(panel); 446 447 return p->orientation; 448 } 449 450 static const struct drm_panel_funcs panel_simple_funcs = { 451 .disable = panel_simple_disable, 452 .unprepare = panel_simple_unprepare, 453 .prepare = panel_simple_prepare, 454 .enable = panel_simple_enable, 455 .get_modes = panel_simple_get_modes, 456 .get_orientation = panel_simple_get_orientation, 457 .get_timings = panel_simple_get_timings, 458 }; 459 460 static struct panel_desc panel_dpi; 461 462 static int panel_dpi_probe(struct device *dev, 463 struct panel_simple *panel) 464 { 465 struct display_timing *timing; 466 const struct device_node *np; 467 struct panel_desc *desc; 468 unsigned int bus_flags; 469 struct videomode vm; 470 int ret; 471 472 np = dev->of_node; 473 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 474 if (!desc) 475 return -ENOMEM; 476 477 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 478 if (!timing) 479 return -ENOMEM; 480 481 ret = of_get_display_timing(np, "panel-timing", timing); 482 if (ret < 0) { 483 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 484 np); 485 return ret; 486 } 487 488 desc->timings = timing; 489 desc->num_timings = 1; 490 491 of_property_read_u32(np, "width-mm", &desc->size.width); 492 of_property_read_u32(np, "height-mm", &desc->size.height); 493 494 /* Extract bus_flags from display_timing */ 495 bus_flags = 0; 496 vm.flags = timing->flags; 497 drm_bus_flags_from_videomode(&vm, &bus_flags); 498 desc->bus_flags = bus_flags; 499 500 /* We do not know the connector for the DT node, so guess it */ 501 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 502 503 panel->desc = desc; 504 505 return 0; 506 } 507 508 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 509 (to_check->field.typ >= bounds->field.min && \ 510 to_check->field.typ <= bounds->field.max) 511 static void panel_simple_parse_panel_timing_node(struct device *dev, 512 struct panel_simple *panel, 513 const struct display_timing *ot) 514 { 515 const struct panel_desc *desc = panel->desc; 516 struct videomode vm; 517 unsigned int i; 518 519 if (WARN_ON(desc->num_modes)) { 520 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 521 return; 522 } 523 if (WARN_ON(!desc->num_timings)) { 524 dev_err(dev, "Reject override mode: no timings specified\n"); 525 return; 526 } 527 528 for (i = 0; i < panel->desc->num_timings; i++) { 529 const struct display_timing *dt = &panel->desc->timings[i]; 530 531 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 537 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 538 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 539 continue; 540 541 if (ot->flags != dt->flags) 542 continue; 543 544 videomode_from_timing(ot, &vm); 545 drm_display_mode_from_videomode(&vm, &panel->override_mode); 546 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 547 DRM_MODE_TYPE_PREFERRED; 548 break; 549 } 550 551 if (WARN_ON(!panel->override_mode.type)) 552 dev_err(dev, "Reject override mode: No display_timing found\n"); 553 } 554 555 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 556 { 557 struct panel_simple *panel; 558 struct display_timing dt; 559 struct device_node *ddc; 560 int connector_type; 561 u32 bus_flags; 562 int err; 563 564 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 565 if (!panel) 566 return -ENOMEM; 567 568 panel->enabled = false; 569 panel->prepared_time = 0; 570 panel->desc = desc; 571 572 panel->supply = devm_regulator_get(dev, "power"); 573 if (IS_ERR(panel->supply)) 574 return PTR_ERR(panel->supply); 575 576 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 577 GPIOD_OUT_LOW); 578 if (IS_ERR(panel->enable_gpio)) 579 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 580 "failed to request GPIO\n"); 581 582 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 583 if (err) { 584 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 585 return err; 586 } 587 588 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 589 if (ddc) { 590 panel->ddc = of_find_i2c_adapter_by_node(ddc); 591 of_node_put(ddc); 592 593 if (!panel->ddc) 594 return -EPROBE_DEFER; 595 } 596 597 if (desc == &panel_dpi) { 598 /* Handle the generic panel-dpi binding */ 599 err = panel_dpi_probe(dev, panel); 600 if (err) 601 goto free_ddc; 602 desc = panel->desc; 603 } else { 604 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 605 panel_simple_parse_panel_timing_node(dev, panel, &dt); 606 } 607 608 connector_type = desc->connector_type; 609 /* Catch common mistakes for panels. */ 610 switch (connector_type) { 611 case 0: 612 dev_warn(dev, "Specify missing connector_type\n"); 613 connector_type = DRM_MODE_CONNECTOR_DPI; 614 break; 615 case DRM_MODE_CONNECTOR_LVDS: 616 WARN_ON(desc->bus_flags & 617 ~(DRM_BUS_FLAG_DE_LOW | 618 DRM_BUS_FLAG_DE_HIGH | 619 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 620 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 621 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 622 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 623 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 624 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 625 desc->bpc != 6); 626 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 627 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 628 desc->bpc != 8); 629 break; 630 case DRM_MODE_CONNECTOR_eDP: 631 dev_warn(dev, "eDP panels moved to panel-edp\n"); 632 err = -EINVAL; 633 goto free_ddc; 634 case DRM_MODE_CONNECTOR_DSI: 635 if (desc->bpc != 6 && desc->bpc != 8) 636 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 637 break; 638 case DRM_MODE_CONNECTOR_DPI: 639 bus_flags = DRM_BUS_FLAG_DE_LOW | 640 DRM_BUS_FLAG_DE_HIGH | 641 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 642 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 643 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 644 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 645 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 646 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 647 if (desc->bus_flags & ~bus_flags) 648 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 649 if (!(desc->bus_flags & bus_flags)) 650 dev_warn(dev, "Specify missing bus_flags\n"); 651 if (desc->bus_format == 0) 652 dev_warn(dev, "Specify missing bus_format\n"); 653 if (desc->bpc != 6 && desc->bpc != 8) 654 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 655 break; 656 default: 657 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 658 connector_type = DRM_MODE_CONNECTOR_DPI; 659 break; 660 } 661 662 dev_set_drvdata(dev, panel); 663 664 /* 665 * We use runtime PM for prepare / unprepare since those power the panel 666 * on and off and those can be very slow operations. This is important 667 * to optimize powering the panel on briefly to read the EDID before 668 * fully enabling the panel. 669 */ 670 pm_runtime_enable(dev); 671 pm_runtime_set_autosuspend_delay(dev, 1000); 672 pm_runtime_use_autosuspend(dev); 673 674 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 675 676 err = drm_panel_of_backlight(&panel->base); 677 if (err) { 678 dev_err_probe(dev, err, "Could not find backlight\n"); 679 goto disable_pm_runtime; 680 } 681 682 drm_panel_add(&panel->base); 683 684 return 0; 685 686 disable_pm_runtime: 687 pm_runtime_dont_use_autosuspend(dev); 688 pm_runtime_disable(dev); 689 free_ddc: 690 if (panel->ddc) 691 put_device(&panel->ddc->dev); 692 693 return err; 694 } 695 696 static void panel_simple_remove(struct device *dev) 697 { 698 struct panel_simple *panel = dev_get_drvdata(dev); 699 700 drm_panel_remove(&panel->base); 701 drm_panel_disable(&panel->base); 702 drm_panel_unprepare(&panel->base); 703 704 pm_runtime_dont_use_autosuspend(dev); 705 pm_runtime_disable(dev); 706 if (panel->ddc) 707 put_device(&panel->ddc->dev); 708 } 709 710 static void panel_simple_shutdown(struct device *dev) 711 { 712 struct panel_simple *panel = dev_get_drvdata(dev); 713 714 drm_panel_disable(&panel->base); 715 drm_panel_unprepare(&panel->base); 716 } 717 718 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 719 .clock = 71100, 720 .hdisplay = 1280, 721 .hsync_start = 1280 + 40, 722 .hsync_end = 1280 + 40 + 80, 723 .htotal = 1280 + 40 + 80 + 40, 724 .vdisplay = 800, 725 .vsync_start = 800 + 3, 726 .vsync_end = 800 + 3 + 10, 727 .vtotal = 800 + 3 + 10 + 10, 728 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 729 }; 730 731 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 732 .modes = &ire_am_1280800n3tzqw_t00h_mode, 733 .num_modes = 1, 734 .bpc = 8, 735 .size = { 736 .width = 217, 737 .height = 136, 738 }, 739 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 740 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 741 .connector_type = DRM_MODE_CONNECTOR_LVDS, 742 }; 743 744 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 745 .clock = 9000, 746 .hdisplay = 480, 747 .hsync_start = 480 + 2, 748 .hsync_end = 480 + 2 + 41, 749 .htotal = 480 + 2 + 41 + 2, 750 .vdisplay = 272, 751 .vsync_start = 272 + 2, 752 .vsync_end = 272 + 2 + 10, 753 .vtotal = 272 + 2 + 10 + 2, 754 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 755 }; 756 757 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 758 .modes = &ire_am_480272h3tmqw_t01h_mode, 759 .num_modes = 1, 760 .bpc = 8, 761 .size = { 762 .width = 105, 763 .height = 67, 764 }, 765 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 766 }; 767 768 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 769 .clock = 33333, 770 .hdisplay = 800, 771 .hsync_start = 800 + 0, 772 .hsync_end = 800 + 0 + 255, 773 .htotal = 800 + 0 + 255 + 0, 774 .vdisplay = 480, 775 .vsync_start = 480 + 2, 776 .vsync_end = 480 + 2 + 45, 777 .vtotal = 480 + 2 + 45 + 0, 778 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 779 }; 780 781 static const struct panel_desc ampire_am800480r3tmqwa1h = { 782 .modes = &ire_am800480r3tmqwa1h_mode, 783 .num_modes = 1, 784 .bpc = 6, 785 .size = { 786 .width = 152, 787 .height = 91, 788 }, 789 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 790 }; 791 792 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 793 .pixelclock = { 34500000, 39600000, 50400000 }, 794 .hactive = { 800, 800, 800 }, 795 .hfront_porch = { 12, 112, 312 }, 796 .hback_porch = { 87, 87, 48 }, 797 .hsync_len = { 1, 1, 40 }, 798 .vactive = { 600, 600, 600 }, 799 .vfront_porch = { 1, 21, 61 }, 800 .vback_porch = { 38, 38, 19 }, 801 .vsync_len = { 1, 1, 20 }, 802 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 803 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 804 DISPLAY_FLAGS_SYNC_POSEDGE, 805 }; 806 807 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 808 .timings = &ire_am800600p5tmqw_tb8h_timing, 809 .num_timings = 1, 810 .bpc = 6, 811 .size = { 812 .width = 162, 813 .height = 122, 814 }, 815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 816 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 817 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 818 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 819 .connector_type = DRM_MODE_CONNECTOR_DPI, 820 }; 821 822 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 823 .pixelclock = { 26400000, 33300000, 46800000 }, 824 .hactive = { 800, 800, 800 }, 825 .hfront_porch = { 16, 210, 354 }, 826 .hback_porch = { 45, 36, 6 }, 827 .hsync_len = { 1, 10, 40 }, 828 .vactive = { 480, 480, 480 }, 829 .vfront_porch = { 7, 22, 147 }, 830 .vback_porch = { 22, 13, 3 }, 831 .vsync_len = { 1, 10, 20 }, 832 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 833 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 834 }; 835 836 static const struct panel_desc armadeus_st0700_adapt = { 837 .timings = &santek_st0700i5y_rbslw_f_timing, 838 .num_timings = 1, 839 .bpc = 6, 840 .size = { 841 .width = 154, 842 .height = 86, 843 }, 844 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 845 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 846 }; 847 848 static const struct drm_display_mode auo_b101aw03_mode = { 849 .clock = 51450, 850 .hdisplay = 1024, 851 .hsync_start = 1024 + 156, 852 .hsync_end = 1024 + 156 + 8, 853 .htotal = 1024 + 156 + 8 + 156, 854 .vdisplay = 600, 855 .vsync_start = 600 + 16, 856 .vsync_end = 600 + 16 + 6, 857 .vtotal = 600 + 16 + 6 + 16, 858 }; 859 860 static const struct panel_desc auo_b101aw03 = { 861 .modes = &auo_b101aw03_mode, 862 .num_modes = 1, 863 .bpc = 6, 864 .size = { 865 .width = 223, 866 .height = 125, 867 }, 868 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 869 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 870 .connector_type = DRM_MODE_CONNECTOR_LVDS, 871 }; 872 873 static const struct drm_display_mode auo_b101xtn01_mode = { 874 .clock = 72000, 875 .hdisplay = 1366, 876 .hsync_start = 1366 + 20, 877 .hsync_end = 1366 + 20 + 70, 878 .htotal = 1366 + 20 + 70, 879 .vdisplay = 768, 880 .vsync_start = 768 + 14, 881 .vsync_end = 768 + 14 + 42, 882 .vtotal = 768 + 14 + 42, 883 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 884 }; 885 886 static const struct panel_desc auo_b101xtn01 = { 887 .modes = &auo_b101xtn01_mode, 888 .num_modes = 1, 889 .bpc = 6, 890 .size = { 891 .width = 223, 892 .height = 125, 893 }, 894 }; 895 896 static const struct display_timing auo_g070vvn01_timings = { 897 .pixelclock = { 33300000, 34209000, 45000000 }, 898 .hactive = { 800, 800, 800 }, 899 .hfront_porch = { 20, 40, 200 }, 900 .hback_porch = { 87, 40, 1 }, 901 .hsync_len = { 1, 48, 87 }, 902 .vactive = { 480, 480, 480 }, 903 .vfront_porch = { 5, 13, 200 }, 904 .vback_porch = { 31, 31, 29 }, 905 .vsync_len = { 1, 1, 3 }, 906 }; 907 908 static const struct panel_desc auo_g070vvn01 = { 909 .timings = &auo_g070vvn01_timings, 910 .num_timings = 1, 911 .bpc = 8, 912 .size = { 913 .width = 152, 914 .height = 91, 915 }, 916 .delay = { 917 .prepare = 200, 918 .enable = 50, 919 .disable = 50, 920 .unprepare = 1000, 921 }, 922 }; 923 924 static const struct drm_display_mode auo_g101evn010_mode = { 925 .clock = 68930, 926 .hdisplay = 1280, 927 .hsync_start = 1280 + 82, 928 .hsync_end = 1280 + 82 + 2, 929 .htotal = 1280 + 82 + 2 + 84, 930 .vdisplay = 800, 931 .vsync_start = 800 + 8, 932 .vsync_end = 800 + 8 + 2, 933 .vtotal = 800 + 8 + 2 + 6, 934 }; 935 936 static const struct panel_desc auo_g101evn010 = { 937 .modes = &auo_g101evn010_mode, 938 .num_modes = 1, 939 .bpc = 6, 940 .size = { 941 .width = 216, 942 .height = 135, 943 }, 944 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 945 .connector_type = DRM_MODE_CONNECTOR_LVDS, 946 }; 947 948 static const struct drm_display_mode auo_g104sn02_mode = { 949 .clock = 40000, 950 .hdisplay = 800, 951 .hsync_start = 800 + 40, 952 .hsync_end = 800 + 40 + 216, 953 .htotal = 800 + 40 + 216 + 128, 954 .vdisplay = 600, 955 .vsync_start = 600 + 10, 956 .vsync_end = 600 + 10 + 35, 957 .vtotal = 600 + 10 + 35 + 2, 958 }; 959 960 static const struct panel_desc auo_g104sn02 = { 961 .modes = &auo_g104sn02_mode, 962 .num_modes = 1, 963 .bpc = 8, 964 .size = { 965 .width = 211, 966 .height = 158, 967 }, 968 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 969 .connector_type = DRM_MODE_CONNECTOR_LVDS, 970 }; 971 972 static const struct drm_display_mode auo_g121ean01_mode = { 973 .clock = 66700, 974 .hdisplay = 1280, 975 .hsync_start = 1280 + 58, 976 .hsync_end = 1280 + 58 + 8, 977 .htotal = 1280 + 58 + 8 + 70, 978 .vdisplay = 800, 979 .vsync_start = 800 + 6, 980 .vsync_end = 800 + 6 + 4, 981 .vtotal = 800 + 6 + 4 + 10, 982 }; 983 984 static const struct panel_desc auo_g121ean01 = { 985 .modes = &auo_g121ean01_mode, 986 .num_modes = 1, 987 .bpc = 8, 988 .size = { 989 .width = 261, 990 .height = 163, 991 }, 992 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 993 .connector_type = DRM_MODE_CONNECTOR_LVDS, 994 }; 995 996 static const struct display_timing auo_g133han01_timings = { 997 .pixelclock = { 134000000, 141200000, 149000000 }, 998 .hactive = { 1920, 1920, 1920 }, 999 .hfront_porch = { 39, 58, 77 }, 1000 .hback_porch = { 59, 88, 117 }, 1001 .hsync_len = { 28, 42, 56 }, 1002 .vactive = { 1080, 1080, 1080 }, 1003 .vfront_porch = { 3, 8, 11 }, 1004 .vback_porch = { 5, 14, 19 }, 1005 .vsync_len = { 4, 14, 19 }, 1006 }; 1007 1008 static const struct panel_desc auo_g133han01 = { 1009 .timings = &auo_g133han01_timings, 1010 .num_timings = 1, 1011 .bpc = 8, 1012 .size = { 1013 .width = 293, 1014 .height = 165, 1015 }, 1016 .delay = { 1017 .prepare = 200, 1018 .enable = 50, 1019 .disable = 50, 1020 .unprepare = 1000, 1021 }, 1022 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1023 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1024 }; 1025 1026 static const struct drm_display_mode auo_g156xtn01_mode = { 1027 .clock = 76000, 1028 .hdisplay = 1366, 1029 .hsync_start = 1366 + 33, 1030 .hsync_end = 1366 + 33 + 67, 1031 .htotal = 1560, 1032 .vdisplay = 768, 1033 .vsync_start = 768 + 4, 1034 .vsync_end = 768 + 4 + 4, 1035 .vtotal = 806, 1036 }; 1037 1038 static const struct panel_desc auo_g156xtn01 = { 1039 .modes = &auo_g156xtn01_mode, 1040 .num_modes = 1, 1041 .bpc = 8, 1042 .size = { 1043 .width = 344, 1044 .height = 194, 1045 }, 1046 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1047 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1048 }; 1049 1050 static const struct display_timing auo_g185han01_timings = { 1051 .pixelclock = { 120000000, 144000000, 175000000 }, 1052 .hactive = { 1920, 1920, 1920 }, 1053 .hfront_porch = { 36, 120, 148 }, 1054 .hback_porch = { 24, 88, 108 }, 1055 .hsync_len = { 20, 48, 64 }, 1056 .vactive = { 1080, 1080, 1080 }, 1057 .vfront_porch = { 6, 10, 40 }, 1058 .vback_porch = { 2, 5, 20 }, 1059 .vsync_len = { 2, 5, 20 }, 1060 }; 1061 1062 static const struct panel_desc auo_g185han01 = { 1063 .timings = &auo_g185han01_timings, 1064 .num_timings = 1, 1065 .bpc = 8, 1066 .size = { 1067 .width = 409, 1068 .height = 230, 1069 }, 1070 .delay = { 1071 .prepare = 50, 1072 .enable = 200, 1073 .disable = 110, 1074 .unprepare = 1000, 1075 }, 1076 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1077 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1078 }; 1079 1080 static const struct display_timing auo_g190ean01_timings = { 1081 .pixelclock = { 90000000, 108000000, 135000000 }, 1082 .hactive = { 1280, 1280, 1280 }, 1083 .hfront_porch = { 126, 184, 1266 }, 1084 .hback_porch = { 84, 122, 844 }, 1085 .hsync_len = { 70, 102, 704 }, 1086 .vactive = { 1024, 1024, 1024 }, 1087 .vfront_porch = { 4, 26, 76 }, 1088 .vback_porch = { 2, 8, 25 }, 1089 .vsync_len = { 2, 8, 25 }, 1090 }; 1091 1092 static const struct panel_desc auo_g190ean01 = { 1093 .timings = &auo_g190ean01_timings, 1094 .num_timings = 1, 1095 .bpc = 8, 1096 .size = { 1097 .width = 376, 1098 .height = 301, 1099 }, 1100 .delay = { 1101 .prepare = 50, 1102 .enable = 200, 1103 .disable = 110, 1104 .unprepare = 1000, 1105 }, 1106 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1107 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1108 }; 1109 1110 static const struct display_timing auo_p320hvn03_timings = { 1111 .pixelclock = { 106000000, 148500000, 164000000 }, 1112 .hactive = { 1920, 1920, 1920 }, 1113 .hfront_porch = { 25, 50, 130 }, 1114 .hback_porch = { 25, 50, 130 }, 1115 .hsync_len = { 20, 40, 105 }, 1116 .vactive = { 1080, 1080, 1080 }, 1117 .vfront_porch = { 8, 17, 150 }, 1118 .vback_porch = { 8, 17, 150 }, 1119 .vsync_len = { 4, 11, 100 }, 1120 }; 1121 1122 static const struct panel_desc auo_p320hvn03 = { 1123 .timings = &auo_p320hvn03_timings, 1124 .num_timings = 1, 1125 .bpc = 8, 1126 .size = { 1127 .width = 698, 1128 .height = 393, 1129 }, 1130 .delay = { 1131 .prepare = 1, 1132 .enable = 450, 1133 .unprepare = 500, 1134 }, 1135 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1136 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1137 }; 1138 1139 static const struct drm_display_mode auo_t215hvn01_mode = { 1140 .clock = 148800, 1141 .hdisplay = 1920, 1142 .hsync_start = 1920 + 88, 1143 .hsync_end = 1920 + 88 + 44, 1144 .htotal = 1920 + 88 + 44 + 148, 1145 .vdisplay = 1080, 1146 .vsync_start = 1080 + 4, 1147 .vsync_end = 1080 + 4 + 5, 1148 .vtotal = 1080 + 4 + 5 + 36, 1149 }; 1150 1151 static const struct panel_desc auo_t215hvn01 = { 1152 .modes = &auo_t215hvn01_mode, 1153 .num_modes = 1, 1154 .bpc = 8, 1155 .size = { 1156 .width = 430, 1157 .height = 270, 1158 }, 1159 .delay = { 1160 .disable = 5, 1161 .unprepare = 1000, 1162 } 1163 }; 1164 1165 static const struct drm_display_mode avic_tm070ddh03_mode = { 1166 .clock = 51200, 1167 .hdisplay = 1024, 1168 .hsync_start = 1024 + 160, 1169 .hsync_end = 1024 + 160 + 4, 1170 .htotal = 1024 + 160 + 4 + 156, 1171 .vdisplay = 600, 1172 .vsync_start = 600 + 17, 1173 .vsync_end = 600 + 17 + 1, 1174 .vtotal = 600 + 17 + 1 + 17, 1175 }; 1176 1177 static const struct panel_desc avic_tm070ddh03 = { 1178 .modes = &avic_tm070ddh03_mode, 1179 .num_modes = 1, 1180 .bpc = 8, 1181 .size = { 1182 .width = 154, 1183 .height = 90, 1184 }, 1185 .delay = { 1186 .prepare = 20, 1187 .enable = 200, 1188 .disable = 200, 1189 }, 1190 }; 1191 1192 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1193 .clock = 30000, 1194 .hdisplay = 800, 1195 .hsync_start = 800 + 40, 1196 .hsync_end = 800 + 40 + 48, 1197 .htotal = 800 + 40 + 48 + 40, 1198 .vdisplay = 480, 1199 .vsync_start = 480 + 13, 1200 .vsync_end = 480 + 13 + 3, 1201 .vtotal = 480 + 13 + 3 + 29, 1202 }; 1203 1204 static const struct panel_desc bananapi_s070wv20_ct16 = { 1205 .modes = &bananapi_s070wv20_ct16_mode, 1206 .num_modes = 1, 1207 .bpc = 6, 1208 .size = { 1209 .width = 154, 1210 .height = 86, 1211 }, 1212 }; 1213 1214 static const struct drm_display_mode boe_hv070wsa_mode = { 1215 .clock = 42105, 1216 .hdisplay = 1024, 1217 .hsync_start = 1024 + 30, 1218 .hsync_end = 1024 + 30 + 30, 1219 .htotal = 1024 + 30 + 30 + 30, 1220 .vdisplay = 600, 1221 .vsync_start = 600 + 10, 1222 .vsync_end = 600 + 10 + 10, 1223 .vtotal = 600 + 10 + 10 + 10, 1224 }; 1225 1226 static const struct panel_desc boe_hv070wsa = { 1227 .modes = &boe_hv070wsa_mode, 1228 .num_modes = 1, 1229 .bpc = 8, 1230 .size = { 1231 .width = 154, 1232 .height = 90, 1233 }, 1234 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1235 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1236 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1237 }; 1238 1239 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1240 .clock = 9000, 1241 .hdisplay = 480, 1242 .hsync_start = 480 + 5, 1243 .hsync_end = 480 + 5 + 5, 1244 .htotal = 480 + 5 + 5 + 40, 1245 .vdisplay = 272, 1246 .vsync_start = 272 + 8, 1247 .vsync_end = 272 + 8 + 8, 1248 .vtotal = 272 + 8 + 8 + 8, 1249 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1250 }; 1251 1252 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1253 .modes = &cdtech_s043wq26h_ct7_mode, 1254 .num_modes = 1, 1255 .bpc = 8, 1256 .size = { 1257 .width = 95, 1258 .height = 54, 1259 }, 1260 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1261 }; 1262 1263 /* S070PWS19HP-FC21 2017/04/22 */ 1264 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1265 .clock = 51200, 1266 .hdisplay = 1024, 1267 .hsync_start = 1024 + 160, 1268 .hsync_end = 1024 + 160 + 20, 1269 .htotal = 1024 + 160 + 20 + 140, 1270 .vdisplay = 600, 1271 .vsync_start = 600 + 12, 1272 .vsync_end = 600 + 12 + 3, 1273 .vtotal = 600 + 12 + 3 + 20, 1274 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1275 }; 1276 1277 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1278 .modes = &cdtech_s070pws19hp_fc21_mode, 1279 .num_modes = 1, 1280 .bpc = 6, 1281 .size = { 1282 .width = 154, 1283 .height = 86, 1284 }, 1285 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1286 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1287 .connector_type = DRM_MODE_CONNECTOR_DPI, 1288 }; 1289 1290 /* S070SWV29HG-DC44 2017/09/21 */ 1291 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1292 .clock = 33300, 1293 .hdisplay = 800, 1294 .hsync_start = 800 + 210, 1295 .hsync_end = 800 + 210 + 2, 1296 .htotal = 800 + 210 + 2 + 44, 1297 .vdisplay = 480, 1298 .vsync_start = 480 + 22, 1299 .vsync_end = 480 + 22 + 2, 1300 .vtotal = 480 + 22 + 2 + 21, 1301 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1302 }; 1303 1304 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1305 .modes = &cdtech_s070swv29hg_dc44_mode, 1306 .num_modes = 1, 1307 .bpc = 6, 1308 .size = { 1309 .width = 154, 1310 .height = 86, 1311 }, 1312 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1313 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1314 .connector_type = DRM_MODE_CONNECTOR_DPI, 1315 }; 1316 1317 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1318 .clock = 35000, 1319 .hdisplay = 800, 1320 .hsync_start = 800 + 40, 1321 .hsync_end = 800 + 40 + 40, 1322 .htotal = 800 + 40 + 40 + 48, 1323 .vdisplay = 480, 1324 .vsync_start = 480 + 29, 1325 .vsync_end = 480 + 29 + 13, 1326 .vtotal = 480 + 29 + 13 + 3, 1327 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1328 }; 1329 1330 static const struct panel_desc cdtech_s070wv95_ct16 = { 1331 .modes = &cdtech_s070wv95_ct16_mode, 1332 .num_modes = 1, 1333 .bpc = 8, 1334 .size = { 1335 .width = 154, 1336 .height = 85, 1337 }, 1338 }; 1339 1340 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1341 .pixelclock = { 68900000, 71100000, 73400000 }, 1342 .hactive = { 1280, 1280, 1280 }, 1343 .hfront_porch = { 65, 80, 95 }, 1344 .hback_porch = { 64, 79, 94 }, 1345 .hsync_len = { 1, 1, 1 }, 1346 .vactive = { 800, 800, 800 }, 1347 .vfront_porch = { 7, 11, 14 }, 1348 .vback_porch = { 7, 11, 14 }, 1349 .vsync_len = { 1, 1, 1 }, 1350 .flags = DISPLAY_FLAGS_DE_HIGH, 1351 }; 1352 1353 static const struct panel_desc chefree_ch101olhlwh_002 = { 1354 .timings = &chefree_ch101olhlwh_002_timing, 1355 .num_timings = 1, 1356 .bpc = 8, 1357 .size = { 1358 .width = 217, 1359 .height = 135, 1360 }, 1361 .delay = { 1362 .enable = 200, 1363 .disable = 200, 1364 }, 1365 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1366 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1367 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1368 }; 1369 1370 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1371 .clock = 66770, 1372 .hdisplay = 800, 1373 .hsync_start = 800 + 49, 1374 .hsync_end = 800 + 49 + 33, 1375 .htotal = 800 + 49 + 33 + 17, 1376 .vdisplay = 1280, 1377 .vsync_start = 1280 + 1, 1378 .vsync_end = 1280 + 1 + 7, 1379 .vtotal = 1280 + 1 + 7 + 15, 1380 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1381 }; 1382 1383 static const struct panel_desc chunghwa_claa070wp03xg = { 1384 .modes = &chunghwa_claa070wp03xg_mode, 1385 .num_modes = 1, 1386 .bpc = 6, 1387 .size = { 1388 .width = 94, 1389 .height = 150, 1390 }, 1391 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1392 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1393 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1394 }; 1395 1396 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1397 .clock = 72070, 1398 .hdisplay = 1366, 1399 .hsync_start = 1366 + 58, 1400 .hsync_end = 1366 + 58 + 58, 1401 .htotal = 1366 + 58 + 58 + 58, 1402 .vdisplay = 768, 1403 .vsync_start = 768 + 4, 1404 .vsync_end = 768 + 4 + 4, 1405 .vtotal = 768 + 4 + 4 + 4, 1406 }; 1407 1408 static const struct panel_desc chunghwa_claa101wa01a = { 1409 .modes = &chunghwa_claa101wa01a_mode, 1410 .num_modes = 1, 1411 .bpc = 6, 1412 .size = { 1413 .width = 220, 1414 .height = 120, 1415 }, 1416 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1417 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1418 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1419 }; 1420 1421 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1422 .clock = 69300, 1423 .hdisplay = 1366, 1424 .hsync_start = 1366 + 48, 1425 .hsync_end = 1366 + 48 + 32, 1426 .htotal = 1366 + 48 + 32 + 20, 1427 .vdisplay = 768, 1428 .vsync_start = 768 + 16, 1429 .vsync_end = 768 + 16 + 8, 1430 .vtotal = 768 + 16 + 8 + 16, 1431 }; 1432 1433 static const struct panel_desc chunghwa_claa101wb01 = { 1434 .modes = &chunghwa_claa101wb01_mode, 1435 .num_modes = 1, 1436 .bpc = 6, 1437 .size = { 1438 .width = 223, 1439 .height = 125, 1440 }, 1441 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1442 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1443 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1444 }; 1445 1446 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1447 .pixelclock = { 5000000, 9000000, 12000000 }, 1448 .hactive = { 480, 480, 480 }, 1449 .hfront_porch = { 12, 12, 12 }, 1450 .hback_porch = { 12, 12, 12 }, 1451 .hsync_len = { 21, 21, 21 }, 1452 .vactive = { 272, 272, 272 }, 1453 .vfront_porch = { 4, 4, 4 }, 1454 .vback_porch = { 4, 4, 4 }, 1455 .vsync_len = { 8, 8, 8 }, 1456 }; 1457 1458 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1459 .timings = &dataimage_fg040346dsswbg04_timing, 1460 .num_timings = 1, 1461 .bpc = 8, 1462 .size = { 1463 .width = 95, 1464 .height = 54, 1465 }, 1466 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1467 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1468 .connector_type = DRM_MODE_CONNECTOR_DPI, 1469 }; 1470 1471 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1472 .pixelclock = { 68900000, 71110000, 73400000 }, 1473 .hactive = { 1280, 1280, 1280 }, 1474 .vactive = { 800, 800, 800 }, 1475 .hback_porch = { 100, 100, 100 }, 1476 .hfront_porch = { 100, 100, 100 }, 1477 .vback_porch = { 5, 5, 5 }, 1478 .vfront_porch = { 5, 5, 5 }, 1479 .hsync_len = { 24, 24, 24 }, 1480 .vsync_len = { 3, 3, 3 }, 1481 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1482 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1483 }; 1484 1485 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1486 .timings = &dataimage_fg1001l0dsswmg01_timing, 1487 .num_timings = 1, 1488 .bpc = 8, 1489 .size = { 1490 .width = 217, 1491 .height = 136, 1492 }, 1493 }; 1494 1495 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1496 .clock = 33260, 1497 .hdisplay = 800, 1498 .hsync_start = 800 + 40, 1499 .hsync_end = 800 + 40 + 128, 1500 .htotal = 800 + 40 + 128 + 88, 1501 .vdisplay = 480, 1502 .vsync_start = 480 + 10, 1503 .vsync_end = 480 + 10 + 2, 1504 .vtotal = 480 + 10 + 2 + 33, 1505 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1506 }; 1507 1508 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1509 .modes = &dataimage_scf0700c48ggu18_mode, 1510 .num_modes = 1, 1511 .bpc = 8, 1512 .size = { 1513 .width = 152, 1514 .height = 91, 1515 }, 1516 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1517 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1518 }; 1519 1520 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1521 .pixelclock = { 45000000, 51200000, 57000000 }, 1522 .hactive = { 1024, 1024, 1024 }, 1523 .hfront_porch = { 100, 106, 113 }, 1524 .hback_porch = { 100, 106, 113 }, 1525 .hsync_len = { 100, 108, 114 }, 1526 .vactive = { 600, 600, 600 }, 1527 .vfront_porch = { 8, 11, 15 }, 1528 .vback_porch = { 8, 11, 15 }, 1529 .vsync_len = { 9, 13, 15 }, 1530 .flags = DISPLAY_FLAGS_DE_HIGH, 1531 }; 1532 1533 static const struct panel_desc dlc_dlc0700yzg_1 = { 1534 .timings = &dlc_dlc0700yzg_1_timing, 1535 .num_timings = 1, 1536 .bpc = 6, 1537 .size = { 1538 .width = 154, 1539 .height = 86, 1540 }, 1541 .delay = { 1542 .prepare = 30, 1543 .enable = 200, 1544 .disable = 200, 1545 }, 1546 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1547 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1548 }; 1549 1550 static const struct display_timing dlc_dlc1010gig_timing = { 1551 .pixelclock = { 68900000, 71100000, 73400000 }, 1552 .hactive = { 1280, 1280, 1280 }, 1553 .hfront_porch = { 43, 53, 63 }, 1554 .hback_porch = { 43, 53, 63 }, 1555 .hsync_len = { 44, 54, 64 }, 1556 .vactive = { 800, 800, 800 }, 1557 .vfront_porch = { 5, 8, 11 }, 1558 .vback_porch = { 5, 8, 11 }, 1559 .vsync_len = { 5, 7, 11 }, 1560 .flags = DISPLAY_FLAGS_DE_HIGH, 1561 }; 1562 1563 static const struct panel_desc dlc_dlc1010gig = { 1564 .timings = &dlc_dlc1010gig_timing, 1565 .num_timings = 1, 1566 .bpc = 8, 1567 .size = { 1568 .width = 216, 1569 .height = 135, 1570 }, 1571 .delay = { 1572 .prepare = 60, 1573 .enable = 150, 1574 .disable = 100, 1575 .unprepare = 60, 1576 }, 1577 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1578 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1579 }; 1580 1581 static const struct drm_display_mode edt_et035012dm6_mode = { 1582 .clock = 6500, 1583 .hdisplay = 320, 1584 .hsync_start = 320 + 20, 1585 .hsync_end = 320 + 20 + 30, 1586 .htotal = 320 + 20 + 68, 1587 .vdisplay = 240, 1588 .vsync_start = 240 + 4, 1589 .vsync_end = 240 + 4 + 4, 1590 .vtotal = 240 + 4 + 4 + 14, 1591 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1592 }; 1593 1594 static const struct panel_desc edt_et035012dm6 = { 1595 .modes = &edt_et035012dm6_mode, 1596 .num_modes = 1, 1597 .bpc = 8, 1598 .size = { 1599 .width = 70, 1600 .height = 52, 1601 }, 1602 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1603 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1604 }; 1605 1606 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1607 .clock = 6520, 1608 .hdisplay = 320, 1609 .hsync_start = 320 + 20, 1610 .hsync_end = 320 + 20 + 68, 1611 .htotal = 320 + 20 + 68, 1612 .vdisplay = 240, 1613 .vsync_start = 240 + 4, 1614 .vsync_end = 240 + 4 + 18, 1615 .vtotal = 240 + 4 + 18, 1616 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1617 }; 1618 1619 static const struct panel_desc edt_etm0350g0dh6 = { 1620 .modes = &edt_etm0350g0dh6_mode, 1621 .num_modes = 1, 1622 .bpc = 6, 1623 .size = { 1624 .width = 70, 1625 .height = 53, 1626 }, 1627 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1628 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1629 .connector_type = DRM_MODE_CONNECTOR_DPI, 1630 }; 1631 1632 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1633 .clock = 10870, 1634 .hdisplay = 480, 1635 .hsync_start = 480 + 8, 1636 .hsync_end = 480 + 8 + 4, 1637 .htotal = 480 + 8 + 4 + 41, 1638 1639 /* 1640 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1641 * fb_align 1642 */ 1643 1644 .vdisplay = 288, 1645 .vsync_start = 288 + 2, 1646 .vsync_end = 288 + 2 + 4, 1647 .vtotal = 288 + 2 + 4 + 10, 1648 }; 1649 1650 static const struct panel_desc edt_etm043080dh6gp = { 1651 .modes = &edt_etm043080dh6gp_mode, 1652 .num_modes = 1, 1653 .bpc = 8, 1654 .size = { 1655 .width = 100, 1656 .height = 65, 1657 }, 1658 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1659 .connector_type = DRM_MODE_CONNECTOR_DPI, 1660 }; 1661 1662 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1663 .clock = 9000, 1664 .hdisplay = 480, 1665 .hsync_start = 480 + 2, 1666 .hsync_end = 480 + 2 + 41, 1667 .htotal = 480 + 2 + 41 + 2, 1668 .vdisplay = 272, 1669 .vsync_start = 272 + 2, 1670 .vsync_end = 272 + 2 + 10, 1671 .vtotal = 272 + 2 + 10 + 2, 1672 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1673 }; 1674 1675 static const struct panel_desc edt_etm0430g0dh6 = { 1676 .modes = &edt_etm0430g0dh6_mode, 1677 .num_modes = 1, 1678 .bpc = 6, 1679 .size = { 1680 .width = 95, 1681 .height = 54, 1682 }, 1683 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1684 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1685 .connector_type = DRM_MODE_CONNECTOR_DPI, 1686 }; 1687 1688 static const struct drm_display_mode edt_et057090dhu_mode = { 1689 .clock = 25175, 1690 .hdisplay = 640, 1691 .hsync_start = 640 + 16, 1692 .hsync_end = 640 + 16 + 30, 1693 .htotal = 640 + 16 + 30 + 114, 1694 .vdisplay = 480, 1695 .vsync_start = 480 + 10, 1696 .vsync_end = 480 + 10 + 3, 1697 .vtotal = 480 + 10 + 3 + 32, 1698 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1699 }; 1700 1701 static const struct panel_desc edt_et057090dhu = { 1702 .modes = &edt_et057090dhu_mode, 1703 .num_modes = 1, 1704 .bpc = 6, 1705 .size = { 1706 .width = 115, 1707 .height = 86, 1708 }, 1709 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1710 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1711 .connector_type = DRM_MODE_CONNECTOR_DPI, 1712 }; 1713 1714 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1715 .clock = 33260, 1716 .hdisplay = 800, 1717 .hsync_start = 800 + 40, 1718 .hsync_end = 800 + 40 + 128, 1719 .htotal = 800 + 40 + 128 + 88, 1720 .vdisplay = 480, 1721 .vsync_start = 480 + 10, 1722 .vsync_end = 480 + 10 + 2, 1723 .vtotal = 480 + 10 + 2 + 33, 1724 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1725 }; 1726 1727 static const struct panel_desc edt_etm0700g0dh6 = { 1728 .modes = &edt_etm0700g0dh6_mode, 1729 .num_modes = 1, 1730 .bpc = 6, 1731 .size = { 1732 .width = 152, 1733 .height = 91, 1734 }, 1735 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1736 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1737 .connector_type = DRM_MODE_CONNECTOR_DPI, 1738 }; 1739 1740 static const struct panel_desc edt_etm0700g0bdh6 = { 1741 .modes = &edt_etm0700g0dh6_mode, 1742 .num_modes = 1, 1743 .bpc = 6, 1744 .size = { 1745 .width = 152, 1746 .height = 91, 1747 }, 1748 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1749 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1750 .connector_type = DRM_MODE_CONNECTOR_DPI, 1751 }; 1752 1753 static const struct display_timing edt_etml0700y5dha_timing = { 1754 .pixelclock = { 40800000, 51200000, 67200000 }, 1755 .hactive = { 1024, 1024, 1024 }, 1756 .hfront_porch = { 30, 106, 125 }, 1757 .hback_porch = { 30, 106, 125 }, 1758 .hsync_len = { 30, 108, 126 }, 1759 .vactive = { 600, 600, 600 }, 1760 .vfront_porch = { 3, 12, 67}, 1761 .vback_porch = { 3, 12, 67 }, 1762 .vsync_len = { 4, 11, 66 }, 1763 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1764 DISPLAY_FLAGS_DE_HIGH, 1765 }; 1766 1767 static const struct panel_desc edt_etml0700y5dha = { 1768 .timings = &edt_etml0700y5dha_timing, 1769 .num_timings = 1, 1770 .bpc = 8, 1771 .size = { 1772 .width = 155, 1773 .height = 86, 1774 }, 1775 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1776 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1777 }; 1778 1779 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1780 .clock = 25175, 1781 .hdisplay = 640, 1782 .hsync_start = 640, 1783 .hsync_end = 640 + 16, 1784 .htotal = 640 + 16 + 30 + 114, 1785 .vdisplay = 480, 1786 .vsync_start = 480 + 10, 1787 .vsync_end = 480 + 10 + 3, 1788 .vtotal = 480 + 10 + 3 + 35, 1789 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1790 }; 1791 1792 static const struct panel_desc edt_etmv570g2dhu = { 1793 .modes = &edt_etmv570g2dhu_mode, 1794 .num_modes = 1, 1795 .bpc = 6, 1796 .size = { 1797 .width = 115, 1798 .height = 86, 1799 }, 1800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1802 .connector_type = DRM_MODE_CONNECTOR_DPI, 1803 }; 1804 1805 static const struct display_timing eink_vb3300_kca_timing = { 1806 .pixelclock = { 40000000, 40000000, 40000000 }, 1807 .hactive = { 334, 334, 334 }, 1808 .hfront_porch = { 1, 1, 1 }, 1809 .hback_porch = { 1, 1, 1 }, 1810 .hsync_len = { 1, 1, 1 }, 1811 .vactive = { 1405, 1405, 1405 }, 1812 .vfront_porch = { 1, 1, 1 }, 1813 .vback_porch = { 1, 1, 1 }, 1814 .vsync_len = { 1, 1, 1 }, 1815 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1816 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1817 }; 1818 1819 static const struct panel_desc eink_vb3300_kca = { 1820 .timings = &eink_vb3300_kca_timing, 1821 .num_timings = 1, 1822 .bpc = 6, 1823 .size = { 1824 .width = 157, 1825 .height = 209, 1826 }, 1827 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1828 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1829 .connector_type = DRM_MODE_CONNECTOR_DPI, 1830 }; 1831 1832 static const struct display_timing evervision_vgg804821_timing = { 1833 .pixelclock = { 27600000, 33300000, 50000000 }, 1834 .hactive = { 800, 800, 800 }, 1835 .hfront_porch = { 40, 66, 70 }, 1836 .hback_porch = { 40, 67, 70 }, 1837 .hsync_len = { 40, 67, 70 }, 1838 .vactive = { 480, 480, 480 }, 1839 .vfront_porch = { 6, 10, 10 }, 1840 .vback_porch = { 7, 11, 11 }, 1841 .vsync_len = { 7, 11, 11 }, 1842 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1843 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1844 DISPLAY_FLAGS_SYNC_NEGEDGE, 1845 }; 1846 1847 static const struct panel_desc evervision_vgg804821 = { 1848 .timings = &evervision_vgg804821_timing, 1849 .num_timings = 1, 1850 .bpc = 8, 1851 .size = { 1852 .width = 108, 1853 .height = 64, 1854 }, 1855 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1856 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1857 }; 1858 1859 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1860 .clock = 32260, 1861 .hdisplay = 800, 1862 .hsync_start = 800 + 168, 1863 .hsync_end = 800 + 168 + 64, 1864 .htotal = 800 + 168 + 64 + 88, 1865 .vdisplay = 480, 1866 .vsync_start = 480 + 37, 1867 .vsync_end = 480 + 37 + 2, 1868 .vtotal = 480 + 37 + 2 + 8, 1869 }; 1870 1871 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1872 .modes = &foxlink_fl500wvr00_a0t_mode, 1873 .num_modes = 1, 1874 .bpc = 8, 1875 .size = { 1876 .width = 108, 1877 .height = 65, 1878 }, 1879 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1880 }; 1881 1882 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1883 { /* 60 Hz */ 1884 .clock = 6000, 1885 .hdisplay = 320, 1886 .hsync_start = 320 + 44, 1887 .hsync_end = 320 + 44 + 16, 1888 .htotal = 320 + 44 + 16 + 20, 1889 .vdisplay = 240, 1890 .vsync_start = 240 + 2, 1891 .vsync_end = 240 + 2 + 6, 1892 .vtotal = 240 + 2 + 6 + 2, 1893 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1894 }, 1895 { /* 50 Hz */ 1896 .clock = 5400, 1897 .hdisplay = 320, 1898 .hsync_start = 320 + 56, 1899 .hsync_end = 320 + 56 + 16, 1900 .htotal = 320 + 56 + 16 + 40, 1901 .vdisplay = 240, 1902 .vsync_start = 240 + 2, 1903 .vsync_end = 240 + 2 + 6, 1904 .vtotal = 240 + 2 + 6 + 2, 1905 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1906 }, 1907 }; 1908 1909 static const struct panel_desc frida_frd350h54004 = { 1910 .modes = frida_frd350h54004_modes, 1911 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1912 .bpc = 8, 1913 .size = { 1914 .width = 77, 1915 .height = 64, 1916 }, 1917 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1918 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1919 .connector_type = DRM_MODE_CONNECTOR_DPI, 1920 }; 1921 1922 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1923 .clock = 67185, 1924 .hdisplay = 800, 1925 .hsync_start = 800 + 20, 1926 .hsync_end = 800 + 20 + 24, 1927 .htotal = 800 + 20 + 24 + 20, 1928 .vdisplay = 1280, 1929 .vsync_start = 1280 + 4, 1930 .vsync_end = 1280 + 4 + 8, 1931 .vtotal = 1280 + 4 + 8 + 4, 1932 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1933 }; 1934 1935 static const struct panel_desc friendlyarm_hd702e = { 1936 .modes = &friendlyarm_hd702e_mode, 1937 .num_modes = 1, 1938 .size = { 1939 .width = 94, 1940 .height = 151, 1941 }, 1942 }; 1943 1944 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1945 .clock = 9000, 1946 .hdisplay = 480, 1947 .hsync_start = 480 + 5, 1948 .hsync_end = 480 + 5 + 1, 1949 .htotal = 480 + 5 + 1 + 40, 1950 .vdisplay = 272, 1951 .vsync_start = 272 + 8, 1952 .vsync_end = 272 + 8 + 1, 1953 .vtotal = 272 + 8 + 1 + 8, 1954 }; 1955 1956 static const struct panel_desc giantplus_gpg482739qs5 = { 1957 .modes = &giantplus_gpg482739qs5_mode, 1958 .num_modes = 1, 1959 .bpc = 8, 1960 .size = { 1961 .width = 95, 1962 .height = 54, 1963 }, 1964 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1965 }; 1966 1967 static const struct display_timing giantplus_gpm940b0_timing = { 1968 .pixelclock = { 13500000, 27000000, 27500000 }, 1969 .hactive = { 320, 320, 320 }, 1970 .hfront_porch = { 14, 686, 718 }, 1971 .hback_porch = { 50, 70, 255 }, 1972 .hsync_len = { 1, 1, 1 }, 1973 .vactive = { 240, 240, 240 }, 1974 .vfront_porch = { 1, 1, 179 }, 1975 .vback_porch = { 1, 21, 31 }, 1976 .vsync_len = { 1, 1, 6 }, 1977 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1978 }; 1979 1980 static const struct panel_desc giantplus_gpm940b0 = { 1981 .timings = &giantplus_gpm940b0_timing, 1982 .num_timings = 1, 1983 .bpc = 8, 1984 .size = { 1985 .width = 60, 1986 .height = 45, 1987 }, 1988 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1989 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1990 }; 1991 1992 static const struct display_timing hannstar_hsd070pww1_timing = { 1993 .pixelclock = { 64300000, 71100000, 82000000 }, 1994 .hactive = { 1280, 1280, 1280 }, 1995 .hfront_porch = { 1, 1, 10 }, 1996 .hback_porch = { 1, 1, 10 }, 1997 /* 1998 * According to the data sheet, the minimum horizontal blanking interval 1999 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2000 * minimum working horizontal blanking interval to be 60 clocks. 2001 */ 2002 .hsync_len = { 58, 158, 661 }, 2003 .vactive = { 800, 800, 800 }, 2004 .vfront_porch = { 1, 1, 10 }, 2005 .vback_porch = { 1, 1, 10 }, 2006 .vsync_len = { 1, 21, 203 }, 2007 .flags = DISPLAY_FLAGS_DE_HIGH, 2008 }; 2009 2010 static const struct panel_desc hannstar_hsd070pww1 = { 2011 .timings = &hannstar_hsd070pww1_timing, 2012 .num_timings = 1, 2013 .bpc = 6, 2014 .size = { 2015 .width = 151, 2016 .height = 94, 2017 }, 2018 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2019 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2020 }; 2021 2022 static const struct display_timing hannstar_hsd100pxn1_timing = { 2023 .pixelclock = { 55000000, 65000000, 75000000 }, 2024 .hactive = { 1024, 1024, 1024 }, 2025 .hfront_porch = { 40, 40, 40 }, 2026 .hback_porch = { 220, 220, 220 }, 2027 .hsync_len = { 20, 60, 100 }, 2028 .vactive = { 768, 768, 768 }, 2029 .vfront_porch = { 7, 7, 7 }, 2030 .vback_porch = { 21, 21, 21 }, 2031 .vsync_len = { 10, 10, 10 }, 2032 .flags = DISPLAY_FLAGS_DE_HIGH, 2033 }; 2034 2035 static const struct panel_desc hannstar_hsd100pxn1 = { 2036 .timings = &hannstar_hsd100pxn1_timing, 2037 .num_timings = 1, 2038 .bpc = 6, 2039 .size = { 2040 .width = 203, 2041 .height = 152, 2042 }, 2043 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2044 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2045 }; 2046 2047 static const struct display_timing hannstar_hsd101pww2_timing = { 2048 .pixelclock = { 64300000, 71100000, 82000000 }, 2049 .hactive = { 1280, 1280, 1280 }, 2050 .hfront_porch = { 1, 1, 10 }, 2051 .hback_porch = { 1, 1, 10 }, 2052 .hsync_len = { 58, 158, 661 }, 2053 .vactive = { 800, 800, 800 }, 2054 .vfront_porch = { 1, 1, 10 }, 2055 .vback_porch = { 1, 1, 10 }, 2056 .vsync_len = { 1, 21, 203 }, 2057 .flags = DISPLAY_FLAGS_DE_HIGH, 2058 }; 2059 2060 static const struct panel_desc hannstar_hsd101pww2 = { 2061 .timings = &hannstar_hsd101pww2_timing, 2062 .num_timings = 1, 2063 .bpc = 8, 2064 .size = { 2065 .width = 217, 2066 .height = 136, 2067 }, 2068 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2069 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2070 }; 2071 2072 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2073 .clock = 33333, 2074 .hdisplay = 800, 2075 .hsync_start = 800 + 85, 2076 .hsync_end = 800 + 85 + 86, 2077 .htotal = 800 + 85 + 86 + 85, 2078 .vdisplay = 480, 2079 .vsync_start = 480 + 16, 2080 .vsync_end = 480 + 16 + 13, 2081 .vtotal = 480 + 16 + 13 + 16, 2082 }; 2083 2084 static const struct panel_desc hitachi_tx23d38vm0caa = { 2085 .modes = &hitachi_tx23d38vm0caa_mode, 2086 .num_modes = 1, 2087 .bpc = 6, 2088 .size = { 2089 .width = 195, 2090 .height = 117, 2091 }, 2092 .delay = { 2093 .enable = 160, 2094 .disable = 160, 2095 }, 2096 }; 2097 2098 static const struct drm_display_mode innolux_at043tn24_mode = { 2099 .clock = 9000, 2100 .hdisplay = 480, 2101 .hsync_start = 480 + 2, 2102 .hsync_end = 480 + 2 + 41, 2103 .htotal = 480 + 2 + 41 + 2, 2104 .vdisplay = 272, 2105 .vsync_start = 272 + 2, 2106 .vsync_end = 272 + 2 + 10, 2107 .vtotal = 272 + 2 + 10 + 2, 2108 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2109 }; 2110 2111 static const struct panel_desc innolux_at043tn24 = { 2112 .modes = &innolux_at043tn24_mode, 2113 .num_modes = 1, 2114 .bpc = 8, 2115 .size = { 2116 .width = 95, 2117 .height = 54, 2118 }, 2119 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2120 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2121 }; 2122 2123 static const struct drm_display_mode innolux_at070tn92_mode = { 2124 .clock = 33333, 2125 .hdisplay = 800, 2126 .hsync_start = 800 + 210, 2127 .hsync_end = 800 + 210 + 20, 2128 .htotal = 800 + 210 + 20 + 46, 2129 .vdisplay = 480, 2130 .vsync_start = 480 + 22, 2131 .vsync_end = 480 + 22 + 10, 2132 .vtotal = 480 + 22 + 23 + 10, 2133 }; 2134 2135 static const struct panel_desc innolux_at070tn92 = { 2136 .modes = &innolux_at070tn92_mode, 2137 .num_modes = 1, 2138 .size = { 2139 .width = 154, 2140 .height = 86, 2141 }, 2142 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2143 }; 2144 2145 static const struct display_timing innolux_g070y2_l01_timing = { 2146 .pixelclock = { 28000000, 29500000, 32000000 }, 2147 .hactive = { 800, 800, 800 }, 2148 .hfront_porch = { 61, 91, 141 }, 2149 .hback_porch = { 60, 90, 140 }, 2150 .hsync_len = { 12, 12, 12 }, 2151 .vactive = { 480, 480, 480 }, 2152 .vfront_porch = { 4, 9, 30 }, 2153 .vback_porch = { 4, 8, 28 }, 2154 .vsync_len = { 2, 2, 2 }, 2155 .flags = DISPLAY_FLAGS_DE_HIGH, 2156 }; 2157 2158 static const struct panel_desc innolux_g070y2_l01 = { 2159 .timings = &innolux_g070y2_l01_timing, 2160 .num_timings = 1, 2161 .bpc = 8, 2162 .size = { 2163 .width = 152, 2164 .height = 91, 2165 }, 2166 .delay = { 2167 .prepare = 10, 2168 .enable = 100, 2169 .disable = 100, 2170 .unprepare = 800, 2171 }, 2172 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2173 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2174 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2175 }; 2176 2177 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2178 .clock = 33333, 2179 .hdisplay = 800, 2180 .hsync_start = 800 + 210, 2181 .hsync_end = 800 + 210 + 20, 2182 .htotal = 800 + 210 + 20 + 46, 2183 .vdisplay = 480, 2184 .vsync_start = 480 + 22, 2185 .vsync_end = 480 + 22 + 10, 2186 .vtotal = 480 + 22 + 23 + 10, 2187 }; 2188 2189 static const struct panel_desc innolux_g070y2_t02 = { 2190 .modes = &innolux_g070y2_t02_mode, 2191 .num_modes = 1, 2192 .bpc = 8, 2193 .size = { 2194 .width = 152, 2195 .height = 92, 2196 }, 2197 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2198 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2199 .connector_type = DRM_MODE_CONNECTOR_DPI, 2200 }; 2201 2202 static const struct display_timing innolux_g101ice_l01_timing = { 2203 .pixelclock = { 60400000, 71100000, 74700000 }, 2204 .hactive = { 1280, 1280, 1280 }, 2205 .hfront_porch = { 41, 80, 100 }, 2206 .hback_porch = { 40, 79, 99 }, 2207 .hsync_len = { 1, 1, 1 }, 2208 .vactive = { 800, 800, 800 }, 2209 .vfront_porch = { 5, 11, 14 }, 2210 .vback_porch = { 4, 11, 14 }, 2211 .vsync_len = { 1, 1, 1 }, 2212 .flags = DISPLAY_FLAGS_DE_HIGH, 2213 }; 2214 2215 static const struct panel_desc innolux_g101ice_l01 = { 2216 .timings = &innolux_g101ice_l01_timing, 2217 .num_timings = 1, 2218 .bpc = 8, 2219 .size = { 2220 .width = 217, 2221 .height = 135, 2222 }, 2223 .delay = { 2224 .enable = 200, 2225 .disable = 200, 2226 }, 2227 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2228 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2229 }; 2230 2231 static const struct display_timing innolux_g121i1_l01_timing = { 2232 .pixelclock = { 67450000, 71000000, 74550000 }, 2233 .hactive = { 1280, 1280, 1280 }, 2234 .hfront_porch = { 40, 80, 160 }, 2235 .hback_porch = { 39, 79, 159 }, 2236 .hsync_len = { 1, 1, 1 }, 2237 .vactive = { 800, 800, 800 }, 2238 .vfront_porch = { 5, 11, 100 }, 2239 .vback_porch = { 4, 11, 99 }, 2240 .vsync_len = { 1, 1, 1 }, 2241 }; 2242 2243 static const struct panel_desc innolux_g121i1_l01 = { 2244 .timings = &innolux_g121i1_l01_timing, 2245 .num_timings = 1, 2246 .bpc = 6, 2247 .size = { 2248 .width = 261, 2249 .height = 163, 2250 }, 2251 .delay = { 2252 .enable = 200, 2253 .disable = 20, 2254 }, 2255 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2256 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2257 }; 2258 2259 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2260 .clock = 65000, 2261 .hdisplay = 1024, 2262 .hsync_start = 1024 + 0, 2263 .hsync_end = 1024 + 1, 2264 .htotal = 1024 + 0 + 1 + 320, 2265 .vdisplay = 768, 2266 .vsync_start = 768 + 38, 2267 .vsync_end = 768 + 38 + 1, 2268 .vtotal = 768 + 38 + 1 + 0, 2269 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2270 }; 2271 2272 static const struct panel_desc innolux_g121x1_l03 = { 2273 .modes = &innolux_g121x1_l03_mode, 2274 .num_modes = 1, 2275 .bpc = 6, 2276 .size = { 2277 .width = 246, 2278 .height = 185, 2279 }, 2280 .delay = { 2281 .enable = 200, 2282 .unprepare = 200, 2283 .disable = 400, 2284 }, 2285 }; 2286 2287 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2288 .clock = 69300, 2289 .hdisplay = 1366, 2290 .hsync_start = 1366 + 16, 2291 .hsync_end = 1366 + 16 + 34, 2292 .htotal = 1366 + 16 + 34 + 50, 2293 .vdisplay = 768, 2294 .vsync_start = 768 + 2, 2295 .vsync_end = 768 + 2 + 6, 2296 .vtotal = 768 + 2 + 6 + 12, 2297 }; 2298 2299 static const struct panel_desc innolux_n156bge_l21 = { 2300 .modes = &innolux_n156bge_l21_mode, 2301 .num_modes = 1, 2302 .bpc = 6, 2303 .size = { 2304 .width = 344, 2305 .height = 193, 2306 }, 2307 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2308 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2309 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2310 }; 2311 2312 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2313 .clock = 51501, 2314 .hdisplay = 1024, 2315 .hsync_start = 1024 + 128, 2316 .hsync_end = 1024 + 128 + 64, 2317 .htotal = 1024 + 128 + 64 + 128, 2318 .vdisplay = 600, 2319 .vsync_start = 600 + 16, 2320 .vsync_end = 600 + 16 + 4, 2321 .vtotal = 600 + 16 + 4 + 16, 2322 }; 2323 2324 static const struct panel_desc innolux_zj070na_01p = { 2325 .modes = &innolux_zj070na_01p_mode, 2326 .num_modes = 1, 2327 .bpc = 6, 2328 .size = { 2329 .width = 154, 2330 .height = 90, 2331 }, 2332 }; 2333 2334 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2335 .pixelclock = { 5580000, 5850000, 6200000 }, 2336 .hactive = { 320, 320, 320 }, 2337 .hfront_porch = { 30, 30, 30 }, 2338 .hback_porch = { 30, 30, 30 }, 2339 .hsync_len = { 1, 5, 17 }, 2340 .vactive = { 240, 240, 240 }, 2341 .vfront_porch = { 6, 6, 6 }, 2342 .vback_porch = { 5, 5, 5 }, 2343 .vsync_len = { 1, 2, 11 }, 2344 .flags = DISPLAY_FLAGS_DE_HIGH, 2345 }; 2346 2347 static const struct panel_desc koe_tx14d24vm1bpa = { 2348 .timings = &koe_tx14d24vm1bpa_timing, 2349 .num_timings = 1, 2350 .bpc = 6, 2351 .size = { 2352 .width = 115, 2353 .height = 86, 2354 }, 2355 }; 2356 2357 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2358 .pixelclock = { 151820000, 156720000, 159780000 }, 2359 .hactive = { 1920, 1920, 1920 }, 2360 .hfront_porch = { 105, 130, 142 }, 2361 .hback_porch = { 45, 70, 82 }, 2362 .hsync_len = { 30, 30, 30 }, 2363 .vactive = { 1200, 1200, 1200}, 2364 .vfront_porch = { 3, 5, 10 }, 2365 .vback_porch = { 2, 5, 10 }, 2366 .vsync_len = { 5, 5, 5 }, 2367 }; 2368 2369 static const struct panel_desc koe_tx26d202vm0bwa = { 2370 .timings = &koe_tx26d202vm0bwa_timing, 2371 .num_timings = 1, 2372 .bpc = 8, 2373 .size = { 2374 .width = 217, 2375 .height = 136, 2376 }, 2377 .delay = { 2378 .prepare = 1000, 2379 .enable = 1000, 2380 .unprepare = 1000, 2381 .disable = 1000, 2382 }, 2383 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2384 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2385 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2386 }; 2387 2388 static const struct display_timing koe_tx31d200vm0baa_timing = { 2389 .pixelclock = { 39600000, 43200000, 48000000 }, 2390 .hactive = { 1280, 1280, 1280 }, 2391 .hfront_porch = { 16, 36, 56 }, 2392 .hback_porch = { 16, 36, 56 }, 2393 .hsync_len = { 8, 8, 8 }, 2394 .vactive = { 480, 480, 480 }, 2395 .vfront_porch = { 6, 21, 33 }, 2396 .vback_porch = { 6, 21, 33 }, 2397 .vsync_len = { 8, 8, 8 }, 2398 .flags = DISPLAY_FLAGS_DE_HIGH, 2399 }; 2400 2401 static const struct panel_desc koe_tx31d200vm0baa = { 2402 .timings = &koe_tx31d200vm0baa_timing, 2403 .num_timings = 1, 2404 .bpc = 6, 2405 .size = { 2406 .width = 292, 2407 .height = 109, 2408 }, 2409 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2410 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2411 }; 2412 2413 static const struct display_timing kyo_tcg121xglp_timing = { 2414 .pixelclock = { 52000000, 65000000, 71000000 }, 2415 .hactive = { 1024, 1024, 1024 }, 2416 .hfront_porch = { 2, 2, 2 }, 2417 .hback_porch = { 2, 2, 2 }, 2418 .hsync_len = { 86, 124, 244 }, 2419 .vactive = { 768, 768, 768 }, 2420 .vfront_porch = { 2, 2, 2 }, 2421 .vback_porch = { 2, 2, 2 }, 2422 .vsync_len = { 6, 34, 73 }, 2423 .flags = DISPLAY_FLAGS_DE_HIGH, 2424 }; 2425 2426 static const struct panel_desc kyo_tcg121xglp = { 2427 .timings = &kyo_tcg121xglp_timing, 2428 .num_timings = 1, 2429 .bpc = 8, 2430 .size = { 2431 .width = 246, 2432 .height = 184, 2433 }, 2434 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2435 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2436 }; 2437 2438 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2439 .clock = 7000, 2440 .hdisplay = 320, 2441 .hsync_start = 320 + 20, 2442 .hsync_end = 320 + 20 + 30, 2443 .htotal = 320 + 20 + 30 + 38, 2444 .vdisplay = 240, 2445 .vsync_start = 240 + 4, 2446 .vsync_end = 240 + 4 + 3, 2447 .vtotal = 240 + 4 + 3 + 15, 2448 }; 2449 2450 static const struct panel_desc lemaker_bl035_rgb_002 = { 2451 .modes = &lemaker_bl035_rgb_002_mode, 2452 .num_modes = 1, 2453 .size = { 2454 .width = 70, 2455 .height = 52, 2456 }, 2457 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2458 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2459 }; 2460 2461 static const struct drm_display_mode lg_lb070wv8_mode = { 2462 .clock = 33246, 2463 .hdisplay = 800, 2464 .hsync_start = 800 + 88, 2465 .hsync_end = 800 + 88 + 80, 2466 .htotal = 800 + 88 + 80 + 88, 2467 .vdisplay = 480, 2468 .vsync_start = 480 + 10, 2469 .vsync_end = 480 + 10 + 25, 2470 .vtotal = 480 + 10 + 25 + 10, 2471 }; 2472 2473 static const struct panel_desc lg_lb070wv8 = { 2474 .modes = &lg_lb070wv8_mode, 2475 .num_modes = 1, 2476 .bpc = 8, 2477 .size = { 2478 .width = 151, 2479 .height = 91, 2480 }, 2481 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2482 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2483 }; 2484 2485 static const struct display_timing logictechno_lt161010_2nh_timing = { 2486 .pixelclock = { 26400000, 33300000, 46800000 }, 2487 .hactive = { 800, 800, 800 }, 2488 .hfront_porch = { 16, 210, 354 }, 2489 .hback_porch = { 46, 46, 46 }, 2490 .hsync_len = { 1, 20, 40 }, 2491 .vactive = { 480, 480, 480 }, 2492 .vfront_porch = { 7, 22, 147 }, 2493 .vback_porch = { 23, 23, 23 }, 2494 .vsync_len = { 1, 10, 20 }, 2495 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2496 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2497 DISPLAY_FLAGS_SYNC_POSEDGE, 2498 }; 2499 2500 static const struct panel_desc logictechno_lt161010_2nh = { 2501 .timings = &logictechno_lt161010_2nh_timing, 2502 .num_timings = 1, 2503 .bpc = 6, 2504 .size = { 2505 .width = 154, 2506 .height = 86, 2507 }, 2508 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2509 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2510 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2511 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2512 .connector_type = DRM_MODE_CONNECTOR_DPI, 2513 }; 2514 2515 static const struct display_timing logictechno_lt170410_2whc_timing = { 2516 .pixelclock = { 68900000, 71100000, 73400000 }, 2517 .hactive = { 1280, 1280, 1280 }, 2518 .hfront_porch = { 23, 60, 71 }, 2519 .hback_porch = { 23, 60, 71 }, 2520 .hsync_len = { 15, 40, 47 }, 2521 .vactive = { 800, 800, 800 }, 2522 .vfront_porch = { 5, 7, 10 }, 2523 .vback_porch = { 5, 7, 10 }, 2524 .vsync_len = { 6, 9, 12 }, 2525 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2526 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2527 DISPLAY_FLAGS_SYNC_POSEDGE, 2528 }; 2529 2530 static const struct panel_desc logictechno_lt170410_2whc = { 2531 .timings = &logictechno_lt170410_2whc_timing, 2532 .num_timings = 1, 2533 .bpc = 8, 2534 .size = { 2535 .width = 217, 2536 .height = 136, 2537 }, 2538 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2539 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2540 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2541 }; 2542 2543 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2544 .clock = 33000, 2545 .hdisplay = 800, 2546 .hsync_start = 800 + 112, 2547 .hsync_end = 800 + 112 + 3, 2548 .htotal = 800 + 112 + 3 + 85, 2549 .vdisplay = 480, 2550 .vsync_start = 480 + 38, 2551 .vsync_end = 480 + 38 + 3, 2552 .vtotal = 480 + 38 + 3 + 29, 2553 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2554 }; 2555 2556 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2557 .modes = &logictechno_lttd800480070_l2rt_mode, 2558 .num_modes = 1, 2559 .bpc = 8, 2560 .size = { 2561 .width = 154, 2562 .height = 86, 2563 }, 2564 .delay = { 2565 .prepare = 45, 2566 .enable = 100, 2567 .disable = 100, 2568 .unprepare = 45 2569 }, 2570 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2571 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2572 .connector_type = DRM_MODE_CONNECTOR_DPI, 2573 }; 2574 2575 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2576 .clock = 33000, 2577 .hdisplay = 800, 2578 .hsync_start = 800 + 154, 2579 .hsync_end = 800 + 154 + 3, 2580 .htotal = 800 + 154 + 3 + 43, 2581 .vdisplay = 480, 2582 .vsync_start = 480 + 47, 2583 .vsync_end = 480 + 47 + 3, 2584 .vtotal = 480 + 47 + 3 + 20, 2585 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2586 }; 2587 2588 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2589 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2590 .num_modes = 1, 2591 .bpc = 8, 2592 .size = { 2593 .width = 154, 2594 .height = 86, 2595 }, 2596 .delay = { 2597 .prepare = 45, 2598 .enable = 100, 2599 .disable = 100, 2600 .unprepare = 45 2601 }, 2602 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2603 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2604 .connector_type = DRM_MODE_CONNECTOR_DPI, 2605 }; 2606 2607 static const struct drm_display_mode logicpd_type_28_mode = { 2608 .clock = 9107, 2609 .hdisplay = 480, 2610 .hsync_start = 480 + 3, 2611 .hsync_end = 480 + 3 + 42, 2612 .htotal = 480 + 3 + 42 + 2, 2613 2614 .vdisplay = 272, 2615 .vsync_start = 272 + 2, 2616 .vsync_end = 272 + 2 + 11, 2617 .vtotal = 272 + 2 + 11 + 3, 2618 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2619 }; 2620 2621 static const struct panel_desc logicpd_type_28 = { 2622 .modes = &logicpd_type_28_mode, 2623 .num_modes = 1, 2624 .bpc = 8, 2625 .size = { 2626 .width = 105, 2627 .height = 67, 2628 }, 2629 .delay = { 2630 .prepare = 200, 2631 .enable = 200, 2632 .unprepare = 200, 2633 .disable = 200, 2634 }, 2635 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2636 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2637 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2638 .connector_type = DRM_MODE_CONNECTOR_DPI, 2639 }; 2640 2641 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2642 .clock = 30400, 2643 .hdisplay = 800, 2644 .hsync_start = 800 + 0, 2645 .hsync_end = 800 + 1, 2646 .htotal = 800 + 0 + 1 + 160, 2647 .vdisplay = 480, 2648 .vsync_start = 480 + 0, 2649 .vsync_end = 480 + 48 + 1, 2650 .vtotal = 480 + 48 + 1 + 0, 2651 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2652 }; 2653 2654 static const struct panel_desc mitsubishi_aa070mc01 = { 2655 .modes = &mitsubishi_aa070mc01_mode, 2656 .num_modes = 1, 2657 .bpc = 8, 2658 .size = { 2659 .width = 152, 2660 .height = 91, 2661 }, 2662 2663 .delay = { 2664 .enable = 200, 2665 .unprepare = 200, 2666 .disable = 400, 2667 }, 2668 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2669 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2670 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2671 }; 2672 2673 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2674 .pixelclock = { 29000000, 33000000, 38000000 }, 2675 .hactive = { 800, 800, 800 }, 2676 .hfront_porch = { 180, 210, 240 }, 2677 .hback_porch = { 16, 16, 16 }, 2678 .hsync_len = { 30, 30, 30 }, 2679 .vactive = { 480, 480, 480 }, 2680 .vfront_porch = { 12, 22, 32 }, 2681 .vback_porch = { 10, 10, 10 }, 2682 .vsync_len = { 13, 13, 13 }, 2683 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2684 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2685 DISPLAY_FLAGS_SYNC_POSEDGE, 2686 }; 2687 2688 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2689 .timings = &multi_inno_mi0700s4t_6_timing, 2690 .num_timings = 1, 2691 .bpc = 8, 2692 .size = { 2693 .width = 154, 2694 .height = 86, 2695 }, 2696 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2697 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2698 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2699 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2700 .connector_type = DRM_MODE_CONNECTOR_DPI, 2701 }; 2702 2703 static const struct display_timing multi_inno_mi0800ft_9_timing = { 2704 .pixelclock = { 32000000, 40000000, 50000000 }, 2705 .hactive = { 800, 800, 800 }, 2706 .hfront_porch = { 16, 210, 354 }, 2707 .hback_porch = { 6, 26, 45 }, 2708 .hsync_len = { 1, 20, 40 }, 2709 .vactive = { 600, 600, 600 }, 2710 .vfront_porch = { 1, 12, 77 }, 2711 .vback_porch = { 3, 13, 22 }, 2712 .vsync_len = { 1, 10, 20 }, 2713 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2714 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2715 DISPLAY_FLAGS_SYNC_POSEDGE, 2716 }; 2717 2718 static const struct panel_desc multi_inno_mi0800ft_9 = { 2719 .timings = &multi_inno_mi0800ft_9_timing, 2720 .num_timings = 1, 2721 .bpc = 8, 2722 .size = { 2723 .width = 162, 2724 .height = 122, 2725 }, 2726 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2727 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2728 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2729 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2730 .connector_type = DRM_MODE_CONNECTOR_DPI, 2731 }; 2732 2733 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2734 .pixelclock = { 68900000, 70000000, 73400000 }, 2735 .hactive = { 1280, 1280, 1280 }, 2736 .hfront_porch = { 30, 60, 71 }, 2737 .hback_porch = { 30, 60, 71 }, 2738 .hsync_len = { 10, 10, 48 }, 2739 .vactive = { 800, 800, 800 }, 2740 .vfront_porch = { 5, 10, 10 }, 2741 .vback_porch = { 5, 10, 10 }, 2742 .vsync_len = { 5, 6, 13 }, 2743 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2744 DISPLAY_FLAGS_DE_HIGH, 2745 }; 2746 2747 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2748 .timings = &multi_inno_mi1010ait_1cp_timing, 2749 .num_timings = 1, 2750 .bpc = 8, 2751 .size = { 2752 .width = 217, 2753 .height = 136, 2754 }, 2755 .delay = { 2756 .enable = 50, 2757 .disable = 50, 2758 }, 2759 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2760 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2761 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2762 }; 2763 2764 static const struct display_timing nec_nl12880bc20_05_timing = { 2765 .pixelclock = { 67000000, 71000000, 75000000 }, 2766 .hactive = { 1280, 1280, 1280 }, 2767 .hfront_porch = { 2, 30, 30 }, 2768 .hback_porch = { 6, 100, 100 }, 2769 .hsync_len = { 2, 30, 30 }, 2770 .vactive = { 800, 800, 800 }, 2771 .vfront_porch = { 5, 5, 5 }, 2772 .vback_porch = { 11, 11, 11 }, 2773 .vsync_len = { 7, 7, 7 }, 2774 }; 2775 2776 static const struct panel_desc nec_nl12880bc20_05 = { 2777 .timings = &nec_nl12880bc20_05_timing, 2778 .num_timings = 1, 2779 .bpc = 8, 2780 .size = { 2781 .width = 261, 2782 .height = 163, 2783 }, 2784 .delay = { 2785 .enable = 50, 2786 .disable = 50, 2787 }, 2788 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2789 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2790 }; 2791 2792 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2793 .clock = 10870, 2794 .hdisplay = 480, 2795 .hsync_start = 480 + 2, 2796 .hsync_end = 480 + 2 + 41, 2797 .htotal = 480 + 2 + 41 + 2, 2798 .vdisplay = 272, 2799 .vsync_start = 272 + 2, 2800 .vsync_end = 272 + 2 + 4, 2801 .vtotal = 272 + 2 + 4 + 2, 2802 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2803 }; 2804 2805 static const struct panel_desc nec_nl4827hc19_05b = { 2806 .modes = &nec_nl4827hc19_05b_mode, 2807 .num_modes = 1, 2808 .bpc = 8, 2809 .size = { 2810 .width = 95, 2811 .height = 54, 2812 }, 2813 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2814 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2815 }; 2816 2817 static const struct drm_display_mode netron_dy_e231732_mode = { 2818 .clock = 66000, 2819 .hdisplay = 1024, 2820 .hsync_start = 1024 + 160, 2821 .hsync_end = 1024 + 160 + 70, 2822 .htotal = 1024 + 160 + 70 + 90, 2823 .vdisplay = 600, 2824 .vsync_start = 600 + 127, 2825 .vsync_end = 600 + 127 + 20, 2826 .vtotal = 600 + 127 + 20 + 3, 2827 }; 2828 2829 static const struct panel_desc netron_dy_e231732 = { 2830 .modes = &netron_dy_e231732_mode, 2831 .num_modes = 1, 2832 .size = { 2833 .width = 154, 2834 .height = 87, 2835 }, 2836 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2837 }; 2838 2839 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2840 .clock = 9000, 2841 .hdisplay = 480, 2842 .hsync_start = 480 + 2, 2843 .hsync_end = 480 + 2 + 41, 2844 .htotal = 480 + 2 + 41 + 2, 2845 .vdisplay = 272, 2846 .vsync_start = 272 + 2, 2847 .vsync_end = 272 + 2 + 10, 2848 .vtotal = 272 + 2 + 10 + 2, 2849 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2850 }; 2851 2852 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2853 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2854 .num_modes = 1, 2855 .bpc = 8, 2856 .size = { 2857 .width = 95, 2858 .height = 54, 2859 }, 2860 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2861 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2862 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2863 .connector_type = DRM_MODE_CONNECTOR_DPI, 2864 }; 2865 2866 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2867 .pixelclock = { 130000000, 148350000, 163000000 }, 2868 .hactive = { 1920, 1920, 1920 }, 2869 .hfront_porch = { 80, 100, 100 }, 2870 .hback_porch = { 100, 120, 120 }, 2871 .hsync_len = { 50, 60, 60 }, 2872 .vactive = { 1080, 1080, 1080 }, 2873 .vfront_porch = { 12, 30, 30 }, 2874 .vback_porch = { 4, 10, 10 }, 2875 .vsync_len = { 4, 5, 5 }, 2876 }; 2877 2878 static const struct panel_desc nlt_nl192108ac18_02d = { 2879 .timings = &nlt_nl192108ac18_02d_timing, 2880 .num_timings = 1, 2881 .bpc = 8, 2882 .size = { 2883 .width = 344, 2884 .height = 194, 2885 }, 2886 .delay = { 2887 .unprepare = 500, 2888 }, 2889 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2890 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2891 }; 2892 2893 static const struct drm_display_mode nvd_9128_mode = { 2894 .clock = 29500, 2895 .hdisplay = 800, 2896 .hsync_start = 800 + 130, 2897 .hsync_end = 800 + 130 + 98, 2898 .htotal = 800 + 0 + 130 + 98, 2899 .vdisplay = 480, 2900 .vsync_start = 480 + 10, 2901 .vsync_end = 480 + 10 + 50, 2902 .vtotal = 480 + 0 + 10 + 50, 2903 }; 2904 2905 static const struct panel_desc nvd_9128 = { 2906 .modes = &nvd_9128_mode, 2907 .num_modes = 1, 2908 .bpc = 8, 2909 .size = { 2910 .width = 156, 2911 .height = 88, 2912 }, 2913 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2914 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2915 }; 2916 2917 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2918 .pixelclock = { 30000000, 30000000, 40000000 }, 2919 .hactive = { 800, 800, 800 }, 2920 .hfront_porch = { 40, 40, 40 }, 2921 .hback_porch = { 40, 40, 40 }, 2922 .hsync_len = { 1, 48, 48 }, 2923 .vactive = { 480, 480, 480 }, 2924 .vfront_porch = { 13, 13, 13 }, 2925 .vback_porch = { 29, 29, 29 }, 2926 .vsync_len = { 3, 3, 3 }, 2927 .flags = DISPLAY_FLAGS_DE_HIGH, 2928 }; 2929 2930 static const struct panel_desc okaya_rs800480t_7x0gp = { 2931 .timings = &okaya_rs800480t_7x0gp_timing, 2932 .num_timings = 1, 2933 .bpc = 6, 2934 .size = { 2935 .width = 154, 2936 .height = 87, 2937 }, 2938 .delay = { 2939 .prepare = 41, 2940 .enable = 50, 2941 .unprepare = 41, 2942 .disable = 50, 2943 }, 2944 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2945 }; 2946 2947 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2948 .clock = 9000, 2949 .hdisplay = 480, 2950 .hsync_start = 480 + 5, 2951 .hsync_end = 480 + 5 + 30, 2952 .htotal = 480 + 5 + 30 + 10, 2953 .vdisplay = 272, 2954 .vsync_start = 272 + 8, 2955 .vsync_end = 272 + 8 + 5, 2956 .vtotal = 272 + 8 + 5 + 3, 2957 }; 2958 2959 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2960 .modes = &olimex_lcd_olinuxino_43ts_mode, 2961 .num_modes = 1, 2962 .size = { 2963 .width = 95, 2964 .height = 54, 2965 }, 2966 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2967 }; 2968 2969 /* 2970 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2971 * pixel clocks, but this is the timing that was being used in the Adafruit 2972 * installation instructions. 2973 */ 2974 static const struct drm_display_mode ontat_yx700wv03_mode = { 2975 .clock = 29500, 2976 .hdisplay = 800, 2977 .hsync_start = 824, 2978 .hsync_end = 896, 2979 .htotal = 992, 2980 .vdisplay = 480, 2981 .vsync_start = 483, 2982 .vsync_end = 493, 2983 .vtotal = 500, 2984 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2985 }; 2986 2987 /* 2988 * Specification at: 2989 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2990 */ 2991 static const struct panel_desc ontat_yx700wv03 = { 2992 .modes = &ontat_yx700wv03_mode, 2993 .num_modes = 1, 2994 .bpc = 8, 2995 .size = { 2996 .width = 154, 2997 .height = 83, 2998 }, 2999 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3000 }; 3001 3002 static const struct drm_display_mode ortustech_com37h3m_mode = { 3003 .clock = 22230, 3004 .hdisplay = 480, 3005 .hsync_start = 480 + 40, 3006 .hsync_end = 480 + 40 + 10, 3007 .htotal = 480 + 40 + 10 + 40, 3008 .vdisplay = 640, 3009 .vsync_start = 640 + 4, 3010 .vsync_end = 640 + 4 + 2, 3011 .vtotal = 640 + 4 + 2 + 4, 3012 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3013 }; 3014 3015 static const struct panel_desc ortustech_com37h3m = { 3016 .modes = &ortustech_com37h3m_mode, 3017 .num_modes = 1, 3018 .bpc = 8, 3019 .size = { 3020 .width = 56, /* 56.16mm */ 3021 .height = 75, /* 74.88mm */ 3022 }, 3023 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3024 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3025 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3026 }; 3027 3028 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3029 .clock = 25000, 3030 .hdisplay = 480, 3031 .hsync_start = 480 + 10, 3032 .hsync_end = 480 + 10 + 10, 3033 .htotal = 480 + 10 + 10 + 15, 3034 .vdisplay = 800, 3035 .vsync_start = 800 + 3, 3036 .vsync_end = 800 + 3 + 3, 3037 .vtotal = 800 + 3 + 3 + 3, 3038 }; 3039 3040 static const struct panel_desc ortustech_com43h4m85ulc = { 3041 .modes = &ortustech_com43h4m85ulc_mode, 3042 .num_modes = 1, 3043 .bpc = 6, 3044 .size = { 3045 .width = 56, 3046 .height = 93, 3047 }, 3048 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3049 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3050 .connector_type = DRM_MODE_CONNECTOR_DPI, 3051 }; 3052 3053 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3054 .clock = 33000, 3055 .hdisplay = 800, 3056 .hsync_start = 800 + 210, 3057 .hsync_end = 800 + 210 + 30, 3058 .htotal = 800 + 210 + 30 + 16, 3059 .vdisplay = 480, 3060 .vsync_start = 480 + 22, 3061 .vsync_end = 480 + 22 + 13, 3062 .vtotal = 480 + 22 + 13 + 10, 3063 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3064 }; 3065 3066 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3067 .modes = &osddisplays_osd070t1718_19ts_mode, 3068 .num_modes = 1, 3069 .bpc = 8, 3070 .size = { 3071 .width = 152, 3072 .height = 91, 3073 }, 3074 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3075 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3076 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3077 .connector_type = DRM_MODE_CONNECTOR_DPI, 3078 }; 3079 3080 static const struct drm_display_mode pda_91_00156_a0_mode = { 3081 .clock = 33300, 3082 .hdisplay = 800, 3083 .hsync_start = 800 + 1, 3084 .hsync_end = 800 + 1 + 64, 3085 .htotal = 800 + 1 + 64 + 64, 3086 .vdisplay = 480, 3087 .vsync_start = 480 + 1, 3088 .vsync_end = 480 + 1 + 23, 3089 .vtotal = 480 + 1 + 23 + 22, 3090 }; 3091 3092 static const struct panel_desc pda_91_00156_a0 = { 3093 .modes = &pda_91_00156_a0_mode, 3094 .num_modes = 1, 3095 .size = { 3096 .width = 152, 3097 .height = 91, 3098 }, 3099 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3100 }; 3101 3102 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3103 .clock = 24750, 3104 .hdisplay = 800, 3105 .hsync_start = 800 + 54, 3106 .hsync_end = 800 + 54 + 2, 3107 .htotal = 800 + 54 + 2 + 44, 3108 .vdisplay = 480, 3109 .vsync_start = 480 + 49, 3110 .vsync_end = 480 + 49 + 2, 3111 .vtotal = 480 + 49 + 2 + 22, 3112 }; 3113 3114 static const struct panel_desc powertip_ph800480t013_idf02 = { 3115 .modes = &powertip_ph800480t013_idf02_mode, 3116 .num_modes = 1, 3117 .size = { 3118 .width = 152, 3119 .height = 91, 3120 }, 3121 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3122 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3123 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3124 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3125 .connector_type = DRM_MODE_CONNECTOR_DPI, 3126 }; 3127 3128 static const struct drm_display_mode qd43003c0_40_mode = { 3129 .clock = 9000, 3130 .hdisplay = 480, 3131 .hsync_start = 480 + 8, 3132 .hsync_end = 480 + 8 + 4, 3133 .htotal = 480 + 8 + 4 + 39, 3134 .vdisplay = 272, 3135 .vsync_start = 272 + 4, 3136 .vsync_end = 272 + 4 + 10, 3137 .vtotal = 272 + 4 + 10 + 2, 3138 }; 3139 3140 static const struct panel_desc qd43003c0_40 = { 3141 .modes = &qd43003c0_40_mode, 3142 .num_modes = 1, 3143 .bpc = 8, 3144 .size = { 3145 .width = 95, 3146 .height = 53, 3147 }, 3148 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3149 }; 3150 3151 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3152 { /* 60 Hz */ 3153 .clock = 10800, 3154 .hdisplay = 480, 3155 .hsync_start = 480 + 77, 3156 .hsync_end = 480 + 77 + 41, 3157 .htotal = 480 + 77 + 41 + 2, 3158 .vdisplay = 272, 3159 .vsync_start = 272 + 16, 3160 .vsync_end = 272 + 16 + 10, 3161 .vtotal = 272 + 16 + 10 + 2, 3162 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3163 }, 3164 { /* 50 Hz */ 3165 .clock = 10800, 3166 .hdisplay = 480, 3167 .hsync_start = 480 + 17, 3168 .hsync_end = 480 + 17 + 41, 3169 .htotal = 480 + 17 + 41 + 2, 3170 .vdisplay = 272, 3171 .vsync_start = 272 + 116, 3172 .vsync_end = 272 + 116 + 10, 3173 .vtotal = 272 + 116 + 10 + 2, 3174 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3175 }, 3176 }; 3177 3178 static const struct panel_desc qishenglong_gopher2b_lcd = { 3179 .modes = qishenglong_gopher2b_lcd_modes, 3180 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3181 .bpc = 8, 3182 .size = { 3183 .width = 95, 3184 .height = 54, 3185 }, 3186 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3187 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3188 .connector_type = DRM_MODE_CONNECTOR_DPI, 3189 }; 3190 3191 static const struct display_timing rocktech_rk070er9427_timing = { 3192 .pixelclock = { 26400000, 33300000, 46800000 }, 3193 .hactive = { 800, 800, 800 }, 3194 .hfront_porch = { 16, 210, 354 }, 3195 .hback_porch = { 46, 46, 46 }, 3196 .hsync_len = { 1, 1, 1 }, 3197 .vactive = { 480, 480, 480 }, 3198 .vfront_porch = { 7, 22, 147 }, 3199 .vback_porch = { 23, 23, 23 }, 3200 .vsync_len = { 1, 1, 1 }, 3201 .flags = DISPLAY_FLAGS_DE_HIGH, 3202 }; 3203 3204 static const struct panel_desc rocktech_rk070er9427 = { 3205 .timings = &rocktech_rk070er9427_timing, 3206 .num_timings = 1, 3207 .bpc = 6, 3208 .size = { 3209 .width = 154, 3210 .height = 86, 3211 }, 3212 .delay = { 3213 .prepare = 41, 3214 .enable = 50, 3215 .unprepare = 41, 3216 .disable = 50, 3217 }, 3218 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3219 }; 3220 3221 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3222 .clock = 71100, 3223 .hdisplay = 1280, 3224 .hsync_start = 1280 + 48, 3225 .hsync_end = 1280 + 48 + 32, 3226 .htotal = 1280 + 48 + 32 + 80, 3227 .vdisplay = 800, 3228 .vsync_start = 800 + 2, 3229 .vsync_end = 800 + 2 + 5, 3230 .vtotal = 800 + 2 + 5 + 16, 3231 }; 3232 3233 static const struct panel_desc rocktech_rk101ii01d_ct = { 3234 .modes = &rocktech_rk101ii01d_ct_mode, 3235 .bpc = 8, 3236 .num_modes = 1, 3237 .size = { 3238 .width = 217, 3239 .height = 136, 3240 }, 3241 .delay = { 3242 .prepare = 50, 3243 .disable = 50, 3244 }, 3245 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3246 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3247 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3248 }; 3249 3250 static const struct display_timing samsung_ltl101al01_timing = { 3251 .pixelclock = { 66663000, 66663000, 66663000 }, 3252 .hactive = { 1280, 1280, 1280 }, 3253 .hfront_porch = { 18, 18, 18 }, 3254 .hback_porch = { 36, 36, 36 }, 3255 .hsync_len = { 16, 16, 16 }, 3256 .vactive = { 800, 800, 800 }, 3257 .vfront_porch = { 4, 4, 4 }, 3258 .vback_porch = { 16, 16, 16 }, 3259 .vsync_len = { 3, 3, 3 }, 3260 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3261 }; 3262 3263 static const struct panel_desc samsung_ltl101al01 = { 3264 .timings = &samsung_ltl101al01_timing, 3265 .num_timings = 1, 3266 .bpc = 8, 3267 .size = { 3268 .width = 217, 3269 .height = 135, 3270 }, 3271 .delay = { 3272 .prepare = 40, 3273 .enable = 300, 3274 .disable = 200, 3275 .unprepare = 600, 3276 }, 3277 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3278 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3279 }; 3280 3281 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3282 .clock = 54030, 3283 .hdisplay = 1024, 3284 .hsync_start = 1024 + 24, 3285 .hsync_end = 1024 + 24 + 136, 3286 .htotal = 1024 + 24 + 136 + 160, 3287 .vdisplay = 600, 3288 .vsync_start = 600 + 3, 3289 .vsync_end = 600 + 3 + 6, 3290 .vtotal = 600 + 3 + 6 + 61, 3291 }; 3292 3293 static const struct panel_desc samsung_ltn101nt05 = { 3294 .modes = &samsung_ltn101nt05_mode, 3295 .num_modes = 1, 3296 .bpc = 6, 3297 .size = { 3298 .width = 223, 3299 .height = 125, 3300 }, 3301 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3302 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3303 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3304 }; 3305 3306 static const struct display_timing satoz_sat050at40h12r2_timing = { 3307 .pixelclock = {33300000, 33300000, 50000000}, 3308 .hactive = {800, 800, 800}, 3309 .hfront_porch = {16, 210, 354}, 3310 .hback_porch = {46, 46, 46}, 3311 .hsync_len = {1, 1, 40}, 3312 .vactive = {480, 480, 480}, 3313 .vfront_porch = {7, 22, 147}, 3314 .vback_porch = {23, 23, 23}, 3315 .vsync_len = {1, 1, 20}, 3316 }; 3317 3318 static const struct panel_desc satoz_sat050at40h12r2 = { 3319 .timings = &satoz_sat050at40h12r2_timing, 3320 .num_timings = 1, 3321 .bpc = 8, 3322 .size = { 3323 .width = 108, 3324 .height = 65, 3325 }, 3326 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3327 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3328 }; 3329 3330 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3331 .clock = 33260, 3332 .hdisplay = 800, 3333 .hsync_start = 800 + 64, 3334 .hsync_end = 800 + 64 + 128, 3335 .htotal = 800 + 64 + 128 + 64, 3336 .vdisplay = 480, 3337 .vsync_start = 480 + 8, 3338 .vsync_end = 480 + 8 + 2, 3339 .vtotal = 480 + 8 + 2 + 35, 3340 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3341 }; 3342 3343 static const struct panel_desc sharp_lq070y3dg3b = { 3344 .modes = &sharp_lq070y3dg3b_mode, 3345 .num_modes = 1, 3346 .bpc = 8, 3347 .size = { 3348 .width = 152, /* 152.4mm */ 3349 .height = 91, /* 91.4mm */ 3350 }, 3351 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3352 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3353 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3354 }; 3355 3356 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3357 .clock = 5500, 3358 .hdisplay = 240, 3359 .hsync_start = 240 + 16, 3360 .hsync_end = 240 + 16 + 7, 3361 .htotal = 240 + 16 + 7 + 5, 3362 .vdisplay = 320, 3363 .vsync_start = 320 + 9, 3364 .vsync_end = 320 + 9 + 1, 3365 .vtotal = 320 + 9 + 1 + 7, 3366 }; 3367 3368 static const struct panel_desc sharp_lq035q7db03 = { 3369 .modes = &sharp_lq035q7db03_mode, 3370 .num_modes = 1, 3371 .bpc = 6, 3372 .size = { 3373 .width = 54, 3374 .height = 72, 3375 }, 3376 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3377 }; 3378 3379 static const struct display_timing sharp_lq101k1ly04_timing = { 3380 .pixelclock = { 60000000, 65000000, 80000000 }, 3381 .hactive = { 1280, 1280, 1280 }, 3382 .hfront_porch = { 20, 20, 20 }, 3383 .hback_porch = { 20, 20, 20 }, 3384 .hsync_len = { 10, 10, 10 }, 3385 .vactive = { 800, 800, 800 }, 3386 .vfront_porch = { 4, 4, 4 }, 3387 .vback_porch = { 4, 4, 4 }, 3388 .vsync_len = { 4, 4, 4 }, 3389 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3390 }; 3391 3392 static const struct panel_desc sharp_lq101k1ly04 = { 3393 .timings = &sharp_lq101k1ly04_timing, 3394 .num_timings = 1, 3395 .bpc = 8, 3396 .size = { 3397 .width = 217, 3398 .height = 136, 3399 }, 3400 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3401 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3402 }; 3403 3404 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3405 { /* 50 Hz */ 3406 .clock = 3000, 3407 .hdisplay = 240, 3408 .hsync_start = 240 + 58, 3409 .hsync_end = 240 + 58 + 1, 3410 .htotal = 240 + 58 + 1 + 1, 3411 .vdisplay = 160, 3412 .vsync_start = 160 + 24, 3413 .vsync_end = 160 + 24 + 10, 3414 .vtotal = 160 + 24 + 10 + 6, 3415 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3416 }, 3417 { /* 60 Hz */ 3418 .clock = 3000, 3419 .hdisplay = 240, 3420 .hsync_start = 240 + 8, 3421 .hsync_end = 240 + 8 + 1, 3422 .htotal = 240 + 8 + 1 + 1, 3423 .vdisplay = 160, 3424 .vsync_start = 160 + 24, 3425 .vsync_end = 160 + 24 + 10, 3426 .vtotal = 160 + 24 + 10 + 6, 3427 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3428 }, 3429 }; 3430 3431 static const struct panel_desc sharp_ls020b1dd01d = { 3432 .modes = sharp_ls020b1dd01d_modes, 3433 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3434 .bpc = 6, 3435 .size = { 3436 .width = 42, 3437 .height = 28, 3438 }, 3439 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3440 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3441 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3442 | DRM_BUS_FLAG_SHARP_SIGNALS, 3443 }; 3444 3445 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3446 .clock = 33300, 3447 .hdisplay = 800, 3448 .hsync_start = 800 + 1, 3449 .hsync_end = 800 + 1 + 64, 3450 .htotal = 800 + 1 + 64 + 64, 3451 .vdisplay = 480, 3452 .vsync_start = 480 + 1, 3453 .vsync_end = 480 + 1 + 23, 3454 .vtotal = 480 + 1 + 23 + 22, 3455 }; 3456 3457 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3458 .modes = &shelly_sca07010_bfn_lnn_mode, 3459 .num_modes = 1, 3460 .size = { 3461 .width = 152, 3462 .height = 91, 3463 }, 3464 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3465 }; 3466 3467 static const struct drm_display_mode starry_kr070pe2t_mode = { 3468 .clock = 33000, 3469 .hdisplay = 800, 3470 .hsync_start = 800 + 209, 3471 .hsync_end = 800 + 209 + 1, 3472 .htotal = 800 + 209 + 1 + 45, 3473 .vdisplay = 480, 3474 .vsync_start = 480 + 22, 3475 .vsync_end = 480 + 22 + 1, 3476 .vtotal = 480 + 22 + 1 + 22, 3477 }; 3478 3479 static const struct panel_desc starry_kr070pe2t = { 3480 .modes = &starry_kr070pe2t_mode, 3481 .num_modes = 1, 3482 .bpc = 8, 3483 .size = { 3484 .width = 152, 3485 .height = 86, 3486 }, 3487 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3488 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3489 .connector_type = DRM_MODE_CONNECTOR_DPI, 3490 }; 3491 3492 static const struct display_timing startek_kd070wvfpa_mode = { 3493 .pixelclock = { 25200000, 27200000, 30500000 }, 3494 .hactive = { 800, 800, 800 }, 3495 .hfront_porch = { 19, 44, 115 }, 3496 .hback_porch = { 5, 16, 101 }, 3497 .hsync_len = { 1, 2, 100 }, 3498 .vactive = { 480, 480, 480 }, 3499 .vfront_porch = { 5, 43, 67 }, 3500 .vback_porch = { 5, 5, 67 }, 3501 .vsync_len = { 1, 2, 66 }, 3502 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3503 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3504 DISPLAY_FLAGS_SYNC_POSEDGE, 3505 }; 3506 3507 static const struct panel_desc startek_kd070wvfpa = { 3508 .timings = &startek_kd070wvfpa_mode, 3509 .num_timings = 1, 3510 .bpc = 8, 3511 .size = { 3512 .width = 152, 3513 .height = 91, 3514 }, 3515 .delay = { 3516 .prepare = 20, 3517 .enable = 200, 3518 .disable = 200, 3519 }, 3520 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3521 .connector_type = DRM_MODE_CONNECTOR_DPI, 3522 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3523 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3524 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3525 }; 3526 3527 static const struct display_timing tsd_tst043015cmhx_timing = { 3528 .pixelclock = { 5000000, 9000000, 12000000 }, 3529 .hactive = { 480, 480, 480 }, 3530 .hfront_porch = { 4, 5, 65 }, 3531 .hback_porch = { 36, 40, 255 }, 3532 .hsync_len = { 1, 1, 1 }, 3533 .vactive = { 272, 272, 272 }, 3534 .vfront_porch = { 2, 8, 97 }, 3535 .vback_porch = { 3, 8, 31 }, 3536 .vsync_len = { 1, 1, 1 }, 3537 3538 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3539 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3540 }; 3541 3542 static const struct panel_desc tsd_tst043015cmhx = { 3543 .timings = &tsd_tst043015cmhx_timing, 3544 .num_timings = 1, 3545 .bpc = 8, 3546 .size = { 3547 .width = 105, 3548 .height = 67, 3549 }, 3550 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3551 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3552 }; 3553 3554 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3555 .clock = 30000, 3556 .hdisplay = 800, 3557 .hsync_start = 800 + 39, 3558 .hsync_end = 800 + 39 + 47, 3559 .htotal = 800 + 39 + 47 + 39, 3560 .vdisplay = 480, 3561 .vsync_start = 480 + 13, 3562 .vsync_end = 480 + 13 + 2, 3563 .vtotal = 480 + 13 + 2 + 29, 3564 }; 3565 3566 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3567 .modes = &tfc_s9700rtwv43tr_01b_mode, 3568 .num_modes = 1, 3569 .bpc = 8, 3570 .size = { 3571 .width = 155, 3572 .height = 90, 3573 }, 3574 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3575 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3576 }; 3577 3578 static const struct display_timing tianma_tm070jdhg30_timing = { 3579 .pixelclock = { 62600000, 68200000, 78100000 }, 3580 .hactive = { 1280, 1280, 1280 }, 3581 .hfront_porch = { 15, 64, 159 }, 3582 .hback_porch = { 5, 5, 5 }, 3583 .hsync_len = { 1, 1, 256 }, 3584 .vactive = { 800, 800, 800 }, 3585 .vfront_porch = { 3, 40, 99 }, 3586 .vback_porch = { 2, 2, 2 }, 3587 .vsync_len = { 1, 1, 128 }, 3588 .flags = DISPLAY_FLAGS_DE_HIGH, 3589 }; 3590 3591 static const struct panel_desc tianma_tm070jdhg30 = { 3592 .timings = &tianma_tm070jdhg30_timing, 3593 .num_timings = 1, 3594 .bpc = 8, 3595 .size = { 3596 .width = 151, 3597 .height = 95, 3598 }, 3599 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3600 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3601 }; 3602 3603 static const struct panel_desc tianma_tm070jvhg33 = { 3604 .timings = &tianma_tm070jdhg30_timing, 3605 .num_timings = 1, 3606 .bpc = 8, 3607 .size = { 3608 .width = 150, 3609 .height = 94, 3610 }, 3611 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3612 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3613 }; 3614 3615 static const struct display_timing tianma_tm070rvhg71_timing = { 3616 .pixelclock = { 27700000, 29200000, 39600000 }, 3617 .hactive = { 800, 800, 800 }, 3618 .hfront_porch = { 12, 40, 212 }, 3619 .hback_porch = { 88, 88, 88 }, 3620 .hsync_len = { 1, 1, 40 }, 3621 .vactive = { 480, 480, 480 }, 3622 .vfront_porch = { 1, 13, 88 }, 3623 .vback_porch = { 32, 32, 32 }, 3624 .vsync_len = { 1, 1, 3 }, 3625 .flags = DISPLAY_FLAGS_DE_HIGH, 3626 }; 3627 3628 static const struct panel_desc tianma_tm070rvhg71 = { 3629 .timings = &tianma_tm070rvhg71_timing, 3630 .num_timings = 1, 3631 .bpc = 8, 3632 .size = { 3633 .width = 154, 3634 .height = 86, 3635 }, 3636 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3637 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3638 }; 3639 3640 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3641 { 3642 .clock = 10000, 3643 .hdisplay = 320, 3644 .hsync_start = 320 + 50, 3645 .hsync_end = 320 + 50 + 6, 3646 .htotal = 320 + 50 + 6 + 38, 3647 .vdisplay = 240, 3648 .vsync_start = 240 + 3, 3649 .vsync_end = 240 + 3 + 1, 3650 .vtotal = 240 + 3 + 1 + 17, 3651 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3652 }, 3653 }; 3654 3655 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3656 .modes = ti_nspire_cx_lcd_mode, 3657 .num_modes = 1, 3658 .bpc = 8, 3659 .size = { 3660 .width = 65, 3661 .height = 49, 3662 }, 3663 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3664 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3665 }; 3666 3667 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3668 { 3669 .clock = 10000, 3670 .hdisplay = 320, 3671 .hsync_start = 320 + 6, 3672 .hsync_end = 320 + 6 + 6, 3673 .htotal = 320 + 6 + 6 + 6, 3674 .vdisplay = 240, 3675 .vsync_start = 240 + 0, 3676 .vsync_end = 240 + 0 + 1, 3677 .vtotal = 240 + 0 + 1 + 0, 3678 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3679 }, 3680 }; 3681 3682 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3683 .modes = ti_nspire_classic_lcd_mode, 3684 .num_modes = 1, 3685 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3686 .bpc = 8, 3687 .size = { 3688 .width = 71, 3689 .height = 53, 3690 }, 3691 /* This is the grayscale bus format */ 3692 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3693 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3694 }; 3695 3696 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3697 .clock = 79500, 3698 .hdisplay = 1280, 3699 .hsync_start = 1280 + 192, 3700 .hsync_end = 1280 + 192 + 128, 3701 .htotal = 1280 + 192 + 128 + 64, 3702 .vdisplay = 768, 3703 .vsync_start = 768 + 20, 3704 .vsync_end = 768 + 20 + 7, 3705 .vtotal = 768 + 20 + 7 + 3, 3706 }; 3707 3708 static const struct panel_desc toshiba_lt089ac29000 = { 3709 .modes = &toshiba_lt089ac29000_mode, 3710 .num_modes = 1, 3711 .size = { 3712 .width = 194, 3713 .height = 116, 3714 }, 3715 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3716 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3717 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3718 }; 3719 3720 static const struct drm_display_mode tpk_f07a_0102_mode = { 3721 .clock = 33260, 3722 .hdisplay = 800, 3723 .hsync_start = 800 + 40, 3724 .hsync_end = 800 + 40 + 128, 3725 .htotal = 800 + 40 + 128 + 88, 3726 .vdisplay = 480, 3727 .vsync_start = 480 + 10, 3728 .vsync_end = 480 + 10 + 2, 3729 .vtotal = 480 + 10 + 2 + 33, 3730 }; 3731 3732 static const struct panel_desc tpk_f07a_0102 = { 3733 .modes = &tpk_f07a_0102_mode, 3734 .num_modes = 1, 3735 .size = { 3736 .width = 152, 3737 .height = 91, 3738 }, 3739 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3740 }; 3741 3742 static const struct drm_display_mode tpk_f10a_0102_mode = { 3743 .clock = 45000, 3744 .hdisplay = 1024, 3745 .hsync_start = 1024 + 176, 3746 .hsync_end = 1024 + 176 + 5, 3747 .htotal = 1024 + 176 + 5 + 88, 3748 .vdisplay = 600, 3749 .vsync_start = 600 + 20, 3750 .vsync_end = 600 + 20 + 5, 3751 .vtotal = 600 + 20 + 5 + 25, 3752 }; 3753 3754 static const struct panel_desc tpk_f10a_0102 = { 3755 .modes = &tpk_f10a_0102_mode, 3756 .num_modes = 1, 3757 .size = { 3758 .width = 223, 3759 .height = 125, 3760 }, 3761 }; 3762 3763 static const struct display_timing urt_umsh_8596md_timing = { 3764 .pixelclock = { 33260000, 33260000, 33260000 }, 3765 .hactive = { 800, 800, 800 }, 3766 .hfront_porch = { 41, 41, 41 }, 3767 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3768 .hsync_len = { 71, 128, 128 }, 3769 .vactive = { 480, 480, 480 }, 3770 .vfront_porch = { 10, 10, 10 }, 3771 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3772 .vsync_len = { 2, 2, 2 }, 3773 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3774 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3775 }; 3776 3777 static const struct panel_desc urt_umsh_8596md_lvds = { 3778 .timings = &urt_umsh_8596md_timing, 3779 .num_timings = 1, 3780 .bpc = 6, 3781 .size = { 3782 .width = 152, 3783 .height = 91, 3784 }, 3785 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3786 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3787 }; 3788 3789 static const struct panel_desc urt_umsh_8596md_parallel = { 3790 .timings = &urt_umsh_8596md_timing, 3791 .num_timings = 1, 3792 .bpc = 6, 3793 .size = { 3794 .width = 152, 3795 .height = 91, 3796 }, 3797 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3798 }; 3799 3800 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 3801 .clock = 60000, 3802 .hdisplay = 1024, 3803 .hsync_start = 1024 + 160, 3804 .hsync_end = 1024 + 160 + 100, 3805 .htotal = 1024 + 160 + 100 + 60, 3806 .vdisplay = 600, 3807 .vsync_start = 600 + 12, 3808 .vsync_end = 600 + 12 + 10, 3809 .vtotal = 600 + 12 + 10 + 13, 3810 }; 3811 3812 static const struct panel_desc vivax_tpc9150_panel = { 3813 .modes = &vivax_tpc9150_panel_mode, 3814 .num_modes = 1, 3815 .bpc = 6, 3816 .size = { 3817 .width = 200, 3818 .height = 115, 3819 }, 3820 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3821 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3822 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3823 }; 3824 3825 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3826 .clock = 33333, 3827 .hdisplay = 800, 3828 .hsync_start = 800 + 210, 3829 .hsync_end = 800 + 210 + 20, 3830 .htotal = 800 + 210 + 20 + 46, 3831 .vdisplay = 480, 3832 .vsync_start = 480 + 22, 3833 .vsync_end = 480 + 22 + 10, 3834 .vtotal = 480 + 22 + 10 + 23, 3835 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3836 }; 3837 3838 static const struct panel_desc vl050_8048nt_c01 = { 3839 .modes = &vl050_8048nt_c01_mode, 3840 .num_modes = 1, 3841 .bpc = 8, 3842 .size = { 3843 .width = 120, 3844 .height = 76, 3845 }, 3846 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3847 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3848 }; 3849 3850 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3851 .clock = 6410, 3852 .hdisplay = 320, 3853 .hsync_start = 320 + 20, 3854 .hsync_end = 320 + 20 + 30, 3855 .htotal = 320 + 20 + 30 + 38, 3856 .vdisplay = 240, 3857 .vsync_start = 240 + 4, 3858 .vsync_end = 240 + 4 + 3, 3859 .vtotal = 240 + 4 + 3 + 15, 3860 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3861 }; 3862 3863 static const struct panel_desc winstar_wf35ltiacd = { 3864 .modes = &winstar_wf35ltiacd_mode, 3865 .num_modes = 1, 3866 .bpc = 8, 3867 .size = { 3868 .width = 70, 3869 .height = 53, 3870 }, 3871 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3872 }; 3873 3874 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 3875 .clock = 51200, 3876 .hdisplay = 1024, 3877 .hsync_start = 1024 + 100, 3878 .hsync_end = 1024 + 100 + 100, 3879 .htotal = 1024 + 100 + 100 + 120, 3880 .vdisplay = 600, 3881 .vsync_start = 600 + 10, 3882 .vsync_end = 600 + 10 + 10, 3883 .vtotal = 600 + 10 + 10 + 15, 3884 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3885 }; 3886 3887 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 3888 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 3889 .num_modes = 1, 3890 .bpc = 8, 3891 .size = { 3892 .width = 154, 3893 .height = 90, 3894 }, 3895 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3896 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3897 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3898 }; 3899 3900 static const struct drm_display_mode arm_rtsm_mode[] = { 3901 { 3902 .clock = 65000, 3903 .hdisplay = 1024, 3904 .hsync_start = 1024 + 24, 3905 .hsync_end = 1024 + 24 + 136, 3906 .htotal = 1024 + 24 + 136 + 160, 3907 .vdisplay = 768, 3908 .vsync_start = 768 + 3, 3909 .vsync_end = 768 + 3 + 6, 3910 .vtotal = 768 + 3 + 6 + 29, 3911 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3912 }, 3913 }; 3914 3915 static const struct panel_desc arm_rtsm = { 3916 .modes = arm_rtsm_mode, 3917 .num_modes = 1, 3918 .bpc = 8, 3919 .size = { 3920 .width = 400, 3921 .height = 300, 3922 }, 3923 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3924 }; 3925 3926 static const struct of_device_id platform_of_match[] = { 3927 { 3928 .compatible = "ampire,am-1280800n3tzqw-t00h", 3929 .data = &ire_am_1280800n3tzqw_t00h, 3930 }, { 3931 .compatible = "ampire,am-480272h3tmqw-t01h", 3932 .data = &ire_am_480272h3tmqw_t01h, 3933 }, { 3934 .compatible = "ampire,am800480r3tmqwa1h", 3935 .data = &ire_am800480r3tmqwa1h, 3936 }, { 3937 .compatible = "ampire,am800600p5tmqw-tb8h", 3938 .data = &ire_am800600p5tmqwtb8h, 3939 }, { 3940 .compatible = "arm,rtsm-display", 3941 .data = &arm_rtsm, 3942 }, { 3943 .compatible = "armadeus,st0700-adapt", 3944 .data = &armadeus_st0700_adapt, 3945 }, { 3946 .compatible = "auo,b101aw03", 3947 .data = &auo_b101aw03, 3948 }, { 3949 .compatible = "auo,b101xtn01", 3950 .data = &auo_b101xtn01, 3951 }, { 3952 .compatible = "auo,g070vvn01", 3953 .data = &auo_g070vvn01, 3954 }, { 3955 .compatible = "auo,g101evn010", 3956 .data = &auo_g101evn010, 3957 }, { 3958 .compatible = "auo,g104sn02", 3959 .data = &auo_g104sn02, 3960 }, { 3961 .compatible = "auo,g121ean01", 3962 .data = &auo_g121ean01, 3963 }, { 3964 .compatible = "auo,g133han01", 3965 .data = &auo_g133han01, 3966 }, { 3967 .compatible = "auo,g156xtn01", 3968 .data = &auo_g156xtn01, 3969 }, { 3970 .compatible = "auo,g185han01", 3971 .data = &auo_g185han01, 3972 }, { 3973 .compatible = "auo,g190ean01", 3974 .data = &auo_g190ean01, 3975 }, { 3976 .compatible = "auo,p320hvn03", 3977 .data = &auo_p320hvn03, 3978 }, { 3979 .compatible = "auo,t215hvn01", 3980 .data = &auo_t215hvn01, 3981 }, { 3982 .compatible = "avic,tm070ddh03", 3983 .data = &avic_tm070ddh03, 3984 }, { 3985 .compatible = "bananapi,s070wv20-ct16", 3986 .data = &bananapi_s070wv20_ct16, 3987 }, { 3988 .compatible = "boe,hv070wsa-100", 3989 .data = &boe_hv070wsa 3990 }, { 3991 .compatible = "cdtech,s043wq26h-ct7", 3992 .data = &cdtech_s043wq26h_ct7, 3993 }, { 3994 .compatible = "cdtech,s070pws19hp-fc21", 3995 .data = &cdtech_s070pws19hp_fc21, 3996 }, { 3997 .compatible = "cdtech,s070swv29hg-dc44", 3998 .data = &cdtech_s070swv29hg_dc44, 3999 }, { 4000 .compatible = "cdtech,s070wv95-ct16", 4001 .data = &cdtech_s070wv95_ct16, 4002 }, { 4003 .compatible = "chefree,ch101olhlwh-002", 4004 .data = &chefree_ch101olhlwh_002, 4005 }, { 4006 .compatible = "chunghwa,claa070wp03xg", 4007 .data = &chunghwa_claa070wp03xg, 4008 }, { 4009 .compatible = "chunghwa,claa101wa01a", 4010 .data = &chunghwa_claa101wa01a 4011 }, { 4012 .compatible = "chunghwa,claa101wb01", 4013 .data = &chunghwa_claa101wb01 4014 }, { 4015 .compatible = "dataimage,fg040346dsswbg04", 4016 .data = &dataimage_fg040346dsswbg04, 4017 }, { 4018 .compatible = "dataimage,fg1001l0dsswmg01", 4019 .data = &dataimage_fg1001l0dsswmg01, 4020 }, { 4021 .compatible = "dataimage,scf0700c48ggu18", 4022 .data = &dataimage_scf0700c48ggu18, 4023 }, { 4024 .compatible = "dlc,dlc0700yzg-1", 4025 .data = &dlc_dlc0700yzg_1, 4026 }, { 4027 .compatible = "dlc,dlc1010gig", 4028 .data = &dlc_dlc1010gig, 4029 }, { 4030 .compatible = "edt,et035012dm6", 4031 .data = &edt_et035012dm6, 4032 }, { 4033 .compatible = "edt,etm0350g0dh6", 4034 .data = &edt_etm0350g0dh6, 4035 }, { 4036 .compatible = "edt,etm043080dh6gp", 4037 .data = &edt_etm043080dh6gp, 4038 }, { 4039 .compatible = "edt,etm0430g0dh6", 4040 .data = &edt_etm0430g0dh6, 4041 }, { 4042 .compatible = "edt,et057090dhu", 4043 .data = &edt_et057090dhu, 4044 }, { 4045 .compatible = "edt,et070080dh6", 4046 .data = &edt_etm0700g0dh6, 4047 }, { 4048 .compatible = "edt,etm0700g0dh6", 4049 .data = &edt_etm0700g0dh6, 4050 }, { 4051 .compatible = "edt,etm0700g0bdh6", 4052 .data = &edt_etm0700g0bdh6, 4053 }, { 4054 .compatible = "edt,etm0700g0edh6", 4055 .data = &edt_etm0700g0bdh6, 4056 }, { 4057 .compatible = "edt,etml0700y5dha", 4058 .data = &edt_etml0700y5dha, 4059 }, { 4060 .compatible = "edt,etmv570g2dhu", 4061 .data = &edt_etmv570g2dhu, 4062 }, { 4063 .compatible = "eink,vb3300-kca", 4064 .data = &eink_vb3300_kca, 4065 }, { 4066 .compatible = "evervision,vgg804821", 4067 .data = &evervision_vgg804821, 4068 }, { 4069 .compatible = "foxlink,fl500wvr00-a0t", 4070 .data = &foxlink_fl500wvr00_a0t, 4071 }, { 4072 .compatible = "frida,frd350h54004", 4073 .data = &frida_frd350h54004, 4074 }, { 4075 .compatible = "friendlyarm,hd702e", 4076 .data = &friendlyarm_hd702e, 4077 }, { 4078 .compatible = "giantplus,gpg482739qs5", 4079 .data = &giantplus_gpg482739qs5 4080 }, { 4081 .compatible = "giantplus,gpm940b0", 4082 .data = &giantplus_gpm940b0, 4083 }, { 4084 .compatible = "hannstar,hsd070pww1", 4085 .data = &hannstar_hsd070pww1, 4086 }, { 4087 .compatible = "hannstar,hsd100pxn1", 4088 .data = &hannstar_hsd100pxn1, 4089 }, { 4090 .compatible = "hannstar,hsd101pww2", 4091 .data = &hannstar_hsd101pww2, 4092 }, { 4093 .compatible = "hit,tx23d38vm0caa", 4094 .data = &hitachi_tx23d38vm0caa 4095 }, { 4096 .compatible = "innolux,at043tn24", 4097 .data = &innolux_at043tn24, 4098 }, { 4099 .compatible = "innolux,at070tn92", 4100 .data = &innolux_at070tn92, 4101 }, { 4102 .compatible = "innolux,g070y2-l01", 4103 .data = &innolux_g070y2_l01, 4104 }, { 4105 .compatible = "innolux,g070y2-t02", 4106 .data = &innolux_g070y2_t02, 4107 }, { 4108 .compatible = "innolux,g101ice-l01", 4109 .data = &innolux_g101ice_l01 4110 }, { 4111 .compatible = "innolux,g121i1-l01", 4112 .data = &innolux_g121i1_l01 4113 }, { 4114 .compatible = "innolux,g121x1-l03", 4115 .data = &innolux_g121x1_l03, 4116 }, { 4117 .compatible = "innolux,n156bge-l21", 4118 .data = &innolux_n156bge_l21, 4119 }, { 4120 .compatible = "innolux,zj070na-01p", 4121 .data = &innolux_zj070na_01p, 4122 }, { 4123 .compatible = "koe,tx14d24vm1bpa", 4124 .data = &koe_tx14d24vm1bpa, 4125 }, { 4126 .compatible = "koe,tx26d202vm0bwa", 4127 .data = &koe_tx26d202vm0bwa, 4128 }, { 4129 .compatible = "koe,tx31d200vm0baa", 4130 .data = &koe_tx31d200vm0baa, 4131 }, { 4132 .compatible = "kyo,tcg121xglp", 4133 .data = &kyo_tcg121xglp, 4134 }, { 4135 .compatible = "lemaker,bl035-rgb-002", 4136 .data = &lemaker_bl035_rgb_002, 4137 }, { 4138 .compatible = "lg,lb070wv8", 4139 .data = &lg_lb070wv8, 4140 }, { 4141 .compatible = "logicpd,type28", 4142 .data = &logicpd_type_28, 4143 }, { 4144 .compatible = "logictechno,lt161010-2nhc", 4145 .data = &logictechno_lt161010_2nh, 4146 }, { 4147 .compatible = "logictechno,lt161010-2nhr", 4148 .data = &logictechno_lt161010_2nh, 4149 }, { 4150 .compatible = "logictechno,lt170410-2whc", 4151 .data = &logictechno_lt170410_2whc, 4152 }, { 4153 .compatible = "logictechno,lttd800480070-l2rt", 4154 .data = &logictechno_lttd800480070_l2rt, 4155 }, { 4156 .compatible = "logictechno,lttd800480070-l6wh-rt", 4157 .data = &logictechno_lttd800480070_l6wh_rt, 4158 }, { 4159 .compatible = "mitsubishi,aa070mc01-ca1", 4160 .data = &mitsubishi_aa070mc01, 4161 }, { 4162 .compatible = "multi-inno,mi0700s4t-6", 4163 .data = &multi_inno_mi0700s4t_6, 4164 }, { 4165 .compatible = "multi-inno,mi0800ft-9", 4166 .data = &multi_inno_mi0800ft_9, 4167 }, { 4168 .compatible = "multi-inno,mi1010ait-1cp", 4169 .data = &multi_inno_mi1010ait_1cp, 4170 }, { 4171 .compatible = "nec,nl12880bc20-05", 4172 .data = &nec_nl12880bc20_05, 4173 }, { 4174 .compatible = "nec,nl4827hc19-05b", 4175 .data = &nec_nl4827hc19_05b, 4176 }, { 4177 .compatible = "netron-dy,e231732", 4178 .data = &netron_dy_e231732, 4179 }, { 4180 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4181 .data = &newhaven_nhd_43_480272ef_atxl, 4182 }, { 4183 .compatible = "nlt,nl192108ac18-02d", 4184 .data = &nlt_nl192108ac18_02d, 4185 }, { 4186 .compatible = "nvd,9128", 4187 .data = &nvd_9128, 4188 }, { 4189 .compatible = "okaya,rs800480t-7x0gp", 4190 .data = &okaya_rs800480t_7x0gp, 4191 }, { 4192 .compatible = "olimex,lcd-olinuxino-43-ts", 4193 .data = &olimex_lcd_olinuxino_43ts, 4194 }, { 4195 .compatible = "ontat,yx700wv03", 4196 .data = &ontat_yx700wv03, 4197 }, { 4198 .compatible = "ortustech,com37h3m05dtc", 4199 .data = &ortustech_com37h3m, 4200 }, { 4201 .compatible = "ortustech,com37h3m99dtc", 4202 .data = &ortustech_com37h3m, 4203 }, { 4204 .compatible = "ortustech,com43h4m85ulc", 4205 .data = &ortustech_com43h4m85ulc, 4206 }, { 4207 .compatible = "osddisplays,osd070t1718-19ts", 4208 .data = &osddisplays_osd070t1718_19ts, 4209 }, { 4210 .compatible = "pda,91-00156-a0", 4211 .data = &pda_91_00156_a0, 4212 }, { 4213 .compatible = "powertip,ph800480t013-idf02", 4214 .data = &powertip_ph800480t013_idf02, 4215 }, { 4216 .compatible = "qiaodian,qd43003c0-40", 4217 .data = &qd43003c0_40, 4218 }, { 4219 .compatible = "qishenglong,gopher2b-lcd", 4220 .data = &qishenglong_gopher2b_lcd, 4221 }, { 4222 .compatible = "rocktech,rk070er9427", 4223 .data = &rocktech_rk070er9427, 4224 }, { 4225 .compatible = "rocktech,rk101ii01d-ct", 4226 .data = &rocktech_rk101ii01d_ct, 4227 }, { 4228 .compatible = "samsung,ltl101al01", 4229 .data = &samsung_ltl101al01, 4230 }, { 4231 .compatible = "samsung,ltn101nt05", 4232 .data = &samsung_ltn101nt05, 4233 }, { 4234 .compatible = "satoz,sat050at40h12r2", 4235 .data = &satoz_sat050at40h12r2, 4236 }, { 4237 .compatible = "sharp,lq035q7db03", 4238 .data = &sharp_lq035q7db03, 4239 }, { 4240 .compatible = "sharp,lq070y3dg3b", 4241 .data = &sharp_lq070y3dg3b, 4242 }, { 4243 .compatible = "sharp,lq101k1ly04", 4244 .data = &sharp_lq101k1ly04, 4245 }, { 4246 .compatible = "sharp,ls020b1dd01d", 4247 .data = &sharp_ls020b1dd01d, 4248 }, { 4249 .compatible = "shelly,sca07010-bfn-lnn", 4250 .data = &shelly_sca07010_bfn_lnn, 4251 }, { 4252 .compatible = "starry,kr070pe2t", 4253 .data = &starry_kr070pe2t, 4254 }, { 4255 .compatible = "startek,kd070wvfpa", 4256 .data = &startek_kd070wvfpa, 4257 }, { 4258 .compatible = "team-source-display,tst043015cmhx", 4259 .data = &tsd_tst043015cmhx, 4260 }, { 4261 .compatible = "tfc,s9700rtwv43tr-01b", 4262 .data = &tfc_s9700rtwv43tr_01b, 4263 }, { 4264 .compatible = "tianma,tm070jdhg30", 4265 .data = &tianma_tm070jdhg30, 4266 }, { 4267 .compatible = "tianma,tm070jvhg33", 4268 .data = &tianma_tm070jvhg33, 4269 }, { 4270 .compatible = "tianma,tm070rvhg71", 4271 .data = &tianma_tm070rvhg71, 4272 }, { 4273 .compatible = "ti,nspire-cx-lcd-panel", 4274 .data = &ti_nspire_cx_lcd_panel, 4275 }, { 4276 .compatible = "ti,nspire-classic-lcd-panel", 4277 .data = &ti_nspire_classic_lcd_panel, 4278 }, { 4279 .compatible = "toshiba,lt089ac29000", 4280 .data = &toshiba_lt089ac29000, 4281 }, { 4282 .compatible = "tpk,f07a-0102", 4283 .data = &tpk_f07a_0102, 4284 }, { 4285 .compatible = "tpk,f10a-0102", 4286 .data = &tpk_f10a_0102, 4287 }, { 4288 .compatible = "urt,umsh-8596md-t", 4289 .data = &urt_umsh_8596md_parallel, 4290 }, { 4291 .compatible = "urt,umsh-8596md-1t", 4292 .data = &urt_umsh_8596md_parallel, 4293 }, { 4294 .compatible = "urt,umsh-8596md-7t", 4295 .data = &urt_umsh_8596md_parallel, 4296 }, { 4297 .compatible = "urt,umsh-8596md-11t", 4298 .data = &urt_umsh_8596md_lvds, 4299 }, { 4300 .compatible = "urt,umsh-8596md-19t", 4301 .data = &urt_umsh_8596md_lvds, 4302 }, { 4303 .compatible = "urt,umsh-8596md-20t", 4304 .data = &urt_umsh_8596md_parallel, 4305 }, { 4306 .compatible = "vivax,tpc9150-panel", 4307 .data = &vivax_tpc9150_panel, 4308 }, { 4309 .compatible = "vxt,vl050-8048nt-c01", 4310 .data = &vl050_8048nt_c01, 4311 }, { 4312 .compatible = "winstar,wf35ltiacd", 4313 .data = &winstar_wf35ltiacd, 4314 }, { 4315 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4316 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4317 }, { 4318 /* Must be the last entry */ 4319 .compatible = "panel-dpi", 4320 .data = &panel_dpi, 4321 }, { 4322 /* sentinel */ 4323 } 4324 }; 4325 MODULE_DEVICE_TABLE(of, platform_of_match); 4326 4327 static int panel_simple_platform_probe(struct platform_device *pdev) 4328 { 4329 const struct of_device_id *id; 4330 4331 id = of_match_node(platform_of_match, pdev->dev.of_node); 4332 if (!id) 4333 return -ENODEV; 4334 4335 return panel_simple_probe(&pdev->dev, id->data); 4336 } 4337 4338 static int panel_simple_platform_remove(struct platform_device *pdev) 4339 { 4340 panel_simple_remove(&pdev->dev); 4341 4342 return 0; 4343 } 4344 4345 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4346 { 4347 panel_simple_shutdown(&pdev->dev); 4348 } 4349 4350 static const struct dev_pm_ops panel_simple_pm_ops = { 4351 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4352 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4353 pm_runtime_force_resume) 4354 }; 4355 4356 static struct platform_driver panel_simple_platform_driver = { 4357 .driver = { 4358 .name = "panel-simple", 4359 .of_match_table = platform_of_match, 4360 .pm = &panel_simple_pm_ops, 4361 }, 4362 .probe = panel_simple_platform_probe, 4363 .remove = panel_simple_platform_remove, 4364 .shutdown = panel_simple_platform_shutdown, 4365 }; 4366 4367 struct panel_desc_dsi { 4368 struct panel_desc desc; 4369 4370 unsigned long flags; 4371 enum mipi_dsi_pixel_format format; 4372 unsigned int lanes; 4373 }; 4374 4375 static const struct drm_display_mode auo_b080uan01_mode = { 4376 .clock = 154500, 4377 .hdisplay = 1200, 4378 .hsync_start = 1200 + 62, 4379 .hsync_end = 1200 + 62 + 4, 4380 .htotal = 1200 + 62 + 4 + 62, 4381 .vdisplay = 1920, 4382 .vsync_start = 1920 + 9, 4383 .vsync_end = 1920 + 9 + 2, 4384 .vtotal = 1920 + 9 + 2 + 8, 4385 }; 4386 4387 static const struct panel_desc_dsi auo_b080uan01 = { 4388 .desc = { 4389 .modes = &auo_b080uan01_mode, 4390 .num_modes = 1, 4391 .bpc = 8, 4392 .size = { 4393 .width = 108, 4394 .height = 272, 4395 }, 4396 .connector_type = DRM_MODE_CONNECTOR_DSI, 4397 }, 4398 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4399 .format = MIPI_DSI_FMT_RGB888, 4400 .lanes = 4, 4401 }; 4402 4403 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4404 .clock = 160000, 4405 .hdisplay = 1200, 4406 .hsync_start = 1200 + 120, 4407 .hsync_end = 1200 + 120 + 20, 4408 .htotal = 1200 + 120 + 20 + 21, 4409 .vdisplay = 1920, 4410 .vsync_start = 1920 + 21, 4411 .vsync_end = 1920 + 21 + 3, 4412 .vtotal = 1920 + 21 + 3 + 18, 4413 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4414 }; 4415 4416 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4417 .desc = { 4418 .modes = &boe_tv080wum_nl0_mode, 4419 .num_modes = 1, 4420 .size = { 4421 .width = 107, 4422 .height = 172, 4423 }, 4424 .connector_type = DRM_MODE_CONNECTOR_DSI, 4425 }, 4426 .flags = MIPI_DSI_MODE_VIDEO | 4427 MIPI_DSI_MODE_VIDEO_BURST | 4428 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4429 .format = MIPI_DSI_FMT_RGB888, 4430 .lanes = 4, 4431 }; 4432 4433 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4434 .clock = 71000, 4435 .hdisplay = 800, 4436 .hsync_start = 800 + 32, 4437 .hsync_end = 800 + 32 + 1, 4438 .htotal = 800 + 32 + 1 + 57, 4439 .vdisplay = 1280, 4440 .vsync_start = 1280 + 28, 4441 .vsync_end = 1280 + 28 + 1, 4442 .vtotal = 1280 + 28 + 1 + 14, 4443 }; 4444 4445 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4446 .desc = { 4447 .modes = &lg_ld070wx3_sl01_mode, 4448 .num_modes = 1, 4449 .bpc = 8, 4450 .size = { 4451 .width = 94, 4452 .height = 151, 4453 }, 4454 .connector_type = DRM_MODE_CONNECTOR_DSI, 4455 }, 4456 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4457 .format = MIPI_DSI_FMT_RGB888, 4458 .lanes = 4, 4459 }; 4460 4461 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4462 .clock = 67000, 4463 .hdisplay = 720, 4464 .hsync_start = 720 + 12, 4465 .hsync_end = 720 + 12 + 4, 4466 .htotal = 720 + 12 + 4 + 112, 4467 .vdisplay = 1280, 4468 .vsync_start = 1280 + 8, 4469 .vsync_end = 1280 + 8 + 4, 4470 .vtotal = 1280 + 8 + 4 + 12, 4471 }; 4472 4473 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4474 .desc = { 4475 .modes = &lg_lh500wx1_sd03_mode, 4476 .num_modes = 1, 4477 .bpc = 8, 4478 .size = { 4479 .width = 62, 4480 .height = 110, 4481 }, 4482 .connector_type = DRM_MODE_CONNECTOR_DSI, 4483 }, 4484 .flags = MIPI_DSI_MODE_VIDEO, 4485 .format = MIPI_DSI_FMT_RGB888, 4486 .lanes = 4, 4487 }; 4488 4489 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4490 .clock = 157200, 4491 .hdisplay = 1920, 4492 .hsync_start = 1920 + 154, 4493 .hsync_end = 1920 + 154 + 16, 4494 .htotal = 1920 + 154 + 16 + 32, 4495 .vdisplay = 1200, 4496 .vsync_start = 1200 + 17, 4497 .vsync_end = 1200 + 17 + 2, 4498 .vtotal = 1200 + 17 + 2 + 16, 4499 }; 4500 4501 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4502 .desc = { 4503 .modes = &panasonic_vvx10f004b00_mode, 4504 .num_modes = 1, 4505 .bpc = 8, 4506 .size = { 4507 .width = 217, 4508 .height = 136, 4509 }, 4510 .connector_type = DRM_MODE_CONNECTOR_DSI, 4511 }, 4512 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4513 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4514 .format = MIPI_DSI_FMT_RGB888, 4515 .lanes = 4, 4516 }; 4517 4518 static const struct drm_display_mode lg_acx467akm_7_mode = { 4519 .clock = 150000, 4520 .hdisplay = 1080, 4521 .hsync_start = 1080 + 2, 4522 .hsync_end = 1080 + 2 + 2, 4523 .htotal = 1080 + 2 + 2 + 2, 4524 .vdisplay = 1920, 4525 .vsync_start = 1920 + 2, 4526 .vsync_end = 1920 + 2 + 2, 4527 .vtotal = 1920 + 2 + 2 + 2, 4528 }; 4529 4530 static const struct panel_desc_dsi lg_acx467akm_7 = { 4531 .desc = { 4532 .modes = &lg_acx467akm_7_mode, 4533 .num_modes = 1, 4534 .bpc = 8, 4535 .size = { 4536 .width = 62, 4537 .height = 110, 4538 }, 4539 .connector_type = DRM_MODE_CONNECTOR_DSI, 4540 }, 4541 .flags = 0, 4542 .format = MIPI_DSI_FMT_RGB888, 4543 .lanes = 4, 4544 }; 4545 4546 static const struct drm_display_mode osd101t2045_53ts_mode = { 4547 .clock = 154500, 4548 .hdisplay = 1920, 4549 .hsync_start = 1920 + 112, 4550 .hsync_end = 1920 + 112 + 16, 4551 .htotal = 1920 + 112 + 16 + 32, 4552 .vdisplay = 1200, 4553 .vsync_start = 1200 + 16, 4554 .vsync_end = 1200 + 16 + 2, 4555 .vtotal = 1200 + 16 + 2 + 16, 4556 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4557 }; 4558 4559 static const struct panel_desc_dsi osd101t2045_53ts = { 4560 .desc = { 4561 .modes = &osd101t2045_53ts_mode, 4562 .num_modes = 1, 4563 .bpc = 8, 4564 .size = { 4565 .width = 217, 4566 .height = 136, 4567 }, 4568 .connector_type = DRM_MODE_CONNECTOR_DSI, 4569 }, 4570 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4571 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4572 MIPI_DSI_MODE_NO_EOT_PACKET, 4573 .format = MIPI_DSI_FMT_RGB888, 4574 .lanes = 4, 4575 }; 4576 4577 static const struct of_device_id dsi_of_match[] = { 4578 { 4579 .compatible = "auo,b080uan01", 4580 .data = &auo_b080uan01 4581 }, { 4582 .compatible = "boe,tv080wum-nl0", 4583 .data = &boe_tv080wum_nl0 4584 }, { 4585 .compatible = "lg,ld070wx3-sl01", 4586 .data = &lg_ld070wx3_sl01 4587 }, { 4588 .compatible = "lg,lh500wx1-sd03", 4589 .data = &lg_lh500wx1_sd03 4590 }, { 4591 .compatible = "panasonic,vvx10f004b00", 4592 .data = &panasonic_vvx10f004b00 4593 }, { 4594 .compatible = "lg,acx467akm-7", 4595 .data = &lg_acx467akm_7 4596 }, { 4597 .compatible = "osddisplays,osd101t2045-53ts", 4598 .data = &osd101t2045_53ts 4599 }, { 4600 /* sentinel */ 4601 } 4602 }; 4603 MODULE_DEVICE_TABLE(of, dsi_of_match); 4604 4605 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4606 { 4607 const struct panel_desc_dsi *desc; 4608 const struct of_device_id *id; 4609 int err; 4610 4611 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4612 if (!id) 4613 return -ENODEV; 4614 4615 desc = id->data; 4616 4617 err = panel_simple_probe(&dsi->dev, &desc->desc); 4618 if (err < 0) 4619 return err; 4620 4621 dsi->mode_flags = desc->flags; 4622 dsi->format = desc->format; 4623 dsi->lanes = desc->lanes; 4624 4625 err = mipi_dsi_attach(dsi); 4626 if (err) { 4627 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4628 4629 drm_panel_remove(&panel->base); 4630 } 4631 4632 return err; 4633 } 4634 4635 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4636 { 4637 int err; 4638 4639 err = mipi_dsi_detach(dsi); 4640 if (err < 0) 4641 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4642 4643 panel_simple_remove(&dsi->dev); 4644 } 4645 4646 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4647 { 4648 panel_simple_shutdown(&dsi->dev); 4649 } 4650 4651 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4652 .driver = { 4653 .name = "panel-simple-dsi", 4654 .of_match_table = dsi_of_match, 4655 .pm = &panel_simple_pm_ops, 4656 }, 4657 .probe = panel_simple_dsi_probe, 4658 .remove = panel_simple_dsi_remove, 4659 .shutdown = panel_simple_dsi_shutdown, 4660 }; 4661 4662 static int __init panel_simple_init(void) 4663 { 4664 int err; 4665 4666 err = platform_driver_register(&panel_simple_platform_driver); 4667 if (err < 0) 4668 return err; 4669 4670 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4671 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4672 if (err < 0) 4673 goto err_did_platform_register; 4674 } 4675 4676 return 0; 4677 4678 err_did_platform_register: 4679 platform_driver_unregister(&panel_simple_platform_driver); 4680 4681 return err; 4682 } 4683 module_init(panel_simple_init); 4684 4685 static void __exit panel_simple_exit(void) 4686 { 4687 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4688 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4689 4690 platform_driver_unregister(&panel_simple_platform_driver); 4691 } 4692 module_exit(panel_simple_exit); 4693 4694 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4695 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4696 MODULE_LICENSE("GPL and additional rights"); 4697