1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/iopoll.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_mipi_dsi.h> 39 #include <drm/drm_panel.h> 40 41 /** 42 * @modes: Pointer to array of fixed modes appropriate for this panel. If 43 * only one mode then this can just be the address of this the mode. 44 * NOTE: cannot be used with "timings" and also if this is specified 45 * then you cannot override the mode in the device tree. 46 * @num_modes: Number of elements in modes array. 47 * @timings: Pointer to array of display timings. NOTE: cannot be used with 48 * "modes" and also these will be used to validate a device tree 49 * override if one is present. 50 * @num_timings: Number of elements in timings array. 51 * @bpc: Bits per color. 52 * @size: Structure containing the physical size of this panel. 53 * @delay: Structure containing various delay values for this panel. 54 * @bus_format: See MEDIA_BUS_FMT_... defines. 55 * @bus_flags: See DRM_BUS_FLAG_... defines. 56 */ 57 struct panel_desc { 58 const struct drm_display_mode *modes; 59 unsigned int num_modes; 60 const struct display_timing *timings; 61 unsigned int num_timings; 62 63 unsigned int bpc; 64 65 /** 66 * @width: width (in millimeters) of the panel's active display area 67 * @height: height (in millimeters) of the panel's active display area 68 */ 69 struct { 70 unsigned int width; 71 unsigned int height; 72 } size; 73 74 /** 75 * @prepare: the time (in milliseconds) that it takes for the panel to 76 * become ready and start receiving video data 77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot 78 * Plug Detect isn't used. 79 * @enable: the time (in milliseconds) that it takes for the panel to 80 * display the first valid frame after starting to receive 81 * video data 82 * @disable: the time (in milliseconds) that it takes for the panel to 83 * turn the display off (no content is visible) 84 * @unprepare: the time (in milliseconds) that it takes for the panel 85 * to power itself down completely 86 */ 87 struct { 88 unsigned int prepare; 89 unsigned int hpd_absent_delay; 90 unsigned int enable; 91 unsigned int disable; 92 unsigned int unprepare; 93 } delay; 94 95 u32 bus_format; 96 u32 bus_flags; 97 int connector_type; 98 }; 99 100 struct panel_simple { 101 struct drm_panel base; 102 bool prepared; 103 bool enabled; 104 bool no_hpd; 105 106 const struct panel_desc *desc; 107 108 struct regulator *supply; 109 struct i2c_adapter *ddc; 110 111 struct gpio_desc *enable_gpio; 112 struct gpio_desc *hpd_gpio; 113 114 struct drm_display_mode override_mode; 115 }; 116 117 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 118 { 119 return container_of(panel, struct panel_simple, base); 120 } 121 122 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 123 struct drm_connector *connector) 124 { 125 struct drm_display_mode *mode; 126 unsigned int i, num = 0; 127 128 for (i = 0; i < panel->desc->num_timings; i++) { 129 const struct display_timing *dt = &panel->desc->timings[i]; 130 struct videomode vm; 131 132 videomode_from_timing(dt, &vm); 133 mode = drm_mode_create(connector->dev); 134 if (!mode) { 135 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 136 dt->hactive.typ, dt->vactive.typ); 137 continue; 138 } 139 140 drm_display_mode_from_videomode(&vm, mode); 141 142 mode->type |= DRM_MODE_TYPE_DRIVER; 143 144 if (panel->desc->num_timings == 1) 145 mode->type |= DRM_MODE_TYPE_PREFERRED; 146 147 drm_mode_probed_add(connector, mode); 148 num++; 149 } 150 151 return num; 152 } 153 154 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 155 struct drm_connector *connector) 156 { 157 struct drm_display_mode *mode; 158 unsigned int i, num = 0; 159 160 for (i = 0; i < panel->desc->num_modes; i++) { 161 const struct drm_display_mode *m = &panel->desc->modes[i]; 162 163 mode = drm_mode_duplicate(connector->dev, m); 164 if (!mode) { 165 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 166 m->hdisplay, m->vdisplay, 167 drm_mode_vrefresh(m)); 168 continue; 169 } 170 171 mode->type |= DRM_MODE_TYPE_DRIVER; 172 173 if (panel->desc->num_modes == 1) 174 mode->type |= DRM_MODE_TYPE_PREFERRED; 175 176 drm_mode_set_name(mode); 177 178 drm_mode_probed_add(connector, mode); 179 num++; 180 } 181 182 return num; 183 } 184 185 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 186 struct drm_connector *connector) 187 { 188 struct drm_display_mode *mode; 189 bool has_override = panel->override_mode.type; 190 unsigned int num = 0; 191 192 if (!panel->desc) 193 return 0; 194 195 if (has_override) { 196 mode = drm_mode_duplicate(connector->dev, 197 &panel->override_mode); 198 if (mode) { 199 drm_mode_probed_add(connector, mode); 200 num = 1; 201 } else { 202 dev_err(panel->base.dev, "failed to add override mode\n"); 203 } 204 } 205 206 /* Only add timings if override was not there or failed to validate */ 207 if (num == 0 && panel->desc->num_timings) 208 num = panel_simple_get_timings_modes(panel, connector); 209 210 /* 211 * Only add fixed modes if timings/override added no mode. 212 * 213 * We should only ever have either the display timings specified 214 * or a fixed mode. Anything else is rather bogus. 215 */ 216 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 217 if (num == 0) 218 num = panel_simple_get_display_modes(panel, connector); 219 220 connector->display_info.bpc = panel->desc->bpc; 221 connector->display_info.width_mm = panel->desc->size.width; 222 connector->display_info.height_mm = panel->desc->size.height; 223 if (panel->desc->bus_format) 224 drm_display_info_set_bus_formats(&connector->display_info, 225 &panel->desc->bus_format, 1); 226 connector->display_info.bus_flags = panel->desc->bus_flags; 227 228 return num; 229 } 230 231 static int panel_simple_disable(struct drm_panel *panel) 232 { 233 struct panel_simple *p = to_panel_simple(panel); 234 235 if (!p->enabled) 236 return 0; 237 238 if (p->desc->delay.disable) 239 msleep(p->desc->delay.disable); 240 241 p->enabled = false; 242 243 return 0; 244 } 245 246 static int panel_simple_unprepare(struct drm_panel *panel) 247 { 248 struct panel_simple *p = to_panel_simple(panel); 249 250 if (!p->prepared) 251 return 0; 252 253 gpiod_set_value_cansleep(p->enable_gpio, 0); 254 255 regulator_disable(p->supply); 256 257 if (p->desc->delay.unprepare) 258 msleep(p->desc->delay.unprepare); 259 260 p->prepared = false; 261 262 return 0; 263 } 264 265 static int panel_simple_get_hpd_gpio(struct device *dev, 266 struct panel_simple *p, bool from_probe) 267 { 268 int err; 269 270 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 271 if (IS_ERR(p->hpd_gpio)) { 272 err = PTR_ERR(p->hpd_gpio); 273 274 /* 275 * If we're called from probe we won't consider '-EPROBE_DEFER' 276 * to be an error--we'll leave the error code in "hpd_gpio". 277 * When we try to use it we'll try again. This allows for 278 * circular dependencies where the component providing the 279 * hpd gpio needs the panel to init before probing. 280 */ 281 if (err != -EPROBE_DEFER || !from_probe) { 282 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err); 283 return err; 284 } 285 } 286 287 return 0; 288 } 289 290 static int panel_simple_prepare(struct drm_panel *panel) 291 { 292 struct panel_simple *p = to_panel_simple(panel); 293 unsigned int delay; 294 int err; 295 int hpd_asserted; 296 297 if (p->prepared) 298 return 0; 299 300 err = regulator_enable(p->supply); 301 if (err < 0) { 302 dev_err(panel->dev, "failed to enable supply: %d\n", err); 303 return err; 304 } 305 306 gpiod_set_value_cansleep(p->enable_gpio, 1); 307 308 delay = p->desc->delay.prepare; 309 if (p->no_hpd) 310 delay += p->desc->delay.hpd_absent_delay; 311 if (delay) 312 msleep(delay); 313 314 if (p->hpd_gpio) { 315 if (IS_ERR(p->hpd_gpio)) { 316 err = panel_simple_get_hpd_gpio(panel->dev, p, false); 317 if (err) 318 return err; 319 } 320 321 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, 322 hpd_asserted, hpd_asserted, 323 1000, 2000000); 324 if (hpd_asserted < 0) 325 err = hpd_asserted; 326 327 if (err) { 328 dev_err(panel->dev, 329 "error waiting for hpd GPIO: %d\n", err); 330 return err; 331 } 332 } 333 334 p->prepared = true; 335 336 return 0; 337 } 338 339 static int panel_simple_enable(struct drm_panel *panel) 340 { 341 struct panel_simple *p = to_panel_simple(panel); 342 343 if (p->enabled) 344 return 0; 345 346 if (p->desc->delay.enable) 347 msleep(p->desc->delay.enable); 348 349 p->enabled = true; 350 351 return 0; 352 } 353 354 static int panel_simple_get_modes(struct drm_panel *panel, 355 struct drm_connector *connector) 356 { 357 struct panel_simple *p = to_panel_simple(panel); 358 int num = 0; 359 360 /* probe EDID if a DDC bus is available */ 361 if (p->ddc) { 362 struct edid *edid = drm_get_edid(connector, p->ddc); 363 364 drm_connector_update_edid_property(connector, edid); 365 if (edid) { 366 num += drm_add_edid_modes(connector, edid); 367 kfree(edid); 368 } 369 } 370 371 /* add hard-coded panel modes */ 372 num += panel_simple_get_non_edid_modes(p, connector); 373 374 return num; 375 } 376 377 static int panel_simple_get_timings(struct drm_panel *panel, 378 unsigned int num_timings, 379 struct display_timing *timings) 380 { 381 struct panel_simple *p = to_panel_simple(panel); 382 unsigned int i; 383 384 if (p->desc->num_timings < num_timings) 385 num_timings = p->desc->num_timings; 386 387 if (timings) 388 for (i = 0; i < num_timings; i++) 389 timings[i] = p->desc->timings[i]; 390 391 return p->desc->num_timings; 392 } 393 394 static const struct drm_panel_funcs panel_simple_funcs = { 395 .disable = panel_simple_disable, 396 .unprepare = panel_simple_unprepare, 397 .prepare = panel_simple_prepare, 398 .enable = panel_simple_enable, 399 .get_modes = panel_simple_get_modes, 400 .get_timings = panel_simple_get_timings, 401 }; 402 403 static struct panel_desc panel_dpi; 404 405 static int panel_dpi_probe(struct device *dev, 406 struct panel_simple *panel) 407 { 408 struct display_timing *timing; 409 const struct device_node *np; 410 struct panel_desc *desc; 411 unsigned int bus_flags; 412 struct videomode vm; 413 int ret; 414 415 np = dev->of_node; 416 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 417 if (!desc) 418 return -ENOMEM; 419 420 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 421 if (!timing) 422 return -ENOMEM; 423 424 ret = of_get_display_timing(np, "panel-timing", timing); 425 if (ret < 0) { 426 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 427 np); 428 return ret; 429 } 430 431 desc->timings = timing; 432 desc->num_timings = 1; 433 434 of_property_read_u32(np, "width-mm", &desc->size.width); 435 of_property_read_u32(np, "height-mm", &desc->size.height); 436 437 /* Extract bus_flags from display_timing */ 438 bus_flags = 0; 439 vm.flags = timing->flags; 440 drm_bus_flags_from_videomode(&vm, &bus_flags); 441 desc->bus_flags = bus_flags; 442 443 /* We do not know the connector for the DT node, so guess it */ 444 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 445 446 panel->desc = desc; 447 448 return 0; 449 } 450 451 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 452 (to_check->field.typ >= bounds->field.min && \ 453 to_check->field.typ <= bounds->field.max) 454 static void panel_simple_parse_panel_timing_node(struct device *dev, 455 struct panel_simple *panel, 456 const struct display_timing *ot) 457 { 458 const struct panel_desc *desc = panel->desc; 459 struct videomode vm; 460 unsigned int i; 461 462 if (WARN_ON(desc->num_modes)) { 463 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 464 return; 465 } 466 if (WARN_ON(!desc->num_timings)) { 467 dev_err(dev, "Reject override mode: no timings specified\n"); 468 return; 469 } 470 471 for (i = 0; i < panel->desc->num_timings; i++) { 472 const struct display_timing *dt = &panel->desc->timings[i]; 473 474 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 475 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 476 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 477 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 478 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 479 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 480 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 481 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 482 continue; 483 484 if (ot->flags != dt->flags) 485 continue; 486 487 videomode_from_timing(ot, &vm); 488 drm_display_mode_from_videomode(&vm, &panel->override_mode); 489 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 490 DRM_MODE_TYPE_PREFERRED; 491 break; 492 } 493 494 if (WARN_ON(!panel->override_mode.type)) 495 dev_err(dev, "Reject override mode: No display_timing found\n"); 496 } 497 498 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 499 { 500 struct panel_simple *panel; 501 struct display_timing dt; 502 struct device_node *ddc; 503 int err; 504 505 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 506 if (!panel) 507 return -ENOMEM; 508 509 panel->enabled = false; 510 panel->prepared = false; 511 panel->desc = desc; 512 513 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 514 if (!panel->no_hpd) { 515 err = panel_simple_get_hpd_gpio(dev, panel, true); 516 if (err) 517 return err; 518 } 519 520 panel->supply = devm_regulator_get(dev, "power"); 521 if (IS_ERR(panel->supply)) 522 return PTR_ERR(panel->supply); 523 524 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 525 GPIOD_OUT_LOW); 526 if (IS_ERR(panel->enable_gpio)) { 527 err = PTR_ERR(panel->enable_gpio); 528 if (err != -EPROBE_DEFER) 529 dev_err(dev, "failed to request GPIO: %d\n", err); 530 return err; 531 } 532 533 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 534 if (ddc) { 535 panel->ddc = of_find_i2c_adapter_by_node(ddc); 536 of_node_put(ddc); 537 538 if (!panel->ddc) 539 return -EPROBE_DEFER; 540 } 541 542 if (desc == &panel_dpi) { 543 /* Handle the generic panel-dpi binding */ 544 err = panel_dpi_probe(dev, panel); 545 if (err) 546 goto free_ddc; 547 } else { 548 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 549 panel_simple_parse_panel_timing_node(dev, panel, &dt); 550 } 551 552 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 553 /* Catch common mistakes for LVDS panels. */ 554 WARN_ON(desc->bus_flags & 555 ~(DRM_BUS_FLAG_DE_LOW | 556 DRM_BUS_FLAG_DE_HIGH | 557 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 558 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 559 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 560 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 561 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 562 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 563 desc->bpc != 6); 564 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 565 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 566 desc->bpc != 8); 567 } 568 569 drm_panel_init(&panel->base, dev, &panel_simple_funcs, 570 desc->connector_type); 571 572 err = drm_panel_of_backlight(&panel->base); 573 if (err) 574 goto free_ddc; 575 576 err = drm_panel_add(&panel->base); 577 if (err < 0) 578 goto free_ddc; 579 580 dev_set_drvdata(dev, panel); 581 582 return 0; 583 584 free_ddc: 585 if (panel->ddc) 586 put_device(&panel->ddc->dev); 587 588 return err; 589 } 590 591 static int panel_simple_remove(struct device *dev) 592 { 593 struct panel_simple *panel = dev_get_drvdata(dev); 594 595 drm_panel_remove(&panel->base); 596 drm_panel_disable(&panel->base); 597 drm_panel_unprepare(&panel->base); 598 599 if (panel->ddc) 600 put_device(&panel->ddc->dev); 601 602 return 0; 603 } 604 605 static void panel_simple_shutdown(struct device *dev) 606 { 607 struct panel_simple *panel = dev_get_drvdata(dev); 608 609 drm_panel_disable(&panel->base); 610 drm_panel_unprepare(&panel->base); 611 } 612 613 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 614 .clock = 9000, 615 .hdisplay = 480, 616 .hsync_start = 480 + 2, 617 .hsync_end = 480 + 2 + 41, 618 .htotal = 480 + 2 + 41 + 2, 619 .vdisplay = 272, 620 .vsync_start = 272 + 2, 621 .vsync_end = 272 + 2 + 10, 622 .vtotal = 272 + 2 + 10 + 2, 623 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 624 }; 625 626 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 627 .modes = &ire_am_480272h3tmqw_t01h_mode, 628 .num_modes = 1, 629 .bpc = 8, 630 .size = { 631 .width = 105, 632 .height = 67, 633 }, 634 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 635 }; 636 637 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 638 .clock = 33333, 639 .hdisplay = 800, 640 .hsync_start = 800 + 0, 641 .hsync_end = 800 + 0 + 255, 642 .htotal = 800 + 0 + 255 + 0, 643 .vdisplay = 480, 644 .vsync_start = 480 + 2, 645 .vsync_end = 480 + 2 + 45, 646 .vtotal = 480 + 2 + 45 + 0, 647 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 648 }; 649 650 static const struct panel_desc ampire_am800480r3tmqwa1h = { 651 .modes = &ire_am800480r3tmqwa1h_mode, 652 .num_modes = 1, 653 .bpc = 6, 654 .size = { 655 .width = 152, 656 .height = 91, 657 }, 658 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 659 }; 660 661 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 662 .pixelclock = { 26400000, 33300000, 46800000 }, 663 .hactive = { 800, 800, 800 }, 664 .hfront_porch = { 16, 210, 354 }, 665 .hback_porch = { 45, 36, 6 }, 666 .hsync_len = { 1, 10, 40 }, 667 .vactive = { 480, 480, 480 }, 668 .vfront_porch = { 7, 22, 147 }, 669 .vback_porch = { 22, 13, 3 }, 670 .vsync_len = { 1, 10, 20 }, 671 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 672 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 673 }; 674 675 static const struct panel_desc armadeus_st0700_adapt = { 676 .timings = &santek_st0700i5y_rbslw_f_timing, 677 .num_timings = 1, 678 .bpc = 6, 679 .size = { 680 .width = 154, 681 .height = 86, 682 }, 683 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 684 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 685 }; 686 687 static const struct drm_display_mode auo_b101aw03_mode = { 688 .clock = 51450, 689 .hdisplay = 1024, 690 .hsync_start = 1024 + 156, 691 .hsync_end = 1024 + 156 + 8, 692 .htotal = 1024 + 156 + 8 + 156, 693 .vdisplay = 600, 694 .vsync_start = 600 + 16, 695 .vsync_end = 600 + 16 + 6, 696 .vtotal = 600 + 16 + 6 + 16, 697 }; 698 699 static const struct panel_desc auo_b101aw03 = { 700 .modes = &auo_b101aw03_mode, 701 .num_modes = 1, 702 .bpc = 6, 703 .size = { 704 .width = 223, 705 .height = 125, 706 }, 707 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 708 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 709 .connector_type = DRM_MODE_CONNECTOR_LVDS, 710 }; 711 712 static const struct display_timing auo_b101ean01_timing = { 713 .pixelclock = { 65300000, 72500000, 75000000 }, 714 .hactive = { 1280, 1280, 1280 }, 715 .hfront_porch = { 18, 119, 119 }, 716 .hback_porch = { 21, 21, 21 }, 717 .hsync_len = { 32, 32, 32 }, 718 .vactive = { 800, 800, 800 }, 719 .vfront_porch = { 4, 4, 4 }, 720 .vback_porch = { 8, 8, 8 }, 721 .vsync_len = { 18, 20, 20 }, 722 }; 723 724 static const struct panel_desc auo_b101ean01 = { 725 .timings = &auo_b101ean01_timing, 726 .num_timings = 1, 727 .bpc = 6, 728 .size = { 729 .width = 217, 730 .height = 136, 731 }, 732 }; 733 734 static const struct drm_display_mode auo_b101xtn01_mode = { 735 .clock = 72000, 736 .hdisplay = 1366, 737 .hsync_start = 1366 + 20, 738 .hsync_end = 1366 + 20 + 70, 739 .htotal = 1366 + 20 + 70, 740 .vdisplay = 768, 741 .vsync_start = 768 + 14, 742 .vsync_end = 768 + 14 + 42, 743 .vtotal = 768 + 14 + 42, 744 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 745 }; 746 747 static const struct panel_desc auo_b101xtn01 = { 748 .modes = &auo_b101xtn01_mode, 749 .num_modes = 1, 750 .bpc = 6, 751 .size = { 752 .width = 223, 753 .height = 125, 754 }, 755 }; 756 757 static const struct drm_display_mode auo_b116xak01_mode = { 758 .clock = 69300, 759 .hdisplay = 1366, 760 .hsync_start = 1366 + 48, 761 .hsync_end = 1366 + 48 + 32, 762 .htotal = 1366 + 48 + 32 + 10, 763 .vdisplay = 768, 764 .vsync_start = 768 + 4, 765 .vsync_end = 768 + 4 + 6, 766 .vtotal = 768 + 4 + 6 + 15, 767 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 768 }; 769 770 static const struct panel_desc auo_b116xak01 = { 771 .modes = &auo_b116xak01_mode, 772 .num_modes = 1, 773 .bpc = 6, 774 .size = { 775 .width = 256, 776 .height = 144, 777 }, 778 .delay = { 779 .hpd_absent_delay = 200, 780 }, 781 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 782 .connector_type = DRM_MODE_CONNECTOR_eDP, 783 }; 784 785 static const struct drm_display_mode auo_b116xw03_mode = { 786 .clock = 70589, 787 .hdisplay = 1366, 788 .hsync_start = 1366 + 40, 789 .hsync_end = 1366 + 40 + 40, 790 .htotal = 1366 + 40 + 40 + 32, 791 .vdisplay = 768, 792 .vsync_start = 768 + 10, 793 .vsync_end = 768 + 10 + 12, 794 .vtotal = 768 + 10 + 12 + 6, 795 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 796 }; 797 798 static const struct panel_desc auo_b116xw03 = { 799 .modes = &auo_b116xw03_mode, 800 .num_modes = 1, 801 .bpc = 6, 802 .size = { 803 .width = 256, 804 .height = 144, 805 }, 806 .delay = { 807 .enable = 400, 808 }, 809 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 810 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 811 .connector_type = DRM_MODE_CONNECTOR_eDP, 812 }; 813 814 static const struct drm_display_mode auo_b133xtn01_mode = { 815 .clock = 69500, 816 .hdisplay = 1366, 817 .hsync_start = 1366 + 48, 818 .hsync_end = 1366 + 48 + 32, 819 .htotal = 1366 + 48 + 32 + 20, 820 .vdisplay = 768, 821 .vsync_start = 768 + 3, 822 .vsync_end = 768 + 3 + 6, 823 .vtotal = 768 + 3 + 6 + 13, 824 }; 825 826 static const struct panel_desc auo_b133xtn01 = { 827 .modes = &auo_b133xtn01_mode, 828 .num_modes = 1, 829 .bpc = 6, 830 .size = { 831 .width = 293, 832 .height = 165, 833 }, 834 }; 835 836 static const struct drm_display_mode auo_b133htn01_mode = { 837 .clock = 150660, 838 .hdisplay = 1920, 839 .hsync_start = 1920 + 172, 840 .hsync_end = 1920 + 172 + 80, 841 .htotal = 1920 + 172 + 80 + 60, 842 .vdisplay = 1080, 843 .vsync_start = 1080 + 25, 844 .vsync_end = 1080 + 25 + 10, 845 .vtotal = 1080 + 25 + 10 + 10, 846 }; 847 848 static const struct panel_desc auo_b133htn01 = { 849 .modes = &auo_b133htn01_mode, 850 .num_modes = 1, 851 .bpc = 6, 852 .size = { 853 .width = 293, 854 .height = 165, 855 }, 856 .delay = { 857 .prepare = 105, 858 .enable = 20, 859 .unprepare = 50, 860 }, 861 }; 862 863 static const struct display_timing auo_g070vvn01_timings = { 864 .pixelclock = { 33300000, 34209000, 45000000 }, 865 .hactive = { 800, 800, 800 }, 866 .hfront_porch = { 20, 40, 200 }, 867 .hback_porch = { 87, 40, 1 }, 868 .hsync_len = { 1, 48, 87 }, 869 .vactive = { 480, 480, 480 }, 870 .vfront_porch = { 5, 13, 200 }, 871 .vback_porch = { 31, 31, 29 }, 872 .vsync_len = { 1, 1, 3 }, 873 }; 874 875 static const struct panel_desc auo_g070vvn01 = { 876 .timings = &auo_g070vvn01_timings, 877 .num_timings = 1, 878 .bpc = 8, 879 .size = { 880 .width = 152, 881 .height = 91, 882 }, 883 .delay = { 884 .prepare = 200, 885 .enable = 50, 886 .disable = 50, 887 .unprepare = 1000, 888 }, 889 }; 890 891 static const struct drm_display_mode auo_g101evn010_mode = { 892 .clock = 68930, 893 .hdisplay = 1280, 894 .hsync_start = 1280 + 82, 895 .hsync_end = 1280 + 82 + 2, 896 .htotal = 1280 + 82 + 2 + 84, 897 .vdisplay = 800, 898 .vsync_start = 800 + 8, 899 .vsync_end = 800 + 8 + 2, 900 .vtotal = 800 + 8 + 2 + 6, 901 }; 902 903 static const struct panel_desc auo_g101evn010 = { 904 .modes = &auo_g101evn010_mode, 905 .num_modes = 1, 906 .bpc = 6, 907 .size = { 908 .width = 216, 909 .height = 135, 910 }, 911 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 912 .connector_type = DRM_MODE_CONNECTOR_LVDS, 913 }; 914 915 static const struct drm_display_mode auo_g104sn02_mode = { 916 .clock = 40000, 917 .hdisplay = 800, 918 .hsync_start = 800 + 40, 919 .hsync_end = 800 + 40 + 216, 920 .htotal = 800 + 40 + 216 + 128, 921 .vdisplay = 600, 922 .vsync_start = 600 + 10, 923 .vsync_end = 600 + 10 + 35, 924 .vtotal = 600 + 10 + 35 + 2, 925 }; 926 927 static const struct panel_desc auo_g104sn02 = { 928 .modes = &auo_g104sn02_mode, 929 .num_modes = 1, 930 .bpc = 8, 931 .size = { 932 .width = 211, 933 .height = 158, 934 }, 935 }; 936 937 static const struct drm_display_mode auo_g121ean01_mode = { 938 .clock = 66700, 939 .hdisplay = 1280, 940 .hsync_start = 1280 + 58, 941 .hsync_end = 1280 + 58 + 8, 942 .htotal = 1280 + 58 + 8 + 70, 943 .vdisplay = 800, 944 .vsync_start = 800 + 6, 945 .vsync_end = 800 + 6 + 4, 946 .vtotal = 800 + 6 + 4 + 10, 947 }; 948 949 static const struct panel_desc auo_g121ean01 = { 950 .modes = &auo_g121ean01_mode, 951 .num_modes = 1, 952 .bpc = 8, 953 .size = { 954 .width = 261, 955 .height = 163, 956 }, 957 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 958 .connector_type = DRM_MODE_CONNECTOR_LVDS, 959 }; 960 961 static const struct display_timing auo_g133han01_timings = { 962 .pixelclock = { 134000000, 141200000, 149000000 }, 963 .hactive = { 1920, 1920, 1920 }, 964 .hfront_porch = { 39, 58, 77 }, 965 .hback_porch = { 59, 88, 117 }, 966 .hsync_len = { 28, 42, 56 }, 967 .vactive = { 1080, 1080, 1080 }, 968 .vfront_porch = { 3, 8, 11 }, 969 .vback_porch = { 5, 14, 19 }, 970 .vsync_len = { 4, 14, 19 }, 971 }; 972 973 static const struct panel_desc auo_g133han01 = { 974 .timings = &auo_g133han01_timings, 975 .num_timings = 1, 976 .bpc = 8, 977 .size = { 978 .width = 293, 979 .height = 165, 980 }, 981 .delay = { 982 .prepare = 200, 983 .enable = 50, 984 .disable = 50, 985 .unprepare = 1000, 986 }, 987 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 988 .connector_type = DRM_MODE_CONNECTOR_LVDS, 989 }; 990 991 static const struct drm_display_mode auo_g156xtn01_mode = { 992 .clock = 76000, 993 .hdisplay = 1366, 994 .hsync_start = 1366 + 33, 995 .hsync_end = 1366 + 33 + 67, 996 .htotal = 1560, 997 .vdisplay = 768, 998 .vsync_start = 768 + 4, 999 .vsync_end = 768 + 4 + 4, 1000 .vtotal = 806, 1001 }; 1002 1003 static const struct panel_desc auo_g156xtn01 = { 1004 .modes = &auo_g156xtn01_mode, 1005 .num_modes = 1, 1006 .bpc = 8, 1007 .size = { 1008 .width = 344, 1009 .height = 194, 1010 }, 1011 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1012 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1013 }; 1014 1015 static const struct display_timing auo_g185han01_timings = { 1016 .pixelclock = { 120000000, 144000000, 175000000 }, 1017 .hactive = { 1920, 1920, 1920 }, 1018 .hfront_porch = { 36, 120, 148 }, 1019 .hback_porch = { 24, 88, 108 }, 1020 .hsync_len = { 20, 48, 64 }, 1021 .vactive = { 1080, 1080, 1080 }, 1022 .vfront_porch = { 6, 10, 40 }, 1023 .vback_porch = { 2, 5, 20 }, 1024 .vsync_len = { 2, 5, 20 }, 1025 }; 1026 1027 static const struct panel_desc auo_g185han01 = { 1028 .timings = &auo_g185han01_timings, 1029 .num_timings = 1, 1030 .bpc = 8, 1031 .size = { 1032 .width = 409, 1033 .height = 230, 1034 }, 1035 .delay = { 1036 .prepare = 50, 1037 .enable = 200, 1038 .disable = 110, 1039 .unprepare = 1000, 1040 }, 1041 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1042 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1043 }; 1044 1045 static const struct display_timing auo_g190ean01_timings = { 1046 .pixelclock = { 90000000, 108000000, 135000000 }, 1047 .hactive = { 1280, 1280, 1280 }, 1048 .hfront_porch = { 126, 184, 1266 }, 1049 .hback_porch = { 84, 122, 844 }, 1050 .hsync_len = { 70, 102, 704 }, 1051 .vactive = { 1024, 1024, 1024 }, 1052 .vfront_porch = { 4, 26, 76 }, 1053 .vback_porch = { 2, 8, 25 }, 1054 .vsync_len = { 2, 8, 25 }, 1055 }; 1056 1057 static const struct panel_desc auo_g190ean01 = { 1058 .timings = &auo_g190ean01_timings, 1059 .num_timings = 1, 1060 .bpc = 8, 1061 .size = { 1062 .width = 376, 1063 .height = 301, 1064 }, 1065 .delay = { 1066 .prepare = 50, 1067 .enable = 200, 1068 .disable = 110, 1069 .unprepare = 1000, 1070 }, 1071 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1072 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1073 }; 1074 1075 static const struct display_timing auo_p320hvn03_timings = { 1076 .pixelclock = { 106000000, 148500000, 164000000 }, 1077 .hactive = { 1920, 1920, 1920 }, 1078 .hfront_porch = { 25, 50, 130 }, 1079 .hback_porch = { 25, 50, 130 }, 1080 .hsync_len = { 20, 40, 105 }, 1081 .vactive = { 1080, 1080, 1080 }, 1082 .vfront_porch = { 8, 17, 150 }, 1083 .vback_porch = { 8, 17, 150 }, 1084 .vsync_len = { 4, 11, 100 }, 1085 }; 1086 1087 static const struct panel_desc auo_p320hvn03 = { 1088 .timings = &auo_p320hvn03_timings, 1089 .num_timings = 1, 1090 .bpc = 8, 1091 .size = { 1092 .width = 698, 1093 .height = 393, 1094 }, 1095 .delay = { 1096 .prepare = 1, 1097 .enable = 450, 1098 .unprepare = 500, 1099 }, 1100 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1101 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1102 }; 1103 1104 static const struct drm_display_mode auo_t215hvn01_mode = { 1105 .clock = 148800, 1106 .hdisplay = 1920, 1107 .hsync_start = 1920 + 88, 1108 .hsync_end = 1920 + 88 + 44, 1109 .htotal = 1920 + 88 + 44 + 148, 1110 .vdisplay = 1080, 1111 .vsync_start = 1080 + 4, 1112 .vsync_end = 1080 + 4 + 5, 1113 .vtotal = 1080 + 4 + 5 + 36, 1114 }; 1115 1116 static const struct panel_desc auo_t215hvn01 = { 1117 .modes = &auo_t215hvn01_mode, 1118 .num_modes = 1, 1119 .bpc = 8, 1120 .size = { 1121 .width = 430, 1122 .height = 270, 1123 }, 1124 .delay = { 1125 .disable = 5, 1126 .unprepare = 1000, 1127 } 1128 }; 1129 1130 static const struct drm_display_mode avic_tm070ddh03_mode = { 1131 .clock = 51200, 1132 .hdisplay = 1024, 1133 .hsync_start = 1024 + 160, 1134 .hsync_end = 1024 + 160 + 4, 1135 .htotal = 1024 + 160 + 4 + 156, 1136 .vdisplay = 600, 1137 .vsync_start = 600 + 17, 1138 .vsync_end = 600 + 17 + 1, 1139 .vtotal = 600 + 17 + 1 + 17, 1140 }; 1141 1142 static const struct panel_desc avic_tm070ddh03 = { 1143 .modes = &avic_tm070ddh03_mode, 1144 .num_modes = 1, 1145 .bpc = 8, 1146 .size = { 1147 .width = 154, 1148 .height = 90, 1149 }, 1150 .delay = { 1151 .prepare = 20, 1152 .enable = 200, 1153 .disable = 200, 1154 }, 1155 }; 1156 1157 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1158 .clock = 30000, 1159 .hdisplay = 800, 1160 .hsync_start = 800 + 40, 1161 .hsync_end = 800 + 40 + 48, 1162 .htotal = 800 + 40 + 48 + 40, 1163 .vdisplay = 480, 1164 .vsync_start = 480 + 13, 1165 .vsync_end = 480 + 13 + 3, 1166 .vtotal = 480 + 13 + 3 + 29, 1167 }; 1168 1169 static const struct panel_desc bananapi_s070wv20_ct16 = { 1170 .modes = &bananapi_s070wv20_ct16_mode, 1171 .num_modes = 1, 1172 .bpc = 6, 1173 .size = { 1174 .width = 154, 1175 .height = 86, 1176 }, 1177 }; 1178 1179 static const struct drm_display_mode boe_hv070wsa_mode = { 1180 .clock = 42105, 1181 .hdisplay = 1024, 1182 .hsync_start = 1024 + 30, 1183 .hsync_end = 1024 + 30 + 30, 1184 .htotal = 1024 + 30 + 30 + 30, 1185 .vdisplay = 600, 1186 .vsync_start = 600 + 10, 1187 .vsync_end = 600 + 10 + 10, 1188 .vtotal = 600 + 10 + 10 + 10, 1189 }; 1190 1191 static const struct panel_desc boe_hv070wsa = { 1192 .modes = &boe_hv070wsa_mode, 1193 .num_modes = 1, 1194 .size = { 1195 .width = 154, 1196 .height = 90, 1197 }, 1198 }; 1199 1200 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1201 { 1202 .clock = 71900, 1203 .hdisplay = 1280, 1204 .hsync_start = 1280 + 48, 1205 .hsync_end = 1280 + 48 + 32, 1206 .htotal = 1280 + 48 + 32 + 80, 1207 .vdisplay = 800, 1208 .vsync_start = 800 + 3, 1209 .vsync_end = 800 + 3 + 5, 1210 .vtotal = 800 + 3 + 5 + 24, 1211 }, 1212 { 1213 .clock = 57500, 1214 .hdisplay = 1280, 1215 .hsync_start = 1280 + 48, 1216 .hsync_end = 1280 + 48 + 32, 1217 .htotal = 1280 + 48 + 32 + 80, 1218 .vdisplay = 800, 1219 .vsync_start = 800 + 3, 1220 .vsync_end = 800 + 3 + 5, 1221 .vtotal = 800 + 3 + 5 + 24, 1222 }, 1223 }; 1224 1225 static const struct panel_desc boe_nv101wxmn51 = { 1226 .modes = boe_nv101wxmn51_modes, 1227 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1228 .bpc = 8, 1229 .size = { 1230 .width = 217, 1231 .height = 136, 1232 }, 1233 .delay = { 1234 .prepare = 210, 1235 .enable = 50, 1236 .unprepare = 160, 1237 }, 1238 }; 1239 1240 /* Also used for boe_nv133fhm_n62 */ 1241 static const struct drm_display_mode boe_nv133fhm_n61_modes = { 1242 .clock = 147840, 1243 .hdisplay = 1920, 1244 .hsync_start = 1920 + 48, 1245 .hsync_end = 1920 + 48 + 32, 1246 .htotal = 1920 + 48 + 32 + 200, 1247 .vdisplay = 1080, 1248 .vsync_start = 1080 + 3, 1249 .vsync_end = 1080 + 3 + 6, 1250 .vtotal = 1080 + 3 + 6 + 31, 1251 }; 1252 1253 /* Also used for boe_nv133fhm_n62 */ 1254 static const struct panel_desc boe_nv133fhm_n61 = { 1255 .modes = &boe_nv133fhm_n61_modes, 1256 .num_modes = 1, 1257 .bpc = 6, 1258 .size = { 1259 .width = 294, 1260 .height = 165, 1261 }, 1262 .delay = { 1263 .hpd_absent_delay = 200, 1264 .unprepare = 500, 1265 }, 1266 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1267 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1268 .connector_type = DRM_MODE_CONNECTOR_eDP, 1269 }; 1270 1271 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1272 { 1273 .clock = 148500, 1274 .hdisplay = 1920, 1275 .hsync_start = 1920 + 48, 1276 .hsync_end = 1920 + 48 + 32, 1277 .htotal = 2200, 1278 .vdisplay = 1080, 1279 .vsync_start = 1080 + 3, 1280 .vsync_end = 1080 + 3 + 5, 1281 .vtotal = 1125, 1282 }, 1283 }; 1284 1285 static const struct panel_desc boe_nv140fhmn49 = { 1286 .modes = boe_nv140fhmn49_modes, 1287 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1288 .bpc = 6, 1289 .size = { 1290 .width = 309, 1291 .height = 174, 1292 }, 1293 .delay = { 1294 .prepare = 210, 1295 .enable = 50, 1296 .unprepare = 160, 1297 }, 1298 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1299 .connector_type = DRM_MODE_CONNECTOR_eDP, 1300 }; 1301 1302 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1303 .clock = 9000, 1304 .hdisplay = 480, 1305 .hsync_start = 480 + 5, 1306 .hsync_end = 480 + 5 + 5, 1307 .htotal = 480 + 5 + 5 + 40, 1308 .vdisplay = 272, 1309 .vsync_start = 272 + 8, 1310 .vsync_end = 272 + 8 + 8, 1311 .vtotal = 272 + 8 + 8 + 8, 1312 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1313 }; 1314 1315 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1316 .modes = &cdtech_s043wq26h_ct7_mode, 1317 .num_modes = 1, 1318 .bpc = 8, 1319 .size = { 1320 .width = 95, 1321 .height = 54, 1322 }, 1323 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1324 }; 1325 1326 /* S070PWS19HP-FC21 2017/04/22 */ 1327 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1328 .clock = 51200, 1329 .hdisplay = 1024, 1330 .hsync_start = 1024 + 160, 1331 .hsync_end = 1024 + 160 + 20, 1332 .htotal = 1024 + 160 + 20 + 140, 1333 .vdisplay = 600, 1334 .vsync_start = 600 + 12, 1335 .vsync_end = 600 + 12 + 3, 1336 .vtotal = 600 + 12 + 3 + 20, 1337 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1338 }; 1339 1340 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1341 .modes = &cdtech_s070pws19hp_fc21_mode, 1342 .num_modes = 1, 1343 .bpc = 6, 1344 .size = { 1345 .width = 154, 1346 .height = 86, 1347 }, 1348 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1349 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1350 .connector_type = DRM_MODE_CONNECTOR_DPI, 1351 }; 1352 1353 /* S070SWV29HG-DC44 2017/09/21 */ 1354 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1355 .clock = 33300, 1356 .hdisplay = 800, 1357 .hsync_start = 800 + 210, 1358 .hsync_end = 800 + 210 + 2, 1359 .htotal = 800 + 210 + 2 + 44, 1360 .vdisplay = 480, 1361 .vsync_start = 480 + 22, 1362 .vsync_end = 480 + 22 + 2, 1363 .vtotal = 480 + 22 + 2 + 21, 1364 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1365 }; 1366 1367 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1368 .modes = &cdtech_s070swv29hg_dc44_mode, 1369 .num_modes = 1, 1370 .bpc = 6, 1371 .size = { 1372 .width = 154, 1373 .height = 86, 1374 }, 1375 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1376 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1377 .connector_type = DRM_MODE_CONNECTOR_DPI, 1378 }; 1379 1380 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1381 .clock = 35000, 1382 .hdisplay = 800, 1383 .hsync_start = 800 + 40, 1384 .hsync_end = 800 + 40 + 40, 1385 .htotal = 800 + 40 + 40 + 48, 1386 .vdisplay = 480, 1387 .vsync_start = 480 + 29, 1388 .vsync_end = 480 + 29 + 13, 1389 .vtotal = 480 + 29 + 13 + 3, 1390 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1391 }; 1392 1393 static const struct panel_desc cdtech_s070wv95_ct16 = { 1394 .modes = &cdtech_s070wv95_ct16_mode, 1395 .num_modes = 1, 1396 .bpc = 8, 1397 .size = { 1398 .width = 154, 1399 .height = 85, 1400 }, 1401 }; 1402 1403 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1404 .clock = 66770, 1405 .hdisplay = 800, 1406 .hsync_start = 800 + 49, 1407 .hsync_end = 800 + 49 + 33, 1408 .htotal = 800 + 49 + 33 + 17, 1409 .vdisplay = 1280, 1410 .vsync_start = 1280 + 1, 1411 .vsync_end = 1280 + 1 + 7, 1412 .vtotal = 1280 + 1 + 7 + 15, 1413 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1414 }; 1415 1416 static const struct panel_desc chunghwa_claa070wp03xg = { 1417 .modes = &chunghwa_claa070wp03xg_mode, 1418 .num_modes = 1, 1419 .bpc = 6, 1420 .size = { 1421 .width = 94, 1422 .height = 150, 1423 }, 1424 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1425 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1426 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1427 }; 1428 1429 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1430 .clock = 72070, 1431 .hdisplay = 1366, 1432 .hsync_start = 1366 + 58, 1433 .hsync_end = 1366 + 58 + 58, 1434 .htotal = 1366 + 58 + 58 + 58, 1435 .vdisplay = 768, 1436 .vsync_start = 768 + 4, 1437 .vsync_end = 768 + 4 + 4, 1438 .vtotal = 768 + 4 + 4 + 4, 1439 }; 1440 1441 static const struct panel_desc chunghwa_claa101wa01a = { 1442 .modes = &chunghwa_claa101wa01a_mode, 1443 .num_modes = 1, 1444 .bpc = 6, 1445 .size = { 1446 .width = 220, 1447 .height = 120, 1448 }, 1449 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1450 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1451 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1452 }; 1453 1454 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1455 .clock = 69300, 1456 .hdisplay = 1366, 1457 .hsync_start = 1366 + 48, 1458 .hsync_end = 1366 + 48 + 32, 1459 .htotal = 1366 + 48 + 32 + 20, 1460 .vdisplay = 768, 1461 .vsync_start = 768 + 16, 1462 .vsync_end = 768 + 16 + 8, 1463 .vtotal = 768 + 16 + 8 + 16, 1464 }; 1465 1466 static const struct panel_desc chunghwa_claa101wb01 = { 1467 .modes = &chunghwa_claa101wb01_mode, 1468 .num_modes = 1, 1469 .bpc = 6, 1470 .size = { 1471 .width = 223, 1472 .height = 125, 1473 }, 1474 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1475 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1476 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1477 }; 1478 1479 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1480 .clock = 33260, 1481 .hdisplay = 800, 1482 .hsync_start = 800 + 40, 1483 .hsync_end = 800 + 40 + 128, 1484 .htotal = 800 + 40 + 128 + 88, 1485 .vdisplay = 480, 1486 .vsync_start = 480 + 10, 1487 .vsync_end = 480 + 10 + 2, 1488 .vtotal = 480 + 10 + 2 + 33, 1489 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1490 }; 1491 1492 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1493 .modes = &dataimage_scf0700c48ggu18_mode, 1494 .num_modes = 1, 1495 .bpc = 8, 1496 .size = { 1497 .width = 152, 1498 .height = 91, 1499 }, 1500 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1501 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1502 }; 1503 1504 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1505 .pixelclock = { 45000000, 51200000, 57000000 }, 1506 .hactive = { 1024, 1024, 1024 }, 1507 .hfront_porch = { 100, 106, 113 }, 1508 .hback_porch = { 100, 106, 113 }, 1509 .hsync_len = { 100, 108, 114 }, 1510 .vactive = { 600, 600, 600 }, 1511 .vfront_porch = { 8, 11, 15 }, 1512 .vback_porch = { 8, 11, 15 }, 1513 .vsync_len = { 9, 13, 15 }, 1514 .flags = DISPLAY_FLAGS_DE_HIGH, 1515 }; 1516 1517 static const struct panel_desc dlc_dlc0700yzg_1 = { 1518 .timings = &dlc_dlc0700yzg_1_timing, 1519 .num_timings = 1, 1520 .bpc = 6, 1521 .size = { 1522 .width = 154, 1523 .height = 86, 1524 }, 1525 .delay = { 1526 .prepare = 30, 1527 .enable = 200, 1528 .disable = 200, 1529 }, 1530 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1531 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1532 }; 1533 1534 static const struct display_timing dlc_dlc1010gig_timing = { 1535 .pixelclock = { 68900000, 71100000, 73400000 }, 1536 .hactive = { 1280, 1280, 1280 }, 1537 .hfront_porch = { 43, 53, 63 }, 1538 .hback_porch = { 43, 53, 63 }, 1539 .hsync_len = { 44, 54, 64 }, 1540 .vactive = { 800, 800, 800 }, 1541 .vfront_porch = { 5, 8, 11 }, 1542 .vback_porch = { 5, 8, 11 }, 1543 .vsync_len = { 5, 7, 11 }, 1544 .flags = DISPLAY_FLAGS_DE_HIGH, 1545 }; 1546 1547 static const struct panel_desc dlc_dlc1010gig = { 1548 .timings = &dlc_dlc1010gig_timing, 1549 .num_timings = 1, 1550 .bpc = 8, 1551 .size = { 1552 .width = 216, 1553 .height = 135, 1554 }, 1555 .delay = { 1556 .prepare = 60, 1557 .enable = 150, 1558 .disable = 100, 1559 .unprepare = 60, 1560 }, 1561 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1562 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1563 }; 1564 1565 static const struct drm_display_mode edt_et035012dm6_mode = { 1566 .clock = 6500, 1567 .hdisplay = 320, 1568 .hsync_start = 320 + 20, 1569 .hsync_end = 320 + 20 + 30, 1570 .htotal = 320 + 20 + 68, 1571 .vdisplay = 240, 1572 .vsync_start = 240 + 4, 1573 .vsync_end = 240 + 4 + 4, 1574 .vtotal = 240 + 4 + 4 + 14, 1575 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1576 }; 1577 1578 static const struct panel_desc edt_et035012dm6 = { 1579 .modes = &edt_et035012dm6_mode, 1580 .num_modes = 1, 1581 .bpc = 8, 1582 .size = { 1583 .width = 70, 1584 .height = 52, 1585 }, 1586 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1587 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1588 }; 1589 1590 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1591 .clock = 10870, 1592 .hdisplay = 480, 1593 .hsync_start = 480 + 8, 1594 .hsync_end = 480 + 8 + 4, 1595 .htotal = 480 + 8 + 4 + 41, 1596 1597 /* 1598 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1599 * fb_align 1600 */ 1601 1602 .vdisplay = 288, 1603 .vsync_start = 288 + 2, 1604 .vsync_end = 288 + 2 + 4, 1605 .vtotal = 288 + 2 + 4 + 10, 1606 }; 1607 1608 static const struct panel_desc edt_etm043080dh6gp = { 1609 .modes = &edt_etm043080dh6gp_mode, 1610 .num_modes = 1, 1611 .bpc = 8, 1612 .size = { 1613 .width = 100, 1614 .height = 65, 1615 }, 1616 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1617 .connector_type = DRM_MODE_CONNECTOR_DPI, 1618 }; 1619 1620 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1621 .clock = 9000, 1622 .hdisplay = 480, 1623 .hsync_start = 480 + 2, 1624 .hsync_end = 480 + 2 + 41, 1625 .htotal = 480 + 2 + 41 + 2, 1626 .vdisplay = 272, 1627 .vsync_start = 272 + 2, 1628 .vsync_end = 272 + 2 + 10, 1629 .vtotal = 272 + 2 + 10 + 2, 1630 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1631 }; 1632 1633 static const struct panel_desc edt_etm0430g0dh6 = { 1634 .modes = &edt_etm0430g0dh6_mode, 1635 .num_modes = 1, 1636 .bpc = 6, 1637 .size = { 1638 .width = 95, 1639 .height = 54, 1640 }, 1641 }; 1642 1643 static const struct drm_display_mode edt_et057090dhu_mode = { 1644 .clock = 25175, 1645 .hdisplay = 640, 1646 .hsync_start = 640 + 16, 1647 .hsync_end = 640 + 16 + 30, 1648 .htotal = 640 + 16 + 30 + 114, 1649 .vdisplay = 480, 1650 .vsync_start = 480 + 10, 1651 .vsync_end = 480 + 10 + 3, 1652 .vtotal = 480 + 10 + 3 + 32, 1653 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1654 }; 1655 1656 static const struct panel_desc edt_et057090dhu = { 1657 .modes = &edt_et057090dhu_mode, 1658 .num_modes = 1, 1659 .bpc = 6, 1660 .size = { 1661 .width = 115, 1662 .height = 86, 1663 }, 1664 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1665 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1666 .connector_type = DRM_MODE_CONNECTOR_DPI, 1667 }; 1668 1669 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1670 .clock = 33260, 1671 .hdisplay = 800, 1672 .hsync_start = 800 + 40, 1673 .hsync_end = 800 + 40 + 128, 1674 .htotal = 800 + 40 + 128 + 88, 1675 .vdisplay = 480, 1676 .vsync_start = 480 + 10, 1677 .vsync_end = 480 + 10 + 2, 1678 .vtotal = 480 + 10 + 2 + 33, 1679 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1680 }; 1681 1682 static const struct panel_desc edt_etm0700g0dh6 = { 1683 .modes = &edt_etm0700g0dh6_mode, 1684 .num_modes = 1, 1685 .bpc = 6, 1686 .size = { 1687 .width = 152, 1688 .height = 91, 1689 }, 1690 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1691 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1692 }; 1693 1694 static const struct panel_desc edt_etm0700g0bdh6 = { 1695 .modes = &edt_etm0700g0dh6_mode, 1696 .num_modes = 1, 1697 .bpc = 6, 1698 .size = { 1699 .width = 152, 1700 .height = 91, 1701 }, 1702 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1703 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1704 }; 1705 1706 static const struct display_timing evervision_vgg804821_timing = { 1707 .pixelclock = { 27600000, 33300000, 50000000 }, 1708 .hactive = { 800, 800, 800 }, 1709 .hfront_porch = { 40, 66, 70 }, 1710 .hback_porch = { 40, 67, 70 }, 1711 .hsync_len = { 40, 67, 70 }, 1712 .vactive = { 480, 480, 480 }, 1713 .vfront_porch = { 6, 10, 10 }, 1714 .vback_porch = { 7, 11, 11 }, 1715 .vsync_len = { 7, 11, 11 }, 1716 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1717 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1718 DISPLAY_FLAGS_SYNC_NEGEDGE, 1719 }; 1720 1721 static const struct panel_desc evervision_vgg804821 = { 1722 .timings = &evervision_vgg804821_timing, 1723 .num_timings = 1, 1724 .bpc = 8, 1725 .size = { 1726 .width = 108, 1727 .height = 64, 1728 }, 1729 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1730 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1731 }; 1732 1733 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1734 .clock = 32260, 1735 .hdisplay = 800, 1736 .hsync_start = 800 + 168, 1737 .hsync_end = 800 + 168 + 64, 1738 .htotal = 800 + 168 + 64 + 88, 1739 .vdisplay = 480, 1740 .vsync_start = 480 + 37, 1741 .vsync_end = 480 + 37 + 2, 1742 .vtotal = 480 + 37 + 2 + 8, 1743 }; 1744 1745 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1746 .modes = &foxlink_fl500wvr00_a0t_mode, 1747 .num_modes = 1, 1748 .bpc = 8, 1749 .size = { 1750 .width = 108, 1751 .height = 65, 1752 }, 1753 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1754 }; 1755 1756 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1757 { /* 60 Hz */ 1758 .clock = 6000, 1759 .hdisplay = 320, 1760 .hsync_start = 320 + 44, 1761 .hsync_end = 320 + 44 + 16, 1762 .htotal = 320 + 44 + 16 + 20, 1763 .vdisplay = 240, 1764 .vsync_start = 240 + 2, 1765 .vsync_end = 240 + 2 + 6, 1766 .vtotal = 240 + 2 + 6 + 2, 1767 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1768 }, 1769 { /* 50 Hz */ 1770 .clock = 5400, 1771 .hdisplay = 320, 1772 .hsync_start = 320 + 56, 1773 .hsync_end = 320 + 56 + 16, 1774 .htotal = 320 + 56 + 16 + 40, 1775 .vdisplay = 240, 1776 .vsync_start = 240 + 2, 1777 .vsync_end = 240 + 2 + 6, 1778 .vtotal = 240 + 2 + 6 + 2, 1779 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1780 }, 1781 }; 1782 1783 static const struct panel_desc frida_frd350h54004 = { 1784 .modes = frida_frd350h54004_modes, 1785 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1786 .bpc = 8, 1787 .size = { 1788 .width = 77, 1789 .height = 64, 1790 }, 1791 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1792 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1793 .connector_type = DRM_MODE_CONNECTOR_DPI, 1794 }; 1795 1796 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1797 .clock = 67185, 1798 .hdisplay = 800, 1799 .hsync_start = 800 + 20, 1800 .hsync_end = 800 + 20 + 24, 1801 .htotal = 800 + 20 + 24 + 20, 1802 .vdisplay = 1280, 1803 .vsync_start = 1280 + 4, 1804 .vsync_end = 1280 + 4 + 8, 1805 .vtotal = 1280 + 4 + 8 + 4, 1806 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1807 }; 1808 1809 static const struct panel_desc friendlyarm_hd702e = { 1810 .modes = &friendlyarm_hd702e_mode, 1811 .num_modes = 1, 1812 .size = { 1813 .width = 94, 1814 .height = 151, 1815 }, 1816 }; 1817 1818 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1819 .clock = 9000, 1820 .hdisplay = 480, 1821 .hsync_start = 480 + 5, 1822 .hsync_end = 480 + 5 + 1, 1823 .htotal = 480 + 5 + 1 + 40, 1824 .vdisplay = 272, 1825 .vsync_start = 272 + 8, 1826 .vsync_end = 272 + 8 + 1, 1827 .vtotal = 272 + 8 + 1 + 8, 1828 }; 1829 1830 static const struct panel_desc giantplus_gpg482739qs5 = { 1831 .modes = &giantplus_gpg482739qs5_mode, 1832 .num_modes = 1, 1833 .bpc = 8, 1834 .size = { 1835 .width = 95, 1836 .height = 54, 1837 }, 1838 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1839 }; 1840 1841 static const struct display_timing giantplus_gpm940b0_timing = { 1842 .pixelclock = { 13500000, 27000000, 27500000 }, 1843 .hactive = { 320, 320, 320 }, 1844 .hfront_porch = { 14, 686, 718 }, 1845 .hback_porch = { 50, 70, 255 }, 1846 .hsync_len = { 1, 1, 1 }, 1847 .vactive = { 240, 240, 240 }, 1848 .vfront_porch = { 1, 1, 179 }, 1849 .vback_porch = { 1, 21, 31 }, 1850 .vsync_len = { 1, 1, 6 }, 1851 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1852 }; 1853 1854 static const struct panel_desc giantplus_gpm940b0 = { 1855 .timings = &giantplus_gpm940b0_timing, 1856 .num_timings = 1, 1857 .bpc = 8, 1858 .size = { 1859 .width = 60, 1860 .height = 45, 1861 }, 1862 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1863 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1864 }; 1865 1866 static const struct display_timing hannstar_hsd070pww1_timing = { 1867 .pixelclock = { 64300000, 71100000, 82000000 }, 1868 .hactive = { 1280, 1280, 1280 }, 1869 .hfront_porch = { 1, 1, 10 }, 1870 .hback_porch = { 1, 1, 10 }, 1871 /* 1872 * According to the data sheet, the minimum horizontal blanking interval 1873 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 1874 * minimum working horizontal blanking interval to be 60 clocks. 1875 */ 1876 .hsync_len = { 58, 158, 661 }, 1877 .vactive = { 800, 800, 800 }, 1878 .vfront_porch = { 1, 1, 10 }, 1879 .vback_porch = { 1, 1, 10 }, 1880 .vsync_len = { 1, 21, 203 }, 1881 .flags = DISPLAY_FLAGS_DE_HIGH, 1882 }; 1883 1884 static const struct panel_desc hannstar_hsd070pww1 = { 1885 .timings = &hannstar_hsd070pww1_timing, 1886 .num_timings = 1, 1887 .bpc = 6, 1888 .size = { 1889 .width = 151, 1890 .height = 94, 1891 }, 1892 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1893 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1894 }; 1895 1896 static const struct display_timing hannstar_hsd100pxn1_timing = { 1897 .pixelclock = { 55000000, 65000000, 75000000 }, 1898 .hactive = { 1024, 1024, 1024 }, 1899 .hfront_porch = { 40, 40, 40 }, 1900 .hback_porch = { 220, 220, 220 }, 1901 .hsync_len = { 20, 60, 100 }, 1902 .vactive = { 768, 768, 768 }, 1903 .vfront_porch = { 7, 7, 7 }, 1904 .vback_porch = { 21, 21, 21 }, 1905 .vsync_len = { 10, 10, 10 }, 1906 .flags = DISPLAY_FLAGS_DE_HIGH, 1907 }; 1908 1909 static const struct panel_desc hannstar_hsd100pxn1 = { 1910 .timings = &hannstar_hsd100pxn1_timing, 1911 .num_timings = 1, 1912 .bpc = 6, 1913 .size = { 1914 .width = 203, 1915 .height = 152, 1916 }, 1917 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1918 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1919 }; 1920 1921 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 1922 .clock = 33333, 1923 .hdisplay = 800, 1924 .hsync_start = 800 + 85, 1925 .hsync_end = 800 + 85 + 86, 1926 .htotal = 800 + 85 + 86 + 85, 1927 .vdisplay = 480, 1928 .vsync_start = 480 + 16, 1929 .vsync_end = 480 + 16 + 13, 1930 .vtotal = 480 + 16 + 13 + 16, 1931 }; 1932 1933 static const struct panel_desc hitachi_tx23d38vm0caa = { 1934 .modes = &hitachi_tx23d38vm0caa_mode, 1935 .num_modes = 1, 1936 .bpc = 6, 1937 .size = { 1938 .width = 195, 1939 .height = 117, 1940 }, 1941 .delay = { 1942 .enable = 160, 1943 .disable = 160, 1944 }, 1945 }; 1946 1947 static const struct drm_display_mode innolux_at043tn24_mode = { 1948 .clock = 9000, 1949 .hdisplay = 480, 1950 .hsync_start = 480 + 2, 1951 .hsync_end = 480 + 2 + 41, 1952 .htotal = 480 + 2 + 41 + 2, 1953 .vdisplay = 272, 1954 .vsync_start = 272 + 2, 1955 .vsync_end = 272 + 2 + 10, 1956 .vtotal = 272 + 2 + 10 + 2, 1957 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1958 }; 1959 1960 static const struct panel_desc innolux_at043tn24 = { 1961 .modes = &innolux_at043tn24_mode, 1962 .num_modes = 1, 1963 .bpc = 8, 1964 .size = { 1965 .width = 95, 1966 .height = 54, 1967 }, 1968 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1969 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1970 }; 1971 1972 static const struct drm_display_mode innolux_at070tn92_mode = { 1973 .clock = 33333, 1974 .hdisplay = 800, 1975 .hsync_start = 800 + 210, 1976 .hsync_end = 800 + 210 + 20, 1977 .htotal = 800 + 210 + 20 + 46, 1978 .vdisplay = 480, 1979 .vsync_start = 480 + 22, 1980 .vsync_end = 480 + 22 + 10, 1981 .vtotal = 480 + 22 + 23 + 10, 1982 }; 1983 1984 static const struct panel_desc innolux_at070tn92 = { 1985 .modes = &innolux_at070tn92_mode, 1986 .num_modes = 1, 1987 .size = { 1988 .width = 154, 1989 .height = 86, 1990 }, 1991 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1992 }; 1993 1994 static const struct display_timing innolux_g070y2_l01_timing = { 1995 .pixelclock = { 28000000, 29500000, 32000000 }, 1996 .hactive = { 800, 800, 800 }, 1997 .hfront_porch = { 61, 91, 141 }, 1998 .hback_porch = { 60, 90, 140 }, 1999 .hsync_len = { 12, 12, 12 }, 2000 .vactive = { 480, 480, 480 }, 2001 .vfront_porch = { 4, 9, 30 }, 2002 .vback_porch = { 4, 8, 28 }, 2003 .vsync_len = { 2, 2, 2 }, 2004 .flags = DISPLAY_FLAGS_DE_HIGH, 2005 }; 2006 2007 static const struct panel_desc innolux_g070y2_l01 = { 2008 .timings = &innolux_g070y2_l01_timing, 2009 .num_timings = 1, 2010 .bpc = 6, 2011 .size = { 2012 .width = 152, 2013 .height = 91, 2014 }, 2015 .delay = { 2016 .prepare = 10, 2017 .enable = 100, 2018 .disable = 100, 2019 .unprepare = 800, 2020 }, 2021 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2022 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2023 }; 2024 2025 static const struct display_timing innolux_g101ice_l01_timing = { 2026 .pixelclock = { 60400000, 71100000, 74700000 }, 2027 .hactive = { 1280, 1280, 1280 }, 2028 .hfront_porch = { 41, 80, 100 }, 2029 .hback_porch = { 40, 79, 99 }, 2030 .hsync_len = { 1, 1, 1 }, 2031 .vactive = { 800, 800, 800 }, 2032 .vfront_porch = { 5, 11, 14 }, 2033 .vback_porch = { 4, 11, 14 }, 2034 .vsync_len = { 1, 1, 1 }, 2035 .flags = DISPLAY_FLAGS_DE_HIGH, 2036 }; 2037 2038 static const struct panel_desc innolux_g101ice_l01 = { 2039 .timings = &innolux_g101ice_l01_timing, 2040 .num_timings = 1, 2041 .bpc = 8, 2042 .size = { 2043 .width = 217, 2044 .height = 135, 2045 }, 2046 .delay = { 2047 .enable = 200, 2048 .disable = 200, 2049 }, 2050 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2051 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2052 }; 2053 2054 static const struct display_timing innolux_g121i1_l01_timing = { 2055 .pixelclock = { 67450000, 71000000, 74550000 }, 2056 .hactive = { 1280, 1280, 1280 }, 2057 .hfront_porch = { 40, 80, 160 }, 2058 .hback_porch = { 39, 79, 159 }, 2059 .hsync_len = { 1, 1, 1 }, 2060 .vactive = { 800, 800, 800 }, 2061 .vfront_porch = { 5, 11, 100 }, 2062 .vback_porch = { 4, 11, 99 }, 2063 .vsync_len = { 1, 1, 1 }, 2064 }; 2065 2066 static const struct panel_desc innolux_g121i1_l01 = { 2067 .timings = &innolux_g121i1_l01_timing, 2068 .num_timings = 1, 2069 .bpc = 6, 2070 .size = { 2071 .width = 261, 2072 .height = 163, 2073 }, 2074 .delay = { 2075 .enable = 200, 2076 .disable = 20, 2077 }, 2078 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2079 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2080 }; 2081 2082 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2083 .clock = 65000, 2084 .hdisplay = 1024, 2085 .hsync_start = 1024 + 0, 2086 .hsync_end = 1024 + 1, 2087 .htotal = 1024 + 0 + 1 + 320, 2088 .vdisplay = 768, 2089 .vsync_start = 768 + 38, 2090 .vsync_end = 768 + 38 + 1, 2091 .vtotal = 768 + 38 + 1 + 0, 2092 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2093 }; 2094 2095 static const struct panel_desc innolux_g121x1_l03 = { 2096 .modes = &innolux_g121x1_l03_mode, 2097 .num_modes = 1, 2098 .bpc = 6, 2099 .size = { 2100 .width = 246, 2101 .height = 185, 2102 }, 2103 .delay = { 2104 .enable = 200, 2105 .unprepare = 200, 2106 .disable = 400, 2107 }, 2108 }; 2109 2110 /* 2111 * Datasheet specifies that at 60 Hz refresh rate: 2112 * - total horizontal time: { 1506, 1592, 1716 } 2113 * - total vertical time: { 788, 800, 868 } 2114 * 2115 * ...but doesn't go into exactly how that should be split into a front 2116 * porch, back porch, or sync length. For now we'll leave a single setting 2117 * here which allows a bit of tweaking of the pixel clock at the expense of 2118 * refresh rate. 2119 */ 2120 static const struct display_timing innolux_n116bge_timing = { 2121 .pixelclock = { 72600000, 76420000, 80240000 }, 2122 .hactive = { 1366, 1366, 1366 }, 2123 .hfront_porch = { 136, 136, 136 }, 2124 .hback_porch = { 60, 60, 60 }, 2125 .hsync_len = { 30, 30, 30 }, 2126 .vactive = { 768, 768, 768 }, 2127 .vfront_porch = { 8, 8, 8 }, 2128 .vback_porch = { 12, 12, 12 }, 2129 .vsync_len = { 12, 12, 12 }, 2130 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2131 }; 2132 2133 static const struct panel_desc innolux_n116bge = { 2134 .timings = &innolux_n116bge_timing, 2135 .num_timings = 1, 2136 .bpc = 6, 2137 .size = { 2138 .width = 256, 2139 .height = 144, 2140 }, 2141 }; 2142 2143 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2144 .clock = 69300, 2145 .hdisplay = 1366, 2146 .hsync_start = 1366 + 16, 2147 .hsync_end = 1366 + 16 + 34, 2148 .htotal = 1366 + 16 + 34 + 50, 2149 .vdisplay = 768, 2150 .vsync_start = 768 + 2, 2151 .vsync_end = 768 + 2 + 6, 2152 .vtotal = 768 + 2 + 6 + 12, 2153 }; 2154 2155 static const struct panel_desc innolux_n156bge_l21 = { 2156 .modes = &innolux_n156bge_l21_mode, 2157 .num_modes = 1, 2158 .bpc = 6, 2159 .size = { 2160 .width = 344, 2161 .height = 193, 2162 }, 2163 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2164 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2165 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2166 }; 2167 2168 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 2169 .clock = 206016, 2170 .hdisplay = 2160, 2171 .hsync_start = 2160 + 48, 2172 .hsync_end = 2160 + 48 + 32, 2173 .htotal = 2160 + 48 + 32 + 80, 2174 .vdisplay = 1440, 2175 .vsync_start = 1440 + 3, 2176 .vsync_end = 1440 + 3 + 10, 2177 .vtotal = 1440 + 3 + 10 + 27, 2178 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2179 }; 2180 2181 static const struct panel_desc innolux_p120zdg_bf1 = { 2182 .modes = &innolux_p120zdg_bf1_mode, 2183 .num_modes = 1, 2184 .bpc = 8, 2185 .size = { 2186 .width = 254, 2187 .height = 169, 2188 }, 2189 .delay = { 2190 .hpd_absent_delay = 200, 2191 .unprepare = 500, 2192 }, 2193 }; 2194 2195 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2196 .clock = 51501, 2197 .hdisplay = 1024, 2198 .hsync_start = 1024 + 128, 2199 .hsync_end = 1024 + 128 + 64, 2200 .htotal = 1024 + 128 + 64 + 128, 2201 .vdisplay = 600, 2202 .vsync_start = 600 + 16, 2203 .vsync_end = 600 + 16 + 4, 2204 .vtotal = 600 + 16 + 4 + 16, 2205 }; 2206 2207 static const struct panel_desc innolux_zj070na_01p = { 2208 .modes = &innolux_zj070na_01p_mode, 2209 .num_modes = 1, 2210 .bpc = 6, 2211 .size = { 2212 .width = 154, 2213 .height = 90, 2214 }, 2215 }; 2216 2217 static const struct drm_display_mode ivo_m133nwf4_r0_mode = { 2218 .clock = 138778, 2219 .hdisplay = 1920, 2220 .hsync_start = 1920 + 24, 2221 .hsync_end = 1920 + 24 + 48, 2222 .htotal = 1920 + 24 + 48 + 88, 2223 .vdisplay = 1080, 2224 .vsync_start = 1080 + 3, 2225 .vsync_end = 1080 + 3 + 12, 2226 .vtotal = 1080 + 3 + 12 + 17, 2227 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2228 }; 2229 2230 static const struct panel_desc ivo_m133nwf4_r0 = { 2231 .modes = &ivo_m133nwf4_r0_mode, 2232 .num_modes = 1, 2233 .bpc = 8, 2234 .size = { 2235 .width = 294, 2236 .height = 165, 2237 }, 2238 .delay = { 2239 .hpd_absent_delay = 200, 2240 .unprepare = 500, 2241 }, 2242 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2243 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2244 .connector_type = DRM_MODE_CONNECTOR_eDP, 2245 }; 2246 2247 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2248 .pixelclock = { 5580000, 5850000, 6200000 }, 2249 .hactive = { 320, 320, 320 }, 2250 .hfront_porch = { 30, 30, 30 }, 2251 .hback_porch = { 30, 30, 30 }, 2252 .hsync_len = { 1, 5, 17 }, 2253 .vactive = { 240, 240, 240 }, 2254 .vfront_porch = { 6, 6, 6 }, 2255 .vback_porch = { 5, 5, 5 }, 2256 .vsync_len = { 1, 2, 11 }, 2257 .flags = DISPLAY_FLAGS_DE_HIGH, 2258 }; 2259 2260 static const struct panel_desc koe_tx14d24vm1bpa = { 2261 .timings = &koe_tx14d24vm1bpa_timing, 2262 .num_timings = 1, 2263 .bpc = 6, 2264 .size = { 2265 .width = 115, 2266 .height = 86, 2267 }, 2268 }; 2269 2270 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2271 .pixelclock = { 151820000, 156720000, 159780000 }, 2272 .hactive = { 1920, 1920, 1920 }, 2273 .hfront_porch = { 105, 130, 142 }, 2274 .hback_porch = { 45, 70, 82 }, 2275 .hsync_len = { 30, 30, 30 }, 2276 .vactive = { 1200, 1200, 1200}, 2277 .vfront_porch = { 3, 5, 10 }, 2278 .vback_porch = { 2, 5, 10 }, 2279 .vsync_len = { 5, 5, 5 }, 2280 }; 2281 2282 static const struct panel_desc koe_tx26d202vm0bwa = { 2283 .timings = &koe_tx26d202vm0bwa_timing, 2284 .num_timings = 1, 2285 .bpc = 8, 2286 .size = { 2287 .width = 217, 2288 .height = 136, 2289 }, 2290 .delay = { 2291 .prepare = 1000, 2292 .enable = 1000, 2293 .unprepare = 1000, 2294 .disable = 1000, 2295 }, 2296 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2297 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2298 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2299 }; 2300 2301 static const struct display_timing koe_tx31d200vm0baa_timing = { 2302 .pixelclock = { 39600000, 43200000, 48000000 }, 2303 .hactive = { 1280, 1280, 1280 }, 2304 .hfront_porch = { 16, 36, 56 }, 2305 .hback_porch = { 16, 36, 56 }, 2306 .hsync_len = { 8, 8, 8 }, 2307 .vactive = { 480, 480, 480 }, 2308 .vfront_porch = { 6, 21, 33 }, 2309 .vback_porch = { 6, 21, 33 }, 2310 .vsync_len = { 8, 8, 8 }, 2311 .flags = DISPLAY_FLAGS_DE_HIGH, 2312 }; 2313 2314 static const struct panel_desc koe_tx31d200vm0baa = { 2315 .timings = &koe_tx31d200vm0baa_timing, 2316 .num_timings = 1, 2317 .bpc = 6, 2318 .size = { 2319 .width = 292, 2320 .height = 109, 2321 }, 2322 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2323 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2324 }; 2325 2326 static const struct display_timing kyo_tcg121xglp_timing = { 2327 .pixelclock = { 52000000, 65000000, 71000000 }, 2328 .hactive = { 1024, 1024, 1024 }, 2329 .hfront_porch = { 2, 2, 2 }, 2330 .hback_porch = { 2, 2, 2 }, 2331 .hsync_len = { 86, 124, 244 }, 2332 .vactive = { 768, 768, 768 }, 2333 .vfront_porch = { 2, 2, 2 }, 2334 .vback_porch = { 2, 2, 2 }, 2335 .vsync_len = { 6, 34, 73 }, 2336 .flags = DISPLAY_FLAGS_DE_HIGH, 2337 }; 2338 2339 static const struct panel_desc kyo_tcg121xglp = { 2340 .timings = &kyo_tcg121xglp_timing, 2341 .num_timings = 1, 2342 .bpc = 8, 2343 .size = { 2344 .width = 246, 2345 .height = 184, 2346 }, 2347 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2348 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2349 }; 2350 2351 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2352 .clock = 7000, 2353 .hdisplay = 320, 2354 .hsync_start = 320 + 20, 2355 .hsync_end = 320 + 20 + 30, 2356 .htotal = 320 + 20 + 30 + 38, 2357 .vdisplay = 240, 2358 .vsync_start = 240 + 4, 2359 .vsync_end = 240 + 4 + 3, 2360 .vtotal = 240 + 4 + 3 + 15, 2361 }; 2362 2363 static const struct panel_desc lemaker_bl035_rgb_002 = { 2364 .modes = &lemaker_bl035_rgb_002_mode, 2365 .num_modes = 1, 2366 .size = { 2367 .width = 70, 2368 .height = 52, 2369 }, 2370 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2371 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2372 }; 2373 2374 static const struct drm_display_mode lg_lb070wv8_mode = { 2375 .clock = 33246, 2376 .hdisplay = 800, 2377 .hsync_start = 800 + 88, 2378 .hsync_end = 800 + 88 + 80, 2379 .htotal = 800 + 88 + 80 + 88, 2380 .vdisplay = 480, 2381 .vsync_start = 480 + 10, 2382 .vsync_end = 480 + 10 + 25, 2383 .vtotal = 480 + 10 + 25 + 10, 2384 }; 2385 2386 static const struct panel_desc lg_lb070wv8 = { 2387 .modes = &lg_lb070wv8_mode, 2388 .num_modes = 1, 2389 .bpc = 8, 2390 .size = { 2391 .width = 151, 2392 .height = 91, 2393 }, 2394 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2395 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2396 }; 2397 2398 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2399 .clock = 200000, 2400 .hdisplay = 1536, 2401 .hsync_start = 1536 + 12, 2402 .hsync_end = 1536 + 12 + 16, 2403 .htotal = 1536 + 12 + 16 + 48, 2404 .vdisplay = 2048, 2405 .vsync_start = 2048 + 8, 2406 .vsync_end = 2048 + 8 + 4, 2407 .vtotal = 2048 + 8 + 4 + 8, 2408 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2409 }; 2410 2411 static const struct panel_desc lg_lp079qx1_sp0v = { 2412 .modes = &lg_lp079qx1_sp0v_mode, 2413 .num_modes = 1, 2414 .size = { 2415 .width = 129, 2416 .height = 171, 2417 }, 2418 }; 2419 2420 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2421 .clock = 205210, 2422 .hdisplay = 2048, 2423 .hsync_start = 2048 + 150, 2424 .hsync_end = 2048 + 150 + 5, 2425 .htotal = 2048 + 150 + 5 + 5, 2426 .vdisplay = 1536, 2427 .vsync_start = 1536 + 3, 2428 .vsync_end = 1536 + 3 + 1, 2429 .vtotal = 1536 + 3 + 1 + 9, 2430 }; 2431 2432 static const struct panel_desc lg_lp097qx1_spa1 = { 2433 .modes = &lg_lp097qx1_spa1_mode, 2434 .num_modes = 1, 2435 .size = { 2436 .width = 208, 2437 .height = 147, 2438 }, 2439 }; 2440 2441 static const struct drm_display_mode lg_lp120up1_mode = { 2442 .clock = 162300, 2443 .hdisplay = 1920, 2444 .hsync_start = 1920 + 40, 2445 .hsync_end = 1920 + 40 + 40, 2446 .htotal = 1920 + 40 + 40+ 80, 2447 .vdisplay = 1280, 2448 .vsync_start = 1280 + 4, 2449 .vsync_end = 1280 + 4 + 4, 2450 .vtotal = 1280 + 4 + 4 + 12, 2451 }; 2452 2453 static const struct panel_desc lg_lp120up1 = { 2454 .modes = &lg_lp120up1_mode, 2455 .num_modes = 1, 2456 .bpc = 8, 2457 .size = { 2458 .width = 267, 2459 .height = 183, 2460 }, 2461 .connector_type = DRM_MODE_CONNECTOR_eDP, 2462 }; 2463 2464 static const struct drm_display_mode lg_lp129qe_mode = { 2465 .clock = 285250, 2466 .hdisplay = 2560, 2467 .hsync_start = 2560 + 48, 2468 .hsync_end = 2560 + 48 + 32, 2469 .htotal = 2560 + 48 + 32 + 80, 2470 .vdisplay = 1700, 2471 .vsync_start = 1700 + 3, 2472 .vsync_end = 1700 + 3 + 10, 2473 .vtotal = 1700 + 3 + 10 + 36, 2474 }; 2475 2476 static const struct panel_desc lg_lp129qe = { 2477 .modes = &lg_lp129qe_mode, 2478 .num_modes = 1, 2479 .bpc = 8, 2480 .size = { 2481 .width = 272, 2482 .height = 181, 2483 }, 2484 }; 2485 2486 static const struct display_timing logictechno_lt161010_2nh_timing = { 2487 .pixelclock = { 26400000, 33300000, 46800000 }, 2488 .hactive = { 800, 800, 800 }, 2489 .hfront_porch = { 16, 210, 354 }, 2490 .hback_porch = { 46, 46, 46 }, 2491 .hsync_len = { 1, 20, 40 }, 2492 .vactive = { 480, 480, 480 }, 2493 .vfront_porch = { 7, 22, 147 }, 2494 .vback_porch = { 23, 23, 23 }, 2495 .vsync_len = { 1, 10, 20 }, 2496 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2497 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2498 DISPLAY_FLAGS_SYNC_POSEDGE, 2499 }; 2500 2501 static const struct panel_desc logictechno_lt161010_2nh = { 2502 .timings = &logictechno_lt161010_2nh_timing, 2503 .num_timings = 1, 2504 .size = { 2505 .width = 154, 2506 .height = 86, 2507 }, 2508 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2509 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2510 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2511 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2512 .connector_type = DRM_MODE_CONNECTOR_DPI, 2513 }; 2514 2515 static const struct display_timing logictechno_lt170410_2whc_timing = { 2516 .pixelclock = { 68900000, 71100000, 73400000 }, 2517 .hactive = { 1280, 1280, 1280 }, 2518 .hfront_porch = { 23, 60, 71 }, 2519 .hback_porch = { 23, 60, 71 }, 2520 .hsync_len = { 15, 40, 47 }, 2521 .vactive = { 800, 800, 800 }, 2522 .vfront_porch = { 5, 7, 10 }, 2523 .vback_porch = { 5, 7, 10 }, 2524 .vsync_len = { 6, 9, 12 }, 2525 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2526 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2527 DISPLAY_FLAGS_SYNC_POSEDGE, 2528 }; 2529 2530 static const struct panel_desc logictechno_lt170410_2whc = { 2531 .timings = &logictechno_lt170410_2whc_timing, 2532 .num_timings = 1, 2533 .size = { 2534 .width = 217, 2535 .height = 136, 2536 }, 2537 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2538 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2539 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2540 }; 2541 2542 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2543 .clock = 30400, 2544 .hdisplay = 800, 2545 .hsync_start = 800 + 0, 2546 .hsync_end = 800 + 1, 2547 .htotal = 800 + 0 + 1 + 160, 2548 .vdisplay = 480, 2549 .vsync_start = 480 + 0, 2550 .vsync_end = 480 + 48 + 1, 2551 .vtotal = 480 + 48 + 1 + 0, 2552 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2553 }; 2554 2555 static const struct drm_display_mode logicpd_type_28_mode = { 2556 .clock = 9107, 2557 .hdisplay = 480, 2558 .hsync_start = 480 + 3, 2559 .hsync_end = 480 + 3 + 42, 2560 .htotal = 480 + 3 + 42 + 2, 2561 2562 .vdisplay = 272, 2563 .vsync_start = 272 + 2, 2564 .vsync_end = 272 + 2 + 11, 2565 .vtotal = 272 + 2 + 11 + 3, 2566 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2567 }; 2568 2569 static const struct panel_desc logicpd_type_28 = { 2570 .modes = &logicpd_type_28_mode, 2571 .num_modes = 1, 2572 .bpc = 8, 2573 .size = { 2574 .width = 105, 2575 .height = 67, 2576 }, 2577 .delay = { 2578 .prepare = 200, 2579 .enable = 200, 2580 .unprepare = 200, 2581 .disable = 200, 2582 }, 2583 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2584 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2585 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2586 .connector_type = DRM_MODE_CONNECTOR_DPI, 2587 }; 2588 2589 static const struct panel_desc mitsubishi_aa070mc01 = { 2590 .modes = &mitsubishi_aa070mc01_mode, 2591 .num_modes = 1, 2592 .bpc = 8, 2593 .size = { 2594 .width = 152, 2595 .height = 91, 2596 }, 2597 2598 .delay = { 2599 .enable = 200, 2600 .unprepare = 200, 2601 .disable = 400, 2602 }, 2603 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2604 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2605 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2606 }; 2607 2608 static const struct display_timing nec_nl12880bc20_05_timing = { 2609 .pixelclock = { 67000000, 71000000, 75000000 }, 2610 .hactive = { 1280, 1280, 1280 }, 2611 .hfront_porch = { 2, 30, 30 }, 2612 .hback_porch = { 6, 100, 100 }, 2613 .hsync_len = { 2, 30, 30 }, 2614 .vactive = { 800, 800, 800 }, 2615 .vfront_porch = { 5, 5, 5 }, 2616 .vback_porch = { 11, 11, 11 }, 2617 .vsync_len = { 7, 7, 7 }, 2618 }; 2619 2620 static const struct panel_desc nec_nl12880bc20_05 = { 2621 .timings = &nec_nl12880bc20_05_timing, 2622 .num_timings = 1, 2623 .bpc = 8, 2624 .size = { 2625 .width = 261, 2626 .height = 163, 2627 }, 2628 .delay = { 2629 .enable = 50, 2630 .disable = 50, 2631 }, 2632 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2633 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2634 }; 2635 2636 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2637 .clock = 10870, 2638 .hdisplay = 480, 2639 .hsync_start = 480 + 2, 2640 .hsync_end = 480 + 2 + 41, 2641 .htotal = 480 + 2 + 41 + 2, 2642 .vdisplay = 272, 2643 .vsync_start = 272 + 2, 2644 .vsync_end = 272 + 2 + 4, 2645 .vtotal = 272 + 2 + 4 + 2, 2646 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2647 }; 2648 2649 static const struct panel_desc nec_nl4827hc19_05b = { 2650 .modes = &nec_nl4827hc19_05b_mode, 2651 .num_modes = 1, 2652 .bpc = 8, 2653 .size = { 2654 .width = 95, 2655 .height = 54, 2656 }, 2657 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2658 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2659 }; 2660 2661 static const struct drm_display_mode netron_dy_e231732_mode = { 2662 .clock = 66000, 2663 .hdisplay = 1024, 2664 .hsync_start = 1024 + 160, 2665 .hsync_end = 1024 + 160 + 70, 2666 .htotal = 1024 + 160 + 70 + 90, 2667 .vdisplay = 600, 2668 .vsync_start = 600 + 127, 2669 .vsync_end = 600 + 127 + 20, 2670 .vtotal = 600 + 127 + 20 + 3, 2671 }; 2672 2673 static const struct panel_desc netron_dy_e231732 = { 2674 .modes = &netron_dy_e231732_mode, 2675 .num_modes = 1, 2676 .size = { 2677 .width = 154, 2678 .height = 87, 2679 }, 2680 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2681 }; 2682 2683 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 2684 { 2685 .clock = 138500, 2686 .hdisplay = 1920, 2687 .hsync_start = 1920 + 48, 2688 .hsync_end = 1920 + 48 + 32, 2689 .htotal = 1920 + 48 + 32 + 80, 2690 .vdisplay = 1080, 2691 .vsync_start = 1080 + 3, 2692 .vsync_end = 1080 + 3 + 5, 2693 .vtotal = 1080 + 3 + 5 + 23, 2694 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2695 }, { 2696 .clock = 110920, 2697 .hdisplay = 1920, 2698 .hsync_start = 1920 + 48, 2699 .hsync_end = 1920 + 48 + 32, 2700 .htotal = 1920 + 48 + 32 + 80, 2701 .vdisplay = 1080, 2702 .vsync_start = 1080 + 3, 2703 .vsync_end = 1080 + 3 + 5, 2704 .vtotal = 1080 + 3 + 5 + 23, 2705 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2706 } 2707 }; 2708 2709 static const struct panel_desc neweast_wjfh116008a = { 2710 .modes = neweast_wjfh116008a_modes, 2711 .num_modes = 2, 2712 .bpc = 6, 2713 .size = { 2714 .width = 260, 2715 .height = 150, 2716 }, 2717 .delay = { 2718 .prepare = 110, 2719 .enable = 20, 2720 .unprepare = 500, 2721 }, 2722 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2723 .connector_type = DRM_MODE_CONNECTOR_eDP, 2724 }; 2725 2726 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2727 .clock = 9000, 2728 .hdisplay = 480, 2729 .hsync_start = 480 + 2, 2730 .hsync_end = 480 + 2 + 41, 2731 .htotal = 480 + 2 + 41 + 2, 2732 .vdisplay = 272, 2733 .vsync_start = 272 + 2, 2734 .vsync_end = 272 + 2 + 10, 2735 .vtotal = 272 + 2 + 10 + 2, 2736 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2737 }; 2738 2739 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2740 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2741 .num_modes = 1, 2742 .bpc = 8, 2743 .size = { 2744 .width = 95, 2745 .height = 54, 2746 }, 2747 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2748 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2749 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2750 .connector_type = DRM_MODE_CONNECTOR_DPI, 2751 }; 2752 2753 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2754 .pixelclock = { 130000000, 148350000, 163000000 }, 2755 .hactive = { 1920, 1920, 1920 }, 2756 .hfront_porch = { 80, 100, 100 }, 2757 .hback_porch = { 100, 120, 120 }, 2758 .hsync_len = { 50, 60, 60 }, 2759 .vactive = { 1080, 1080, 1080 }, 2760 .vfront_porch = { 12, 30, 30 }, 2761 .vback_porch = { 4, 10, 10 }, 2762 .vsync_len = { 4, 5, 5 }, 2763 }; 2764 2765 static const struct panel_desc nlt_nl192108ac18_02d = { 2766 .timings = &nlt_nl192108ac18_02d_timing, 2767 .num_timings = 1, 2768 .bpc = 8, 2769 .size = { 2770 .width = 344, 2771 .height = 194, 2772 }, 2773 .delay = { 2774 .unprepare = 500, 2775 }, 2776 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2777 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2778 }; 2779 2780 static const struct drm_display_mode nvd_9128_mode = { 2781 .clock = 29500, 2782 .hdisplay = 800, 2783 .hsync_start = 800 + 130, 2784 .hsync_end = 800 + 130 + 98, 2785 .htotal = 800 + 0 + 130 + 98, 2786 .vdisplay = 480, 2787 .vsync_start = 480 + 10, 2788 .vsync_end = 480 + 10 + 50, 2789 .vtotal = 480 + 0 + 10 + 50, 2790 }; 2791 2792 static const struct panel_desc nvd_9128 = { 2793 .modes = &nvd_9128_mode, 2794 .num_modes = 1, 2795 .bpc = 8, 2796 .size = { 2797 .width = 156, 2798 .height = 88, 2799 }, 2800 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2801 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2802 }; 2803 2804 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2805 .pixelclock = { 30000000, 30000000, 40000000 }, 2806 .hactive = { 800, 800, 800 }, 2807 .hfront_porch = { 40, 40, 40 }, 2808 .hback_porch = { 40, 40, 40 }, 2809 .hsync_len = { 1, 48, 48 }, 2810 .vactive = { 480, 480, 480 }, 2811 .vfront_porch = { 13, 13, 13 }, 2812 .vback_porch = { 29, 29, 29 }, 2813 .vsync_len = { 3, 3, 3 }, 2814 .flags = DISPLAY_FLAGS_DE_HIGH, 2815 }; 2816 2817 static const struct panel_desc okaya_rs800480t_7x0gp = { 2818 .timings = &okaya_rs800480t_7x0gp_timing, 2819 .num_timings = 1, 2820 .bpc = 6, 2821 .size = { 2822 .width = 154, 2823 .height = 87, 2824 }, 2825 .delay = { 2826 .prepare = 41, 2827 .enable = 50, 2828 .unprepare = 41, 2829 .disable = 50, 2830 }, 2831 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2832 }; 2833 2834 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2835 .clock = 9000, 2836 .hdisplay = 480, 2837 .hsync_start = 480 + 5, 2838 .hsync_end = 480 + 5 + 30, 2839 .htotal = 480 + 5 + 30 + 10, 2840 .vdisplay = 272, 2841 .vsync_start = 272 + 8, 2842 .vsync_end = 272 + 8 + 5, 2843 .vtotal = 272 + 8 + 5 + 3, 2844 }; 2845 2846 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2847 .modes = &olimex_lcd_olinuxino_43ts_mode, 2848 .num_modes = 1, 2849 .size = { 2850 .width = 95, 2851 .height = 54, 2852 }, 2853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2854 }; 2855 2856 /* 2857 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2858 * pixel clocks, but this is the timing that was being used in the Adafruit 2859 * installation instructions. 2860 */ 2861 static const struct drm_display_mode ontat_yx700wv03_mode = { 2862 .clock = 29500, 2863 .hdisplay = 800, 2864 .hsync_start = 824, 2865 .hsync_end = 896, 2866 .htotal = 992, 2867 .vdisplay = 480, 2868 .vsync_start = 483, 2869 .vsync_end = 493, 2870 .vtotal = 500, 2871 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2872 }; 2873 2874 /* 2875 * Specification at: 2876 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2877 */ 2878 static const struct panel_desc ontat_yx700wv03 = { 2879 .modes = &ontat_yx700wv03_mode, 2880 .num_modes = 1, 2881 .bpc = 8, 2882 .size = { 2883 .width = 154, 2884 .height = 83, 2885 }, 2886 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2887 }; 2888 2889 static const struct drm_display_mode ortustech_com37h3m_mode = { 2890 .clock = 22230, 2891 .hdisplay = 480, 2892 .hsync_start = 480 + 40, 2893 .hsync_end = 480 + 40 + 10, 2894 .htotal = 480 + 40 + 10 + 40, 2895 .vdisplay = 640, 2896 .vsync_start = 640 + 4, 2897 .vsync_end = 640 + 4 + 2, 2898 .vtotal = 640 + 4 + 2 + 4, 2899 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2900 }; 2901 2902 static const struct panel_desc ortustech_com37h3m = { 2903 .modes = &ortustech_com37h3m_mode, 2904 .num_modes = 1, 2905 .bpc = 8, 2906 .size = { 2907 .width = 56, /* 56.16mm */ 2908 .height = 75, /* 74.88mm */ 2909 }, 2910 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2911 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2912 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2913 }; 2914 2915 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 2916 .clock = 25000, 2917 .hdisplay = 480, 2918 .hsync_start = 480 + 10, 2919 .hsync_end = 480 + 10 + 10, 2920 .htotal = 480 + 10 + 10 + 15, 2921 .vdisplay = 800, 2922 .vsync_start = 800 + 3, 2923 .vsync_end = 800 + 3 + 3, 2924 .vtotal = 800 + 3 + 3 + 3, 2925 }; 2926 2927 static const struct panel_desc ortustech_com43h4m85ulc = { 2928 .modes = &ortustech_com43h4m85ulc_mode, 2929 .num_modes = 1, 2930 .bpc = 8, 2931 .size = { 2932 .width = 56, 2933 .height = 93, 2934 }, 2935 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2936 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2937 .connector_type = DRM_MODE_CONNECTOR_DPI, 2938 }; 2939 2940 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 2941 .clock = 33000, 2942 .hdisplay = 800, 2943 .hsync_start = 800 + 210, 2944 .hsync_end = 800 + 210 + 30, 2945 .htotal = 800 + 210 + 30 + 16, 2946 .vdisplay = 480, 2947 .vsync_start = 480 + 22, 2948 .vsync_end = 480 + 22 + 13, 2949 .vtotal = 480 + 22 + 13 + 10, 2950 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2951 }; 2952 2953 static const struct panel_desc osddisplays_osd070t1718_19ts = { 2954 .modes = &osddisplays_osd070t1718_19ts_mode, 2955 .num_modes = 1, 2956 .bpc = 8, 2957 .size = { 2958 .width = 152, 2959 .height = 91, 2960 }, 2961 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2962 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2963 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2964 .connector_type = DRM_MODE_CONNECTOR_DPI, 2965 }; 2966 2967 static const struct drm_display_mode pda_91_00156_a0_mode = { 2968 .clock = 33300, 2969 .hdisplay = 800, 2970 .hsync_start = 800 + 1, 2971 .hsync_end = 800 + 1 + 64, 2972 .htotal = 800 + 1 + 64 + 64, 2973 .vdisplay = 480, 2974 .vsync_start = 480 + 1, 2975 .vsync_end = 480 + 1 + 23, 2976 .vtotal = 480 + 1 + 23 + 22, 2977 }; 2978 2979 static const struct panel_desc pda_91_00156_a0 = { 2980 .modes = &pda_91_00156_a0_mode, 2981 .num_modes = 1, 2982 .size = { 2983 .width = 152, 2984 .height = 91, 2985 }, 2986 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2987 }; 2988 2989 2990 static const struct drm_display_mode qd43003c0_40_mode = { 2991 .clock = 9000, 2992 .hdisplay = 480, 2993 .hsync_start = 480 + 8, 2994 .hsync_end = 480 + 8 + 4, 2995 .htotal = 480 + 8 + 4 + 39, 2996 .vdisplay = 272, 2997 .vsync_start = 272 + 4, 2998 .vsync_end = 272 + 4 + 10, 2999 .vtotal = 272 + 4 + 10 + 2, 3000 }; 3001 3002 static const struct panel_desc qd43003c0_40 = { 3003 .modes = &qd43003c0_40_mode, 3004 .num_modes = 1, 3005 .bpc = 8, 3006 .size = { 3007 .width = 95, 3008 .height = 53, 3009 }, 3010 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3011 }; 3012 3013 static const struct display_timing rocktech_rk070er9427_timing = { 3014 .pixelclock = { 26400000, 33300000, 46800000 }, 3015 .hactive = { 800, 800, 800 }, 3016 .hfront_porch = { 16, 210, 354 }, 3017 .hback_porch = { 46, 46, 46 }, 3018 .hsync_len = { 1, 1, 1 }, 3019 .vactive = { 480, 480, 480 }, 3020 .vfront_porch = { 7, 22, 147 }, 3021 .vback_porch = { 23, 23, 23 }, 3022 .vsync_len = { 1, 1, 1 }, 3023 .flags = DISPLAY_FLAGS_DE_HIGH, 3024 }; 3025 3026 static const struct panel_desc rocktech_rk070er9427 = { 3027 .timings = &rocktech_rk070er9427_timing, 3028 .num_timings = 1, 3029 .bpc = 6, 3030 .size = { 3031 .width = 154, 3032 .height = 86, 3033 }, 3034 .delay = { 3035 .prepare = 41, 3036 .enable = 50, 3037 .unprepare = 41, 3038 .disable = 50, 3039 }, 3040 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3041 }; 3042 3043 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3044 .clock = 71100, 3045 .hdisplay = 1280, 3046 .hsync_start = 1280 + 48, 3047 .hsync_end = 1280 + 48 + 32, 3048 .htotal = 1280 + 48 + 32 + 80, 3049 .vdisplay = 800, 3050 .vsync_start = 800 + 2, 3051 .vsync_end = 800 + 2 + 5, 3052 .vtotal = 800 + 2 + 5 + 16, 3053 }; 3054 3055 static const struct panel_desc rocktech_rk101ii01d_ct = { 3056 .modes = &rocktech_rk101ii01d_ct_mode, 3057 .num_modes = 1, 3058 .size = { 3059 .width = 217, 3060 .height = 136, 3061 }, 3062 .delay = { 3063 .prepare = 50, 3064 .disable = 50, 3065 }, 3066 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3067 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3068 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3069 }; 3070 3071 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 3072 .clock = 271560, 3073 .hdisplay = 2560, 3074 .hsync_start = 2560 + 48, 3075 .hsync_end = 2560 + 48 + 32, 3076 .htotal = 2560 + 48 + 32 + 80, 3077 .vdisplay = 1600, 3078 .vsync_start = 1600 + 2, 3079 .vsync_end = 1600 + 2 + 5, 3080 .vtotal = 1600 + 2 + 5 + 57, 3081 }; 3082 3083 static const struct panel_desc samsung_lsn122dl01_c01 = { 3084 .modes = &samsung_lsn122dl01_c01_mode, 3085 .num_modes = 1, 3086 .size = { 3087 .width = 263, 3088 .height = 164, 3089 }, 3090 }; 3091 3092 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3093 .clock = 54030, 3094 .hdisplay = 1024, 3095 .hsync_start = 1024 + 24, 3096 .hsync_end = 1024 + 24 + 136, 3097 .htotal = 1024 + 24 + 136 + 160, 3098 .vdisplay = 600, 3099 .vsync_start = 600 + 3, 3100 .vsync_end = 600 + 3 + 6, 3101 .vtotal = 600 + 3 + 6 + 61, 3102 }; 3103 3104 static const struct panel_desc samsung_ltn101nt05 = { 3105 .modes = &samsung_ltn101nt05_mode, 3106 .num_modes = 1, 3107 .bpc = 6, 3108 .size = { 3109 .width = 223, 3110 .height = 125, 3111 }, 3112 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3113 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3114 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3115 }; 3116 3117 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 3118 .clock = 76300, 3119 .hdisplay = 1366, 3120 .hsync_start = 1366 + 64, 3121 .hsync_end = 1366 + 64 + 48, 3122 .htotal = 1366 + 64 + 48 + 128, 3123 .vdisplay = 768, 3124 .vsync_start = 768 + 2, 3125 .vsync_end = 768 + 2 + 5, 3126 .vtotal = 768 + 2 + 5 + 17, 3127 }; 3128 3129 static const struct panel_desc samsung_ltn140at29_301 = { 3130 .modes = &samsung_ltn140at29_301_mode, 3131 .num_modes = 1, 3132 .bpc = 6, 3133 .size = { 3134 .width = 320, 3135 .height = 187, 3136 }, 3137 }; 3138 3139 static const struct display_timing satoz_sat050at40h12r2_timing = { 3140 .pixelclock = {33300000, 33300000, 50000000}, 3141 .hactive = {800, 800, 800}, 3142 .hfront_porch = {16, 210, 354}, 3143 .hback_porch = {46, 46, 46}, 3144 .hsync_len = {1, 1, 40}, 3145 .vactive = {480, 480, 480}, 3146 .vfront_porch = {7, 22, 147}, 3147 .vback_porch = {23, 23, 23}, 3148 .vsync_len = {1, 1, 20}, 3149 }; 3150 3151 static const struct panel_desc satoz_sat050at40h12r2 = { 3152 .timings = &satoz_sat050at40h12r2_timing, 3153 .num_timings = 1, 3154 .bpc = 8, 3155 .size = { 3156 .width = 108, 3157 .height = 65, 3158 }, 3159 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3160 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3161 }; 3162 3163 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 3164 .clock = 168480, 3165 .hdisplay = 1920, 3166 .hsync_start = 1920 + 48, 3167 .hsync_end = 1920 + 48 + 32, 3168 .htotal = 1920 + 48 + 32 + 80, 3169 .vdisplay = 1280, 3170 .vsync_start = 1280 + 3, 3171 .vsync_end = 1280 + 3 + 10, 3172 .vtotal = 1280 + 3 + 10 + 57, 3173 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3174 }; 3175 3176 static const struct panel_desc sharp_ld_d5116z01b = { 3177 .modes = &sharp_ld_d5116z01b_mode, 3178 .num_modes = 1, 3179 .bpc = 8, 3180 .size = { 3181 .width = 260, 3182 .height = 120, 3183 }, 3184 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3185 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 3186 }; 3187 3188 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3189 .clock = 33260, 3190 .hdisplay = 800, 3191 .hsync_start = 800 + 64, 3192 .hsync_end = 800 + 64 + 128, 3193 .htotal = 800 + 64 + 128 + 64, 3194 .vdisplay = 480, 3195 .vsync_start = 480 + 8, 3196 .vsync_end = 480 + 8 + 2, 3197 .vtotal = 480 + 8 + 2 + 35, 3198 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3199 }; 3200 3201 static const struct panel_desc sharp_lq070y3dg3b = { 3202 .modes = &sharp_lq070y3dg3b_mode, 3203 .num_modes = 1, 3204 .bpc = 8, 3205 .size = { 3206 .width = 152, /* 152.4mm */ 3207 .height = 91, /* 91.4mm */ 3208 }, 3209 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3210 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3211 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3212 }; 3213 3214 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3215 .clock = 5500, 3216 .hdisplay = 240, 3217 .hsync_start = 240 + 16, 3218 .hsync_end = 240 + 16 + 7, 3219 .htotal = 240 + 16 + 7 + 5, 3220 .vdisplay = 320, 3221 .vsync_start = 320 + 9, 3222 .vsync_end = 320 + 9 + 1, 3223 .vtotal = 320 + 9 + 1 + 7, 3224 }; 3225 3226 static const struct panel_desc sharp_lq035q7db03 = { 3227 .modes = &sharp_lq035q7db03_mode, 3228 .num_modes = 1, 3229 .bpc = 6, 3230 .size = { 3231 .width = 54, 3232 .height = 72, 3233 }, 3234 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3235 }; 3236 3237 static const struct display_timing sharp_lq101k1ly04_timing = { 3238 .pixelclock = { 60000000, 65000000, 80000000 }, 3239 .hactive = { 1280, 1280, 1280 }, 3240 .hfront_porch = { 20, 20, 20 }, 3241 .hback_porch = { 20, 20, 20 }, 3242 .hsync_len = { 10, 10, 10 }, 3243 .vactive = { 800, 800, 800 }, 3244 .vfront_porch = { 4, 4, 4 }, 3245 .vback_porch = { 4, 4, 4 }, 3246 .vsync_len = { 4, 4, 4 }, 3247 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3248 }; 3249 3250 static const struct panel_desc sharp_lq101k1ly04 = { 3251 .timings = &sharp_lq101k1ly04_timing, 3252 .num_timings = 1, 3253 .bpc = 8, 3254 .size = { 3255 .width = 217, 3256 .height = 136, 3257 }, 3258 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3259 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3260 }; 3261 3262 static const struct display_timing sharp_lq123p1jx31_timing = { 3263 .pixelclock = { 252750000, 252750000, 266604720 }, 3264 .hactive = { 2400, 2400, 2400 }, 3265 .hfront_porch = { 48, 48, 48 }, 3266 .hback_porch = { 80, 80, 84 }, 3267 .hsync_len = { 32, 32, 32 }, 3268 .vactive = { 1600, 1600, 1600 }, 3269 .vfront_porch = { 3, 3, 3 }, 3270 .vback_porch = { 33, 33, 120 }, 3271 .vsync_len = { 10, 10, 10 }, 3272 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3273 }; 3274 3275 static const struct panel_desc sharp_lq123p1jx31 = { 3276 .timings = &sharp_lq123p1jx31_timing, 3277 .num_timings = 1, 3278 .bpc = 8, 3279 .size = { 3280 .width = 259, 3281 .height = 173, 3282 }, 3283 .delay = { 3284 .prepare = 110, 3285 .enable = 50, 3286 .unprepare = 550, 3287 }, 3288 }; 3289 3290 static const struct display_timing sharp_ls020b1dd01d_timing = { 3291 .pixelclock = { 2000000, 4200000, 5000000 }, 3292 .hactive = { 240, 240, 240 }, 3293 .hfront_porch = { 66, 66, 66 }, 3294 .hback_porch = { 1, 1, 1 }, 3295 .hsync_len = { 1, 1, 1 }, 3296 .vactive = { 160, 160, 160 }, 3297 .vfront_porch = { 52, 52, 52 }, 3298 .vback_porch = { 6, 6, 6 }, 3299 .vsync_len = { 10, 10, 10 }, 3300 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW, 3301 }; 3302 3303 static const struct panel_desc sharp_ls020b1dd01d = { 3304 .timings = &sharp_ls020b1dd01d_timing, 3305 .num_timings = 1, 3306 .bpc = 6, 3307 .size = { 3308 .width = 42, 3309 .height = 28, 3310 }, 3311 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3312 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3313 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3314 | DRM_BUS_FLAG_SHARP_SIGNALS, 3315 }; 3316 3317 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3318 .clock = 33300, 3319 .hdisplay = 800, 3320 .hsync_start = 800 + 1, 3321 .hsync_end = 800 + 1 + 64, 3322 .htotal = 800 + 1 + 64 + 64, 3323 .vdisplay = 480, 3324 .vsync_start = 480 + 1, 3325 .vsync_end = 480 + 1 + 23, 3326 .vtotal = 480 + 1 + 23 + 22, 3327 }; 3328 3329 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3330 .modes = &shelly_sca07010_bfn_lnn_mode, 3331 .num_modes = 1, 3332 .size = { 3333 .width = 152, 3334 .height = 91, 3335 }, 3336 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3337 }; 3338 3339 static const struct drm_display_mode starry_kr070pe2t_mode = { 3340 .clock = 33000, 3341 .hdisplay = 800, 3342 .hsync_start = 800 + 209, 3343 .hsync_end = 800 + 209 + 1, 3344 .htotal = 800 + 209 + 1 + 45, 3345 .vdisplay = 480, 3346 .vsync_start = 480 + 22, 3347 .vsync_end = 480 + 22 + 1, 3348 .vtotal = 480 + 22 + 1 + 22, 3349 }; 3350 3351 static const struct panel_desc starry_kr070pe2t = { 3352 .modes = &starry_kr070pe2t_mode, 3353 .num_modes = 1, 3354 .bpc = 8, 3355 .size = { 3356 .width = 152, 3357 .height = 86, 3358 }, 3359 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3360 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3361 .connector_type = DRM_MODE_CONNECTOR_DPI, 3362 }; 3363 3364 static const struct drm_display_mode starry_kr122ea0sra_mode = { 3365 .clock = 147000, 3366 .hdisplay = 1920, 3367 .hsync_start = 1920 + 16, 3368 .hsync_end = 1920 + 16 + 16, 3369 .htotal = 1920 + 16 + 16 + 32, 3370 .vdisplay = 1200, 3371 .vsync_start = 1200 + 15, 3372 .vsync_end = 1200 + 15 + 2, 3373 .vtotal = 1200 + 15 + 2 + 18, 3374 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3375 }; 3376 3377 static const struct panel_desc starry_kr122ea0sra = { 3378 .modes = &starry_kr122ea0sra_mode, 3379 .num_modes = 1, 3380 .size = { 3381 .width = 263, 3382 .height = 164, 3383 }, 3384 .delay = { 3385 .prepare = 10 + 200, 3386 .enable = 50, 3387 .unprepare = 10 + 500, 3388 }, 3389 }; 3390 3391 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3392 .clock = 30000, 3393 .hdisplay = 800, 3394 .hsync_start = 800 + 39, 3395 .hsync_end = 800 + 39 + 47, 3396 .htotal = 800 + 39 + 47 + 39, 3397 .vdisplay = 480, 3398 .vsync_start = 480 + 13, 3399 .vsync_end = 480 + 13 + 2, 3400 .vtotal = 480 + 13 + 2 + 29, 3401 }; 3402 3403 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3404 .modes = &tfc_s9700rtwv43tr_01b_mode, 3405 .num_modes = 1, 3406 .bpc = 8, 3407 .size = { 3408 .width = 155, 3409 .height = 90, 3410 }, 3411 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3412 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3413 }; 3414 3415 static const struct display_timing tianma_tm070jdhg30_timing = { 3416 .pixelclock = { 62600000, 68200000, 78100000 }, 3417 .hactive = { 1280, 1280, 1280 }, 3418 .hfront_porch = { 15, 64, 159 }, 3419 .hback_porch = { 5, 5, 5 }, 3420 .hsync_len = { 1, 1, 256 }, 3421 .vactive = { 800, 800, 800 }, 3422 .vfront_porch = { 3, 40, 99 }, 3423 .vback_porch = { 2, 2, 2 }, 3424 .vsync_len = { 1, 1, 128 }, 3425 .flags = DISPLAY_FLAGS_DE_HIGH, 3426 }; 3427 3428 static const struct panel_desc tianma_tm070jdhg30 = { 3429 .timings = &tianma_tm070jdhg30_timing, 3430 .num_timings = 1, 3431 .bpc = 8, 3432 .size = { 3433 .width = 151, 3434 .height = 95, 3435 }, 3436 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3437 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3438 }; 3439 3440 static const struct panel_desc tianma_tm070jvhg33 = { 3441 .timings = &tianma_tm070jdhg30_timing, 3442 .num_timings = 1, 3443 .bpc = 8, 3444 .size = { 3445 .width = 150, 3446 .height = 94, 3447 }, 3448 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3449 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3450 }; 3451 3452 static const struct display_timing tianma_tm070rvhg71_timing = { 3453 .pixelclock = { 27700000, 29200000, 39600000 }, 3454 .hactive = { 800, 800, 800 }, 3455 .hfront_porch = { 12, 40, 212 }, 3456 .hback_porch = { 88, 88, 88 }, 3457 .hsync_len = { 1, 1, 40 }, 3458 .vactive = { 480, 480, 480 }, 3459 .vfront_porch = { 1, 13, 88 }, 3460 .vback_porch = { 32, 32, 32 }, 3461 .vsync_len = { 1, 1, 3 }, 3462 .flags = DISPLAY_FLAGS_DE_HIGH, 3463 }; 3464 3465 static const struct panel_desc tianma_tm070rvhg71 = { 3466 .timings = &tianma_tm070rvhg71_timing, 3467 .num_timings = 1, 3468 .bpc = 8, 3469 .size = { 3470 .width = 154, 3471 .height = 86, 3472 }, 3473 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3474 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3475 }; 3476 3477 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3478 { 3479 .clock = 10000, 3480 .hdisplay = 320, 3481 .hsync_start = 320 + 50, 3482 .hsync_end = 320 + 50 + 6, 3483 .htotal = 320 + 50 + 6 + 38, 3484 .vdisplay = 240, 3485 .vsync_start = 240 + 3, 3486 .vsync_end = 240 + 3 + 1, 3487 .vtotal = 240 + 3 + 1 + 17, 3488 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3489 }, 3490 }; 3491 3492 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3493 .modes = ti_nspire_cx_lcd_mode, 3494 .num_modes = 1, 3495 .bpc = 8, 3496 .size = { 3497 .width = 65, 3498 .height = 49, 3499 }, 3500 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3501 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3502 }; 3503 3504 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3505 { 3506 .clock = 10000, 3507 .hdisplay = 320, 3508 .hsync_start = 320 + 6, 3509 .hsync_end = 320 + 6 + 6, 3510 .htotal = 320 + 6 + 6 + 6, 3511 .vdisplay = 240, 3512 .vsync_start = 240 + 0, 3513 .vsync_end = 240 + 0 + 1, 3514 .vtotal = 240 + 0 + 1 + 0, 3515 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3516 }, 3517 }; 3518 3519 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3520 .modes = ti_nspire_classic_lcd_mode, 3521 .num_modes = 1, 3522 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3523 .bpc = 8, 3524 .size = { 3525 .width = 71, 3526 .height = 53, 3527 }, 3528 /* This is the grayscale bus format */ 3529 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3530 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3531 }; 3532 3533 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3534 .clock = 79500, 3535 .hdisplay = 1280, 3536 .hsync_start = 1280 + 192, 3537 .hsync_end = 1280 + 192 + 128, 3538 .htotal = 1280 + 192 + 128 + 64, 3539 .vdisplay = 768, 3540 .vsync_start = 768 + 20, 3541 .vsync_end = 768 + 20 + 7, 3542 .vtotal = 768 + 20 + 7 + 3, 3543 }; 3544 3545 static const struct panel_desc toshiba_lt089ac29000 = { 3546 .modes = &toshiba_lt089ac29000_mode, 3547 .num_modes = 1, 3548 .size = { 3549 .width = 194, 3550 .height = 116, 3551 }, 3552 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3553 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3554 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3555 }; 3556 3557 static const struct drm_display_mode tpk_f07a_0102_mode = { 3558 .clock = 33260, 3559 .hdisplay = 800, 3560 .hsync_start = 800 + 40, 3561 .hsync_end = 800 + 40 + 128, 3562 .htotal = 800 + 40 + 128 + 88, 3563 .vdisplay = 480, 3564 .vsync_start = 480 + 10, 3565 .vsync_end = 480 + 10 + 2, 3566 .vtotal = 480 + 10 + 2 + 33, 3567 }; 3568 3569 static const struct panel_desc tpk_f07a_0102 = { 3570 .modes = &tpk_f07a_0102_mode, 3571 .num_modes = 1, 3572 .size = { 3573 .width = 152, 3574 .height = 91, 3575 }, 3576 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3577 }; 3578 3579 static const struct drm_display_mode tpk_f10a_0102_mode = { 3580 .clock = 45000, 3581 .hdisplay = 1024, 3582 .hsync_start = 1024 + 176, 3583 .hsync_end = 1024 + 176 + 5, 3584 .htotal = 1024 + 176 + 5 + 88, 3585 .vdisplay = 600, 3586 .vsync_start = 600 + 20, 3587 .vsync_end = 600 + 20 + 5, 3588 .vtotal = 600 + 20 + 5 + 25, 3589 }; 3590 3591 static const struct panel_desc tpk_f10a_0102 = { 3592 .modes = &tpk_f10a_0102_mode, 3593 .num_modes = 1, 3594 .size = { 3595 .width = 223, 3596 .height = 125, 3597 }, 3598 }; 3599 3600 static const struct display_timing urt_umsh_8596md_timing = { 3601 .pixelclock = { 33260000, 33260000, 33260000 }, 3602 .hactive = { 800, 800, 800 }, 3603 .hfront_porch = { 41, 41, 41 }, 3604 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3605 .hsync_len = { 71, 128, 128 }, 3606 .vactive = { 480, 480, 480 }, 3607 .vfront_porch = { 10, 10, 10 }, 3608 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3609 .vsync_len = { 2, 2, 2 }, 3610 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3611 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3612 }; 3613 3614 static const struct panel_desc urt_umsh_8596md_lvds = { 3615 .timings = &urt_umsh_8596md_timing, 3616 .num_timings = 1, 3617 .bpc = 6, 3618 .size = { 3619 .width = 152, 3620 .height = 91, 3621 }, 3622 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3623 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3624 }; 3625 3626 static const struct panel_desc urt_umsh_8596md_parallel = { 3627 .timings = &urt_umsh_8596md_timing, 3628 .num_timings = 1, 3629 .bpc = 6, 3630 .size = { 3631 .width = 152, 3632 .height = 91, 3633 }, 3634 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3635 }; 3636 3637 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3638 .clock = 33333, 3639 .hdisplay = 800, 3640 .hsync_start = 800 + 210, 3641 .hsync_end = 800 + 210 + 20, 3642 .htotal = 800 + 210 + 20 + 46, 3643 .vdisplay = 480, 3644 .vsync_start = 480 + 22, 3645 .vsync_end = 480 + 22 + 10, 3646 .vtotal = 480 + 22 + 10 + 23, 3647 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3648 }; 3649 3650 static const struct panel_desc vl050_8048nt_c01 = { 3651 .modes = &vl050_8048nt_c01_mode, 3652 .num_modes = 1, 3653 .bpc = 8, 3654 .size = { 3655 .width = 120, 3656 .height = 76, 3657 }, 3658 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3659 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3660 }; 3661 3662 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3663 .clock = 6410, 3664 .hdisplay = 320, 3665 .hsync_start = 320 + 20, 3666 .hsync_end = 320 + 20 + 30, 3667 .htotal = 320 + 20 + 30 + 38, 3668 .vdisplay = 240, 3669 .vsync_start = 240 + 4, 3670 .vsync_end = 240 + 4 + 3, 3671 .vtotal = 240 + 4 + 3 + 15, 3672 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3673 }; 3674 3675 static const struct panel_desc winstar_wf35ltiacd = { 3676 .modes = &winstar_wf35ltiacd_mode, 3677 .num_modes = 1, 3678 .bpc = 8, 3679 .size = { 3680 .width = 70, 3681 .height = 53, 3682 }, 3683 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3684 }; 3685 3686 static const struct drm_display_mode arm_rtsm_mode[] = { 3687 { 3688 .clock = 65000, 3689 .hdisplay = 1024, 3690 .hsync_start = 1024 + 24, 3691 .hsync_end = 1024 + 24 + 136, 3692 .htotal = 1024 + 24 + 136 + 160, 3693 .vdisplay = 768, 3694 .vsync_start = 768 + 3, 3695 .vsync_end = 768 + 3 + 6, 3696 .vtotal = 768 + 3 + 6 + 29, 3697 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3698 }, 3699 }; 3700 3701 static const struct panel_desc arm_rtsm = { 3702 .modes = arm_rtsm_mode, 3703 .num_modes = 1, 3704 .bpc = 8, 3705 .size = { 3706 .width = 400, 3707 .height = 300, 3708 }, 3709 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3710 }; 3711 3712 static const struct of_device_id platform_of_match[] = { 3713 { 3714 .compatible = "ampire,am-480272h3tmqw-t01h", 3715 .data = &ire_am_480272h3tmqw_t01h, 3716 }, { 3717 .compatible = "ampire,am800480r3tmqwa1h", 3718 .data = &ire_am800480r3tmqwa1h, 3719 }, { 3720 .compatible = "arm,rtsm-display", 3721 .data = &arm_rtsm, 3722 }, { 3723 .compatible = "armadeus,st0700-adapt", 3724 .data = &armadeus_st0700_adapt, 3725 }, { 3726 .compatible = "auo,b101aw03", 3727 .data = &auo_b101aw03, 3728 }, { 3729 .compatible = "auo,b101ean01", 3730 .data = &auo_b101ean01, 3731 }, { 3732 .compatible = "auo,b101xtn01", 3733 .data = &auo_b101xtn01, 3734 }, { 3735 .compatible = "auo,b116xa01", 3736 .data = &auo_b116xak01, 3737 }, { 3738 .compatible = "auo,b116xw03", 3739 .data = &auo_b116xw03, 3740 }, { 3741 .compatible = "auo,b133htn01", 3742 .data = &auo_b133htn01, 3743 }, { 3744 .compatible = "auo,b133xtn01", 3745 .data = &auo_b133xtn01, 3746 }, { 3747 .compatible = "auo,g070vvn01", 3748 .data = &auo_g070vvn01, 3749 }, { 3750 .compatible = "auo,g101evn010", 3751 .data = &auo_g101evn010, 3752 }, { 3753 .compatible = "auo,g104sn02", 3754 .data = &auo_g104sn02, 3755 }, { 3756 .compatible = "auo,g121ean01", 3757 .data = &auo_g121ean01, 3758 }, { 3759 .compatible = "auo,g133han01", 3760 .data = &auo_g133han01, 3761 }, { 3762 .compatible = "auo,g156xtn01", 3763 .data = &auo_g156xtn01, 3764 }, { 3765 .compatible = "auo,g185han01", 3766 .data = &auo_g185han01, 3767 }, { 3768 .compatible = "auo,g190ean01", 3769 .data = &auo_g190ean01, 3770 }, { 3771 .compatible = "auo,p320hvn03", 3772 .data = &auo_p320hvn03, 3773 }, { 3774 .compatible = "auo,t215hvn01", 3775 .data = &auo_t215hvn01, 3776 }, { 3777 .compatible = "avic,tm070ddh03", 3778 .data = &avic_tm070ddh03, 3779 }, { 3780 .compatible = "bananapi,s070wv20-ct16", 3781 .data = &bananapi_s070wv20_ct16, 3782 }, { 3783 .compatible = "boe,hv070wsa-100", 3784 .data = &boe_hv070wsa 3785 }, { 3786 .compatible = "boe,nv101wxmn51", 3787 .data = &boe_nv101wxmn51, 3788 }, { 3789 .compatible = "boe,nv133fhm-n61", 3790 .data = &boe_nv133fhm_n61, 3791 }, { 3792 .compatible = "boe,nv133fhm-n62", 3793 .data = &boe_nv133fhm_n61, 3794 }, { 3795 .compatible = "boe,nv140fhmn49", 3796 .data = &boe_nv140fhmn49, 3797 }, { 3798 .compatible = "cdtech,s043wq26h-ct7", 3799 .data = &cdtech_s043wq26h_ct7, 3800 }, { 3801 .compatible = "cdtech,s070pws19hp-fc21", 3802 .data = &cdtech_s070pws19hp_fc21, 3803 }, { 3804 .compatible = "cdtech,s070swv29hg-dc44", 3805 .data = &cdtech_s070swv29hg_dc44, 3806 }, { 3807 .compatible = "cdtech,s070wv95-ct16", 3808 .data = &cdtech_s070wv95_ct16, 3809 }, { 3810 .compatible = "chunghwa,claa070wp03xg", 3811 .data = &chunghwa_claa070wp03xg, 3812 }, { 3813 .compatible = "chunghwa,claa101wa01a", 3814 .data = &chunghwa_claa101wa01a 3815 }, { 3816 .compatible = "chunghwa,claa101wb01", 3817 .data = &chunghwa_claa101wb01 3818 }, { 3819 .compatible = "dataimage,scf0700c48ggu18", 3820 .data = &dataimage_scf0700c48ggu18, 3821 }, { 3822 .compatible = "dlc,dlc0700yzg-1", 3823 .data = &dlc_dlc0700yzg_1, 3824 }, { 3825 .compatible = "dlc,dlc1010gig", 3826 .data = &dlc_dlc1010gig, 3827 }, { 3828 .compatible = "edt,et035012dm6", 3829 .data = &edt_et035012dm6, 3830 }, { 3831 .compatible = "edt,etm043080dh6gp", 3832 .data = &edt_etm043080dh6gp, 3833 }, { 3834 .compatible = "edt,etm0430g0dh6", 3835 .data = &edt_etm0430g0dh6, 3836 }, { 3837 .compatible = "edt,et057090dhu", 3838 .data = &edt_et057090dhu, 3839 }, { 3840 .compatible = "edt,et070080dh6", 3841 .data = &edt_etm0700g0dh6, 3842 }, { 3843 .compatible = "edt,etm0700g0dh6", 3844 .data = &edt_etm0700g0dh6, 3845 }, { 3846 .compatible = "edt,etm0700g0bdh6", 3847 .data = &edt_etm0700g0bdh6, 3848 }, { 3849 .compatible = "edt,etm0700g0edh6", 3850 .data = &edt_etm0700g0bdh6, 3851 }, { 3852 .compatible = "evervision,vgg804821", 3853 .data = &evervision_vgg804821, 3854 }, { 3855 .compatible = "foxlink,fl500wvr00-a0t", 3856 .data = &foxlink_fl500wvr00_a0t, 3857 }, { 3858 .compatible = "frida,frd350h54004", 3859 .data = &frida_frd350h54004, 3860 }, { 3861 .compatible = "friendlyarm,hd702e", 3862 .data = &friendlyarm_hd702e, 3863 }, { 3864 .compatible = "giantplus,gpg482739qs5", 3865 .data = &giantplus_gpg482739qs5 3866 }, { 3867 .compatible = "giantplus,gpm940b0", 3868 .data = &giantplus_gpm940b0, 3869 }, { 3870 .compatible = "hannstar,hsd070pww1", 3871 .data = &hannstar_hsd070pww1, 3872 }, { 3873 .compatible = "hannstar,hsd100pxn1", 3874 .data = &hannstar_hsd100pxn1, 3875 }, { 3876 .compatible = "hit,tx23d38vm0caa", 3877 .data = &hitachi_tx23d38vm0caa 3878 }, { 3879 .compatible = "innolux,at043tn24", 3880 .data = &innolux_at043tn24, 3881 }, { 3882 .compatible = "innolux,at070tn92", 3883 .data = &innolux_at070tn92, 3884 }, { 3885 .compatible = "innolux,g070y2-l01", 3886 .data = &innolux_g070y2_l01, 3887 }, { 3888 .compatible = "innolux,g101ice-l01", 3889 .data = &innolux_g101ice_l01 3890 }, { 3891 .compatible = "innolux,g121i1-l01", 3892 .data = &innolux_g121i1_l01 3893 }, { 3894 .compatible = "innolux,g121x1-l03", 3895 .data = &innolux_g121x1_l03, 3896 }, { 3897 .compatible = "innolux,n116bge", 3898 .data = &innolux_n116bge, 3899 }, { 3900 .compatible = "innolux,n156bge-l21", 3901 .data = &innolux_n156bge_l21, 3902 }, { 3903 .compatible = "innolux,p120zdg-bf1", 3904 .data = &innolux_p120zdg_bf1, 3905 }, { 3906 .compatible = "innolux,zj070na-01p", 3907 .data = &innolux_zj070na_01p, 3908 }, { 3909 .compatible = "ivo,m133nwf4-r0", 3910 .data = &ivo_m133nwf4_r0, 3911 }, { 3912 .compatible = "koe,tx14d24vm1bpa", 3913 .data = &koe_tx14d24vm1bpa, 3914 }, { 3915 .compatible = "koe,tx26d202vm0bwa", 3916 .data = &koe_tx26d202vm0bwa, 3917 }, { 3918 .compatible = "koe,tx31d200vm0baa", 3919 .data = &koe_tx31d200vm0baa, 3920 }, { 3921 .compatible = "kyo,tcg121xglp", 3922 .data = &kyo_tcg121xglp, 3923 }, { 3924 .compatible = "lemaker,bl035-rgb-002", 3925 .data = &lemaker_bl035_rgb_002, 3926 }, { 3927 .compatible = "lg,lb070wv8", 3928 .data = &lg_lb070wv8, 3929 }, { 3930 .compatible = "lg,lp079qx1-sp0v", 3931 .data = &lg_lp079qx1_sp0v, 3932 }, { 3933 .compatible = "lg,lp097qx1-spa1", 3934 .data = &lg_lp097qx1_spa1, 3935 }, { 3936 .compatible = "lg,lp120up1", 3937 .data = &lg_lp120up1, 3938 }, { 3939 .compatible = "lg,lp129qe", 3940 .data = &lg_lp129qe, 3941 }, { 3942 .compatible = "logicpd,type28", 3943 .data = &logicpd_type_28, 3944 }, { 3945 .compatible = "logictechno,lt161010-2nhc", 3946 .data = &logictechno_lt161010_2nh, 3947 }, { 3948 .compatible = "logictechno,lt161010-2nhr", 3949 .data = &logictechno_lt161010_2nh, 3950 }, { 3951 .compatible = "logictechno,lt170410-2whc", 3952 .data = &logictechno_lt170410_2whc, 3953 }, { 3954 .compatible = "mitsubishi,aa070mc01-ca1", 3955 .data = &mitsubishi_aa070mc01, 3956 }, { 3957 .compatible = "nec,nl12880bc20-05", 3958 .data = &nec_nl12880bc20_05, 3959 }, { 3960 .compatible = "nec,nl4827hc19-05b", 3961 .data = &nec_nl4827hc19_05b, 3962 }, { 3963 .compatible = "netron-dy,e231732", 3964 .data = &netron_dy_e231732, 3965 }, { 3966 .compatible = "neweast,wjfh116008a", 3967 .data = &neweast_wjfh116008a, 3968 }, { 3969 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 3970 .data = &newhaven_nhd_43_480272ef_atxl, 3971 }, { 3972 .compatible = "nlt,nl192108ac18-02d", 3973 .data = &nlt_nl192108ac18_02d, 3974 }, { 3975 .compatible = "nvd,9128", 3976 .data = &nvd_9128, 3977 }, { 3978 .compatible = "okaya,rs800480t-7x0gp", 3979 .data = &okaya_rs800480t_7x0gp, 3980 }, { 3981 .compatible = "olimex,lcd-olinuxino-43-ts", 3982 .data = &olimex_lcd_olinuxino_43ts, 3983 }, { 3984 .compatible = "ontat,yx700wv03", 3985 .data = &ontat_yx700wv03, 3986 }, { 3987 .compatible = "ortustech,com37h3m05dtc", 3988 .data = &ortustech_com37h3m, 3989 }, { 3990 .compatible = "ortustech,com37h3m99dtc", 3991 .data = &ortustech_com37h3m, 3992 }, { 3993 .compatible = "ortustech,com43h4m85ulc", 3994 .data = &ortustech_com43h4m85ulc, 3995 }, { 3996 .compatible = "osddisplays,osd070t1718-19ts", 3997 .data = &osddisplays_osd070t1718_19ts, 3998 }, { 3999 .compatible = "pda,91-00156-a0", 4000 .data = &pda_91_00156_a0, 4001 }, { 4002 .compatible = "qiaodian,qd43003c0-40", 4003 .data = &qd43003c0_40, 4004 }, { 4005 .compatible = "rocktech,rk070er9427", 4006 .data = &rocktech_rk070er9427, 4007 }, { 4008 .compatible = "rocktech,rk101ii01d-ct", 4009 .data = &rocktech_rk101ii01d_ct, 4010 }, { 4011 .compatible = "samsung,lsn122dl01-c01", 4012 .data = &samsung_lsn122dl01_c01, 4013 }, { 4014 .compatible = "samsung,ltn101nt05", 4015 .data = &samsung_ltn101nt05, 4016 }, { 4017 .compatible = "samsung,ltn140at29-301", 4018 .data = &samsung_ltn140at29_301, 4019 }, { 4020 .compatible = "satoz,sat050at40h12r2", 4021 .data = &satoz_sat050at40h12r2, 4022 }, { 4023 .compatible = "sharp,ld-d5116z01b", 4024 .data = &sharp_ld_d5116z01b, 4025 }, { 4026 .compatible = "sharp,lq035q7db03", 4027 .data = &sharp_lq035q7db03, 4028 }, { 4029 .compatible = "sharp,lq070y3dg3b", 4030 .data = &sharp_lq070y3dg3b, 4031 }, { 4032 .compatible = "sharp,lq101k1ly04", 4033 .data = &sharp_lq101k1ly04, 4034 }, { 4035 .compatible = "sharp,lq123p1jx31", 4036 .data = &sharp_lq123p1jx31, 4037 }, { 4038 .compatible = "sharp,ls020b1dd01d", 4039 .data = &sharp_ls020b1dd01d, 4040 }, { 4041 .compatible = "shelly,sca07010-bfn-lnn", 4042 .data = &shelly_sca07010_bfn_lnn, 4043 }, { 4044 .compatible = "starry,kr070pe2t", 4045 .data = &starry_kr070pe2t, 4046 }, { 4047 .compatible = "starry,kr122ea0sra", 4048 .data = &starry_kr122ea0sra, 4049 }, { 4050 .compatible = "tfc,s9700rtwv43tr-01b", 4051 .data = &tfc_s9700rtwv43tr_01b, 4052 }, { 4053 .compatible = "tianma,tm070jdhg30", 4054 .data = &tianma_tm070jdhg30, 4055 }, { 4056 .compatible = "tianma,tm070jvhg33", 4057 .data = &tianma_tm070jvhg33, 4058 }, { 4059 .compatible = "tianma,tm070rvhg71", 4060 .data = &tianma_tm070rvhg71, 4061 }, { 4062 .compatible = "ti,nspire-cx-lcd-panel", 4063 .data = &ti_nspire_cx_lcd_panel, 4064 }, { 4065 .compatible = "ti,nspire-classic-lcd-panel", 4066 .data = &ti_nspire_classic_lcd_panel, 4067 }, { 4068 .compatible = "toshiba,lt089ac29000", 4069 .data = &toshiba_lt089ac29000, 4070 }, { 4071 .compatible = "tpk,f07a-0102", 4072 .data = &tpk_f07a_0102, 4073 }, { 4074 .compatible = "tpk,f10a-0102", 4075 .data = &tpk_f10a_0102, 4076 }, { 4077 .compatible = "urt,umsh-8596md-t", 4078 .data = &urt_umsh_8596md_parallel, 4079 }, { 4080 .compatible = "urt,umsh-8596md-1t", 4081 .data = &urt_umsh_8596md_parallel, 4082 }, { 4083 .compatible = "urt,umsh-8596md-7t", 4084 .data = &urt_umsh_8596md_parallel, 4085 }, { 4086 .compatible = "urt,umsh-8596md-11t", 4087 .data = &urt_umsh_8596md_lvds, 4088 }, { 4089 .compatible = "urt,umsh-8596md-19t", 4090 .data = &urt_umsh_8596md_lvds, 4091 }, { 4092 .compatible = "urt,umsh-8596md-20t", 4093 .data = &urt_umsh_8596md_parallel, 4094 }, { 4095 .compatible = "vxt,vl050-8048nt-c01", 4096 .data = &vl050_8048nt_c01, 4097 }, { 4098 .compatible = "winstar,wf35ltiacd", 4099 .data = &winstar_wf35ltiacd, 4100 }, { 4101 /* Must be the last entry */ 4102 .compatible = "panel-dpi", 4103 .data = &panel_dpi, 4104 }, { 4105 /* sentinel */ 4106 } 4107 }; 4108 MODULE_DEVICE_TABLE(of, platform_of_match); 4109 4110 static int panel_simple_platform_probe(struct platform_device *pdev) 4111 { 4112 const struct of_device_id *id; 4113 4114 id = of_match_node(platform_of_match, pdev->dev.of_node); 4115 if (!id) 4116 return -ENODEV; 4117 4118 return panel_simple_probe(&pdev->dev, id->data); 4119 } 4120 4121 static int panel_simple_platform_remove(struct platform_device *pdev) 4122 { 4123 return panel_simple_remove(&pdev->dev); 4124 } 4125 4126 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4127 { 4128 panel_simple_shutdown(&pdev->dev); 4129 } 4130 4131 static struct platform_driver panel_simple_platform_driver = { 4132 .driver = { 4133 .name = "panel-simple", 4134 .of_match_table = platform_of_match, 4135 }, 4136 .probe = panel_simple_platform_probe, 4137 .remove = panel_simple_platform_remove, 4138 .shutdown = panel_simple_platform_shutdown, 4139 }; 4140 4141 struct panel_desc_dsi { 4142 struct panel_desc desc; 4143 4144 unsigned long flags; 4145 enum mipi_dsi_pixel_format format; 4146 unsigned int lanes; 4147 }; 4148 4149 static const struct drm_display_mode auo_b080uan01_mode = { 4150 .clock = 154500, 4151 .hdisplay = 1200, 4152 .hsync_start = 1200 + 62, 4153 .hsync_end = 1200 + 62 + 4, 4154 .htotal = 1200 + 62 + 4 + 62, 4155 .vdisplay = 1920, 4156 .vsync_start = 1920 + 9, 4157 .vsync_end = 1920 + 9 + 2, 4158 .vtotal = 1920 + 9 + 2 + 8, 4159 }; 4160 4161 static const struct panel_desc_dsi auo_b080uan01 = { 4162 .desc = { 4163 .modes = &auo_b080uan01_mode, 4164 .num_modes = 1, 4165 .bpc = 8, 4166 .size = { 4167 .width = 108, 4168 .height = 272, 4169 }, 4170 .connector_type = DRM_MODE_CONNECTOR_DSI, 4171 }, 4172 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4173 .format = MIPI_DSI_FMT_RGB888, 4174 .lanes = 4, 4175 }; 4176 4177 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4178 .clock = 160000, 4179 .hdisplay = 1200, 4180 .hsync_start = 1200 + 120, 4181 .hsync_end = 1200 + 120 + 20, 4182 .htotal = 1200 + 120 + 20 + 21, 4183 .vdisplay = 1920, 4184 .vsync_start = 1920 + 21, 4185 .vsync_end = 1920 + 21 + 3, 4186 .vtotal = 1920 + 21 + 3 + 18, 4187 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4188 }; 4189 4190 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4191 .desc = { 4192 .modes = &boe_tv080wum_nl0_mode, 4193 .num_modes = 1, 4194 .size = { 4195 .width = 107, 4196 .height = 172, 4197 }, 4198 .connector_type = DRM_MODE_CONNECTOR_DSI, 4199 }, 4200 .flags = MIPI_DSI_MODE_VIDEO | 4201 MIPI_DSI_MODE_VIDEO_BURST | 4202 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4203 .format = MIPI_DSI_FMT_RGB888, 4204 .lanes = 4, 4205 }; 4206 4207 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4208 .clock = 71000, 4209 .hdisplay = 800, 4210 .hsync_start = 800 + 32, 4211 .hsync_end = 800 + 32 + 1, 4212 .htotal = 800 + 32 + 1 + 57, 4213 .vdisplay = 1280, 4214 .vsync_start = 1280 + 28, 4215 .vsync_end = 1280 + 28 + 1, 4216 .vtotal = 1280 + 28 + 1 + 14, 4217 }; 4218 4219 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4220 .desc = { 4221 .modes = &lg_ld070wx3_sl01_mode, 4222 .num_modes = 1, 4223 .bpc = 8, 4224 .size = { 4225 .width = 94, 4226 .height = 151, 4227 }, 4228 .connector_type = DRM_MODE_CONNECTOR_DSI, 4229 }, 4230 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4231 .format = MIPI_DSI_FMT_RGB888, 4232 .lanes = 4, 4233 }; 4234 4235 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4236 .clock = 67000, 4237 .hdisplay = 720, 4238 .hsync_start = 720 + 12, 4239 .hsync_end = 720 + 12 + 4, 4240 .htotal = 720 + 12 + 4 + 112, 4241 .vdisplay = 1280, 4242 .vsync_start = 1280 + 8, 4243 .vsync_end = 1280 + 8 + 4, 4244 .vtotal = 1280 + 8 + 4 + 12, 4245 }; 4246 4247 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4248 .desc = { 4249 .modes = &lg_lh500wx1_sd03_mode, 4250 .num_modes = 1, 4251 .bpc = 8, 4252 .size = { 4253 .width = 62, 4254 .height = 110, 4255 }, 4256 .connector_type = DRM_MODE_CONNECTOR_DSI, 4257 }, 4258 .flags = MIPI_DSI_MODE_VIDEO, 4259 .format = MIPI_DSI_FMT_RGB888, 4260 .lanes = 4, 4261 }; 4262 4263 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4264 .clock = 157200, 4265 .hdisplay = 1920, 4266 .hsync_start = 1920 + 154, 4267 .hsync_end = 1920 + 154 + 16, 4268 .htotal = 1920 + 154 + 16 + 32, 4269 .vdisplay = 1200, 4270 .vsync_start = 1200 + 17, 4271 .vsync_end = 1200 + 17 + 2, 4272 .vtotal = 1200 + 17 + 2 + 16, 4273 }; 4274 4275 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4276 .desc = { 4277 .modes = &panasonic_vvx10f004b00_mode, 4278 .num_modes = 1, 4279 .bpc = 8, 4280 .size = { 4281 .width = 217, 4282 .height = 136, 4283 }, 4284 .connector_type = DRM_MODE_CONNECTOR_DSI, 4285 }, 4286 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4287 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4288 .format = MIPI_DSI_FMT_RGB888, 4289 .lanes = 4, 4290 }; 4291 4292 static const struct drm_display_mode lg_acx467akm_7_mode = { 4293 .clock = 150000, 4294 .hdisplay = 1080, 4295 .hsync_start = 1080 + 2, 4296 .hsync_end = 1080 + 2 + 2, 4297 .htotal = 1080 + 2 + 2 + 2, 4298 .vdisplay = 1920, 4299 .vsync_start = 1920 + 2, 4300 .vsync_end = 1920 + 2 + 2, 4301 .vtotal = 1920 + 2 + 2 + 2, 4302 }; 4303 4304 static const struct panel_desc_dsi lg_acx467akm_7 = { 4305 .desc = { 4306 .modes = &lg_acx467akm_7_mode, 4307 .num_modes = 1, 4308 .bpc = 8, 4309 .size = { 4310 .width = 62, 4311 .height = 110, 4312 }, 4313 .connector_type = DRM_MODE_CONNECTOR_DSI, 4314 }, 4315 .flags = 0, 4316 .format = MIPI_DSI_FMT_RGB888, 4317 .lanes = 4, 4318 }; 4319 4320 static const struct drm_display_mode osd101t2045_53ts_mode = { 4321 .clock = 154500, 4322 .hdisplay = 1920, 4323 .hsync_start = 1920 + 112, 4324 .hsync_end = 1920 + 112 + 16, 4325 .htotal = 1920 + 112 + 16 + 32, 4326 .vdisplay = 1200, 4327 .vsync_start = 1200 + 16, 4328 .vsync_end = 1200 + 16 + 2, 4329 .vtotal = 1200 + 16 + 2 + 16, 4330 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4331 }; 4332 4333 static const struct panel_desc_dsi osd101t2045_53ts = { 4334 .desc = { 4335 .modes = &osd101t2045_53ts_mode, 4336 .num_modes = 1, 4337 .bpc = 8, 4338 .size = { 4339 .width = 217, 4340 .height = 136, 4341 }, 4342 .connector_type = DRM_MODE_CONNECTOR_DSI, 4343 }, 4344 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4345 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4346 MIPI_DSI_MODE_EOT_PACKET, 4347 .format = MIPI_DSI_FMT_RGB888, 4348 .lanes = 4, 4349 }; 4350 4351 static const struct of_device_id dsi_of_match[] = { 4352 { 4353 .compatible = "auo,b080uan01", 4354 .data = &auo_b080uan01 4355 }, { 4356 .compatible = "boe,tv080wum-nl0", 4357 .data = &boe_tv080wum_nl0 4358 }, { 4359 .compatible = "lg,ld070wx3-sl01", 4360 .data = &lg_ld070wx3_sl01 4361 }, { 4362 .compatible = "lg,lh500wx1-sd03", 4363 .data = &lg_lh500wx1_sd03 4364 }, { 4365 .compatible = "panasonic,vvx10f004b00", 4366 .data = &panasonic_vvx10f004b00 4367 }, { 4368 .compatible = "lg,acx467akm-7", 4369 .data = &lg_acx467akm_7 4370 }, { 4371 .compatible = "osddisplays,osd101t2045-53ts", 4372 .data = &osd101t2045_53ts 4373 }, { 4374 /* sentinel */ 4375 } 4376 }; 4377 MODULE_DEVICE_TABLE(of, dsi_of_match); 4378 4379 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4380 { 4381 const struct panel_desc_dsi *desc; 4382 const struct of_device_id *id; 4383 int err; 4384 4385 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4386 if (!id) 4387 return -ENODEV; 4388 4389 desc = id->data; 4390 4391 err = panel_simple_probe(&dsi->dev, &desc->desc); 4392 if (err < 0) 4393 return err; 4394 4395 dsi->mode_flags = desc->flags; 4396 dsi->format = desc->format; 4397 dsi->lanes = desc->lanes; 4398 4399 err = mipi_dsi_attach(dsi); 4400 if (err) { 4401 struct panel_simple *panel = dev_get_drvdata(&dsi->dev); 4402 4403 drm_panel_remove(&panel->base); 4404 } 4405 4406 return err; 4407 } 4408 4409 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4410 { 4411 int err; 4412 4413 err = mipi_dsi_detach(dsi); 4414 if (err < 0) 4415 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4416 4417 return panel_simple_remove(&dsi->dev); 4418 } 4419 4420 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4421 { 4422 panel_simple_shutdown(&dsi->dev); 4423 } 4424 4425 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4426 .driver = { 4427 .name = "panel-simple-dsi", 4428 .of_match_table = dsi_of_match, 4429 }, 4430 .probe = panel_simple_dsi_probe, 4431 .remove = panel_simple_dsi_remove, 4432 .shutdown = panel_simple_dsi_shutdown, 4433 }; 4434 4435 static int __init panel_simple_init(void) 4436 { 4437 int err; 4438 4439 err = platform_driver_register(&panel_simple_platform_driver); 4440 if (err < 0) 4441 return err; 4442 4443 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4444 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4445 if (err < 0) 4446 return err; 4447 } 4448 4449 return 0; 4450 } 4451 module_init(panel_simple_init); 4452 4453 static void __exit panel_simple_exit(void) 4454 { 4455 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4456 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4457 4458 platform_driver_unregister(&panel_simple_platform_driver); 4459 } 4460 module_exit(panel_simple_exit); 4461 4462 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4463 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4464 MODULE_LICENSE("GPL and additional rights"); 4465