1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/iopoll.h> 27 #include <linux/module.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/regulator/consumer.h> 32 33 #include <video/display_timing.h> 34 #include <video/of_display_timing.h> 35 #include <video/videomode.h> 36 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_device.h> 39 #include <drm/drm_dp_aux_bus.h> 40 #include <drm/drm_dp_helper.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 44 /** 45 * struct panel_desc - Describes a simple panel. 46 */ 47 struct panel_desc { 48 /** 49 * @modes: Pointer to array of fixed modes appropriate for this panel. 50 * 51 * If only one mode then this can just be the address of the mode. 52 * NOTE: cannot be used with "timings" and also if this is specified 53 * then you cannot override the mode in the device tree. 54 */ 55 const struct drm_display_mode *modes; 56 57 /** @num_modes: Number of elements in modes array. */ 58 unsigned int num_modes; 59 60 /** 61 * @timings: Pointer to array of display timings 62 * 63 * NOTE: cannot be used with "modes" and also these will be used to 64 * validate a device tree override if one is present. 65 */ 66 const struct display_timing *timings; 67 68 /** @num_timings: Number of elements in timings array. */ 69 unsigned int num_timings; 70 71 /** @bpc: Bits per color. */ 72 unsigned int bpc; 73 74 /** @size: Structure containing the physical size of this panel. */ 75 struct { 76 /** 77 * @size.width: Width (in mm) of the active display area. 78 */ 79 unsigned int width; 80 81 /** 82 * @size.height: Height (in mm) of the active display area. 83 */ 84 unsigned int height; 85 } size; 86 87 /** @delay: Structure containing various delay values for this panel. */ 88 struct { 89 /** 90 * @delay.prepare: Time for the panel to become ready. 91 * 92 * The time (in milliseconds) that it takes for the panel to 93 * become ready and start receiving video data 94 */ 95 unsigned int prepare; 96 97 /** 98 * @delay.hpd_absent_delay: Time to wait if HPD isn't hooked up. 99 * 100 * Add this to the prepare delay if we know Hot Plug Detect 101 * isn't used. 102 */ 103 unsigned int hpd_absent_delay; 104 105 /** 106 * @delay.prepare_to_enable: Time between prepare and enable. 107 * 108 * The minimum time, in milliseconds, that needs to have passed 109 * between when prepare finished and enable may begin. If at 110 * enable time less time has passed since prepare finished, 111 * the driver waits for the remaining time. 112 * 113 * If a fixed enable delay is also specified, we'll start 114 * counting before delaying for the fixed delay. 115 * 116 * If a fixed prepare delay is also specified, we won't start 117 * counting until after the fixed delay. We can't overlap this 118 * fixed delay with the min time because the fixed delay 119 * doesn't happen at the end of the function if a HPD GPIO was 120 * specified. 121 * 122 * In other words: 123 * prepare() 124 * ... 125 * // do fixed prepare delay 126 * // wait for HPD GPIO if applicable 127 * // start counting for prepare_to_enable 128 * 129 * enable() 130 * // do fixed enable delay 131 * // enforce prepare_to_enable min time 132 */ 133 unsigned int prepare_to_enable; 134 135 /** 136 * @delay.power_to_enable: Time for the power to enable the display on. 137 * 138 * The time (in milliseconds) to wait after powering up the display 139 * before asserting its enable pin. 140 */ 141 unsigned int power_to_enable; 142 143 /** 144 * @delay.disable_to_power_off: Time for the disable to power the display off. 145 * 146 * The time (in milliseconds) to wait before powering off the display 147 * after deasserting its enable pin. 148 */ 149 unsigned int disable_to_power_off; 150 151 /** 152 * @delay.enable: Time for the panel to display a valid frame. 153 * 154 * The time (in milliseconds) that it takes for the panel to 155 * display the first valid frame after starting to receive 156 * video data. 157 */ 158 unsigned int enable; 159 160 /** 161 * @delay.disable: Time for the panel to turn the display off. 162 * 163 * The time (in milliseconds) that it takes for the panel to 164 * turn the display off (no content is visible). 165 */ 166 unsigned int disable; 167 168 /** 169 * @delay.unprepare: Time to power down completely. 170 * 171 * The time (in milliseconds) that it takes for the panel 172 * to power itself down completely. 173 * 174 * This time is used to prevent a future "prepare" from 175 * starting until at least this many milliseconds has passed. 176 * If at prepare time less time has passed since unprepare 177 * finished, the driver waits for the remaining time. 178 */ 179 unsigned int unprepare; 180 } delay; 181 182 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 183 u32 bus_format; 184 185 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 186 u32 bus_flags; 187 188 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 189 int connector_type; 190 }; 191 192 struct panel_simple { 193 struct drm_panel base; 194 bool enabled; 195 bool no_hpd; 196 197 bool prepared; 198 199 ktime_t prepared_time; 200 ktime_t unprepared_time; 201 202 const struct panel_desc *desc; 203 204 struct regulator *supply; 205 struct i2c_adapter *ddc; 206 struct drm_dp_aux *aux; 207 208 struct gpio_desc *enable_gpio; 209 struct gpio_desc *hpd_gpio; 210 211 struct edid *edid; 212 213 struct drm_display_mode override_mode; 214 215 enum drm_panel_orientation orientation; 216 }; 217 218 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 219 { 220 return container_of(panel, struct panel_simple, base); 221 } 222 223 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 224 struct drm_connector *connector) 225 { 226 struct drm_display_mode *mode; 227 unsigned int i, num = 0; 228 229 for (i = 0; i < panel->desc->num_timings; i++) { 230 const struct display_timing *dt = &panel->desc->timings[i]; 231 struct videomode vm; 232 233 videomode_from_timing(dt, &vm); 234 mode = drm_mode_create(connector->dev); 235 if (!mode) { 236 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 237 dt->hactive.typ, dt->vactive.typ); 238 continue; 239 } 240 241 drm_display_mode_from_videomode(&vm, mode); 242 243 mode->type |= DRM_MODE_TYPE_DRIVER; 244 245 if (panel->desc->num_timings == 1) 246 mode->type |= DRM_MODE_TYPE_PREFERRED; 247 248 drm_mode_probed_add(connector, mode); 249 num++; 250 } 251 252 return num; 253 } 254 255 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 256 struct drm_connector *connector) 257 { 258 struct drm_display_mode *mode; 259 unsigned int i, num = 0; 260 261 for (i = 0; i < panel->desc->num_modes; i++) { 262 const struct drm_display_mode *m = &panel->desc->modes[i]; 263 264 mode = drm_mode_duplicate(connector->dev, m); 265 if (!mode) { 266 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 267 m->hdisplay, m->vdisplay, 268 drm_mode_vrefresh(m)); 269 continue; 270 } 271 272 mode->type |= DRM_MODE_TYPE_DRIVER; 273 274 if (panel->desc->num_modes == 1) 275 mode->type |= DRM_MODE_TYPE_PREFERRED; 276 277 drm_mode_set_name(mode); 278 279 drm_mode_probed_add(connector, mode); 280 num++; 281 } 282 283 return num; 284 } 285 286 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 287 struct drm_connector *connector) 288 { 289 struct drm_display_mode *mode; 290 bool has_override = panel->override_mode.type; 291 unsigned int num = 0; 292 293 if (!panel->desc) 294 return 0; 295 296 if (has_override) { 297 mode = drm_mode_duplicate(connector->dev, 298 &panel->override_mode); 299 if (mode) { 300 drm_mode_probed_add(connector, mode); 301 num = 1; 302 } else { 303 dev_err(panel->base.dev, "failed to add override mode\n"); 304 } 305 } 306 307 /* Only add timings if override was not there or failed to validate */ 308 if (num == 0 && panel->desc->num_timings) 309 num = panel_simple_get_timings_modes(panel, connector); 310 311 /* 312 * Only add fixed modes if timings/override added no mode. 313 * 314 * We should only ever have either the display timings specified 315 * or a fixed mode. Anything else is rather bogus. 316 */ 317 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 318 if (num == 0) 319 num = panel_simple_get_display_modes(panel, connector); 320 321 connector->display_info.bpc = panel->desc->bpc; 322 connector->display_info.width_mm = panel->desc->size.width; 323 connector->display_info.height_mm = panel->desc->size.height; 324 if (panel->desc->bus_format) 325 drm_display_info_set_bus_formats(&connector->display_info, 326 &panel->desc->bus_format, 1); 327 connector->display_info.bus_flags = panel->desc->bus_flags; 328 329 return num; 330 } 331 332 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 333 { 334 ktime_t now_ktime, min_ktime; 335 336 if (!min_ms) 337 return; 338 339 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 340 now_ktime = ktime_get(); 341 342 if (ktime_before(now_ktime, min_ktime)) 343 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 344 } 345 346 static int panel_simple_disable(struct drm_panel *panel) 347 { 348 struct panel_simple *p = to_panel_simple(panel); 349 350 if (!p->enabled) 351 return 0; 352 353 if (p->desc->delay.disable) 354 msleep(p->desc->delay.disable); 355 356 p->enabled = false; 357 358 return 0; 359 } 360 361 static int panel_simple_suspend(struct device *dev) 362 { 363 struct panel_simple *p = dev_get_drvdata(dev); 364 365 gpiod_set_value_cansleep(p->enable_gpio, 0); 366 367 if (p->desc->delay.disable_to_power_off) 368 msleep(p->desc->delay.disable_to_power_off); 369 370 regulator_disable(p->supply); 371 p->unprepared_time = ktime_get(); 372 373 kfree(p->edid); 374 p->edid = NULL; 375 376 return 0; 377 } 378 379 static int panel_simple_unprepare(struct drm_panel *panel) 380 { 381 struct panel_simple *p = to_panel_simple(panel); 382 int ret; 383 384 /* Unpreparing when already unprepared is a no-op */ 385 if (!p->prepared) 386 return 0; 387 388 pm_runtime_mark_last_busy(panel->dev); 389 ret = pm_runtime_put_autosuspend(panel->dev); 390 if (ret < 0) 391 return ret; 392 p->prepared = false; 393 394 return 0; 395 } 396 397 static int panel_simple_get_hpd_gpio(struct device *dev, struct panel_simple *p) 398 { 399 int err; 400 401 p->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 402 if (IS_ERR(p->hpd_gpio)) { 403 err = PTR_ERR(p->hpd_gpio); 404 405 if (err != -EPROBE_DEFER) 406 dev_err(dev, "failed to get 'hpd' GPIO: %d\n", err); 407 408 return err; 409 } 410 411 return 0; 412 } 413 414 static int panel_simple_prepare_once(struct panel_simple *p) 415 { 416 struct device *dev = p->base.dev; 417 unsigned int delay; 418 int err; 419 int hpd_asserted; 420 unsigned long hpd_wait_us; 421 422 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 423 424 err = regulator_enable(p->supply); 425 if (err < 0) { 426 dev_err(dev, "failed to enable supply: %d\n", err); 427 return err; 428 } 429 430 if (p->desc->delay.power_to_enable) 431 msleep(p->desc->delay.power_to_enable); 432 433 gpiod_set_value_cansleep(p->enable_gpio, 1); 434 435 delay = p->desc->delay.prepare; 436 if (p->no_hpd) 437 delay += p->desc->delay.hpd_absent_delay; 438 if (delay) 439 msleep(delay); 440 441 if (p->hpd_gpio) { 442 if (p->desc->delay.hpd_absent_delay) 443 hpd_wait_us = p->desc->delay.hpd_absent_delay * 1000UL; 444 else 445 hpd_wait_us = 2000000; 446 447 err = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, 448 hpd_asserted, hpd_asserted, 449 1000, hpd_wait_us); 450 if (hpd_asserted < 0) 451 err = hpd_asserted; 452 453 if (err) { 454 if (err != -ETIMEDOUT) 455 dev_err(dev, 456 "error waiting for hpd GPIO: %d\n", err); 457 goto error; 458 } 459 } 460 461 p->prepared_time = ktime_get(); 462 463 return 0; 464 465 error: 466 gpiod_set_value_cansleep(p->enable_gpio, 0); 467 regulator_disable(p->supply); 468 p->unprepared_time = ktime_get(); 469 470 return err; 471 } 472 473 /* 474 * Some panels simply don't always come up and need to be power cycled to 475 * work properly. We'll allow for a handful of retries. 476 */ 477 #define MAX_PANEL_PREPARE_TRIES 5 478 479 static int panel_simple_resume(struct device *dev) 480 { 481 struct panel_simple *p = dev_get_drvdata(dev); 482 int ret; 483 int try; 484 485 for (try = 0; try < MAX_PANEL_PREPARE_TRIES; try++) { 486 ret = panel_simple_prepare_once(p); 487 if (ret != -ETIMEDOUT) 488 break; 489 } 490 491 if (ret == -ETIMEDOUT) 492 dev_err(dev, "Prepare timeout after %d tries\n", try); 493 else if (try) 494 dev_warn(dev, "Prepare needed %d retries\n", try); 495 496 return ret; 497 } 498 499 static int panel_simple_prepare(struct drm_panel *panel) 500 { 501 struct panel_simple *p = to_panel_simple(panel); 502 int ret; 503 504 /* Preparing when already prepared is a no-op */ 505 if (p->prepared) 506 return 0; 507 508 ret = pm_runtime_get_sync(panel->dev); 509 if (ret < 0) { 510 pm_runtime_put_autosuspend(panel->dev); 511 return ret; 512 } 513 514 p->prepared = true; 515 516 return 0; 517 } 518 519 static int panel_simple_enable(struct drm_panel *panel) 520 { 521 struct panel_simple *p = to_panel_simple(panel); 522 523 if (p->enabled) 524 return 0; 525 526 if (p->desc->delay.enable) 527 msleep(p->desc->delay.enable); 528 529 panel_simple_wait(p->prepared_time, p->desc->delay.prepare_to_enable); 530 531 p->enabled = true; 532 533 return 0; 534 } 535 536 static int panel_simple_get_modes(struct drm_panel *panel, 537 struct drm_connector *connector) 538 { 539 struct panel_simple *p = to_panel_simple(panel); 540 int num = 0; 541 542 /* probe EDID if a DDC bus is available */ 543 if (p->ddc) { 544 pm_runtime_get_sync(panel->dev); 545 546 if (!p->edid) 547 p->edid = drm_get_edid(connector, p->ddc); 548 549 if (p->edid) 550 num += drm_add_edid_modes(connector, p->edid); 551 552 pm_runtime_mark_last_busy(panel->dev); 553 pm_runtime_put_autosuspend(panel->dev); 554 } 555 556 /* add hard-coded panel modes */ 557 num += panel_simple_get_non_edid_modes(p, connector); 558 559 /* set up connector's "panel orientation" property */ 560 drm_connector_set_panel_orientation(connector, p->orientation); 561 562 return num; 563 } 564 565 static int panel_simple_get_timings(struct drm_panel *panel, 566 unsigned int num_timings, 567 struct display_timing *timings) 568 { 569 struct panel_simple *p = to_panel_simple(panel); 570 unsigned int i; 571 572 if (p->desc->num_timings < num_timings) 573 num_timings = p->desc->num_timings; 574 575 if (timings) 576 for (i = 0; i < num_timings; i++) 577 timings[i] = p->desc->timings[i]; 578 579 return p->desc->num_timings; 580 } 581 582 static const struct drm_panel_funcs panel_simple_funcs = { 583 .disable = panel_simple_disable, 584 .unprepare = panel_simple_unprepare, 585 .prepare = panel_simple_prepare, 586 .enable = panel_simple_enable, 587 .get_modes = panel_simple_get_modes, 588 .get_timings = panel_simple_get_timings, 589 }; 590 591 static struct panel_desc panel_dpi; 592 593 static int panel_dpi_probe(struct device *dev, 594 struct panel_simple *panel) 595 { 596 struct display_timing *timing; 597 const struct device_node *np; 598 struct panel_desc *desc; 599 unsigned int bus_flags; 600 struct videomode vm; 601 int ret; 602 603 np = dev->of_node; 604 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 605 if (!desc) 606 return -ENOMEM; 607 608 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 609 if (!timing) 610 return -ENOMEM; 611 612 ret = of_get_display_timing(np, "panel-timing", timing); 613 if (ret < 0) { 614 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 615 np); 616 return ret; 617 } 618 619 desc->timings = timing; 620 desc->num_timings = 1; 621 622 of_property_read_u32(np, "width-mm", &desc->size.width); 623 of_property_read_u32(np, "height-mm", &desc->size.height); 624 625 /* Extract bus_flags from display_timing */ 626 bus_flags = 0; 627 vm.flags = timing->flags; 628 drm_bus_flags_from_videomode(&vm, &bus_flags); 629 desc->bus_flags = bus_flags; 630 631 /* We do not know the connector for the DT node, so guess it */ 632 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 633 634 panel->desc = desc; 635 636 return 0; 637 } 638 639 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 640 (to_check->field.typ >= bounds->field.min && \ 641 to_check->field.typ <= bounds->field.max) 642 static void panel_simple_parse_panel_timing_node(struct device *dev, 643 struct panel_simple *panel, 644 const struct display_timing *ot) 645 { 646 const struct panel_desc *desc = panel->desc; 647 struct videomode vm; 648 unsigned int i; 649 650 if (WARN_ON(desc->num_modes)) { 651 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 652 return; 653 } 654 if (WARN_ON(!desc->num_timings)) { 655 dev_err(dev, "Reject override mode: no timings specified\n"); 656 return; 657 } 658 659 for (i = 0; i < panel->desc->num_timings; i++) { 660 const struct display_timing *dt = &panel->desc->timings[i]; 661 662 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 663 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 664 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 665 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 666 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 667 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 668 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 669 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 670 continue; 671 672 if (ot->flags != dt->flags) 673 continue; 674 675 videomode_from_timing(ot, &vm); 676 drm_display_mode_from_videomode(&vm, &panel->override_mode); 677 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 678 DRM_MODE_TYPE_PREFERRED; 679 break; 680 } 681 682 if (WARN_ON(!panel->override_mode.type)) 683 dev_err(dev, "Reject override mode: No display_timing found\n"); 684 } 685 686 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc, 687 struct drm_dp_aux *aux) 688 { 689 struct panel_simple *panel; 690 struct display_timing dt; 691 struct device_node *ddc; 692 int connector_type; 693 u32 bus_flags; 694 int err; 695 696 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 697 if (!panel) 698 return -ENOMEM; 699 700 panel->enabled = false; 701 panel->prepared_time = 0; 702 panel->desc = desc; 703 panel->aux = aux; 704 705 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd"); 706 if (!panel->no_hpd) { 707 err = panel_simple_get_hpd_gpio(dev, panel); 708 if (err) 709 return err; 710 } 711 712 panel->supply = devm_regulator_get(dev, "power"); 713 if (IS_ERR(panel->supply)) 714 return PTR_ERR(panel->supply); 715 716 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 717 GPIOD_OUT_LOW); 718 if (IS_ERR(panel->enable_gpio)) { 719 err = PTR_ERR(panel->enable_gpio); 720 if (err != -EPROBE_DEFER) 721 dev_err(dev, "failed to request GPIO: %d\n", err); 722 return err; 723 } 724 725 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 726 if (err) { 727 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 728 return err; 729 } 730 731 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 732 if (ddc) { 733 panel->ddc = of_find_i2c_adapter_by_node(ddc); 734 of_node_put(ddc); 735 736 if (!panel->ddc) 737 return -EPROBE_DEFER; 738 } else if (aux) { 739 panel->ddc = &aux->ddc; 740 } 741 742 if (desc == &panel_dpi) { 743 /* Handle the generic panel-dpi binding */ 744 err = panel_dpi_probe(dev, panel); 745 if (err) 746 goto free_ddc; 747 } else { 748 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 749 panel_simple_parse_panel_timing_node(dev, panel, &dt); 750 } 751 752 connector_type = desc->connector_type; 753 /* Catch common mistakes for panels. */ 754 switch (connector_type) { 755 case 0: 756 dev_warn(dev, "Specify missing connector_type\n"); 757 connector_type = DRM_MODE_CONNECTOR_DPI; 758 break; 759 case DRM_MODE_CONNECTOR_LVDS: 760 WARN_ON(desc->bus_flags & 761 ~(DRM_BUS_FLAG_DE_LOW | 762 DRM_BUS_FLAG_DE_HIGH | 763 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 764 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 765 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 766 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 767 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 768 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 769 desc->bpc != 6); 770 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 771 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 772 desc->bpc != 8); 773 break; 774 case DRM_MODE_CONNECTOR_eDP: 775 if (desc->bpc != 6 && desc->bpc != 8 && desc->bpc != 10) 776 dev_warn(dev, "Expected bpc in {6,8,10} but got: %u\n", desc->bpc); 777 break; 778 case DRM_MODE_CONNECTOR_DSI: 779 if (desc->bpc != 6 && desc->bpc != 8) 780 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 781 break; 782 case DRM_MODE_CONNECTOR_DPI: 783 bus_flags = DRM_BUS_FLAG_DE_LOW | 784 DRM_BUS_FLAG_DE_HIGH | 785 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 786 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 787 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 788 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 789 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 790 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 791 if (desc->bus_flags & ~bus_flags) 792 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 793 if (!(desc->bus_flags & bus_flags)) 794 dev_warn(dev, "Specify missing bus_flags\n"); 795 if (desc->bus_format == 0) 796 dev_warn(dev, "Specify missing bus_format\n"); 797 if (desc->bpc != 6 && desc->bpc != 8) 798 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 799 break; 800 default: 801 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 802 connector_type = DRM_MODE_CONNECTOR_DPI; 803 break; 804 } 805 806 if (!panel->enable_gpio && desc->delay.disable_to_power_off) 807 dev_warn(dev, "Need a delay after disabling panel GPIO, but a GPIO wasn't provided\n"); 808 if (!panel->enable_gpio && desc->delay.power_to_enable) 809 dev_warn(dev, "Need a delay before enabling panel GPIO, but a GPIO wasn't provided\n"); 810 811 dev_set_drvdata(dev, panel); 812 813 /* 814 * We use runtime PM for prepare / unprepare since those power the panel 815 * on and off and those can be very slow operations. This is important 816 * to optimize powering the panel on briefly to read the EDID before 817 * fully enabling the panel. 818 */ 819 pm_runtime_enable(dev); 820 pm_runtime_set_autosuspend_delay(dev, 1000); 821 pm_runtime_use_autosuspend(dev); 822 823 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 824 825 err = drm_panel_of_backlight(&panel->base); 826 if (err) 827 goto disable_pm_runtime; 828 829 if (!panel->base.backlight && panel->aux) { 830 pm_runtime_get_sync(dev); 831 err = drm_panel_dp_aux_backlight(&panel->base, panel->aux); 832 pm_runtime_mark_last_busy(dev); 833 pm_runtime_put_autosuspend(dev); 834 if (err) 835 goto disable_pm_runtime; 836 } 837 838 drm_panel_add(&panel->base); 839 840 return 0; 841 842 disable_pm_runtime: 843 pm_runtime_dont_use_autosuspend(dev); 844 pm_runtime_disable(dev); 845 free_ddc: 846 if (panel->ddc && (!panel->aux || panel->ddc != &panel->aux->ddc)) 847 put_device(&panel->ddc->dev); 848 849 return err; 850 } 851 852 static int panel_simple_remove(struct device *dev) 853 { 854 struct panel_simple *panel = dev_get_drvdata(dev); 855 856 drm_panel_remove(&panel->base); 857 drm_panel_disable(&panel->base); 858 drm_panel_unprepare(&panel->base); 859 860 pm_runtime_dont_use_autosuspend(dev); 861 pm_runtime_disable(dev); 862 if (panel->ddc && (!panel->aux || panel->ddc != &panel->aux->ddc)) 863 put_device(&panel->ddc->dev); 864 865 return 0; 866 } 867 868 static void panel_simple_shutdown(struct device *dev) 869 { 870 struct panel_simple *panel = dev_get_drvdata(dev); 871 872 drm_panel_disable(&panel->base); 873 drm_panel_unprepare(&panel->base); 874 } 875 876 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 877 .clock = 71100, 878 .hdisplay = 1280, 879 .hsync_start = 1280 + 40, 880 .hsync_end = 1280 + 40 + 80, 881 .htotal = 1280 + 40 + 80 + 40, 882 .vdisplay = 800, 883 .vsync_start = 800 + 3, 884 .vsync_end = 800 + 3 + 10, 885 .vtotal = 800 + 3 + 10 + 10, 886 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 887 }; 888 889 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 890 .modes = &ire_am_1280800n3tzqw_t00h_mode, 891 .num_modes = 1, 892 .bpc = 6, 893 .size = { 894 .width = 217, 895 .height = 136, 896 }, 897 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 898 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 899 .connector_type = DRM_MODE_CONNECTOR_LVDS, 900 }; 901 902 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 903 .clock = 9000, 904 .hdisplay = 480, 905 .hsync_start = 480 + 2, 906 .hsync_end = 480 + 2 + 41, 907 .htotal = 480 + 2 + 41 + 2, 908 .vdisplay = 272, 909 .vsync_start = 272 + 2, 910 .vsync_end = 272 + 2 + 10, 911 .vtotal = 272 + 2 + 10 + 2, 912 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 913 }; 914 915 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 916 .modes = &ire_am_480272h3tmqw_t01h_mode, 917 .num_modes = 1, 918 .bpc = 8, 919 .size = { 920 .width = 105, 921 .height = 67, 922 }, 923 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 924 }; 925 926 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 927 .clock = 33333, 928 .hdisplay = 800, 929 .hsync_start = 800 + 0, 930 .hsync_end = 800 + 0 + 255, 931 .htotal = 800 + 0 + 255 + 0, 932 .vdisplay = 480, 933 .vsync_start = 480 + 2, 934 .vsync_end = 480 + 2 + 45, 935 .vtotal = 480 + 2 + 45 + 0, 936 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 937 }; 938 939 static const struct panel_desc ampire_am800480r3tmqwa1h = { 940 .modes = &ire_am800480r3tmqwa1h_mode, 941 .num_modes = 1, 942 .bpc = 6, 943 .size = { 944 .width = 152, 945 .height = 91, 946 }, 947 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 948 }; 949 950 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 951 .pixelclock = { 26400000, 33300000, 46800000 }, 952 .hactive = { 800, 800, 800 }, 953 .hfront_porch = { 16, 210, 354 }, 954 .hback_porch = { 45, 36, 6 }, 955 .hsync_len = { 1, 10, 40 }, 956 .vactive = { 480, 480, 480 }, 957 .vfront_porch = { 7, 22, 147 }, 958 .vback_porch = { 22, 13, 3 }, 959 .vsync_len = { 1, 10, 20 }, 960 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 961 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 962 }; 963 964 static const struct panel_desc armadeus_st0700_adapt = { 965 .timings = &santek_st0700i5y_rbslw_f_timing, 966 .num_timings = 1, 967 .bpc = 6, 968 .size = { 969 .width = 154, 970 .height = 86, 971 }, 972 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 973 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 974 }; 975 976 static const struct drm_display_mode auo_b101aw03_mode = { 977 .clock = 51450, 978 .hdisplay = 1024, 979 .hsync_start = 1024 + 156, 980 .hsync_end = 1024 + 156 + 8, 981 .htotal = 1024 + 156 + 8 + 156, 982 .vdisplay = 600, 983 .vsync_start = 600 + 16, 984 .vsync_end = 600 + 16 + 6, 985 .vtotal = 600 + 16 + 6 + 16, 986 }; 987 988 static const struct panel_desc auo_b101aw03 = { 989 .modes = &auo_b101aw03_mode, 990 .num_modes = 1, 991 .bpc = 6, 992 .size = { 993 .width = 223, 994 .height = 125, 995 }, 996 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 997 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 998 .connector_type = DRM_MODE_CONNECTOR_LVDS, 999 }; 1000 1001 static const struct display_timing auo_b101ean01_timing = { 1002 .pixelclock = { 65300000, 72500000, 75000000 }, 1003 .hactive = { 1280, 1280, 1280 }, 1004 .hfront_porch = { 18, 119, 119 }, 1005 .hback_porch = { 21, 21, 21 }, 1006 .hsync_len = { 32, 32, 32 }, 1007 .vactive = { 800, 800, 800 }, 1008 .vfront_porch = { 4, 4, 4 }, 1009 .vback_porch = { 8, 8, 8 }, 1010 .vsync_len = { 18, 20, 20 }, 1011 }; 1012 1013 static const struct panel_desc auo_b101ean01 = { 1014 .timings = &auo_b101ean01_timing, 1015 .num_timings = 1, 1016 .bpc = 6, 1017 .size = { 1018 .width = 217, 1019 .height = 136, 1020 }, 1021 }; 1022 1023 static const struct drm_display_mode auo_b101xtn01_mode = { 1024 .clock = 72000, 1025 .hdisplay = 1366, 1026 .hsync_start = 1366 + 20, 1027 .hsync_end = 1366 + 20 + 70, 1028 .htotal = 1366 + 20 + 70, 1029 .vdisplay = 768, 1030 .vsync_start = 768 + 14, 1031 .vsync_end = 768 + 14 + 42, 1032 .vtotal = 768 + 14 + 42, 1033 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1034 }; 1035 1036 static const struct panel_desc auo_b101xtn01 = { 1037 .modes = &auo_b101xtn01_mode, 1038 .num_modes = 1, 1039 .bpc = 6, 1040 .size = { 1041 .width = 223, 1042 .height = 125, 1043 }, 1044 }; 1045 1046 static const struct drm_display_mode auo_b116xak01_mode = { 1047 .clock = 69300, 1048 .hdisplay = 1366, 1049 .hsync_start = 1366 + 48, 1050 .hsync_end = 1366 + 48 + 32, 1051 .htotal = 1366 + 48 + 32 + 10, 1052 .vdisplay = 768, 1053 .vsync_start = 768 + 4, 1054 .vsync_end = 768 + 4 + 6, 1055 .vtotal = 768 + 4 + 6 + 15, 1056 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1057 }; 1058 1059 static const struct panel_desc auo_b116xak01 = { 1060 .modes = &auo_b116xak01_mode, 1061 .num_modes = 1, 1062 .bpc = 6, 1063 .size = { 1064 .width = 256, 1065 .height = 144, 1066 }, 1067 .delay = { 1068 .hpd_absent_delay = 200, 1069 }, 1070 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1071 .connector_type = DRM_MODE_CONNECTOR_eDP, 1072 }; 1073 1074 static const struct drm_display_mode auo_b116xw03_mode = { 1075 .clock = 70589, 1076 .hdisplay = 1366, 1077 .hsync_start = 1366 + 40, 1078 .hsync_end = 1366 + 40 + 40, 1079 .htotal = 1366 + 40 + 40 + 32, 1080 .vdisplay = 768, 1081 .vsync_start = 768 + 10, 1082 .vsync_end = 768 + 10 + 12, 1083 .vtotal = 768 + 10 + 12 + 6, 1084 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1085 }; 1086 1087 static const struct panel_desc auo_b116xw03 = { 1088 .modes = &auo_b116xw03_mode, 1089 .num_modes = 1, 1090 .bpc = 6, 1091 .size = { 1092 .width = 256, 1093 .height = 144, 1094 }, 1095 .delay = { 1096 .enable = 400, 1097 }, 1098 .bus_flags = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 1099 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1100 .connector_type = DRM_MODE_CONNECTOR_eDP, 1101 }; 1102 1103 static const struct drm_display_mode auo_b133xtn01_mode = { 1104 .clock = 69500, 1105 .hdisplay = 1366, 1106 .hsync_start = 1366 + 48, 1107 .hsync_end = 1366 + 48 + 32, 1108 .htotal = 1366 + 48 + 32 + 20, 1109 .vdisplay = 768, 1110 .vsync_start = 768 + 3, 1111 .vsync_end = 768 + 3 + 6, 1112 .vtotal = 768 + 3 + 6 + 13, 1113 }; 1114 1115 static const struct panel_desc auo_b133xtn01 = { 1116 .modes = &auo_b133xtn01_mode, 1117 .num_modes = 1, 1118 .bpc = 6, 1119 .size = { 1120 .width = 293, 1121 .height = 165, 1122 }, 1123 }; 1124 1125 static const struct drm_display_mode auo_b133htn01_mode = { 1126 .clock = 150660, 1127 .hdisplay = 1920, 1128 .hsync_start = 1920 + 172, 1129 .hsync_end = 1920 + 172 + 80, 1130 .htotal = 1920 + 172 + 80 + 60, 1131 .vdisplay = 1080, 1132 .vsync_start = 1080 + 25, 1133 .vsync_end = 1080 + 25 + 10, 1134 .vtotal = 1080 + 25 + 10 + 10, 1135 }; 1136 1137 static const struct panel_desc auo_b133htn01 = { 1138 .modes = &auo_b133htn01_mode, 1139 .num_modes = 1, 1140 .bpc = 6, 1141 .size = { 1142 .width = 293, 1143 .height = 165, 1144 }, 1145 .delay = { 1146 .prepare = 105, 1147 .enable = 20, 1148 .unprepare = 50, 1149 }, 1150 }; 1151 1152 static const struct display_timing auo_g070vvn01_timings = { 1153 .pixelclock = { 33300000, 34209000, 45000000 }, 1154 .hactive = { 800, 800, 800 }, 1155 .hfront_porch = { 20, 40, 200 }, 1156 .hback_porch = { 87, 40, 1 }, 1157 .hsync_len = { 1, 48, 87 }, 1158 .vactive = { 480, 480, 480 }, 1159 .vfront_porch = { 5, 13, 200 }, 1160 .vback_porch = { 31, 31, 29 }, 1161 .vsync_len = { 1, 1, 3 }, 1162 }; 1163 1164 static const struct panel_desc auo_g070vvn01 = { 1165 .timings = &auo_g070vvn01_timings, 1166 .num_timings = 1, 1167 .bpc = 8, 1168 .size = { 1169 .width = 152, 1170 .height = 91, 1171 }, 1172 .delay = { 1173 .prepare = 200, 1174 .enable = 50, 1175 .disable = 50, 1176 .unprepare = 1000, 1177 }, 1178 }; 1179 1180 static const struct drm_display_mode auo_g101evn010_mode = { 1181 .clock = 68930, 1182 .hdisplay = 1280, 1183 .hsync_start = 1280 + 82, 1184 .hsync_end = 1280 + 82 + 2, 1185 .htotal = 1280 + 82 + 2 + 84, 1186 .vdisplay = 800, 1187 .vsync_start = 800 + 8, 1188 .vsync_end = 800 + 8 + 2, 1189 .vtotal = 800 + 8 + 2 + 6, 1190 }; 1191 1192 static const struct panel_desc auo_g101evn010 = { 1193 .modes = &auo_g101evn010_mode, 1194 .num_modes = 1, 1195 .bpc = 6, 1196 .size = { 1197 .width = 216, 1198 .height = 135, 1199 }, 1200 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1201 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1202 }; 1203 1204 static const struct drm_display_mode auo_g104sn02_mode = { 1205 .clock = 40000, 1206 .hdisplay = 800, 1207 .hsync_start = 800 + 40, 1208 .hsync_end = 800 + 40 + 216, 1209 .htotal = 800 + 40 + 216 + 128, 1210 .vdisplay = 600, 1211 .vsync_start = 600 + 10, 1212 .vsync_end = 600 + 10 + 35, 1213 .vtotal = 600 + 10 + 35 + 2, 1214 }; 1215 1216 static const struct panel_desc auo_g104sn02 = { 1217 .modes = &auo_g104sn02_mode, 1218 .num_modes = 1, 1219 .bpc = 8, 1220 .size = { 1221 .width = 211, 1222 .height = 158, 1223 }, 1224 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1225 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1226 }; 1227 1228 static const struct drm_display_mode auo_g121ean01_mode = { 1229 .clock = 66700, 1230 .hdisplay = 1280, 1231 .hsync_start = 1280 + 58, 1232 .hsync_end = 1280 + 58 + 8, 1233 .htotal = 1280 + 58 + 8 + 70, 1234 .vdisplay = 800, 1235 .vsync_start = 800 + 6, 1236 .vsync_end = 800 + 6 + 4, 1237 .vtotal = 800 + 6 + 4 + 10, 1238 }; 1239 1240 static const struct panel_desc auo_g121ean01 = { 1241 .modes = &auo_g121ean01_mode, 1242 .num_modes = 1, 1243 .bpc = 8, 1244 .size = { 1245 .width = 261, 1246 .height = 163, 1247 }, 1248 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1249 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1250 }; 1251 1252 static const struct display_timing auo_g133han01_timings = { 1253 .pixelclock = { 134000000, 141200000, 149000000 }, 1254 .hactive = { 1920, 1920, 1920 }, 1255 .hfront_porch = { 39, 58, 77 }, 1256 .hback_porch = { 59, 88, 117 }, 1257 .hsync_len = { 28, 42, 56 }, 1258 .vactive = { 1080, 1080, 1080 }, 1259 .vfront_porch = { 3, 8, 11 }, 1260 .vback_porch = { 5, 14, 19 }, 1261 .vsync_len = { 4, 14, 19 }, 1262 }; 1263 1264 static const struct panel_desc auo_g133han01 = { 1265 .timings = &auo_g133han01_timings, 1266 .num_timings = 1, 1267 .bpc = 8, 1268 .size = { 1269 .width = 293, 1270 .height = 165, 1271 }, 1272 .delay = { 1273 .prepare = 200, 1274 .enable = 50, 1275 .disable = 50, 1276 .unprepare = 1000, 1277 }, 1278 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1279 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1280 }; 1281 1282 static const struct drm_display_mode auo_g156xtn01_mode = { 1283 .clock = 76000, 1284 .hdisplay = 1366, 1285 .hsync_start = 1366 + 33, 1286 .hsync_end = 1366 + 33 + 67, 1287 .htotal = 1560, 1288 .vdisplay = 768, 1289 .vsync_start = 768 + 4, 1290 .vsync_end = 768 + 4 + 4, 1291 .vtotal = 806, 1292 }; 1293 1294 static const struct panel_desc auo_g156xtn01 = { 1295 .modes = &auo_g156xtn01_mode, 1296 .num_modes = 1, 1297 .bpc = 8, 1298 .size = { 1299 .width = 344, 1300 .height = 194, 1301 }, 1302 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1303 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1304 }; 1305 1306 static const struct display_timing auo_g185han01_timings = { 1307 .pixelclock = { 120000000, 144000000, 175000000 }, 1308 .hactive = { 1920, 1920, 1920 }, 1309 .hfront_porch = { 36, 120, 148 }, 1310 .hback_porch = { 24, 88, 108 }, 1311 .hsync_len = { 20, 48, 64 }, 1312 .vactive = { 1080, 1080, 1080 }, 1313 .vfront_porch = { 6, 10, 40 }, 1314 .vback_porch = { 2, 5, 20 }, 1315 .vsync_len = { 2, 5, 20 }, 1316 }; 1317 1318 static const struct panel_desc auo_g185han01 = { 1319 .timings = &auo_g185han01_timings, 1320 .num_timings = 1, 1321 .bpc = 8, 1322 .size = { 1323 .width = 409, 1324 .height = 230, 1325 }, 1326 .delay = { 1327 .prepare = 50, 1328 .enable = 200, 1329 .disable = 110, 1330 .unprepare = 1000, 1331 }, 1332 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1333 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1334 }; 1335 1336 static const struct display_timing auo_g190ean01_timings = { 1337 .pixelclock = { 90000000, 108000000, 135000000 }, 1338 .hactive = { 1280, 1280, 1280 }, 1339 .hfront_porch = { 126, 184, 1266 }, 1340 .hback_porch = { 84, 122, 844 }, 1341 .hsync_len = { 70, 102, 704 }, 1342 .vactive = { 1024, 1024, 1024 }, 1343 .vfront_porch = { 4, 26, 76 }, 1344 .vback_porch = { 2, 8, 25 }, 1345 .vsync_len = { 2, 8, 25 }, 1346 }; 1347 1348 static const struct panel_desc auo_g190ean01 = { 1349 .timings = &auo_g190ean01_timings, 1350 .num_timings = 1, 1351 .bpc = 8, 1352 .size = { 1353 .width = 376, 1354 .height = 301, 1355 }, 1356 .delay = { 1357 .prepare = 50, 1358 .enable = 200, 1359 .disable = 110, 1360 .unprepare = 1000, 1361 }, 1362 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1363 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1364 }; 1365 1366 static const struct display_timing auo_p320hvn03_timings = { 1367 .pixelclock = { 106000000, 148500000, 164000000 }, 1368 .hactive = { 1920, 1920, 1920 }, 1369 .hfront_porch = { 25, 50, 130 }, 1370 .hback_porch = { 25, 50, 130 }, 1371 .hsync_len = { 20, 40, 105 }, 1372 .vactive = { 1080, 1080, 1080 }, 1373 .vfront_porch = { 8, 17, 150 }, 1374 .vback_porch = { 8, 17, 150 }, 1375 .vsync_len = { 4, 11, 100 }, 1376 }; 1377 1378 static const struct panel_desc auo_p320hvn03 = { 1379 .timings = &auo_p320hvn03_timings, 1380 .num_timings = 1, 1381 .bpc = 8, 1382 .size = { 1383 .width = 698, 1384 .height = 393, 1385 }, 1386 .delay = { 1387 .prepare = 1, 1388 .enable = 450, 1389 .unprepare = 500, 1390 }, 1391 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1392 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1393 }; 1394 1395 static const struct drm_display_mode auo_t215hvn01_mode = { 1396 .clock = 148800, 1397 .hdisplay = 1920, 1398 .hsync_start = 1920 + 88, 1399 .hsync_end = 1920 + 88 + 44, 1400 .htotal = 1920 + 88 + 44 + 148, 1401 .vdisplay = 1080, 1402 .vsync_start = 1080 + 4, 1403 .vsync_end = 1080 + 4 + 5, 1404 .vtotal = 1080 + 4 + 5 + 36, 1405 }; 1406 1407 static const struct panel_desc auo_t215hvn01 = { 1408 .modes = &auo_t215hvn01_mode, 1409 .num_modes = 1, 1410 .bpc = 8, 1411 .size = { 1412 .width = 430, 1413 .height = 270, 1414 }, 1415 .delay = { 1416 .disable = 5, 1417 .unprepare = 1000, 1418 } 1419 }; 1420 1421 static const struct drm_display_mode avic_tm070ddh03_mode = { 1422 .clock = 51200, 1423 .hdisplay = 1024, 1424 .hsync_start = 1024 + 160, 1425 .hsync_end = 1024 + 160 + 4, 1426 .htotal = 1024 + 160 + 4 + 156, 1427 .vdisplay = 600, 1428 .vsync_start = 600 + 17, 1429 .vsync_end = 600 + 17 + 1, 1430 .vtotal = 600 + 17 + 1 + 17, 1431 }; 1432 1433 static const struct panel_desc avic_tm070ddh03 = { 1434 .modes = &avic_tm070ddh03_mode, 1435 .num_modes = 1, 1436 .bpc = 8, 1437 .size = { 1438 .width = 154, 1439 .height = 90, 1440 }, 1441 .delay = { 1442 .prepare = 20, 1443 .enable = 200, 1444 .disable = 200, 1445 }, 1446 }; 1447 1448 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1449 .clock = 30000, 1450 .hdisplay = 800, 1451 .hsync_start = 800 + 40, 1452 .hsync_end = 800 + 40 + 48, 1453 .htotal = 800 + 40 + 48 + 40, 1454 .vdisplay = 480, 1455 .vsync_start = 480 + 13, 1456 .vsync_end = 480 + 13 + 3, 1457 .vtotal = 480 + 13 + 3 + 29, 1458 }; 1459 1460 static const struct panel_desc bananapi_s070wv20_ct16 = { 1461 .modes = &bananapi_s070wv20_ct16_mode, 1462 .num_modes = 1, 1463 .bpc = 6, 1464 .size = { 1465 .width = 154, 1466 .height = 86, 1467 }, 1468 }; 1469 1470 static const struct drm_display_mode boe_hv070wsa_mode = { 1471 .clock = 42105, 1472 .hdisplay = 1024, 1473 .hsync_start = 1024 + 30, 1474 .hsync_end = 1024 + 30 + 30, 1475 .htotal = 1024 + 30 + 30 + 30, 1476 .vdisplay = 600, 1477 .vsync_start = 600 + 10, 1478 .vsync_end = 600 + 10 + 10, 1479 .vtotal = 600 + 10 + 10 + 10, 1480 }; 1481 1482 static const struct panel_desc boe_hv070wsa = { 1483 .modes = &boe_hv070wsa_mode, 1484 .num_modes = 1, 1485 .bpc = 8, 1486 .size = { 1487 .width = 154, 1488 .height = 90, 1489 }, 1490 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1491 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1492 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1493 }; 1494 1495 static const struct drm_display_mode boe_nv101wxmn51_modes[] = { 1496 { 1497 .clock = 71900, 1498 .hdisplay = 1280, 1499 .hsync_start = 1280 + 48, 1500 .hsync_end = 1280 + 48 + 32, 1501 .htotal = 1280 + 48 + 32 + 80, 1502 .vdisplay = 800, 1503 .vsync_start = 800 + 3, 1504 .vsync_end = 800 + 3 + 5, 1505 .vtotal = 800 + 3 + 5 + 24, 1506 }, 1507 { 1508 .clock = 57500, 1509 .hdisplay = 1280, 1510 .hsync_start = 1280 + 48, 1511 .hsync_end = 1280 + 48 + 32, 1512 .htotal = 1280 + 48 + 32 + 80, 1513 .vdisplay = 800, 1514 .vsync_start = 800 + 3, 1515 .vsync_end = 800 + 3 + 5, 1516 .vtotal = 800 + 3 + 5 + 24, 1517 }, 1518 }; 1519 1520 static const struct panel_desc boe_nv101wxmn51 = { 1521 .modes = boe_nv101wxmn51_modes, 1522 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), 1523 .bpc = 8, 1524 .size = { 1525 .width = 217, 1526 .height = 136, 1527 }, 1528 .delay = { 1529 .prepare = 210, 1530 .enable = 50, 1531 .unprepare = 160, 1532 }, 1533 }; 1534 1535 static const struct drm_display_mode boe_nv110wtm_n61_modes[] = { 1536 { 1537 .clock = 207800, 1538 .hdisplay = 2160, 1539 .hsync_start = 2160 + 48, 1540 .hsync_end = 2160 + 48 + 32, 1541 .htotal = 2160 + 48 + 32 + 100, 1542 .vdisplay = 1440, 1543 .vsync_start = 1440 + 3, 1544 .vsync_end = 1440 + 3 + 6, 1545 .vtotal = 1440 + 3 + 6 + 31, 1546 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 1547 }, 1548 { 1549 .clock = 138500, 1550 .hdisplay = 2160, 1551 .hsync_start = 2160 + 48, 1552 .hsync_end = 2160 + 48 + 32, 1553 .htotal = 2160 + 48 + 32 + 100, 1554 .vdisplay = 1440, 1555 .vsync_start = 1440 + 3, 1556 .vsync_end = 1440 + 3 + 6, 1557 .vtotal = 1440 + 3 + 6 + 31, 1558 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 1559 }, 1560 }; 1561 1562 static const struct panel_desc boe_nv110wtm_n61 = { 1563 .modes = boe_nv110wtm_n61_modes, 1564 .num_modes = ARRAY_SIZE(boe_nv110wtm_n61_modes), 1565 .bpc = 8, 1566 .size = { 1567 .width = 233, 1568 .height = 155, 1569 }, 1570 .delay = { 1571 .hpd_absent_delay = 200, 1572 .prepare_to_enable = 80, 1573 .enable = 50, 1574 .unprepare = 500, 1575 }, 1576 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1577 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1578 .connector_type = DRM_MODE_CONNECTOR_eDP, 1579 }; 1580 1581 /* Also used for boe_nv133fhm_n62 */ 1582 static const struct drm_display_mode boe_nv133fhm_n61_modes = { 1583 .clock = 147840, 1584 .hdisplay = 1920, 1585 .hsync_start = 1920 + 48, 1586 .hsync_end = 1920 + 48 + 32, 1587 .htotal = 1920 + 48 + 32 + 200, 1588 .vdisplay = 1080, 1589 .vsync_start = 1080 + 3, 1590 .vsync_end = 1080 + 3 + 6, 1591 .vtotal = 1080 + 3 + 6 + 31, 1592 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 1593 }; 1594 1595 /* Also used for boe_nv133fhm_n62 */ 1596 static const struct panel_desc boe_nv133fhm_n61 = { 1597 .modes = &boe_nv133fhm_n61_modes, 1598 .num_modes = 1, 1599 .bpc = 6, 1600 .size = { 1601 .width = 294, 1602 .height = 165, 1603 }, 1604 .delay = { 1605 /* 1606 * When power is first given to the panel there's a short 1607 * spike on the HPD line. It was explained that this spike 1608 * was until the TCON data download was complete. On 1609 * one system this was measured at 8 ms. We'll put 15 ms 1610 * in the prepare delay just to be safe and take it away 1611 * from the hpd_absent_delay (which would otherwise be 200 ms) 1612 * to handle this. That means: 1613 * - If HPD isn't hooked up you still have 200 ms delay. 1614 * - If HPD is hooked up we won't try to look at it for the 1615 * first 15 ms. 1616 */ 1617 .prepare = 15, 1618 .hpd_absent_delay = 185, 1619 1620 .unprepare = 500, 1621 }, 1622 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1623 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 1624 .connector_type = DRM_MODE_CONNECTOR_eDP, 1625 }; 1626 1627 static const struct drm_display_mode boe_nv140fhmn49_modes[] = { 1628 { 1629 .clock = 148500, 1630 .hdisplay = 1920, 1631 .hsync_start = 1920 + 48, 1632 .hsync_end = 1920 + 48 + 32, 1633 .htotal = 2200, 1634 .vdisplay = 1080, 1635 .vsync_start = 1080 + 3, 1636 .vsync_end = 1080 + 3 + 5, 1637 .vtotal = 1125, 1638 }, 1639 }; 1640 1641 static const struct panel_desc boe_nv140fhmn49 = { 1642 .modes = boe_nv140fhmn49_modes, 1643 .num_modes = ARRAY_SIZE(boe_nv140fhmn49_modes), 1644 .bpc = 6, 1645 .size = { 1646 .width = 309, 1647 .height = 174, 1648 }, 1649 .delay = { 1650 .prepare = 210, 1651 .enable = 50, 1652 .unprepare = 160, 1653 }, 1654 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1655 .connector_type = DRM_MODE_CONNECTOR_eDP, 1656 }; 1657 1658 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1659 .clock = 9000, 1660 .hdisplay = 480, 1661 .hsync_start = 480 + 5, 1662 .hsync_end = 480 + 5 + 5, 1663 .htotal = 480 + 5 + 5 + 40, 1664 .vdisplay = 272, 1665 .vsync_start = 272 + 8, 1666 .vsync_end = 272 + 8 + 8, 1667 .vtotal = 272 + 8 + 8 + 8, 1668 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1669 }; 1670 1671 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1672 .modes = &cdtech_s043wq26h_ct7_mode, 1673 .num_modes = 1, 1674 .bpc = 8, 1675 .size = { 1676 .width = 95, 1677 .height = 54, 1678 }, 1679 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1680 }; 1681 1682 /* S070PWS19HP-FC21 2017/04/22 */ 1683 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1684 .clock = 51200, 1685 .hdisplay = 1024, 1686 .hsync_start = 1024 + 160, 1687 .hsync_end = 1024 + 160 + 20, 1688 .htotal = 1024 + 160 + 20 + 140, 1689 .vdisplay = 600, 1690 .vsync_start = 600 + 12, 1691 .vsync_end = 600 + 12 + 3, 1692 .vtotal = 600 + 12 + 3 + 20, 1693 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1694 }; 1695 1696 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1697 .modes = &cdtech_s070pws19hp_fc21_mode, 1698 .num_modes = 1, 1699 .bpc = 6, 1700 .size = { 1701 .width = 154, 1702 .height = 86, 1703 }, 1704 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1705 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1706 .connector_type = DRM_MODE_CONNECTOR_DPI, 1707 }; 1708 1709 /* S070SWV29HG-DC44 2017/09/21 */ 1710 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1711 .clock = 33300, 1712 .hdisplay = 800, 1713 .hsync_start = 800 + 210, 1714 .hsync_end = 800 + 210 + 2, 1715 .htotal = 800 + 210 + 2 + 44, 1716 .vdisplay = 480, 1717 .vsync_start = 480 + 22, 1718 .vsync_end = 480 + 22 + 2, 1719 .vtotal = 480 + 22 + 2 + 21, 1720 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1721 }; 1722 1723 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1724 .modes = &cdtech_s070swv29hg_dc44_mode, 1725 .num_modes = 1, 1726 .bpc = 6, 1727 .size = { 1728 .width = 154, 1729 .height = 86, 1730 }, 1731 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1732 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1733 .connector_type = DRM_MODE_CONNECTOR_DPI, 1734 }; 1735 1736 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1737 .clock = 35000, 1738 .hdisplay = 800, 1739 .hsync_start = 800 + 40, 1740 .hsync_end = 800 + 40 + 40, 1741 .htotal = 800 + 40 + 40 + 48, 1742 .vdisplay = 480, 1743 .vsync_start = 480 + 29, 1744 .vsync_end = 480 + 29 + 13, 1745 .vtotal = 480 + 29 + 13 + 3, 1746 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1747 }; 1748 1749 static const struct panel_desc cdtech_s070wv95_ct16 = { 1750 .modes = &cdtech_s070wv95_ct16_mode, 1751 .num_modes = 1, 1752 .bpc = 8, 1753 .size = { 1754 .width = 154, 1755 .height = 85, 1756 }, 1757 }; 1758 1759 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1760 .pixelclock = { 68900000, 71100000, 73400000 }, 1761 .hactive = { 1280, 1280, 1280 }, 1762 .hfront_porch = { 65, 80, 95 }, 1763 .hback_porch = { 64, 79, 94 }, 1764 .hsync_len = { 1, 1, 1 }, 1765 .vactive = { 800, 800, 800 }, 1766 .vfront_porch = { 7, 11, 14 }, 1767 .vback_porch = { 7, 11, 14 }, 1768 .vsync_len = { 1, 1, 1 }, 1769 .flags = DISPLAY_FLAGS_DE_HIGH, 1770 }; 1771 1772 static const struct panel_desc chefree_ch101olhlwh_002 = { 1773 .timings = &chefree_ch101olhlwh_002_timing, 1774 .num_timings = 1, 1775 .bpc = 8, 1776 .size = { 1777 .width = 217, 1778 .height = 135, 1779 }, 1780 .delay = { 1781 .enable = 200, 1782 .disable = 200, 1783 }, 1784 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1785 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1786 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1787 }; 1788 1789 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1790 .clock = 66770, 1791 .hdisplay = 800, 1792 .hsync_start = 800 + 49, 1793 .hsync_end = 800 + 49 + 33, 1794 .htotal = 800 + 49 + 33 + 17, 1795 .vdisplay = 1280, 1796 .vsync_start = 1280 + 1, 1797 .vsync_end = 1280 + 1 + 7, 1798 .vtotal = 1280 + 1 + 7 + 15, 1799 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1800 }; 1801 1802 static const struct panel_desc chunghwa_claa070wp03xg = { 1803 .modes = &chunghwa_claa070wp03xg_mode, 1804 .num_modes = 1, 1805 .bpc = 6, 1806 .size = { 1807 .width = 94, 1808 .height = 150, 1809 }, 1810 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1811 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1812 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1813 }; 1814 1815 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1816 .clock = 72070, 1817 .hdisplay = 1366, 1818 .hsync_start = 1366 + 58, 1819 .hsync_end = 1366 + 58 + 58, 1820 .htotal = 1366 + 58 + 58 + 58, 1821 .vdisplay = 768, 1822 .vsync_start = 768 + 4, 1823 .vsync_end = 768 + 4 + 4, 1824 .vtotal = 768 + 4 + 4 + 4, 1825 }; 1826 1827 static const struct panel_desc chunghwa_claa101wa01a = { 1828 .modes = &chunghwa_claa101wa01a_mode, 1829 .num_modes = 1, 1830 .bpc = 6, 1831 .size = { 1832 .width = 220, 1833 .height = 120, 1834 }, 1835 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1836 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1837 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1838 }; 1839 1840 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1841 .clock = 69300, 1842 .hdisplay = 1366, 1843 .hsync_start = 1366 + 48, 1844 .hsync_end = 1366 + 48 + 32, 1845 .htotal = 1366 + 48 + 32 + 20, 1846 .vdisplay = 768, 1847 .vsync_start = 768 + 16, 1848 .vsync_end = 768 + 16 + 8, 1849 .vtotal = 768 + 16 + 8 + 16, 1850 }; 1851 1852 static const struct panel_desc chunghwa_claa101wb01 = { 1853 .modes = &chunghwa_claa101wb01_mode, 1854 .num_modes = 1, 1855 .bpc = 6, 1856 .size = { 1857 .width = 223, 1858 .height = 125, 1859 }, 1860 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1861 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1862 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1863 }; 1864 1865 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1866 .clock = 33260, 1867 .hdisplay = 800, 1868 .hsync_start = 800 + 40, 1869 .hsync_end = 800 + 40 + 128, 1870 .htotal = 800 + 40 + 128 + 88, 1871 .vdisplay = 480, 1872 .vsync_start = 480 + 10, 1873 .vsync_end = 480 + 10 + 2, 1874 .vtotal = 480 + 10 + 2 + 33, 1875 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1876 }; 1877 1878 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1879 .modes = &dataimage_scf0700c48ggu18_mode, 1880 .num_modes = 1, 1881 .bpc = 8, 1882 .size = { 1883 .width = 152, 1884 .height = 91, 1885 }, 1886 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1887 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1888 }; 1889 1890 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1891 .pixelclock = { 45000000, 51200000, 57000000 }, 1892 .hactive = { 1024, 1024, 1024 }, 1893 .hfront_porch = { 100, 106, 113 }, 1894 .hback_porch = { 100, 106, 113 }, 1895 .hsync_len = { 100, 108, 114 }, 1896 .vactive = { 600, 600, 600 }, 1897 .vfront_porch = { 8, 11, 15 }, 1898 .vback_porch = { 8, 11, 15 }, 1899 .vsync_len = { 9, 13, 15 }, 1900 .flags = DISPLAY_FLAGS_DE_HIGH, 1901 }; 1902 1903 static const struct panel_desc dlc_dlc0700yzg_1 = { 1904 .timings = &dlc_dlc0700yzg_1_timing, 1905 .num_timings = 1, 1906 .bpc = 6, 1907 .size = { 1908 .width = 154, 1909 .height = 86, 1910 }, 1911 .delay = { 1912 .prepare = 30, 1913 .enable = 200, 1914 .disable = 200, 1915 }, 1916 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1917 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1918 }; 1919 1920 static const struct display_timing dlc_dlc1010gig_timing = { 1921 .pixelclock = { 68900000, 71100000, 73400000 }, 1922 .hactive = { 1280, 1280, 1280 }, 1923 .hfront_porch = { 43, 53, 63 }, 1924 .hback_porch = { 43, 53, 63 }, 1925 .hsync_len = { 44, 54, 64 }, 1926 .vactive = { 800, 800, 800 }, 1927 .vfront_porch = { 5, 8, 11 }, 1928 .vback_porch = { 5, 8, 11 }, 1929 .vsync_len = { 5, 7, 11 }, 1930 .flags = DISPLAY_FLAGS_DE_HIGH, 1931 }; 1932 1933 static const struct panel_desc dlc_dlc1010gig = { 1934 .timings = &dlc_dlc1010gig_timing, 1935 .num_timings = 1, 1936 .bpc = 8, 1937 .size = { 1938 .width = 216, 1939 .height = 135, 1940 }, 1941 .delay = { 1942 .prepare = 60, 1943 .enable = 150, 1944 .disable = 100, 1945 .unprepare = 60, 1946 }, 1947 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1948 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1949 }; 1950 1951 static const struct drm_display_mode edt_et035012dm6_mode = { 1952 .clock = 6500, 1953 .hdisplay = 320, 1954 .hsync_start = 320 + 20, 1955 .hsync_end = 320 + 20 + 30, 1956 .htotal = 320 + 20 + 68, 1957 .vdisplay = 240, 1958 .vsync_start = 240 + 4, 1959 .vsync_end = 240 + 4 + 4, 1960 .vtotal = 240 + 4 + 4 + 14, 1961 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1962 }; 1963 1964 static const struct panel_desc edt_et035012dm6 = { 1965 .modes = &edt_et035012dm6_mode, 1966 .num_modes = 1, 1967 .bpc = 8, 1968 .size = { 1969 .width = 70, 1970 .height = 52, 1971 }, 1972 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1973 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1974 }; 1975 1976 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1977 .clock = 6520, 1978 .hdisplay = 320, 1979 .hsync_start = 320 + 20, 1980 .hsync_end = 320 + 20 + 68, 1981 .htotal = 320 + 20 + 68, 1982 .vdisplay = 240, 1983 .vsync_start = 240 + 4, 1984 .vsync_end = 240 + 4 + 18, 1985 .vtotal = 240 + 4 + 18, 1986 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1987 }; 1988 1989 static const struct panel_desc edt_etm0350g0dh6 = { 1990 .modes = &edt_etm0350g0dh6_mode, 1991 .num_modes = 1, 1992 .bpc = 6, 1993 .size = { 1994 .width = 70, 1995 .height = 53, 1996 }, 1997 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1998 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1999 .connector_type = DRM_MODE_CONNECTOR_DPI, 2000 }; 2001 2002 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 2003 .clock = 10870, 2004 .hdisplay = 480, 2005 .hsync_start = 480 + 8, 2006 .hsync_end = 480 + 8 + 4, 2007 .htotal = 480 + 8 + 4 + 41, 2008 2009 /* 2010 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 2011 * fb_align 2012 */ 2013 2014 .vdisplay = 288, 2015 .vsync_start = 288 + 2, 2016 .vsync_end = 288 + 2 + 4, 2017 .vtotal = 288 + 2 + 4 + 10, 2018 }; 2019 2020 static const struct panel_desc edt_etm043080dh6gp = { 2021 .modes = &edt_etm043080dh6gp_mode, 2022 .num_modes = 1, 2023 .bpc = 8, 2024 .size = { 2025 .width = 100, 2026 .height = 65, 2027 }, 2028 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2029 .connector_type = DRM_MODE_CONNECTOR_DPI, 2030 }; 2031 2032 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 2033 .clock = 9000, 2034 .hdisplay = 480, 2035 .hsync_start = 480 + 2, 2036 .hsync_end = 480 + 2 + 41, 2037 .htotal = 480 + 2 + 41 + 2, 2038 .vdisplay = 272, 2039 .vsync_start = 272 + 2, 2040 .vsync_end = 272 + 2 + 10, 2041 .vtotal = 272 + 2 + 10 + 2, 2042 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2043 }; 2044 2045 static const struct panel_desc edt_etm0430g0dh6 = { 2046 .modes = &edt_etm0430g0dh6_mode, 2047 .num_modes = 1, 2048 .bpc = 6, 2049 .size = { 2050 .width = 95, 2051 .height = 54, 2052 }, 2053 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2054 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2055 .connector_type = DRM_MODE_CONNECTOR_DPI, 2056 }; 2057 2058 static const struct drm_display_mode edt_et057090dhu_mode = { 2059 .clock = 25175, 2060 .hdisplay = 640, 2061 .hsync_start = 640 + 16, 2062 .hsync_end = 640 + 16 + 30, 2063 .htotal = 640 + 16 + 30 + 114, 2064 .vdisplay = 480, 2065 .vsync_start = 480 + 10, 2066 .vsync_end = 480 + 10 + 3, 2067 .vtotal = 480 + 10 + 3 + 32, 2068 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2069 }; 2070 2071 static const struct panel_desc edt_et057090dhu = { 2072 .modes = &edt_et057090dhu_mode, 2073 .num_modes = 1, 2074 .bpc = 6, 2075 .size = { 2076 .width = 115, 2077 .height = 86, 2078 }, 2079 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2080 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2081 .connector_type = DRM_MODE_CONNECTOR_DPI, 2082 }; 2083 2084 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2085 .clock = 33260, 2086 .hdisplay = 800, 2087 .hsync_start = 800 + 40, 2088 .hsync_end = 800 + 40 + 128, 2089 .htotal = 800 + 40 + 128 + 88, 2090 .vdisplay = 480, 2091 .vsync_start = 480 + 10, 2092 .vsync_end = 480 + 10 + 2, 2093 .vtotal = 480 + 10 + 2 + 33, 2094 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2095 }; 2096 2097 static const struct panel_desc edt_etm0700g0dh6 = { 2098 .modes = &edt_etm0700g0dh6_mode, 2099 .num_modes = 1, 2100 .bpc = 6, 2101 .size = { 2102 .width = 152, 2103 .height = 91, 2104 }, 2105 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2106 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2107 .connector_type = DRM_MODE_CONNECTOR_DPI, 2108 }; 2109 2110 static const struct panel_desc edt_etm0700g0bdh6 = { 2111 .modes = &edt_etm0700g0dh6_mode, 2112 .num_modes = 1, 2113 .bpc = 6, 2114 .size = { 2115 .width = 152, 2116 .height = 91, 2117 }, 2118 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2119 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2120 .connector_type = DRM_MODE_CONNECTOR_DPI, 2121 }; 2122 2123 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2124 .clock = 25175, 2125 .hdisplay = 640, 2126 .hsync_start = 640, 2127 .hsync_end = 640 + 16, 2128 .htotal = 640 + 16 + 30 + 114, 2129 .vdisplay = 480, 2130 .vsync_start = 480 + 10, 2131 .vsync_end = 480 + 10 + 3, 2132 .vtotal = 480 + 10 + 3 + 35, 2133 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2134 }; 2135 2136 static const struct panel_desc edt_etmv570g2dhu = { 2137 .modes = &edt_etmv570g2dhu_mode, 2138 .num_modes = 1, 2139 .bpc = 6, 2140 .size = { 2141 .width = 115, 2142 .height = 86, 2143 }, 2144 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2145 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2146 .connector_type = DRM_MODE_CONNECTOR_DPI, 2147 }; 2148 2149 static const struct display_timing evervision_vgg804821_timing = { 2150 .pixelclock = { 27600000, 33300000, 50000000 }, 2151 .hactive = { 800, 800, 800 }, 2152 .hfront_porch = { 40, 66, 70 }, 2153 .hback_porch = { 40, 67, 70 }, 2154 .hsync_len = { 40, 67, 70 }, 2155 .vactive = { 480, 480, 480 }, 2156 .vfront_porch = { 6, 10, 10 }, 2157 .vback_porch = { 7, 11, 11 }, 2158 .vsync_len = { 7, 11, 11 }, 2159 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2160 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2161 DISPLAY_FLAGS_SYNC_NEGEDGE, 2162 }; 2163 2164 static const struct panel_desc evervision_vgg804821 = { 2165 .timings = &evervision_vgg804821_timing, 2166 .num_timings = 1, 2167 .bpc = 8, 2168 .size = { 2169 .width = 108, 2170 .height = 64, 2171 }, 2172 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2173 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2174 }; 2175 2176 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2177 .clock = 32260, 2178 .hdisplay = 800, 2179 .hsync_start = 800 + 168, 2180 .hsync_end = 800 + 168 + 64, 2181 .htotal = 800 + 168 + 64 + 88, 2182 .vdisplay = 480, 2183 .vsync_start = 480 + 37, 2184 .vsync_end = 480 + 37 + 2, 2185 .vtotal = 480 + 37 + 2 + 8, 2186 }; 2187 2188 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2189 .modes = &foxlink_fl500wvr00_a0t_mode, 2190 .num_modes = 1, 2191 .bpc = 8, 2192 .size = { 2193 .width = 108, 2194 .height = 65, 2195 }, 2196 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2197 }; 2198 2199 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2200 { /* 60 Hz */ 2201 .clock = 6000, 2202 .hdisplay = 320, 2203 .hsync_start = 320 + 44, 2204 .hsync_end = 320 + 44 + 16, 2205 .htotal = 320 + 44 + 16 + 20, 2206 .vdisplay = 240, 2207 .vsync_start = 240 + 2, 2208 .vsync_end = 240 + 2 + 6, 2209 .vtotal = 240 + 2 + 6 + 2, 2210 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2211 }, 2212 { /* 50 Hz */ 2213 .clock = 5400, 2214 .hdisplay = 320, 2215 .hsync_start = 320 + 56, 2216 .hsync_end = 320 + 56 + 16, 2217 .htotal = 320 + 56 + 16 + 40, 2218 .vdisplay = 240, 2219 .vsync_start = 240 + 2, 2220 .vsync_end = 240 + 2 + 6, 2221 .vtotal = 240 + 2 + 6 + 2, 2222 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2223 }, 2224 }; 2225 2226 static const struct panel_desc frida_frd350h54004 = { 2227 .modes = frida_frd350h54004_modes, 2228 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2229 .bpc = 8, 2230 .size = { 2231 .width = 77, 2232 .height = 64, 2233 }, 2234 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2235 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2236 .connector_type = DRM_MODE_CONNECTOR_DPI, 2237 }; 2238 2239 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2240 .clock = 67185, 2241 .hdisplay = 800, 2242 .hsync_start = 800 + 20, 2243 .hsync_end = 800 + 20 + 24, 2244 .htotal = 800 + 20 + 24 + 20, 2245 .vdisplay = 1280, 2246 .vsync_start = 1280 + 4, 2247 .vsync_end = 1280 + 4 + 8, 2248 .vtotal = 1280 + 4 + 8 + 4, 2249 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2250 }; 2251 2252 static const struct panel_desc friendlyarm_hd702e = { 2253 .modes = &friendlyarm_hd702e_mode, 2254 .num_modes = 1, 2255 .size = { 2256 .width = 94, 2257 .height = 151, 2258 }, 2259 }; 2260 2261 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2262 .clock = 9000, 2263 .hdisplay = 480, 2264 .hsync_start = 480 + 5, 2265 .hsync_end = 480 + 5 + 1, 2266 .htotal = 480 + 5 + 1 + 40, 2267 .vdisplay = 272, 2268 .vsync_start = 272 + 8, 2269 .vsync_end = 272 + 8 + 1, 2270 .vtotal = 272 + 8 + 1 + 8, 2271 }; 2272 2273 static const struct panel_desc giantplus_gpg482739qs5 = { 2274 .modes = &giantplus_gpg482739qs5_mode, 2275 .num_modes = 1, 2276 .bpc = 8, 2277 .size = { 2278 .width = 95, 2279 .height = 54, 2280 }, 2281 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2282 }; 2283 2284 static const struct display_timing giantplus_gpm940b0_timing = { 2285 .pixelclock = { 13500000, 27000000, 27500000 }, 2286 .hactive = { 320, 320, 320 }, 2287 .hfront_porch = { 14, 686, 718 }, 2288 .hback_porch = { 50, 70, 255 }, 2289 .hsync_len = { 1, 1, 1 }, 2290 .vactive = { 240, 240, 240 }, 2291 .vfront_porch = { 1, 1, 179 }, 2292 .vback_porch = { 1, 21, 31 }, 2293 .vsync_len = { 1, 1, 6 }, 2294 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2295 }; 2296 2297 static const struct panel_desc giantplus_gpm940b0 = { 2298 .timings = &giantplus_gpm940b0_timing, 2299 .num_timings = 1, 2300 .bpc = 8, 2301 .size = { 2302 .width = 60, 2303 .height = 45, 2304 }, 2305 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2306 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2307 }; 2308 2309 static const struct display_timing hannstar_hsd070pww1_timing = { 2310 .pixelclock = { 64300000, 71100000, 82000000 }, 2311 .hactive = { 1280, 1280, 1280 }, 2312 .hfront_porch = { 1, 1, 10 }, 2313 .hback_porch = { 1, 1, 10 }, 2314 /* 2315 * According to the data sheet, the minimum horizontal blanking interval 2316 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2317 * minimum working horizontal blanking interval to be 60 clocks. 2318 */ 2319 .hsync_len = { 58, 158, 661 }, 2320 .vactive = { 800, 800, 800 }, 2321 .vfront_porch = { 1, 1, 10 }, 2322 .vback_porch = { 1, 1, 10 }, 2323 .vsync_len = { 1, 21, 203 }, 2324 .flags = DISPLAY_FLAGS_DE_HIGH, 2325 }; 2326 2327 static const struct panel_desc hannstar_hsd070pww1 = { 2328 .timings = &hannstar_hsd070pww1_timing, 2329 .num_timings = 1, 2330 .bpc = 6, 2331 .size = { 2332 .width = 151, 2333 .height = 94, 2334 }, 2335 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2336 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2337 }; 2338 2339 static const struct display_timing hannstar_hsd100pxn1_timing = { 2340 .pixelclock = { 55000000, 65000000, 75000000 }, 2341 .hactive = { 1024, 1024, 1024 }, 2342 .hfront_porch = { 40, 40, 40 }, 2343 .hback_porch = { 220, 220, 220 }, 2344 .hsync_len = { 20, 60, 100 }, 2345 .vactive = { 768, 768, 768 }, 2346 .vfront_porch = { 7, 7, 7 }, 2347 .vback_porch = { 21, 21, 21 }, 2348 .vsync_len = { 10, 10, 10 }, 2349 .flags = DISPLAY_FLAGS_DE_HIGH, 2350 }; 2351 2352 static const struct panel_desc hannstar_hsd100pxn1 = { 2353 .timings = &hannstar_hsd100pxn1_timing, 2354 .num_timings = 1, 2355 .bpc = 6, 2356 .size = { 2357 .width = 203, 2358 .height = 152, 2359 }, 2360 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2361 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2362 }; 2363 2364 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2365 .clock = 33333, 2366 .hdisplay = 800, 2367 .hsync_start = 800 + 85, 2368 .hsync_end = 800 + 85 + 86, 2369 .htotal = 800 + 85 + 86 + 85, 2370 .vdisplay = 480, 2371 .vsync_start = 480 + 16, 2372 .vsync_end = 480 + 16 + 13, 2373 .vtotal = 480 + 16 + 13 + 16, 2374 }; 2375 2376 static const struct panel_desc hitachi_tx23d38vm0caa = { 2377 .modes = &hitachi_tx23d38vm0caa_mode, 2378 .num_modes = 1, 2379 .bpc = 6, 2380 .size = { 2381 .width = 195, 2382 .height = 117, 2383 }, 2384 .delay = { 2385 .enable = 160, 2386 .disable = 160, 2387 }, 2388 }; 2389 2390 static const struct drm_display_mode innolux_at043tn24_mode = { 2391 .clock = 9000, 2392 .hdisplay = 480, 2393 .hsync_start = 480 + 2, 2394 .hsync_end = 480 + 2 + 41, 2395 .htotal = 480 + 2 + 41 + 2, 2396 .vdisplay = 272, 2397 .vsync_start = 272 + 2, 2398 .vsync_end = 272 + 2 + 10, 2399 .vtotal = 272 + 2 + 10 + 2, 2400 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2401 }; 2402 2403 static const struct panel_desc innolux_at043tn24 = { 2404 .modes = &innolux_at043tn24_mode, 2405 .num_modes = 1, 2406 .bpc = 8, 2407 .size = { 2408 .width = 95, 2409 .height = 54, 2410 }, 2411 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2412 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2413 }; 2414 2415 static const struct drm_display_mode innolux_at070tn92_mode = { 2416 .clock = 33333, 2417 .hdisplay = 800, 2418 .hsync_start = 800 + 210, 2419 .hsync_end = 800 + 210 + 20, 2420 .htotal = 800 + 210 + 20 + 46, 2421 .vdisplay = 480, 2422 .vsync_start = 480 + 22, 2423 .vsync_end = 480 + 22 + 10, 2424 .vtotal = 480 + 22 + 23 + 10, 2425 }; 2426 2427 static const struct panel_desc innolux_at070tn92 = { 2428 .modes = &innolux_at070tn92_mode, 2429 .num_modes = 1, 2430 .size = { 2431 .width = 154, 2432 .height = 86, 2433 }, 2434 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2435 }; 2436 2437 static const struct display_timing innolux_g070y2_l01_timing = { 2438 .pixelclock = { 28000000, 29500000, 32000000 }, 2439 .hactive = { 800, 800, 800 }, 2440 .hfront_porch = { 61, 91, 141 }, 2441 .hback_porch = { 60, 90, 140 }, 2442 .hsync_len = { 12, 12, 12 }, 2443 .vactive = { 480, 480, 480 }, 2444 .vfront_porch = { 4, 9, 30 }, 2445 .vback_porch = { 4, 8, 28 }, 2446 .vsync_len = { 2, 2, 2 }, 2447 .flags = DISPLAY_FLAGS_DE_HIGH, 2448 }; 2449 2450 static const struct panel_desc innolux_g070y2_l01 = { 2451 .timings = &innolux_g070y2_l01_timing, 2452 .num_timings = 1, 2453 .bpc = 6, 2454 .size = { 2455 .width = 152, 2456 .height = 91, 2457 }, 2458 .delay = { 2459 .prepare = 10, 2460 .enable = 100, 2461 .disable = 100, 2462 .unprepare = 800, 2463 }, 2464 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2465 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2466 }; 2467 2468 static const struct display_timing innolux_g101ice_l01_timing = { 2469 .pixelclock = { 60400000, 71100000, 74700000 }, 2470 .hactive = { 1280, 1280, 1280 }, 2471 .hfront_porch = { 41, 80, 100 }, 2472 .hback_porch = { 40, 79, 99 }, 2473 .hsync_len = { 1, 1, 1 }, 2474 .vactive = { 800, 800, 800 }, 2475 .vfront_porch = { 5, 11, 14 }, 2476 .vback_porch = { 4, 11, 14 }, 2477 .vsync_len = { 1, 1, 1 }, 2478 .flags = DISPLAY_FLAGS_DE_HIGH, 2479 }; 2480 2481 static const struct panel_desc innolux_g101ice_l01 = { 2482 .timings = &innolux_g101ice_l01_timing, 2483 .num_timings = 1, 2484 .bpc = 8, 2485 .size = { 2486 .width = 217, 2487 .height = 135, 2488 }, 2489 .delay = { 2490 .enable = 200, 2491 .disable = 200, 2492 }, 2493 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2494 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2495 }; 2496 2497 static const struct display_timing innolux_g121i1_l01_timing = { 2498 .pixelclock = { 67450000, 71000000, 74550000 }, 2499 .hactive = { 1280, 1280, 1280 }, 2500 .hfront_porch = { 40, 80, 160 }, 2501 .hback_porch = { 39, 79, 159 }, 2502 .hsync_len = { 1, 1, 1 }, 2503 .vactive = { 800, 800, 800 }, 2504 .vfront_porch = { 5, 11, 100 }, 2505 .vback_porch = { 4, 11, 99 }, 2506 .vsync_len = { 1, 1, 1 }, 2507 }; 2508 2509 static const struct panel_desc innolux_g121i1_l01 = { 2510 .timings = &innolux_g121i1_l01_timing, 2511 .num_timings = 1, 2512 .bpc = 6, 2513 .size = { 2514 .width = 261, 2515 .height = 163, 2516 }, 2517 .delay = { 2518 .enable = 200, 2519 .disable = 20, 2520 }, 2521 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2522 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2523 }; 2524 2525 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2526 .clock = 65000, 2527 .hdisplay = 1024, 2528 .hsync_start = 1024 + 0, 2529 .hsync_end = 1024 + 1, 2530 .htotal = 1024 + 0 + 1 + 320, 2531 .vdisplay = 768, 2532 .vsync_start = 768 + 38, 2533 .vsync_end = 768 + 38 + 1, 2534 .vtotal = 768 + 38 + 1 + 0, 2535 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2536 }; 2537 2538 static const struct panel_desc innolux_g121x1_l03 = { 2539 .modes = &innolux_g121x1_l03_mode, 2540 .num_modes = 1, 2541 .bpc = 6, 2542 .size = { 2543 .width = 246, 2544 .height = 185, 2545 }, 2546 .delay = { 2547 .enable = 200, 2548 .unprepare = 200, 2549 .disable = 400, 2550 }, 2551 }; 2552 2553 static const struct drm_display_mode innolux_n116bca_ea1_mode = { 2554 .clock = 76420, 2555 .hdisplay = 1366, 2556 .hsync_start = 1366 + 136, 2557 .hsync_end = 1366 + 136 + 30, 2558 .htotal = 1366 + 136 + 30 + 60, 2559 .vdisplay = 768, 2560 .vsync_start = 768 + 8, 2561 .vsync_end = 768 + 8 + 12, 2562 .vtotal = 768 + 8 + 12 + 12, 2563 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2564 }; 2565 2566 static const struct panel_desc innolux_n116bca_ea1 = { 2567 .modes = &innolux_n116bca_ea1_mode, 2568 .num_modes = 1, 2569 .bpc = 6, 2570 .size = { 2571 .width = 256, 2572 .height = 144, 2573 }, 2574 .delay = { 2575 .hpd_absent_delay = 200, 2576 .prepare_to_enable = 80, 2577 .unprepare = 500, 2578 }, 2579 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2580 .connector_type = DRM_MODE_CONNECTOR_eDP, 2581 }; 2582 2583 /* 2584 * Datasheet specifies that at 60 Hz refresh rate: 2585 * - total horizontal time: { 1506, 1592, 1716 } 2586 * - total vertical time: { 788, 800, 868 } 2587 * 2588 * ...but doesn't go into exactly how that should be split into a front 2589 * porch, back porch, or sync length. For now we'll leave a single setting 2590 * here which allows a bit of tweaking of the pixel clock at the expense of 2591 * refresh rate. 2592 */ 2593 static const struct display_timing innolux_n116bge_timing = { 2594 .pixelclock = { 72600000, 76420000, 80240000 }, 2595 .hactive = { 1366, 1366, 1366 }, 2596 .hfront_porch = { 136, 136, 136 }, 2597 .hback_porch = { 60, 60, 60 }, 2598 .hsync_len = { 30, 30, 30 }, 2599 .vactive = { 768, 768, 768 }, 2600 .vfront_porch = { 8, 8, 8 }, 2601 .vback_porch = { 12, 12, 12 }, 2602 .vsync_len = { 12, 12, 12 }, 2603 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 2604 }; 2605 2606 static const struct panel_desc innolux_n116bge = { 2607 .timings = &innolux_n116bge_timing, 2608 .num_timings = 1, 2609 .bpc = 6, 2610 .size = { 2611 .width = 256, 2612 .height = 144, 2613 }, 2614 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2615 .connector_type = DRM_MODE_CONNECTOR_eDP, 2616 }; 2617 2618 static const struct drm_display_mode innolux_n125hce_gn1_mode = { 2619 .clock = 162000, 2620 .hdisplay = 1920, 2621 .hsync_start = 1920 + 40, 2622 .hsync_end = 1920 + 40 + 40, 2623 .htotal = 1920 + 40 + 40 + 80, 2624 .vdisplay = 1080, 2625 .vsync_start = 1080 + 4, 2626 .vsync_end = 1080 + 4 + 4, 2627 .vtotal = 1080 + 4 + 4 + 24, 2628 }; 2629 2630 static const struct panel_desc innolux_n125hce_gn1 = { 2631 .modes = &innolux_n125hce_gn1_mode, 2632 .num_modes = 1, 2633 .bpc = 8, 2634 .size = { 2635 .width = 276, 2636 .height = 155, 2637 }, 2638 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2639 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2640 .connector_type = DRM_MODE_CONNECTOR_eDP, 2641 }; 2642 2643 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2644 .clock = 69300, 2645 .hdisplay = 1366, 2646 .hsync_start = 1366 + 16, 2647 .hsync_end = 1366 + 16 + 34, 2648 .htotal = 1366 + 16 + 34 + 50, 2649 .vdisplay = 768, 2650 .vsync_start = 768 + 2, 2651 .vsync_end = 768 + 2 + 6, 2652 .vtotal = 768 + 2 + 6 + 12, 2653 }; 2654 2655 static const struct panel_desc innolux_n156bge_l21 = { 2656 .modes = &innolux_n156bge_l21_mode, 2657 .num_modes = 1, 2658 .bpc = 6, 2659 .size = { 2660 .width = 344, 2661 .height = 193, 2662 }, 2663 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2664 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2665 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2666 }; 2667 2668 static const struct drm_display_mode innolux_p120zdg_bf1_mode = { 2669 .clock = 206016, 2670 .hdisplay = 2160, 2671 .hsync_start = 2160 + 48, 2672 .hsync_end = 2160 + 48 + 32, 2673 .htotal = 2160 + 48 + 32 + 80, 2674 .vdisplay = 1440, 2675 .vsync_start = 1440 + 3, 2676 .vsync_end = 1440 + 3 + 10, 2677 .vtotal = 1440 + 3 + 10 + 27, 2678 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2679 }; 2680 2681 static const struct panel_desc innolux_p120zdg_bf1 = { 2682 .modes = &innolux_p120zdg_bf1_mode, 2683 .num_modes = 1, 2684 .bpc = 8, 2685 .size = { 2686 .width = 254, 2687 .height = 169, 2688 }, 2689 .delay = { 2690 .hpd_absent_delay = 200, 2691 .unprepare = 500, 2692 }, 2693 }; 2694 2695 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2696 .clock = 51501, 2697 .hdisplay = 1024, 2698 .hsync_start = 1024 + 128, 2699 .hsync_end = 1024 + 128 + 64, 2700 .htotal = 1024 + 128 + 64 + 128, 2701 .vdisplay = 600, 2702 .vsync_start = 600 + 16, 2703 .vsync_end = 600 + 16 + 4, 2704 .vtotal = 600 + 16 + 4 + 16, 2705 }; 2706 2707 static const struct panel_desc innolux_zj070na_01p = { 2708 .modes = &innolux_zj070na_01p_mode, 2709 .num_modes = 1, 2710 .bpc = 6, 2711 .size = { 2712 .width = 154, 2713 .height = 90, 2714 }, 2715 }; 2716 2717 static const struct drm_display_mode ivo_m133nwf4_r0_mode = { 2718 .clock = 138778, 2719 .hdisplay = 1920, 2720 .hsync_start = 1920 + 24, 2721 .hsync_end = 1920 + 24 + 48, 2722 .htotal = 1920 + 24 + 48 + 88, 2723 .vdisplay = 1080, 2724 .vsync_start = 1080 + 3, 2725 .vsync_end = 1080 + 3 + 12, 2726 .vtotal = 1080 + 3 + 12 + 17, 2727 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2728 }; 2729 2730 static const struct panel_desc ivo_m133nwf4_r0 = { 2731 .modes = &ivo_m133nwf4_r0_mode, 2732 .num_modes = 1, 2733 .bpc = 8, 2734 .size = { 2735 .width = 294, 2736 .height = 165, 2737 }, 2738 .delay = { 2739 .hpd_absent_delay = 200, 2740 .unprepare = 500, 2741 }, 2742 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2743 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 2744 .connector_type = DRM_MODE_CONNECTOR_eDP, 2745 }; 2746 2747 static const struct drm_display_mode kingdisplay_kd116n21_30nv_a010_mode = { 2748 .clock = 81000, 2749 .hdisplay = 1366, 2750 .hsync_start = 1366 + 40, 2751 .hsync_end = 1366 + 40 + 32, 2752 .htotal = 1366 + 40 + 32 + 62, 2753 .vdisplay = 768, 2754 .vsync_start = 768 + 5, 2755 .vsync_end = 768 + 5 + 5, 2756 .vtotal = 768 + 5 + 5 + 122, 2757 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2758 }; 2759 2760 static const struct panel_desc kingdisplay_kd116n21_30nv_a010 = { 2761 .modes = &kingdisplay_kd116n21_30nv_a010_mode, 2762 .num_modes = 1, 2763 .bpc = 6, 2764 .size = { 2765 .width = 256, 2766 .height = 144, 2767 }, 2768 .delay = { 2769 .hpd_absent_delay = 200, 2770 }, 2771 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2772 .connector_type = DRM_MODE_CONNECTOR_eDP, 2773 }; 2774 2775 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2776 .pixelclock = { 5580000, 5850000, 6200000 }, 2777 .hactive = { 320, 320, 320 }, 2778 .hfront_porch = { 30, 30, 30 }, 2779 .hback_porch = { 30, 30, 30 }, 2780 .hsync_len = { 1, 5, 17 }, 2781 .vactive = { 240, 240, 240 }, 2782 .vfront_porch = { 6, 6, 6 }, 2783 .vback_porch = { 5, 5, 5 }, 2784 .vsync_len = { 1, 2, 11 }, 2785 .flags = DISPLAY_FLAGS_DE_HIGH, 2786 }; 2787 2788 static const struct panel_desc koe_tx14d24vm1bpa = { 2789 .timings = &koe_tx14d24vm1bpa_timing, 2790 .num_timings = 1, 2791 .bpc = 6, 2792 .size = { 2793 .width = 115, 2794 .height = 86, 2795 }, 2796 }; 2797 2798 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2799 .pixelclock = { 151820000, 156720000, 159780000 }, 2800 .hactive = { 1920, 1920, 1920 }, 2801 .hfront_porch = { 105, 130, 142 }, 2802 .hback_porch = { 45, 70, 82 }, 2803 .hsync_len = { 30, 30, 30 }, 2804 .vactive = { 1200, 1200, 1200}, 2805 .vfront_porch = { 3, 5, 10 }, 2806 .vback_porch = { 2, 5, 10 }, 2807 .vsync_len = { 5, 5, 5 }, 2808 }; 2809 2810 static const struct panel_desc koe_tx26d202vm0bwa = { 2811 .timings = &koe_tx26d202vm0bwa_timing, 2812 .num_timings = 1, 2813 .bpc = 8, 2814 .size = { 2815 .width = 217, 2816 .height = 136, 2817 }, 2818 .delay = { 2819 .prepare = 1000, 2820 .enable = 1000, 2821 .unprepare = 1000, 2822 .disable = 1000, 2823 }, 2824 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2825 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2826 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2827 }; 2828 2829 static const struct display_timing koe_tx31d200vm0baa_timing = { 2830 .pixelclock = { 39600000, 43200000, 48000000 }, 2831 .hactive = { 1280, 1280, 1280 }, 2832 .hfront_porch = { 16, 36, 56 }, 2833 .hback_porch = { 16, 36, 56 }, 2834 .hsync_len = { 8, 8, 8 }, 2835 .vactive = { 480, 480, 480 }, 2836 .vfront_porch = { 6, 21, 33 }, 2837 .vback_porch = { 6, 21, 33 }, 2838 .vsync_len = { 8, 8, 8 }, 2839 .flags = DISPLAY_FLAGS_DE_HIGH, 2840 }; 2841 2842 static const struct panel_desc koe_tx31d200vm0baa = { 2843 .timings = &koe_tx31d200vm0baa_timing, 2844 .num_timings = 1, 2845 .bpc = 6, 2846 .size = { 2847 .width = 292, 2848 .height = 109, 2849 }, 2850 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2851 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2852 }; 2853 2854 static const struct display_timing kyo_tcg121xglp_timing = { 2855 .pixelclock = { 52000000, 65000000, 71000000 }, 2856 .hactive = { 1024, 1024, 1024 }, 2857 .hfront_porch = { 2, 2, 2 }, 2858 .hback_porch = { 2, 2, 2 }, 2859 .hsync_len = { 86, 124, 244 }, 2860 .vactive = { 768, 768, 768 }, 2861 .vfront_porch = { 2, 2, 2 }, 2862 .vback_porch = { 2, 2, 2 }, 2863 .vsync_len = { 6, 34, 73 }, 2864 .flags = DISPLAY_FLAGS_DE_HIGH, 2865 }; 2866 2867 static const struct panel_desc kyo_tcg121xglp = { 2868 .timings = &kyo_tcg121xglp_timing, 2869 .num_timings = 1, 2870 .bpc = 8, 2871 .size = { 2872 .width = 246, 2873 .height = 184, 2874 }, 2875 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2876 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2877 }; 2878 2879 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2880 .clock = 7000, 2881 .hdisplay = 320, 2882 .hsync_start = 320 + 20, 2883 .hsync_end = 320 + 20 + 30, 2884 .htotal = 320 + 20 + 30 + 38, 2885 .vdisplay = 240, 2886 .vsync_start = 240 + 4, 2887 .vsync_end = 240 + 4 + 3, 2888 .vtotal = 240 + 4 + 3 + 15, 2889 }; 2890 2891 static const struct panel_desc lemaker_bl035_rgb_002 = { 2892 .modes = &lemaker_bl035_rgb_002_mode, 2893 .num_modes = 1, 2894 .size = { 2895 .width = 70, 2896 .height = 52, 2897 }, 2898 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2899 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2900 }; 2901 2902 static const struct drm_display_mode lg_lb070wv8_mode = { 2903 .clock = 33246, 2904 .hdisplay = 800, 2905 .hsync_start = 800 + 88, 2906 .hsync_end = 800 + 88 + 80, 2907 .htotal = 800 + 88 + 80 + 88, 2908 .vdisplay = 480, 2909 .vsync_start = 480 + 10, 2910 .vsync_end = 480 + 10 + 25, 2911 .vtotal = 480 + 10 + 25 + 10, 2912 }; 2913 2914 static const struct panel_desc lg_lb070wv8 = { 2915 .modes = &lg_lb070wv8_mode, 2916 .num_modes = 1, 2917 .bpc = 8, 2918 .size = { 2919 .width = 151, 2920 .height = 91, 2921 }, 2922 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2923 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2924 }; 2925 2926 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = { 2927 .clock = 200000, 2928 .hdisplay = 1536, 2929 .hsync_start = 1536 + 12, 2930 .hsync_end = 1536 + 12 + 16, 2931 .htotal = 1536 + 12 + 16 + 48, 2932 .vdisplay = 2048, 2933 .vsync_start = 2048 + 8, 2934 .vsync_end = 2048 + 8 + 4, 2935 .vtotal = 2048 + 8 + 4 + 8, 2936 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2937 }; 2938 2939 static const struct panel_desc lg_lp079qx1_sp0v = { 2940 .modes = &lg_lp079qx1_sp0v_mode, 2941 .num_modes = 1, 2942 .size = { 2943 .width = 129, 2944 .height = 171, 2945 }, 2946 }; 2947 2948 static const struct drm_display_mode lg_lp097qx1_spa1_mode = { 2949 .clock = 205210, 2950 .hdisplay = 2048, 2951 .hsync_start = 2048 + 150, 2952 .hsync_end = 2048 + 150 + 5, 2953 .htotal = 2048 + 150 + 5 + 5, 2954 .vdisplay = 1536, 2955 .vsync_start = 1536 + 3, 2956 .vsync_end = 1536 + 3 + 1, 2957 .vtotal = 1536 + 3 + 1 + 9, 2958 }; 2959 2960 static const struct panel_desc lg_lp097qx1_spa1 = { 2961 .modes = &lg_lp097qx1_spa1_mode, 2962 .num_modes = 1, 2963 .size = { 2964 .width = 208, 2965 .height = 147, 2966 }, 2967 }; 2968 2969 static const struct drm_display_mode lg_lp120up1_mode = { 2970 .clock = 162300, 2971 .hdisplay = 1920, 2972 .hsync_start = 1920 + 40, 2973 .hsync_end = 1920 + 40 + 40, 2974 .htotal = 1920 + 40 + 40+ 80, 2975 .vdisplay = 1280, 2976 .vsync_start = 1280 + 4, 2977 .vsync_end = 1280 + 4 + 4, 2978 .vtotal = 1280 + 4 + 4 + 12, 2979 }; 2980 2981 static const struct panel_desc lg_lp120up1 = { 2982 .modes = &lg_lp120up1_mode, 2983 .num_modes = 1, 2984 .bpc = 8, 2985 .size = { 2986 .width = 267, 2987 .height = 183, 2988 }, 2989 .connector_type = DRM_MODE_CONNECTOR_eDP, 2990 }; 2991 2992 static const struct drm_display_mode lg_lp129qe_mode = { 2993 .clock = 285250, 2994 .hdisplay = 2560, 2995 .hsync_start = 2560 + 48, 2996 .hsync_end = 2560 + 48 + 32, 2997 .htotal = 2560 + 48 + 32 + 80, 2998 .vdisplay = 1700, 2999 .vsync_start = 1700 + 3, 3000 .vsync_end = 1700 + 3 + 10, 3001 .vtotal = 1700 + 3 + 10 + 36, 3002 }; 3003 3004 static const struct panel_desc lg_lp129qe = { 3005 .modes = &lg_lp129qe_mode, 3006 .num_modes = 1, 3007 .bpc = 8, 3008 .size = { 3009 .width = 272, 3010 .height = 181, 3011 }, 3012 }; 3013 3014 static const struct display_timing logictechno_lt161010_2nh_timing = { 3015 .pixelclock = { 26400000, 33300000, 46800000 }, 3016 .hactive = { 800, 800, 800 }, 3017 .hfront_porch = { 16, 210, 354 }, 3018 .hback_porch = { 46, 46, 46 }, 3019 .hsync_len = { 1, 20, 40 }, 3020 .vactive = { 480, 480, 480 }, 3021 .vfront_porch = { 7, 22, 147 }, 3022 .vback_porch = { 23, 23, 23 }, 3023 .vsync_len = { 1, 10, 20 }, 3024 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3025 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3026 DISPLAY_FLAGS_SYNC_POSEDGE, 3027 }; 3028 3029 static const struct panel_desc logictechno_lt161010_2nh = { 3030 .timings = &logictechno_lt161010_2nh_timing, 3031 .num_timings = 1, 3032 .size = { 3033 .width = 154, 3034 .height = 86, 3035 }, 3036 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3037 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3038 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3039 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3040 .connector_type = DRM_MODE_CONNECTOR_DPI, 3041 }; 3042 3043 static const struct display_timing logictechno_lt170410_2whc_timing = { 3044 .pixelclock = { 68900000, 71100000, 73400000 }, 3045 .hactive = { 1280, 1280, 1280 }, 3046 .hfront_porch = { 23, 60, 71 }, 3047 .hback_porch = { 23, 60, 71 }, 3048 .hsync_len = { 15, 40, 47 }, 3049 .vactive = { 800, 800, 800 }, 3050 .vfront_porch = { 5, 7, 10 }, 3051 .vback_porch = { 5, 7, 10 }, 3052 .vsync_len = { 6, 9, 12 }, 3053 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3054 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3055 DISPLAY_FLAGS_SYNC_POSEDGE, 3056 }; 3057 3058 static const struct panel_desc logictechno_lt170410_2whc = { 3059 .timings = &logictechno_lt170410_2whc_timing, 3060 .num_timings = 1, 3061 .size = { 3062 .width = 217, 3063 .height = 136, 3064 }, 3065 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3066 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3067 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3068 }; 3069 3070 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3071 .clock = 30400, 3072 .hdisplay = 800, 3073 .hsync_start = 800 + 0, 3074 .hsync_end = 800 + 1, 3075 .htotal = 800 + 0 + 1 + 160, 3076 .vdisplay = 480, 3077 .vsync_start = 480 + 0, 3078 .vsync_end = 480 + 48 + 1, 3079 .vtotal = 480 + 48 + 1 + 0, 3080 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3081 }; 3082 3083 static const struct drm_display_mode logicpd_type_28_mode = { 3084 .clock = 9107, 3085 .hdisplay = 480, 3086 .hsync_start = 480 + 3, 3087 .hsync_end = 480 + 3 + 42, 3088 .htotal = 480 + 3 + 42 + 2, 3089 3090 .vdisplay = 272, 3091 .vsync_start = 272 + 2, 3092 .vsync_end = 272 + 2 + 11, 3093 .vtotal = 272 + 2 + 11 + 3, 3094 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3095 }; 3096 3097 static const struct panel_desc logicpd_type_28 = { 3098 .modes = &logicpd_type_28_mode, 3099 .num_modes = 1, 3100 .bpc = 8, 3101 .size = { 3102 .width = 105, 3103 .height = 67, 3104 }, 3105 .delay = { 3106 .prepare = 200, 3107 .enable = 200, 3108 .unprepare = 200, 3109 .disable = 200, 3110 }, 3111 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3112 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3113 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3114 .connector_type = DRM_MODE_CONNECTOR_DPI, 3115 }; 3116 3117 static const struct panel_desc mitsubishi_aa070mc01 = { 3118 .modes = &mitsubishi_aa070mc01_mode, 3119 .num_modes = 1, 3120 .bpc = 8, 3121 .size = { 3122 .width = 152, 3123 .height = 91, 3124 }, 3125 3126 .delay = { 3127 .enable = 200, 3128 .unprepare = 200, 3129 .disable = 400, 3130 }, 3131 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3132 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3133 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3134 }; 3135 3136 static const struct display_timing nec_nl12880bc20_05_timing = { 3137 .pixelclock = { 67000000, 71000000, 75000000 }, 3138 .hactive = { 1280, 1280, 1280 }, 3139 .hfront_porch = { 2, 30, 30 }, 3140 .hback_porch = { 6, 100, 100 }, 3141 .hsync_len = { 2, 30, 30 }, 3142 .vactive = { 800, 800, 800 }, 3143 .vfront_porch = { 5, 5, 5 }, 3144 .vback_porch = { 11, 11, 11 }, 3145 .vsync_len = { 7, 7, 7 }, 3146 }; 3147 3148 static const struct panel_desc nec_nl12880bc20_05 = { 3149 .timings = &nec_nl12880bc20_05_timing, 3150 .num_timings = 1, 3151 .bpc = 8, 3152 .size = { 3153 .width = 261, 3154 .height = 163, 3155 }, 3156 .delay = { 3157 .enable = 50, 3158 .disable = 50, 3159 }, 3160 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3161 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3162 }; 3163 3164 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3165 .clock = 10870, 3166 .hdisplay = 480, 3167 .hsync_start = 480 + 2, 3168 .hsync_end = 480 + 2 + 41, 3169 .htotal = 480 + 2 + 41 + 2, 3170 .vdisplay = 272, 3171 .vsync_start = 272 + 2, 3172 .vsync_end = 272 + 2 + 4, 3173 .vtotal = 272 + 2 + 4 + 2, 3174 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3175 }; 3176 3177 static const struct panel_desc nec_nl4827hc19_05b = { 3178 .modes = &nec_nl4827hc19_05b_mode, 3179 .num_modes = 1, 3180 .bpc = 8, 3181 .size = { 3182 .width = 95, 3183 .height = 54, 3184 }, 3185 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3186 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3187 }; 3188 3189 static const struct drm_display_mode netron_dy_e231732_mode = { 3190 .clock = 66000, 3191 .hdisplay = 1024, 3192 .hsync_start = 1024 + 160, 3193 .hsync_end = 1024 + 160 + 70, 3194 .htotal = 1024 + 160 + 70 + 90, 3195 .vdisplay = 600, 3196 .vsync_start = 600 + 127, 3197 .vsync_end = 600 + 127 + 20, 3198 .vtotal = 600 + 127 + 20 + 3, 3199 }; 3200 3201 static const struct panel_desc netron_dy_e231732 = { 3202 .modes = &netron_dy_e231732_mode, 3203 .num_modes = 1, 3204 .size = { 3205 .width = 154, 3206 .height = 87, 3207 }, 3208 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3209 }; 3210 3211 static const struct drm_display_mode neweast_wjfh116008a_modes[] = { 3212 { 3213 .clock = 138500, 3214 .hdisplay = 1920, 3215 .hsync_start = 1920 + 48, 3216 .hsync_end = 1920 + 48 + 32, 3217 .htotal = 1920 + 48 + 32 + 80, 3218 .vdisplay = 1080, 3219 .vsync_start = 1080 + 3, 3220 .vsync_end = 1080 + 3 + 5, 3221 .vtotal = 1080 + 3 + 5 + 23, 3222 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3223 }, { 3224 .clock = 110920, 3225 .hdisplay = 1920, 3226 .hsync_start = 1920 + 48, 3227 .hsync_end = 1920 + 48 + 32, 3228 .htotal = 1920 + 48 + 32 + 80, 3229 .vdisplay = 1080, 3230 .vsync_start = 1080 + 3, 3231 .vsync_end = 1080 + 3 + 5, 3232 .vtotal = 1080 + 3 + 5 + 23, 3233 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3234 } 3235 }; 3236 3237 static const struct panel_desc neweast_wjfh116008a = { 3238 .modes = neweast_wjfh116008a_modes, 3239 .num_modes = 2, 3240 .bpc = 6, 3241 .size = { 3242 .width = 260, 3243 .height = 150, 3244 }, 3245 .delay = { 3246 .prepare = 110, 3247 .enable = 20, 3248 .unprepare = 500, 3249 }, 3250 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3251 .connector_type = DRM_MODE_CONNECTOR_eDP, 3252 }; 3253 3254 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3255 .clock = 9000, 3256 .hdisplay = 480, 3257 .hsync_start = 480 + 2, 3258 .hsync_end = 480 + 2 + 41, 3259 .htotal = 480 + 2 + 41 + 2, 3260 .vdisplay = 272, 3261 .vsync_start = 272 + 2, 3262 .vsync_end = 272 + 2 + 10, 3263 .vtotal = 272 + 2 + 10 + 2, 3264 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3265 }; 3266 3267 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3268 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3269 .num_modes = 1, 3270 .bpc = 8, 3271 .size = { 3272 .width = 95, 3273 .height = 54, 3274 }, 3275 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3276 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3277 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3278 .connector_type = DRM_MODE_CONNECTOR_DPI, 3279 }; 3280 3281 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3282 .pixelclock = { 130000000, 148350000, 163000000 }, 3283 .hactive = { 1920, 1920, 1920 }, 3284 .hfront_porch = { 80, 100, 100 }, 3285 .hback_porch = { 100, 120, 120 }, 3286 .hsync_len = { 50, 60, 60 }, 3287 .vactive = { 1080, 1080, 1080 }, 3288 .vfront_porch = { 12, 30, 30 }, 3289 .vback_porch = { 4, 10, 10 }, 3290 .vsync_len = { 4, 5, 5 }, 3291 }; 3292 3293 static const struct panel_desc nlt_nl192108ac18_02d = { 3294 .timings = &nlt_nl192108ac18_02d_timing, 3295 .num_timings = 1, 3296 .bpc = 8, 3297 .size = { 3298 .width = 344, 3299 .height = 194, 3300 }, 3301 .delay = { 3302 .unprepare = 500, 3303 }, 3304 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3305 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3306 }; 3307 3308 static const struct drm_display_mode nvd_9128_mode = { 3309 .clock = 29500, 3310 .hdisplay = 800, 3311 .hsync_start = 800 + 130, 3312 .hsync_end = 800 + 130 + 98, 3313 .htotal = 800 + 0 + 130 + 98, 3314 .vdisplay = 480, 3315 .vsync_start = 480 + 10, 3316 .vsync_end = 480 + 10 + 50, 3317 .vtotal = 480 + 0 + 10 + 50, 3318 }; 3319 3320 static const struct panel_desc nvd_9128 = { 3321 .modes = &nvd_9128_mode, 3322 .num_modes = 1, 3323 .bpc = 8, 3324 .size = { 3325 .width = 156, 3326 .height = 88, 3327 }, 3328 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3329 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3330 }; 3331 3332 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3333 .pixelclock = { 30000000, 30000000, 40000000 }, 3334 .hactive = { 800, 800, 800 }, 3335 .hfront_porch = { 40, 40, 40 }, 3336 .hback_porch = { 40, 40, 40 }, 3337 .hsync_len = { 1, 48, 48 }, 3338 .vactive = { 480, 480, 480 }, 3339 .vfront_porch = { 13, 13, 13 }, 3340 .vback_porch = { 29, 29, 29 }, 3341 .vsync_len = { 3, 3, 3 }, 3342 .flags = DISPLAY_FLAGS_DE_HIGH, 3343 }; 3344 3345 static const struct panel_desc okaya_rs800480t_7x0gp = { 3346 .timings = &okaya_rs800480t_7x0gp_timing, 3347 .num_timings = 1, 3348 .bpc = 6, 3349 .size = { 3350 .width = 154, 3351 .height = 87, 3352 }, 3353 .delay = { 3354 .prepare = 41, 3355 .enable = 50, 3356 .unprepare = 41, 3357 .disable = 50, 3358 }, 3359 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3360 }; 3361 3362 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3363 .clock = 9000, 3364 .hdisplay = 480, 3365 .hsync_start = 480 + 5, 3366 .hsync_end = 480 + 5 + 30, 3367 .htotal = 480 + 5 + 30 + 10, 3368 .vdisplay = 272, 3369 .vsync_start = 272 + 8, 3370 .vsync_end = 272 + 8 + 5, 3371 .vtotal = 272 + 8 + 5 + 3, 3372 }; 3373 3374 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3375 .modes = &olimex_lcd_olinuxino_43ts_mode, 3376 .num_modes = 1, 3377 .size = { 3378 .width = 95, 3379 .height = 54, 3380 }, 3381 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3382 }; 3383 3384 /* 3385 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3386 * pixel clocks, but this is the timing that was being used in the Adafruit 3387 * installation instructions. 3388 */ 3389 static const struct drm_display_mode ontat_yx700wv03_mode = { 3390 .clock = 29500, 3391 .hdisplay = 800, 3392 .hsync_start = 824, 3393 .hsync_end = 896, 3394 .htotal = 992, 3395 .vdisplay = 480, 3396 .vsync_start = 483, 3397 .vsync_end = 493, 3398 .vtotal = 500, 3399 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3400 }; 3401 3402 /* 3403 * Specification at: 3404 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3405 */ 3406 static const struct panel_desc ontat_yx700wv03 = { 3407 .modes = &ontat_yx700wv03_mode, 3408 .num_modes = 1, 3409 .bpc = 8, 3410 .size = { 3411 .width = 154, 3412 .height = 83, 3413 }, 3414 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3415 }; 3416 3417 static const struct drm_display_mode ortustech_com37h3m_mode = { 3418 .clock = 22230, 3419 .hdisplay = 480, 3420 .hsync_start = 480 + 40, 3421 .hsync_end = 480 + 40 + 10, 3422 .htotal = 480 + 40 + 10 + 40, 3423 .vdisplay = 640, 3424 .vsync_start = 640 + 4, 3425 .vsync_end = 640 + 4 + 2, 3426 .vtotal = 640 + 4 + 2 + 4, 3427 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3428 }; 3429 3430 static const struct panel_desc ortustech_com37h3m = { 3431 .modes = &ortustech_com37h3m_mode, 3432 .num_modes = 1, 3433 .bpc = 8, 3434 .size = { 3435 .width = 56, /* 56.16mm */ 3436 .height = 75, /* 74.88mm */ 3437 }, 3438 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3439 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3440 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3441 }; 3442 3443 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3444 .clock = 25000, 3445 .hdisplay = 480, 3446 .hsync_start = 480 + 10, 3447 .hsync_end = 480 + 10 + 10, 3448 .htotal = 480 + 10 + 10 + 15, 3449 .vdisplay = 800, 3450 .vsync_start = 800 + 3, 3451 .vsync_end = 800 + 3 + 3, 3452 .vtotal = 800 + 3 + 3 + 3, 3453 }; 3454 3455 static const struct panel_desc ortustech_com43h4m85ulc = { 3456 .modes = &ortustech_com43h4m85ulc_mode, 3457 .num_modes = 1, 3458 .bpc = 6, 3459 .size = { 3460 .width = 56, 3461 .height = 93, 3462 }, 3463 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3464 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3465 .connector_type = DRM_MODE_CONNECTOR_DPI, 3466 }; 3467 3468 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3469 .clock = 33000, 3470 .hdisplay = 800, 3471 .hsync_start = 800 + 210, 3472 .hsync_end = 800 + 210 + 30, 3473 .htotal = 800 + 210 + 30 + 16, 3474 .vdisplay = 480, 3475 .vsync_start = 480 + 22, 3476 .vsync_end = 480 + 22 + 13, 3477 .vtotal = 480 + 22 + 13 + 10, 3478 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3479 }; 3480 3481 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3482 .modes = &osddisplays_osd070t1718_19ts_mode, 3483 .num_modes = 1, 3484 .bpc = 8, 3485 .size = { 3486 .width = 152, 3487 .height = 91, 3488 }, 3489 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3490 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3491 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3492 .connector_type = DRM_MODE_CONNECTOR_DPI, 3493 }; 3494 3495 static const struct drm_display_mode pda_91_00156_a0_mode = { 3496 .clock = 33300, 3497 .hdisplay = 800, 3498 .hsync_start = 800 + 1, 3499 .hsync_end = 800 + 1 + 64, 3500 .htotal = 800 + 1 + 64 + 64, 3501 .vdisplay = 480, 3502 .vsync_start = 480 + 1, 3503 .vsync_end = 480 + 1 + 23, 3504 .vtotal = 480 + 1 + 23 + 22, 3505 }; 3506 3507 static const struct panel_desc pda_91_00156_a0 = { 3508 .modes = &pda_91_00156_a0_mode, 3509 .num_modes = 1, 3510 .size = { 3511 .width = 152, 3512 .height = 91, 3513 }, 3514 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3515 }; 3516 3517 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3518 .clock = 24750, 3519 .hdisplay = 800, 3520 .hsync_start = 800 + 54, 3521 .hsync_end = 800 + 54 + 2, 3522 .htotal = 800 + 54 + 2 + 44, 3523 .vdisplay = 480, 3524 .vsync_start = 480 + 49, 3525 .vsync_end = 480 + 49 + 2, 3526 .vtotal = 480 + 49 + 2 + 22, 3527 }; 3528 3529 static const struct panel_desc powertip_ph800480t013_idf02 = { 3530 .modes = &powertip_ph800480t013_idf02_mode, 3531 .num_modes = 1, 3532 .size = { 3533 .width = 152, 3534 .height = 91, 3535 }, 3536 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3537 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3538 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3539 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3540 .connector_type = DRM_MODE_CONNECTOR_DPI, 3541 }; 3542 3543 static const struct drm_display_mode qd43003c0_40_mode = { 3544 .clock = 9000, 3545 .hdisplay = 480, 3546 .hsync_start = 480 + 8, 3547 .hsync_end = 480 + 8 + 4, 3548 .htotal = 480 + 8 + 4 + 39, 3549 .vdisplay = 272, 3550 .vsync_start = 272 + 4, 3551 .vsync_end = 272 + 4 + 10, 3552 .vtotal = 272 + 4 + 10 + 2, 3553 }; 3554 3555 static const struct panel_desc qd43003c0_40 = { 3556 .modes = &qd43003c0_40_mode, 3557 .num_modes = 1, 3558 .bpc = 8, 3559 .size = { 3560 .width = 95, 3561 .height = 53, 3562 }, 3563 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3564 }; 3565 3566 static const struct display_timing rocktech_rk070er9427_timing = { 3567 .pixelclock = { 26400000, 33300000, 46800000 }, 3568 .hactive = { 800, 800, 800 }, 3569 .hfront_porch = { 16, 210, 354 }, 3570 .hback_porch = { 46, 46, 46 }, 3571 .hsync_len = { 1, 1, 1 }, 3572 .vactive = { 480, 480, 480 }, 3573 .vfront_porch = { 7, 22, 147 }, 3574 .vback_porch = { 23, 23, 23 }, 3575 .vsync_len = { 1, 1, 1 }, 3576 .flags = DISPLAY_FLAGS_DE_HIGH, 3577 }; 3578 3579 static const struct panel_desc rocktech_rk070er9427 = { 3580 .timings = &rocktech_rk070er9427_timing, 3581 .num_timings = 1, 3582 .bpc = 6, 3583 .size = { 3584 .width = 154, 3585 .height = 86, 3586 }, 3587 .delay = { 3588 .prepare = 41, 3589 .enable = 50, 3590 .unprepare = 41, 3591 .disable = 50, 3592 }, 3593 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3594 }; 3595 3596 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3597 .clock = 71100, 3598 .hdisplay = 1280, 3599 .hsync_start = 1280 + 48, 3600 .hsync_end = 1280 + 48 + 32, 3601 .htotal = 1280 + 48 + 32 + 80, 3602 .vdisplay = 800, 3603 .vsync_start = 800 + 2, 3604 .vsync_end = 800 + 2 + 5, 3605 .vtotal = 800 + 2 + 5 + 16, 3606 }; 3607 3608 static const struct panel_desc rocktech_rk101ii01d_ct = { 3609 .modes = &rocktech_rk101ii01d_ct_mode, 3610 .num_modes = 1, 3611 .size = { 3612 .width = 217, 3613 .height = 136, 3614 }, 3615 .delay = { 3616 .prepare = 50, 3617 .disable = 50, 3618 }, 3619 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3620 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3621 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3622 }; 3623 3624 static const struct drm_display_mode samsung_atna33xc20_mode = { 3625 .clock = 138770, 3626 .hdisplay = 1920, 3627 .hsync_start = 1920 + 48, 3628 .hsync_end = 1920 + 48 + 32, 3629 .htotal = 1920 + 48 + 32 + 80, 3630 .vdisplay = 1080, 3631 .vsync_start = 1080 + 8, 3632 .vsync_end = 1080 + 8 + 8, 3633 .vtotal = 1080 + 8 + 8 + 16, 3634 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3635 }; 3636 3637 static const struct panel_desc samsung_atna33xc20 = { 3638 .modes = &samsung_atna33xc20_mode, 3639 .num_modes = 1, 3640 .bpc = 10, 3641 .size = { 3642 .width = 294, 3643 .height = 165, 3644 }, 3645 .delay = { 3646 .disable_to_power_off = 200, 3647 .power_to_enable = 400, 3648 .hpd_absent_delay = 200, 3649 .unprepare = 500, 3650 }, 3651 .connector_type = DRM_MODE_CONNECTOR_eDP, 3652 }; 3653 3654 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = { 3655 .clock = 271560, 3656 .hdisplay = 2560, 3657 .hsync_start = 2560 + 48, 3658 .hsync_end = 2560 + 48 + 32, 3659 .htotal = 2560 + 48 + 32 + 80, 3660 .vdisplay = 1600, 3661 .vsync_start = 1600 + 2, 3662 .vsync_end = 1600 + 2 + 5, 3663 .vtotal = 1600 + 2 + 5 + 57, 3664 }; 3665 3666 static const struct panel_desc samsung_lsn122dl01_c01 = { 3667 .modes = &samsung_lsn122dl01_c01_mode, 3668 .num_modes = 1, 3669 .size = { 3670 .width = 263, 3671 .height = 164, 3672 }, 3673 }; 3674 3675 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3676 .clock = 54030, 3677 .hdisplay = 1024, 3678 .hsync_start = 1024 + 24, 3679 .hsync_end = 1024 + 24 + 136, 3680 .htotal = 1024 + 24 + 136 + 160, 3681 .vdisplay = 600, 3682 .vsync_start = 600 + 3, 3683 .vsync_end = 600 + 3 + 6, 3684 .vtotal = 600 + 3 + 6 + 61, 3685 }; 3686 3687 static const struct panel_desc samsung_ltn101nt05 = { 3688 .modes = &samsung_ltn101nt05_mode, 3689 .num_modes = 1, 3690 .bpc = 6, 3691 .size = { 3692 .width = 223, 3693 .height = 125, 3694 }, 3695 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3696 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3697 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3698 }; 3699 3700 static const struct drm_display_mode samsung_ltn140at29_301_mode = { 3701 .clock = 76300, 3702 .hdisplay = 1366, 3703 .hsync_start = 1366 + 64, 3704 .hsync_end = 1366 + 64 + 48, 3705 .htotal = 1366 + 64 + 48 + 128, 3706 .vdisplay = 768, 3707 .vsync_start = 768 + 2, 3708 .vsync_end = 768 + 2 + 5, 3709 .vtotal = 768 + 2 + 5 + 17, 3710 }; 3711 3712 static const struct panel_desc samsung_ltn140at29_301 = { 3713 .modes = &samsung_ltn140at29_301_mode, 3714 .num_modes = 1, 3715 .bpc = 6, 3716 .size = { 3717 .width = 320, 3718 .height = 187, 3719 }, 3720 }; 3721 3722 static const struct display_timing satoz_sat050at40h12r2_timing = { 3723 .pixelclock = {33300000, 33300000, 50000000}, 3724 .hactive = {800, 800, 800}, 3725 .hfront_porch = {16, 210, 354}, 3726 .hback_porch = {46, 46, 46}, 3727 .hsync_len = {1, 1, 40}, 3728 .vactive = {480, 480, 480}, 3729 .vfront_porch = {7, 22, 147}, 3730 .vback_porch = {23, 23, 23}, 3731 .vsync_len = {1, 1, 20}, 3732 }; 3733 3734 static const struct panel_desc satoz_sat050at40h12r2 = { 3735 .timings = &satoz_sat050at40h12r2_timing, 3736 .num_timings = 1, 3737 .bpc = 8, 3738 .size = { 3739 .width = 108, 3740 .height = 65, 3741 }, 3742 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3743 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3744 }; 3745 3746 static const struct drm_display_mode sharp_ld_d5116z01b_mode = { 3747 .clock = 168480, 3748 .hdisplay = 1920, 3749 .hsync_start = 1920 + 48, 3750 .hsync_end = 1920 + 48 + 32, 3751 .htotal = 1920 + 48 + 32 + 80, 3752 .vdisplay = 1280, 3753 .vsync_start = 1280 + 3, 3754 .vsync_end = 1280 + 3 + 10, 3755 .vtotal = 1280 + 3 + 10 + 57, 3756 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3757 }; 3758 3759 static const struct panel_desc sharp_ld_d5116z01b = { 3760 .modes = &sharp_ld_d5116z01b_mode, 3761 .num_modes = 1, 3762 .bpc = 8, 3763 .size = { 3764 .width = 260, 3765 .height = 120, 3766 }, 3767 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3768 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB, 3769 }; 3770 3771 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3772 .clock = 33260, 3773 .hdisplay = 800, 3774 .hsync_start = 800 + 64, 3775 .hsync_end = 800 + 64 + 128, 3776 .htotal = 800 + 64 + 128 + 64, 3777 .vdisplay = 480, 3778 .vsync_start = 480 + 8, 3779 .vsync_end = 480 + 8 + 2, 3780 .vtotal = 480 + 8 + 2 + 35, 3781 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3782 }; 3783 3784 static const struct panel_desc sharp_lq070y3dg3b = { 3785 .modes = &sharp_lq070y3dg3b_mode, 3786 .num_modes = 1, 3787 .bpc = 8, 3788 .size = { 3789 .width = 152, /* 152.4mm */ 3790 .height = 91, /* 91.4mm */ 3791 }, 3792 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3793 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3794 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3795 }; 3796 3797 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3798 .clock = 5500, 3799 .hdisplay = 240, 3800 .hsync_start = 240 + 16, 3801 .hsync_end = 240 + 16 + 7, 3802 .htotal = 240 + 16 + 7 + 5, 3803 .vdisplay = 320, 3804 .vsync_start = 320 + 9, 3805 .vsync_end = 320 + 9 + 1, 3806 .vtotal = 320 + 9 + 1 + 7, 3807 }; 3808 3809 static const struct panel_desc sharp_lq035q7db03 = { 3810 .modes = &sharp_lq035q7db03_mode, 3811 .num_modes = 1, 3812 .bpc = 6, 3813 .size = { 3814 .width = 54, 3815 .height = 72, 3816 }, 3817 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3818 }; 3819 3820 static const struct display_timing sharp_lq101k1ly04_timing = { 3821 .pixelclock = { 60000000, 65000000, 80000000 }, 3822 .hactive = { 1280, 1280, 1280 }, 3823 .hfront_porch = { 20, 20, 20 }, 3824 .hback_porch = { 20, 20, 20 }, 3825 .hsync_len = { 10, 10, 10 }, 3826 .vactive = { 800, 800, 800 }, 3827 .vfront_porch = { 4, 4, 4 }, 3828 .vback_porch = { 4, 4, 4 }, 3829 .vsync_len = { 4, 4, 4 }, 3830 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3831 }; 3832 3833 static const struct panel_desc sharp_lq101k1ly04 = { 3834 .timings = &sharp_lq101k1ly04_timing, 3835 .num_timings = 1, 3836 .bpc = 8, 3837 .size = { 3838 .width = 217, 3839 .height = 136, 3840 }, 3841 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3842 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3843 }; 3844 3845 static const struct display_timing sharp_lq123p1jx31_timing = { 3846 .pixelclock = { 252750000, 252750000, 266604720 }, 3847 .hactive = { 2400, 2400, 2400 }, 3848 .hfront_porch = { 48, 48, 48 }, 3849 .hback_porch = { 80, 80, 84 }, 3850 .hsync_len = { 32, 32, 32 }, 3851 .vactive = { 1600, 1600, 1600 }, 3852 .vfront_porch = { 3, 3, 3 }, 3853 .vback_porch = { 33, 33, 120 }, 3854 .vsync_len = { 10, 10, 10 }, 3855 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW, 3856 }; 3857 3858 static const struct panel_desc sharp_lq123p1jx31 = { 3859 .timings = &sharp_lq123p1jx31_timing, 3860 .num_timings = 1, 3861 .bpc = 8, 3862 .size = { 3863 .width = 259, 3864 .height = 173, 3865 }, 3866 .delay = { 3867 .prepare = 110, 3868 .enable = 50, 3869 .unprepare = 550, 3870 }, 3871 }; 3872 3873 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3874 { /* 50 Hz */ 3875 .clock = 3000, 3876 .hdisplay = 240, 3877 .hsync_start = 240 + 58, 3878 .hsync_end = 240 + 58 + 1, 3879 .htotal = 240 + 58 + 1 + 1, 3880 .vdisplay = 160, 3881 .vsync_start = 160 + 24, 3882 .vsync_end = 160 + 24 + 10, 3883 .vtotal = 160 + 24 + 10 + 6, 3884 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3885 }, 3886 { /* 60 Hz */ 3887 .clock = 3000, 3888 .hdisplay = 240, 3889 .hsync_start = 240 + 8, 3890 .hsync_end = 240 + 8 + 1, 3891 .htotal = 240 + 8 + 1 + 1, 3892 .vdisplay = 160, 3893 .vsync_start = 160 + 24, 3894 .vsync_end = 160 + 24 + 10, 3895 .vtotal = 160 + 24 + 10 + 6, 3896 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3897 }, 3898 }; 3899 3900 static const struct panel_desc sharp_ls020b1dd01d = { 3901 .modes = sharp_ls020b1dd01d_modes, 3902 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3903 .bpc = 6, 3904 .size = { 3905 .width = 42, 3906 .height = 28, 3907 }, 3908 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3909 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3910 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3911 | DRM_BUS_FLAG_SHARP_SIGNALS, 3912 }; 3913 3914 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3915 .clock = 33300, 3916 .hdisplay = 800, 3917 .hsync_start = 800 + 1, 3918 .hsync_end = 800 + 1 + 64, 3919 .htotal = 800 + 1 + 64 + 64, 3920 .vdisplay = 480, 3921 .vsync_start = 480 + 1, 3922 .vsync_end = 480 + 1 + 23, 3923 .vtotal = 480 + 1 + 23 + 22, 3924 }; 3925 3926 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3927 .modes = &shelly_sca07010_bfn_lnn_mode, 3928 .num_modes = 1, 3929 .size = { 3930 .width = 152, 3931 .height = 91, 3932 }, 3933 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3934 }; 3935 3936 static const struct drm_display_mode starry_kr070pe2t_mode = { 3937 .clock = 33000, 3938 .hdisplay = 800, 3939 .hsync_start = 800 + 209, 3940 .hsync_end = 800 + 209 + 1, 3941 .htotal = 800 + 209 + 1 + 45, 3942 .vdisplay = 480, 3943 .vsync_start = 480 + 22, 3944 .vsync_end = 480 + 22 + 1, 3945 .vtotal = 480 + 22 + 1 + 22, 3946 }; 3947 3948 static const struct panel_desc starry_kr070pe2t = { 3949 .modes = &starry_kr070pe2t_mode, 3950 .num_modes = 1, 3951 .bpc = 8, 3952 .size = { 3953 .width = 152, 3954 .height = 86, 3955 }, 3956 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3957 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3958 .connector_type = DRM_MODE_CONNECTOR_DPI, 3959 }; 3960 3961 static const struct drm_display_mode starry_kr122ea0sra_mode = { 3962 .clock = 147000, 3963 .hdisplay = 1920, 3964 .hsync_start = 1920 + 16, 3965 .hsync_end = 1920 + 16 + 16, 3966 .htotal = 1920 + 16 + 16 + 32, 3967 .vdisplay = 1200, 3968 .vsync_start = 1200 + 15, 3969 .vsync_end = 1200 + 15 + 2, 3970 .vtotal = 1200 + 15 + 2 + 18, 3971 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3972 }; 3973 3974 static const struct panel_desc starry_kr122ea0sra = { 3975 .modes = &starry_kr122ea0sra_mode, 3976 .num_modes = 1, 3977 .size = { 3978 .width = 263, 3979 .height = 164, 3980 }, 3981 .delay = { 3982 .prepare = 10 + 200, 3983 .enable = 50, 3984 .unprepare = 10 + 500, 3985 }, 3986 }; 3987 3988 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3989 .clock = 30000, 3990 .hdisplay = 800, 3991 .hsync_start = 800 + 39, 3992 .hsync_end = 800 + 39 + 47, 3993 .htotal = 800 + 39 + 47 + 39, 3994 .vdisplay = 480, 3995 .vsync_start = 480 + 13, 3996 .vsync_end = 480 + 13 + 2, 3997 .vtotal = 480 + 13 + 2 + 29, 3998 }; 3999 4000 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4001 .modes = &tfc_s9700rtwv43tr_01b_mode, 4002 .num_modes = 1, 4003 .bpc = 8, 4004 .size = { 4005 .width = 155, 4006 .height = 90, 4007 }, 4008 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4009 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4010 }; 4011 4012 static const struct display_timing tianma_tm070jdhg30_timing = { 4013 .pixelclock = { 62600000, 68200000, 78100000 }, 4014 .hactive = { 1280, 1280, 1280 }, 4015 .hfront_porch = { 15, 64, 159 }, 4016 .hback_porch = { 5, 5, 5 }, 4017 .hsync_len = { 1, 1, 256 }, 4018 .vactive = { 800, 800, 800 }, 4019 .vfront_porch = { 3, 40, 99 }, 4020 .vback_porch = { 2, 2, 2 }, 4021 .vsync_len = { 1, 1, 128 }, 4022 .flags = DISPLAY_FLAGS_DE_HIGH, 4023 }; 4024 4025 static const struct panel_desc tianma_tm070jdhg30 = { 4026 .timings = &tianma_tm070jdhg30_timing, 4027 .num_timings = 1, 4028 .bpc = 8, 4029 .size = { 4030 .width = 151, 4031 .height = 95, 4032 }, 4033 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4034 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4035 }; 4036 4037 static const struct panel_desc tianma_tm070jvhg33 = { 4038 .timings = &tianma_tm070jdhg30_timing, 4039 .num_timings = 1, 4040 .bpc = 8, 4041 .size = { 4042 .width = 150, 4043 .height = 94, 4044 }, 4045 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4046 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4047 }; 4048 4049 static const struct display_timing tianma_tm070rvhg71_timing = { 4050 .pixelclock = { 27700000, 29200000, 39600000 }, 4051 .hactive = { 800, 800, 800 }, 4052 .hfront_porch = { 12, 40, 212 }, 4053 .hback_porch = { 88, 88, 88 }, 4054 .hsync_len = { 1, 1, 40 }, 4055 .vactive = { 480, 480, 480 }, 4056 .vfront_porch = { 1, 13, 88 }, 4057 .vback_porch = { 32, 32, 32 }, 4058 .vsync_len = { 1, 1, 3 }, 4059 .flags = DISPLAY_FLAGS_DE_HIGH, 4060 }; 4061 4062 static const struct panel_desc tianma_tm070rvhg71 = { 4063 .timings = &tianma_tm070rvhg71_timing, 4064 .num_timings = 1, 4065 .bpc = 8, 4066 .size = { 4067 .width = 154, 4068 .height = 86, 4069 }, 4070 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4071 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4072 }; 4073 4074 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4075 { 4076 .clock = 10000, 4077 .hdisplay = 320, 4078 .hsync_start = 320 + 50, 4079 .hsync_end = 320 + 50 + 6, 4080 .htotal = 320 + 50 + 6 + 38, 4081 .vdisplay = 240, 4082 .vsync_start = 240 + 3, 4083 .vsync_end = 240 + 3 + 1, 4084 .vtotal = 240 + 3 + 1 + 17, 4085 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4086 }, 4087 }; 4088 4089 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4090 .modes = ti_nspire_cx_lcd_mode, 4091 .num_modes = 1, 4092 .bpc = 8, 4093 .size = { 4094 .width = 65, 4095 .height = 49, 4096 }, 4097 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4098 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4099 }; 4100 4101 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4102 { 4103 .clock = 10000, 4104 .hdisplay = 320, 4105 .hsync_start = 320 + 6, 4106 .hsync_end = 320 + 6 + 6, 4107 .htotal = 320 + 6 + 6 + 6, 4108 .vdisplay = 240, 4109 .vsync_start = 240 + 0, 4110 .vsync_end = 240 + 0 + 1, 4111 .vtotal = 240 + 0 + 1 + 0, 4112 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4113 }, 4114 }; 4115 4116 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4117 .modes = ti_nspire_classic_lcd_mode, 4118 .num_modes = 1, 4119 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4120 .bpc = 8, 4121 .size = { 4122 .width = 71, 4123 .height = 53, 4124 }, 4125 /* This is the grayscale bus format */ 4126 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4127 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4128 }; 4129 4130 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4131 .clock = 79500, 4132 .hdisplay = 1280, 4133 .hsync_start = 1280 + 192, 4134 .hsync_end = 1280 + 192 + 128, 4135 .htotal = 1280 + 192 + 128 + 64, 4136 .vdisplay = 768, 4137 .vsync_start = 768 + 20, 4138 .vsync_end = 768 + 20 + 7, 4139 .vtotal = 768 + 20 + 7 + 3, 4140 }; 4141 4142 static const struct panel_desc toshiba_lt089ac29000 = { 4143 .modes = &toshiba_lt089ac29000_mode, 4144 .num_modes = 1, 4145 .size = { 4146 .width = 194, 4147 .height = 116, 4148 }, 4149 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4150 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4151 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4152 }; 4153 4154 static const struct drm_display_mode tpk_f07a_0102_mode = { 4155 .clock = 33260, 4156 .hdisplay = 800, 4157 .hsync_start = 800 + 40, 4158 .hsync_end = 800 + 40 + 128, 4159 .htotal = 800 + 40 + 128 + 88, 4160 .vdisplay = 480, 4161 .vsync_start = 480 + 10, 4162 .vsync_end = 480 + 10 + 2, 4163 .vtotal = 480 + 10 + 2 + 33, 4164 }; 4165 4166 static const struct panel_desc tpk_f07a_0102 = { 4167 .modes = &tpk_f07a_0102_mode, 4168 .num_modes = 1, 4169 .size = { 4170 .width = 152, 4171 .height = 91, 4172 }, 4173 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4174 }; 4175 4176 static const struct drm_display_mode tpk_f10a_0102_mode = { 4177 .clock = 45000, 4178 .hdisplay = 1024, 4179 .hsync_start = 1024 + 176, 4180 .hsync_end = 1024 + 176 + 5, 4181 .htotal = 1024 + 176 + 5 + 88, 4182 .vdisplay = 600, 4183 .vsync_start = 600 + 20, 4184 .vsync_end = 600 + 20 + 5, 4185 .vtotal = 600 + 20 + 5 + 25, 4186 }; 4187 4188 static const struct panel_desc tpk_f10a_0102 = { 4189 .modes = &tpk_f10a_0102_mode, 4190 .num_modes = 1, 4191 .size = { 4192 .width = 223, 4193 .height = 125, 4194 }, 4195 }; 4196 4197 static const struct display_timing urt_umsh_8596md_timing = { 4198 .pixelclock = { 33260000, 33260000, 33260000 }, 4199 .hactive = { 800, 800, 800 }, 4200 .hfront_porch = { 41, 41, 41 }, 4201 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4202 .hsync_len = { 71, 128, 128 }, 4203 .vactive = { 480, 480, 480 }, 4204 .vfront_porch = { 10, 10, 10 }, 4205 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4206 .vsync_len = { 2, 2, 2 }, 4207 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4208 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4209 }; 4210 4211 static const struct panel_desc urt_umsh_8596md_lvds = { 4212 .timings = &urt_umsh_8596md_timing, 4213 .num_timings = 1, 4214 .bpc = 6, 4215 .size = { 4216 .width = 152, 4217 .height = 91, 4218 }, 4219 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4220 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4221 }; 4222 4223 static const struct panel_desc urt_umsh_8596md_parallel = { 4224 .timings = &urt_umsh_8596md_timing, 4225 .num_timings = 1, 4226 .bpc = 6, 4227 .size = { 4228 .width = 152, 4229 .height = 91, 4230 }, 4231 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4232 }; 4233 4234 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4235 .clock = 33333, 4236 .hdisplay = 800, 4237 .hsync_start = 800 + 210, 4238 .hsync_end = 800 + 210 + 20, 4239 .htotal = 800 + 210 + 20 + 46, 4240 .vdisplay = 480, 4241 .vsync_start = 480 + 22, 4242 .vsync_end = 480 + 22 + 10, 4243 .vtotal = 480 + 22 + 10 + 23, 4244 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4245 }; 4246 4247 static const struct panel_desc vl050_8048nt_c01 = { 4248 .modes = &vl050_8048nt_c01_mode, 4249 .num_modes = 1, 4250 .bpc = 8, 4251 .size = { 4252 .width = 120, 4253 .height = 76, 4254 }, 4255 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4256 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4257 }; 4258 4259 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4260 .clock = 6410, 4261 .hdisplay = 320, 4262 .hsync_start = 320 + 20, 4263 .hsync_end = 320 + 20 + 30, 4264 .htotal = 320 + 20 + 30 + 38, 4265 .vdisplay = 240, 4266 .vsync_start = 240 + 4, 4267 .vsync_end = 240 + 4 + 3, 4268 .vtotal = 240 + 4 + 3 + 15, 4269 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4270 }; 4271 4272 static const struct panel_desc winstar_wf35ltiacd = { 4273 .modes = &winstar_wf35ltiacd_mode, 4274 .num_modes = 1, 4275 .bpc = 8, 4276 .size = { 4277 .width = 70, 4278 .height = 53, 4279 }, 4280 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4281 }; 4282 4283 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4284 .clock = 51200, 4285 .hdisplay = 1024, 4286 .hsync_start = 1024 + 100, 4287 .hsync_end = 1024 + 100 + 100, 4288 .htotal = 1024 + 100 + 100 + 120, 4289 .vdisplay = 600, 4290 .vsync_start = 600 + 10, 4291 .vsync_end = 600 + 10 + 10, 4292 .vtotal = 600 + 10 + 10 + 15, 4293 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4294 }; 4295 4296 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4297 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4298 .num_modes = 1, 4299 .bpc = 6, 4300 .size = { 4301 .width = 154, 4302 .height = 90, 4303 }, 4304 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4305 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4306 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4307 }; 4308 4309 static const struct drm_display_mode arm_rtsm_mode[] = { 4310 { 4311 .clock = 65000, 4312 .hdisplay = 1024, 4313 .hsync_start = 1024 + 24, 4314 .hsync_end = 1024 + 24 + 136, 4315 .htotal = 1024 + 24 + 136 + 160, 4316 .vdisplay = 768, 4317 .vsync_start = 768 + 3, 4318 .vsync_end = 768 + 3 + 6, 4319 .vtotal = 768 + 3 + 6 + 29, 4320 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4321 }, 4322 }; 4323 4324 static const struct panel_desc arm_rtsm = { 4325 .modes = arm_rtsm_mode, 4326 .num_modes = 1, 4327 .bpc = 8, 4328 .size = { 4329 .width = 400, 4330 .height = 300, 4331 }, 4332 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4333 }; 4334 4335 static const struct of_device_id platform_of_match[] = { 4336 { 4337 .compatible = "ampire,am-1280800n3tzqw-t00h", 4338 .data = &ire_am_1280800n3tzqw_t00h, 4339 }, { 4340 .compatible = "ampire,am-480272h3tmqw-t01h", 4341 .data = &ire_am_480272h3tmqw_t01h, 4342 }, { 4343 .compatible = "ampire,am800480r3tmqwa1h", 4344 .data = &ire_am800480r3tmqwa1h, 4345 }, { 4346 .compatible = "arm,rtsm-display", 4347 .data = &arm_rtsm, 4348 }, { 4349 .compatible = "armadeus,st0700-adapt", 4350 .data = &armadeus_st0700_adapt, 4351 }, { 4352 .compatible = "auo,b101aw03", 4353 .data = &auo_b101aw03, 4354 }, { 4355 .compatible = "auo,b101ean01", 4356 .data = &auo_b101ean01, 4357 }, { 4358 .compatible = "auo,b101xtn01", 4359 .data = &auo_b101xtn01, 4360 }, { 4361 .compatible = "auo,b116xa01", 4362 .data = &auo_b116xak01, 4363 }, { 4364 .compatible = "auo,b116xw03", 4365 .data = &auo_b116xw03, 4366 }, { 4367 .compatible = "auo,b133htn01", 4368 .data = &auo_b133htn01, 4369 }, { 4370 .compatible = "auo,b133xtn01", 4371 .data = &auo_b133xtn01, 4372 }, { 4373 .compatible = "auo,g070vvn01", 4374 .data = &auo_g070vvn01, 4375 }, { 4376 .compatible = "auo,g101evn010", 4377 .data = &auo_g101evn010, 4378 }, { 4379 .compatible = "auo,g104sn02", 4380 .data = &auo_g104sn02, 4381 }, { 4382 .compatible = "auo,g121ean01", 4383 .data = &auo_g121ean01, 4384 }, { 4385 .compatible = "auo,g133han01", 4386 .data = &auo_g133han01, 4387 }, { 4388 .compatible = "auo,g156xtn01", 4389 .data = &auo_g156xtn01, 4390 }, { 4391 .compatible = "auo,g185han01", 4392 .data = &auo_g185han01, 4393 }, { 4394 .compatible = "auo,g190ean01", 4395 .data = &auo_g190ean01, 4396 }, { 4397 .compatible = "auo,p320hvn03", 4398 .data = &auo_p320hvn03, 4399 }, { 4400 .compatible = "auo,t215hvn01", 4401 .data = &auo_t215hvn01, 4402 }, { 4403 .compatible = "avic,tm070ddh03", 4404 .data = &avic_tm070ddh03, 4405 }, { 4406 .compatible = "bananapi,s070wv20-ct16", 4407 .data = &bananapi_s070wv20_ct16, 4408 }, { 4409 .compatible = "boe,hv070wsa-100", 4410 .data = &boe_hv070wsa 4411 }, { 4412 .compatible = "boe,nv101wxmn51", 4413 .data = &boe_nv101wxmn51, 4414 }, { 4415 .compatible = "boe,nv110wtm-n61", 4416 .data = &boe_nv110wtm_n61, 4417 }, { 4418 .compatible = "boe,nv133fhm-n61", 4419 .data = &boe_nv133fhm_n61, 4420 }, { 4421 .compatible = "boe,nv133fhm-n62", 4422 .data = &boe_nv133fhm_n61, 4423 }, { 4424 .compatible = "boe,nv140fhmn49", 4425 .data = &boe_nv140fhmn49, 4426 }, { 4427 .compatible = "cdtech,s043wq26h-ct7", 4428 .data = &cdtech_s043wq26h_ct7, 4429 }, { 4430 .compatible = "cdtech,s070pws19hp-fc21", 4431 .data = &cdtech_s070pws19hp_fc21, 4432 }, { 4433 .compatible = "cdtech,s070swv29hg-dc44", 4434 .data = &cdtech_s070swv29hg_dc44, 4435 }, { 4436 .compatible = "cdtech,s070wv95-ct16", 4437 .data = &cdtech_s070wv95_ct16, 4438 }, { 4439 .compatible = "chefree,ch101olhlwh-002", 4440 .data = &chefree_ch101olhlwh_002, 4441 }, { 4442 .compatible = "chunghwa,claa070wp03xg", 4443 .data = &chunghwa_claa070wp03xg, 4444 }, { 4445 .compatible = "chunghwa,claa101wa01a", 4446 .data = &chunghwa_claa101wa01a 4447 }, { 4448 .compatible = "chunghwa,claa101wb01", 4449 .data = &chunghwa_claa101wb01 4450 }, { 4451 .compatible = "dataimage,scf0700c48ggu18", 4452 .data = &dataimage_scf0700c48ggu18, 4453 }, { 4454 .compatible = "dlc,dlc0700yzg-1", 4455 .data = &dlc_dlc0700yzg_1, 4456 }, { 4457 .compatible = "dlc,dlc1010gig", 4458 .data = &dlc_dlc1010gig, 4459 }, { 4460 .compatible = "edt,et035012dm6", 4461 .data = &edt_et035012dm6, 4462 }, { 4463 .compatible = "edt,etm0350g0dh6", 4464 .data = &edt_etm0350g0dh6, 4465 }, { 4466 .compatible = "edt,etm043080dh6gp", 4467 .data = &edt_etm043080dh6gp, 4468 }, { 4469 .compatible = "edt,etm0430g0dh6", 4470 .data = &edt_etm0430g0dh6, 4471 }, { 4472 .compatible = "edt,et057090dhu", 4473 .data = &edt_et057090dhu, 4474 }, { 4475 .compatible = "edt,et070080dh6", 4476 .data = &edt_etm0700g0dh6, 4477 }, { 4478 .compatible = "edt,etm0700g0dh6", 4479 .data = &edt_etm0700g0dh6, 4480 }, { 4481 .compatible = "edt,etm0700g0bdh6", 4482 .data = &edt_etm0700g0bdh6, 4483 }, { 4484 .compatible = "edt,etm0700g0edh6", 4485 .data = &edt_etm0700g0bdh6, 4486 }, { 4487 .compatible = "edt,etmv570g2dhu", 4488 .data = &edt_etmv570g2dhu, 4489 }, { 4490 .compatible = "evervision,vgg804821", 4491 .data = &evervision_vgg804821, 4492 }, { 4493 .compatible = "foxlink,fl500wvr00-a0t", 4494 .data = &foxlink_fl500wvr00_a0t, 4495 }, { 4496 .compatible = "frida,frd350h54004", 4497 .data = &frida_frd350h54004, 4498 }, { 4499 .compatible = "friendlyarm,hd702e", 4500 .data = &friendlyarm_hd702e, 4501 }, { 4502 .compatible = "giantplus,gpg482739qs5", 4503 .data = &giantplus_gpg482739qs5 4504 }, { 4505 .compatible = "giantplus,gpm940b0", 4506 .data = &giantplus_gpm940b0, 4507 }, { 4508 .compatible = "hannstar,hsd070pww1", 4509 .data = &hannstar_hsd070pww1, 4510 }, { 4511 .compatible = "hannstar,hsd100pxn1", 4512 .data = &hannstar_hsd100pxn1, 4513 }, { 4514 .compatible = "hit,tx23d38vm0caa", 4515 .data = &hitachi_tx23d38vm0caa 4516 }, { 4517 .compatible = "innolux,at043tn24", 4518 .data = &innolux_at043tn24, 4519 }, { 4520 .compatible = "innolux,at070tn92", 4521 .data = &innolux_at070tn92, 4522 }, { 4523 .compatible = "innolux,g070y2-l01", 4524 .data = &innolux_g070y2_l01, 4525 }, { 4526 .compatible = "innolux,g101ice-l01", 4527 .data = &innolux_g101ice_l01 4528 }, { 4529 .compatible = "innolux,g121i1-l01", 4530 .data = &innolux_g121i1_l01 4531 }, { 4532 .compatible = "innolux,g121x1-l03", 4533 .data = &innolux_g121x1_l03, 4534 }, { 4535 .compatible = "innolux,n116bca-ea1", 4536 .data = &innolux_n116bca_ea1, 4537 }, { 4538 .compatible = "innolux,n116bge", 4539 .data = &innolux_n116bge, 4540 }, { 4541 .compatible = "innolux,n125hce-gn1", 4542 .data = &innolux_n125hce_gn1, 4543 }, { 4544 .compatible = "innolux,n156bge-l21", 4545 .data = &innolux_n156bge_l21, 4546 }, { 4547 .compatible = "innolux,p120zdg-bf1", 4548 .data = &innolux_p120zdg_bf1, 4549 }, { 4550 .compatible = "innolux,zj070na-01p", 4551 .data = &innolux_zj070na_01p, 4552 }, { 4553 .compatible = "ivo,m133nwf4-r0", 4554 .data = &ivo_m133nwf4_r0, 4555 }, { 4556 .compatible = "kingdisplay,kd116n21-30nv-a010", 4557 .data = &kingdisplay_kd116n21_30nv_a010, 4558 }, { 4559 .compatible = "koe,tx14d24vm1bpa", 4560 .data = &koe_tx14d24vm1bpa, 4561 }, { 4562 .compatible = "koe,tx26d202vm0bwa", 4563 .data = &koe_tx26d202vm0bwa, 4564 }, { 4565 .compatible = "koe,tx31d200vm0baa", 4566 .data = &koe_tx31d200vm0baa, 4567 }, { 4568 .compatible = "kyo,tcg121xglp", 4569 .data = &kyo_tcg121xglp, 4570 }, { 4571 .compatible = "lemaker,bl035-rgb-002", 4572 .data = &lemaker_bl035_rgb_002, 4573 }, { 4574 .compatible = "lg,lb070wv8", 4575 .data = &lg_lb070wv8, 4576 }, { 4577 .compatible = "lg,lp079qx1-sp0v", 4578 .data = &lg_lp079qx1_sp0v, 4579 }, { 4580 .compatible = "lg,lp097qx1-spa1", 4581 .data = &lg_lp097qx1_spa1, 4582 }, { 4583 .compatible = "lg,lp120up1", 4584 .data = &lg_lp120up1, 4585 }, { 4586 .compatible = "lg,lp129qe", 4587 .data = &lg_lp129qe, 4588 }, { 4589 .compatible = "logicpd,type28", 4590 .data = &logicpd_type_28, 4591 }, { 4592 .compatible = "logictechno,lt161010-2nhc", 4593 .data = &logictechno_lt161010_2nh, 4594 }, { 4595 .compatible = "logictechno,lt161010-2nhr", 4596 .data = &logictechno_lt161010_2nh, 4597 }, { 4598 .compatible = "logictechno,lt170410-2whc", 4599 .data = &logictechno_lt170410_2whc, 4600 }, { 4601 .compatible = "mitsubishi,aa070mc01-ca1", 4602 .data = &mitsubishi_aa070mc01, 4603 }, { 4604 .compatible = "nec,nl12880bc20-05", 4605 .data = &nec_nl12880bc20_05, 4606 }, { 4607 .compatible = "nec,nl4827hc19-05b", 4608 .data = &nec_nl4827hc19_05b, 4609 }, { 4610 .compatible = "netron-dy,e231732", 4611 .data = &netron_dy_e231732, 4612 }, { 4613 .compatible = "neweast,wjfh116008a", 4614 .data = &neweast_wjfh116008a, 4615 }, { 4616 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4617 .data = &newhaven_nhd_43_480272ef_atxl, 4618 }, { 4619 .compatible = "nlt,nl192108ac18-02d", 4620 .data = &nlt_nl192108ac18_02d, 4621 }, { 4622 .compatible = "nvd,9128", 4623 .data = &nvd_9128, 4624 }, { 4625 .compatible = "okaya,rs800480t-7x0gp", 4626 .data = &okaya_rs800480t_7x0gp, 4627 }, { 4628 .compatible = "olimex,lcd-olinuxino-43-ts", 4629 .data = &olimex_lcd_olinuxino_43ts, 4630 }, { 4631 .compatible = "ontat,yx700wv03", 4632 .data = &ontat_yx700wv03, 4633 }, { 4634 .compatible = "ortustech,com37h3m05dtc", 4635 .data = &ortustech_com37h3m, 4636 }, { 4637 .compatible = "ortustech,com37h3m99dtc", 4638 .data = &ortustech_com37h3m, 4639 }, { 4640 .compatible = "ortustech,com43h4m85ulc", 4641 .data = &ortustech_com43h4m85ulc, 4642 }, { 4643 .compatible = "osddisplays,osd070t1718-19ts", 4644 .data = &osddisplays_osd070t1718_19ts, 4645 }, { 4646 .compatible = "pda,91-00156-a0", 4647 .data = &pda_91_00156_a0, 4648 }, { 4649 .compatible = "powertip,ph800480t013-idf02", 4650 .data = &powertip_ph800480t013_idf02, 4651 }, { 4652 .compatible = "qiaodian,qd43003c0-40", 4653 .data = &qd43003c0_40, 4654 }, { 4655 .compatible = "rocktech,rk070er9427", 4656 .data = &rocktech_rk070er9427, 4657 }, { 4658 .compatible = "rocktech,rk101ii01d-ct", 4659 .data = &rocktech_rk101ii01d_ct, 4660 }, { 4661 .compatible = "samsung,atna33xc20", 4662 .data = &samsung_atna33xc20, 4663 }, { 4664 .compatible = "samsung,lsn122dl01-c01", 4665 .data = &samsung_lsn122dl01_c01, 4666 }, { 4667 .compatible = "samsung,ltn101nt05", 4668 .data = &samsung_ltn101nt05, 4669 }, { 4670 .compatible = "samsung,ltn140at29-301", 4671 .data = &samsung_ltn140at29_301, 4672 }, { 4673 .compatible = "satoz,sat050at40h12r2", 4674 .data = &satoz_sat050at40h12r2, 4675 }, { 4676 .compatible = "sharp,ld-d5116z01b", 4677 .data = &sharp_ld_d5116z01b, 4678 }, { 4679 .compatible = "sharp,lq035q7db03", 4680 .data = &sharp_lq035q7db03, 4681 }, { 4682 .compatible = "sharp,lq070y3dg3b", 4683 .data = &sharp_lq070y3dg3b, 4684 }, { 4685 .compatible = "sharp,lq101k1ly04", 4686 .data = &sharp_lq101k1ly04, 4687 }, { 4688 .compatible = "sharp,lq123p1jx31", 4689 .data = &sharp_lq123p1jx31, 4690 }, { 4691 .compatible = "sharp,ls020b1dd01d", 4692 .data = &sharp_ls020b1dd01d, 4693 }, { 4694 .compatible = "shelly,sca07010-bfn-lnn", 4695 .data = &shelly_sca07010_bfn_lnn, 4696 }, { 4697 .compatible = "starry,kr070pe2t", 4698 .data = &starry_kr070pe2t, 4699 }, { 4700 .compatible = "starry,kr122ea0sra", 4701 .data = &starry_kr122ea0sra, 4702 }, { 4703 .compatible = "tfc,s9700rtwv43tr-01b", 4704 .data = &tfc_s9700rtwv43tr_01b, 4705 }, { 4706 .compatible = "tianma,tm070jdhg30", 4707 .data = &tianma_tm070jdhg30, 4708 }, { 4709 .compatible = "tianma,tm070jvhg33", 4710 .data = &tianma_tm070jvhg33, 4711 }, { 4712 .compatible = "tianma,tm070rvhg71", 4713 .data = &tianma_tm070rvhg71, 4714 }, { 4715 .compatible = "ti,nspire-cx-lcd-panel", 4716 .data = &ti_nspire_cx_lcd_panel, 4717 }, { 4718 .compatible = "ti,nspire-classic-lcd-panel", 4719 .data = &ti_nspire_classic_lcd_panel, 4720 }, { 4721 .compatible = "toshiba,lt089ac29000", 4722 .data = &toshiba_lt089ac29000, 4723 }, { 4724 .compatible = "tpk,f07a-0102", 4725 .data = &tpk_f07a_0102, 4726 }, { 4727 .compatible = "tpk,f10a-0102", 4728 .data = &tpk_f10a_0102, 4729 }, { 4730 .compatible = "urt,umsh-8596md-t", 4731 .data = &urt_umsh_8596md_parallel, 4732 }, { 4733 .compatible = "urt,umsh-8596md-1t", 4734 .data = &urt_umsh_8596md_parallel, 4735 }, { 4736 .compatible = "urt,umsh-8596md-7t", 4737 .data = &urt_umsh_8596md_parallel, 4738 }, { 4739 .compatible = "urt,umsh-8596md-11t", 4740 .data = &urt_umsh_8596md_lvds, 4741 }, { 4742 .compatible = "urt,umsh-8596md-19t", 4743 .data = &urt_umsh_8596md_lvds, 4744 }, { 4745 .compatible = "urt,umsh-8596md-20t", 4746 .data = &urt_umsh_8596md_parallel, 4747 }, { 4748 .compatible = "vxt,vl050-8048nt-c01", 4749 .data = &vl050_8048nt_c01, 4750 }, { 4751 .compatible = "winstar,wf35ltiacd", 4752 .data = &winstar_wf35ltiacd, 4753 }, { 4754 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4755 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4756 }, { 4757 /* Must be the last entry */ 4758 .compatible = "panel-dpi", 4759 .data = &panel_dpi, 4760 }, { 4761 /* sentinel */ 4762 } 4763 }; 4764 MODULE_DEVICE_TABLE(of, platform_of_match); 4765 4766 static int panel_simple_platform_probe(struct platform_device *pdev) 4767 { 4768 const struct of_device_id *id; 4769 4770 id = of_match_node(platform_of_match, pdev->dev.of_node); 4771 if (!id) 4772 return -ENODEV; 4773 4774 return panel_simple_probe(&pdev->dev, id->data, NULL); 4775 } 4776 4777 static int panel_simple_platform_remove(struct platform_device *pdev) 4778 { 4779 return panel_simple_remove(&pdev->dev); 4780 } 4781 4782 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4783 { 4784 panel_simple_shutdown(&pdev->dev); 4785 } 4786 4787 static const struct dev_pm_ops panel_simple_pm_ops = { 4788 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4789 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4790 pm_runtime_force_resume) 4791 }; 4792 4793 static struct platform_driver panel_simple_platform_driver = { 4794 .driver = { 4795 .name = "panel-simple", 4796 .of_match_table = platform_of_match, 4797 .pm = &panel_simple_pm_ops, 4798 }, 4799 .probe = panel_simple_platform_probe, 4800 .remove = panel_simple_platform_remove, 4801 .shutdown = panel_simple_platform_shutdown, 4802 }; 4803 4804 struct panel_desc_dsi { 4805 struct panel_desc desc; 4806 4807 unsigned long flags; 4808 enum mipi_dsi_pixel_format format; 4809 unsigned int lanes; 4810 }; 4811 4812 static const struct drm_display_mode auo_b080uan01_mode = { 4813 .clock = 154500, 4814 .hdisplay = 1200, 4815 .hsync_start = 1200 + 62, 4816 .hsync_end = 1200 + 62 + 4, 4817 .htotal = 1200 + 62 + 4 + 62, 4818 .vdisplay = 1920, 4819 .vsync_start = 1920 + 9, 4820 .vsync_end = 1920 + 9 + 2, 4821 .vtotal = 1920 + 9 + 2 + 8, 4822 }; 4823 4824 static const struct panel_desc_dsi auo_b080uan01 = { 4825 .desc = { 4826 .modes = &auo_b080uan01_mode, 4827 .num_modes = 1, 4828 .bpc = 8, 4829 .size = { 4830 .width = 108, 4831 .height = 272, 4832 }, 4833 .connector_type = DRM_MODE_CONNECTOR_DSI, 4834 }, 4835 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4836 .format = MIPI_DSI_FMT_RGB888, 4837 .lanes = 4, 4838 }; 4839 4840 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4841 .clock = 160000, 4842 .hdisplay = 1200, 4843 .hsync_start = 1200 + 120, 4844 .hsync_end = 1200 + 120 + 20, 4845 .htotal = 1200 + 120 + 20 + 21, 4846 .vdisplay = 1920, 4847 .vsync_start = 1920 + 21, 4848 .vsync_end = 1920 + 21 + 3, 4849 .vtotal = 1920 + 21 + 3 + 18, 4850 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4851 }; 4852 4853 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4854 .desc = { 4855 .modes = &boe_tv080wum_nl0_mode, 4856 .num_modes = 1, 4857 .size = { 4858 .width = 107, 4859 .height = 172, 4860 }, 4861 .connector_type = DRM_MODE_CONNECTOR_DSI, 4862 }, 4863 .flags = MIPI_DSI_MODE_VIDEO | 4864 MIPI_DSI_MODE_VIDEO_BURST | 4865 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4866 .format = MIPI_DSI_FMT_RGB888, 4867 .lanes = 4, 4868 }; 4869 4870 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4871 .clock = 71000, 4872 .hdisplay = 800, 4873 .hsync_start = 800 + 32, 4874 .hsync_end = 800 + 32 + 1, 4875 .htotal = 800 + 32 + 1 + 57, 4876 .vdisplay = 1280, 4877 .vsync_start = 1280 + 28, 4878 .vsync_end = 1280 + 28 + 1, 4879 .vtotal = 1280 + 28 + 1 + 14, 4880 }; 4881 4882 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4883 .desc = { 4884 .modes = &lg_ld070wx3_sl01_mode, 4885 .num_modes = 1, 4886 .bpc = 8, 4887 .size = { 4888 .width = 94, 4889 .height = 151, 4890 }, 4891 .connector_type = DRM_MODE_CONNECTOR_DSI, 4892 }, 4893 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4894 .format = MIPI_DSI_FMT_RGB888, 4895 .lanes = 4, 4896 }; 4897 4898 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4899 .clock = 67000, 4900 .hdisplay = 720, 4901 .hsync_start = 720 + 12, 4902 .hsync_end = 720 + 12 + 4, 4903 .htotal = 720 + 12 + 4 + 112, 4904 .vdisplay = 1280, 4905 .vsync_start = 1280 + 8, 4906 .vsync_end = 1280 + 8 + 4, 4907 .vtotal = 1280 + 8 + 4 + 12, 4908 }; 4909 4910 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4911 .desc = { 4912 .modes = &lg_lh500wx1_sd03_mode, 4913 .num_modes = 1, 4914 .bpc = 8, 4915 .size = { 4916 .width = 62, 4917 .height = 110, 4918 }, 4919 .connector_type = DRM_MODE_CONNECTOR_DSI, 4920 }, 4921 .flags = MIPI_DSI_MODE_VIDEO, 4922 .format = MIPI_DSI_FMT_RGB888, 4923 .lanes = 4, 4924 }; 4925 4926 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4927 .clock = 157200, 4928 .hdisplay = 1920, 4929 .hsync_start = 1920 + 154, 4930 .hsync_end = 1920 + 154 + 16, 4931 .htotal = 1920 + 154 + 16 + 32, 4932 .vdisplay = 1200, 4933 .vsync_start = 1200 + 17, 4934 .vsync_end = 1200 + 17 + 2, 4935 .vtotal = 1200 + 17 + 2 + 16, 4936 }; 4937 4938 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4939 .desc = { 4940 .modes = &panasonic_vvx10f004b00_mode, 4941 .num_modes = 1, 4942 .bpc = 8, 4943 .size = { 4944 .width = 217, 4945 .height = 136, 4946 }, 4947 .connector_type = DRM_MODE_CONNECTOR_DSI, 4948 }, 4949 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4950 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4951 .format = MIPI_DSI_FMT_RGB888, 4952 .lanes = 4, 4953 }; 4954 4955 static const struct drm_display_mode lg_acx467akm_7_mode = { 4956 .clock = 150000, 4957 .hdisplay = 1080, 4958 .hsync_start = 1080 + 2, 4959 .hsync_end = 1080 + 2 + 2, 4960 .htotal = 1080 + 2 + 2 + 2, 4961 .vdisplay = 1920, 4962 .vsync_start = 1920 + 2, 4963 .vsync_end = 1920 + 2 + 2, 4964 .vtotal = 1920 + 2 + 2 + 2, 4965 }; 4966 4967 static const struct panel_desc_dsi lg_acx467akm_7 = { 4968 .desc = { 4969 .modes = &lg_acx467akm_7_mode, 4970 .num_modes = 1, 4971 .bpc = 8, 4972 .size = { 4973 .width = 62, 4974 .height = 110, 4975 }, 4976 .connector_type = DRM_MODE_CONNECTOR_DSI, 4977 }, 4978 .flags = 0, 4979 .format = MIPI_DSI_FMT_RGB888, 4980 .lanes = 4, 4981 }; 4982 4983 static const struct drm_display_mode osd101t2045_53ts_mode = { 4984 .clock = 154500, 4985 .hdisplay = 1920, 4986 .hsync_start = 1920 + 112, 4987 .hsync_end = 1920 + 112 + 16, 4988 .htotal = 1920 + 112 + 16 + 32, 4989 .vdisplay = 1200, 4990 .vsync_start = 1200 + 16, 4991 .vsync_end = 1200 + 16 + 2, 4992 .vtotal = 1200 + 16 + 2 + 16, 4993 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4994 }; 4995 4996 static const struct panel_desc_dsi osd101t2045_53ts = { 4997 .desc = { 4998 .modes = &osd101t2045_53ts_mode, 4999 .num_modes = 1, 5000 .bpc = 8, 5001 .size = { 5002 .width = 217, 5003 .height = 136, 5004 }, 5005 .connector_type = DRM_MODE_CONNECTOR_DSI, 5006 }, 5007 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5008 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5009 MIPI_DSI_MODE_EOT_PACKET, 5010 .format = MIPI_DSI_FMT_RGB888, 5011 .lanes = 4, 5012 }; 5013 5014 static const struct of_device_id dsi_of_match[] = { 5015 { 5016 .compatible = "auo,b080uan01", 5017 .data = &auo_b080uan01 5018 }, { 5019 .compatible = "boe,tv080wum-nl0", 5020 .data = &boe_tv080wum_nl0 5021 }, { 5022 .compatible = "lg,ld070wx3-sl01", 5023 .data = &lg_ld070wx3_sl01 5024 }, { 5025 .compatible = "lg,lh500wx1-sd03", 5026 .data = &lg_lh500wx1_sd03 5027 }, { 5028 .compatible = "panasonic,vvx10f004b00", 5029 .data = &panasonic_vvx10f004b00 5030 }, { 5031 .compatible = "lg,acx467akm-7", 5032 .data = &lg_acx467akm_7 5033 }, { 5034 .compatible = "osddisplays,osd101t2045-53ts", 5035 .data = &osd101t2045_53ts 5036 }, { 5037 /* sentinel */ 5038 } 5039 }; 5040 MODULE_DEVICE_TABLE(of, dsi_of_match); 5041 5042 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5043 { 5044 const struct panel_desc_dsi *desc; 5045 const struct of_device_id *id; 5046 int err; 5047 5048 id = of_match_node(dsi_of_match, dsi->dev.of_node); 5049 if (!id) 5050 return -ENODEV; 5051 5052 desc = id->data; 5053 5054 err = panel_simple_probe(&dsi->dev, &desc->desc, NULL); 5055 if (err < 0) 5056 return err; 5057 5058 dsi->mode_flags = desc->flags; 5059 dsi->format = desc->format; 5060 dsi->lanes = desc->lanes; 5061 5062 err = mipi_dsi_attach(dsi); 5063 if (err) { 5064 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5065 5066 drm_panel_remove(&panel->base); 5067 } 5068 5069 return err; 5070 } 5071 5072 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5073 { 5074 int err; 5075 5076 err = mipi_dsi_detach(dsi); 5077 if (err < 0) 5078 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5079 5080 return panel_simple_remove(&dsi->dev); 5081 } 5082 5083 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5084 { 5085 panel_simple_shutdown(&dsi->dev); 5086 } 5087 5088 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5089 .driver = { 5090 .name = "panel-simple-dsi", 5091 .of_match_table = dsi_of_match, 5092 .pm = &panel_simple_pm_ops, 5093 }, 5094 .probe = panel_simple_dsi_probe, 5095 .remove = panel_simple_dsi_remove, 5096 .shutdown = panel_simple_dsi_shutdown, 5097 }; 5098 5099 static int panel_simple_dp_aux_ep_probe(struct dp_aux_ep_device *aux_ep) 5100 { 5101 const struct of_device_id *id; 5102 5103 id = of_match_node(platform_of_match, aux_ep->dev.of_node); 5104 if (!id) 5105 return -ENODEV; 5106 5107 return panel_simple_probe(&aux_ep->dev, id->data, aux_ep->aux); 5108 } 5109 5110 static void panel_simple_dp_aux_ep_remove(struct dp_aux_ep_device *aux_ep) 5111 { 5112 panel_simple_remove(&aux_ep->dev); 5113 } 5114 5115 static void panel_simple_dp_aux_ep_shutdown(struct dp_aux_ep_device *aux_ep) 5116 { 5117 panel_simple_shutdown(&aux_ep->dev); 5118 } 5119 5120 static struct dp_aux_ep_driver panel_simple_dp_aux_ep_driver = { 5121 .driver = { 5122 .name = "panel-simple-dp-aux", 5123 .of_match_table = platform_of_match, /* Same as platform one! */ 5124 .pm = &panel_simple_pm_ops, 5125 }, 5126 .probe = panel_simple_dp_aux_ep_probe, 5127 .remove = panel_simple_dp_aux_ep_remove, 5128 .shutdown = panel_simple_dp_aux_ep_shutdown, 5129 }; 5130 5131 static int __init panel_simple_init(void) 5132 { 5133 int err; 5134 5135 err = platform_driver_register(&panel_simple_platform_driver); 5136 if (err < 0) 5137 return err; 5138 5139 err = dp_aux_dp_driver_register(&panel_simple_dp_aux_ep_driver); 5140 if (err < 0) 5141 goto err_did_platform_register; 5142 5143 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5144 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5145 if (err < 0) 5146 goto err_did_aux_ep_register; 5147 } 5148 5149 return 0; 5150 5151 err_did_aux_ep_register: 5152 dp_aux_dp_driver_unregister(&panel_simple_dp_aux_ep_driver); 5153 5154 err_did_platform_register: 5155 platform_driver_unregister(&panel_simple_platform_driver); 5156 5157 return err; 5158 } 5159 module_init(panel_simple_init); 5160 5161 static void __exit panel_simple_exit(void) 5162 { 5163 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5164 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5165 5166 dp_aux_dp_driver_unregister(&panel_simple_dp_aux_ep_driver); 5167 platform_driver_unregister(&panel_simple_platform_driver); 5168 } 5169 module_exit(panel_simple_exit); 5170 5171 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5172 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5173 MODULE_LICENSE("GPL and additional rights"); 5174