1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 bool enabled; 142 143 bool prepared; 144 145 ktime_t unprepared_time; 146 147 const struct panel_desc *desc; 148 149 struct regulator *supply; 150 struct i2c_adapter *ddc; 151 152 struct gpio_desc *enable_gpio; 153 154 struct edid *edid; 155 156 struct drm_display_mode override_mode; 157 158 enum drm_panel_orientation orientation; 159 }; 160 161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 162 { 163 return container_of(panel, struct panel_simple, base); 164 } 165 166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 167 struct drm_connector *connector) 168 { 169 struct drm_display_mode *mode; 170 unsigned int i, num = 0; 171 172 for (i = 0; i < panel->desc->num_timings; i++) { 173 const struct display_timing *dt = &panel->desc->timings[i]; 174 struct videomode vm; 175 176 videomode_from_timing(dt, &vm); 177 mode = drm_mode_create(connector->dev); 178 if (!mode) { 179 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 180 dt->hactive.typ, dt->vactive.typ); 181 continue; 182 } 183 184 drm_display_mode_from_videomode(&vm, mode); 185 186 mode->type |= DRM_MODE_TYPE_DRIVER; 187 188 if (panel->desc->num_timings == 1) 189 mode->type |= DRM_MODE_TYPE_PREFERRED; 190 191 drm_mode_probed_add(connector, mode); 192 num++; 193 } 194 195 return num; 196 } 197 198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 199 struct drm_connector *connector) 200 { 201 struct drm_display_mode *mode; 202 unsigned int i, num = 0; 203 204 for (i = 0; i < panel->desc->num_modes; i++) { 205 const struct drm_display_mode *m = &panel->desc->modes[i]; 206 207 mode = drm_mode_duplicate(connector->dev, m); 208 if (!mode) { 209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 210 m->hdisplay, m->vdisplay, 211 drm_mode_vrefresh(m)); 212 continue; 213 } 214 215 mode->type |= DRM_MODE_TYPE_DRIVER; 216 217 if (panel->desc->num_modes == 1) 218 mode->type |= DRM_MODE_TYPE_PREFERRED; 219 220 drm_mode_set_name(mode); 221 222 drm_mode_probed_add(connector, mode); 223 num++; 224 } 225 226 return num; 227 } 228 229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 230 struct drm_connector *connector) 231 { 232 struct drm_display_mode *mode; 233 bool has_override = panel->override_mode.type; 234 unsigned int num = 0; 235 236 if (!panel->desc) 237 return 0; 238 239 if (has_override) { 240 mode = drm_mode_duplicate(connector->dev, 241 &panel->override_mode); 242 if (mode) { 243 drm_mode_probed_add(connector, mode); 244 num = 1; 245 } else { 246 dev_err(panel->base.dev, "failed to add override mode\n"); 247 } 248 } 249 250 /* Only add timings if override was not there or failed to validate */ 251 if (num == 0 && panel->desc->num_timings) 252 num = panel_simple_get_timings_modes(panel, connector); 253 254 /* 255 * Only add fixed modes if timings/override added no mode. 256 * 257 * We should only ever have either the display timings specified 258 * or a fixed mode. Anything else is rather bogus. 259 */ 260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 261 if (num == 0) 262 num = panel_simple_get_display_modes(panel, connector); 263 264 connector->display_info.bpc = panel->desc->bpc; 265 connector->display_info.width_mm = panel->desc->size.width; 266 connector->display_info.height_mm = panel->desc->size.height; 267 if (panel->desc->bus_format) 268 drm_display_info_set_bus_formats(&connector->display_info, 269 &panel->desc->bus_format, 1); 270 connector->display_info.bus_flags = panel->desc->bus_flags; 271 272 return num; 273 } 274 275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 276 { 277 ktime_t now_ktime, min_ktime; 278 279 if (!min_ms) 280 return; 281 282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 283 now_ktime = ktime_get_boottime(); 284 285 if (ktime_before(now_ktime, min_ktime)) 286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 287 } 288 289 static int panel_simple_disable(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 293 if (!p->enabled) 294 return 0; 295 296 if (p->desc->delay.disable) 297 msleep(p->desc->delay.disable); 298 299 p->enabled = false; 300 301 return 0; 302 } 303 304 static int panel_simple_suspend(struct device *dev) 305 { 306 struct panel_simple *p = dev_get_drvdata(dev); 307 308 gpiod_set_value_cansleep(p->enable_gpio, 0); 309 regulator_disable(p->supply); 310 p->unprepared_time = ktime_get_boottime(); 311 312 kfree(p->edid); 313 p->edid = NULL; 314 315 return 0; 316 } 317 318 static int panel_simple_unprepare(struct drm_panel *panel) 319 { 320 struct panel_simple *p = to_panel_simple(panel); 321 int ret; 322 323 /* Unpreparing when already unprepared is a no-op */ 324 if (!p->prepared) 325 return 0; 326 327 pm_runtime_mark_last_busy(panel->dev); 328 ret = pm_runtime_put_autosuspend(panel->dev); 329 if (ret < 0) 330 return ret; 331 p->prepared = false; 332 333 return 0; 334 } 335 336 static int panel_simple_resume(struct device *dev) 337 { 338 struct panel_simple *p = dev_get_drvdata(dev); 339 int err; 340 341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 342 343 err = regulator_enable(p->supply); 344 if (err < 0) { 345 dev_err(dev, "failed to enable supply: %d\n", err); 346 return err; 347 } 348 349 gpiod_set_value_cansleep(p->enable_gpio, 1); 350 351 if (p->desc->delay.prepare) 352 msleep(p->desc->delay.prepare); 353 354 return 0; 355 } 356 357 static int panel_simple_prepare(struct drm_panel *panel) 358 { 359 struct panel_simple *p = to_panel_simple(panel); 360 int ret; 361 362 /* Preparing when already prepared is a no-op */ 363 if (p->prepared) 364 return 0; 365 366 ret = pm_runtime_get_sync(panel->dev); 367 if (ret < 0) { 368 pm_runtime_put_autosuspend(panel->dev); 369 return ret; 370 } 371 372 p->prepared = true; 373 374 return 0; 375 } 376 377 static int panel_simple_enable(struct drm_panel *panel) 378 { 379 struct panel_simple *p = to_panel_simple(panel); 380 381 if (p->enabled) 382 return 0; 383 384 if (p->desc->delay.enable) 385 msleep(p->desc->delay.enable); 386 387 p->enabled = true; 388 389 return 0; 390 } 391 392 static int panel_simple_get_modes(struct drm_panel *panel, 393 struct drm_connector *connector) 394 { 395 struct panel_simple *p = to_panel_simple(panel); 396 int num = 0; 397 398 /* probe EDID if a DDC bus is available */ 399 if (p->ddc) { 400 pm_runtime_get_sync(panel->dev); 401 402 if (!p->edid) 403 p->edid = drm_get_edid(connector, p->ddc); 404 405 if (p->edid) 406 num += drm_add_edid_modes(connector, p->edid); 407 408 pm_runtime_mark_last_busy(panel->dev); 409 pm_runtime_put_autosuspend(panel->dev); 410 } 411 412 /* add hard-coded panel modes */ 413 num += panel_simple_get_non_edid_modes(p, connector); 414 415 /* 416 * TODO: Remove once all drm drivers call 417 * drm_connector_set_orientation_from_panel() 418 */ 419 drm_connector_set_panel_orientation(connector, p->orientation); 420 421 return num; 422 } 423 424 static int panel_simple_get_timings(struct drm_panel *panel, 425 unsigned int num_timings, 426 struct display_timing *timings) 427 { 428 struct panel_simple *p = to_panel_simple(panel); 429 unsigned int i; 430 431 if (p->desc->num_timings < num_timings) 432 num_timings = p->desc->num_timings; 433 434 if (timings) 435 for (i = 0; i < num_timings; i++) 436 timings[i] = p->desc->timings[i]; 437 438 return p->desc->num_timings; 439 } 440 441 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 442 { 443 struct panel_simple *p = to_panel_simple(panel); 444 445 return p->orientation; 446 } 447 448 static const struct drm_panel_funcs panel_simple_funcs = { 449 .disable = panel_simple_disable, 450 .unprepare = panel_simple_unprepare, 451 .prepare = panel_simple_prepare, 452 .enable = panel_simple_enable, 453 .get_modes = panel_simple_get_modes, 454 .get_orientation = panel_simple_get_orientation, 455 .get_timings = panel_simple_get_timings, 456 }; 457 458 static struct panel_desc panel_dpi; 459 460 static int panel_dpi_probe(struct device *dev, 461 struct panel_simple *panel) 462 { 463 struct display_timing *timing; 464 const struct device_node *np; 465 struct panel_desc *desc; 466 unsigned int bus_flags; 467 struct videomode vm; 468 int ret; 469 470 np = dev->of_node; 471 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 472 if (!desc) 473 return -ENOMEM; 474 475 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 476 if (!timing) 477 return -ENOMEM; 478 479 ret = of_get_display_timing(np, "panel-timing", timing); 480 if (ret < 0) { 481 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 482 np); 483 return ret; 484 } 485 486 desc->timings = timing; 487 desc->num_timings = 1; 488 489 of_property_read_u32(np, "width-mm", &desc->size.width); 490 of_property_read_u32(np, "height-mm", &desc->size.height); 491 492 /* Extract bus_flags from display_timing */ 493 bus_flags = 0; 494 vm.flags = timing->flags; 495 drm_bus_flags_from_videomode(&vm, &bus_flags); 496 desc->bus_flags = bus_flags; 497 498 /* We do not know the connector for the DT node, so guess it */ 499 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 500 501 panel->desc = desc; 502 503 return 0; 504 } 505 506 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 507 (to_check->field.typ >= bounds->field.min && \ 508 to_check->field.typ <= bounds->field.max) 509 static void panel_simple_parse_panel_timing_node(struct device *dev, 510 struct panel_simple *panel, 511 const struct display_timing *ot) 512 { 513 const struct panel_desc *desc = panel->desc; 514 struct videomode vm; 515 unsigned int i; 516 517 if (WARN_ON(desc->num_modes)) { 518 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 519 return; 520 } 521 if (WARN_ON(!desc->num_timings)) { 522 dev_err(dev, "Reject override mode: no timings specified\n"); 523 return; 524 } 525 526 for (i = 0; i < panel->desc->num_timings; i++) { 527 const struct display_timing *dt = &panel->desc->timings[i]; 528 529 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 537 continue; 538 539 if (ot->flags != dt->flags) 540 continue; 541 542 videomode_from_timing(ot, &vm); 543 drm_display_mode_from_videomode(&vm, &panel->override_mode); 544 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 545 DRM_MODE_TYPE_PREFERRED; 546 break; 547 } 548 549 if (WARN_ON(!panel->override_mode.type)) 550 dev_err(dev, "Reject override mode: No display_timing found\n"); 551 } 552 553 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 554 struct panel_simple *panel) 555 { 556 int ret, bpc; 557 558 ret = drm_of_lvds_get_data_mapping(dev->of_node); 559 if (ret < 0) { 560 if (ret == -EINVAL) 561 dev_warn(dev, "Ignore invalid data-mapping property\n"); 562 563 /* 564 * Ignore non-existing or malformatted property, fallback to 565 * default data-mapping, and return 0. 566 */ 567 return 0; 568 } 569 570 switch (ret) { 571 default: 572 WARN_ON(1); 573 fallthrough; 574 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 575 fallthrough; 576 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 577 bpc = 8; 578 break; 579 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 580 bpc = 6; 581 } 582 583 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 584 struct panel_desc *override_desc; 585 586 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 587 if (!override_desc) 588 return -ENOMEM; 589 590 override_desc->bus_format = ret; 591 override_desc->bpc = bpc; 592 panel->desc = override_desc; 593 } 594 595 return 0; 596 } 597 598 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 599 { 600 struct panel_simple *panel; 601 struct display_timing dt; 602 struct device_node *ddc; 603 int connector_type; 604 u32 bus_flags; 605 int err; 606 607 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 608 if (!panel) 609 return -ENOMEM; 610 611 panel->enabled = false; 612 panel->desc = desc; 613 614 panel->supply = devm_regulator_get(dev, "power"); 615 if (IS_ERR(panel->supply)) 616 return PTR_ERR(panel->supply); 617 618 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 619 GPIOD_OUT_LOW); 620 if (IS_ERR(panel->enable_gpio)) 621 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 622 "failed to request GPIO\n"); 623 624 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 625 if (err) { 626 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 627 return err; 628 } 629 630 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 631 if (ddc) { 632 panel->ddc = of_find_i2c_adapter_by_node(ddc); 633 of_node_put(ddc); 634 635 if (!panel->ddc) 636 return -EPROBE_DEFER; 637 } 638 639 if (desc == &panel_dpi) { 640 /* Handle the generic panel-dpi binding */ 641 err = panel_dpi_probe(dev, panel); 642 if (err) 643 goto free_ddc; 644 desc = panel->desc; 645 } else { 646 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 647 panel_simple_parse_panel_timing_node(dev, panel, &dt); 648 } 649 650 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 651 /* Optional data-mapping property for overriding bus format */ 652 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 653 if (err) 654 goto free_ddc; 655 } 656 657 connector_type = desc->connector_type; 658 /* Catch common mistakes for panels. */ 659 switch (connector_type) { 660 case 0: 661 dev_warn(dev, "Specify missing connector_type\n"); 662 connector_type = DRM_MODE_CONNECTOR_DPI; 663 break; 664 case DRM_MODE_CONNECTOR_LVDS: 665 WARN_ON(desc->bus_flags & 666 ~(DRM_BUS_FLAG_DE_LOW | 667 DRM_BUS_FLAG_DE_HIGH | 668 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 669 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 670 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 671 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 672 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 673 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 674 desc->bpc != 6); 675 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 676 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 677 desc->bpc != 8); 678 break; 679 case DRM_MODE_CONNECTOR_eDP: 680 dev_warn(dev, "eDP panels moved to panel-edp\n"); 681 err = -EINVAL; 682 goto free_ddc; 683 case DRM_MODE_CONNECTOR_DSI: 684 if (desc->bpc != 6 && desc->bpc != 8) 685 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 686 break; 687 case DRM_MODE_CONNECTOR_DPI: 688 bus_flags = DRM_BUS_FLAG_DE_LOW | 689 DRM_BUS_FLAG_DE_HIGH | 690 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 691 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 692 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 693 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 694 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 695 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 696 if (desc->bus_flags & ~bus_flags) 697 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 698 if (!(desc->bus_flags & bus_flags)) 699 dev_warn(dev, "Specify missing bus_flags\n"); 700 if (desc->bus_format == 0) 701 dev_warn(dev, "Specify missing bus_format\n"); 702 if (desc->bpc != 6 && desc->bpc != 8) 703 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 704 break; 705 default: 706 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 707 connector_type = DRM_MODE_CONNECTOR_DPI; 708 break; 709 } 710 711 dev_set_drvdata(dev, panel); 712 713 /* 714 * We use runtime PM for prepare / unprepare since those power the panel 715 * on and off and those can be very slow operations. This is important 716 * to optimize powering the panel on briefly to read the EDID before 717 * fully enabling the panel. 718 */ 719 pm_runtime_enable(dev); 720 pm_runtime_set_autosuspend_delay(dev, 1000); 721 pm_runtime_use_autosuspend(dev); 722 723 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 724 725 err = drm_panel_of_backlight(&panel->base); 726 if (err) { 727 dev_err_probe(dev, err, "Could not find backlight\n"); 728 goto disable_pm_runtime; 729 } 730 731 drm_panel_add(&panel->base); 732 733 return 0; 734 735 disable_pm_runtime: 736 pm_runtime_dont_use_autosuspend(dev); 737 pm_runtime_disable(dev); 738 free_ddc: 739 if (panel->ddc) 740 put_device(&panel->ddc->dev); 741 742 return err; 743 } 744 745 static void panel_simple_remove(struct device *dev) 746 { 747 struct panel_simple *panel = dev_get_drvdata(dev); 748 749 drm_panel_remove(&panel->base); 750 drm_panel_disable(&panel->base); 751 drm_panel_unprepare(&panel->base); 752 753 pm_runtime_dont_use_autosuspend(dev); 754 pm_runtime_disable(dev); 755 if (panel->ddc) 756 put_device(&panel->ddc->dev); 757 } 758 759 static void panel_simple_shutdown(struct device *dev) 760 { 761 struct panel_simple *panel = dev_get_drvdata(dev); 762 763 drm_panel_disable(&panel->base); 764 drm_panel_unprepare(&panel->base); 765 } 766 767 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 768 .clock = 71100, 769 .hdisplay = 1280, 770 .hsync_start = 1280 + 40, 771 .hsync_end = 1280 + 40 + 80, 772 .htotal = 1280 + 40 + 80 + 40, 773 .vdisplay = 800, 774 .vsync_start = 800 + 3, 775 .vsync_end = 800 + 3 + 10, 776 .vtotal = 800 + 3 + 10 + 10, 777 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 778 }; 779 780 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 781 .modes = &ire_am_1280800n3tzqw_t00h_mode, 782 .num_modes = 1, 783 .bpc = 8, 784 .size = { 785 .width = 217, 786 .height = 136, 787 }, 788 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 789 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 790 .connector_type = DRM_MODE_CONNECTOR_LVDS, 791 }; 792 793 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 794 .clock = 9000, 795 .hdisplay = 480, 796 .hsync_start = 480 + 2, 797 .hsync_end = 480 + 2 + 41, 798 .htotal = 480 + 2 + 41 + 2, 799 .vdisplay = 272, 800 .vsync_start = 272 + 2, 801 .vsync_end = 272 + 2 + 10, 802 .vtotal = 272 + 2 + 10 + 2, 803 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 804 }; 805 806 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 807 .modes = &ire_am_480272h3tmqw_t01h_mode, 808 .num_modes = 1, 809 .bpc = 8, 810 .size = { 811 .width = 99, 812 .height = 58, 813 }, 814 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 815 }; 816 817 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 818 .clock = 33333, 819 .hdisplay = 800, 820 .hsync_start = 800 + 0, 821 .hsync_end = 800 + 0 + 255, 822 .htotal = 800 + 0 + 255 + 0, 823 .vdisplay = 480, 824 .vsync_start = 480 + 2, 825 .vsync_end = 480 + 2 + 45, 826 .vtotal = 480 + 2 + 45 + 0, 827 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 828 }; 829 830 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 831 .pixelclock = { 29930000, 33260000, 36590000 }, 832 .hactive = { 800, 800, 800 }, 833 .hfront_porch = { 1, 40, 168 }, 834 .hback_porch = { 88, 88, 88 }, 835 .hsync_len = { 1, 128, 128 }, 836 .vactive = { 480, 480, 480 }, 837 .vfront_porch = { 1, 35, 37 }, 838 .vback_porch = { 8, 8, 8 }, 839 .vsync_len = { 1, 2, 2 }, 840 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 841 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 842 DISPLAY_FLAGS_SYNC_POSEDGE, 843 }; 844 845 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 846 .timings = &ire_am_800480l1tmqw_t00h_timing, 847 .num_timings = 1, 848 .bpc = 8, 849 .size = { 850 .width = 111, 851 .height = 67, 852 }, 853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 854 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 855 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 856 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 857 .connector_type = DRM_MODE_CONNECTOR_DPI, 858 }; 859 860 static const struct panel_desc ampire_am800480r3tmqwa1h = { 861 .modes = &ire_am800480r3tmqwa1h_mode, 862 .num_modes = 1, 863 .bpc = 6, 864 .size = { 865 .width = 152, 866 .height = 91, 867 }, 868 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 869 }; 870 871 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 872 .pixelclock = { 34500000, 39600000, 50400000 }, 873 .hactive = { 800, 800, 800 }, 874 .hfront_porch = { 12, 112, 312 }, 875 .hback_porch = { 87, 87, 48 }, 876 .hsync_len = { 1, 1, 40 }, 877 .vactive = { 600, 600, 600 }, 878 .vfront_porch = { 1, 21, 61 }, 879 .vback_porch = { 38, 38, 19 }, 880 .vsync_len = { 1, 1, 20 }, 881 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 882 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 883 DISPLAY_FLAGS_SYNC_POSEDGE, 884 }; 885 886 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 887 .timings = &ire_am800600p5tmqw_tb8h_timing, 888 .num_timings = 1, 889 .bpc = 6, 890 .size = { 891 .width = 162, 892 .height = 122, 893 }, 894 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 895 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 896 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 897 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 898 .connector_type = DRM_MODE_CONNECTOR_DPI, 899 }; 900 901 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 902 .pixelclock = { 26400000, 33300000, 46800000 }, 903 .hactive = { 800, 800, 800 }, 904 .hfront_porch = { 16, 210, 354 }, 905 .hback_porch = { 45, 36, 6 }, 906 .hsync_len = { 1, 10, 40 }, 907 .vactive = { 480, 480, 480 }, 908 .vfront_porch = { 7, 22, 147 }, 909 .vback_porch = { 22, 13, 3 }, 910 .vsync_len = { 1, 10, 20 }, 911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 913 }; 914 915 static const struct panel_desc armadeus_st0700_adapt = { 916 .timings = &santek_st0700i5y_rbslw_f_timing, 917 .num_timings = 1, 918 .bpc = 6, 919 .size = { 920 .width = 154, 921 .height = 86, 922 }, 923 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 924 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 925 }; 926 927 static const struct drm_display_mode auo_b101aw03_mode = { 928 .clock = 51450, 929 .hdisplay = 1024, 930 .hsync_start = 1024 + 156, 931 .hsync_end = 1024 + 156 + 8, 932 .htotal = 1024 + 156 + 8 + 156, 933 .vdisplay = 600, 934 .vsync_start = 600 + 16, 935 .vsync_end = 600 + 16 + 6, 936 .vtotal = 600 + 16 + 6 + 16, 937 }; 938 939 static const struct panel_desc auo_b101aw03 = { 940 .modes = &auo_b101aw03_mode, 941 .num_modes = 1, 942 .bpc = 6, 943 .size = { 944 .width = 223, 945 .height = 125, 946 }, 947 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 948 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 949 .connector_type = DRM_MODE_CONNECTOR_LVDS, 950 }; 951 952 static const struct drm_display_mode auo_b101xtn01_mode = { 953 .clock = 72000, 954 .hdisplay = 1366, 955 .hsync_start = 1366 + 20, 956 .hsync_end = 1366 + 20 + 70, 957 .htotal = 1366 + 20 + 70, 958 .vdisplay = 768, 959 .vsync_start = 768 + 14, 960 .vsync_end = 768 + 14 + 42, 961 .vtotal = 768 + 14 + 42, 962 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 963 }; 964 965 static const struct panel_desc auo_b101xtn01 = { 966 .modes = &auo_b101xtn01_mode, 967 .num_modes = 1, 968 .bpc = 6, 969 .size = { 970 .width = 223, 971 .height = 125, 972 }, 973 }; 974 975 static const struct drm_display_mode auo_b116xw03_mode = { 976 .clock = 70589, 977 .hdisplay = 1366, 978 .hsync_start = 1366 + 40, 979 .hsync_end = 1366 + 40 + 40, 980 .htotal = 1366 + 40 + 40 + 32, 981 .vdisplay = 768, 982 .vsync_start = 768 + 10, 983 .vsync_end = 768 + 10 + 12, 984 .vtotal = 768 + 10 + 12 + 6, 985 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 986 }; 987 988 static const struct panel_desc auo_b116xw03 = { 989 .modes = &auo_b116xw03_mode, 990 .num_modes = 1, 991 .bpc = 6, 992 .size = { 993 .width = 256, 994 .height = 144, 995 }, 996 .delay = { 997 .prepare = 1, 998 .enable = 200, 999 .disable = 200, 1000 .unprepare = 500, 1001 }, 1002 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1003 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1004 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1005 }; 1006 1007 static const struct display_timing auo_g070vvn01_timings = { 1008 .pixelclock = { 33300000, 34209000, 45000000 }, 1009 .hactive = { 800, 800, 800 }, 1010 .hfront_porch = { 20, 40, 200 }, 1011 .hback_porch = { 87, 40, 1 }, 1012 .hsync_len = { 1, 48, 87 }, 1013 .vactive = { 480, 480, 480 }, 1014 .vfront_porch = { 5, 13, 200 }, 1015 .vback_porch = { 31, 31, 29 }, 1016 .vsync_len = { 1, 1, 3 }, 1017 }; 1018 1019 static const struct panel_desc auo_g070vvn01 = { 1020 .timings = &auo_g070vvn01_timings, 1021 .num_timings = 1, 1022 .bpc = 8, 1023 .size = { 1024 .width = 152, 1025 .height = 91, 1026 }, 1027 .delay = { 1028 .prepare = 200, 1029 .enable = 50, 1030 .disable = 50, 1031 .unprepare = 1000, 1032 }, 1033 }; 1034 1035 static const struct drm_display_mode auo_g101evn010_mode = { 1036 .clock = 68930, 1037 .hdisplay = 1280, 1038 .hsync_start = 1280 + 82, 1039 .hsync_end = 1280 + 82 + 2, 1040 .htotal = 1280 + 82 + 2 + 84, 1041 .vdisplay = 800, 1042 .vsync_start = 800 + 8, 1043 .vsync_end = 800 + 8 + 2, 1044 .vtotal = 800 + 8 + 2 + 6, 1045 }; 1046 1047 static const struct panel_desc auo_g101evn010 = { 1048 .modes = &auo_g101evn010_mode, 1049 .num_modes = 1, 1050 .bpc = 6, 1051 .size = { 1052 .width = 216, 1053 .height = 135, 1054 }, 1055 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1056 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1057 }; 1058 1059 static const struct drm_display_mode auo_g104sn02_mode = { 1060 .clock = 40000, 1061 .hdisplay = 800, 1062 .hsync_start = 800 + 40, 1063 .hsync_end = 800 + 40 + 216, 1064 .htotal = 800 + 40 + 216 + 128, 1065 .vdisplay = 600, 1066 .vsync_start = 600 + 10, 1067 .vsync_end = 600 + 10 + 35, 1068 .vtotal = 600 + 10 + 35 + 2, 1069 }; 1070 1071 static const struct panel_desc auo_g104sn02 = { 1072 .modes = &auo_g104sn02_mode, 1073 .num_modes = 1, 1074 .bpc = 8, 1075 .size = { 1076 .width = 211, 1077 .height = 158, 1078 }, 1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1080 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1081 }; 1082 1083 static const struct display_timing auo_g121ean01_timing = { 1084 .pixelclock = { 60000000, 74400000, 90000000 }, 1085 .hactive = { 1280, 1280, 1280 }, 1086 .hfront_porch = { 20, 50, 100 }, 1087 .hback_porch = { 20, 50, 100 }, 1088 .hsync_len = { 30, 100, 200 }, 1089 .vactive = { 800, 800, 800 }, 1090 .vfront_porch = { 2, 10, 25 }, 1091 .vback_porch = { 2, 10, 25 }, 1092 .vsync_len = { 4, 18, 50 }, 1093 }; 1094 1095 static const struct panel_desc auo_g121ean01 = { 1096 .timings = &auo_g121ean01_timing, 1097 .num_timings = 1, 1098 .bpc = 8, 1099 .size = { 1100 .width = 261, 1101 .height = 163, 1102 }, 1103 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1104 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1105 }; 1106 1107 static const struct display_timing auo_g133han01_timings = { 1108 .pixelclock = { 134000000, 141200000, 149000000 }, 1109 .hactive = { 1920, 1920, 1920 }, 1110 .hfront_porch = { 39, 58, 77 }, 1111 .hback_porch = { 59, 88, 117 }, 1112 .hsync_len = { 28, 42, 56 }, 1113 .vactive = { 1080, 1080, 1080 }, 1114 .vfront_porch = { 3, 8, 11 }, 1115 .vback_porch = { 5, 14, 19 }, 1116 .vsync_len = { 4, 14, 19 }, 1117 }; 1118 1119 static const struct panel_desc auo_g133han01 = { 1120 .timings = &auo_g133han01_timings, 1121 .num_timings = 1, 1122 .bpc = 8, 1123 .size = { 1124 .width = 293, 1125 .height = 165, 1126 }, 1127 .delay = { 1128 .prepare = 200, 1129 .enable = 50, 1130 .disable = 50, 1131 .unprepare = 1000, 1132 }, 1133 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1134 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1135 }; 1136 1137 static const struct drm_display_mode auo_g156xtn01_mode = { 1138 .clock = 76000, 1139 .hdisplay = 1366, 1140 .hsync_start = 1366 + 33, 1141 .hsync_end = 1366 + 33 + 67, 1142 .htotal = 1560, 1143 .vdisplay = 768, 1144 .vsync_start = 768 + 4, 1145 .vsync_end = 768 + 4 + 4, 1146 .vtotal = 806, 1147 }; 1148 1149 static const struct panel_desc auo_g156xtn01 = { 1150 .modes = &auo_g156xtn01_mode, 1151 .num_modes = 1, 1152 .bpc = 8, 1153 .size = { 1154 .width = 344, 1155 .height = 194, 1156 }, 1157 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1158 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1159 }; 1160 1161 static const struct display_timing auo_g185han01_timings = { 1162 .pixelclock = { 120000000, 144000000, 175000000 }, 1163 .hactive = { 1920, 1920, 1920 }, 1164 .hfront_porch = { 36, 120, 148 }, 1165 .hback_porch = { 24, 88, 108 }, 1166 .hsync_len = { 20, 48, 64 }, 1167 .vactive = { 1080, 1080, 1080 }, 1168 .vfront_porch = { 6, 10, 40 }, 1169 .vback_porch = { 2, 5, 20 }, 1170 .vsync_len = { 2, 5, 20 }, 1171 }; 1172 1173 static const struct panel_desc auo_g185han01 = { 1174 .timings = &auo_g185han01_timings, 1175 .num_timings = 1, 1176 .bpc = 8, 1177 .size = { 1178 .width = 409, 1179 .height = 230, 1180 }, 1181 .delay = { 1182 .prepare = 50, 1183 .enable = 200, 1184 .disable = 110, 1185 .unprepare = 1000, 1186 }, 1187 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1188 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1189 }; 1190 1191 static const struct display_timing auo_g190ean01_timings = { 1192 .pixelclock = { 90000000, 108000000, 135000000 }, 1193 .hactive = { 1280, 1280, 1280 }, 1194 .hfront_porch = { 126, 184, 1266 }, 1195 .hback_porch = { 84, 122, 844 }, 1196 .hsync_len = { 70, 102, 704 }, 1197 .vactive = { 1024, 1024, 1024 }, 1198 .vfront_porch = { 4, 26, 76 }, 1199 .vback_porch = { 2, 8, 25 }, 1200 .vsync_len = { 2, 8, 25 }, 1201 }; 1202 1203 static const struct panel_desc auo_g190ean01 = { 1204 .timings = &auo_g190ean01_timings, 1205 .num_timings = 1, 1206 .bpc = 8, 1207 .size = { 1208 .width = 376, 1209 .height = 301, 1210 }, 1211 .delay = { 1212 .prepare = 50, 1213 .enable = 200, 1214 .disable = 110, 1215 .unprepare = 1000, 1216 }, 1217 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1218 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1219 }; 1220 1221 static const struct display_timing auo_p320hvn03_timings = { 1222 .pixelclock = { 106000000, 148500000, 164000000 }, 1223 .hactive = { 1920, 1920, 1920 }, 1224 .hfront_porch = { 25, 50, 130 }, 1225 .hback_porch = { 25, 50, 130 }, 1226 .hsync_len = { 20, 40, 105 }, 1227 .vactive = { 1080, 1080, 1080 }, 1228 .vfront_porch = { 8, 17, 150 }, 1229 .vback_porch = { 8, 17, 150 }, 1230 .vsync_len = { 4, 11, 100 }, 1231 }; 1232 1233 static const struct panel_desc auo_p320hvn03 = { 1234 .timings = &auo_p320hvn03_timings, 1235 .num_timings = 1, 1236 .bpc = 8, 1237 .size = { 1238 .width = 698, 1239 .height = 393, 1240 }, 1241 .delay = { 1242 .prepare = 1, 1243 .enable = 450, 1244 .unprepare = 500, 1245 }, 1246 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1247 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1248 }; 1249 1250 static const struct drm_display_mode auo_t215hvn01_mode = { 1251 .clock = 148800, 1252 .hdisplay = 1920, 1253 .hsync_start = 1920 + 88, 1254 .hsync_end = 1920 + 88 + 44, 1255 .htotal = 1920 + 88 + 44 + 148, 1256 .vdisplay = 1080, 1257 .vsync_start = 1080 + 4, 1258 .vsync_end = 1080 + 4 + 5, 1259 .vtotal = 1080 + 4 + 5 + 36, 1260 }; 1261 1262 static const struct panel_desc auo_t215hvn01 = { 1263 .modes = &auo_t215hvn01_mode, 1264 .num_modes = 1, 1265 .bpc = 8, 1266 .size = { 1267 .width = 430, 1268 .height = 270, 1269 }, 1270 .delay = { 1271 .disable = 5, 1272 .unprepare = 1000, 1273 }, 1274 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1275 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1276 }; 1277 1278 static const struct drm_display_mode avic_tm070ddh03_mode = { 1279 .clock = 51200, 1280 .hdisplay = 1024, 1281 .hsync_start = 1024 + 160, 1282 .hsync_end = 1024 + 160 + 4, 1283 .htotal = 1024 + 160 + 4 + 156, 1284 .vdisplay = 600, 1285 .vsync_start = 600 + 17, 1286 .vsync_end = 600 + 17 + 1, 1287 .vtotal = 600 + 17 + 1 + 17, 1288 }; 1289 1290 static const struct panel_desc avic_tm070ddh03 = { 1291 .modes = &avic_tm070ddh03_mode, 1292 .num_modes = 1, 1293 .bpc = 8, 1294 .size = { 1295 .width = 154, 1296 .height = 90, 1297 }, 1298 .delay = { 1299 .prepare = 20, 1300 .enable = 200, 1301 .disable = 200, 1302 }, 1303 }; 1304 1305 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1306 .clock = 30000, 1307 .hdisplay = 800, 1308 .hsync_start = 800 + 40, 1309 .hsync_end = 800 + 40 + 48, 1310 .htotal = 800 + 40 + 48 + 40, 1311 .vdisplay = 480, 1312 .vsync_start = 480 + 13, 1313 .vsync_end = 480 + 13 + 3, 1314 .vtotal = 480 + 13 + 3 + 29, 1315 }; 1316 1317 static const struct panel_desc bananapi_s070wv20_ct16 = { 1318 .modes = &bananapi_s070wv20_ct16_mode, 1319 .num_modes = 1, 1320 .bpc = 6, 1321 .size = { 1322 .width = 154, 1323 .height = 86, 1324 }, 1325 }; 1326 1327 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1328 .pixelclock = { 69922000, 71000000, 72293000 }, 1329 .hactive = { 1280, 1280, 1280 }, 1330 .hfront_porch = { 48, 48, 48 }, 1331 .hback_porch = { 80, 80, 80 }, 1332 .hsync_len = { 32, 32, 32 }, 1333 .vactive = { 800, 800, 800 }, 1334 .vfront_porch = { 3, 3, 3 }, 1335 .vback_porch = { 14, 14, 14 }, 1336 .vsync_len = { 6, 6, 6 }, 1337 }; 1338 1339 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1340 .timings = &boe_ev121wxm_n10_1850_timing, 1341 .num_timings = 1, 1342 .bpc = 8, 1343 .size = { 1344 .width = 261, 1345 .height = 163, 1346 }, 1347 .delay = { 1348 .prepare = 9, 1349 .enable = 300, 1350 .unprepare = 300, 1351 .disable = 560, 1352 }, 1353 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1354 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1355 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1356 }; 1357 1358 static const struct drm_display_mode boe_hv070wsa_mode = { 1359 .clock = 42105, 1360 .hdisplay = 1024, 1361 .hsync_start = 1024 + 30, 1362 .hsync_end = 1024 + 30 + 30, 1363 .htotal = 1024 + 30 + 30 + 30, 1364 .vdisplay = 600, 1365 .vsync_start = 600 + 10, 1366 .vsync_end = 600 + 10 + 10, 1367 .vtotal = 600 + 10 + 10 + 10, 1368 }; 1369 1370 static const struct panel_desc boe_hv070wsa = { 1371 .modes = &boe_hv070wsa_mode, 1372 .num_modes = 1, 1373 .bpc = 8, 1374 .size = { 1375 .width = 154, 1376 .height = 90, 1377 }, 1378 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1379 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1380 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1381 }; 1382 1383 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1384 .clock = 9000, 1385 .hdisplay = 480, 1386 .hsync_start = 480 + 5, 1387 .hsync_end = 480 + 5 + 5, 1388 .htotal = 480 + 5 + 5 + 40, 1389 .vdisplay = 272, 1390 .vsync_start = 272 + 8, 1391 .vsync_end = 272 + 8 + 8, 1392 .vtotal = 272 + 8 + 8 + 8, 1393 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1394 }; 1395 1396 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1397 .modes = &cdtech_s043wq26h_ct7_mode, 1398 .num_modes = 1, 1399 .bpc = 8, 1400 .size = { 1401 .width = 95, 1402 .height = 54, 1403 }, 1404 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1405 }; 1406 1407 /* S070PWS19HP-FC21 2017/04/22 */ 1408 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1409 .clock = 51200, 1410 .hdisplay = 1024, 1411 .hsync_start = 1024 + 160, 1412 .hsync_end = 1024 + 160 + 20, 1413 .htotal = 1024 + 160 + 20 + 140, 1414 .vdisplay = 600, 1415 .vsync_start = 600 + 12, 1416 .vsync_end = 600 + 12 + 3, 1417 .vtotal = 600 + 12 + 3 + 20, 1418 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1419 }; 1420 1421 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1422 .modes = &cdtech_s070pws19hp_fc21_mode, 1423 .num_modes = 1, 1424 .bpc = 6, 1425 .size = { 1426 .width = 154, 1427 .height = 86, 1428 }, 1429 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1430 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1431 .connector_type = DRM_MODE_CONNECTOR_DPI, 1432 }; 1433 1434 /* S070SWV29HG-DC44 2017/09/21 */ 1435 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1436 .clock = 33300, 1437 .hdisplay = 800, 1438 .hsync_start = 800 + 210, 1439 .hsync_end = 800 + 210 + 2, 1440 .htotal = 800 + 210 + 2 + 44, 1441 .vdisplay = 480, 1442 .vsync_start = 480 + 22, 1443 .vsync_end = 480 + 22 + 2, 1444 .vtotal = 480 + 22 + 2 + 21, 1445 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1446 }; 1447 1448 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1449 .modes = &cdtech_s070swv29hg_dc44_mode, 1450 .num_modes = 1, 1451 .bpc = 6, 1452 .size = { 1453 .width = 154, 1454 .height = 86, 1455 }, 1456 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1457 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1458 .connector_type = DRM_MODE_CONNECTOR_DPI, 1459 }; 1460 1461 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1462 .clock = 35000, 1463 .hdisplay = 800, 1464 .hsync_start = 800 + 40, 1465 .hsync_end = 800 + 40 + 40, 1466 .htotal = 800 + 40 + 40 + 48, 1467 .vdisplay = 480, 1468 .vsync_start = 480 + 29, 1469 .vsync_end = 480 + 29 + 13, 1470 .vtotal = 480 + 29 + 13 + 3, 1471 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1472 }; 1473 1474 static const struct panel_desc cdtech_s070wv95_ct16 = { 1475 .modes = &cdtech_s070wv95_ct16_mode, 1476 .num_modes = 1, 1477 .bpc = 8, 1478 .size = { 1479 .width = 154, 1480 .height = 85, 1481 }, 1482 }; 1483 1484 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1485 .pixelclock = { 68900000, 71100000, 73400000 }, 1486 .hactive = { 1280, 1280, 1280 }, 1487 .hfront_porch = { 65, 80, 95 }, 1488 .hback_porch = { 64, 79, 94 }, 1489 .hsync_len = { 1, 1, 1 }, 1490 .vactive = { 800, 800, 800 }, 1491 .vfront_porch = { 7, 11, 14 }, 1492 .vback_porch = { 7, 11, 14 }, 1493 .vsync_len = { 1, 1, 1 }, 1494 .flags = DISPLAY_FLAGS_DE_HIGH, 1495 }; 1496 1497 static const struct panel_desc chefree_ch101olhlwh_002 = { 1498 .timings = &chefree_ch101olhlwh_002_timing, 1499 .num_timings = 1, 1500 .bpc = 8, 1501 .size = { 1502 .width = 217, 1503 .height = 135, 1504 }, 1505 .delay = { 1506 .enable = 200, 1507 .disable = 200, 1508 }, 1509 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1510 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1511 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1512 }; 1513 1514 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1515 .clock = 66770, 1516 .hdisplay = 800, 1517 .hsync_start = 800 + 49, 1518 .hsync_end = 800 + 49 + 33, 1519 .htotal = 800 + 49 + 33 + 17, 1520 .vdisplay = 1280, 1521 .vsync_start = 1280 + 1, 1522 .vsync_end = 1280 + 1 + 7, 1523 .vtotal = 1280 + 1 + 7 + 15, 1524 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1525 }; 1526 1527 static const struct panel_desc chunghwa_claa070wp03xg = { 1528 .modes = &chunghwa_claa070wp03xg_mode, 1529 .num_modes = 1, 1530 .bpc = 6, 1531 .size = { 1532 .width = 94, 1533 .height = 150, 1534 }, 1535 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1536 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1537 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1538 }; 1539 1540 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1541 .clock = 72070, 1542 .hdisplay = 1366, 1543 .hsync_start = 1366 + 58, 1544 .hsync_end = 1366 + 58 + 58, 1545 .htotal = 1366 + 58 + 58 + 58, 1546 .vdisplay = 768, 1547 .vsync_start = 768 + 4, 1548 .vsync_end = 768 + 4 + 4, 1549 .vtotal = 768 + 4 + 4 + 4, 1550 }; 1551 1552 static const struct panel_desc chunghwa_claa101wa01a = { 1553 .modes = &chunghwa_claa101wa01a_mode, 1554 .num_modes = 1, 1555 .bpc = 6, 1556 .size = { 1557 .width = 220, 1558 .height = 120, 1559 }, 1560 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1561 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1562 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1563 }; 1564 1565 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1566 .clock = 69300, 1567 .hdisplay = 1366, 1568 .hsync_start = 1366 + 48, 1569 .hsync_end = 1366 + 48 + 32, 1570 .htotal = 1366 + 48 + 32 + 20, 1571 .vdisplay = 768, 1572 .vsync_start = 768 + 16, 1573 .vsync_end = 768 + 16 + 8, 1574 .vtotal = 768 + 16 + 8 + 16, 1575 }; 1576 1577 static const struct panel_desc chunghwa_claa101wb01 = { 1578 .modes = &chunghwa_claa101wb01_mode, 1579 .num_modes = 1, 1580 .bpc = 6, 1581 .size = { 1582 .width = 223, 1583 .height = 125, 1584 }, 1585 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1586 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1587 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1588 }; 1589 1590 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1591 .pixelclock = { 5000000, 9000000, 12000000 }, 1592 .hactive = { 480, 480, 480 }, 1593 .hfront_porch = { 12, 12, 12 }, 1594 .hback_porch = { 12, 12, 12 }, 1595 .hsync_len = { 21, 21, 21 }, 1596 .vactive = { 272, 272, 272 }, 1597 .vfront_porch = { 4, 4, 4 }, 1598 .vback_porch = { 4, 4, 4 }, 1599 .vsync_len = { 8, 8, 8 }, 1600 }; 1601 1602 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1603 .timings = &dataimage_fg040346dsswbg04_timing, 1604 .num_timings = 1, 1605 .bpc = 8, 1606 .size = { 1607 .width = 95, 1608 .height = 54, 1609 }, 1610 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1611 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1612 .connector_type = DRM_MODE_CONNECTOR_DPI, 1613 }; 1614 1615 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1616 .pixelclock = { 68900000, 71110000, 73400000 }, 1617 .hactive = { 1280, 1280, 1280 }, 1618 .vactive = { 800, 800, 800 }, 1619 .hback_porch = { 100, 100, 100 }, 1620 .hfront_porch = { 100, 100, 100 }, 1621 .vback_porch = { 5, 5, 5 }, 1622 .vfront_porch = { 5, 5, 5 }, 1623 .hsync_len = { 24, 24, 24 }, 1624 .vsync_len = { 3, 3, 3 }, 1625 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1626 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1627 }; 1628 1629 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1630 .timings = &dataimage_fg1001l0dsswmg01_timing, 1631 .num_timings = 1, 1632 .bpc = 8, 1633 .size = { 1634 .width = 217, 1635 .height = 136, 1636 }, 1637 }; 1638 1639 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1640 .clock = 33260, 1641 .hdisplay = 800, 1642 .hsync_start = 800 + 40, 1643 .hsync_end = 800 + 40 + 128, 1644 .htotal = 800 + 40 + 128 + 88, 1645 .vdisplay = 480, 1646 .vsync_start = 480 + 10, 1647 .vsync_end = 480 + 10 + 2, 1648 .vtotal = 480 + 10 + 2 + 33, 1649 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1650 }; 1651 1652 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1653 .modes = &dataimage_scf0700c48ggu18_mode, 1654 .num_modes = 1, 1655 .bpc = 8, 1656 .size = { 1657 .width = 152, 1658 .height = 91, 1659 }, 1660 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1661 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1662 }; 1663 1664 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1665 .pixelclock = { 45000000, 51200000, 57000000 }, 1666 .hactive = { 1024, 1024, 1024 }, 1667 .hfront_porch = { 100, 106, 113 }, 1668 .hback_porch = { 100, 106, 113 }, 1669 .hsync_len = { 100, 108, 114 }, 1670 .vactive = { 600, 600, 600 }, 1671 .vfront_porch = { 8, 11, 15 }, 1672 .vback_porch = { 8, 11, 15 }, 1673 .vsync_len = { 9, 13, 15 }, 1674 .flags = DISPLAY_FLAGS_DE_HIGH, 1675 }; 1676 1677 static const struct panel_desc dlc_dlc0700yzg_1 = { 1678 .timings = &dlc_dlc0700yzg_1_timing, 1679 .num_timings = 1, 1680 .bpc = 6, 1681 .size = { 1682 .width = 154, 1683 .height = 86, 1684 }, 1685 .delay = { 1686 .prepare = 30, 1687 .enable = 200, 1688 .disable = 200, 1689 }, 1690 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1691 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1692 }; 1693 1694 static const struct display_timing dlc_dlc1010gig_timing = { 1695 .pixelclock = { 68900000, 71100000, 73400000 }, 1696 .hactive = { 1280, 1280, 1280 }, 1697 .hfront_porch = { 43, 53, 63 }, 1698 .hback_porch = { 43, 53, 63 }, 1699 .hsync_len = { 44, 54, 64 }, 1700 .vactive = { 800, 800, 800 }, 1701 .vfront_porch = { 5, 8, 11 }, 1702 .vback_porch = { 5, 8, 11 }, 1703 .vsync_len = { 5, 7, 11 }, 1704 .flags = DISPLAY_FLAGS_DE_HIGH, 1705 }; 1706 1707 static const struct panel_desc dlc_dlc1010gig = { 1708 .timings = &dlc_dlc1010gig_timing, 1709 .num_timings = 1, 1710 .bpc = 8, 1711 .size = { 1712 .width = 216, 1713 .height = 135, 1714 }, 1715 .delay = { 1716 .prepare = 60, 1717 .enable = 150, 1718 .disable = 100, 1719 .unprepare = 60, 1720 }, 1721 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1722 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1723 }; 1724 1725 static const struct drm_display_mode edt_et035012dm6_mode = { 1726 .clock = 6500, 1727 .hdisplay = 320, 1728 .hsync_start = 320 + 20, 1729 .hsync_end = 320 + 20 + 30, 1730 .htotal = 320 + 20 + 68, 1731 .vdisplay = 240, 1732 .vsync_start = 240 + 4, 1733 .vsync_end = 240 + 4 + 4, 1734 .vtotal = 240 + 4 + 4 + 14, 1735 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1736 }; 1737 1738 static const struct panel_desc edt_et035012dm6 = { 1739 .modes = &edt_et035012dm6_mode, 1740 .num_modes = 1, 1741 .bpc = 8, 1742 .size = { 1743 .width = 70, 1744 .height = 52, 1745 }, 1746 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1747 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1748 }; 1749 1750 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1751 .clock = 6520, 1752 .hdisplay = 320, 1753 .hsync_start = 320 + 20, 1754 .hsync_end = 320 + 20 + 68, 1755 .htotal = 320 + 20 + 68, 1756 .vdisplay = 240, 1757 .vsync_start = 240 + 4, 1758 .vsync_end = 240 + 4 + 18, 1759 .vtotal = 240 + 4 + 18, 1760 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1761 }; 1762 1763 static const struct panel_desc edt_etm0350g0dh6 = { 1764 .modes = &edt_etm0350g0dh6_mode, 1765 .num_modes = 1, 1766 .bpc = 6, 1767 .size = { 1768 .width = 70, 1769 .height = 53, 1770 }, 1771 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1772 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1773 .connector_type = DRM_MODE_CONNECTOR_DPI, 1774 }; 1775 1776 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1777 .clock = 10870, 1778 .hdisplay = 480, 1779 .hsync_start = 480 + 8, 1780 .hsync_end = 480 + 8 + 4, 1781 .htotal = 480 + 8 + 4 + 41, 1782 1783 /* 1784 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1785 * fb_align 1786 */ 1787 1788 .vdisplay = 288, 1789 .vsync_start = 288 + 2, 1790 .vsync_end = 288 + 2 + 4, 1791 .vtotal = 288 + 2 + 4 + 10, 1792 }; 1793 1794 static const struct panel_desc edt_etm043080dh6gp = { 1795 .modes = &edt_etm043080dh6gp_mode, 1796 .num_modes = 1, 1797 .bpc = 8, 1798 .size = { 1799 .width = 100, 1800 .height = 65, 1801 }, 1802 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1803 .connector_type = DRM_MODE_CONNECTOR_DPI, 1804 }; 1805 1806 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1807 .clock = 9000, 1808 .hdisplay = 480, 1809 .hsync_start = 480 + 2, 1810 .hsync_end = 480 + 2 + 41, 1811 .htotal = 480 + 2 + 41 + 2, 1812 .vdisplay = 272, 1813 .vsync_start = 272 + 2, 1814 .vsync_end = 272 + 2 + 10, 1815 .vtotal = 272 + 2 + 10 + 2, 1816 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1817 }; 1818 1819 static const struct panel_desc edt_etm0430g0dh6 = { 1820 .modes = &edt_etm0430g0dh6_mode, 1821 .num_modes = 1, 1822 .bpc = 6, 1823 .size = { 1824 .width = 95, 1825 .height = 54, 1826 }, 1827 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1828 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1829 .connector_type = DRM_MODE_CONNECTOR_DPI, 1830 }; 1831 1832 static const struct drm_display_mode edt_et057090dhu_mode = { 1833 .clock = 25175, 1834 .hdisplay = 640, 1835 .hsync_start = 640 + 16, 1836 .hsync_end = 640 + 16 + 30, 1837 .htotal = 640 + 16 + 30 + 114, 1838 .vdisplay = 480, 1839 .vsync_start = 480 + 10, 1840 .vsync_end = 480 + 10 + 3, 1841 .vtotal = 480 + 10 + 3 + 32, 1842 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1843 }; 1844 1845 static const struct panel_desc edt_et057090dhu = { 1846 .modes = &edt_et057090dhu_mode, 1847 .num_modes = 1, 1848 .bpc = 6, 1849 .size = { 1850 .width = 115, 1851 .height = 86, 1852 }, 1853 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1854 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1855 .connector_type = DRM_MODE_CONNECTOR_DPI, 1856 }; 1857 1858 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1859 .clock = 33260, 1860 .hdisplay = 800, 1861 .hsync_start = 800 + 40, 1862 .hsync_end = 800 + 40 + 128, 1863 .htotal = 800 + 40 + 128 + 88, 1864 .vdisplay = 480, 1865 .vsync_start = 480 + 10, 1866 .vsync_end = 480 + 10 + 2, 1867 .vtotal = 480 + 10 + 2 + 33, 1868 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1869 }; 1870 1871 static const struct panel_desc edt_etm0700g0dh6 = { 1872 .modes = &edt_etm0700g0dh6_mode, 1873 .num_modes = 1, 1874 .bpc = 6, 1875 .size = { 1876 .width = 152, 1877 .height = 91, 1878 }, 1879 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1880 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1881 .connector_type = DRM_MODE_CONNECTOR_DPI, 1882 }; 1883 1884 static const struct panel_desc edt_etm0700g0bdh6 = { 1885 .modes = &edt_etm0700g0dh6_mode, 1886 .num_modes = 1, 1887 .bpc = 6, 1888 .size = { 1889 .width = 152, 1890 .height = 91, 1891 }, 1892 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1893 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1894 .connector_type = DRM_MODE_CONNECTOR_DPI, 1895 }; 1896 1897 static const struct display_timing edt_etml0700y5dha_timing = { 1898 .pixelclock = { 40800000, 51200000, 67200000 }, 1899 .hactive = { 1024, 1024, 1024 }, 1900 .hfront_porch = { 30, 106, 125 }, 1901 .hback_porch = { 30, 106, 125 }, 1902 .hsync_len = { 30, 108, 126 }, 1903 .vactive = { 600, 600, 600 }, 1904 .vfront_porch = { 3, 12, 67}, 1905 .vback_porch = { 3, 12, 67 }, 1906 .vsync_len = { 4, 11, 66 }, 1907 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1908 DISPLAY_FLAGS_DE_HIGH, 1909 }; 1910 1911 static const struct panel_desc edt_etml0700y5dha = { 1912 .timings = &edt_etml0700y5dha_timing, 1913 .num_timings = 1, 1914 .bpc = 8, 1915 .size = { 1916 .width = 155, 1917 .height = 86, 1918 }, 1919 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1920 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1921 }; 1922 1923 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1924 .clock = 25175, 1925 .hdisplay = 640, 1926 .hsync_start = 640, 1927 .hsync_end = 640 + 16, 1928 .htotal = 640 + 16 + 30 + 114, 1929 .vdisplay = 480, 1930 .vsync_start = 480 + 10, 1931 .vsync_end = 480 + 10 + 3, 1932 .vtotal = 480 + 10 + 3 + 35, 1933 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1934 }; 1935 1936 static const struct panel_desc edt_etmv570g2dhu = { 1937 .modes = &edt_etmv570g2dhu_mode, 1938 .num_modes = 1, 1939 .bpc = 6, 1940 .size = { 1941 .width = 115, 1942 .height = 86, 1943 }, 1944 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1945 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1946 .connector_type = DRM_MODE_CONNECTOR_DPI, 1947 }; 1948 1949 static const struct display_timing eink_vb3300_kca_timing = { 1950 .pixelclock = { 40000000, 40000000, 40000000 }, 1951 .hactive = { 334, 334, 334 }, 1952 .hfront_porch = { 1, 1, 1 }, 1953 .hback_porch = { 1, 1, 1 }, 1954 .hsync_len = { 1, 1, 1 }, 1955 .vactive = { 1405, 1405, 1405 }, 1956 .vfront_porch = { 1, 1, 1 }, 1957 .vback_porch = { 1, 1, 1 }, 1958 .vsync_len = { 1, 1, 1 }, 1959 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1960 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1961 }; 1962 1963 static const struct panel_desc eink_vb3300_kca = { 1964 .timings = &eink_vb3300_kca_timing, 1965 .num_timings = 1, 1966 .bpc = 6, 1967 .size = { 1968 .width = 157, 1969 .height = 209, 1970 }, 1971 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1972 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1973 .connector_type = DRM_MODE_CONNECTOR_DPI, 1974 }; 1975 1976 static const struct display_timing evervision_vgg804821_timing = { 1977 .pixelclock = { 27600000, 33300000, 50000000 }, 1978 .hactive = { 800, 800, 800 }, 1979 .hfront_porch = { 40, 66, 70 }, 1980 .hback_porch = { 40, 67, 70 }, 1981 .hsync_len = { 40, 67, 70 }, 1982 .vactive = { 480, 480, 480 }, 1983 .vfront_porch = { 6, 10, 10 }, 1984 .vback_porch = { 7, 11, 11 }, 1985 .vsync_len = { 7, 11, 11 }, 1986 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1987 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1988 DISPLAY_FLAGS_SYNC_NEGEDGE, 1989 }; 1990 1991 static const struct panel_desc evervision_vgg804821 = { 1992 .timings = &evervision_vgg804821_timing, 1993 .num_timings = 1, 1994 .bpc = 8, 1995 .size = { 1996 .width = 108, 1997 .height = 64, 1998 }, 1999 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2000 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2001 }; 2002 2003 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2004 .clock = 32260, 2005 .hdisplay = 800, 2006 .hsync_start = 800 + 168, 2007 .hsync_end = 800 + 168 + 64, 2008 .htotal = 800 + 168 + 64 + 88, 2009 .vdisplay = 480, 2010 .vsync_start = 480 + 37, 2011 .vsync_end = 480 + 37 + 2, 2012 .vtotal = 480 + 37 + 2 + 8, 2013 }; 2014 2015 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2016 .modes = &foxlink_fl500wvr00_a0t_mode, 2017 .num_modes = 1, 2018 .bpc = 8, 2019 .size = { 2020 .width = 108, 2021 .height = 65, 2022 }, 2023 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2024 }; 2025 2026 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2027 { /* 60 Hz */ 2028 .clock = 6000, 2029 .hdisplay = 320, 2030 .hsync_start = 320 + 44, 2031 .hsync_end = 320 + 44 + 16, 2032 .htotal = 320 + 44 + 16 + 20, 2033 .vdisplay = 240, 2034 .vsync_start = 240 + 2, 2035 .vsync_end = 240 + 2 + 6, 2036 .vtotal = 240 + 2 + 6 + 2, 2037 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2038 }, 2039 { /* 50 Hz */ 2040 .clock = 5400, 2041 .hdisplay = 320, 2042 .hsync_start = 320 + 56, 2043 .hsync_end = 320 + 56 + 16, 2044 .htotal = 320 + 56 + 16 + 40, 2045 .vdisplay = 240, 2046 .vsync_start = 240 + 2, 2047 .vsync_end = 240 + 2 + 6, 2048 .vtotal = 240 + 2 + 6 + 2, 2049 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2050 }, 2051 }; 2052 2053 static const struct panel_desc frida_frd350h54004 = { 2054 .modes = frida_frd350h54004_modes, 2055 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2056 .bpc = 8, 2057 .size = { 2058 .width = 77, 2059 .height = 64, 2060 }, 2061 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2062 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2063 .connector_type = DRM_MODE_CONNECTOR_DPI, 2064 }; 2065 2066 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2067 .clock = 67185, 2068 .hdisplay = 800, 2069 .hsync_start = 800 + 20, 2070 .hsync_end = 800 + 20 + 24, 2071 .htotal = 800 + 20 + 24 + 20, 2072 .vdisplay = 1280, 2073 .vsync_start = 1280 + 4, 2074 .vsync_end = 1280 + 4 + 8, 2075 .vtotal = 1280 + 4 + 8 + 4, 2076 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2077 }; 2078 2079 static const struct panel_desc friendlyarm_hd702e = { 2080 .modes = &friendlyarm_hd702e_mode, 2081 .num_modes = 1, 2082 .size = { 2083 .width = 94, 2084 .height = 151, 2085 }, 2086 }; 2087 2088 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2089 .clock = 9000, 2090 .hdisplay = 480, 2091 .hsync_start = 480 + 5, 2092 .hsync_end = 480 + 5 + 1, 2093 .htotal = 480 + 5 + 1 + 40, 2094 .vdisplay = 272, 2095 .vsync_start = 272 + 8, 2096 .vsync_end = 272 + 8 + 1, 2097 .vtotal = 272 + 8 + 1 + 8, 2098 }; 2099 2100 static const struct panel_desc giantplus_gpg482739qs5 = { 2101 .modes = &giantplus_gpg482739qs5_mode, 2102 .num_modes = 1, 2103 .bpc = 8, 2104 .size = { 2105 .width = 95, 2106 .height = 54, 2107 }, 2108 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2109 }; 2110 2111 static const struct display_timing giantplus_gpm940b0_timing = { 2112 .pixelclock = { 13500000, 27000000, 27500000 }, 2113 .hactive = { 320, 320, 320 }, 2114 .hfront_porch = { 14, 686, 718 }, 2115 .hback_porch = { 50, 70, 255 }, 2116 .hsync_len = { 1, 1, 1 }, 2117 .vactive = { 240, 240, 240 }, 2118 .vfront_porch = { 1, 1, 179 }, 2119 .vback_porch = { 1, 21, 31 }, 2120 .vsync_len = { 1, 1, 6 }, 2121 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2122 }; 2123 2124 static const struct panel_desc giantplus_gpm940b0 = { 2125 .timings = &giantplus_gpm940b0_timing, 2126 .num_timings = 1, 2127 .bpc = 8, 2128 .size = { 2129 .width = 60, 2130 .height = 45, 2131 }, 2132 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2133 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2134 }; 2135 2136 static const struct display_timing hannstar_hsd070pww1_timing = { 2137 .pixelclock = { 64300000, 71100000, 82000000 }, 2138 .hactive = { 1280, 1280, 1280 }, 2139 .hfront_porch = { 1, 1, 10 }, 2140 .hback_porch = { 1, 1, 10 }, 2141 /* 2142 * According to the data sheet, the minimum horizontal blanking interval 2143 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2144 * minimum working horizontal blanking interval to be 60 clocks. 2145 */ 2146 .hsync_len = { 58, 158, 661 }, 2147 .vactive = { 800, 800, 800 }, 2148 .vfront_porch = { 1, 1, 10 }, 2149 .vback_porch = { 1, 1, 10 }, 2150 .vsync_len = { 1, 21, 203 }, 2151 .flags = DISPLAY_FLAGS_DE_HIGH, 2152 }; 2153 2154 static const struct panel_desc hannstar_hsd070pww1 = { 2155 .timings = &hannstar_hsd070pww1_timing, 2156 .num_timings = 1, 2157 .bpc = 6, 2158 .size = { 2159 .width = 151, 2160 .height = 94, 2161 }, 2162 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2163 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2164 }; 2165 2166 static const struct display_timing hannstar_hsd100pxn1_timing = { 2167 .pixelclock = { 55000000, 65000000, 75000000 }, 2168 .hactive = { 1024, 1024, 1024 }, 2169 .hfront_porch = { 40, 40, 40 }, 2170 .hback_porch = { 220, 220, 220 }, 2171 .hsync_len = { 20, 60, 100 }, 2172 .vactive = { 768, 768, 768 }, 2173 .vfront_porch = { 7, 7, 7 }, 2174 .vback_porch = { 21, 21, 21 }, 2175 .vsync_len = { 10, 10, 10 }, 2176 .flags = DISPLAY_FLAGS_DE_HIGH, 2177 }; 2178 2179 static const struct panel_desc hannstar_hsd100pxn1 = { 2180 .timings = &hannstar_hsd100pxn1_timing, 2181 .num_timings = 1, 2182 .bpc = 6, 2183 .size = { 2184 .width = 203, 2185 .height = 152, 2186 }, 2187 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2188 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2189 }; 2190 2191 static const struct display_timing hannstar_hsd101pww2_timing = { 2192 .pixelclock = { 64300000, 71100000, 82000000 }, 2193 .hactive = { 1280, 1280, 1280 }, 2194 .hfront_porch = { 1, 1, 10 }, 2195 .hback_porch = { 1, 1, 10 }, 2196 .hsync_len = { 58, 158, 661 }, 2197 .vactive = { 800, 800, 800 }, 2198 .vfront_porch = { 1, 1, 10 }, 2199 .vback_porch = { 1, 1, 10 }, 2200 .vsync_len = { 1, 21, 203 }, 2201 .flags = DISPLAY_FLAGS_DE_HIGH, 2202 }; 2203 2204 static const struct panel_desc hannstar_hsd101pww2 = { 2205 .timings = &hannstar_hsd101pww2_timing, 2206 .num_timings = 1, 2207 .bpc = 8, 2208 .size = { 2209 .width = 217, 2210 .height = 136, 2211 }, 2212 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2213 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2214 }; 2215 2216 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2217 .clock = 33333, 2218 .hdisplay = 800, 2219 .hsync_start = 800 + 85, 2220 .hsync_end = 800 + 85 + 86, 2221 .htotal = 800 + 85 + 86 + 85, 2222 .vdisplay = 480, 2223 .vsync_start = 480 + 16, 2224 .vsync_end = 480 + 16 + 13, 2225 .vtotal = 480 + 16 + 13 + 16, 2226 }; 2227 2228 static const struct panel_desc hitachi_tx23d38vm0caa = { 2229 .modes = &hitachi_tx23d38vm0caa_mode, 2230 .num_modes = 1, 2231 .bpc = 6, 2232 .size = { 2233 .width = 195, 2234 .height = 117, 2235 }, 2236 .delay = { 2237 .enable = 160, 2238 .disable = 160, 2239 }, 2240 }; 2241 2242 static const struct drm_display_mode innolux_at043tn24_mode = { 2243 .clock = 9000, 2244 .hdisplay = 480, 2245 .hsync_start = 480 + 2, 2246 .hsync_end = 480 + 2 + 41, 2247 .htotal = 480 + 2 + 41 + 2, 2248 .vdisplay = 272, 2249 .vsync_start = 272 + 2, 2250 .vsync_end = 272 + 2 + 10, 2251 .vtotal = 272 + 2 + 10 + 2, 2252 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2253 }; 2254 2255 static const struct panel_desc innolux_at043tn24 = { 2256 .modes = &innolux_at043tn24_mode, 2257 .num_modes = 1, 2258 .bpc = 8, 2259 .size = { 2260 .width = 95, 2261 .height = 54, 2262 }, 2263 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2264 .connector_type = DRM_MODE_CONNECTOR_DPI, 2265 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2266 }; 2267 2268 static const struct drm_display_mode innolux_at070tn92_mode = { 2269 .clock = 33333, 2270 .hdisplay = 800, 2271 .hsync_start = 800 + 210, 2272 .hsync_end = 800 + 210 + 20, 2273 .htotal = 800 + 210 + 20 + 46, 2274 .vdisplay = 480, 2275 .vsync_start = 480 + 22, 2276 .vsync_end = 480 + 22 + 10, 2277 .vtotal = 480 + 22 + 23 + 10, 2278 }; 2279 2280 static const struct panel_desc innolux_at070tn92 = { 2281 .modes = &innolux_at070tn92_mode, 2282 .num_modes = 1, 2283 .size = { 2284 .width = 154, 2285 .height = 86, 2286 }, 2287 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2288 }; 2289 2290 static const struct display_timing innolux_g070ace_l01_timing = { 2291 .pixelclock = { 25200000, 35000000, 35700000 }, 2292 .hactive = { 800, 800, 800 }, 2293 .hfront_porch = { 30, 32, 87 }, 2294 .hback_porch = { 30, 32, 87 }, 2295 .hsync_len = { 1, 1, 1 }, 2296 .vactive = { 480, 480, 480 }, 2297 .vfront_porch = { 3, 3, 3 }, 2298 .vback_porch = { 13, 13, 13 }, 2299 .vsync_len = { 1, 1, 4 }, 2300 .flags = DISPLAY_FLAGS_DE_HIGH, 2301 }; 2302 2303 static const struct panel_desc innolux_g070ace_l01 = { 2304 .timings = &innolux_g070ace_l01_timing, 2305 .num_timings = 1, 2306 .bpc = 8, 2307 .size = { 2308 .width = 152, 2309 .height = 91, 2310 }, 2311 .delay = { 2312 .prepare = 10, 2313 .enable = 50, 2314 .disable = 50, 2315 .unprepare = 500, 2316 }, 2317 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2318 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2319 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2320 }; 2321 2322 static const struct display_timing innolux_g070y2_l01_timing = { 2323 .pixelclock = { 28000000, 29500000, 32000000 }, 2324 .hactive = { 800, 800, 800 }, 2325 .hfront_porch = { 61, 91, 141 }, 2326 .hback_porch = { 60, 90, 140 }, 2327 .hsync_len = { 12, 12, 12 }, 2328 .vactive = { 480, 480, 480 }, 2329 .vfront_porch = { 4, 9, 30 }, 2330 .vback_porch = { 4, 8, 28 }, 2331 .vsync_len = { 2, 2, 2 }, 2332 .flags = DISPLAY_FLAGS_DE_HIGH, 2333 }; 2334 2335 static const struct panel_desc innolux_g070y2_l01 = { 2336 .timings = &innolux_g070y2_l01_timing, 2337 .num_timings = 1, 2338 .bpc = 8, 2339 .size = { 2340 .width = 152, 2341 .height = 91, 2342 }, 2343 .delay = { 2344 .prepare = 10, 2345 .enable = 100, 2346 .disable = 100, 2347 .unprepare = 800, 2348 }, 2349 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2350 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2351 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2352 }; 2353 2354 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2355 .clock = 33333, 2356 .hdisplay = 800, 2357 .hsync_start = 800 + 210, 2358 .hsync_end = 800 + 210 + 20, 2359 .htotal = 800 + 210 + 20 + 46, 2360 .vdisplay = 480, 2361 .vsync_start = 480 + 22, 2362 .vsync_end = 480 + 22 + 10, 2363 .vtotal = 480 + 22 + 23 + 10, 2364 }; 2365 2366 static const struct panel_desc innolux_g070y2_t02 = { 2367 .modes = &innolux_g070y2_t02_mode, 2368 .num_modes = 1, 2369 .bpc = 8, 2370 .size = { 2371 .width = 152, 2372 .height = 92, 2373 }, 2374 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2375 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2376 .connector_type = DRM_MODE_CONNECTOR_DPI, 2377 }; 2378 2379 static const struct display_timing innolux_g101ice_l01_timing = { 2380 .pixelclock = { 60400000, 71100000, 74700000 }, 2381 .hactive = { 1280, 1280, 1280 }, 2382 .hfront_porch = { 41, 80, 100 }, 2383 .hback_porch = { 40, 79, 99 }, 2384 .hsync_len = { 1, 1, 1 }, 2385 .vactive = { 800, 800, 800 }, 2386 .vfront_porch = { 5, 11, 14 }, 2387 .vback_porch = { 4, 11, 14 }, 2388 .vsync_len = { 1, 1, 1 }, 2389 .flags = DISPLAY_FLAGS_DE_HIGH, 2390 }; 2391 2392 static const struct panel_desc innolux_g101ice_l01 = { 2393 .timings = &innolux_g101ice_l01_timing, 2394 .num_timings = 1, 2395 .bpc = 8, 2396 .size = { 2397 .width = 217, 2398 .height = 135, 2399 }, 2400 .delay = { 2401 .enable = 200, 2402 .disable = 200, 2403 }, 2404 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2405 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2406 }; 2407 2408 static const struct display_timing innolux_g121i1_l01_timing = { 2409 .pixelclock = { 67450000, 71000000, 74550000 }, 2410 .hactive = { 1280, 1280, 1280 }, 2411 .hfront_porch = { 40, 80, 160 }, 2412 .hback_porch = { 39, 79, 159 }, 2413 .hsync_len = { 1, 1, 1 }, 2414 .vactive = { 800, 800, 800 }, 2415 .vfront_porch = { 5, 11, 100 }, 2416 .vback_porch = { 4, 11, 99 }, 2417 .vsync_len = { 1, 1, 1 }, 2418 }; 2419 2420 static const struct panel_desc innolux_g121i1_l01 = { 2421 .timings = &innolux_g121i1_l01_timing, 2422 .num_timings = 1, 2423 .bpc = 6, 2424 .size = { 2425 .width = 261, 2426 .height = 163, 2427 }, 2428 .delay = { 2429 .enable = 200, 2430 .disable = 20, 2431 }, 2432 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2433 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2434 }; 2435 2436 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2437 .clock = 65000, 2438 .hdisplay = 1024, 2439 .hsync_start = 1024 + 0, 2440 .hsync_end = 1024 + 1, 2441 .htotal = 1024 + 0 + 1 + 320, 2442 .vdisplay = 768, 2443 .vsync_start = 768 + 38, 2444 .vsync_end = 768 + 38 + 1, 2445 .vtotal = 768 + 38 + 1 + 0, 2446 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2447 }; 2448 2449 static const struct panel_desc innolux_g121x1_l03 = { 2450 .modes = &innolux_g121x1_l03_mode, 2451 .num_modes = 1, 2452 .bpc = 6, 2453 .size = { 2454 .width = 246, 2455 .height = 185, 2456 }, 2457 .delay = { 2458 .enable = 200, 2459 .unprepare = 200, 2460 .disable = 400, 2461 }, 2462 }; 2463 2464 static const struct display_timing innolux_g156hce_l01_timings = { 2465 .pixelclock = { 120000000, 141860000, 150000000 }, 2466 .hactive = { 1920, 1920, 1920 }, 2467 .hfront_porch = { 80, 90, 100 }, 2468 .hback_porch = { 80, 90, 100 }, 2469 .hsync_len = { 20, 30, 30 }, 2470 .vactive = { 1080, 1080, 1080 }, 2471 .vfront_porch = { 3, 10, 20 }, 2472 .vback_porch = { 3, 10, 20 }, 2473 .vsync_len = { 4, 10, 10 }, 2474 }; 2475 2476 static const struct panel_desc innolux_g156hce_l01 = { 2477 .timings = &innolux_g156hce_l01_timings, 2478 .num_timings = 1, 2479 .bpc = 8, 2480 .size = { 2481 .width = 344, 2482 .height = 194, 2483 }, 2484 .delay = { 2485 .prepare = 1, /* T1+T2 */ 2486 .enable = 450, /* T5 */ 2487 .disable = 200, /* T6 */ 2488 .unprepare = 10, /* T3+T7 */ 2489 }, 2490 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2491 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2492 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2493 }; 2494 2495 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2496 .clock = 69300, 2497 .hdisplay = 1366, 2498 .hsync_start = 1366 + 16, 2499 .hsync_end = 1366 + 16 + 34, 2500 .htotal = 1366 + 16 + 34 + 50, 2501 .vdisplay = 768, 2502 .vsync_start = 768 + 2, 2503 .vsync_end = 768 + 2 + 6, 2504 .vtotal = 768 + 2 + 6 + 12, 2505 }; 2506 2507 static const struct panel_desc innolux_n156bge_l21 = { 2508 .modes = &innolux_n156bge_l21_mode, 2509 .num_modes = 1, 2510 .bpc = 6, 2511 .size = { 2512 .width = 344, 2513 .height = 193, 2514 }, 2515 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2516 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2517 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2518 }; 2519 2520 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2521 .clock = 51501, 2522 .hdisplay = 1024, 2523 .hsync_start = 1024 + 128, 2524 .hsync_end = 1024 + 128 + 64, 2525 .htotal = 1024 + 128 + 64 + 128, 2526 .vdisplay = 600, 2527 .vsync_start = 600 + 16, 2528 .vsync_end = 600 + 16 + 4, 2529 .vtotal = 600 + 16 + 4 + 16, 2530 }; 2531 2532 static const struct panel_desc innolux_zj070na_01p = { 2533 .modes = &innolux_zj070na_01p_mode, 2534 .num_modes = 1, 2535 .bpc = 6, 2536 .size = { 2537 .width = 154, 2538 .height = 90, 2539 }, 2540 }; 2541 2542 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2543 .pixelclock = { 5580000, 5850000, 6200000 }, 2544 .hactive = { 320, 320, 320 }, 2545 .hfront_porch = { 30, 30, 30 }, 2546 .hback_porch = { 30, 30, 30 }, 2547 .hsync_len = { 1, 5, 17 }, 2548 .vactive = { 240, 240, 240 }, 2549 .vfront_porch = { 6, 6, 6 }, 2550 .vback_porch = { 5, 5, 5 }, 2551 .vsync_len = { 1, 2, 11 }, 2552 .flags = DISPLAY_FLAGS_DE_HIGH, 2553 }; 2554 2555 static const struct panel_desc koe_tx14d24vm1bpa = { 2556 .timings = &koe_tx14d24vm1bpa_timing, 2557 .num_timings = 1, 2558 .bpc = 6, 2559 .size = { 2560 .width = 115, 2561 .height = 86, 2562 }, 2563 }; 2564 2565 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2566 .pixelclock = { 151820000, 156720000, 159780000 }, 2567 .hactive = { 1920, 1920, 1920 }, 2568 .hfront_porch = { 105, 130, 142 }, 2569 .hback_porch = { 45, 70, 82 }, 2570 .hsync_len = { 30, 30, 30 }, 2571 .vactive = { 1200, 1200, 1200}, 2572 .vfront_porch = { 3, 5, 10 }, 2573 .vback_porch = { 2, 5, 10 }, 2574 .vsync_len = { 5, 5, 5 }, 2575 }; 2576 2577 static const struct panel_desc koe_tx26d202vm0bwa = { 2578 .timings = &koe_tx26d202vm0bwa_timing, 2579 .num_timings = 1, 2580 .bpc = 8, 2581 .size = { 2582 .width = 217, 2583 .height = 136, 2584 }, 2585 .delay = { 2586 .prepare = 1000, 2587 .enable = 1000, 2588 .unprepare = 1000, 2589 .disable = 1000, 2590 }, 2591 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2592 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2593 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2594 }; 2595 2596 static const struct display_timing koe_tx31d200vm0baa_timing = { 2597 .pixelclock = { 39600000, 43200000, 48000000 }, 2598 .hactive = { 1280, 1280, 1280 }, 2599 .hfront_porch = { 16, 36, 56 }, 2600 .hback_porch = { 16, 36, 56 }, 2601 .hsync_len = { 8, 8, 8 }, 2602 .vactive = { 480, 480, 480 }, 2603 .vfront_porch = { 6, 21, 33 }, 2604 .vback_porch = { 6, 21, 33 }, 2605 .vsync_len = { 8, 8, 8 }, 2606 .flags = DISPLAY_FLAGS_DE_HIGH, 2607 }; 2608 2609 static const struct panel_desc koe_tx31d200vm0baa = { 2610 .timings = &koe_tx31d200vm0baa_timing, 2611 .num_timings = 1, 2612 .bpc = 6, 2613 .size = { 2614 .width = 292, 2615 .height = 109, 2616 }, 2617 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2618 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2619 }; 2620 2621 static const struct display_timing kyo_tcg121xglp_timing = { 2622 .pixelclock = { 52000000, 65000000, 71000000 }, 2623 .hactive = { 1024, 1024, 1024 }, 2624 .hfront_porch = { 2, 2, 2 }, 2625 .hback_porch = { 2, 2, 2 }, 2626 .hsync_len = { 86, 124, 244 }, 2627 .vactive = { 768, 768, 768 }, 2628 .vfront_porch = { 2, 2, 2 }, 2629 .vback_porch = { 2, 2, 2 }, 2630 .vsync_len = { 6, 34, 73 }, 2631 .flags = DISPLAY_FLAGS_DE_HIGH, 2632 }; 2633 2634 static const struct panel_desc kyo_tcg121xglp = { 2635 .timings = &kyo_tcg121xglp_timing, 2636 .num_timings = 1, 2637 .bpc = 8, 2638 .size = { 2639 .width = 246, 2640 .height = 184, 2641 }, 2642 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2643 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2644 }; 2645 2646 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2647 .clock = 7000, 2648 .hdisplay = 320, 2649 .hsync_start = 320 + 20, 2650 .hsync_end = 320 + 20 + 30, 2651 .htotal = 320 + 20 + 30 + 38, 2652 .vdisplay = 240, 2653 .vsync_start = 240 + 4, 2654 .vsync_end = 240 + 4 + 3, 2655 .vtotal = 240 + 4 + 3 + 15, 2656 }; 2657 2658 static const struct panel_desc lemaker_bl035_rgb_002 = { 2659 .modes = &lemaker_bl035_rgb_002_mode, 2660 .num_modes = 1, 2661 .size = { 2662 .width = 70, 2663 .height = 52, 2664 }, 2665 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2666 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2667 }; 2668 2669 static const struct drm_display_mode lg_lb070wv8_mode = { 2670 .clock = 33246, 2671 .hdisplay = 800, 2672 .hsync_start = 800 + 88, 2673 .hsync_end = 800 + 88 + 80, 2674 .htotal = 800 + 88 + 80 + 88, 2675 .vdisplay = 480, 2676 .vsync_start = 480 + 10, 2677 .vsync_end = 480 + 10 + 25, 2678 .vtotal = 480 + 10 + 25 + 10, 2679 }; 2680 2681 static const struct panel_desc lg_lb070wv8 = { 2682 .modes = &lg_lb070wv8_mode, 2683 .num_modes = 1, 2684 .bpc = 8, 2685 .size = { 2686 .width = 151, 2687 .height = 91, 2688 }, 2689 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2690 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2691 }; 2692 2693 static const struct display_timing logictechno_lt161010_2nh_timing = { 2694 .pixelclock = { 26400000, 33300000, 46800000 }, 2695 .hactive = { 800, 800, 800 }, 2696 .hfront_porch = { 16, 210, 354 }, 2697 .hback_porch = { 46, 46, 46 }, 2698 .hsync_len = { 1, 20, 40 }, 2699 .vactive = { 480, 480, 480 }, 2700 .vfront_porch = { 7, 22, 147 }, 2701 .vback_porch = { 23, 23, 23 }, 2702 .vsync_len = { 1, 10, 20 }, 2703 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2704 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2705 DISPLAY_FLAGS_SYNC_POSEDGE, 2706 }; 2707 2708 static const struct panel_desc logictechno_lt161010_2nh = { 2709 .timings = &logictechno_lt161010_2nh_timing, 2710 .num_timings = 1, 2711 .bpc = 6, 2712 .size = { 2713 .width = 154, 2714 .height = 86, 2715 }, 2716 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2717 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2718 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2719 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2720 .connector_type = DRM_MODE_CONNECTOR_DPI, 2721 }; 2722 2723 static const struct display_timing logictechno_lt170410_2whc_timing = { 2724 .pixelclock = { 68900000, 71100000, 73400000 }, 2725 .hactive = { 1280, 1280, 1280 }, 2726 .hfront_porch = { 23, 60, 71 }, 2727 .hback_porch = { 23, 60, 71 }, 2728 .hsync_len = { 15, 40, 47 }, 2729 .vactive = { 800, 800, 800 }, 2730 .vfront_porch = { 5, 7, 10 }, 2731 .vback_porch = { 5, 7, 10 }, 2732 .vsync_len = { 6, 9, 12 }, 2733 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2734 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2735 DISPLAY_FLAGS_SYNC_POSEDGE, 2736 }; 2737 2738 static const struct panel_desc logictechno_lt170410_2whc = { 2739 .timings = &logictechno_lt170410_2whc_timing, 2740 .num_timings = 1, 2741 .bpc = 8, 2742 .size = { 2743 .width = 217, 2744 .height = 136, 2745 }, 2746 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2747 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2748 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2749 }; 2750 2751 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2752 .clock = 33000, 2753 .hdisplay = 800, 2754 .hsync_start = 800 + 112, 2755 .hsync_end = 800 + 112 + 3, 2756 .htotal = 800 + 112 + 3 + 85, 2757 .vdisplay = 480, 2758 .vsync_start = 480 + 38, 2759 .vsync_end = 480 + 38 + 3, 2760 .vtotal = 480 + 38 + 3 + 29, 2761 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2762 }; 2763 2764 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2765 .modes = &logictechno_lttd800480070_l2rt_mode, 2766 .num_modes = 1, 2767 .bpc = 8, 2768 .size = { 2769 .width = 154, 2770 .height = 86, 2771 }, 2772 .delay = { 2773 .prepare = 45, 2774 .enable = 100, 2775 .disable = 100, 2776 .unprepare = 45 2777 }, 2778 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2779 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2780 .connector_type = DRM_MODE_CONNECTOR_DPI, 2781 }; 2782 2783 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2784 .clock = 33000, 2785 .hdisplay = 800, 2786 .hsync_start = 800 + 154, 2787 .hsync_end = 800 + 154 + 3, 2788 .htotal = 800 + 154 + 3 + 43, 2789 .vdisplay = 480, 2790 .vsync_start = 480 + 47, 2791 .vsync_end = 480 + 47 + 3, 2792 .vtotal = 480 + 47 + 3 + 20, 2793 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2794 }; 2795 2796 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2797 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2798 .num_modes = 1, 2799 .bpc = 8, 2800 .size = { 2801 .width = 154, 2802 .height = 86, 2803 }, 2804 .delay = { 2805 .prepare = 45, 2806 .enable = 100, 2807 .disable = 100, 2808 .unprepare = 45 2809 }, 2810 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2811 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2812 .connector_type = DRM_MODE_CONNECTOR_DPI, 2813 }; 2814 2815 static const struct drm_display_mode logicpd_type_28_mode = { 2816 .clock = 9107, 2817 .hdisplay = 480, 2818 .hsync_start = 480 + 3, 2819 .hsync_end = 480 + 3 + 42, 2820 .htotal = 480 + 3 + 42 + 2, 2821 2822 .vdisplay = 272, 2823 .vsync_start = 272 + 2, 2824 .vsync_end = 272 + 2 + 11, 2825 .vtotal = 272 + 2 + 11 + 3, 2826 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2827 }; 2828 2829 static const struct panel_desc logicpd_type_28 = { 2830 .modes = &logicpd_type_28_mode, 2831 .num_modes = 1, 2832 .bpc = 8, 2833 .size = { 2834 .width = 105, 2835 .height = 67, 2836 }, 2837 .delay = { 2838 .prepare = 200, 2839 .enable = 200, 2840 .unprepare = 200, 2841 .disable = 200, 2842 }, 2843 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2844 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2845 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2846 .connector_type = DRM_MODE_CONNECTOR_DPI, 2847 }; 2848 2849 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2850 .clock = 30400, 2851 .hdisplay = 800, 2852 .hsync_start = 800 + 0, 2853 .hsync_end = 800 + 1, 2854 .htotal = 800 + 0 + 1 + 160, 2855 .vdisplay = 480, 2856 .vsync_start = 480 + 0, 2857 .vsync_end = 480 + 48 + 1, 2858 .vtotal = 480 + 48 + 1 + 0, 2859 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2860 }; 2861 2862 static const struct panel_desc mitsubishi_aa070mc01 = { 2863 .modes = &mitsubishi_aa070mc01_mode, 2864 .num_modes = 1, 2865 .bpc = 8, 2866 .size = { 2867 .width = 152, 2868 .height = 91, 2869 }, 2870 2871 .delay = { 2872 .enable = 200, 2873 .unprepare = 200, 2874 .disable = 400, 2875 }, 2876 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2877 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2878 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2879 }; 2880 2881 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 2882 .clock = 56234, 2883 .hdisplay = 1024, 2884 .hsync_start = 1024 + 24, 2885 .hsync_end = 1024 + 24 + 63, 2886 .htotal = 1024 + 24 + 63 + 1, 2887 .vdisplay = 768, 2888 .vsync_start = 768 + 3, 2889 .vsync_end = 768 + 3 + 6, 2890 .vtotal = 768 + 3 + 6 + 1, 2891 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2892 }; 2893 2894 static const struct panel_desc mitsubishi_aa084xe01 = { 2895 .modes = &mitsubishi_aa084xe01_mode, 2896 .num_modes = 1, 2897 .bpc = 8, 2898 .size = { 2899 .width = 1024, 2900 .height = 768, 2901 }, 2902 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 2903 .connector_type = DRM_MODE_CONNECTOR_DPI, 2904 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2905 }; 2906 2907 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2908 .pixelclock = { 29000000, 33000000, 38000000 }, 2909 .hactive = { 800, 800, 800 }, 2910 .hfront_porch = { 180, 210, 240 }, 2911 .hback_porch = { 16, 16, 16 }, 2912 .hsync_len = { 30, 30, 30 }, 2913 .vactive = { 480, 480, 480 }, 2914 .vfront_porch = { 12, 22, 32 }, 2915 .vback_porch = { 10, 10, 10 }, 2916 .vsync_len = { 13, 13, 13 }, 2917 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2918 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2919 DISPLAY_FLAGS_SYNC_POSEDGE, 2920 }; 2921 2922 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2923 .timings = &multi_inno_mi0700s4t_6_timing, 2924 .num_timings = 1, 2925 .bpc = 8, 2926 .size = { 2927 .width = 154, 2928 .height = 86, 2929 }, 2930 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2931 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2932 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2933 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2934 .connector_type = DRM_MODE_CONNECTOR_DPI, 2935 }; 2936 2937 static const struct display_timing multi_inno_mi0800ft_9_timing = { 2938 .pixelclock = { 32000000, 40000000, 50000000 }, 2939 .hactive = { 800, 800, 800 }, 2940 .hfront_porch = { 16, 210, 354 }, 2941 .hback_porch = { 6, 26, 45 }, 2942 .hsync_len = { 1, 20, 40 }, 2943 .vactive = { 600, 600, 600 }, 2944 .vfront_porch = { 1, 12, 77 }, 2945 .vback_porch = { 3, 13, 22 }, 2946 .vsync_len = { 1, 10, 20 }, 2947 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2948 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2949 DISPLAY_FLAGS_SYNC_POSEDGE, 2950 }; 2951 2952 static const struct panel_desc multi_inno_mi0800ft_9 = { 2953 .timings = &multi_inno_mi0800ft_9_timing, 2954 .num_timings = 1, 2955 .bpc = 8, 2956 .size = { 2957 .width = 162, 2958 .height = 122, 2959 }, 2960 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2961 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2962 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2963 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2964 .connector_type = DRM_MODE_CONNECTOR_DPI, 2965 }; 2966 2967 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2968 .pixelclock = { 68900000, 70000000, 73400000 }, 2969 .hactive = { 1280, 1280, 1280 }, 2970 .hfront_porch = { 30, 60, 71 }, 2971 .hback_porch = { 30, 60, 71 }, 2972 .hsync_len = { 10, 10, 48 }, 2973 .vactive = { 800, 800, 800 }, 2974 .vfront_porch = { 5, 10, 10 }, 2975 .vback_porch = { 5, 10, 10 }, 2976 .vsync_len = { 5, 6, 13 }, 2977 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2978 DISPLAY_FLAGS_DE_HIGH, 2979 }; 2980 2981 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2982 .timings = &multi_inno_mi1010ait_1cp_timing, 2983 .num_timings = 1, 2984 .bpc = 8, 2985 .size = { 2986 .width = 217, 2987 .height = 136, 2988 }, 2989 .delay = { 2990 .enable = 50, 2991 .disable = 50, 2992 }, 2993 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2994 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2995 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2996 }; 2997 2998 static const struct display_timing nec_nl12880bc20_05_timing = { 2999 .pixelclock = { 67000000, 71000000, 75000000 }, 3000 .hactive = { 1280, 1280, 1280 }, 3001 .hfront_porch = { 2, 30, 30 }, 3002 .hback_porch = { 6, 100, 100 }, 3003 .hsync_len = { 2, 30, 30 }, 3004 .vactive = { 800, 800, 800 }, 3005 .vfront_porch = { 5, 5, 5 }, 3006 .vback_porch = { 11, 11, 11 }, 3007 .vsync_len = { 7, 7, 7 }, 3008 }; 3009 3010 static const struct panel_desc nec_nl12880bc20_05 = { 3011 .timings = &nec_nl12880bc20_05_timing, 3012 .num_timings = 1, 3013 .bpc = 8, 3014 .size = { 3015 .width = 261, 3016 .height = 163, 3017 }, 3018 .delay = { 3019 .enable = 50, 3020 .disable = 50, 3021 }, 3022 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3023 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3024 }; 3025 3026 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3027 .clock = 10870, 3028 .hdisplay = 480, 3029 .hsync_start = 480 + 2, 3030 .hsync_end = 480 + 2 + 41, 3031 .htotal = 480 + 2 + 41 + 2, 3032 .vdisplay = 272, 3033 .vsync_start = 272 + 2, 3034 .vsync_end = 272 + 2 + 4, 3035 .vtotal = 272 + 2 + 4 + 2, 3036 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3037 }; 3038 3039 static const struct panel_desc nec_nl4827hc19_05b = { 3040 .modes = &nec_nl4827hc19_05b_mode, 3041 .num_modes = 1, 3042 .bpc = 8, 3043 .size = { 3044 .width = 95, 3045 .height = 54, 3046 }, 3047 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3048 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3049 }; 3050 3051 static const struct drm_display_mode netron_dy_e231732_mode = { 3052 .clock = 66000, 3053 .hdisplay = 1024, 3054 .hsync_start = 1024 + 160, 3055 .hsync_end = 1024 + 160 + 70, 3056 .htotal = 1024 + 160 + 70 + 90, 3057 .vdisplay = 600, 3058 .vsync_start = 600 + 127, 3059 .vsync_end = 600 + 127 + 20, 3060 .vtotal = 600 + 127 + 20 + 3, 3061 }; 3062 3063 static const struct panel_desc netron_dy_e231732 = { 3064 .modes = &netron_dy_e231732_mode, 3065 .num_modes = 1, 3066 .size = { 3067 .width = 154, 3068 .height = 87, 3069 }, 3070 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3071 }; 3072 3073 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3074 .clock = 9000, 3075 .hdisplay = 480, 3076 .hsync_start = 480 + 2, 3077 .hsync_end = 480 + 2 + 41, 3078 .htotal = 480 + 2 + 41 + 2, 3079 .vdisplay = 272, 3080 .vsync_start = 272 + 2, 3081 .vsync_end = 272 + 2 + 10, 3082 .vtotal = 272 + 2 + 10 + 2, 3083 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3084 }; 3085 3086 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3087 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3088 .num_modes = 1, 3089 .bpc = 8, 3090 .size = { 3091 .width = 95, 3092 .height = 54, 3093 }, 3094 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3095 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3096 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3097 .connector_type = DRM_MODE_CONNECTOR_DPI, 3098 }; 3099 3100 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3101 .pixelclock = { 130000000, 148350000, 163000000 }, 3102 .hactive = { 1920, 1920, 1920 }, 3103 .hfront_porch = { 80, 100, 100 }, 3104 .hback_porch = { 100, 120, 120 }, 3105 .hsync_len = { 50, 60, 60 }, 3106 .vactive = { 1080, 1080, 1080 }, 3107 .vfront_porch = { 12, 30, 30 }, 3108 .vback_porch = { 4, 10, 10 }, 3109 .vsync_len = { 4, 5, 5 }, 3110 }; 3111 3112 static const struct panel_desc nlt_nl192108ac18_02d = { 3113 .timings = &nlt_nl192108ac18_02d_timing, 3114 .num_timings = 1, 3115 .bpc = 8, 3116 .size = { 3117 .width = 344, 3118 .height = 194, 3119 }, 3120 .delay = { 3121 .unprepare = 500, 3122 }, 3123 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3124 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3125 }; 3126 3127 static const struct drm_display_mode nvd_9128_mode = { 3128 .clock = 29500, 3129 .hdisplay = 800, 3130 .hsync_start = 800 + 130, 3131 .hsync_end = 800 + 130 + 98, 3132 .htotal = 800 + 0 + 130 + 98, 3133 .vdisplay = 480, 3134 .vsync_start = 480 + 10, 3135 .vsync_end = 480 + 10 + 50, 3136 .vtotal = 480 + 0 + 10 + 50, 3137 }; 3138 3139 static const struct panel_desc nvd_9128 = { 3140 .modes = &nvd_9128_mode, 3141 .num_modes = 1, 3142 .bpc = 8, 3143 .size = { 3144 .width = 156, 3145 .height = 88, 3146 }, 3147 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3148 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3149 }; 3150 3151 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3152 .pixelclock = { 30000000, 30000000, 40000000 }, 3153 .hactive = { 800, 800, 800 }, 3154 .hfront_porch = { 40, 40, 40 }, 3155 .hback_porch = { 40, 40, 40 }, 3156 .hsync_len = { 1, 48, 48 }, 3157 .vactive = { 480, 480, 480 }, 3158 .vfront_porch = { 13, 13, 13 }, 3159 .vback_porch = { 29, 29, 29 }, 3160 .vsync_len = { 3, 3, 3 }, 3161 .flags = DISPLAY_FLAGS_DE_HIGH, 3162 }; 3163 3164 static const struct panel_desc okaya_rs800480t_7x0gp = { 3165 .timings = &okaya_rs800480t_7x0gp_timing, 3166 .num_timings = 1, 3167 .bpc = 6, 3168 .size = { 3169 .width = 154, 3170 .height = 87, 3171 }, 3172 .delay = { 3173 .prepare = 41, 3174 .enable = 50, 3175 .unprepare = 41, 3176 .disable = 50, 3177 }, 3178 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3179 }; 3180 3181 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3182 .clock = 9000, 3183 .hdisplay = 480, 3184 .hsync_start = 480 + 5, 3185 .hsync_end = 480 + 5 + 30, 3186 .htotal = 480 + 5 + 30 + 10, 3187 .vdisplay = 272, 3188 .vsync_start = 272 + 8, 3189 .vsync_end = 272 + 8 + 5, 3190 .vtotal = 272 + 8 + 5 + 3, 3191 }; 3192 3193 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3194 .modes = &olimex_lcd_olinuxino_43ts_mode, 3195 .num_modes = 1, 3196 .size = { 3197 .width = 95, 3198 .height = 54, 3199 }, 3200 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3201 }; 3202 3203 /* 3204 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3205 * pixel clocks, but this is the timing that was being used in the Adafruit 3206 * installation instructions. 3207 */ 3208 static const struct drm_display_mode ontat_yx700wv03_mode = { 3209 .clock = 29500, 3210 .hdisplay = 800, 3211 .hsync_start = 824, 3212 .hsync_end = 896, 3213 .htotal = 992, 3214 .vdisplay = 480, 3215 .vsync_start = 483, 3216 .vsync_end = 493, 3217 .vtotal = 500, 3218 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3219 }; 3220 3221 /* 3222 * Specification at: 3223 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3224 */ 3225 static const struct panel_desc ontat_yx700wv03 = { 3226 .modes = &ontat_yx700wv03_mode, 3227 .num_modes = 1, 3228 .bpc = 8, 3229 .size = { 3230 .width = 154, 3231 .height = 83, 3232 }, 3233 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3234 }; 3235 3236 static const struct drm_display_mode ortustech_com37h3m_mode = { 3237 .clock = 22230, 3238 .hdisplay = 480, 3239 .hsync_start = 480 + 40, 3240 .hsync_end = 480 + 40 + 10, 3241 .htotal = 480 + 40 + 10 + 40, 3242 .vdisplay = 640, 3243 .vsync_start = 640 + 4, 3244 .vsync_end = 640 + 4 + 2, 3245 .vtotal = 640 + 4 + 2 + 4, 3246 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3247 }; 3248 3249 static const struct panel_desc ortustech_com37h3m = { 3250 .modes = &ortustech_com37h3m_mode, 3251 .num_modes = 1, 3252 .bpc = 8, 3253 .size = { 3254 .width = 56, /* 56.16mm */ 3255 .height = 75, /* 74.88mm */ 3256 }, 3257 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3258 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3259 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3260 }; 3261 3262 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3263 .clock = 25000, 3264 .hdisplay = 480, 3265 .hsync_start = 480 + 10, 3266 .hsync_end = 480 + 10 + 10, 3267 .htotal = 480 + 10 + 10 + 15, 3268 .vdisplay = 800, 3269 .vsync_start = 800 + 3, 3270 .vsync_end = 800 + 3 + 3, 3271 .vtotal = 800 + 3 + 3 + 3, 3272 }; 3273 3274 static const struct panel_desc ortustech_com43h4m85ulc = { 3275 .modes = &ortustech_com43h4m85ulc_mode, 3276 .num_modes = 1, 3277 .bpc = 6, 3278 .size = { 3279 .width = 56, 3280 .height = 93, 3281 }, 3282 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3283 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3284 .connector_type = DRM_MODE_CONNECTOR_DPI, 3285 }; 3286 3287 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3288 .clock = 33000, 3289 .hdisplay = 800, 3290 .hsync_start = 800 + 210, 3291 .hsync_end = 800 + 210 + 30, 3292 .htotal = 800 + 210 + 30 + 16, 3293 .vdisplay = 480, 3294 .vsync_start = 480 + 22, 3295 .vsync_end = 480 + 22 + 13, 3296 .vtotal = 480 + 22 + 13 + 10, 3297 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3298 }; 3299 3300 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3301 .modes = &osddisplays_osd070t1718_19ts_mode, 3302 .num_modes = 1, 3303 .bpc = 8, 3304 .size = { 3305 .width = 152, 3306 .height = 91, 3307 }, 3308 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3309 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3310 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3311 .connector_type = DRM_MODE_CONNECTOR_DPI, 3312 }; 3313 3314 static const struct drm_display_mode pda_91_00156_a0_mode = { 3315 .clock = 33300, 3316 .hdisplay = 800, 3317 .hsync_start = 800 + 1, 3318 .hsync_end = 800 + 1 + 64, 3319 .htotal = 800 + 1 + 64 + 64, 3320 .vdisplay = 480, 3321 .vsync_start = 480 + 1, 3322 .vsync_end = 480 + 1 + 23, 3323 .vtotal = 480 + 1 + 23 + 22, 3324 }; 3325 3326 static const struct panel_desc pda_91_00156_a0 = { 3327 .modes = &pda_91_00156_a0_mode, 3328 .num_modes = 1, 3329 .size = { 3330 .width = 152, 3331 .height = 91, 3332 }, 3333 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3334 }; 3335 3336 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3337 .clock = 24750, 3338 .hdisplay = 800, 3339 .hsync_start = 800 + 54, 3340 .hsync_end = 800 + 54 + 2, 3341 .htotal = 800 + 54 + 2 + 44, 3342 .vdisplay = 480, 3343 .vsync_start = 480 + 49, 3344 .vsync_end = 480 + 49 + 2, 3345 .vtotal = 480 + 49 + 2 + 22, 3346 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3347 }; 3348 3349 static const struct panel_desc powertip_ph800480t013_idf02 = { 3350 .modes = &powertip_ph800480t013_idf02_mode, 3351 .num_modes = 1, 3352 .bpc = 8, 3353 .size = { 3354 .width = 152, 3355 .height = 91, 3356 }, 3357 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3358 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3359 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3360 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3361 .connector_type = DRM_MODE_CONNECTOR_DPI, 3362 }; 3363 3364 static const struct drm_display_mode qd43003c0_40_mode = { 3365 .clock = 9000, 3366 .hdisplay = 480, 3367 .hsync_start = 480 + 8, 3368 .hsync_end = 480 + 8 + 4, 3369 .htotal = 480 + 8 + 4 + 39, 3370 .vdisplay = 272, 3371 .vsync_start = 272 + 4, 3372 .vsync_end = 272 + 4 + 10, 3373 .vtotal = 272 + 4 + 10 + 2, 3374 }; 3375 3376 static const struct panel_desc qd43003c0_40 = { 3377 .modes = &qd43003c0_40_mode, 3378 .num_modes = 1, 3379 .bpc = 8, 3380 .size = { 3381 .width = 95, 3382 .height = 53, 3383 }, 3384 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3385 }; 3386 3387 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3388 { /* 60 Hz */ 3389 .clock = 10800, 3390 .hdisplay = 480, 3391 .hsync_start = 480 + 77, 3392 .hsync_end = 480 + 77 + 41, 3393 .htotal = 480 + 77 + 41 + 2, 3394 .vdisplay = 272, 3395 .vsync_start = 272 + 16, 3396 .vsync_end = 272 + 16 + 10, 3397 .vtotal = 272 + 16 + 10 + 2, 3398 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3399 }, 3400 { /* 50 Hz */ 3401 .clock = 10800, 3402 .hdisplay = 480, 3403 .hsync_start = 480 + 17, 3404 .hsync_end = 480 + 17 + 41, 3405 .htotal = 480 + 17 + 41 + 2, 3406 .vdisplay = 272, 3407 .vsync_start = 272 + 116, 3408 .vsync_end = 272 + 116 + 10, 3409 .vtotal = 272 + 116 + 10 + 2, 3410 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3411 }, 3412 }; 3413 3414 static const struct panel_desc qishenglong_gopher2b_lcd = { 3415 .modes = qishenglong_gopher2b_lcd_modes, 3416 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3417 .bpc = 8, 3418 .size = { 3419 .width = 95, 3420 .height = 54, 3421 }, 3422 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3423 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3424 .connector_type = DRM_MODE_CONNECTOR_DPI, 3425 }; 3426 3427 static const struct display_timing rocktech_rk043fn48h_timing = { 3428 .pixelclock = { 6000000, 9000000, 12000000 }, 3429 .hactive = { 480, 480, 480 }, 3430 .hback_porch = { 8, 43, 43 }, 3431 .hfront_porch = { 2, 8, 8 }, 3432 .hsync_len = { 1, 1, 1 }, 3433 .vactive = { 272, 272, 272 }, 3434 .vback_porch = { 2, 12, 12 }, 3435 .vfront_porch = { 1, 4, 4 }, 3436 .vsync_len = { 1, 10, 10 }, 3437 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3438 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3439 }; 3440 3441 static const struct panel_desc rocktech_rk043fn48h = { 3442 .timings = &rocktech_rk043fn48h_timing, 3443 .num_timings = 1, 3444 .bpc = 8, 3445 .size = { 3446 .width = 95, 3447 .height = 54, 3448 }, 3449 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3450 .connector_type = DRM_MODE_CONNECTOR_DPI, 3451 }; 3452 3453 static const struct display_timing rocktech_rk070er9427_timing = { 3454 .pixelclock = { 26400000, 33300000, 46800000 }, 3455 .hactive = { 800, 800, 800 }, 3456 .hfront_porch = { 16, 210, 354 }, 3457 .hback_porch = { 46, 46, 46 }, 3458 .hsync_len = { 1, 1, 1 }, 3459 .vactive = { 480, 480, 480 }, 3460 .vfront_porch = { 7, 22, 147 }, 3461 .vback_porch = { 23, 23, 23 }, 3462 .vsync_len = { 1, 1, 1 }, 3463 .flags = DISPLAY_FLAGS_DE_HIGH, 3464 }; 3465 3466 static const struct panel_desc rocktech_rk070er9427 = { 3467 .timings = &rocktech_rk070er9427_timing, 3468 .num_timings = 1, 3469 .bpc = 6, 3470 .size = { 3471 .width = 154, 3472 .height = 86, 3473 }, 3474 .delay = { 3475 .prepare = 41, 3476 .enable = 50, 3477 .unprepare = 41, 3478 .disable = 50, 3479 }, 3480 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3481 }; 3482 3483 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3484 .clock = 71100, 3485 .hdisplay = 1280, 3486 .hsync_start = 1280 + 48, 3487 .hsync_end = 1280 + 48 + 32, 3488 .htotal = 1280 + 48 + 32 + 80, 3489 .vdisplay = 800, 3490 .vsync_start = 800 + 2, 3491 .vsync_end = 800 + 2 + 5, 3492 .vtotal = 800 + 2 + 5 + 16, 3493 }; 3494 3495 static const struct panel_desc rocktech_rk101ii01d_ct = { 3496 .modes = &rocktech_rk101ii01d_ct_mode, 3497 .bpc = 8, 3498 .num_modes = 1, 3499 .size = { 3500 .width = 217, 3501 .height = 136, 3502 }, 3503 .delay = { 3504 .prepare = 50, 3505 .disable = 50, 3506 }, 3507 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3508 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3509 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3510 }; 3511 3512 static const struct display_timing samsung_ltl101al01_timing = { 3513 .pixelclock = { 66663000, 66663000, 66663000 }, 3514 .hactive = { 1280, 1280, 1280 }, 3515 .hfront_porch = { 18, 18, 18 }, 3516 .hback_porch = { 36, 36, 36 }, 3517 .hsync_len = { 16, 16, 16 }, 3518 .vactive = { 800, 800, 800 }, 3519 .vfront_porch = { 4, 4, 4 }, 3520 .vback_porch = { 16, 16, 16 }, 3521 .vsync_len = { 3, 3, 3 }, 3522 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3523 }; 3524 3525 static const struct panel_desc samsung_ltl101al01 = { 3526 .timings = &samsung_ltl101al01_timing, 3527 .num_timings = 1, 3528 .bpc = 8, 3529 .size = { 3530 .width = 217, 3531 .height = 135, 3532 }, 3533 .delay = { 3534 .prepare = 40, 3535 .enable = 300, 3536 .disable = 200, 3537 .unprepare = 600, 3538 }, 3539 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3540 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3541 }; 3542 3543 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3544 .clock = 54030, 3545 .hdisplay = 1024, 3546 .hsync_start = 1024 + 24, 3547 .hsync_end = 1024 + 24 + 136, 3548 .htotal = 1024 + 24 + 136 + 160, 3549 .vdisplay = 600, 3550 .vsync_start = 600 + 3, 3551 .vsync_end = 600 + 3 + 6, 3552 .vtotal = 600 + 3 + 6 + 61, 3553 }; 3554 3555 static const struct panel_desc samsung_ltn101nt05 = { 3556 .modes = &samsung_ltn101nt05_mode, 3557 .num_modes = 1, 3558 .bpc = 6, 3559 .size = { 3560 .width = 223, 3561 .height = 125, 3562 }, 3563 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3564 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3565 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3566 }; 3567 3568 static const struct display_timing satoz_sat050at40h12r2_timing = { 3569 .pixelclock = {33300000, 33300000, 50000000}, 3570 .hactive = {800, 800, 800}, 3571 .hfront_porch = {16, 210, 354}, 3572 .hback_porch = {46, 46, 46}, 3573 .hsync_len = {1, 1, 40}, 3574 .vactive = {480, 480, 480}, 3575 .vfront_porch = {7, 22, 147}, 3576 .vback_porch = {23, 23, 23}, 3577 .vsync_len = {1, 1, 20}, 3578 }; 3579 3580 static const struct panel_desc satoz_sat050at40h12r2 = { 3581 .timings = &satoz_sat050at40h12r2_timing, 3582 .num_timings = 1, 3583 .bpc = 8, 3584 .size = { 3585 .width = 108, 3586 .height = 65, 3587 }, 3588 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3589 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3590 }; 3591 3592 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3593 .clock = 33260, 3594 .hdisplay = 800, 3595 .hsync_start = 800 + 64, 3596 .hsync_end = 800 + 64 + 128, 3597 .htotal = 800 + 64 + 128 + 64, 3598 .vdisplay = 480, 3599 .vsync_start = 480 + 8, 3600 .vsync_end = 480 + 8 + 2, 3601 .vtotal = 480 + 8 + 2 + 35, 3602 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3603 }; 3604 3605 static const struct panel_desc sharp_lq070y3dg3b = { 3606 .modes = &sharp_lq070y3dg3b_mode, 3607 .num_modes = 1, 3608 .bpc = 8, 3609 .size = { 3610 .width = 152, /* 152.4mm */ 3611 .height = 91, /* 91.4mm */ 3612 }, 3613 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3614 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3615 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3616 }; 3617 3618 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3619 .clock = 5500, 3620 .hdisplay = 240, 3621 .hsync_start = 240 + 16, 3622 .hsync_end = 240 + 16 + 7, 3623 .htotal = 240 + 16 + 7 + 5, 3624 .vdisplay = 320, 3625 .vsync_start = 320 + 9, 3626 .vsync_end = 320 + 9 + 1, 3627 .vtotal = 320 + 9 + 1 + 7, 3628 }; 3629 3630 static const struct panel_desc sharp_lq035q7db03 = { 3631 .modes = &sharp_lq035q7db03_mode, 3632 .num_modes = 1, 3633 .bpc = 6, 3634 .size = { 3635 .width = 54, 3636 .height = 72, 3637 }, 3638 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3639 }; 3640 3641 static const struct display_timing sharp_lq101k1ly04_timing = { 3642 .pixelclock = { 60000000, 65000000, 80000000 }, 3643 .hactive = { 1280, 1280, 1280 }, 3644 .hfront_porch = { 20, 20, 20 }, 3645 .hback_porch = { 20, 20, 20 }, 3646 .hsync_len = { 10, 10, 10 }, 3647 .vactive = { 800, 800, 800 }, 3648 .vfront_porch = { 4, 4, 4 }, 3649 .vback_porch = { 4, 4, 4 }, 3650 .vsync_len = { 4, 4, 4 }, 3651 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3652 }; 3653 3654 static const struct panel_desc sharp_lq101k1ly04 = { 3655 .timings = &sharp_lq101k1ly04_timing, 3656 .num_timings = 1, 3657 .bpc = 8, 3658 .size = { 3659 .width = 217, 3660 .height = 136, 3661 }, 3662 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3663 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3664 }; 3665 3666 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3667 { /* 50 Hz */ 3668 .clock = 3000, 3669 .hdisplay = 240, 3670 .hsync_start = 240 + 58, 3671 .hsync_end = 240 + 58 + 1, 3672 .htotal = 240 + 58 + 1 + 1, 3673 .vdisplay = 160, 3674 .vsync_start = 160 + 24, 3675 .vsync_end = 160 + 24 + 10, 3676 .vtotal = 160 + 24 + 10 + 6, 3677 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3678 }, 3679 { /* 60 Hz */ 3680 .clock = 3000, 3681 .hdisplay = 240, 3682 .hsync_start = 240 + 8, 3683 .hsync_end = 240 + 8 + 1, 3684 .htotal = 240 + 8 + 1 + 1, 3685 .vdisplay = 160, 3686 .vsync_start = 160 + 24, 3687 .vsync_end = 160 + 24 + 10, 3688 .vtotal = 160 + 24 + 10 + 6, 3689 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3690 }, 3691 }; 3692 3693 static const struct panel_desc sharp_ls020b1dd01d = { 3694 .modes = sharp_ls020b1dd01d_modes, 3695 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3696 .bpc = 6, 3697 .size = { 3698 .width = 42, 3699 .height = 28, 3700 }, 3701 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3702 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3703 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3704 | DRM_BUS_FLAG_SHARP_SIGNALS, 3705 }; 3706 3707 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3708 .clock = 33300, 3709 .hdisplay = 800, 3710 .hsync_start = 800 + 1, 3711 .hsync_end = 800 + 1 + 64, 3712 .htotal = 800 + 1 + 64 + 64, 3713 .vdisplay = 480, 3714 .vsync_start = 480 + 1, 3715 .vsync_end = 480 + 1 + 23, 3716 .vtotal = 480 + 1 + 23 + 22, 3717 }; 3718 3719 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3720 .modes = &shelly_sca07010_bfn_lnn_mode, 3721 .num_modes = 1, 3722 .size = { 3723 .width = 152, 3724 .height = 91, 3725 }, 3726 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3727 }; 3728 3729 static const struct drm_display_mode starry_kr070pe2t_mode = { 3730 .clock = 33000, 3731 .hdisplay = 800, 3732 .hsync_start = 800 + 209, 3733 .hsync_end = 800 + 209 + 1, 3734 .htotal = 800 + 209 + 1 + 45, 3735 .vdisplay = 480, 3736 .vsync_start = 480 + 22, 3737 .vsync_end = 480 + 22 + 1, 3738 .vtotal = 480 + 22 + 1 + 22, 3739 }; 3740 3741 static const struct panel_desc starry_kr070pe2t = { 3742 .modes = &starry_kr070pe2t_mode, 3743 .num_modes = 1, 3744 .bpc = 8, 3745 .size = { 3746 .width = 152, 3747 .height = 86, 3748 }, 3749 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3750 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3751 .connector_type = DRM_MODE_CONNECTOR_DPI, 3752 }; 3753 3754 static const struct display_timing startek_kd070wvfpa_mode = { 3755 .pixelclock = { 25200000, 27200000, 30500000 }, 3756 .hactive = { 800, 800, 800 }, 3757 .hfront_porch = { 19, 44, 115 }, 3758 .hback_porch = { 5, 16, 101 }, 3759 .hsync_len = { 1, 2, 100 }, 3760 .vactive = { 480, 480, 480 }, 3761 .vfront_porch = { 5, 43, 67 }, 3762 .vback_porch = { 5, 5, 67 }, 3763 .vsync_len = { 1, 2, 66 }, 3764 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3765 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3766 DISPLAY_FLAGS_SYNC_POSEDGE, 3767 }; 3768 3769 static const struct panel_desc startek_kd070wvfpa = { 3770 .timings = &startek_kd070wvfpa_mode, 3771 .num_timings = 1, 3772 .bpc = 8, 3773 .size = { 3774 .width = 152, 3775 .height = 91, 3776 }, 3777 .delay = { 3778 .prepare = 20, 3779 .enable = 200, 3780 .disable = 200, 3781 }, 3782 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3783 .connector_type = DRM_MODE_CONNECTOR_DPI, 3784 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3785 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3786 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3787 }; 3788 3789 static const struct display_timing tsd_tst043015cmhx_timing = { 3790 .pixelclock = { 5000000, 9000000, 12000000 }, 3791 .hactive = { 480, 480, 480 }, 3792 .hfront_porch = { 4, 5, 65 }, 3793 .hback_porch = { 36, 40, 255 }, 3794 .hsync_len = { 1, 1, 1 }, 3795 .vactive = { 272, 272, 272 }, 3796 .vfront_porch = { 2, 8, 97 }, 3797 .vback_porch = { 3, 8, 31 }, 3798 .vsync_len = { 1, 1, 1 }, 3799 3800 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3801 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3802 }; 3803 3804 static const struct panel_desc tsd_tst043015cmhx = { 3805 .timings = &tsd_tst043015cmhx_timing, 3806 .num_timings = 1, 3807 .bpc = 8, 3808 .size = { 3809 .width = 105, 3810 .height = 67, 3811 }, 3812 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3813 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3814 }; 3815 3816 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3817 .clock = 30000, 3818 .hdisplay = 800, 3819 .hsync_start = 800 + 39, 3820 .hsync_end = 800 + 39 + 47, 3821 .htotal = 800 + 39 + 47 + 39, 3822 .vdisplay = 480, 3823 .vsync_start = 480 + 13, 3824 .vsync_end = 480 + 13 + 2, 3825 .vtotal = 480 + 13 + 2 + 29, 3826 }; 3827 3828 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3829 .modes = &tfc_s9700rtwv43tr_01b_mode, 3830 .num_modes = 1, 3831 .bpc = 8, 3832 .size = { 3833 .width = 155, 3834 .height = 90, 3835 }, 3836 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3837 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3838 }; 3839 3840 static const struct display_timing tianma_tm070jdhg30_timing = { 3841 .pixelclock = { 62600000, 68200000, 78100000 }, 3842 .hactive = { 1280, 1280, 1280 }, 3843 .hfront_porch = { 15, 64, 159 }, 3844 .hback_porch = { 5, 5, 5 }, 3845 .hsync_len = { 1, 1, 256 }, 3846 .vactive = { 800, 800, 800 }, 3847 .vfront_porch = { 3, 40, 99 }, 3848 .vback_porch = { 2, 2, 2 }, 3849 .vsync_len = { 1, 1, 128 }, 3850 .flags = DISPLAY_FLAGS_DE_HIGH, 3851 }; 3852 3853 static const struct panel_desc tianma_tm070jdhg30 = { 3854 .timings = &tianma_tm070jdhg30_timing, 3855 .num_timings = 1, 3856 .bpc = 8, 3857 .size = { 3858 .width = 151, 3859 .height = 95, 3860 }, 3861 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3862 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3863 }; 3864 3865 static const struct panel_desc tianma_tm070jvhg33 = { 3866 .timings = &tianma_tm070jdhg30_timing, 3867 .num_timings = 1, 3868 .bpc = 8, 3869 .size = { 3870 .width = 150, 3871 .height = 94, 3872 }, 3873 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3874 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3875 }; 3876 3877 static const struct display_timing tianma_tm070rvhg71_timing = { 3878 .pixelclock = { 27700000, 29200000, 39600000 }, 3879 .hactive = { 800, 800, 800 }, 3880 .hfront_porch = { 12, 40, 212 }, 3881 .hback_porch = { 88, 88, 88 }, 3882 .hsync_len = { 1, 1, 40 }, 3883 .vactive = { 480, 480, 480 }, 3884 .vfront_porch = { 1, 13, 88 }, 3885 .vback_porch = { 32, 32, 32 }, 3886 .vsync_len = { 1, 1, 3 }, 3887 .flags = DISPLAY_FLAGS_DE_HIGH, 3888 }; 3889 3890 static const struct panel_desc tianma_tm070rvhg71 = { 3891 .timings = &tianma_tm070rvhg71_timing, 3892 .num_timings = 1, 3893 .bpc = 8, 3894 .size = { 3895 .width = 154, 3896 .height = 86, 3897 }, 3898 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3899 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3900 }; 3901 3902 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3903 { 3904 .clock = 10000, 3905 .hdisplay = 320, 3906 .hsync_start = 320 + 50, 3907 .hsync_end = 320 + 50 + 6, 3908 .htotal = 320 + 50 + 6 + 38, 3909 .vdisplay = 240, 3910 .vsync_start = 240 + 3, 3911 .vsync_end = 240 + 3 + 1, 3912 .vtotal = 240 + 3 + 1 + 17, 3913 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3914 }, 3915 }; 3916 3917 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3918 .modes = ti_nspire_cx_lcd_mode, 3919 .num_modes = 1, 3920 .bpc = 8, 3921 .size = { 3922 .width = 65, 3923 .height = 49, 3924 }, 3925 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3926 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3927 }; 3928 3929 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3930 { 3931 .clock = 10000, 3932 .hdisplay = 320, 3933 .hsync_start = 320 + 6, 3934 .hsync_end = 320 + 6 + 6, 3935 .htotal = 320 + 6 + 6 + 6, 3936 .vdisplay = 240, 3937 .vsync_start = 240 + 0, 3938 .vsync_end = 240 + 0 + 1, 3939 .vtotal = 240 + 0 + 1 + 0, 3940 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3941 }, 3942 }; 3943 3944 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3945 .modes = ti_nspire_classic_lcd_mode, 3946 .num_modes = 1, 3947 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3948 .bpc = 8, 3949 .size = { 3950 .width = 71, 3951 .height = 53, 3952 }, 3953 /* This is the grayscale bus format */ 3954 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3955 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3956 }; 3957 3958 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3959 .clock = 79500, 3960 .hdisplay = 1280, 3961 .hsync_start = 1280 + 192, 3962 .hsync_end = 1280 + 192 + 128, 3963 .htotal = 1280 + 192 + 128 + 64, 3964 .vdisplay = 768, 3965 .vsync_start = 768 + 20, 3966 .vsync_end = 768 + 20 + 7, 3967 .vtotal = 768 + 20 + 7 + 3, 3968 }; 3969 3970 static const struct panel_desc toshiba_lt089ac29000 = { 3971 .modes = &toshiba_lt089ac29000_mode, 3972 .num_modes = 1, 3973 .size = { 3974 .width = 194, 3975 .height = 116, 3976 }, 3977 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3978 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3979 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3980 }; 3981 3982 static const struct drm_display_mode tpk_f07a_0102_mode = { 3983 .clock = 33260, 3984 .hdisplay = 800, 3985 .hsync_start = 800 + 40, 3986 .hsync_end = 800 + 40 + 128, 3987 .htotal = 800 + 40 + 128 + 88, 3988 .vdisplay = 480, 3989 .vsync_start = 480 + 10, 3990 .vsync_end = 480 + 10 + 2, 3991 .vtotal = 480 + 10 + 2 + 33, 3992 }; 3993 3994 static const struct panel_desc tpk_f07a_0102 = { 3995 .modes = &tpk_f07a_0102_mode, 3996 .num_modes = 1, 3997 .size = { 3998 .width = 152, 3999 .height = 91, 4000 }, 4001 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4002 }; 4003 4004 static const struct drm_display_mode tpk_f10a_0102_mode = { 4005 .clock = 45000, 4006 .hdisplay = 1024, 4007 .hsync_start = 1024 + 176, 4008 .hsync_end = 1024 + 176 + 5, 4009 .htotal = 1024 + 176 + 5 + 88, 4010 .vdisplay = 600, 4011 .vsync_start = 600 + 20, 4012 .vsync_end = 600 + 20 + 5, 4013 .vtotal = 600 + 20 + 5 + 25, 4014 }; 4015 4016 static const struct panel_desc tpk_f10a_0102 = { 4017 .modes = &tpk_f10a_0102_mode, 4018 .num_modes = 1, 4019 .size = { 4020 .width = 223, 4021 .height = 125, 4022 }, 4023 }; 4024 4025 static const struct display_timing urt_umsh_8596md_timing = { 4026 .pixelclock = { 33260000, 33260000, 33260000 }, 4027 .hactive = { 800, 800, 800 }, 4028 .hfront_porch = { 41, 41, 41 }, 4029 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4030 .hsync_len = { 71, 128, 128 }, 4031 .vactive = { 480, 480, 480 }, 4032 .vfront_porch = { 10, 10, 10 }, 4033 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4034 .vsync_len = { 2, 2, 2 }, 4035 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4036 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4037 }; 4038 4039 static const struct panel_desc urt_umsh_8596md_lvds = { 4040 .timings = &urt_umsh_8596md_timing, 4041 .num_timings = 1, 4042 .bpc = 6, 4043 .size = { 4044 .width = 152, 4045 .height = 91, 4046 }, 4047 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4048 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4049 }; 4050 4051 static const struct panel_desc urt_umsh_8596md_parallel = { 4052 .timings = &urt_umsh_8596md_timing, 4053 .num_timings = 1, 4054 .bpc = 6, 4055 .size = { 4056 .width = 152, 4057 .height = 91, 4058 }, 4059 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4060 }; 4061 4062 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4063 .clock = 60000, 4064 .hdisplay = 1024, 4065 .hsync_start = 1024 + 160, 4066 .hsync_end = 1024 + 160 + 100, 4067 .htotal = 1024 + 160 + 100 + 60, 4068 .vdisplay = 600, 4069 .vsync_start = 600 + 12, 4070 .vsync_end = 600 + 12 + 10, 4071 .vtotal = 600 + 12 + 10 + 13, 4072 }; 4073 4074 static const struct panel_desc vivax_tpc9150_panel = { 4075 .modes = &vivax_tpc9150_panel_mode, 4076 .num_modes = 1, 4077 .bpc = 6, 4078 .size = { 4079 .width = 200, 4080 .height = 115, 4081 }, 4082 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4083 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4084 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4085 }; 4086 4087 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4088 .clock = 33333, 4089 .hdisplay = 800, 4090 .hsync_start = 800 + 210, 4091 .hsync_end = 800 + 210 + 20, 4092 .htotal = 800 + 210 + 20 + 46, 4093 .vdisplay = 480, 4094 .vsync_start = 480 + 22, 4095 .vsync_end = 480 + 22 + 10, 4096 .vtotal = 480 + 22 + 10 + 23, 4097 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4098 }; 4099 4100 static const struct panel_desc vl050_8048nt_c01 = { 4101 .modes = &vl050_8048nt_c01_mode, 4102 .num_modes = 1, 4103 .bpc = 8, 4104 .size = { 4105 .width = 120, 4106 .height = 76, 4107 }, 4108 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4109 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4110 }; 4111 4112 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4113 .clock = 6410, 4114 .hdisplay = 320, 4115 .hsync_start = 320 + 20, 4116 .hsync_end = 320 + 20 + 30, 4117 .htotal = 320 + 20 + 30 + 38, 4118 .vdisplay = 240, 4119 .vsync_start = 240 + 4, 4120 .vsync_end = 240 + 4 + 3, 4121 .vtotal = 240 + 4 + 3 + 15, 4122 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4123 }; 4124 4125 static const struct panel_desc winstar_wf35ltiacd = { 4126 .modes = &winstar_wf35ltiacd_mode, 4127 .num_modes = 1, 4128 .bpc = 8, 4129 .size = { 4130 .width = 70, 4131 .height = 53, 4132 }, 4133 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4134 }; 4135 4136 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4137 .clock = 51200, 4138 .hdisplay = 1024, 4139 .hsync_start = 1024 + 100, 4140 .hsync_end = 1024 + 100 + 100, 4141 .htotal = 1024 + 100 + 100 + 120, 4142 .vdisplay = 600, 4143 .vsync_start = 600 + 10, 4144 .vsync_end = 600 + 10 + 10, 4145 .vtotal = 600 + 10 + 10 + 15, 4146 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4147 }; 4148 4149 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4150 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4151 .num_modes = 1, 4152 .bpc = 8, 4153 .size = { 4154 .width = 154, 4155 .height = 90, 4156 }, 4157 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4158 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4159 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4160 }; 4161 4162 static const struct drm_display_mode arm_rtsm_mode[] = { 4163 { 4164 .clock = 65000, 4165 .hdisplay = 1024, 4166 .hsync_start = 1024 + 24, 4167 .hsync_end = 1024 + 24 + 136, 4168 .htotal = 1024 + 24 + 136 + 160, 4169 .vdisplay = 768, 4170 .vsync_start = 768 + 3, 4171 .vsync_end = 768 + 3 + 6, 4172 .vtotal = 768 + 3 + 6 + 29, 4173 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4174 }, 4175 }; 4176 4177 static const struct panel_desc arm_rtsm = { 4178 .modes = arm_rtsm_mode, 4179 .num_modes = 1, 4180 .bpc = 8, 4181 .size = { 4182 .width = 400, 4183 .height = 300, 4184 }, 4185 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4186 }; 4187 4188 static const struct of_device_id platform_of_match[] = { 4189 { 4190 .compatible = "ampire,am-1280800n3tzqw-t00h", 4191 .data = &ire_am_1280800n3tzqw_t00h, 4192 }, { 4193 .compatible = "ampire,am-480272h3tmqw-t01h", 4194 .data = &ire_am_480272h3tmqw_t01h, 4195 }, { 4196 .compatible = "ampire,am-800480l1tmqw-t00h", 4197 .data = &ire_am_800480l1tmqw_t00h, 4198 }, { 4199 .compatible = "ampire,am800480r3tmqwa1h", 4200 .data = &ire_am800480r3tmqwa1h, 4201 }, { 4202 .compatible = "ampire,am800600p5tmqw-tb8h", 4203 .data = &ire_am800600p5tmqwtb8h, 4204 }, { 4205 .compatible = "arm,rtsm-display", 4206 .data = &arm_rtsm, 4207 }, { 4208 .compatible = "armadeus,st0700-adapt", 4209 .data = &armadeus_st0700_adapt, 4210 }, { 4211 .compatible = "auo,b101aw03", 4212 .data = &auo_b101aw03, 4213 }, { 4214 .compatible = "auo,b101xtn01", 4215 .data = &auo_b101xtn01, 4216 }, { 4217 .compatible = "auo,b116xw03", 4218 .data = &auo_b116xw03, 4219 }, { 4220 .compatible = "auo,g070vvn01", 4221 .data = &auo_g070vvn01, 4222 }, { 4223 .compatible = "auo,g101evn010", 4224 .data = &auo_g101evn010, 4225 }, { 4226 .compatible = "auo,g104sn02", 4227 .data = &auo_g104sn02, 4228 }, { 4229 .compatible = "auo,g121ean01", 4230 .data = &auo_g121ean01, 4231 }, { 4232 .compatible = "auo,g133han01", 4233 .data = &auo_g133han01, 4234 }, { 4235 .compatible = "auo,g156xtn01", 4236 .data = &auo_g156xtn01, 4237 }, { 4238 .compatible = "auo,g185han01", 4239 .data = &auo_g185han01, 4240 }, { 4241 .compatible = "auo,g190ean01", 4242 .data = &auo_g190ean01, 4243 }, { 4244 .compatible = "auo,p320hvn03", 4245 .data = &auo_p320hvn03, 4246 }, { 4247 .compatible = "auo,t215hvn01", 4248 .data = &auo_t215hvn01, 4249 }, { 4250 .compatible = "avic,tm070ddh03", 4251 .data = &avic_tm070ddh03, 4252 }, { 4253 .compatible = "bananapi,s070wv20-ct16", 4254 .data = &bananapi_s070wv20_ct16, 4255 }, { 4256 .compatible = "boe,ev121wxm-n10-1850", 4257 .data = &boe_ev121wxm_n10_1850, 4258 }, { 4259 .compatible = "boe,hv070wsa-100", 4260 .data = &boe_hv070wsa 4261 }, { 4262 .compatible = "cdtech,s043wq26h-ct7", 4263 .data = &cdtech_s043wq26h_ct7, 4264 }, { 4265 .compatible = "cdtech,s070pws19hp-fc21", 4266 .data = &cdtech_s070pws19hp_fc21, 4267 }, { 4268 .compatible = "cdtech,s070swv29hg-dc44", 4269 .data = &cdtech_s070swv29hg_dc44, 4270 }, { 4271 .compatible = "cdtech,s070wv95-ct16", 4272 .data = &cdtech_s070wv95_ct16, 4273 }, { 4274 .compatible = "chefree,ch101olhlwh-002", 4275 .data = &chefree_ch101olhlwh_002, 4276 }, { 4277 .compatible = "chunghwa,claa070wp03xg", 4278 .data = &chunghwa_claa070wp03xg, 4279 }, { 4280 .compatible = "chunghwa,claa101wa01a", 4281 .data = &chunghwa_claa101wa01a 4282 }, { 4283 .compatible = "chunghwa,claa101wb01", 4284 .data = &chunghwa_claa101wb01 4285 }, { 4286 .compatible = "dataimage,fg040346dsswbg04", 4287 .data = &dataimage_fg040346dsswbg04, 4288 }, { 4289 .compatible = "dataimage,fg1001l0dsswmg01", 4290 .data = &dataimage_fg1001l0dsswmg01, 4291 }, { 4292 .compatible = "dataimage,scf0700c48ggu18", 4293 .data = &dataimage_scf0700c48ggu18, 4294 }, { 4295 .compatible = "dlc,dlc0700yzg-1", 4296 .data = &dlc_dlc0700yzg_1, 4297 }, { 4298 .compatible = "dlc,dlc1010gig", 4299 .data = &dlc_dlc1010gig, 4300 }, { 4301 .compatible = "edt,et035012dm6", 4302 .data = &edt_et035012dm6, 4303 }, { 4304 .compatible = "edt,etm0350g0dh6", 4305 .data = &edt_etm0350g0dh6, 4306 }, { 4307 .compatible = "edt,etm043080dh6gp", 4308 .data = &edt_etm043080dh6gp, 4309 }, { 4310 .compatible = "edt,etm0430g0dh6", 4311 .data = &edt_etm0430g0dh6, 4312 }, { 4313 .compatible = "edt,et057090dhu", 4314 .data = &edt_et057090dhu, 4315 }, { 4316 .compatible = "edt,et070080dh6", 4317 .data = &edt_etm0700g0dh6, 4318 }, { 4319 .compatible = "edt,etm0700g0dh6", 4320 .data = &edt_etm0700g0dh6, 4321 }, { 4322 .compatible = "edt,etm0700g0bdh6", 4323 .data = &edt_etm0700g0bdh6, 4324 }, { 4325 .compatible = "edt,etm0700g0edh6", 4326 .data = &edt_etm0700g0bdh6, 4327 }, { 4328 .compatible = "edt,etml0700y5dha", 4329 .data = &edt_etml0700y5dha, 4330 }, { 4331 .compatible = "edt,etmv570g2dhu", 4332 .data = &edt_etmv570g2dhu, 4333 }, { 4334 .compatible = "eink,vb3300-kca", 4335 .data = &eink_vb3300_kca, 4336 }, { 4337 .compatible = "evervision,vgg804821", 4338 .data = &evervision_vgg804821, 4339 }, { 4340 .compatible = "foxlink,fl500wvr00-a0t", 4341 .data = &foxlink_fl500wvr00_a0t, 4342 }, { 4343 .compatible = "frida,frd350h54004", 4344 .data = &frida_frd350h54004, 4345 }, { 4346 .compatible = "friendlyarm,hd702e", 4347 .data = &friendlyarm_hd702e, 4348 }, { 4349 .compatible = "giantplus,gpg482739qs5", 4350 .data = &giantplus_gpg482739qs5 4351 }, { 4352 .compatible = "giantplus,gpm940b0", 4353 .data = &giantplus_gpm940b0, 4354 }, { 4355 .compatible = "hannstar,hsd070pww1", 4356 .data = &hannstar_hsd070pww1, 4357 }, { 4358 .compatible = "hannstar,hsd100pxn1", 4359 .data = &hannstar_hsd100pxn1, 4360 }, { 4361 .compatible = "hannstar,hsd101pww2", 4362 .data = &hannstar_hsd101pww2, 4363 }, { 4364 .compatible = "hit,tx23d38vm0caa", 4365 .data = &hitachi_tx23d38vm0caa 4366 }, { 4367 .compatible = "innolux,at043tn24", 4368 .data = &innolux_at043tn24, 4369 }, { 4370 .compatible = "innolux,at070tn92", 4371 .data = &innolux_at070tn92, 4372 }, { 4373 .compatible = "innolux,g070ace-l01", 4374 .data = &innolux_g070ace_l01, 4375 }, { 4376 .compatible = "innolux,g070y2-l01", 4377 .data = &innolux_g070y2_l01, 4378 }, { 4379 .compatible = "innolux,g070y2-t02", 4380 .data = &innolux_g070y2_t02, 4381 }, { 4382 .compatible = "innolux,g101ice-l01", 4383 .data = &innolux_g101ice_l01 4384 }, { 4385 .compatible = "innolux,g121i1-l01", 4386 .data = &innolux_g121i1_l01 4387 }, { 4388 .compatible = "innolux,g121x1-l03", 4389 .data = &innolux_g121x1_l03, 4390 }, { 4391 .compatible = "innolux,g156hce-l01", 4392 .data = &innolux_g156hce_l01, 4393 }, { 4394 .compatible = "innolux,n156bge-l21", 4395 .data = &innolux_n156bge_l21, 4396 }, { 4397 .compatible = "innolux,zj070na-01p", 4398 .data = &innolux_zj070na_01p, 4399 }, { 4400 .compatible = "koe,tx14d24vm1bpa", 4401 .data = &koe_tx14d24vm1bpa, 4402 }, { 4403 .compatible = "koe,tx26d202vm0bwa", 4404 .data = &koe_tx26d202vm0bwa, 4405 }, { 4406 .compatible = "koe,tx31d200vm0baa", 4407 .data = &koe_tx31d200vm0baa, 4408 }, { 4409 .compatible = "kyo,tcg121xglp", 4410 .data = &kyo_tcg121xglp, 4411 }, { 4412 .compatible = "lemaker,bl035-rgb-002", 4413 .data = &lemaker_bl035_rgb_002, 4414 }, { 4415 .compatible = "lg,lb070wv8", 4416 .data = &lg_lb070wv8, 4417 }, { 4418 .compatible = "logicpd,type28", 4419 .data = &logicpd_type_28, 4420 }, { 4421 .compatible = "logictechno,lt161010-2nhc", 4422 .data = &logictechno_lt161010_2nh, 4423 }, { 4424 .compatible = "logictechno,lt161010-2nhr", 4425 .data = &logictechno_lt161010_2nh, 4426 }, { 4427 .compatible = "logictechno,lt170410-2whc", 4428 .data = &logictechno_lt170410_2whc, 4429 }, { 4430 .compatible = "logictechno,lttd800480070-l2rt", 4431 .data = &logictechno_lttd800480070_l2rt, 4432 }, { 4433 .compatible = "logictechno,lttd800480070-l6wh-rt", 4434 .data = &logictechno_lttd800480070_l6wh_rt, 4435 }, { 4436 .compatible = "mitsubishi,aa070mc01-ca1", 4437 .data = &mitsubishi_aa070mc01, 4438 }, { 4439 .compatible = "mitsubishi,aa084xe01", 4440 .data = &mitsubishi_aa084xe01, 4441 }, { 4442 .compatible = "multi-inno,mi0700s4t-6", 4443 .data = &multi_inno_mi0700s4t_6, 4444 }, { 4445 .compatible = "multi-inno,mi0800ft-9", 4446 .data = &multi_inno_mi0800ft_9, 4447 }, { 4448 .compatible = "multi-inno,mi1010ait-1cp", 4449 .data = &multi_inno_mi1010ait_1cp, 4450 }, { 4451 .compatible = "nec,nl12880bc20-05", 4452 .data = &nec_nl12880bc20_05, 4453 }, { 4454 .compatible = "nec,nl4827hc19-05b", 4455 .data = &nec_nl4827hc19_05b, 4456 }, { 4457 .compatible = "netron-dy,e231732", 4458 .data = &netron_dy_e231732, 4459 }, { 4460 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4461 .data = &newhaven_nhd_43_480272ef_atxl, 4462 }, { 4463 .compatible = "nlt,nl192108ac18-02d", 4464 .data = &nlt_nl192108ac18_02d, 4465 }, { 4466 .compatible = "nvd,9128", 4467 .data = &nvd_9128, 4468 }, { 4469 .compatible = "okaya,rs800480t-7x0gp", 4470 .data = &okaya_rs800480t_7x0gp, 4471 }, { 4472 .compatible = "olimex,lcd-olinuxino-43-ts", 4473 .data = &olimex_lcd_olinuxino_43ts, 4474 }, { 4475 .compatible = "ontat,yx700wv03", 4476 .data = &ontat_yx700wv03, 4477 }, { 4478 .compatible = "ortustech,com37h3m05dtc", 4479 .data = &ortustech_com37h3m, 4480 }, { 4481 .compatible = "ortustech,com37h3m99dtc", 4482 .data = &ortustech_com37h3m, 4483 }, { 4484 .compatible = "ortustech,com43h4m85ulc", 4485 .data = &ortustech_com43h4m85ulc, 4486 }, { 4487 .compatible = "osddisplays,osd070t1718-19ts", 4488 .data = &osddisplays_osd070t1718_19ts, 4489 }, { 4490 .compatible = "pda,91-00156-a0", 4491 .data = &pda_91_00156_a0, 4492 }, { 4493 .compatible = "powertip,ph800480t013-idf02", 4494 .data = &powertip_ph800480t013_idf02, 4495 }, { 4496 .compatible = "qiaodian,qd43003c0-40", 4497 .data = &qd43003c0_40, 4498 }, { 4499 .compatible = "qishenglong,gopher2b-lcd", 4500 .data = &qishenglong_gopher2b_lcd, 4501 }, { 4502 .compatible = "rocktech,rk043fn48h", 4503 .data = &rocktech_rk043fn48h, 4504 }, { 4505 .compatible = "rocktech,rk070er9427", 4506 .data = &rocktech_rk070er9427, 4507 }, { 4508 .compatible = "rocktech,rk101ii01d-ct", 4509 .data = &rocktech_rk101ii01d_ct, 4510 }, { 4511 .compatible = "samsung,ltl101al01", 4512 .data = &samsung_ltl101al01, 4513 }, { 4514 .compatible = "samsung,ltn101nt05", 4515 .data = &samsung_ltn101nt05, 4516 }, { 4517 .compatible = "satoz,sat050at40h12r2", 4518 .data = &satoz_sat050at40h12r2, 4519 }, { 4520 .compatible = "sharp,lq035q7db03", 4521 .data = &sharp_lq035q7db03, 4522 }, { 4523 .compatible = "sharp,lq070y3dg3b", 4524 .data = &sharp_lq070y3dg3b, 4525 }, { 4526 .compatible = "sharp,lq101k1ly04", 4527 .data = &sharp_lq101k1ly04, 4528 }, { 4529 .compatible = "sharp,ls020b1dd01d", 4530 .data = &sharp_ls020b1dd01d, 4531 }, { 4532 .compatible = "shelly,sca07010-bfn-lnn", 4533 .data = &shelly_sca07010_bfn_lnn, 4534 }, { 4535 .compatible = "starry,kr070pe2t", 4536 .data = &starry_kr070pe2t, 4537 }, { 4538 .compatible = "startek,kd070wvfpa", 4539 .data = &startek_kd070wvfpa, 4540 }, { 4541 .compatible = "team-source-display,tst043015cmhx", 4542 .data = &tsd_tst043015cmhx, 4543 }, { 4544 .compatible = "tfc,s9700rtwv43tr-01b", 4545 .data = &tfc_s9700rtwv43tr_01b, 4546 }, { 4547 .compatible = "tianma,tm070jdhg30", 4548 .data = &tianma_tm070jdhg30, 4549 }, { 4550 .compatible = "tianma,tm070jvhg33", 4551 .data = &tianma_tm070jvhg33, 4552 }, { 4553 .compatible = "tianma,tm070rvhg71", 4554 .data = &tianma_tm070rvhg71, 4555 }, { 4556 .compatible = "ti,nspire-cx-lcd-panel", 4557 .data = &ti_nspire_cx_lcd_panel, 4558 }, { 4559 .compatible = "ti,nspire-classic-lcd-panel", 4560 .data = &ti_nspire_classic_lcd_panel, 4561 }, { 4562 .compatible = "toshiba,lt089ac29000", 4563 .data = &toshiba_lt089ac29000, 4564 }, { 4565 .compatible = "tpk,f07a-0102", 4566 .data = &tpk_f07a_0102, 4567 }, { 4568 .compatible = "tpk,f10a-0102", 4569 .data = &tpk_f10a_0102, 4570 }, { 4571 .compatible = "urt,umsh-8596md-t", 4572 .data = &urt_umsh_8596md_parallel, 4573 }, { 4574 .compatible = "urt,umsh-8596md-1t", 4575 .data = &urt_umsh_8596md_parallel, 4576 }, { 4577 .compatible = "urt,umsh-8596md-7t", 4578 .data = &urt_umsh_8596md_parallel, 4579 }, { 4580 .compatible = "urt,umsh-8596md-11t", 4581 .data = &urt_umsh_8596md_lvds, 4582 }, { 4583 .compatible = "urt,umsh-8596md-19t", 4584 .data = &urt_umsh_8596md_lvds, 4585 }, { 4586 .compatible = "urt,umsh-8596md-20t", 4587 .data = &urt_umsh_8596md_parallel, 4588 }, { 4589 .compatible = "vivax,tpc9150-panel", 4590 .data = &vivax_tpc9150_panel, 4591 }, { 4592 .compatible = "vxt,vl050-8048nt-c01", 4593 .data = &vl050_8048nt_c01, 4594 }, { 4595 .compatible = "winstar,wf35ltiacd", 4596 .data = &winstar_wf35ltiacd, 4597 }, { 4598 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4599 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4600 }, { 4601 /* Must be the last entry */ 4602 .compatible = "panel-dpi", 4603 .data = &panel_dpi, 4604 }, { 4605 /* sentinel */ 4606 } 4607 }; 4608 MODULE_DEVICE_TABLE(of, platform_of_match); 4609 4610 static int panel_simple_platform_probe(struct platform_device *pdev) 4611 { 4612 const struct panel_desc *desc; 4613 4614 desc = of_device_get_match_data(&pdev->dev); 4615 if (!desc) 4616 return -ENODEV; 4617 4618 return panel_simple_probe(&pdev->dev, desc); 4619 } 4620 4621 static void panel_simple_platform_remove(struct platform_device *pdev) 4622 { 4623 panel_simple_remove(&pdev->dev); 4624 } 4625 4626 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4627 { 4628 panel_simple_shutdown(&pdev->dev); 4629 } 4630 4631 static const struct dev_pm_ops panel_simple_pm_ops = { 4632 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4633 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4634 pm_runtime_force_resume) 4635 }; 4636 4637 static struct platform_driver panel_simple_platform_driver = { 4638 .driver = { 4639 .name = "panel-simple", 4640 .of_match_table = platform_of_match, 4641 .pm = &panel_simple_pm_ops, 4642 }, 4643 .probe = panel_simple_platform_probe, 4644 .remove_new = panel_simple_platform_remove, 4645 .shutdown = panel_simple_platform_shutdown, 4646 }; 4647 4648 struct panel_desc_dsi { 4649 struct panel_desc desc; 4650 4651 unsigned long flags; 4652 enum mipi_dsi_pixel_format format; 4653 unsigned int lanes; 4654 }; 4655 4656 static const struct drm_display_mode auo_b080uan01_mode = { 4657 .clock = 154500, 4658 .hdisplay = 1200, 4659 .hsync_start = 1200 + 62, 4660 .hsync_end = 1200 + 62 + 4, 4661 .htotal = 1200 + 62 + 4 + 62, 4662 .vdisplay = 1920, 4663 .vsync_start = 1920 + 9, 4664 .vsync_end = 1920 + 9 + 2, 4665 .vtotal = 1920 + 9 + 2 + 8, 4666 }; 4667 4668 static const struct panel_desc_dsi auo_b080uan01 = { 4669 .desc = { 4670 .modes = &auo_b080uan01_mode, 4671 .num_modes = 1, 4672 .bpc = 8, 4673 .size = { 4674 .width = 108, 4675 .height = 272, 4676 }, 4677 .connector_type = DRM_MODE_CONNECTOR_DSI, 4678 }, 4679 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4680 .format = MIPI_DSI_FMT_RGB888, 4681 .lanes = 4, 4682 }; 4683 4684 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4685 .clock = 160000, 4686 .hdisplay = 1200, 4687 .hsync_start = 1200 + 120, 4688 .hsync_end = 1200 + 120 + 20, 4689 .htotal = 1200 + 120 + 20 + 21, 4690 .vdisplay = 1920, 4691 .vsync_start = 1920 + 21, 4692 .vsync_end = 1920 + 21 + 3, 4693 .vtotal = 1920 + 21 + 3 + 18, 4694 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4695 }; 4696 4697 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4698 .desc = { 4699 .modes = &boe_tv080wum_nl0_mode, 4700 .num_modes = 1, 4701 .size = { 4702 .width = 107, 4703 .height = 172, 4704 }, 4705 .connector_type = DRM_MODE_CONNECTOR_DSI, 4706 }, 4707 .flags = MIPI_DSI_MODE_VIDEO | 4708 MIPI_DSI_MODE_VIDEO_BURST | 4709 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4710 .format = MIPI_DSI_FMT_RGB888, 4711 .lanes = 4, 4712 }; 4713 4714 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4715 .clock = 71000, 4716 .hdisplay = 800, 4717 .hsync_start = 800 + 32, 4718 .hsync_end = 800 + 32 + 1, 4719 .htotal = 800 + 32 + 1 + 57, 4720 .vdisplay = 1280, 4721 .vsync_start = 1280 + 28, 4722 .vsync_end = 1280 + 28 + 1, 4723 .vtotal = 1280 + 28 + 1 + 14, 4724 }; 4725 4726 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4727 .desc = { 4728 .modes = &lg_ld070wx3_sl01_mode, 4729 .num_modes = 1, 4730 .bpc = 8, 4731 .size = { 4732 .width = 94, 4733 .height = 151, 4734 }, 4735 .connector_type = DRM_MODE_CONNECTOR_DSI, 4736 }, 4737 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4738 .format = MIPI_DSI_FMT_RGB888, 4739 .lanes = 4, 4740 }; 4741 4742 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4743 .clock = 67000, 4744 .hdisplay = 720, 4745 .hsync_start = 720 + 12, 4746 .hsync_end = 720 + 12 + 4, 4747 .htotal = 720 + 12 + 4 + 112, 4748 .vdisplay = 1280, 4749 .vsync_start = 1280 + 8, 4750 .vsync_end = 1280 + 8 + 4, 4751 .vtotal = 1280 + 8 + 4 + 12, 4752 }; 4753 4754 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4755 .desc = { 4756 .modes = &lg_lh500wx1_sd03_mode, 4757 .num_modes = 1, 4758 .bpc = 8, 4759 .size = { 4760 .width = 62, 4761 .height = 110, 4762 }, 4763 .connector_type = DRM_MODE_CONNECTOR_DSI, 4764 }, 4765 .flags = MIPI_DSI_MODE_VIDEO, 4766 .format = MIPI_DSI_FMT_RGB888, 4767 .lanes = 4, 4768 }; 4769 4770 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4771 .clock = 157200, 4772 .hdisplay = 1920, 4773 .hsync_start = 1920 + 154, 4774 .hsync_end = 1920 + 154 + 16, 4775 .htotal = 1920 + 154 + 16 + 32, 4776 .vdisplay = 1200, 4777 .vsync_start = 1200 + 17, 4778 .vsync_end = 1200 + 17 + 2, 4779 .vtotal = 1200 + 17 + 2 + 16, 4780 }; 4781 4782 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4783 .desc = { 4784 .modes = &panasonic_vvx10f004b00_mode, 4785 .num_modes = 1, 4786 .bpc = 8, 4787 .size = { 4788 .width = 217, 4789 .height = 136, 4790 }, 4791 .connector_type = DRM_MODE_CONNECTOR_DSI, 4792 }, 4793 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4794 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4795 .format = MIPI_DSI_FMT_RGB888, 4796 .lanes = 4, 4797 }; 4798 4799 static const struct drm_display_mode lg_acx467akm_7_mode = { 4800 .clock = 150000, 4801 .hdisplay = 1080, 4802 .hsync_start = 1080 + 2, 4803 .hsync_end = 1080 + 2 + 2, 4804 .htotal = 1080 + 2 + 2 + 2, 4805 .vdisplay = 1920, 4806 .vsync_start = 1920 + 2, 4807 .vsync_end = 1920 + 2 + 2, 4808 .vtotal = 1920 + 2 + 2 + 2, 4809 }; 4810 4811 static const struct panel_desc_dsi lg_acx467akm_7 = { 4812 .desc = { 4813 .modes = &lg_acx467akm_7_mode, 4814 .num_modes = 1, 4815 .bpc = 8, 4816 .size = { 4817 .width = 62, 4818 .height = 110, 4819 }, 4820 .connector_type = DRM_MODE_CONNECTOR_DSI, 4821 }, 4822 .flags = 0, 4823 .format = MIPI_DSI_FMT_RGB888, 4824 .lanes = 4, 4825 }; 4826 4827 static const struct drm_display_mode osd101t2045_53ts_mode = { 4828 .clock = 154500, 4829 .hdisplay = 1920, 4830 .hsync_start = 1920 + 112, 4831 .hsync_end = 1920 + 112 + 16, 4832 .htotal = 1920 + 112 + 16 + 32, 4833 .vdisplay = 1200, 4834 .vsync_start = 1200 + 16, 4835 .vsync_end = 1200 + 16 + 2, 4836 .vtotal = 1200 + 16 + 2 + 16, 4837 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4838 }; 4839 4840 static const struct panel_desc_dsi osd101t2045_53ts = { 4841 .desc = { 4842 .modes = &osd101t2045_53ts_mode, 4843 .num_modes = 1, 4844 .bpc = 8, 4845 .size = { 4846 .width = 217, 4847 .height = 136, 4848 }, 4849 .connector_type = DRM_MODE_CONNECTOR_DSI, 4850 }, 4851 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4852 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4853 MIPI_DSI_MODE_NO_EOT_PACKET, 4854 .format = MIPI_DSI_FMT_RGB888, 4855 .lanes = 4, 4856 }; 4857 4858 static const struct of_device_id dsi_of_match[] = { 4859 { 4860 .compatible = "auo,b080uan01", 4861 .data = &auo_b080uan01 4862 }, { 4863 .compatible = "boe,tv080wum-nl0", 4864 .data = &boe_tv080wum_nl0 4865 }, { 4866 .compatible = "lg,ld070wx3-sl01", 4867 .data = &lg_ld070wx3_sl01 4868 }, { 4869 .compatible = "lg,lh500wx1-sd03", 4870 .data = &lg_lh500wx1_sd03 4871 }, { 4872 .compatible = "panasonic,vvx10f004b00", 4873 .data = &panasonic_vvx10f004b00 4874 }, { 4875 .compatible = "lg,acx467akm-7", 4876 .data = &lg_acx467akm_7 4877 }, { 4878 .compatible = "osddisplays,osd101t2045-53ts", 4879 .data = &osd101t2045_53ts 4880 }, { 4881 /* sentinel */ 4882 } 4883 }; 4884 MODULE_DEVICE_TABLE(of, dsi_of_match); 4885 4886 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4887 { 4888 const struct panel_desc_dsi *desc; 4889 int err; 4890 4891 desc = of_device_get_match_data(&dsi->dev); 4892 if (!desc) 4893 return -ENODEV; 4894 4895 err = panel_simple_probe(&dsi->dev, &desc->desc); 4896 if (err < 0) 4897 return err; 4898 4899 dsi->mode_flags = desc->flags; 4900 dsi->format = desc->format; 4901 dsi->lanes = desc->lanes; 4902 4903 err = mipi_dsi_attach(dsi); 4904 if (err) { 4905 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4906 4907 drm_panel_remove(&panel->base); 4908 } 4909 4910 return err; 4911 } 4912 4913 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4914 { 4915 int err; 4916 4917 err = mipi_dsi_detach(dsi); 4918 if (err < 0) 4919 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4920 4921 panel_simple_remove(&dsi->dev); 4922 } 4923 4924 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4925 { 4926 panel_simple_shutdown(&dsi->dev); 4927 } 4928 4929 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4930 .driver = { 4931 .name = "panel-simple-dsi", 4932 .of_match_table = dsi_of_match, 4933 .pm = &panel_simple_pm_ops, 4934 }, 4935 .probe = panel_simple_dsi_probe, 4936 .remove = panel_simple_dsi_remove, 4937 .shutdown = panel_simple_dsi_shutdown, 4938 }; 4939 4940 static int __init panel_simple_init(void) 4941 { 4942 int err; 4943 4944 err = platform_driver_register(&panel_simple_platform_driver); 4945 if (err < 0) 4946 return err; 4947 4948 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4949 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4950 if (err < 0) 4951 goto err_did_platform_register; 4952 } 4953 4954 return 0; 4955 4956 err_did_platform_register: 4957 platform_driver_unregister(&panel_simple_platform_driver); 4958 4959 return err; 4960 } 4961 module_init(panel_simple_init); 4962 4963 static void __exit panel_simple_exit(void) 4964 { 4965 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4966 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4967 4968 platform_driver_unregister(&panel_simple_platform_driver); 4969 } 4970 module_exit(panel_simple_exit); 4971 4972 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4973 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4974 MODULE_LICENSE("GPL and additional rights"); 4975