1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 142 ktime_t unprepared_time; 143 144 const struct panel_desc *desc; 145 146 struct regulator *supply; 147 struct i2c_adapter *ddc; 148 149 struct gpio_desc *enable_gpio; 150 151 const struct drm_edid *drm_edid; 152 153 struct drm_display_mode override_mode; 154 155 enum drm_panel_orientation orientation; 156 }; 157 158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 159 { 160 return container_of(panel, struct panel_simple, base); 161 } 162 163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 164 struct drm_connector *connector) 165 { 166 struct drm_display_mode *mode; 167 unsigned int i, num = 0; 168 169 for (i = 0; i < panel->desc->num_timings; i++) { 170 const struct display_timing *dt = &panel->desc->timings[i]; 171 struct videomode vm; 172 173 videomode_from_timing(dt, &vm); 174 mode = drm_mode_create(connector->dev); 175 if (!mode) { 176 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 177 dt->hactive.typ, dt->vactive.typ); 178 continue; 179 } 180 181 drm_display_mode_from_videomode(&vm, mode); 182 183 mode->type |= DRM_MODE_TYPE_DRIVER; 184 185 if (panel->desc->num_timings == 1) 186 mode->type |= DRM_MODE_TYPE_PREFERRED; 187 188 drm_mode_probed_add(connector, mode); 189 num++; 190 } 191 192 return num; 193 } 194 195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 196 struct drm_connector *connector) 197 { 198 struct drm_display_mode *mode; 199 unsigned int i, num = 0; 200 201 for (i = 0; i < panel->desc->num_modes; i++) { 202 const struct drm_display_mode *m = &panel->desc->modes[i]; 203 204 mode = drm_mode_duplicate(connector->dev, m); 205 if (!mode) { 206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 207 m->hdisplay, m->vdisplay, 208 drm_mode_vrefresh(m)); 209 continue; 210 } 211 212 mode->type |= DRM_MODE_TYPE_DRIVER; 213 214 if (panel->desc->num_modes == 1) 215 mode->type |= DRM_MODE_TYPE_PREFERRED; 216 217 drm_mode_set_name(mode); 218 219 drm_mode_probed_add(connector, mode); 220 num++; 221 } 222 223 return num; 224 } 225 226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 227 struct drm_connector *connector) 228 { 229 struct drm_display_mode *mode; 230 bool has_override = panel->override_mode.type; 231 unsigned int num = 0; 232 233 if (!panel->desc) 234 return 0; 235 236 if (has_override) { 237 mode = drm_mode_duplicate(connector->dev, 238 &panel->override_mode); 239 if (mode) { 240 drm_mode_probed_add(connector, mode); 241 num = 1; 242 } else { 243 dev_err(panel->base.dev, "failed to add override mode\n"); 244 } 245 } 246 247 /* Only add timings if override was not there or failed to validate */ 248 if (num == 0 && panel->desc->num_timings) 249 num = panel_simple_get_timings_modes(panel, connector); 250 251 /* 252 * Only add fixed modes if timings/override added no mode. 253 * 254 * We should only ever have either the display timings specified 255 * or a fixed mode. Anything else is rather bogus. 256 */ 257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 258 if (num == 0) 259 num = panel_simple_get_display_modes(panel, connector); 260 261 connector->display_info.bpc = panel->desc->bpc; 262 connector->display_info.width_mm = panel->desc->size.width; 263 connector->display_info.height_mm = panel->desc->size.height; 264 if (panel->desc->bus_format) 265 drm_display_info_set_bus_formats(&connector->display_info, 266 &panel->desc->bus_format, 1); 267 connector->display_info.bus_flags = panel->desc->bus_flags; 268 269 return num; 270 } 271 272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 273 { 274 ktime_t now_ktime, min_ktime; 275 276 if (!min_ms) 277 return; 278 279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 280 now_ktime = ktime_get_boottime(); 281 282 if (ktime_before(now_ktime, min_ktime)) 283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 284 } 285 286 static int panel_simple_disable(struct drm_panel *panel) 287 { 288 struct panel_simple *p = to_panel_simple(panel); 289 290 if (p->desc->delay.disable) 291 msleep(p->desc->delay.disable); 292 293 return 0; 294 } 295 296 static int panel_simple_suspend(struct device *dev) 297 { 298 struct panel_simple *p = dev_get_drvdata(dev); 299 300 gpiod_set_value_cansleep(p->enable_gpio, 0); 301 regulator_disable(p->supply); 302 p->unprepared_time = ktime_get_boottime(); 303 304 drm_edid_free(p->drm_edid); 305 p->drm_edid = NULL; 306 307 return 0; 308 } 309 310 static int panel_simple_unprepare(struct drm_panel *panel) 311 { 312 int ret; 313 314 pm_runtime_mark_last_busy(panel->dev); 315 ret = pm_runtime_put_autosuspend(panel->dev); 316 if (ret < 0) 317 return ret; 318 319 return 0; 320 } 321 322 static int panel_simple_resume(struct device *dev) 323 { 324 struct panel_simple *p = dev_get_drvdata(dev); 325 int err; 326 327 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 328 329 err = regulator_enable(p->supply); 330 if (err < 0) { 331 dev_err(dev, "failed to enable supply: %d\n", err); 332 return err; 333 } 334 335 gpiod_set_value_cansleep(p->enable_gpio, 1); 336 337 if (p->desc->delay.prepare) 338 msleep(p->desc->delay.prepare); 339 340 return 0; 341 } 342 343 static int panel_simple_prepare(struct drm_panel *panel) 344 { 345 int ret; 346 347 ret = pm_runtime_get_sync(panel->dev); 348 if (ret < 0) { 349 pm_runtime_put_autosuspend(panel->dev); 350 return ret; 351 } 352 353 return 0; 354 } 355 356 static int panel_simple_enable(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 360 if (p->desc->delay.enable) 361 msleep(p->desc->delay.enable); 362 363 return 0; 364 } 365 366 static int panel_simple_get_modes(struct drm_panel *panel, 367 struct drm_connector *connector) 368 { 369 struct panel_simple *p = to_panel_simple(panel); 370 int num = 0; 371 372 /* probe EDID if a DDC bus is available */ 373 if (p->ddc) { 374 pm_runtime_get_sync(panel->dev); 375 376 if (!p->drm_edid) 377 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 378 379 drm_edid_connector_update(connector, p->drm_edid); 380 381 num += drm_edid_connector_add_modes(connector); 382 383 pm_runtime_mark_last_busy(panel->dev); 384 pm_runtime_put_autosuspend(panel->dev); 385 } 386 387 /* add hard-coded panel modes */ 388 num += panel_simple_get_non_edid_modes(p, connector); 389 390 /* 391 * TODO: Remove once all drm drivers call 392 * drm_connector_set_orientation_from_panel() 393 */ 394 drm_connector_set_panel_orientation(connector, p->orientation); 395 396 return num; 397 } 398 399 static int panel_simple_get_timings(struct drm_panel *panel, 400 unsigned int num_timings, 401 struct display_timing *timings) 402 { 403 struct panel_simple *p = to_panel_simple(panel); 404 unsigned int i; 405 406 if (p->desc->num_timings < num_timings) 407 num_timings = p->desc->num_timings; 408 409 if (timings) 410 for (i = 0; i < num_timings; i++) 411 timings[i] = p->desc->timings[i]; 412 413 return p->desc->num_timings; 414 } 415 416 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 417 { 418 struct panel_simple *p = to_panel_simple(panel); 419 420 return p->orientation; 421 } 422 423 static const struct drm_panel_funcs panel_simple_funcs = { 424 .disable = panel_simple_disable, 425 .unprepare = panel_simple_unprepare, 426 .prepare = panel_simple_prepare, 427 .enable = panel_simple_enable, 428 .get_modes = panel_simple_get_modes, 429 .get_orientation = panel_simple_get_orientation, 430 .get_timings = panel_simple_get_timings, 431 }; 432 433 static struct panel_desc panel_dpi; 434 435 static int panel_dpi_probe(struct device *dev, 436 struct panel_simple *panel) 437 { 438 struct display_timing *timing; 439 const struct device_node *np; 440 struct panel_desc *desc; 441 unsigned int bus_flags; 442 struct videomode vm; 443 int ret; 444 445 np = dev->of_node; 446 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 447 if (!desc) 448 return -ENOMEM; 449 450 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 451 if (!timing) 452 return -ENOMEM; 453 454 ret = of_get_display_timing(np, "panel-timing", timing); 455 if (ret < 0) { 456 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 457 np); 458 return ret; 459 } 460 461 desc->timings = timing; 462 desc->num_timings = 1; 463 464 of_property_read_u32(np, "width-mm", &desc->size.width); 465 of_property_read_u32(np, "height-mm", &desc->size.height); 466 467 /* Extract bus_flags from display_timing */ 468 bus_flags = 0; 469 vm.flags = timing->flags; 470 drm_bus_flags_from_videomode(&vm, &bus_flags); 471 desc->bus_flags = bus_flags; 472 473 /* We do not know the connector for the DT node, so guess it */ 474 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 475 476 panel->desc = desc; 477 478 return 0; 479 } 480 481 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 482 (to_check->field.typ >= bounds->field.min && \ 483 to_check->field.typ <= bounds->field.max) 484 static void panel_simple_parse_panel_timing_node(struct device *dev, 485 struct panel_simple *panel, 486 const struct display_timing *ot) 487 { 488 const struct panel_desc *desc = panel->desc; 489 struct videomode vm; 490 unsigned int i; 491 492 if (WARN_ON(desc->num_modes)) { 493 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 494 return; 495 } 496 if (WARN_ON(!desc->num_timings)) { 497 dev_err(dev, "Reject override mode: no timings specified\n"); 498 return; 499 } 500 501 for (i = 0; i < panel->desc->num_timings; i++) { 502 const struct display_timing *dt = &panel->desc->timings[i]; 503 504 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 505 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 506 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 507 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 508 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 512 continue; 513 514 if (ot->flags != dt->flags) 515 continue; 516 517 videomode_from_timing(ot, &vm); 518 drm_display_mode_from_videomode(&vm, &panel->override_mode); 519 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 520 DRM_MODE_TYPE_PREFERRED; 521 break; 522 } 523 524 if (WARN_ON(!panel->override_mode.type)) 525 dev_err(dev, "Reject override mode: No display_timing found\n"); 526 } 527 528 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 529 struct panel_simple *panel) 530 { 531 int ret, bpc; 532 533 ret = drm_of_lvds_get_data_mapping(dev->of_node); 534 if (ret < 0) { 535 if (ret == -EINVAL) 536 dev_warn(dev, "Ignore invalid data-mapping property\n"); 537 538 /* 539 * Ignore non-existing or malformatted property, fallback to 540 * default data-mapping, and return 0. 541 */ 542 return 0; 543 } 544 545 switch (ret) { 546 default: 547 WARN_ON(1); 548 fallthrough; 549 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 550 fallthrough; 551 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 552 bpc = 8; 553 break; 554 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 555 bpc = 6; 556 } 557 558 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 559 struct panel_desc *override_desc; 560 561 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 562 if (!override_desc) 563 return -ENOMEM; 564 565 override_desc->bus_format = ret; 566 override_desc->bpc = bpc; 567 panel->desc = override_desc; 568 } 569 570 return 0; 571 } 572 573 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 574 { 575 struct panel_simple *panel; 576 struct display_timing dt; 577 struct device_node *ddc; 578 int connector_type; 579 u32 bus_flags; 580 int err; 581 582 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 583 &panel_simple_funcs, desc->connector_type); 584 if (IS_ERR(panel)) 585 return PTR_ERR(panel); 586 587 panel->desc = desc; 588 589 panel->supply = devm_regulator_get(dev, "power"); 590 if (IS_ERR(panel->supply)) 591 return PTR_ERR(panel->supply); 592 593 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 594 GPIOD_OUT_LOW); 595 if (IS_ERR(panel->enable_gpio)) 596 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 597 "failed to request GPIO\n"); 598 599 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 600 if (err) { 601 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 602 return err; 603 } 604 605 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 606 if (ddc) { 607 panel->ddc = of_find_i2c_adapter_by_node(ddc); 608 of_node_put(ddc); 609 610 if (!panel->ddc) 611 return -EPROBE_DEFER; 612 } 613 614 if (desc == &panel_dpi) { 615 /* Handle the generic panel-dpi binding */ 616 err = panel_dpi_probe(dev, panel); 617 if (err) 618 goto free_ddc; 619 desc = panel->desc; 620 } else { 621 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 622 panel_simple_parse_panel_timing_node(dev, panel, &dt); 623 } 624 625 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 626 /* Optional data-mapping property for overriding bus format */ 627 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 628 if (err) 629 goto free_ddc; 630 } 631 632 connector_type = desc->connector_type; 633 /* Catch common mistakes for panels. */ 634 switch (connector_type) { 635 case 0: 636 dev_warn(dev, "Specify missing connector_type\n"); 637 connector_type = DRM_MODE_CONNECTOR_DPI; 638 break; 639 case DRM_MODE_CONNECTOR_LVDS: 640 WARN_ON(desc->bus_flags & 641 ~(DRM_BUS_FLAG_DE_LOW | 642 DRM_BUS_FLAG_DE_HIGH | 643 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 644 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 645 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 646 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 647 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 648 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 649 desc->bpc != 6); 650 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 651 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 652 desc->bpc != 8); 653 break; 654 case DRM_MODE_CONNECTOR_eDP: 655 dev_warn(dev, "eDP panels moved to panel-edp\n"); 656 err = -EINVAL; 657 goto free_ddc; 658 case DRM_MODE_CONNECTOR_DSI: 659 if (desc->bpc != 6 && desc->bpc != 8) 660 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 661 break; 662 case DRM_MODE_CONNECTOR_DPI: 663 bus_flags = DRM_BUS_FLAG_DE_LOW | 664 DRM_BUS_FLAG_DE_HIGH | 665 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 666 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 667 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 668 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 669 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 670 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 671 if (desc->bus_flags & ~bus_flags) 672 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 673 if (!(desc->bus_flags & bus_flags)) 674 dev_warn(dev, "Specify missing bus_flags\n"); 675 if (desc->bus_format == 0) 676 dev_warn(dev, "Specify missing bus_format\n"); 677 if (desc->bpc != 6 && desc->bpc != 8) 678 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 679 break; 680 default: 681 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 682 connector_type = DRM_MODE_CONNECTOR_DPI; 683 break; 684 } 685 686 dev_set_drvdata(dev, panel); 687 688 /* 689 * We use runtime PM for prepare / unprepare since those power the panel 690 * on and off and those can be very slow operations. This is important 691 * to optimize powering the panel on briefly to read the EDID before 692 * fully enabling the panel. 693 */ 694 pm_runtime_enable(dev); 695 pm_runtime_set_autosuspend_delay(dev, 1000); 696 pm_runtime_use_autosuspend(dev); 697 698 err = drm_panel_of_backlight(&panel->base); 699 if (err) { 700 dev_err_probe(dev, err, "Could not find backlight\n"); 701 goto disable_pm_runtime; 702 } 703 704 drm_panel_add(&panel->base); 705 706 return 0; 707 708 disable_pm_runtime: 709 pm_runtime_dont_use_autosuspend(dev); 710 pm_runtime_disable(dev); 711 free_ddc: 712 if (panel->ddc) 713 put_device(&panel->ddc->dev); 714 715 return err; 716 } 717 718 static void panel_simple_shutdown(struct device *dev) 719 { 720 struct panel_simple *panel = dev_get_drvdata(dev); 721 722 /* 723 * NOTE: the following two calls don't really belong here. It is the 724 * responsibility of a correctly written DRM modeset driver to call 725 * drm_atomic_helper_shutdown() at shutdown time and that should 726 * cause the panel to be disabled / unprepared if needed. For now, 727 * however, we'll keep these calls due to the sheer number of 728 * different DRM modeset drivers used with panel-simple. Once we've 729 * confirmed that all DRM modeset drivers using this panel properly 730 * call drm_atomic_helper_shutdown() we can simply delete the two 731 * calls below. 732 * 733 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 734 * PANEL DRIVERS. 735 * 736 * FIXME: If we're still haven't figured out if all DRM modeset 737 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 738 * managed to make sure that DRM modeset drivers get their shutdown() 739 * callback before the panel's shutdown() callback (perhaps using 740 * device link), we could add a WARN_ON here to help move forward. 741 */ 742 if (panel->base.enabled) 743 drm_panel_disable(&panel->base); 744 if (panel->base.prepared) 745 drm_panel_unprepare(&panel->base); 746 } 747 748 static void panel_simple_remove(struct device *dev) 749 { 750 struct panel_simple *panel = dev_get_drvdata(dev); 751 752 drm_panel_remove(&panel->base); 753 panel_simple_shutdown(dev); 754 755 pm_runtime_dont_use_autosuspend(dev); 756 pm_runtime_disable(dev); 757 if (panel->ddc) 758 put_device(&panel->ddc->dev); 759 } 760 761 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 762 .clock = 71100, 763 .hdisplay = 1280, 764 .hsync_start = 1280 + 40, 765 .hsync_end = 1280 + 40 + 80, 766 .htotal = 1280 + 40 + 80 + 40, 767 .vdisplay = 800, 768 .vsync_start = 800 + 3, 769 .vsync_end = 800 + 3 + 10, 770 .vtotal = 800 + 3 + 10 + 10, 771 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 772 }; 773 774 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 775 .modes = &ire_am_1280800n3tzqw_t00h_mode, 776 .num_modes = 1, 777 .bpc = 8, 778 .size = { 779 .width = 217, 780 .height = 136, 781 }, 782 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 783 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 784 .connector_type = DRM_MODE_CONNECTOR_LVDS, 785 }; 786 787 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 788 .clock = 9000, 789 .hdisplay = 480, 790 .hsync_start = 480 + 2, 791 .hsync_end = 480 + 2 + 41, 792 .htotal = 480 + 2 + 41 + 2, 793 .vdisplay = 272, 794 .vsync_start = 272 + 2, 795 .vsync_end = 272 + 2 + 10, 796 .vtotal = 272 + 2 + 10 + 2, 797 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 798 }; 799 800 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 801 .modes = &ire_am_480272h3tmqw_t01h_mode, 802 .num_modes = 1, 803 .bpc = 8, 804 .size = { 805 .width = 99, 806 .height = 58, 807 }, 808 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 809 }; 810 811 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 812 .clock = 33333, 813 .hdisplay = 800, 814 .hsync_start = 800 + 0, 815 .hsync_end = 800 + 0 + 255, 816 .htotal = 800 + 0 + 255 + 0, 817 .vdisplay = 480, 818 .vsync_start = 480 + 2, 819 .vsync_end = 480 + 2 + 45, 820 .vtotal = 480 + 2 + 45 + 0, 821 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 822 }; 823 824 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 825 .pixelclock = { 29930000, 33260000, 36590000 }, 826 .hactive = { 800, 800, 800 }, 827 .hfront_porch = { 1, 40, 168 }, 828 .hback_porch = { 88, 88, 88 }, 829 .hsync_len = { 1, 128, 128 }, 830 .vactive = { 480, 480, 480 }, 831 .vfront_porch = { 1, 35, 37 }, 832 .vback_porch = { 8, 8, 8 }, 833 .vsync_len = { 1, 2, 2 }, 834 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 835 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 836 DISPLAY_FLAGS_SYNC_POSEDGE, 837 }; 838 839 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 840 .timings = &ire_am_800480l1tmqw_t00h_timing, 841 .num_timings = 1, 842 .bpc = 8, 843 .size = { 844 .width = 111, 845 .height = 67, 846 }, 847 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 848 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 849 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 850 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 851 .connector_type = DRM_MODE_CONNECTOR_DPI, 852 }; 853 854 static const struct panel_desc ampire_am800480r3tmqwa1h = { 855 .modes = &ire_am800480r3tmqwa1h_mode, 856 .num_modes = 1, 857 .bpc = 6, 858 .size = { 859 .width = 152, 860 .height = 91, 861 }, 862 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 863 }; 864 865 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 866 .pixelclock = { 34500000, 39600000, 50400000 }, 867 .hactive = { 800, 800, 800 }, 868 .hfront_porch = { 12, 112, 312 }, 869 .hback_porch = { 87, 87, 48 }, 870 .hsync_len = { 1, 1, 40 }, 871 .vactive = { 600, 600, 600 }, 872 .vfront_porch = { 1, 21, 61 }, 873 .vback_porch = { 38, 38, 19 }, 874 .vsync_len = { 1, 1, 20 }, 875 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 876 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 877 DISPLAY_FLAGS_SYNC_POSEDGE, 878 }; 879 880 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 881 .timings = &ire_am800600p5tmqw_tb8h_timing, 882 .num_timings = 1, 883 .bpc = 6, 884 .size = { 885 .width = 162, 886 .height = 122, 887 }, 888 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 889 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 890 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 891 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 892 .connector_type = DRM_MODE_CONNECTOR_DPI, 893 }; 894 895 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 896 .pixelclock = { 26400000, 33300000, 46800000 }, 897 .hactive = { 800, 800, 800 }, 898 .hfront_porch = { 16, 210, 354 }, 899 .hback_porch = { 45, 36, 6 }, 900 .hsync_len = { 1, 10, 40 }, 901 .vactive = { 480, 480, 480 }, 902 .vfront_porch = { 7, 22, 147 }, 903 .vback_porch = { 22, 13, 3 }, 904 .vsync_len = { 1, 10, 20 }, 905 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 906 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 907 }; 908 909 static const struct panel_desc armadeus_st0700_adapt = { 910 .timings = &santek_st0700i5y_rbslw_f_timing, 911 .num_timings = 1, 912 .bpc = 6, 913 .size = { 914 .width = 154, 915 .height = 86, 916 }, 917 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 918 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 919 }; 920 921 static const struct drm_display_mode auo_b101aw03_mode = { 922 .clock = 51450, 923 .hdisplay = 1024, 924 .hsync_start = 1024 + 156, 925 .hsync_end = 1024 + 156 + 8, 926 .htotal = 1024 + 156 + 8 + 156, 927 .vdisplay = 600, 928 .vsync_start = 600 + 16, 929 .vsync_end = 600 + 16 + 6, 930 .vtotal = 600 + 16 + 6 + 16, 931 }; 932 933 static const struct panel_desc auo_b101aw03 = { 934 .modes = &auo_b101aw03_mode, 935 .num_modes = 1, 936 .bpc = 6, 937 .size = { 938 .width = 223, 939 .height = 125, 940 }, 941 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 942 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 943 .connector_type = DRM_MODE_CONNECTOR_LVDS, 944 }; 945 946 static const struct drm_display_mode auo_b101xtn01_mode = { 947 .clock = 72000, 948 .hdisplay = 1366, 949 .hsync_start = 1366 + 20, 950 .hsync_end = 1366 + 20 + 70, 951 .htotal = 1366 + 20 + 70, 952 .vdisplay = 768, 953 .vsync_start = 768 + 14, 954 .vsync_end = 768 + 14 + 42, 955 .vtotal = 768 + 14 + 42, 956 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 957 }; 958 959 static const struct panel_desc auo_b101xtn01 = { 960 .modes = &auo_b101xtn01_mode, 961 .num_modes = 1, 962 .bpc = 6, 963 .size = { 964 .width = 223, 965 .height = 125, 966 }, 967 }; 968 969 static const struct drm_display_mode auo_b116xw03_mode = { 970 .clock = 70589, 971 .hdisplay = 1366, 972 .hsync_start = 1366 + 40, 973 .hsync_end = 1366 + 40 + 40, 974 .htotal = 1366 + 40 + 40 + 32, 975 .vdisplay = 768, 976 .vsync_start = 768 + 10, 977 .vsync_end = 768 + 10 + 12, 978 .vtotal = 768 + 10 + 12 + 6, 979 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 980 }; 981 982 static const struct panel_desc auo_b116xw03 = { 983 .modes = &auo_b116xw03_mode, 984 .num_modes = 1, 985 .bpc = 6, 986 .size = { 987 .width = 256, 988 .height = 144, 989 }, 990 .delay = { 991 .prepare = 1, 992 .enable = 200, 993 .disable = 200, 994 .unprepare = 500, 995 }, 996 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 997 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 998 .connector_type = DRM_MODE_CONNECTOR_LVDS, 999 }; 1000 1001 static const struct display_timing auo_g070vvn01_timings = { 1002 .pixelclock = { 33300000, 34209000, 45000000 }, 1003 .hactive = { 800, 800, 800 }, 1004 .hfront_porch = { 20, 40, 200 }, 1005 .hback_porch = { 87, 40, 1 }, 1006 .hsync_len = { 1, 48, 87 }, 1007 .vactive = { 480, 480, 480 }, 1008 .vfront_porch = { 5, 13, 200 }, 1009 .vback_porch = { 31, 31, 29 }, 1010 .vsync_len = { 1, 1, 3 }, 1011 }; 1012 1013 static const struct panel_desc auo_g070vvn01 = { 1014 .timings = &auo_g070vvn01_timings, 1015 .num_timings = 1, 1016 .bpc = 8, 1017 .size = { 1018 .width = 152, 1019 .height = 91, 1020 }, 1021 .delay = { 1022 .prepare = 200, 1023 .enable = 50, 1024 .disable = 50, 1025 .unprepare = 1000, 1026 }, 1027 }; 1028 1029 static const struct drm_display_mode auo_g101evn010_mode = { 1030 .clock = 68930, 1031 .hdisplay = 1280, 1032 .hsync_start = 1280 + 82, 1033 .hsync_end = 1280 + 82 + 2, 1034 .htotal = 1280 + 82 + 2 + 84, 1035 .vdisplay = 800, 1036 .vsync_start = 800 + 8, 1037 .vsync_end = 800 + 8 + 2, 1038 .vtotal = 800 + 8 + 2 + 6, 1039 }; 1040 1041 static const struct panel_desc auo_g101evn010 = { 1042 .modes = &auo_g101evn010_mode, 1043 .num_modes = 1, 1044 .bpc = 6, 1045 .size = { 1046 .width = 216, 1047 .height = 135, 1048 }, 1049 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1050 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1051 }; 1052 1053 static const struct drm_display_mode auo_g104sn02_mode = { 1054 .clock = 40000, 1055 .hdisplay = 800, 1056 .hsync_start = 800 + 40, 1057 .hsync_end = 800 + 40 + 216, 1058 .htotal = 800 + 40 + 216 + 128, 1059 .vdisplay = 600, 1060 .vsync_start = 600 + 10, 1061 .vsync_end = 600 + 10 + 35, 1062 .vtotal = 600 + 10 + 35 + 2, 1063 }; 1064 1065 static const struct panel_desc auo_g104sn02 = { 1066 .modes = &auo_g104sn02_mode, 1067 .num_modes = 1, 1068 .bpc = 8, 1069 .size = { 1070 .width = 211, 1071 .height = 158, 1072 }, 1073 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1074 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1075 }; 1076 1077 static const struct drm_display_mode auo_g104stn01_mode = { 1078 .clock = 40000, 1079 .hdisplay = 800, 1080 .hsync_start = 800 + 40, 1081 .hsync_end = 800 + 40 + 88, 1082 .htotal = 800 + 40 + 88 + 128, 1083 .vdisplay = 600, 1084 .vsync_start = 600 + 1, 1085 .vsync_end = 600 + 1 + 23, 1086 .vtotal = 600 + 1 + 23 + 4, 1087 }; 1088 1089 static const struct panel_desc auo_g104stn01 = { 1090 .modes = &auo_g104stn01_mode, 1091 .num_modes = 1, 1092 .bpc = 8, 1093 .size = { 1094 .width = 211, 1095 .height = 158, 1096 }, 1097 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1098 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1099 }; 1100 1101 static const struct display_timing auo_g121ean01_timing = { 1102 .pixelclock = { 60000000, 74400000, 90000000 }, 1103 .hactive = { 1280, 1280, 1280 }, 1104 .hfront_porch = { 20, 50, 100 }, 1105 .hback_porch = { 20, 50, 100 }, 1106 .hsync_len = { 30, 100, 200 }, 1107 .vactive = { 800, 800, 800 }, 1108 .vfront_porch = { 2, 10, 25 }, 1109 .vback_porch = { 2, 10, 25 }, 1110 .vsync_len = { 4, 18, 50 }, 1111 }; 1112 1113 static const struct panel_desc auo_g121ean01 = { 1114 .timings = &auo_g121ean01_timing, 1115 .num_timings = 1, 1116 .bpc = 8, 1117 .size = { 1118 .width = 261, 1119 .height = 163, 1120 }, 1121 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1122 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1123 }; 1124 1125 static const struct display_timing auo_g133han01_timings = { 1126 .pixelclock = { 134000000, 141200000, 149000000 }, 1127 .hactive = { 1920, 1920, 1920 }, 1128 .hfront_porch = { 39, 58, 77 }, 1129 .hback_porch = { 59, 88, 117 }, 1130 .hsync_len = { 28, 42, 56 }, 1131 .vactive = { 1080, 1080, 1080 }, 1132 .vfront_porch = { 3, 8, 11 }, 1133 .vback_porch = { 5, 14, 19 }, 1134 .vsync_len = { 4, 14, 19 }, 1135 }; 1136 1137 static const struct panel_desc auo_g133han01 = { 1138 .timings = &auo_g133han01_timings, 1139 .num_timings = 1, 1140 .bpc = 8, 1141 .size = { 1142 .width = 293, 1143 .height = 165, 1144 }, 1145 .delay = { 1146 .prepare = 200, 1147 .enable = 50, 1148 .disable = 50, 1149 .unprepare = 1000, 1150 }, 1151 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1152 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1153 }; 1154 1155 static const struct display_timing auo_g156han04_timings = { 1156 .pixelclock = { 137000000, 141000000, 146000000 }, 1157 .hactive = { 1920, 1920, 1920 }, 1158 .hfront_porch = { 60, 60, 60 }, 1159 .hback_porch = { 90, 92, 111 }, 1160 .hsync_len = { 32, 32, 32 }, 1161 .vactive = { 1080, 1080, 1080 }, 1162 .vfront_porch = { 12, 12, 12 }, 1163 .vback_porch = { 24, 36, 56 }, 1164 .vsync_len = { 8, 8, 8 }, 1165 }; 1166 1167 static const struct panel_desc auo_g156han04 = { 1168 .timings = &auo_g156han04_timings, 1169 .num_timings = 1, 1170 .bpc = 8, 1171 .size = { 1172 .width = 344, 1173 .height = 194, 1174 }, 1175 .delay = { 1176 .prepare = 50, /* T2 */ 1177 .enable = 200, /* T3 */ 1178 .disable = 110, /* T10 */ 1179 .unprepare = 1000, /* T13 */ 1180 }, 1181 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1182 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1183 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1184 }; 1185 1186 static const struct drm_display_mode auo_g156xtn01_mode = { 1187 .clock = 76000, 1188 .hdisplay = 1366, 1189 .hsync_start = 1366 + 33, 1190 .hsync_end = 1366 + 33 + 67, 1191 .htotal = 1560, 1192 .vdisplay = 768, 1193 .vsync_start = 768 + 4, 1194 .vsync_end = 768 + 4 + 4, 1195 .vtotal = 806, 1196 }; 1197 1198 static const struct panel_desc auo_g156xtn01 = { 1199 .modes = &auo_g156xtn01_mode, 1200 .num_modes = 1, 1201 .bpc = 8, 1202 .size = { 1203 .width = 344, 1204 .height = 194, 1205 }, 1206 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1207 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1208 }; 1209 1210 static const struct display_timing auo_g185han01_timings = { 1211 .pixelclock = { 120000000, 144000000, 175000000 }, 1212 .hactive = { 1920, 1920, 1920 }, 1213 .hfront_porch = { 36, 120, 148 }, 1214 .hback_porch = { 24, 88, 108 }, 1215 .hsync_len = { 20, 48, 64 }, 1216 .vactive = { 1080, 1080, 1080 }, 1217 .vfront_porch = { 6, 10, 40 }, 1218 .vback_porch = { 2, 5, 20 }, 1219 .vsync_len = { 2, 5, 20 }, 1220 }; 1221 1222 static const struct panel_desc auo_g185han01 = { 1223 .timings = &auo_g185han01_timings, 1224 .num_timings = 1, 1225 .bpc = 8, 1226 .size = { 1227 .width = 409, 1228 .height = 230, 1229 }, 1230 .delay = { 1231 .prepare = 50, 1232 .enable = 200, 1233 .disable = 110, 1234 .unprepare = 1000, 1235 }, 1236 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1237 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1238 }; 1239 1240 static const struct display_timing auo_g190ean01_timings = { 1241 .pixelclock = { 90000000, 108000000, 135000000 }, 1242 .hactive = { 1280, 1280, 1280 }, 1243 .hfront_porch = { 126, 184, 1266 }, 1244 .hback_porch = { 84, 122, 844 }, 1245 .hsync_len = { 70, 102, 704 }, 1246 .vactive = { 1024, 1024, 1024 }, 1247 .vfront_porch = { 4, 26, 76 }, 1248 .vback_porch = { 2, 8, 25 }, 1249 .vsync_len = { 2, 8, 25 }, 1250 }; 1251 1252 static const struct panel_desc auo_g190ean01 = { 1253 .timings = &auo_g190ean01_timings, 1254 .num_timings = 1, 1255 .bpc = 8, 1256 .size = { 1257 .width = 376, 1258 .height = 301, 1259 }, 1260 .delay = { 1261 .prepare = 50, 1262 .enable = 200, 1263 .disable = 110, 1264 .unprepare = 1000, 1265 }, 1266 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1267 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1268 }; 1269 1270 static const struct display_timing auo_p320hvn03_timings = { 1271 .pixelclock = { 106000000, 148500000, 164000000 }, 1272 .hactive = { 1920, 1920, 1920 }, 1273 .hfront_porch = { 25, 50, 130 }, 1274 .hback_porch = { 25, 50, 130 }, 1275 .hsync_len = { 20, 40, 105 }, 1276 .vactive = { 1080, 1080, 1080 }, 1277 .vfront_porch = { 8, 17, 150 }, 1278 .vback_porch = { 8, 17, 150 }, 1279 .vsync_len = { 4, 11, 100 }, 1280 }; 1281 1282 static const struct panel_desc auo_p320hvn03 = { 1283 .timings = &auo_p320hvn03_timings, 1284 .num_timings = 1, 1285 .bpc = 8, 1286 .size = { 1287 .width = 698, 1288 .height = 393, 1289 }, 1290 .delay = { 1291 .prepare = 1, 1292 .enable = 450, 1293 .unprepare = 500, 1294 }, 1295 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1296 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1297 }; 1298 1299 static const struct drm_display_mode auo_t215hvn01_mode = { 1300 .clock = 148800, 1301 .hdisplay = 1920, 1302 .hsync_start = 1920 + 88, 1303 .hsync_end = 1920 + 88 + 44, 1304 .htotal = 1920 + 88 + 44 + 148, 1305 .vdisplay = 1080, 1306 .vsync_start = 1080 + 4, 1307 .vsync_end = 1080 + 4 + 5, 1308 .vtotal = 1080 + 4 + 5 + 36, 1309 }; 1310 1311 static const struct panel_desc auo_t215hvn01 = { 1312 .modes = &auo_t215hvn01_mode, 1313 .num_modes = 1, 1314 .bpc = 8, 1315 .size = { 1316 .width = 430, 1317 .height = 270, 1318 }, 1319 .delay = { 1320 .disable = 5, 1321 .unprepare = 1000, 1322 }, 1323 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1324 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1325 }; 1326 1327 static const struct drm_display_mode avic_tm070ddh03_mode = { 1328 .clock = 51200, 1329 .hdisplay = 1024, 1330 .hsync_start = 1024 + 160, 1331 .hsync_end = 1024 + 160 + 4, 1332 .htotal = 1024 + 160 + 4 + 156, 1333 .vdisplay = 600, 1334 .vsync_start = 600 + 17, 1335 .vsync_end = 600 + 17 + 1, 1336 .vtotal = 600 + 17 + 1 + 17, 1337 }; 1338 1339 static const struct panel_desc avic_tm070ddh03 = { 1340 .modes = &avic_tm070ddh03_mode, 1341 .num_modes = 1, 1342 .bpc = 8, 1343 .size = { 1344 .width = 154, 1345 .height = 90, 1346 }, 1347 .delay = { 1348 .prepare = 20, 1349 .enable = 200, 1350 .disable = 200, 1351 }, 1352 }; 1353 1354 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1355 .clock = 30000, 1356 .hdisplay = 800, 1357 .hsync_start = 800 + 40, 1358 .hsync_end = 800 + 40 + 48, 1359 .htotal = 800 + 40 + 48 + 40, 1360 .vdisplay = 480, 1361 .vsync_start = 480 + 13, 1362 .vsync_end = 480 + 13 + 3, 1363 .vtotal = 480 + 13 + 3 + 29, 1364 }; 1365 1366 static const struct panel_desc bananapi_s070wv20_ct16 = { 1367 .modes = &bananapi_s070wv20_ct16_mode, 1368 .num_modes = 1, 1369 .bpc = 6, 1370 .size = { 1371 .width = 154, 1372 .height = 86, 1373 }, 1374 }; 1375 1376 static const struct display_timing boe_av101hdt_a10_timing = { 1377 .pixelclock = { 74210000, 75330000, 76780000, }, 1378 .hactive = { 1280, 1280, 1280, }, 1379 .hfront_porch = { 10, 42, 33, }, 1380 .hback_porch = { 10, 18, 33, }, 1381 .hsync_len = { 30, 10, 30, }, 1382 .vactive = { 720, 720, 720, }, 1383 .vfront_porch = { 200, 183, 200, }, 1384 .vback_porch = { 8, 8, 8, }, 1385 .vsync_len = { 2, 19, 2, }, 1386 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1387 }; 1388 1389 static const struct panel_desc boe_av101hdt_a10 = { 1390 .timings = &boe_av101hdt_a10_timing, 1391 .num_timings = 1, 1392 .bpc = 8, 1393 .size = { 1394 .width = 224, 1395 .height = 126, 1396 }, 1397 .delay = { 1398 .enable = 50, 1399 .disable = 50, 1400 }, 1401 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1402 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1403 }; 1404 1405 static const struct display_timing boe_av123z7m_n17_timing = { 1406 .pixelclock = { 86600000, 88000000, 90800000, }, 1407 .hactive = { 1920, 1920, 1920, }, 1408 .hfront_porch = { 10, 10, 10, }, 1409 .hback_porch = { 10, 10, 10, }, 1410 .hsync_len = { 9, 12, 25, }, 1411 .vactive = { 720, 720, 720, }, 1412 .vfront_porch = { 7, 10, 13, }, 1413 .vback_porch = { 7, 10, 13, }, 1414 .vsync_len = { 7, 11, 14, }, 1415 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1416 }; 1417 1418 static const struct panel_desc boe_av123z7m_n17 = { 1419 .timings = &boe_av123z7m_n17_timing, 1420 .bpc = 8, 1421 .num_timings = 1, 1422 .size = { 1423 .width = 292, 1424 .height = 110, 1425 }, 1426 .delay = { 1427 .prepare = 50, 1428 .disable = 50, 1429 }, 1430 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1431 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1432 }; 1433 1434 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1435 .clock = 78945, 1436 .hdisplay = 1280, 1437 .hsync_start = 1280 + 0, 1438 .hsync_end = 1280 + 0 + 2, 1439 .htotal = 1280 + 62 + 0 + 2, 1440 .vdisplay = 800, 1441 .vsync_start = 800 + 8, 1442 .vsync_end = 800 + 8 + 2, 1443 .vtotal = 800 + 6 + 8 + 2, 1444 }; 1445 1446 static const struct panel_desc boe_bp082wx1_100 = { 1447 .modes = &boe_bp101wx1_100_mode, 1448 .num_modes = 1, 1449 .bpc = 8, 1450 .size = { 1451 .width = 177, 1452 .height = 110, 1453 }, 1454 .delay = { 1455 .enable = 50, 1456 .disable = 50, 1457 }, 1458 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1459 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1460 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1461 }; 1462 1463 static const struct panel_desc boe_bp101wx1_100 = { 1464 .modes = &boe_bp101wx1_100_mode, 1465 .num_modes = 1, 1466 .bpc = 8, 1467 .size = { 1468 .width = 217, 1469 .height = 136, 1470 }, 1471 .delay = { 1472 .enable = 50, 1473 .disable = 50, 1474 }, 1475 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1476 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1477 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1478 }; 1479 1480 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1481 .pixelclock = { 69922000, 71000000, 72293000 }, 1482 .hactive = { 1280, 1280, 1280 }, 1483 .hfront_porch = { 48, 48, 48 }, 1484 .hback_porch = { 80, 80, 80 }, 1485 .hsync_len = { 32, 32, 32 }, 1486 .vactive = { 800, 800, 800 }, 1487 .vfront_porch = { 3, 3, 3 }, 1488 .vback_porch = { 14, 14, 14 }, 1489 .vsync_len = { 6, 6, 6 }, 1490 }; 1491 1492 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1493 .timings = &boe_ev121wxm_n10_1850_timing, 1494 .num_timings = 1, 1495 .bpc = 8, 1496 .size = { 1497 .width = 261, 1498 .height = 163, 1499 }, 1500 .delay = { 1501 .prepare = 9, 1502 .enable = 300, 1503 .unprepare = 300, 1504 .disable = 560, 1505 }, 1506 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1507 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1508 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1509 }; 1510 1511 static const struct drm_display_mode boe_hv070wsa_mode = { 1512 .clock = 42105, 1513 .hdisplay = 1024, 1514 .hsync_start = 1024 + 30, 1515 .hsync_end = 1024 + 30 + 30, 1516 .htotal = 1024 + 30 + 30 + 30, 1517 .vdisplay = 600, 1518 .vsync_start = 600 + 10, 1519 .vsync_end = 600 + 10 + 10, 1520 .vtotal = 600 + 10 + 10 + 10, 1521 }; 1522 1523 static const struct panel_desc boe_hv070wsa = { 1524 .modes = &boe_hv070wsa_mode, 1525 .num_modes = 1, 1526 .bpc = 8, 1527 .size = { 1528 .width = 154, 1529 .height = 90, 1530 }, 1531 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1532 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1533 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1534 }; 1535 1536 static const struct display_timing cct_cmt430b19n00_timing = { 1537 .pixelclock = { 8000000, 9000000, 12000000 }, 1538 .hactive = { 480, 480, 480 }, 1539 .hfront_porch = { 2, 8, 75 }, 1540 .hback_porch = { 3, 43, 43 }, 1541 .hsync_len = { 2, 4, 75 }, 1542 .vactive = { 272, 272, 272 }, 1543 .vfront_porch = { 2, 8, 37 }, 1544 .vback_porch = { 2, 12, 12 }, 1545 .vsync_len = { 2, 4, 37 }, 1546 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1547 }; 1548 1549 static const struct panel_desc cct_cmt430b19n00 = { 1550 .timings = &cct_cmt430b19n00_timing, 1551 .num_timings = 1, 1552 .bpc = 8, 1553 .size = { 1554 .width = 95, 1555 .height = 53, 1556 }, 1557 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1558 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1559 .connector_type = DRM_MODE_CONNECTOR_DPI, 1560 }; 1561 1562 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1563 .clock = 9000, 1564 .hdisplay = 480, 1565 .hsync_start = 480 + 5, 1566 .hsync_end = 480 + 5 + 5, 1567 .htotal = 480 + 5 + 5 + 40, 1568 .vdisplay = 272, 1569 .vsync_start = 272 + 8, 1570 .vsync_end = 272 + 8 + 8, 1571 .vtotal = 272 + 8 + 8 + 8, 1572 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1573 }; 1574 1575 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1576 .modes = &cdtech_s043wq26h_ct7_mode, 1577 .num_modes = 1, 1578 .bpc = 8, 1579 .size = { 1580 .width = 95, 1581 .height = 54, 1582 }, 1583 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1584 }; 1585 1586 /* S070PWS19HP-FC21 2017/04/22 */ 1587 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1588 .clock = 51200, 1589 .hdisplay = 1024, 1590 .hsync_start = 1024 + 160, 1591 .hsync_end = 1024 + 160 + 20, 1592 .htotal = 1024 + 160 + 20 + 140, 1593 .vdisplay = 600, 1594 .vsync_start = 600 + 12, 1595 .vsync_end = 600 + 12 + 3, 1596 .vtotal = 600 + 12 + 3 + 20, 1597 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1598 }; 1599 1600 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1601 .modes = &cdtech_s070pws19hp_fc21_mode, 1602 .num_modes = 1, 1603 .bpc = 6, 1604 .size = { 1605 .width = 154, 1606 .height = 86, 1607 }, 1608 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1609 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1610 .connector_type = DRM_MODE_CONNECTOR_DPI, 1611 }; 1612 1613 /* S070SWV29HG-DC44 2017/09/21 */ 1614 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1615 .clock = 33300, 1616 .hdisplay = 800, 1617 .hsync_start = 800 + 210, 1618 .hsync_end = 800 + 210 + 2, 1619 .htotal = 800 + 210 + 2 + 44, 1620 .vdisplay = 480, 1621 .vsync_start = 480 + 22, 1622 .vsync_end = 480 + 22 + 2, 1623 .vtotal = 480 + 22 + 2 + 21, 1624 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1625 }; 1626 1627 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1628 .modes = &cdtech_s070swv29hg_dc44_mode, 1629 .num_modes = 1, 1630 .bpc = 6, 1631 .size = { 1632 .width = 154, 1633 .height = 86, 1634 }, 1635 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1636 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1637 .connector_type = DRM_MODE_CONNECTOR_DPI, 1638 }; 1639 1640 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1641 .clock = 35000, 1642 .hdisplay = 800, 1643 .hsync_start = 800 + 40, 1644 .hsync_end = 800 + 40 + 40, 1645 .htotal = 800 + 40 + 40 + 48, 1646 .vdisplay = 480, 1647 .vsync_start = 480 + 29, 1648 .vsync_end = 480 + 29 + 13, 1649 .vtotal = 480 + 29 + 13 + 3, 1650 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1651 }; 1652 1653 static const struct panel_desc cdtech_s070wv95_ct16 = { 1654 .modes = &cdtech_s070wv95_ct16_mode, 1655 .num_modes = 1, 1656 .bpc = 8, 1657 .size = { 1658 .width = 154, 1659 .height = 85, 1660 }, 1661 }; 1662 1663 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1664 .pixelclock = { 68900000, 71100000, 73400000 }, 1665 .hactive = { 1280, 1280, 1280 }, 1666 .hfront_porch = { 65, 80, 95 }, 1667 .hback_porch = { 64, 79, 94 }, 1668 .hsync_len = { 1, 1, 1 }, 1669 .vactive = { 800, 800, 800 }, 1670 .vfront_porch = { 7, 11, 14 }, 1671 .vback_porch = { 7, 11, 14 }, 1672 .vsync_len = { 1, 1, 1 }, 1673 .flags = DISPLAY_FLAGS_DE_HIGH, 1674 }; 1675 1676 static const struct panel_desc chefree_ch101olhlwh_002 = { 1677 .timings = &chefree_ch101olhlwh_002_timing, 1678 .num_timings = 1, 1679 .bpc = 8, 1680 .size = { 1681 .width = 217, 1682 .height = 135, 1683 }, 1684 .delay = { 1685 .enable = 200, 1686 .disable = 200, 1687 }, 1688 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1689 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1690 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1691 }; 1692 1693 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1694 .clock = 66770, 1695 .hdisplay = 800, 1696 .hsync_start = 800 + 49, 1697 .hsync_end = 800 + 49 + 33, 1698 .htotal = 800 + 49 + 33 + 17, 1699 .vdisplay = 1280, 1700 .vsync_start = 1280 + 1, 1701 .vsync_end = 1280 + 1 + 7, 1702 .vtotal = 1280 + 1 + 7 + 15, 1703 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1704 }; 1705 1706 static const struct panel_desc chunghwa_claa070wp03xg = { 1707 .modes = &chunghwa_claa070wp03xg_mode, 1708 .num_modes = 1, 1709 .bpc = 6, 1710 .size = { 1711 .width = 94, 1712 .height = 150, 1713 }, 1714 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1715 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1716 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1717 }; 1718 1719 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1720 .clock = 72070, 1721 .hdisplay = 1366, 1722 .hsync_start = 1366 + 58, 1723 .hsync_end = 1366 + 58 + 58, 1724 .htotal = 1366 + 58 + 58 + 58, 1725 .vdisplay = 768, 1726 .vsync_start = 768 + 4, 1727 .vsync_end = 768 + 4 + 4, 1728 .vtotal = 768 + 4 + 4 + 4, 1729 }; 1730 1731 static const struct panel_desc chunghwa_claa101wa01a = { 1732 .modes = &chunghwa_claa101wa01a_mode, 1733 .num_modes = 1, 1734 .bpc = 6, 1735 .size = { 1736 .width = 220, 1737 .height = 120, 1738 }, 1739 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1740 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1741 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1742 }; 1743 1744 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1745 .clock = 69300, 1746 .hdisplay = 1366, 1747 .hsync_start = 1366 + 48, 1748 .hsync_end = 1366 + 48 + 32, 1749 .htotal = 1366 + 48 + 32 + 20, 1750 .vdisplay = 768, 1751 .vsync_start = 768 + 16, 1752 .vsync_end = 768 + 16 + 8, 1753 .vtotal = 768 + 16 + 8 + 16, 1754 }; 1755 1756 static const struct panel_desc chunghwa_claa101wb01 = { 1757 .modes = &chunghwa_claa101wb01_mode, 1758 .num_modes = 1, 1759 .bpc = 6, 1760 .size = { 1761 .width = 223, 1762 .height = 125, 1763 }, 1764 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1765 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1766 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1767 }; 1768 1769 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1770 .pixelclock = { 5000000, 9000000, 12000000 }, 1771 .hactive = { 480, 480, 480 }, 1772 .hfront_porch = { 12, 12, 12 }, 1773 .hback_porch = { 12, 12, 12 }, 1774 .hsync_len = { 21, 21, 21 }, 1775 .vactive = { 272, 272, 272 }, 1776 .vfront_porch = { 4, 4, 4 }, 1777 .vback_porch = { 4, 4, 4 }, 1778 .vsync_len = { 8, 8, 8 }, 1779 }; 1780 1781 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1782 .timings = &dataimage_fg040346dsswbg04_timing, 1783 .num_timings = 1, 1784 .bpc = 8, 1785 .size = { 1786 .width = 95, 1787 .height = 54, 1788 }, 1789 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1790 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1791 .connector_type = DRM_MODE_CONNECTOR_DPI, 1792 }; 1793 1794 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1795 .pixelclock = { 68900000, 71110000, 73400000 }, 1796 .hactive = { 1280, 1280, 1280 }, 1797 .vactive = { 800, 800, 800 }, 1798 .hback_porch = { 100, 100, 100 }, 1799 .hfront_porch = { 100, 100, 100 }, 1800 .vback_porch = { 5, 5, 5 }, 1801 .vfront_porch = { 5, 5, 5 }, 1802 .hsync_len = { 24, 24, 24 }, 1803 .vsync_len = { 3, 3, 3 }, 1804 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1805 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1806 }; 1807 1808 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1809 .timings = &dataimage_fg1001l0dsswmg01_timing, 1810 .num_timings = 1, 1811 .bpc = 8, 1812 .size = { 1813 .width = 217, 1814 .height = 136, 1815 }, 1816 }; 1817 1818 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1819 .clock = 33260, 1820 .hdisplay = 800, 1821 .hsync_start = 800 + 40, 1822 .hsync_end = 800 + 40 + 128, 1823 .htotal = 800 + 40 + 128 + 88, 1824 .vdisplay = 480, 1825 .vsync_start = 480 + 10, 1826 .vsync_end = 480 + 10 + 2, 1827 .vtotal = 480 + 10 + 2 + 33, 1828 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1829 }; 1830 1831 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1832 .modes = &dataimage_scf0700c48ggu18_mode, 1833 .num_modes = 1, 1834 .bpc = 8, 1835 .size = { 1836 .width = 152, 1837 .height = 91, 1838 }, 1839 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1840 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1841 }; 1842 1843 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1844 .pixelclock = { 45000000, 51200000, 57000000 }, 1845 .hactive = { 1024, 1024, 1024 }, 1846 .hfront_porch = { 100, 106, 113 }, 1847 .hback_porch = { 100, 106, 113 }, 1848 .hsync_len = { 100, 108, 114 }, 1849 .vactive = { 600, 600, 600 }, 1850 .vfront_porch = { 8, 11, 15 }, 1851 .vback_porch = { 8, 11, 15 }, 1852 .vsync_len = { 9, 13, 15 }, 1853 .flags = DISPLAY_FLAGS_DE_HIGH, 1854 }; 1855 1856 static const struct panel_desc dlc_dlc0700yzg_1 = { 1857 .timings = &dlc_dlc0700yzg_1_timing, 1858 .num_timings = 1, 1859 .bpc = 6, 1860 .size = { 1861 .width = 154, 1862 .height = 86, 1863 }, 1864 .delay = { 1865 .prepare = 30, 1866 .enable = 200, 1867 .disable = 200, 1868 }, 1869 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1870 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1871 }; 1872 1873 static const struct display_timing dlc_dlc1010gig_timing = { 1874 .pixelclock = { 68900000, 71100000, 73400000 }, 1875 .hactive = { 1280, 1280, 1280 }, 1876 .hfront_porch = { 43, 53, 63 }, 1877 .hback_porch = { 43, 53, 63 }, 1878 .hsync_len = { 44, 54, 64 }, 1879 .vactive = { 800, 800, 800 }, 1880 .vfront_porch = { 5, 8, 11 }, 1881 .vback_porch = { 5, 8, 11 }, 1882 .vsync_len = { 5, 7, 11 }, 1883 .flags = DISPLAY_FLAGS_DE_HIGH, 1884 }; 1885 1886 static const struct panel_desc dlc_dlc1010gig = { 1887 .timings = &dlc_dlc1010gig_timing, 1888 .num_timings = 1, 1889 .bpc = 8, 1890 .size = { 1891 .width = 216, 1892 .height = 135, 1893 }, 1894 .delay = { 1895 .prepare = 60, 1896 .enable = 150, 1897 .disable = 100, 1898 .unprepare = 60, 1899 }, 1900 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1901 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1902 }; 1903 1904 static const struct drm_display_mode edt_et035012dm6_mode = { 1905 .clock = 6500, 1906 .hdisplay = 320, 1907 .hsync_start = 320 + 20, 1908 .hsync_end = 320 + 20 + 30, 1909 .htotal = 320 + 20 + 68, 1910 .vdisplay = 240, 1911 .vsync_start = 240 + 4, 1912 .vsync_end = 240 + 4 + 4, 1913 .vtotal = 240 + 4 + 4 + 14, 1914 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1915 }; 1916 1917 static const struct panel_desc edt_et035012dm6 = { 1918 .modes = &edt_et035012dm6_mode, 1919 .num_modes = 1, 1920 .bpc = 8, 1921 .size = { 1922 .width = 70, 1923 .height = 52, 1924 }, 1925 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1926 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1927 }; 1928 1929 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1930 .clock = 6520, 1931 .hdisplay = 320, 1932 .hsync_start = 320 + 20, 1933 .hsync_end = 320 + 20 + 68, 1934 .htotal = 320 + 20 + 68, 1935 .vdisplay = 240, 1936 .vsync_start = 240 + 4, 1937 .vsync_end = 240 + 4 + 18, 1938 .vtotal = 240 + 4 + 18, 1939 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1940 }; 1941 1942 static const struct panel_desc edt_etm0350g0dh6 = { 1943 .modes = &edt_etm0350g0dh6_mode, 1944 .num_modes = 1, 1945 .bpc = 6, 1946 .size = { 1947 .width = 70, 1948 .height = 53, 1949 }, 1950 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1951 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1952 .connector_type = DRM_MODE_CONNECTOR_DPI, 1953 }; 1954 1955 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1956 .clock = 10870, 1957 .hdisplay = 480, 1958 .hsync_start = 480 + 8, 1959 .hsync_end = 480 + 8 + 4, 1960 .htotal = 480 + 8 + 4 + 41, 1961 1962 /* 1963 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1964 * fb_align 1965 */ 1966 1967 .vdisplay = 288, 1968 .vsync_start = 288 + 2, 1969 .vsync_end = 288 + 2 + 4, 1970 .vtotal = 288 + 2 + 4 + 10, 1971 }; 1972 1973 static const struct panel_desc edt_etm043080dh6gp = { 1974 .modes = &edt_etm043080dh6gp_mode, 1975 .num_modes = 1, 1976 .bpc = 8, 1977 .size = { 1978 .width = 100, 1979 .height = 65, 1980 }, 1981 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1982 .connector_type = DRM_MODE_CONNECTOR_DPI, 1983 }; 1984 1985 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1986 .clock = 9000, 1987 .hdisplay = 480, 1988 .hsync_start = 480 + 2, 1989 .hsync_end = 480 + 2 + 41, 1990 .htotal = 480 + 2 + 41 + 2, 1991 .vdisplay = 272, 1992 .vsync_start = 272 + 2, 1993 .vsync_end = 272 + 2 + 10, 1994 .vtotal = 272 + 2 + 10 + 2, 1995 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1996 }; 1997 1998 static const struct panel_desc edt_etm0430g0dh6 = { 1999 .modes = &edt_etm0430g0dh6_mode, 2000 .num_modes = 1, 2001 .bpc = 6, 2002 .size = { 2003 .width = 95, 2004 .height = 54, 2005 }, 2006 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2007 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2008 .connector_type = DRM_MODE_CONNECTOR_DPI, 2009 }; 2010 2011 static const struct drm_display_mode edt_et057090dhu_mode = { 2012 .clock = 25175, 2013 .hdisplay = 640, 2014 .hsync_start = 640 + 16, 2015 .hsync_end = 640 + 16 + 30, 2016 .htotal = 640 + 16 + 30 + 114, 2017 .vdisplay = 480, 2018 .vsync_start = 480 + 10, 2019 .vsync_end = 480 + 10 + 3, 2020 .vtotal = 480 + 10 + 3 + 32, 2021 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2022 }; 2023 2024 static const struct panel_desc edt_et057090dhu = { 2025 .modes = &edt_et057090dhu_mode, 2026 .num_modes = 1, 2027 .bpc = 6, 2028 .size = { 2029 .width = 115, 2030 .height = 86, 2031 }, 2032 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2033 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2034 .connector_type = DRM_MODE_CONNECTOR_DPI, 2035 }; 2036 2037 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2038 .clock = 33260, 2039 .hdisplay = 800, 2040 .hsync_start = 800 + 40, 2041 .hsync_end = 800 + 40 + 128, 2042 .htotal = 800 + 40 + 128 + 88, 2043 .vdisplay = 480, 2044 .vsync_start = 480 + 10, 2045 .vsync_end = 480 + 10 + 2, 2046 .vtotal = 480 + 10 + 2 + 33, 2047 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2048 }; 2049 2050 static const struct panel_desc edt_etm0700g0dh6 = { 2051 .modes = &edt_etm0700g0dh6_mode, 2052 .num_modes = 1, 2053 .bpc = 6, 2054 .size = { 2055 .width = 152, 2056 .height = 91, 2057 }, 2058 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2059 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2060 .connector_type = DRM_MODE_CONNECTOR_DPI, 2061 }; 2062 2063 static const struct panel_desc edt_etm0700g0bdh6 = { 2064 .modes = &edt_etm0700g0dh6_mode, 2065 .num_modes = 1, 2066 .bpc = 6, 2067 .size = { 2068 .width = 152, 2069 .height = 91, 2070 }, 2071 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2072 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2073 .connector_type = DRM_MODE_CONNECTOR_DPI, 2074 }; 2075 2076 static const struct display_timing edt_etml0700y5dha_timing = { 2077 .pixelclock = { 40800000, 51200000, 67200000 }, 2078 .hactive = { 1024, 1024, 1024 }, 2079 .hfront_porch = { 30, 106, 125 }, 2080 .hback_porch = { 30, 106, 125 }, 2081 .hsync_len = { 30, 108, 126 }, 2082 .vactive = { 600, 600, 600 }, 2083 .vfront_porch = { 3, 12, 67}, 2084 .vback_porch = { 3, 12, 67 }, 2085 .vsync_len = { 4, 11, 66 }, 2086 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2087 DISPLAY_FLAGS_DE_HIGH, 2088 }; 2089 2090 static const struct panel_desc edt_etml0700y5dha = { 2091 .timings = &edt_etml0700y5dha_timing, 2092 .num_timings = 1, 2093 .bpc = 8, 2094 .size = { 2095 .width = 155, 2096 .height = 86, 2097 }, 2098 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2099 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2100 }; 2101 2102 static const struct display_timing edt_etml1010g3dra_timing = { 2103 .pixelclock = { 66300000, 72400000, 78900000 }, 2104 .hactive = { 1280, 1280, 1280 }, 2105 .hfront_porch = { 12, 72, 132 }, 2106 .hback_porch = { 86, 86, 86 }, 2107 .hsync_len = { 2, 2, 2 }, 2108 .vactive = { 800, 800, 800 }, 2109 .vfront_porch = { 1, 15, 49 }, 2110 .vback_porch = { 21, 21, 21 }, 2111 .vsync_len = { 2, 2, 2 }, 2112 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2113 DISPLAY_FLAGS_DE_HIGH, 2114 }; 2115 2116 static const struct panel_desc edt_etml1010g3dra = { 2117 .timings = &edt_etml1010g3dra_timing, 2118 .num_timings = 1, 2119 .bpc = 8, 2120 .size = { 2121 .width = 216, 2122 .height = 135, 2123 }, 2124 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2125 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2126 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2127 }; 2128 2129 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2130 .clock = 25175, 2131 .hdisplay = 640, 2132 .hsync_start = 640, 2133 .hsync_end = 640 + 16, 2134 .htotal = 640 + 16 + 30 + 114, 2135 .vdisplay = 480, 2136 .vsync_start = 480 + 10, 2137 .vsync_end = 480 + 10 + 3, 2138 .vtotal = 480 + 10 + 3 + 35, 2139 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2140 }; 2141 2142 static const struct panel_desc edt_etmv570g2dhu = { 2143 .modes = &edt_etmv570g2dhu_mode, 2144 .num_modes = 1, 2145 .bpc = 6, 2146 .size = { 2147 .width = 115, 2148 .height = 86, 2149 }, 2150 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2151 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2152 .connector_type = DRM_MODE_CONNECTOR_DPI, 2153 }; 2154 2155 static const struct display_timing eink_vb3300_kca_timing = { 2156 .pixelclock = { 40000000, 40000000, 40000000 }, 2157 .hactive = { 334, 334, 334 }, 2158 .hfront_porch = { 1, 1, 1 }, 2159 .hback_porch = { 1, 1, 1 }, 2160 .hsync_len = { 1, 1, 1 }, 2161 .vactive = { 1405, 1405, 1405 }, 2162 .vfront_porch = { 1, 1, 1 }, 2163 .vback_porch = { 1, 1, 1 }, 2164 .vsync_len = { 1, 1, 1 }, 2165 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2166 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2167 }; 2168 2169 static const struct panel_desc eink_vb3300_kca = { 2170 .timings = &eink_vb3300_kca_timing, 2171 .num_timings = 1, 2172 .bpc = 6, 2173 .size = { 2174 .width = 157, 2175 .height = 209, 2176 }, 2177 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2178 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2179 .connector_type = DRM_MODE_CONNECTOR_DPI, 2180 }; 2181 2182 static const struct display_timing evervision_vgg644804_timing = { 2183 .pixelclock = { 25175000, 25175000, 25175000 }, 2184 .hactive = { 640, 640, 640 }, 2185 .hfront_porch = { 16, 16, 16 }, 2186 .hback_porch = { 82, 114, 170 }, 2187 .hsync_len = { 5, 30, 30 }, 2188 .vactive = { 480, 480, 480 }, 2189 .vfront_porch = { 10, 10, 10 }, 2190 .vback_porch = { 30, 32, 34 }, 2191 .vsync_len = { 1, 3, 5 }, 2192 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2193 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2194 DISPLAY_FLAGS_SYNC_POSEDGE, 2195 }; 2196 2197 static const struct panel_desc evervision_vgg644804 = { 2198 .timings = &evervision_vgg644804_timing, 2199 .num_timings = 1, 2200 .bpc = 8, 2201 .size = { 2202 .width = 115, 2203 .height = 86, 2204 }, 2205 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2206 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2207 }; 2208 2209 static const struct display_timing evervision_vgg804821_timing = { 2210 .pixelclock = { 27600000, 33300000, 50000000 }, 2211 .hactive = { 800, 800, 800 }, 2212 .hfront_porch = { 40, 66, 70 }, 2213 .hback_porch = { 40, 67, 70 }, 2214 .hsync_len = { 40, 67, 70 }, 2215 .vactive = { 480, 480, 480 }, 2216 .vfront_porch = { 6, 10, 10 }, 2217 .vback_porch = { 7, 11, 11 }, 2218 .vsync_len = { 7, 11, 11 }, 2219 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2220 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2221 DISPLAY_FLAGS_SYNC_NEGEDGE, 2222 }; 2223 2224 static const struct panel_desc evervision_vgg804821 = { 2225 .timings = &evervision_vgg804821_timing, 2226 .num_timings = 1, 2227 .bpc = 8, 2228 .size = { 2229 .width = 108, 2230 .height = 64, 2231 }, 2232 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2233 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2234 }; 2235 2236 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2237 .clock = 32260, 2238 .hdisplay = 800, 2239 .hsync_start = 800 + 168, 2240 .hsync_end = 800 + 168 + 64, 2241 .htotal = 800 + 168 + 64 + 88, 2242 .vdisplay = 480, 2243 .vsync_start = 480 + 37, 2244 .vsync_end = 480 + 37 + 2, 2245 .vtotal = 480 + 37 + 2 + 8, 2246 }; 2247 2248 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2249 .modes = &foxlink_fl500wvr00_a0t_mode, 2250 .num_modes = 1, 2251 .bpc = 8, 2252 .size = { 2253 .width = 108, 2254 .height = 65, 2255 }, 2256 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2257 }; 2258 2259 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2260 { /* 60 Hz */ 2261 .clock = 6000, 2262 .hdisplay = 320, 2263 .hsync_start = 320 + 44, 2264 .hsync_end = 320 + 44 + 16, 2265 .htotal = 320 + 44 + 16 + 20, 2266 .vdisplay = 240, 2267 .vsync_start = 240 + 2, 2268 .vsync_end = 240 + 2 + 6, 2269 .vtotal = 240 + 2 + 6 + 2, 2270 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2271 }, 2272 { /* 50 Hz */ 2273 .clock = 5400, 2274 .hdisplay = 320, 2275 .hsync_start = 320 + 56, 2276 .hsync_end = 320 + 56 + 16, 2277 .htotal = 320 + 56 + 16 + 40, 2278 .vdisplay = 240, 2279 .vsync_start = 240 + 2, 2280 .vsync_end = 240 + 2 + 6, 2281 .vtotal = 240 + 2 + 6 + 2, 2282 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2283 }, 2284 }; 2285 2286 static const struct panel_desc frida_frd350h54004 = { 2287 .modes = frida_frd350h54004_modes, 2288 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2289 .bpc = 8, 2290 .size = { 2291 .width = 77, 2292 .height = 64, 2293 }, 2294 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2295 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2296 .connector_type = DRM_MODE_CONNECTOR_DPI, 2297 }; 2298 2299 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2300 .clock = 67185, 2301 .hdisplay = 800, 2302 .hsync_start = 800 + 20, 2303 .hsync_end = 800 + 20 + 24, 2304 .htotal = 800 + 20 + 24 + 20, 2305 .vdisplay = 1280, 2306 .vsync_start = 1280 + 4, 2307 .vsync_end = 1280 + 4 + 8, 2308 .vtotal = 1280 + 4 + 8 + 4, 2309 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2310 }; 2311 2312 static const struct panel_desc friendlyarm_hd702e = { 2313 .modes = &friendlyarm_hd702e_mode, 2314 .num_modes = 1, 2315 .size = { 2316 .width = 94, 2317 .height = 151, 2318 }, 2319 }; 2320 2321 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2322 .clock = 9000, 2323 .hdisplay = 480, 2324 .hsync_start = 480 + 5, 2325 .hsync_end = 480 + 5 + 1, 2326 .htotal = 480 + 5 + 1 + 40, 2327 .vdisplay = 272, 2328 .vsync_start = 272 + 8, 2329 .vsync_end = 272 + 8 + 1, 2330 .vtotal = 272 + 8 + 1 + 8, 2331 }; 2332 2333 static const struct panel_desc giantplus_gpg482739qs5 = { 2334 .modes = &giantplus_gpg482739qs5_mode, 2335 .num_modes = 1, 2336 .bpc = 8, 2337 .size = { 2338 .width = 95, 2339 .height = 54, 2340 }, 2341 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2342 }; 2343 2344 static const struct display_timing giantplus_gpm940b0_timing = { 2345 .pixelclock = { 13500000, 27000000, 27500000 }, 2346 .hactive = { 320, 320, 320 }, 2347 .hfront_porch = { 14, 686, 718 }, 2348 .hback_porch = { 50, 70, 255 }, 2349 .hsync_len = { 1, 1, 1 }, 2350 .vactive = { 240, 240, 240 }, 2351 .vfront_porch = { 1, 1, 179 }, 2352 .vback_porch = { 1, 21, 31 }, 2353 .vsync_len = { 1, 1, 6 }, 2354 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2355 }; 2356 2357 static const struct panel_desc giantplus_gpm940b0 = { 2358 .timings = &giantplus_gpm940b0_timing, 2359 .num_timings = 1, 2360 .bpc = 8, 2361 .size = { 2362 .width = 60, 2363 .height = 45, 2364 }, 2365 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2366 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2367 }; 2368 2369 static const struct display_timing hannstar_hsd070pww1_timing = { 2370 .pixelclock = { 64300000, 71100000, 82000000 }, 2371 .hactive = { 1280, 1280, 1280 }, 2372 .hfront_porch = { 1, 1, 10 }, 2373 .hback_porch = { 1, 1, 10 }, 2374 /* 2375 * According to the data sheet, the minimum horizontal blanking interval 2376 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2377 * minimum working horizontal blanking interval to be 60 clocks. 2378 */ 2379 .hsync_len = { 58, 158, 661 }, 2380 .vactive = { 800, 800, 800 }, 2381 .vfront_porch = { 1, 1, 10 }, 2382 .vback_porch = { 1, 1, 10 }, 2383 .vsync_len = { 1, 21, 203 }, 2384 .flags = DISPLAY_FLAGS_DE_HIGH, 2385 }; 2386 2387 static const struct panel_desc hannstar_hsd070pww1 = { 2388 .timings = &hannstar_hsd070pww1_timing, 2389 .num_timings = 1, 2390 .bpc = 6, 2391 .size = { 2392 .width = 151, 2393 .height = 94, 2394 }, 2395 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2396 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2397 }; 2398 2399 static const struct display_timing hannstar_hsd100pxn1_timing = { 2400 .pixelclock = { 55000000, 65000000, 75000000 }, 2401 .hactive = { 1024, 1024, 1024 }, 2402 .hfront_porch = { 40, 40, 40 }, 2403 .hback_porch = { 220, 220, 220 }, 2404 .hsync_len = { 20, 60, 100 }, 2405 .vactive = { 768, 768, 768 }, 2406 .vfront_porch = { 7, 7, 7 }, 2407 .vback_porch = { 21, 21, 21 }, 2408 .vsync_len = { 10, 10, 10 }, 2409 .flags = DISPLAY_FLAGS_DE_HIGH, 2410 }; 2411 2412 static const struct panel_desc hannstar_hsd100pxn1 = { 2413 .timings = &hannstar_hsd100pxn1_timing, 2414 .num_timings = 1, 2415 .bpc = 6, 2416 .size = { 2417 .width = 203, 2418 .height = 152, 2419 }, 2420 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2421 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2422 }; 2423 2424 static const struct display_timing hannstar_hsd101pww2_timing = { 2425 .pixelclock = { 64300000, 71100000, 82000000 }, 2426 .hactive = { 1280, 1280, 1280 }, 2427 .hfront_porch = { 1, 1, 10 }, 2428 .hback_porch = { 1, 1, 10 }, 2429 .hsync_len = { 58, 158, 661 }, 2430 .vactive = { 800, 800, 800 }, 2431 .vfront_porch = { 1, 1, 10 }, 2432 .vback_porch = { 1, 1, 10 }, 2433 .vsync_len = { 1, 21, 203 }, 2434 .flags = DISPLAY_FLAGS_DE_HIGH, 2435 }; 2436 2437 static const struct panel_desc hannstar_hsd101pww2 = { 2438 .timings = &hannstar_hsd101pww2_timing, 2439 .num_timings = 1, 2440 .bpc = 8, 2441 .size = { 2442 .width = 217, 2443 .height = 136, 2444 }, 2445 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2446 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2447 }; 2448 2449 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2450 .clock = 33333, 2451 .hdisplay = 800, 2452 .hsync_start = 800 + 85, 2453 .hsync_end = 800 + 85 + 86, 2454 .htotal = 800 + 85 + 86 + 85, 2455 .vdisplay = 480, 2456 .vsync_start = 480 + 16, 2457 .vsync_end = 480 + 16 + 13, 2458 .vtotal = 480 + 16 + 13 + 16, 2459 }; 2460 2461 static const struct panel_desc hitachi_tx23d38vm0caa = { 2462 .modes = &hitachi_tx23d38vm0caa_mode, 2463 .num_modes = 1, 2464 .bpc = 6, 2465 .size = { 2466 .width = 195, 2467 .height = 117, 2468 }, 2469 .delay = { 2470 .enable = 160, 2471 .disable = 160, 2472 }, 2473 }; 2474 2475 static const struct drm_display_mode innolux_at043tn24_mode = { 2476 .clock = 9000, 2477 .hdisplay = 480, 2478 .hsync_start = 480 + 2, 2479 .hsync_end = 480 + 2 + 41, 2480 .htotal = 480 + 2 + 41 + 2, 2481 .vdisplay = 272, 2482 .vsync_start = 272 + 2, 2483 .vsync_end = 272 + 2 + 10, 2484 .vtotal = 272 + 2 + 10 + 2, 2485 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2486 }; 2487 2488 static const struct panel_desc innolux_at043tn24 = { 2489 .modes = &innolux_at043tn24_mode, 2490 .num_modes = 1, 2491 .bpc = 8, 2492 .size = { 2493 .width = 95, 2494 .height = 54, 2495 }, 2496 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2497 .connector_type = DRM_MODE_CONNECTOR_DPI, 2498 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2499 }; 2500 2501 static const struct drm_display_mode innolux_at070tn92_mode = { 2502 .clock = 33333, 2503 .hdisplay = 800, 2504 .hsync_start = 800 + 210, 2505 .hsync_end = 800 + 210 + 20, 2506 .htotal = 800 + 210 + 20 + 46, 2507 .vdisplay = 480, 2508 .vsync_start = 480 + 22, 2509 .vsync_end = 480 + 22 + 10, 2510 .vtotal = 480 + 22 + 23 + 10, 2511 }; 2512 2513 static const struct panel_desc innolux_at070tn92 = { 2514 .modes = &innolux_at070tn92_mode, 2515 .num_modes = 1, 2516 .size = { 2517 .width = 154, 2518 .height = 86, 2519 }, 2520 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2521 }; 2522 2523 static const struct display_timing innolux_g070ace_l01_timing = { 2524 .pixelclock = { 25200000, 35000000, 35700000 }, 2525 .hactive = { 800, 800, 800 }, 2526 .hfront_porch = { 30, 32, 87 }, 2527 .hback_porch = { 30, 32, 87 }, 2528 .hsync_len = { 1, 1, 1 }, 2529 .vactive = { 480, 480, 480 }, 2530 .vfront_porch = { 3, 3, 3 }, 2531 .vback_porch = { 13, 13, 13 }, 2532 .vsync_len = { 1, 1, 4 }, 2533 .flags = DISPLAY_FLAGS_DE_HIGH, 2534 }; 2535 2536 static const struct panel_desc innolux_g070ace_l01 = { 2537 .timings = &innolux_g070ace_l01_timing, 2538 .num_timings = 1, 2539 .bpc = 8, 2540 .size = { 2541 .width = 152, 2542 .height = 91, 2543 }, 2544 .delay = { 2545 .prepare = 10, 2546 .enable = 50, 2547 .disable = 50, 2548 .unprepare = 500, 2549 }, 2550 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2551 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2552 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2553 }; 2554 2555 static const struct display_timing innolux_g070y2_l01_timing = { 2556 .pixelclock = { 28000000, 29500000, 32000000 }, 2557 .hactive = { 800, 800, 800 }, 2558 .hfront_porch = { 61, 91, 141 }, 2559 .hback_porch = { 60, 90, 140 }, 2560 .hsync_len = { 12, 12, 12 }, 2561 .vactive = { 480, 480, 480 }, 2562 .vfront_porch = { 4, 9, 30 }, 2563 .vback_porch = { 4, 8, 28 }, 2564 .vsync_len = { 2, 2, 2 }, 2565 .flags = DISPLAY_FLAGS_DE_HIGH, 2566 }; 2567 2568 static const struct panel_desc innolux_g070y2_l01 = { 2569 .timings = &innolux_g070y2_l01_timing, 2570 .num_timings = 1, 2571 .bpc = 8, 2572 .size = { 2573 .width = 152, 2574 .height = 91, 2575 }, 2576 .delay = { 2577 .prepare = 10, 2578 .enable = 100, 2579 .disable = 100, 2580 .unprepare = 800, 2581 }, 2582 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2583 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2584 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2585 }; 2586 2587 static const struct display_timing innolux_g070ace_lh3_timing = { 2588 .pixelclock = { 25200000, 25400000, 35700000 }, 2589 .hactive = { 800, 800, 800 }, 2590 .hfront_porch = { 30, 32, 87 }, 2591 .hback_porch = { 29, 31, 86 }, 2592 .hsync_len = { 1, 1, 1 }, 2593 .vactive = { 480, 480, 480 }, 2594 .vfront_porch = { 4, 5, 65 }, 2595 .vback_porch = { 3, 4, 65 }, 2596 .vsync_len = { 1, 1, 1 }, 2597 .flags = DISPLAY_FLAGS_DE_HIGH, 2598 }; 2599 2600 static const struct panel_desc innolux_g070ace_lh3 = { 2601 .timings = &innolux_g070ace_lh3_timing, 2602 .num_timings = 1, 2603 .bpc = 8, 2604 .size = { 2605 .width = 152, 2606 .height = 91, 2607 }, 2608 .delay = { 2609 .prepare = 10, 2610 .enable = 450, 2611 .disable = 200, 2612 .unprepare = 510, 2613 }, 2614 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2615 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2616 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2617 }; 2618 2619 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2620 .clock = 33333, 2621 .hdisplay = 800, 2622 .hsync_start = 800 + 210, 2623 .hsync_end = 800 + 210 + 20, 2624 .htotal = 800 + 210 + 20 + 46, 2625 .vdisplay = 480, 2626 .vsync_start = 480 + 22, 2627 .vsync_end = 480 + 22 + 10, 2628 .vtotal = 480 + 22 + 23 + 10, 2629 }; 2630 2631 static const struct panel_desc innolux_g070y2_t02 = { 2632 .modes = &innolux_g070y2_t02_mode, 2633 .num_modes = 1, 2634 .bpc = 8, 2635 .size = { 2636 .width = 152, 2637 .height = 92, 2638 }, 2639 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2640 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2641 .connector_type = DRM_MODE_CONNECTOR_DPI, 2642 }; 2643 2644 static const struct display_timing innolux_g101ice_l01_timing = { 2645 .pixelclock = { 60400000, 71100000, 74700000 }, 2646 .hactive = { 1280, 1280, 1280 }, 2647 .hfront_porch = { 30, 60, 70 }, 2648 .hback_porch = { 30, 60, 70 }, 2649 .hsync_len = { 22, 40, 60 }, 2650 .vactive = { 800, 800, 800 }, 2651 .vfront_porch = { 3, 8, 14 }, 2652 .vback_porch = { 3, 8, 14 }, 2653 .vsync_len = { 4, 7, 12 }, 2654 .flags = DISPLAY_FLAGS_DE_HIGH, 2655 }; 2656 2657 static const struct panel_desc innolux_g101ice_l01 = { 2658 .timings = &innolux_g101ice_l01_timing, 2659 .num_timings = 1, 2660 .bpc = 8, 2661 .size = { 2662 .width = 217, 2663 .height = 135, 2664 }, 2665 .delay = { 2666 .enable = 200, 2667 .disable = 200, 2668 }, 2669 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2670 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2671 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2672 }; 2673 2674 static const struct display_timing innolux_g121i1_l01_timing = { 2675 .pixelclock = { 67450000, 71000000, 74550000 }, 2676 .hactive = { 1280, 1280, 1280 }, 2677 .hfront_porch = { 40, 80, 160 }, 2678 .hback_porch = { 39, 79, 159 }, 2679 .hsync_len = { 1, 1, 1 }, 2680 .vactive = { 800, 800, 800 }, 2681 .vfront_porch = { 5, 11, 100 }, 2682 .vback_porch = { 4, 11, 99 }, 2683 .vsync_len = { 1, 1, 1 }, 2684 }; 2685 2686 static const struct panel_desc innolux_g121i1_l01 = { 2687 .timings = &innolux_g121i1_l01_timing, 2688 .num_timings = 1, 2689 .bpc = 6, 2690 .size = { 2691 .width = 261, 2692 .height = 163, 2693 }, 2694 .delay = { 2695 .enable = 200, 2696 .disable = 20, 2697 }, 2698 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2699 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2700 }; 2701 2702 static const struct display_timing innolux_g121x1_l03_timings = { 2703 .pixelclock = { 57500000, 64900000, 74400000 }, 2704 .hactive = { 1024, 1024, 1024 }, 2705 .hfront_porch = { 90, 140, 190 }, 2706 .hback_porch = { 90, 140, 190 }, 2707 .hsync_len = { 36, 40, 60 }, 2708 .vactive = { 768, 768, 768 }, 2709 .vfront_porch = { 2, 15, 30 }, 2710 .vback_porch = { 2, 15, 30 }, 2711 .vsync_len = { 2, 8, 20 }, 2712 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2713 }; 2714 2715 static const struct panel_desc innolux_g121x1_l03 = { 2716 .timings = &innolux_g121x1_l03_timings, 2717 .num_timings = 1, 2718 .bpc = 6, 2719 .size = { 2720 .width = 246, 2721 .height = 185, 2722 }, 2723 .delay = { 2724 .enable = 200, 2725 .unprepare = 200, 2726 .disable = 400, 2727 }, 2728 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2729 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2730 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2731 }; 2732 2733 static const struct panel_desc innolux_g121xce_l01 = { 2734 .timings = &innolux_g121x1_l03_timings, 2735 .num_timings = 1, 2736 .bpc = 8, 2737 .size = { 2738 .width = 246, 2739 .height = 185, 2740 }, 2741 .delay = { 2742 .enable = 200, 2743 .unprepare = 200, 2744 .disable = 400, 2745 }, 2746 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2747 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2748 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2749 }; 2750 2751 static const struct display_timing innolux_g156hce_l01_timings = { 2752 .pixelclock = { 120000000, 141860000, 150000000 }, 2753 .hactive = { 1920, 1920, 1920 }, 2754 .hfront_porch = { 80, 90, 100 }, 2755 .hback_porch = { 80, 90, 100 }, 2756 .hsync_len = { 20, 30, 30 }, 2757 .vactive = { 1080, 1080, 1080 }, 2758 .vfront_porch = { 3, 10, 20 }, 2759 .vback_porch = { 3, 10, 20 }, 2760 .vsync_len = { 4, 10, 10 }, 2761 }; 2762 2763 static const struct panel_desc innolux_g156hce_l01 = { 2764 .timings = &innolux_g156hce_l01_timings, 2765 .num_timings = 1, 2766 .bpc = 8, 2767 .size = { 2768 .width = 344, 2769 .height = 194, 2770 }, 2771 .delay = { 2772 .prepare = 1, /* T1+T2 */ 2773 .enable = 450, /* T5 */ 2774 .disable = 200, /* T6 */ 2775 .unprepare = 10, /* T3+T7 */ 2776 }, 2777 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2778 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2779 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2780 }; 2781 2782 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2783 .clock = 69300, 2784 .hdisplay = 1366, 2785 .hsync_start = 1366 + 16, 2786 .hsync_end = 1366 + 16 + 34, 2787 .htotal = 1366 + 16 + 34 + 50, 2788 .vdisplay = 768, 2789 .vsync_start = 768 + 2, 2790 .vsync_end = 768 + 2 + 6, 2791 .vtotal = 768 + 2 + 6 + 12, 2792 }; 2793 2794 static const struct panel_desc innolux_n156bge_l21 = { 2795 .modes = &innolux_n156bge_l21_mode, 2796 .num_modes = 1, 2797 .bpc = 6, 2798 .size = { 2799 .width = 344, 2800 .height = 193, 2801 }, 2802 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2803 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2804 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2805 }; 2806 2807 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2808 .clock = 51501, 2809 .hdisplay = 1024, 2810 .hsync_start = 1024 + 128, 2811 .hsync_end = 1024 + 128 + 64, 2812 .htotal = 1024 + 128 + 64 + 128, 2813 .vdisplay = 600, 2814 .vsync_start = 600 + 16, 2815 .vsync_end = 600 + 16 + 4, 2816 .vtotal = 600 + 16 + 4 + 16, 2817 }; 2818 2819 static const struct panel_desc innolux_zj070na_01p = { 2820 .modes = &innolux_zj070na_01p_mode, 2821 .num_modes = 1, 2822 .bpc = 6, 2823 .size = { 2824 .width = 154, 2825 .height = 90, 2826 }, 2827 }; 2828 2829 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2830 .pixelclock = { 5580000, 5850000, 6200000 }, 2831 .hactive = { 320, 320, 320 }, 2832 .hfront_porch = { 30, 30, 30 }, 2833 .hback_porch = { 30, 30, 30 }, 2834 .hsync_len = { 1, 5, 17 }, 2835 .vactive = { 240, 240, 240 }, 2836 .vfront_porch = { 6, 6, 6 }, 2837 .vback_porch = { 5, 5, 5 }, 2838 .vsync_len = { 1, 2, 11 }, 2839 .flags = DISPLAY_FLAGS_DE_HIGH, 2840 }; 2841 2842 static const struct panel_desc koe_tx14d24vm1bpa = { 2843 .timings = &koe_tx14d24vm1bpa_timing, 2844 .num_timings = 1, 2845 .bpc = 6, 2846 .size = { 2847 .width = 115, 2848 .height = 86, 2849 }, 2850 }; 2851 2852 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2853 .pixelclock = { 151820000, 156720000, 159780000 }, 2854 .hactive = { 1920, 1920, 1920 }, 2855 .hfront_porch = { 105, 130, 142 }, 2856 .hback_porch = { 45, 70, 82 }, 2857 .hsync_len = { 30, 30, 30 }, 2858 .vactive = { 1200, 1200, 1200}, 2859 .vfront_porch = { 3, 5, 10 }, 2860 .vback_porch = { 2, 5, 10 }, 2861 .vsync_len = { 5, 5, 5 }, 2862 .flags = DISPLAY_FLAGS_DE_HIGH, 2863 }; 2864 2865 static const struct panel_desc koe_tx26d202vm0bwa = { 2866 .timings = &koe_tx26d202vm0bwa_timing, 2867 .num_timings = 1, 2868 .bpc = 8, 2869 .size = { 2870 .width = 217, 2871 .height = 136, 2872 }, 2873 .delay = { 2874 .prepare = 1000, 2875 .enable = 1000, 2876 .unprepare = 1000, 2877 .disable = 1000, 2878 }, 2879 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2880 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2881 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2882 }; 2883 2884 static const struct display_timing koe_tx31d200vm0baa_timing = { 2885 .pixelclock = { 39600000, 43200000, 48000000 }, 2886 .hactive = { 1280, 1280, 1280 }, 2887 .hfront_porch = { 16, 36, 56 }, 2888 .hback_porch = { 16, 36, 56 }, 2889 .hsync_len = { 8, 8, 8 }, 2890 .vactive = { 480, 480, 480 }, 2891 .vfront_porch = { 6, 21, 33 }, 2892 .vback_porch = { 6, 21, 33 }, 2893 .vsync_len = { 8, 8, 8 }, 2894 .flags = DISPLAY_FLAGS_DE_HIGH, 2895 }; 2896 2897 static const struct panel_desc koe_tx31d200vm0baa = { 2898 .timings = &koe_tx31d200vm0baa_timing, 2899 .num_timings = 1, 2900 .bpc = 6, 2901 .size = { 2902 .width = 292, 2903 .height = 109, 2904 }, 2905 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2906 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2907 }; 2908 2909 static const struct display_timing kyo_tcg121xglp_timing = { 2910 .pixelclock = { 52000000, 65000000, 71000000 }, 2911 .hactive = { 1024, 1024, 1024 }, 2912 .hfront_porch = { 2, 2, 2 }, 2913 .hback_porch = { 2, 2, 2 }, 2914 .hsync_len = { 86, 124, 244 }, 2915 .vactive = { 768, 768, 768 }, 2916 .vfront_porch = { 2, 2, 2 }, 2917 .vback_porch = { 2, 2, 2 }, 2918 .vsync_len = { 6, 34, 73 }, 2919 .flags = DISPLAY_FLAGS_DE_HIGH, 2920 }; 2921 2922 static const struct panel_desc kyo_tcg121xglp = { 2923 .timings = &kyo_tcg121xglp_timing, 2924 .num_timings = 1, 2925 .bpc = 8, 2926 .size = { 2927 .width = 246, 2928 .height = 184, 2929 }, 2930 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2931 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2932 }; 2933 2934 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2935 .clock = 7000, 2936 .hdisplay = 320, 2937 .hsync_start = 320 + 20, 2938 .hsync_end = 320 + 20 + 30, 2939 .htotal = 320 + 20 + 30 + 38, 2940 .vdisplay = 240, 2941 .vsync_start = 240 + 4, 2942 .vsync_end = 240 + 4 + 3, 2943 .vtotal = 240 + 4 + 3 + 15, 2944 }; 2945 2946 static const struct panel_desc lemaker_bl035_rgb_002 = { 2947 .modes = &lemaker_bl035_rgb_002_mode, 2948 .num_modes = 1, 2949 .size = { 2950 .width = 70, 2951 .height = 52, 2952 }, 2953 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2954 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2955 }; 2956 2957 static const struct display_timing lg_lb070wv8_timing = { 2958 .pixelclock = { 31950000, 33260000, 34600000 }, 2959 .hactive = { 800, 800, 800 }, 2960 .hfront_porch = { 88, 88, 88 }, 2961 .hback_porch = { 88, 88, 88 }, 2962 .hsync_len = { 80, 80, 80 }, 2963 .vactive = { 480, 480, 480 }, 2964 .vfront_porch = { 10, 10, 10 }, 2965 .vback_porch = { 10, 10, 10 }, 2966 .vsync_len = { 25, 25, 25 }, 2967 }; 2968 2969 static const struct panel_desc lg_lb070wv8 = { 2970 .timings = &lg_lb070wv8_timing, 2971 .num_timings = 1, 2972 .bpc = 8, 2973 .size = { 2974 .width = 151, 2975 .height = 91, 2976 }, 2977 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2978 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2979 }; 2980 2981 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 2982 .clock = 155127, 2983 .hdisplay = 1920, 2984 .hsync_start = 1920 + 128, 2985 .hsync_end = 1920 + 128 + 20, 2986 .htotal = 1920 + 128 + 20 + 12, 2987 .vdisplay = 1200, 2988 .vsync_start = 1200 + 19, 2989 .vsync_end = 1200 + 19 + 4, 2990 .vtotal = 1200 + 19 + 4 + 20, 2991 }; 2992 2993 static const struct panel_desc lincolntech_lcd185_101ct = { 2994 .modes = &lincolntech_lcd185_101ct_mode, 2995 .bpc = 8, 2996 .num_modes = 1, 2997 .size = { 2998 .width = 217, 2999 .height = 136, 3000 }, 3001 .delay = { 3002 .prepare = 50, 3003 .disable = 50, 3004 }, 3005 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3006 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3007 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3008 }; 3009 3010 static const struct display_timing logictechno_lt161010_2nh_timing = { 3011 .pixelclock = { 26400000, 33300000, 46800000 }, 3012 .hactive = { 800, 800, 800 }, 3013 .hfront_porch = { 16, 210, 354 }, 3014 .hback_porch = { 46, 46, 46 }, 3015 .hsync_len = { 1, 20, 40 }, 3016 .vactive = { 480, 480, 480 }, 3017 .vfront_porch = { 7, 22, 147 }, 3018 .vback_porch = { 23, 23, 23 }, 3019 .vsync_len = { 1, 10, 20 }, 3020 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3021 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3022 DISPLAY_FLAGS_SYNC_POSEDGE, 3023 }; 3024 3025 static const struct panel_desc logictechno_lt161010_2nh = { 3026 .timings = &logictechno_lt161010_2nh_timing, 3027 .num_timings = 1, 3028 .bpc = 6, 3029 .size = { 3030 .width = 154, 3031 .height = 86, 3032 }, 3033 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3034 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3035 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3036 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3037 .connector_type = DRM_MODE_CONNECTOR_DPI, 3038 }; 3039 3040 static const struct display_timing logictechno_lt170410_2whc_timing = { 3041 .pixelclock = { 68900000, 71100000, 73400000 }, 3042 .hactive = { 1280, 1280, 1280 }, 3043 .hfront_porch = { 23, 60, 71 }, 3044 .hback_porch = { 23, 60, 71 }, 3045 .hsync_len = { 15, 40, 47 }, 3046 .vactive = { 800, 800, 800 }, 3047 .vfront_porch = { 5, 7, 10 }, 3048 .vback_porch = { 5, 7, 10 }, 3049 .vsync_len = { 6, 9, 12 }, 3050 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3051 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3052 DISPLAY_FLAGS_SYNC_POSEDGE, 3053 }; 3054 3055 static const struct panel_desc logictechno_lt170410_2whc = { 3056 .timings = &logictechno_lt170410_2whc_timing, 3057 .num_timings = 1, 3058 .bpc = 8, 3059 .size = { 3060 .width = 217, 3061 .height = 136, 3062 }, 3063 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3064 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3065 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3066 }; 3067 3068 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3069 .clock = 33000, 3070 .hdisplay = 800, 3071 .hsync_start = 800 + 112, 3072 .hsync_end = 800 + 112 + 3, 3073 .htotal = 800 + 112 + 3 + 85, 3074 .vdisplay = 480, 3075 .vsync_start = 480 + 38, 3076 .vsync_end = 480 + 38 + 3, 3077 .vtotal = 480 + 38 + 3 + 29, 3078 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3079 }; 3080 3081 static const struct panel_desc logictechno_lttd800480070_l2rt = { 3082 .modes = &logictechno_lttd800480070_l2rt_mode, 3083 .num_modes = 1, 3084 .bpc = 8, 3085 .size = { 3086 .width = 154, 3087 .height = 86, 3088 }, 3089 .delay = { 3090 .prepare = 45, 3091 .enable = 100, 3092 .disable = 100, 3093 .unprepare = 45 3094 }, 3095 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3096 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3097 .connector_type = DRM_MODE_CONNECTOR_DPI, 3098 }; 3099 3100 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3101 .clock = 33000, 3102 .hdisplay = 800, 3103 .hsync_start = 800 + 154, 3104 .hsync_end = 800 + 154 + 3, 3105 .htotal = 800 + 154 + 3 + 43, 3106 .vdisplay = 480, 3107 .vsync_start = 480 + 47, 3108 .vsync_end = 480 + 47 + 3, 3109 .vtotal = 480 + 47 + 3 + 20, 3110 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3111 }; 3112 3113 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3114 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3115 .num_modes = 1, 3116 .bpc = 8, 3117 .size = { 3118 .width = 154, 3119 .height = 86, 3120 }, 3121 .delay = { 3122 .prepare = 45, 3123 .enable = 100, 3124 .disable = 100, 3125 .unprepare = 45 3126 }, 3127 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3128 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3129 .connector_type = DRM_MODE_CONNECTOR_DPI, 3130 }; 3131 3132 static const struct drm_display_mode logicpd_type_28_mode = { 3133 .clock = 9107, 3134 .hdisplay = 480, 3135 .hsync_start = 480 + 3, 3136 .hsync_end = 480 + 3 + 42, 3137 .htotal = 480 + 3 + 42 + 2, 3138 3139 .vdisplay = 272, 3140 .vsync_start = 272 + 2, 3141 .vsync_end = 272 + 2 + 11, 3142 .vtotal = 272 + 2 + 11 + 3, 3143 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3144 }; 3145 3146 static const struct panel_desc logicpd_type_28 = { 3147 .modes = &logicpd_type_28_mode, 3148 .num_modes = 1, 3149 .bpc = 8, 3150 .size = { 3151 .width = 105, 3152 .height = 67, 3153 }, 3154 .delay = { 3155 .prepare = 200, 3156 .enable = 200, 3157 .unprepare = 200, 3158 .disable = 200, 3159 }, 3160 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3161 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3162 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3163 .connector_type = DRM_MODE_CONNECTOR_DPI, 3164 }; 3165 3166 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3167 .clock = 150275, 3168 .hdisplay = 1920, 3169 .hsync_start = 1920 + 32, 3170 .hsync_end = 1920 + 32 + 52, 3171 .htotal = 1920 + 32 + 52 + 24, 3172 .vdisplay = 1200, 3173 .vsync_start = 1200 + 24, 3174 .vsync_end = 1200 + 24 + 8, 3175 .vtotal = 1200 + 24 + 8 + 3, 3176 }; 3177 3178 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3179 .modes = µtips_mf_101hiebcaf0_c_mode, 3180 .bpc = 8, 3181 .num_modes = 1, 3182 .size = { 3183 .width = 217, 3184 .height = 136, 3185 }, 3186 .delay = { 3187 .prepare = 50, 3188 .disable = 50, 3189 }, 3190 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3191 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3192 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3193 }; 3194 3195 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3196 .clock = 93301, 3197 .hdisplay = 1920, 3198 .hsync_start = 1920 + 72, 3199 .hsync_end = 1920 + 72 + 72, 3200 .htotal = 1920 + 72 + 72 + 72, 3201 .vdisplay = 720, 3202 .vsync_start = 720 + 3, 3203 .vsync_end = 720 + 3 + 3, 3204 .vtotal = 720 + 3 + 3 + 2, 3205 }; 3206 3207 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3208 .modes = µtips_mf_103hieb0ga0_mode, 3209 .bpc = 8, 3210 .num_modes = 1, 3211 .size = { 3212 .width = 244, 3213 .height = 92, 3214 }, 3215 .delay = { 3216 .prepare = 50, 3217 .disable = 50, 3218 }, 3219 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3220 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3221 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3222 }; 3223 3224 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3225 .clock = 30400, 3226 .hdisplay = 800, 3227 .hsync_start = 800 + 0, 3228 .hsync_end = 800 + 1, 3229 .htotal = 800 + 0 + 1 + 160, 3230 .vdisplay = 480, 3231 .vsync_start = 480 + 0, 3232 .vsync_end = 480 + 48 + 1, 3233 .vtotal = 480 + 48 + 1 + 0, 3234 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3235 }; 3236 3237 static const struct panel_desc mitsubishi_aa070mc01 = { 3238 .modes = &mitsubishi_aa070mc01_mode, 3239 .num_modes = 1, 3240 .bpc = 8, 3241 .size = { 3242 .width = 152, 3243 .height = 91, 3244 }, 3245 3246 .delay = { 3247 .enable = 200, 3248 .unprepare = 200, 3249 .disable = 400, 3250 }, 3251 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3252 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3253 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3254 }; 3255 3256 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3257 .clock = 56234, 3258 .hdisplay = 1024, 3259 .hsync_start = 1024 + 24, 3260 .hsync_end = 1024 + 24 + 63, 3261 .htotal = 1024 + 24 + 63 + 1, 3262 .vdisplay = 768, 3263 .vsync_start = 768 + 3, 3264 .vsync_end = 768 + 3 + 6, 3265 .vtotal = 768 + 3 + 6 + 1, 3266 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3267 }; 3268 3269 static const struct panel_desc mitsubishi_aa084xe01 = { 3270 .modes = &mitsubishi_aa084xe01_mode, 3271 .num_modes = 1, 3272 .bpc = 8, 3273 .size = { 3274 .width = 1024, 3275 .height = 768, 3276 }, 3277 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3278 .connector_type = DRM_MODE_CONNECTOR_DPI, 3279 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3280 }; 3281 3282 static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3283 .pixelclock = { 26400000, 33000000, 46800000 }, 3284 .hactive = { 800, 800, 800 }, 3285 .hfront_porch = { 16, 204, 354 }, 3286 .hback_porch = { 46, 46, 46 }, 3287 .hsync_len = { 1, 6, 40 }, 3288 .vactive = { 480, 480, 480 }, 3289 .vfront_porch = { 7, 22, 147 }, 3290 .vback_porch = { 23, 23, 23 }, 3291 .vsync_len = { 1, 3, 20 }, 3292 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3293 DISPLAY_FLAGS_DE_HIGH, 3294 }; 3295 3296 static const struct panel_desc multi_inno_mi0700a2t_30 = { 3297 .timings = &multi_inno_mi0700a2t_30_timing, 3298 .num_timings = 1, 3299 .bpc = 6, 3300 .size = { 3301 .width = 153, 3302 .height = 92, 3303 }, 3304 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3305 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3306 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3307 }; 3308 3309 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3310 .pixelclock = { 29000000, 33000000, 38000000 }, 3311 .hactive = { 800, 800, 800 }, 3312 .hfront_porch = { 180, 210, 240 }, 3313 .hback_porch = { 16, 16, 16 }, 3314 .hsync_len = { 30, 30, 30 }, 3315 .vactive = { 480, 480, 480 }, 3316 .vfront_porch = { 12, 22, 32 }, 3317 .vback_porch = { 10, 10, 10 }, 3318 .vsync_len = { 13, 13, 13 }, 3319 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3320 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3321 DISPLAY_FLAGS_SYNC_POSEDGE, 3322 }; 3323 3324 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3325 .timings = &multi_inno_mi0700s4t_6_timing, 3326 .num_timings = 1, 3327 .bpc = 8, 3328 .size = { 3329 .width = 154, 3330 .height = 86, 3331 }, 3332 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3333 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3334 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3335 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3336 .connector_type = DRM_MODE_CONNECTOR_DPI, 3337 }; 3338 3339 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3340 .pixelclock = { 32000000, 40000000, 50000000 }, 3341 .hactive = { 800, 800, 800 }, 3342 .hfront_porch = { 16, 210, 354 }, 3343 .hback_porch = { 6, 26, 45 }, 3344 .hsync_len = { 1, 20, 40 }, 3345 .vactive = { 600, 600, 600 }, 3346 .vfront_porch = { 1, 12, 77 }, 3347 .vback_porch = { 3, 13, 22 }, 3348 .vsync_len = { 1, 10, 20 }, 3349 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3350 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3351 DISPLAY_FLAGS_SYNC_POSEDGE, 3352 }; 3353 3354 static const struct panel_desc multi_inno_mi0800ft_9 = { 3355 .timings = &multi_inno_mi0800ft_9_timing, 3356 .num_timings = 1, 3357 .bpc = 8, 3358 .size = { 3359 .width = 162, 3360 .height = 122, 3361 }, 3362 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3363 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3364 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3365 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3366 .connector_type = DRM_MODE_CONNECTOR_DPI, 3367 }; 3368 3369 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3370 .pixelclock = { 68900000, 70000000, 73400000 }, 3371 .hactive = { 1280, 1280, 1280 }, 3372 .hfront_porch = { 30, 60, 71 }, 3373 .hback_porch = { 30, 60, 71 }, 3374 .hsync_len = { 10, 10, 48 }, 3375 .vactive = { 800, 800, 800 }, 3376 .vfront_porch = { 5, 10, 10 }, 3377 .vback_porch = { 5, 10, 10 }, 3378 .vsync_len = { 5, 6, 13 }, 3379 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3380 DISPLAY_FLAGS_DE_HIGH, 3381 }; 3382 3383 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3384 .timings = &multi_inno_mi1010ait_1cp_timing, 3385 .num_timings = 1, 3386 .bpc = 8, 3387 .size = { 3388 .width = 217, 3389 .height = 136, 3390 }, 3391 .delay = { 3392 .enable = 50, 3393 .disable = 50, 3394 }, 3395 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3396 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3397 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3398 }; 3399 3400 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3401 .pixelclock = { 40800000, 51200000, 67200000 }, 3402 .hactive = { 1024, 1024, 1024 }, 3403 .hfront_porch = { 30, 110, 130 }, 3404 .hback_porch = { 30, 110, 130 }, 3405 .hsync_len = { 30, 100, 116 }, 3406 .vactive = { 600, 600, 600 }, 3407 .vfront_porch = { 4, 13, 80 }, 3408 .vback_porch = { 4, 13, 80 }, 3409 .vsync_len = { 2, 9, 40 }, 3410 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3411 DISPLAY_FLAGS_DE_HIGH, 3412 }; 3413 3414 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3415 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3416 .num_timings = 1, 3417 .bpc = 6, 3418 .size = { 3419 .width = 260, 3420 .height = 162, 3421 }, 3422 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3423 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3424 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3425 }; 3426 3427 static const struct display_timing nec_nl12880bc20_05_timing = { 3428 .pixelclock = { 67000000, 71000000, 75000000 }, 3429 .hactive = { 1280, 1280, 1280 }, 3430 .hfront_porch = { 2, 30, 30 }, 3431 .hback_porch = { 6, 100, 100 }, 3432 .hsync_len = { 2, 30, 30 }, 3433 .vactive = { 800, 800, 800 }, 3434 .vfront_porch = { 5, 5, 5 }, 3435 .vback_porch = { 11, 11, 11 }, 3436 .vsync_len = { 7, 7, 7 }, 3437 }; 3438 3439 static const struct panel_desc nec_nl12880bc20_05 = { 3440 .timings = &nec_nl12880bc20_05_timing, 3441 .num_timings = 1, 3442 .bpc = 8, 3443 .size = { 3444 .width = 261, 3445 .height = 163, 3446 }, 3447 .delay = { 3448 .enable = 50, 3449 .disable = 50, 3450 }, 3451 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3452 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3453 }; 3454 3455 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3456 .clock = 10870, 3457 .hdisplay = 480, 3458 .hsync_start = 480 + 2, 3459 .hsync_end = 480 + 2 + 41, 3460 .htotal = 480 + 2 + 41 + 2, 3461 .vdisplay = 272, 3462 .vsync_start = 272 + 2, 3463 .vsync_end = 272 + 2 + 4, 3464 .vtotal = 272 + 2 + 4 + 2, 3465 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3466 }; 3467 3468 static const struct panel_desc nec_nl4827hc19_05b = { 3469 .modes = &nec_nl4827hc19_05b_mode, 3470 .num_modes = 1, 3471 .bpc = 8, 3472 .size = { 3473 .width = 95, 3474 .height = 54, 3475 }, 3476 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3477 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3478 }; 3479 3480 static const struct drm_display_mode netron_dy_e231732_mode = { 3481 .clock = 66000, 3482 .hdisplay = 1024, 3483 .hsync_start = 1024 + 160, 3484 .hsync_end = 1024 + 160 + 70, 3485 .htotal = 1024 + 160 + 70 + 90, 3486 .vdisplay = 600, 3487 .vsync_start = 600 + 127, 3488 .vsync_end = 600 + 127 + 20, 3489 .vtotal = 600 + 127 + 20 + 3, 3490 }; 3491 3492 static const struct panel_desc netron_dy_e231732 = { 3493 .modes = &netron_dy_e231732_mode, 3494 .num_modes = 1, 3495 .size = { 3496 .width = 154, 3497 .height = 87, 3498 }, 3499 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3500 }; 3501 3502 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3503 .clock = 9000, 3504 .hdisplay = 480, 3505 .hsync_start = 480 + 2, 3506 .hsync_end = 480 + 2 + 41, 3507 .htotal = 480 + 2 + 41 + 2, 3508 .vdisplay = 272, 3509 .vsync_start = 272 + 2, 3510 .vsync_end = 272 + 2 + 10, 3511 .vtotal = 272 + 2 + 10 + 2, 3512 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3513 }; 3514 3515 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3516 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3517 .num_modes = 1, 3518 .bpc = 8, 3519 .size = { 3520 .width = 95, 3521 .height = 54, 3522 }, 3523 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3524 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3525 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3526 .connector_type = DRM_MODE_CONNECTOR_DPI, 3527 }; 3528 3529 static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { 3530 .clock = 75400, 3531 .hdisplay = 1366, 3532 .hsync_start = 1366 + 14, 3533 .hsync_end = 1366 + 14 + 56, 3534 .htotal = 1366 + 14 + 56 + 64, 3535 .vdisplay = 768, 3536 .vsync_start = 768 + 1, 3537 .vsync_end = 768 + 1 + 3, 3538 .vtotal = 768 + 1 + 3 + 22, 3539 }; 3540 3541 static const struct panel_desc nlt_nl13676bc25_03f = { 3542 .modes = &nlt_nl13676bc25_03f_mode, 3543 .num_modes = 1, 3544 .bpc = 8, 3545 .size = { 3546 .width = 363, 3547 .height = 215, 3548 }, 3549 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3550 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3551 }; 3552 3553 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3554 .pixelclock = { 130000000, 148350000, 163000000 }, 3555 .hactive = { 1920, 1920, 1920 }, 3556 .hfront_porch = { 80, 100, 100 }, 3557 .hback_porch = { 100, 120, 120 }, 3558 .hsync_len = { 50, 60, 60 }, 3559 .vactive = { 1080, 1080, 1080 }, 3560 .vfront_porch = { 12, 30, 30 }, 3561 .vback_porch = { 4, 10, 10 }, 3562 .vsync_len = { 4, 5, 5 }, 3563 }; 3564 3565 static const struct panel_desc nlt_nl192108ac18_02d = { 3566 .timings = &nlt_nl192108ac18_02d_timing, 3567 .num_timings = 1, 3568 .bpc = 8, 3569 .size = { 3570 .width = 344, 3571 .height = 194, 3572 }, 3573 .delay = { 3574 .unprepare = 500, 3575 }, 3576 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3577 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3578 }; 3579 3580 static const struct drm_display_mode nvd_9128_mode = { 3581 .clock = 29500, 3582 .hdisplay = 800, 3583 .hsync_start = 800 + 130, 3584 .hsync_end = 800 + 130 + 98, 3585 .htotal = 800 + 0 + 130 + 98, 3586 .vdisplay = 480, 3587 .vsync_start = 480 + 10, 3588 .vsync_end = 480 + 10 + 50, 3589 .vtotal = 480 + 0 + 10 + 50, 3590 }; 3591 3592 static const struct panel_desc nvd_9128 = { 3593 .modes = &nvd_9128_mode, 3594 .num_modes = 1, 3595 .bpc = 8, 3596 .size = { 3597 .width = 156, 3598 .height = 88, 3599 }, 3600 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3601 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3602 }; 3603 3604 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3605 .pixelclock = { 30000000, 30000000, 40000000 }, 3606 .hactive = { 800, 800, 800 }, 3607 .hfront_porch = { 40, 40, 40 }, 3608 .hback_porch = { 40, 40, 40 }, 3609 .hsync_len = { 1, 48, 48 }, 3610 .vactive = { 480, 480, 480 }, 3611 .vfront_porch = { 13, 13, 13 }, 3612 .vback_porch = { 29, 29, 29 }, 3613 .vsync_len = { 3, 3, 3 }, 3614 .flags = DISPLAY_FLAGS_DE_HIGH, 3615 }; 3616 3617 static const struct panel_desc okaya_rs800480t_7x0gp = { 3618 .timings = &okaya_rs800480t_7x0gp_timing, 3619 .num_timings = 1, 3620 .bpc = 6, 3621 .size = { 3622 .width = 154, 3623 .height = 87, 3624 }, 3625 .delay = { 3626 .prepare = 41, 3627 .enable = 50, 3628 .unprepare = 41, 3629 .disable = 50, 3630 }, 3631 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3632 }; 3633 3634 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3635 .clock = 9000, 3636 .hdisplay = 480, 3637 .hsync_start = 480 + 5, 3638 .hsync_end = 480 + 5 + 30, 3639 .htotal = 480 + 5 + 30 + 10, 3640 .vdisplay = 272, 3641 .vsync_start = 272 + 8, 3642 .vsync_end = 272 + 8 + 5, 3643 .vtotal = 272 + 8 + 5 + 3, 3644 }; 3645 3646 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3647 .modes = &olimex_lcd_olinuxino_43ts_mode, 3648 .num_modes = 1, 3649 .size = { 3650 .width = 95, 3651 .height = 54, 3652 }, 3653 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3654 }; 3655 3656 static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 3657 .pixelclock = { 30000000, 30000000, 50000000 }, 3658 .hactive = { 800, 800, 800 }, 3659 .hfront_porch = { 1, 40, 255 }, 3660 .hback_porch = { 1, 40, 87 }, 3661 .hsync_len = { 1, 48, 87 }, 3662 .vactive = { 480, 480, 480 }, 3663 .vfront_porch = { 1, 13, 255 }, 3664 .vback_porch = { 1, 29, 29 }, 3665 .vsync_len = { 3, 3, 31 }, 3666 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3667 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3668 }; 3669 3670 static const struct panel_desc ontat_kd50g21_40nt_a1 = { 3671 .timings = &ontat_kd50g21_40nt_a1_timing, 3672 .num_timings = 1, 3673 .bpc = 8, 3674 .size = { 3675 .width = 108, 3676 .height = 65, 3677 }, 3678 .delay = { 3679 .prepare = 147, /* 5 VSDs */ 3680 .enable = 147, /* 5 VSDs */ 3681 .disable = 88, /* 3 VSDs */ 3682 .unprepare = 117, /* 4 VSDs */ 3683 }, 3684 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3685 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3686 .connector_type = DRM_MODE_CONNECTOR_DPI, 3687 }; 3688 3689 /* 3690 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3691 * pixel clocks, but this is the timing that was being used in the Adafruit 3692 * installation instructions. 3693 */ 3694 static const struct drm_display_mode ontat_yx700wv03_mode = { 3695 .clock = 29500, 3696 .hdisplay = 800, 3697 .hsync_start = 824, 3698 .hsync_end = 896, 3699 .htotal = 992, 3700 .vdisplay = 480, 3701 .vsync_start = 483, 3702 .vsync_end = 493, 3703 .vtotal = 500, 3704 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3705 }; 3706 3707 /* 3708 * Specification at: 3709 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3710 */ 3711 static const struct panel_desc ontat_yx700wv03 = { 3712 .modes = &ontat_yx700wv03_mode, 3713 .num_modes = 1, 3714 .bpc = 8, 3715 .size = { 3716 .width = 154, 3717 .height = 83, 3718 }, 3719 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3720 }; 3721 3722 static const struct drm_display_mode ortustech_com37h3m_mode = { 3723 .clock = 22230, 3724 .hdisplay = 480, 3725 .hsync_start = 480 + 40, 3726 .hsync_end = 480 + 40 + 10, 3727 .htotal = 480 + 40 + 10 + 40, 3728 .vdisplay = 640, 3729 .vsync_start = 640 + 4, 3730 .vsync_end = 640 + 4 + 2, 3731 .vtotal = 640 + 4 + 2 + 4, 3732 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3733 }; 3734 3735 static const struct panel_desc ortustech_com37h3m = { 3736 .modes = &ortustech_com37h3m_mode, 3737 .num_modes = 1, 3738 .bpc = 8, 3739 .size = { 3740 .width = 56, /* 56.16mm */ 3741 .height = 75, /* 74.88mm */ 3742 }, 3743 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3744 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3745 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3746 }; 3747 3748 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3749 .clock = 25000, 3750 .hdisplay = 480, 3751 .hsync_start = 480 + 10, 3752 .hsync_end = 480 + 10 + 10, 3753 .htotal = 480 + 10 + 10 + 15, 3754 .vdisplay = 800, 3755 .vsync_start = 800 + 3, 3756 .vsync_end = 800 + 3 + 3, 3757 .vtotal = 800 + 3 + 3 + 3, 3758 }; 3759 3760 static const struct panel_desc ortustech_com43h4m85ulc = { 3761 .modes = &ortustech_com43h4m85ulc_mode, 3762 .num_modes = 1, 3763 .bpc = 6, 3764 .size = { 3765 .width = 56, 3766 .height = 93, 3767 }, 3768 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3769 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3770 .connector_type = DRM_MODE_CONNECTOR_DPI, 3771 }; 3772 3773 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3774 .clock = 33000, 3775 .hdisplay = 800, 3776 .hsync_start = 800 + 210, 3777 .hsync_end = 800 + 210 + 30, 3778 .htotal = 800 + 210 + 30 + 16, 3779 .vdisplay = 480, 3780 .vsync_start = 480 + 22, 3781 .vsync_end = 480 + 22 + 13, 3782 .vtotal = 480 + 22 + 13 + 10, 3783 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3784 }; 3785 3786 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3787 .modes = &osddisplays_osd070t1718_19ts_mode, 3788 .num_modes = 1, 3789 .bpc = 8, 3790 .size = { 3791 .width = 152, 3792 .height = 91, 3793 }, 3794 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3795 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3796 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3797 .connector_type = DRM_MODE_CONNECTOR_DPI, 3798 }; 3799 3800 static const struct drm_display_mode pda_91_00156_a0_mode = { 3801 .clock = 33300, 3802 .hdisplay = 800, 3803 .hsync_start = 800 + 1, 3804 .hsync_end = 800 + 1 + 64, 3805 .htotal = 800 + 1 + 64 + 64, 3806 .vdisplay = 480, 3807 .vsync_start = 480 + 1, 3808 .vsync_end = 480 + 1 + 23, 3809 .vtotal = 480 + 1 + 23 + 22, 3810 }; 3811 3812 static const struct panel_desc pda_91_00156_a0 = { 3813 .modes = &pda_91_00156_a0_mode, 3814 .num_modes = 1, 3815 .size = { 3816 .width = 152, 3817 .height = 91, 3818 }, 3819 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3820 }; 3821 3822 static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { 3823 .clock = 71150, 3824 .hdisplay = 1280, 3825 .hsync_start = 1280 + 48, 3826 .hsync_end = 1280 + 48 + 32, 3827 .htotal = 1280 + 48 + 32 + 80, 3828 .vdisplay = 800, 3829 .vsync_start = 800 + 9, 3830 .vsync_end = 800 + 9 + 8, 3831 .vtotal = 800 + 9 + 8 + 6, 3832 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3833 }; 3834 3835 static const struct panel_desc powertip_ph128800t004_zza01 = { 3836 .modes = &powertip_ph128800t004_zza01_mode, 3837 .num_modes = 1, 3838 .bpc = 8, 3839 .size = { 3840 .width = 216, 3841 .height = 135, 3842 }, 3843 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3844 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3845 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3846 }; 3847 3848 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 3849 .clock = 66500, 3850 .hdisplay = 1280, 3851 .hsync_start = 1280 + 12, 3852 .hsync_end = 1280 + 12 + 20, 3853 .htotal = 1280 + 12 + 20 + 56, 3854 .vdisplay = 800, 3855 .vsync_start = 800 + 1, 3856 .vsync_end = 800 + 1 + 3, 3857 .vtotal = 800 + 1 + 3 + 20, 3858 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3859 }; 3860 3861 static const struct panel_desc powertip_ph128800t006_zhc01 = { 3862 .modes = &powertip_ph128800t006_zhc01_mode, 3863 .num_modes = 1, 3864 .bpc = 8, 3865 .size = { 3866 .width = 216, 3867 .height = 135, 3868 }, 3869 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3870 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3871 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3872 }; 3873 3874 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3875 .clock = 24750, 3876 .hdisplay = 800, 3877 .hsync_start = 800 + 54, 3878 .hsync_end = 800 + 54 + 2, 3879 .htotal = 800 + 54 + 2 + 44, 3880 .vdisplay = 480, 3881 .vsync_start = 480 + 49, 3882 .vsync_end = 480 + 49 + 2, 3883 .vtotal = 480 + 49 + 2 + 22, 3884 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3885 }; 3886 3887 static const struct panel_desc powertip_ph800480t013_idf02 = { 3888 .modes = &powertip_ph800480t013_idf02_mode, 3889 .num_modes = 1, 3890 .bpc = 8, 3891 .size = { 3892 .width = 152, 3893 .height = 91, 3894 }, 3895 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3896 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3897 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3898 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3899 .connector_type = DRM_MODE_CONNECTOR_DPI, 3900 }; 3901 3902 static const struct drm_display_mode primeview_pm070wl4_mode = { 3903 .clock = 32000, 3904 .hdisplay = 800, 3905 .hsync_start = 800 + 42, 3906 .hsync_end = 800 + 42 + 128, 3907 .htotal = 800 + 42 + 128 + 86, 3908 .vdisplay = 480, 3909 .vsync_start = 480 + 10, 3910 .vsync_end = 480 + 10 + 2, 3911 .vtotal = 480 + 10 + 2 + 33, 3912 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3913 }; 3914 3915 static const struct panel_desc primeview_pm070wl4 = { 3916 .modes = &primeview_pm070wl4_mode, 3917 .num_modes = 1, 3918 .bpc = 6, 3919 .size = { 3920 .width = 152, 3921 .height = 91, 3922 }, 3923 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3924 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3925 .connector_type = DRM_MODE_CONNECTOR_DPI, 3926 }; 3927 3928 static const struct drm_display_mode qd43003c0_40_mode = { 3929 .clock = 9000, 3930 .hdisplay = 480, 3931 .hsync_start = 480 + 8, 3932 .hsync_end = 480 + 8 + 4, 3933 .htotal = 480 + 8 + 4 + 39, 3934 .vdisplay = 272, 3935 .vsync_start = 272 + 4, 3936 .vsync_end = 272 + 4 + 10, 3937 .vtotal = 272 + 4 + 10 + 2, 3938 }; 3939 3940 static const struct panel_desc qd43003c0_40 = { 3941 .modes = &qd43003c0_40_mode, 3942 .num_modes = 1, 3943 .bpc = 8, 3944 .size = { 3945 .width = 95, 3946 .height = 53, 3947 }, 3948 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3949 }; 3950 3951 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3952 { /* 60 Hz */ 3953 .clock = 10800, 3954 .hdisplay = 480, 3955 .hsync_start = 480 + 77, 3956 .hsync_end = 480 + 77 + 41, 3957 .htotal = 480 + 77 + 41 + 2, 3958 .vdisplay = 272, 3959 .vsync_start = 272 + 16, 3960 .vsync_end = 272 + 16 + 10, 3961 .vtotal = 272 + 16 + 10 + 2, 3962 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3963 }, 3964 { /* 50 Hz */ 3965 .clock = 10800, 3966 .hdisplay = 480, 3967 .hsync_start = 480 + 17, 3968 .hsync_end = 480 + 17 + 41, 3969 .htotal = 480 + 17 + 41 + 2, 3970 .vdisplay = 272, 3971 .vsync_start = 272 + 116, 3972 .vsync_end = 272 + 116 + 10, 3973 .vtotal = 272 + 116 + 10 + 2, 3974 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3975 }, 3976 }; 3977 3978 static const struct panel_desc qishenglong_gopher2b_lcd = { 3979 .modes = qishenglong_gopher2b_lcd_modes, 3980 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3981 .bpc = 8, 3982 .size = { 3983 .width = 95, 3984 .height = 54, 3985 }, 3986 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3987 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3988 .connector_type = DRM_MODE_CONNECTOR_DPI, 3989 }; 3990 3991 static const struct display_timing rocktech_rk043fn48h_timing = { 3992 .pixelclock = { 6000000, 9000000, 12000000 }, 3993 .hactive = { 480, 480, 480 }, 3994 .hback_porch = { 8, 43, 43 }, 3995 .hfront_porch = { 2, 8, 10 }, 3996 .hsync_len = { 1, 1, 1 }, 3997 .vactive = { 272, 272, 272 }, 3998 .vback_porch = { 2, 12, 26 }, 3999 .vfront_porch = { 1, 4, 4 }, 4000 .vsync_len = { 1, 10, 10 }, 4001 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 4002 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4003 DISPLAY_FLAGS_SYNC_POSEDGE, 4004 }; 4005 4006 static const struct panel_desc rocktech_rk043fn48h = { 4007 .timings = &rocktech_rk043fn48h_timing, 4008 .num_timings = 1, 4009 .bpc = 8, 4010 .size = { 4011 .width = 95, 4012 .height = 54, 4013 }, 4014 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4015 .connector_type = DRM_MODE_CONNECTOR_DPI, 4016 }; 4017 4018 static const struct display_timing rocktech_rk070er9427_timing = { 4019 .pixelclock = { 26400000, 33300000, 46800000 }, 4020 .hactive = { 800, 800, 800 }, 4021 .hfront_porch = { 16, 210, 354 }, 4022 .hback_porch = { 46, 46, 46 }, 4023 .hsync_len = { 1, 1, 1 }, 4024 .vactive = { 480, 480, 480 }, 4025 .vfront_porch = { 7, 22, 147 }, 4026 .vback_porch = { 23, 23, 23 }, 4027 .vsync_len = { 1, 1, 1 }, 4028 .flags = DISPLAY_FLAGS_DE_HIGH, 4029 }; 4030 4031 static const struct panel_desc rocktech_rk070er9427 = { 4032 .timings = &rocktech_rk070er9427_timing, 4033 .num_timings = 1, 4034 .bpc = 6, 4035 .size = { 4036 .width = 154, 4037 .height = 86, 4038 }, 4039 .delay = { 4040 .prepare = 41, 4041 .enable = 50, 4042 .unprepare = 41, 4043 .disable = 50, 4044 }, 4045 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4046 }; 4047 4048 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4049 .clock = 71100, 4050 .hdisplay = 1280, 4051 .hsync_start = 1280 + 48, 4052 .hsync_end = 1280 + 48 + 32, 4053 .htotal = 1280 + 48 + 32 + 80, 4054 .vdisplay = 800, 4055 .vsync_start = 800 + 2, 4056 .vsync_end = 800 + 2 + 5, 4057 .vtotal = 800 + 2 + 5 + 16, 4058 }; 4059 4060 static const struct panel_desc rocktech_rk101ii01d_ct = { 4061 .modes = &rocktech_rk101ii01d_ct_mode, 4062 .bpc = 8, 4063 .num_modes = 1, 4064 .size = { 4065 .width = 217, 4066 .height = 136, 4067 }, 4068 .delay = { 4069 .prepare = 50, 4070 .disable = 50, 4071 }, 4072 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4073 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4074 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4075 }; 4076 4077 static const struct display_timing samsung_ltl101al01_timing = { 4078 .pixelclock = { 66663000, 66663000, 66663000 }, 4079 .hactive = { 1280, 1280, 1280 }, 4080 .hfront_porch = { 18, 18, 18 }, 4081 .hback_porch = { 36, 36, 36 }, 4082 .hsync_len = { 16, 16, 16 }, 4083 .vactive = { 800, 800, 800 }, 4084 .vfront_porch = { 4, 4, 4 }, 4085 .vback_porch = { 16, 16, 16 }, 4086 .vsync_len = { 3, 3, 3 }, 4087 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4088 }; 4089 4090 static const struct panel_desc samsung_ltl101al01 = { 4091 .timings = &samsung_ltl101al01_timing, 4092 .num_timings = 1, 4093 .bpc = 8, 4094 .size = { 4095 .width = 217, 4096 .height = 135, 4097 }, 4098 .delay = { 4099 .prepare = 40, 4100 .enable = 300, 4101 .disable = 200, 4102 .unprepare = 600, 4103 }, 4104 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4105 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4106 }; 4107 4108 static const struct drm_display_mode samsung_ltn101nt05_mode = { 4109 .clock = 54030, 4110 .hdisplay = 1024, 4111 .hsync_start = 1024 + 24, 4112 .hsync_end = 1024 + 24 + 136, 4113 .htotal = 1024 + 24 + 136 + 160, 4114 .vdisplay = 600, 4115 .vsync_start = 600 + 3, 4116 .vsync_end = 600 + 3 + 6, 4117 .vtotal = 600 + 3 + 6 + 61, 4118 }; 4119 4120 static const struct panel_desc samsung_ltn101nt05 = { 4121 .modes = &samsung_ltn101nt05_mode, 4122 .num_modes = 1, 4123 .bpc = 6, 4124 .size = { 4125 .width = 223, 4126 .height = 125, 4127 }, 4128 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4129 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4130 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4131 }; 4132 4133 static const struct display_timing satoz_sat050at40h12r2_timing = { 4134 .pixelclock = {33300000, 33300000, 50000000}, 4135 .hactive = {800, 800, 800}, 4136 .hfront_porch = {16, 210, 354}, 4137 .hback_porch = {46, 46, 46}, 4138 .hsync_len = {1, 1, 40}, 4139 .vactive = {480, 480, 480}, 4140 .vfront_porch = {7, 22, 147}, 4141 .vback_porch = {23, 23, 23}, 4142 .vsync_len = {1, 1, 20}, 4143 }; 4144 4145 static const struct panel_desc satoz_sat050at40h12r2 = { 4146 .timings = &satoz_sat050at40h12r2_timing, 4147 .num_timings = 1, 4148 .bpc = 8, 4149 .size = { 4150 .width = 108, 4151 .height = 65, 4152 }, 4153 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4154 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4155 }; 4156 4157 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4158 .clock = 33260, 4159 .hdisplay = 800, 4160 .hsync_start = 800 + 64, 4161 .hsync_end = 800 + 64 + 128, 4162 .htotal = 800 + 64 + 128 + 64, 4163 .vdisplay = 480, 4164 .vsync_start = 480 + 8, 4165 .vsync_end = 480 + 8 + 2, 4166 .vtotal = 480 + 8 + 2 + 35, 4167 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4168 }; 4169 4170 static const struct panel_desc sharp_lq070y3dg3b = { 4171 .modes = &sharp_lq070y3dg3b_mode, 4172 .num_modes = 1, 4173 .bpc = 8, 4174 .size = { 4175 .width = 152, /* 152.4mm */ 4176 .height = 91, /* 91.4mm */ 4177 }, 4178 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4179 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4180 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4181 }; 4182 4183 static const struct drm_display_mode sharp_lq035q7db03_mode = { 4184 .clock = 5500, 4185 .hdisplay = 240, 4186 .hsync_start = 240 + 16, 4187 .hsync_end = 240 + 16 + 7, 4188 .htotal = 240 + 16 + 7 + 5, 4189 .vdisplay = 320, 4190 .vsync_start = 320 + 9, 4191 .vsync_end = 320 + 9 + 1, 4192 .vtotal = 320 + 9 + 1 + 7, 4193 }; 4194 4195 static const struct panel_desc sharp_lq035q7db03 = { 4196 .modes = &sharp_lq035q7db03_mode, 4197 .num_modes = 1, 4198 .bpc = 6, 4199 .size = { 4200 .width = 54, 4201 .height = 72, 4202 }, 4203 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4204 }; 4205 4206 static const struct display_timing sharp_lq101k1ly04_timing = { 4207 .pixelclock = { 60000000, 65000000, 80000000 }, 4208 .hactive = { 1280, 1280, 1280 }, 4209 .hfront_porch = { 20, 20, 20 }, 4210 .hback_porch = { 20, 20, 20 }, 4211 .hsync_len = { 10, 10, 10 }, 4212 .vactive = { 800, 800, 800 }, 4213 .vfront_porch = { 4, 4, 4 }, 4214 .vback_porch = { 4, 4, 4 }, 4215 .vsync_len = { 4, 4, 4 }, 4216 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4217 }; 4218 4219 static const struct panel_desc sharp_lq101k1ly04 = { 4220 .timings = &sharp_lq101k1ly04_timing, 4221 .num_timings = 1, 4222 .bpc = 8, 4223 .size = { 4224 .width = 217, 4225 .height = 136, 4226 }, 4227 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4228 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4229 }; 4230 4231 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4232 { /* 50 Hz */ 4233 .clock = 3000, 4234 .hdisplay = 240, 4235 .hsync_start = 240 + 58, 4236 .hsync_end = 240 + 58 + 1, 4237 .htotal = 240 + 58 + 1 + 1, 4238 .vdisplay = 160, 4239 .vsync_start = 160 + 24, 4240 .vsync_end = 160 + 24 + 10, 4241 .vtotal = 160 + 24 + 10 + 6, 4242 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4243 }, 4244 { /* 60 Hz */ 4245 .clock = 3000, 4246 .hdisplay = 240, 4247 .hsync_start = 240 + 8, 4248 .hsync_end = 240 + 8 + 1, 4249 .htotal = 240 + 8 + 1 + 1, 4250 .vdisplay = 160, 4251 .vsync_start = 160 + 24, 4252 .vsync_end = 160 + 24 + 10, 4253 .vtotal = 160 + 24 + 10 + 6, 4254 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4255 }, 4256 }; 4257 4258 static const struct panel_desc sharp_ls020b1dd01d = { 4259 .modes = sharp_ls020b1dd01d_modes, 4260 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4261 .bpc = 6, 4262 .size = { 4263 .width = 42, 4264 .height = 28, 4265 }, 4266 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4267 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4268 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4269 | DRM_BUS_FLAG_SHARP_SIGNALS, 4270 }; 4271 4272 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4273 .clock = 33300, 4274 .hdisplay = 800, 4275 .hsync_start = 800 + 1, 4276 .hsync_end = 800 + 1 + 64, 4277 .htotal = 800 + 1 + 64 + 64, 4278 .vdisplay = 480, 4279 .vsync_start = 480 + 1, 4280 .vsync_end = 480 + 1 + 23, 4281 .vtotal = 480 + 1 + 23 + 22, 4282 }; 4283 4284 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4285 .modes = &shelly_sca07010_bfn_lnn_mode, 4286 .num_modes = 1, 4287 .size = { 4288 .width = 152, 4289 .height = 91, 4290 }, 4291 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4292 }; 4293 4294 static const struct drm_display_mode starry_kr070pe2t_mode = { 4295 .clock = 33000, 4296 .hdisplay = 800, 4297 .hsync_start = 800 + 209, 4298 .hsync_end = 800 + 209 + 1, 4299 .htotal = 800 + 209 + 1 + 45, 4300 .vdisplay = 480, 4301 .vsync_start = 480 + 22, 4302 .vsync_end = 480 + 22 + 1, 4303 .vtotal = 480 + 22 + 1 + 22, 4304 }; 4305 4306 static const struct panel_desc starry_kr070pe2t = { 4307 .modes = &starry_kr070pe2t_mode, 4308 .num_modes = 1, 4309 .bpc = 8, 4310 .size = { 4311 .width = 152, 4312 .height = 86, 4313 }, 4314 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4315 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4316 .connector_type = DRM_MODE_CONNECTOR_DPI, 4317 }; 4318 4319 static const struct display_timing startek_kd070wvfpa_mode = { 4320 .pixelclock = { 25200000, 27200000, 30500000 }, 4321 .hactive = { 800, 800, 800 }, 4322 .hfront_porch = { 19, 44, 115 }, 4323 .hback_porch = { 5, 16, 101 }, 4324 .hsync_len = { 1, 2, 100 }, 4325 .vactive = { 480, 480, 480 }, 4326 .vfront_porch = { 5, 43, 67 }, 4327 .vback_porch = { 5, 5, 67 }, 4328 .vsync_len = { 1, 2, 66 }, 4329 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4330 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4331 DISPLAY_FLAGS_SYNC_POSEDGE, 4332 }; 4333 4334 static const struct panel_desc startek_kd070wvfpa = { 4335 .timings = &startek_kd070wvfpa_mode, 4336 .num_timings = 1, 4337 .bpc = 8, 4338 .size = { 4339 .width = 152, 4340 .height = 91, 4341 }, 4342 .delay = { 4343 .prepare = 20, 4344 .enable = 200, 4345 .disable = 200, 4346 }, 4347 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4348 .connector_type = DRM_MODE_CONNECTOR_DPI, 4349 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4350 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4351 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4352 }; 4353 4354 static const struct display_timing tsd_tst043015cmhx_timing = { 4355 .pixelclock = { 5000000, 9000000, 12000000 }, 4356 .hactive = { 480, 480, 480 }, 4357 .hfront_porch = { 4, 5, 65 }, 4358 .hback_porch = { 36, 40, 255 }, 4359 .hsync_len = { 1, 1, 1 }, 4360 .vactive = { 272, 272, 272 }, 4361 .vfront_porch = { 2, 8, 97 }, 4362 .vback_porch = { 3, 8, 31 }, 4363 .vsync_len = { 1, 1, 1 }, 4364 4365 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4366 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4367 }; 4368 4369 static const struct panel_desc tsd_tst043015cmhx = { 4370 .timings = &tsd_tst043015cmhx_timing, 4371 .num_timings = 1, 4372 .bpc = 8, 4373 .size = { 4374 .width = 105, 4375 .height = 67, 4376 }, 4377 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4378 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4379 }; 4380 4381 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4382 .clock = 30000, 4383 .hdisplay = 800, 4384 .hsync_start = 800 + 39, 4385 .hsync_end = 800 + 39 + 47, 4386 .htotal = 800 + 39 + 47 + 39, 4387 .vdisplay = 480, 4388 .vsync_start = 480 + 13, 4389 .vsync_end = 480 + 13 + 2, 4390 .vtotal = 480 + 13 + 2 + 29, 4391 }; 4392 4393 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4394 .modes = &tfc_s9700rtwv43tr_01b_mode, 4395 .num_modes = 1, 4396 .bpc = 8, 4397 .size = { 4398 .width = 155, 4399 .height = 90, 4400 }, 4401 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4402 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4403 }; 4404 4405 static const struct display_timing tianma_tm070jdhg30_timing = { 4406 .pixelclock = { 62600000, 68200000, 78100000 }, 4407 .hactive = { 1280, 1280, 1280 }, 4408 .hfront_porch = { 15, 64, 159 }, 4409 .hback_porch = { 5, 5, 5 }, 4410 .hsync_len = { 1, 1, 256 }, 4411 .vactive = { 800, 800, 800 }, 4412 .vfront_porch = { 3, 40, 99 }, 4413 .vback_porch = { 2, 2, 2 }, 4414 .vsync_len = { 1, 1, 128 }, 4415 .flags = DISPLAY_FLAGS_DE_HIGH, 4416 }; 4417 4418 static const struct panel_desc tianma_tm070jdhg30 = { 4419 .timings = &tianma_tm070jdhg30_timing, 4420 .num_timings = 1, 4421 .bpc = 8, 4422 .size = { 4423 .width = 151, 4424 .height = 95, 4425 }, 4426 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4427 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4428 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4429 }; 4430 4431 static const struct panel_desc tianma_tm070jvhg33 = { 4432 .timings = &tianma_tm070jdhg30_timing, 4433 .num_timings = 1, 4434 .bpc = 8, 4435 .size = { 4436 .width = 150, 4437 .height = 94, 4438 }, 4439 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4440 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4441 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4442 }; 4443 4444 /* 4445 * The datasheet computes total blanking as back porch + front porch, not 4446 * including sync pulse width. This is for both H and V. To make the total 4447 * blanking and period correct, subtract the pulse width from the front 4448 * porch. 4449 * 4450 * This works well for the Min and Typ values, but for Max values the sync 4451 * pulse width is higher than back porch + front porch, so work around that 4452 * by reducing the Max sync length value to 1 and then treating the Max 4453 * porches as in the Min and Typ cases. 4454 * 4455 * Exact datasheet values are added as a comment where they differ from the 4456 * ones implemented for the above reason. 4457 */ 4458 static const struct display_timing tianma_tm070jdhg34_00_timing = { 4459 .pixelclock = { 68400000, 71900000, 78100000 }, 4460 .hactive = { 1280, 1280, 1280 }, 4461 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4462 .hback_porch = { 5, 5, 5 }, 4463 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4464 .vactive = { 800, 800, 800 }, 4465 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4466 .vback_porch = { 2, 2, 2 }, 4467 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4468 .flags = DISPLAY_FLAGS_DE_HIGH, 4469 }; 4470 4471 static const struct panel_desc tianma_tm070jdhg34_00 = { 4472 .timings = &tianma_tm070jdhg34_00_timing, 4473 .num_timings = 1, 4474 .bpc = 8, 4475 .size = { 4476 .width = 150, /* 149.76 */ 4477 .height = 94, /* 93.60 */ 4478 }, 4479 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4480 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4481 }; 4482 4483 static const struct display_timing tianma_tm070rvhg71_timing = { 4484 .pixelclock = { 27700000, 29200000, 39600000 }, 4485 .hactive = { 800, 800, 800 }, 4486 .hfront_porch = { 12, 40, 212 }, 4487 .hback_porch = { 88, 88, 88 }, 4488 .hsync_len = { 1, 1, 40 }, 4489 .vactive = { 480, 480, 480 }, 4490 .vfront_porch = { 1, 13, 88 }, 4491 .vback_porch = { 32, 32, 32 }, 4492 .vsync_len = { 1, 1, 3 }, 4493 .flags = DISPLAY_FLAGS_DE_HIGH, 4494 }; 4495 4496 static const struct panel_desc tianma_tm070rvhg71 = { 4497 .timings = &tianma_tm070rvhg71_timing, 4498 .num_timings = 1, 4499 .bpc = 8, 4500 .size = { 4501 .width = 154, 4502 .height = 86, 4503 }, 4504 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4505 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4506 }; 4507 4508 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4509 { 4510 .clock = 10000, 4511 .hdisplay = 320, 4512 .hsync_start = 320 + 50, 4513 .hsync_end = 320 + 50 + 6, 4514 .htotal = 320 + 50 + 6 + 38, 4515 .vdisplay = 240, 4516 .vsync_start = 240 + 3, 4517 .vsync_end = 240 + 3 + 1, 4518 .vtotal = 240 + 3 + 1 + 17, 4519 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4520 }, 4521 }; 4522 4523 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4524 .modes = ti_nspire_cx_lcd_mode, 4525 .num_modes = 1, 4526 .bpc = 8, 4527 .size = { 4528 .width = 65, 4529 .height = 49, 4530 }, 4531 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4532 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4533 }; 4534 4535 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4536 { 4537 .clock = 10000, 4538 .hdisplay = 320, 4539 .hsync_start = 320 + 6, 4540 .hsync_end = 320 + 6 + 6, 4541 .htotal = 320 + 6 + 6 + 6, 4542 .vdisplay = 240, 4543 .vsync_start = 240 + 0, 4544 .vsync_end = 240 + 0 + 1, 4545 .vtotal = 240 + 0 + 1 + 0, 4546 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4547 }, 4548 }; 4549 4550 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4551 .modes = ti_nspire_classic_lcd_mode, 4552 .num_modes = 1, 4553 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4554 .bpc = 8, 4555 .size = { 4556 .width = 71, 4557 .height = 53, 4558 }, 4559 /* This is the grayscale bus format */ 4560 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4561 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4562 }; 4563 4564 static const struct display_timing topland_tian_g07017_01_timing = { 4565 .pixelclock = { 44900000, 51200000, 63000000 }, 4566 .hactive = { 1024, 1024, 1024 }, 4567 .hfront_porch = { 16, 160, 216 }, 4568 .hback_porch = { 160, 160, 160 }, 4569 .hsync_len = { 1, 1, 140 }, 4570 .vactive = { 600, 600, 600 }, 4571 .vfront_porch = { 1, 12, 127 }, 4572 .vback_porch = { 23, 23, 23 }, 4573 .vsync_len = { 1, 1, 20 }, 4574 }; 4575 4576 static const struct panel_desc topland_tian_g07017_01 = { 4577 .timings = &topland_tian_g07017_01_timing, 4578 .num_timings = 1, 4579 .bpc = 8, 4580 .size = { 4581 .width = 154, 4582 .height = 86, 4583 }, 4584 .delay = { 4585 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 4586 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 4587 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 4588 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 4589 }, 4590 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4591 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4592 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4593 }; 4594 4595 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4596 .clock = 79500, 4597 .hdisplay = 1280, 4598 .hsync_start = 1280 + 192, 4599 .hsync_end = 1280 + 192 + 128, 4600 .htotal = 1280 + 192 + 128 + 64, 4601 .vdisplay = 768, 4602 .vsync_start = 768 + 20, 4603 .vsync_end = 768 + 20 + 7, 4604 .vtotal = 768 + 20 + 7 + 3, 4605 }; 4606 4607 static const struct panel_desc toshiba_lt089ac29000 = { 4608 .modes = &toshiba_lt089ac29000_mode, 4609 .num_modes = 1, 4610 .size = { 4611 .width = 194, 4612 .height = 116, 4613 }, 4614 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4615 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4616 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4617 }; 4618 4619 static const struct drm_display_mode tpk_f07a_0102_mode = { 4620 .clock = 33260, 4621 .hdisplay = 800, 4622 .hsync_start = 800 + 40, 4623 .hsync_end = 800 + 40 + 128, 4624 .htotal = 800 + 40 + 128 + 88, 4625 .vdisplay = 480, 4626 .vsync_start = 480 + 10, 4627 .vsync_end = 480 + 10 + 2, 4628 .vtotal = 480 + 10 + 2 + 33, 4629 }; 4630 4631 static const struct panel_desc tpk_f07a_0102 = { 4632 .modes = &tpk_f07a_0102_mode, 4633 .num_modes = 1, 4634 .size = { 4635 .width = 152, 4636 .height = 91, 4637 }, 4638 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4639 }; 4640 4641 static const struct drm_display_mode tpk_f10a_0102_mode = { 4642 .clock = 45000, 4643 .hdisplay = 1024, 4644 .hsync_start = 1024 + 176, 4645 .hsync_end = 1024 + 176 + 5, 4646 .htotal = 1024 + 176 + 5 + 88, 4647 .vdisplay = 600, 4648 .vsync_start = 600 + 20, 4649 .vsync_end = 600 + 20 + 5, 4650 .vtotal = 600 + 20 + 5 + 25, 4651 }; 4652 4653 static const struct panel_desc tpk_f10a_0102 = { 4654 .modes = &tpk_f10a_0102_mode, 4655 .num_modes = 1, 4656 .size = { 4657 .width = 223, 4658 .height = 125, 4659 }, 4660 }; 4661 4662 static const struct display_timing urt_umsh_8596md_timing = { 4663 .pixelclock = { 33260000, 33260000, 33260000 }, 4664 .hactive = { 800, 800, 800 }, 4665 .hfront_porch = { 41, 41, 41 }, 4666 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4667 .hsync_len = { 71, 128, 128 }, 4668 .vactive = { 480, 480, 480 }, 4669 .vfront_porch = { 10, 10, 10 }, 4670 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4671 .vsync_len = { 2, 2, 2 }, 4672 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4673 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4674 }; 4675 4676 static const struct panel_desc urt_umsh_8596md_lvds = { 4677 .timings = &urt_umsh_8596md_timing, 4678 .num_timings = 1, 4679 .bpc = 6, 4680 .size = { 4681 .width = 152, 4682 .height = 91, 4683 }, 4684 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4685 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4686 }; 4687 4688 static const struct panel_desc urt_umsh_8596md_parallel = { 4689 .timings = &urt_umsh_8596md_timing, 4690 .num_timings = 1, 4691 .bpc = 6, 4692 .size = { 4693 .width = 152, 4694 .height = 91, 4695 }, 4696 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4697 }; 4698 4699 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4700 .clock = 60000, 4701 .hdisplay = 1024, 4702 .hsync_start = 1024 + 160, 4703 .hsync_end = 1024 + 160 + 100, 4704 .htotal = 1024 + 160 + 100 + 60, 4705 .vdisplay = 600, 4706 .vsync_start = 600 + 12, 4707 .vsync_end = 600 + 12 + 10, 4708 .vtotal = 600 + 12 + 10 + 13, 4709 }; 4710 4711 static const struct panel_desc vivax_tpc9150_panel = { 4712 .modes = &vivax_tpc9150_panel_mode, 4713 .num_modes = 1, 4714 .bpc = 6, 4715 .size = { 4716 .width = 200, 4717 .height = 115, 4718 }, 4719 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4720 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4721 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4722 }; 4723 4724 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4725 .clock = 33333, 4726 .hdisplay = 800, 4727 .hsync_start = 800 + 210, 4728 .hsync_end = 800 + 210 + 20, 4729 .htotal = 800 + 210 + 20 + 46, 4730 .vdisplay = 480, 4731 .vsync_start = 480 + 22, 4732 .vsync_end = 480 + 22 + 10, 4733 .vtotal = 480 + 22 + 10 + 23, 4734 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4735 }; 4736 4737 static const struct panel_desc vl050_8048nt_c01 = { 4738 .modes = &vl050_8048nt_c01_mode, 4739 .num_modes = 1, 4740 .bpc = 8, 4741 .size = { 4742 .width = 120, 4743 .height = 76, 4744 }, 4745 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4746 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4747 }; 4748 4749 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4750 .clock = 6410, 4751 .hdisplay = 320, 4752 .hsync_start = 320 + 20, 4753 .hsync_end = 320 + 20 + 30, 4754 .htotal = 320 + 20 + 30 + 38, 4755 .vdisplay = 240, 4756 .vsync_start = 240 + 4, 4757 .vsync_end = 240 + 4 + 3, 4758 .vtotal = 240 + 4 + 3 + 15, 4759 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4760 }; 4761 4762 static const struct panel_desc winstar_wf35ltiacd = { 4763 .modes = &winstar_wf35ltiacd_mode, 4764 .num_modes = 1, 4765 .bpc = 8, 4766 .size = { 4767 .width = 70, 4768 .height = 53, 4769 }, 4770 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4771 }; 4772 4773 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4774 .clock = 51200, 4775 .hdisplay = 1024, 4776 .hsync_start = 1024 + 100, 4777 .hsync_end = 1024 + 100 + 100, 4778 .htotal = 1024 + 100 + 100 + 120, 4779 .vdisplay = 600, 4780 .vsync_start = 600 + 10, 4781 .vsync_end = 600 + 10 + 10, 4782 .vtotal = 600 + 10 + 10 + 15, 4783 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4784 }; 4785 4786 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4787 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4788 .num_modes = 1, 4789 .bpc = 8, 4790 .size = { 4791 .width = 154, 4792 .height = 90, 4793 }, 4794 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4795 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4796 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4797 }; 4798 4799 static const struct drm_display_mode mchp_ac69t88a_mode = { 4800 .clock = 25000, 4801 .hdisplay = 800, 4802 .hsync_start = 800 + 88, 4803 .hsync_end = 800 + 88 + 5, 4804 .htotal = 800 + 88 + 5 + 40, 4805 .vdisplay = 480, 4806 .vsync_start = 480 + 23, 4807 .vsync_end = 480 + 23 + 5, 4808 .vtotal = 480 + 23 + 5 + 1, 4809 }; 4810 4811 static const struct panel_desc mchp_ac69t88a = { 4812 .modes = &mchp_ac69t88a_mode, 4813 .num_modes = 1, 4814 .bpc = 8, 4815 .size = { 4816 .width = 108, 4817 .height = 65, 4818 }, 4819 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4820 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4821 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4822 }; 4823 4824 static const struct drm_display_mode arm_rtsm_mode[] = { 4825 { 4826 .clock = 65000, 4827 .hdisplay = 1024, 4828 .hsync_start = 1024 + 24, 4829 .hsync_end = 1024 + 24 + 136, 4830 .htotal = 1024 + 24 + 136 + 160, 4831 .vdisplay = 768, 4832 .vsync_start = 768 + 3, 4833 .vsync_end = 768 + 3 + 6, 4834 .vtotal = 768 + 3 + 6 + 29, 4835 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4836 }, 4837 }; 4838 4839 static const struct panel_desc arm_rtsm = { 4840 .modes = arm_rtsm_mode, 4841 .num_modes = 1, 4842 .bpc = 8, 4843 .size = { 4844 .width = 400, 4845 .height = 300, 4846 }, 4847 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4848 }; 4849 4850 static const struct of_device_id platform_of_match[] = { 4851 { 4852 .compatible = "ampire,am-1280800n3tzqw-t00h", 4853 .data = &ire_am_1280800n3tzqw_t00h, 4854 }, { 4855 .compatible = "ampire,am-480272h3tmqw-t01h", 4856 .data = &ire_am_480272h3tmqw_t01h, 4857 }, { 4858 .compatible = "ampire,am-800480l1tmqw-t00h", 4859 .data = &ire_am_800480l1tmqw_t00h, 4860 }, { 4861 .compatible = "ampire,am800480r3tmqwa1h", 4862 .data = &ire_am800480r3tmqwa1h, 4863 }, { 4864 .compatible = "ampire,am800600p5tmqw-tb8h", 4865 .data = &ire_am800600p5tmqwtb8h, 4866 }, { 4867 .compatible = "arm,rtsm-display", 4868 .data = &arm_rtsm, 4869 }, { 4870 .compatible = "armadeus,st0700-adapt", 4871 .data = &armadeus_st0700_adapt, 4872 }, { 4873 .compatible = "auo,b101aw03", 4874 .data = &auo_b101aw03, 4875 }, { 4876 .compatible = "auo,b101xtn01", 4877 .data = &auo_b101xtn01, 4878 }, { 4879 .compatible = "auo,b116xw03", 4880 .data = &auo_b116xw03, 4881 }, { 4882 .compatible = "auo,g070vvn01", 4883 .data = &auo_g070vvn01, 4884 }, { 4885 .compatible = "auo,g101evn010", 4886 .data = &auo_g101evn010, 4887 }, { 4888 .compatible = "auo,g104sn02", 4889 .data = &auo_g104sn02, 4890 }, { 4891 .compatible = "auo,g104stn01", 4892 .data = &auo_g104stn01, 4893 }, { 4894 .compatible = "auo,g121ean01", 4895 .data = &auo_g121ean01, 4896 }, { 4897 .compatible = "auo,g133han01", 4898 .data = &auo_g133han01, 4899 }, { 4900 .compatible = "auo,g156han04", 4901 .data = &auo_g156han04, 4902 }, { 4903 .compatible = "auo,g156xtn01", 4904 .data = &auo_g156xtn01, 4905 }, { 4906 .compatible = "auo,g185han01", 4907 .data = &auo_g185han01, 4908 }, { 4909 .compatible = "auo,g190ean01", 4910 .data = &auo_g190ean01, 4911 }, { 4912 .compatible = "auo,p320hvn03", 4913 .data = &auo_p320hvn03, 4914 }, { 4915 .compatible = "auo,t215hvn01", 4916 .data = &auo_t215hvn01, 4917 }, { 4918 .compatible = "avic,tm070ddh03", 4919 .data = &avic_tm070ddh03, 4920 }, { 4921 .compatible = "bananapi,s070wv20-ct16", 4922 .data = &bananapi_s070wv20_ct16, 4923 }, { 4924 .compatible = "boe,av101hdt-a10", 4925 .data = &boe_av101hdt_a10, 4926 }, { 4927 .compatible = "boe,av123z7m-n17", 4928 .data = &boe_av123z7m_n17, 4929 }, { 4930 .compatible = "boe,bp082wx1-100", 4931 .data = &boe_bp082wx1_100, 4932 }, { 4933 .compatible = "boe,bp101wx1-100", 4934 .data = &boe_bp101wx1_100, 4935 }, { 4936 .compatible = "boe,ev121wxm-n10-1850", 4937 .data = &boe_ev121wxm_n10_1850, 4938 }, { 4939 .compatible = "boe,hv070wsa-100", 4940 .data = &boe_hv070wsa 4941 }, { 4942 .compatible = "cct,cmt430b19n00", 4943 .data = &cct_cmt430b19n00, 4944 }, { 4945 .compatible = "cdtech,s043wq26h-ct7", 4946 .data = &cdtech_s043wq26h_ct7, 4947 }, { 4948 .compatible = "cdtech,s070pws19hp-fc21", 4949 .data = &cdtech_s070pws19hp_fc21, 4950 }, { 4951 .compatible = "cdtech,s070swv29hg-dc44", 4952 .data = &cdtech_s070swv29hg_dc44, 4953 }, { 4954 .compatible = "cdtech,s070wv95-ct16", 4955 .data = &cdtech_s070wv95_ct16, 4956 }, { 4957 .compatible = "chefree,ch101olhlwh-002", 4958 .data = &chefree_ch101olhlwh_002, 4959 }, { 4960 .compatible = "chunghwa,claa070wp03xg", 4961 .data = &chunghwa_claa070wp03xg, 4962 }, { 4963 .compatible = "chunghwa,claa101wa01a", 4964 .data = &chunghwa_claa101wa01a 4965 }, { 4966 .compatible = "chunghwa,claa101wb01", 4967 .data = &chunghwa_claa101wb01 4968 }, { 4969 .compatible = "dataimage,fg040346dsswbg04", 4970 .data = &dataimage_fg040346dsswbg04, 4971 }, { 4972 .compatible = "dataimage,fg1001l0dsswmg01", 4973 .data = &dataimage_fg1001l0dsswmg01, 4974 }, { 4975 .compatible = "dataimage,scf0700c48ggu18", 4976 .data = &dataimage_scf0700c48ggu18, 4977 }, { 4978 .compatible = "dlc,dlc0700yzg-1", 4979 .data = &dlc_dlc0700yzg_1, 4980 }, { 4981 .compatible = "dlc,dlc1010gig", 4982 .data = &dlc_dlc1010gig, 4983 }, { 4984 .compatible = "edt,et035012dm6", 4985 .data = &edt_et035012dm6, 4986 }, { 4987 .compatible = "edt,etm0350g0dh6", 4988 .data = &edt_etm0350g0dh6, 4989 }, { 4990 .compatible = "edt,etm043080dh6gp", 4991 .data = &edt_etm043080dh6gp, 4992 }, { 4993 .compatible = "edt,etm0430g0dh6", 4994 .data = &edt_etm0430g0dh6, 4995 }, { 4996 .compatible = "edt,et057090dhu", 4997 .data = &edt_et057090dhu, 4998 }, { 4999 .compatible = "edt,et070080dh6", 5000 .data = &edt_etm0700g0dh6, 5001 }, { 5002 .compatible = "edt,etm0700g0dh6", 5003 .data = &edt_etm0700g0dh6, 5004 }, { 5005 .compatible = "edt,etm0700g0bdh6", 5006 .data = &edt_etm0700g0bdh6, 5007 }, { 5008 .compatible = "edt,etm0700g0edh6", 5009 .data = &edt_etm0700g0bdh6, 5010 }, { 5011 .compatible = "edt,etml0700y5dha", 5012 .data = &edt_etml0700y5dha, 5013 }, { 5014 .compatible = "edt,etml1010g3dra", 5015 .data = &edt_etml1010g3dra, 5016 }, { 5017 .compatible = "edt,etmv570g2dhu", 5018 .data = &edt_etmv570g2dhu, 5019 }, { 5020 .compatible = "eink,vb3300-kca", 5021 .data = &eink_vb3300_kca, 5022 }, { 5023 .compatible = "evervision,vgg644804", 5024 .data = &evervision_vgg644804, 5025 }, { 5026 .compatible = "evervision,vgg804821", 5027 .data = &evervision_vgg804821, 5028 }, { 5029 .compatible = "foxlink,fl500wvr00-a0t", 5030 .data = &foxlink_fl500wvr00_a0t, 5031 }, { 5032 .compatible = "frida,frd350h54004", 5033 .data = &frida_frd350h54004, 5034 }, { 5035 .compatible = "friendlyarm,hd702e", 5036 .data = &friendlyarm_hd702e, 5037 }, { 5038 .compatible = "giantplus,gpg482739qs5", 5039 .data = &giantplus_gpg482739qs5 5040 }, { 5041 .compatible = "giantplus,gpm940b0", 5042 .data = &giantplus_gpm940b0, 5043 }, { 5044 .compatible = "hannstar,hsd070pww1", 5045 .data = &hannstar_hsd070pww1, 5046 }, { 5047 .compatible = "hannstar,hsd100pxn1", 5048 .data = &hannstar_hsd100pxn1, 5049 }, { 5050 .compatible = "hannstar,hsd101pww2", 5051 .data = &hannstar_hsd101pww2, 5052 }, { 5053 .compatible = "hit,tx23d38vm0caa", 5054 .data = &hitachi_tx23d38vm0caa 5055 }, { 5056 .compatible = "innolux,at043tn24", 5057 .data = &innolux_at043tn24, 5058 }, { 5059 .compatible = "innolux,at070tn92", 5060 .data = &innolux_at070tn92, 5061 }, { 5062 .compatible = "innolux,g070ace-l01", 5063 .data = &innolux_g070ace_l01, 5064 }, { 5065 .compatible = "innolux,g070ace-lh3", 5066 .data = &innolux_g070ace_lh3, 5067 }, { 5068 .compatible = "innolux,g070y2-l01", 5069 .data = &innolux_g070y2_l01, 5070 }, { 5071 .compatible = "innolux,g070y2-t02", 5072 .data = &innolux_g070y2_t02, 5073 }, { 5074 .compatible = "innolux,g101ice-l01", 5075 .data = &innolux_g101ice_l01 5076 }, { 5077 .compatible = "innolux,g121i1-l01", 5078 .data = &innolux_g121i1_l01 5079 }, { 5080 .compatible = "innolux,g121x1-l03", 5081 .data = &innolux_g121x1_l03, 5082 }, { 5083 .compatible = "innolux,g121xce-l01", 5084 .data = &innolux_g121xce_l01, 5085 }, { 5086 .compatible = "innolux,g156hce-l01", 5087 .data = &innolux_g156hce_l01, 5088 }, { 5089 .compatible = "innolux,n156bge-l21", 5090 .data = &innolux_n156bge_l21, 5091 }, { 5092 .compatible = "innolux,zj070na-01p", 5093 .data = &innolux_zj070na_01p, 5094 }, { 5095 .compatible = "koe,tx14d24vm1bpa", 5096 .data = &koe_tx14d24vm1bpa, 5097 }, { 5098 .compatible = "koe,tx26d202vm0bwa", 5099 .data = &koe_tx26d202vm0bwa, 5100 }, { 5101 .compatible = "koe,tx31d200vm0baa", 5102 .data = &koe_tx31d200vm0baa, 5103 }, { 5104 .compatible = "kyo,tcg121xglp", 5105 .data = &kyo_tcg121xglp, 5106 }, { 5107 .compatible = "lemaker,bl035-rgb-002", 5108 .data = &lemaker_bl035_rgb_002, 5109 }, { 5110 .compatible = "lg,lb070wv8", 5111 .data = &lg_lb070wv8, 5112 }, { 5113 .compatible = "lincolntech,lcd185-101ct", 5114 .data = &lincolntech_lcd185_101ct, 5115 }, { 5116 .compatible = "logicpd,type28", 5117 .data = &logicpd_type_28, 5118 }, { 5119 .compatible = "logictechno,lt161010-2nhc", 5120 .data = &logictechno_lt161010_2nh, 5121 }, { 5122 .compatible = "logictechno,lt161010-2nhr", 5123 .data = &logictechno_lt161010_2nh, 5124 }, { 5125 .compatible = "logictechno,lt170410-2whc", 5126 .data = &logictechno_lt170410_2whc, 5127 }, { 5128 .compatible = "logictechno,lttd800480070-l2rt", 5129 .data = &logictechno_lttd800480070_l2rt, 5130 }, { 5131 .compatible = "logictechno,lttd800480070-l6wh-rt", 5132 .data = &logictechno_lttd800480070_l6wh_rt, 5133 }, { 5134 .compatible = "microtips,mf-101hiebcaf0", 5135 .data = µtips_mf_101hiebcaf0_c, 5136 }, { 5137 .compatible = "microtips,mf-103hieb0ga0", 5138 .data = µtips_mf_103hieb0ga0, 5139 }, { 5140 .compatible = "mitsubishi,aa070mc01-ca1", 5141 .data = &mitsubishi_aa070mc01, 5142 }, { 5143 .compatible = "mitsubishi,aa084xe01", 5144 .data = &mitsubishi_aa084xe01, 5145 }, { 5146 .compatible = "multi-inno,mi0700a2t-30", 5147 .data = &multi_inno_mi0700a2t_30, 5148 }, { 5149 .compatible = "multi-inno,mi0700s4t-6", 5150 .data = &multi_inno_mi0700s4t_6, 5151 }, { 5152 .compatible = "multi-inno,mi0800ft-9", 5153 .data = &multi_inno_mi0800ft_9, 5154 }, { 5155 .compatible = "multi-inno,mi1010ait-1cp", 5156 .data = &multi_inno_mi1010ait_1cp, 5157 }, { 5158 .compatible = "multi-inno,mi1010z1t-1cp11", 5159 .data = &multi_inno_mi1010z1t_1cp11, 5160 }, { 5161 .compatible = "nec,nl12880bc20-05", 5162 .data = &nec_nl12880bc20_05, 5163 }, { 5164 .compatible = "nec,nl4827hc19-05b", 5165 .data = &nec_nl4827hc19_05b, 5166 }, { 5167 .compatible = "netron-dy,e231732", 5168 .data = &netron_dy_e231732, 5169 }, { 5170 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 5171 .data = &newhaven_nhd_43_480272ef_atxl, 5172 }, { 5173 .compatible = "nlt,nl13676bc25-03f", 5174 .data = &nlt_nl13676bc25_03f, 5175 }, { 5176 .compatible = "nlt,nl192108ac18-02d", 5177 .data = &nlt_nl192108ac18_02d, 5178 }, { 5179 .compatible = "nvd,9128", 5180 .data = &nvd_9128, 5181 }, { 5182 .compatible = "okaya,rs800480t-7x0gp", 5183 .data = &okaya_rs800480t_7x0gp, 5184 }, { 5185 .compatible = "olimex,lcd-olinuxino-43-ts", 5186 .data = &olimex_lcd_olinuxino_43ts, 5187 }, { 5188 .compatible = "ontat,kd50g21-40nt-a1", 5189 .data = &ontat_kd50g21_40nt_a1, 5190 }, { 5191 .compatible = "ontat,yx700wv03", 5192 .data = &ontat_yx700wv03, 5193 }, { 5194 .compatible = "ortustech,com37h3m05dtc", 5195 .data = &ortustech_com37h3m, 5196 }, { 5197 .compatible = "ortustech,com37h3m99dtc", 5198 .data = &ortustech_com37h3m, 5199 }, { 5200 .compatible = "ortustech,com43h4m85ulc", 5201 .data = &ortustech_com43h4m85ulc, 5202 }, { 5203 .compatible = "osddisplays,osd070t1718-19ts", 5204 .data = &osddisplays_osd070t1718_19ts, 5205 }, { 5206 .compatible = "pda,91-00156-a0", 5207 .data = &pda_91_00156_a0, 5208 }, { 5209 .compatible = "powertip,ph128800t004-zza01", 5210 .data = &powertip_ph128800t004_zza01, 5211 }, { 5212 .compatible = "powertip,ph128800t006-zhc01", 5213 .data = &powertip_ph128800t006_zhc01, 5214 }, { 5215 .compatible = "powertip,ph800480t013-idf02", 5216 .data = &powertip_ph800480t013_idf02, 5217 }, { 5218 .compatible = "primeview,pm070wl4", 5219 .data = &primeview_pm070wl4, 5220 }, { 5221 .compatible = "qiaodian,qd43003c0-40", 5222 .data = &qd43003c0_40, 5223 }, { 5224 .compatible = "qishenglong,gopher2b-lcd", 5225 .data = &qishenglong_gopher2b_lcd, 5226 }, { 5227 .compatible = "rocktech,rk043fn48h", 5228 .data = &rocktech_rk043fn48h, 5229 }, { 5230 .compatible = "rocktech,rk070er9427", 5231 .data = &rocktech_rk070er9427, 5232 }, { 5233 .compatible = "rocktech,rk101ii01d-ct", 5234 .data = &rocktech_rk101ii01d_ct, 5235 }, { 5236 .compatible = "samsung,ltl101al01", 5237 .data = &samsung_ltl101al01, 5238 }, { 5239 .compatible = "samsung,ltn101nt05", 5240 .data = &samsung_ltn101nt05, 5241 }, { 5242 .compatible = "satoz,sat050at40h12r2", 5243 .data = &satoz_sat050at40h12r2, 5244 }, { 5245 .compatible = "sharp,lq035q7db03", 5246 .data = &sharp_lq035q7db03, 5247 }, { 5248 .compatible = "sharp,lq070y3dg3b", 5249 .data = &sharp_lq070y3dg3b, 5250 }, { 5251 .compatible = "sharp,lq101k1ly04", 5252 .data = &sharp_lq101k1ly04, 5253 }, { 5254 .compatible = "sharp,ls020b1dd01d", 5255 .data = &sharp_ls020b1dd01d, 5256 }, { 5257 .compatible = "shelly,sca07010-bfn-lnn", 5258 .data = &shelly_sca07010_bfn_lnn, 5259 }, { 5260 .compatible = "starry,kr070pe2t", 5261 .data = &starry_kr070pe2t, 5262 }, { 5263 .compatible = "startek,kd070wvfpa", 5264 .data = &startek_kd070wvfpa, 5265 }, { 5266 .compatible = "team-source-display,tst043015cmhx", 5267 .data = &tsd_tst043015cmhx, 5268 }, { 5269 .compatible = "tfc,s9700rtwv43tr-01b", 5270 .data = &tfc_s9700rtwv43tr_01b, 5271 }, { 5272 .compatible = "tianma,tm070jdhg30", 5273 .data = &tianma_tm070jdhg30, 5274 }, { 5275 .compatible = "tianma,tm070jdhg34-00", 5276 .data = &tianma_tm070jdhg34_00, 5277 }, { 5278 .compatible = "tianma,tm070jvhg33", 5279 .data = &tianma_tm070jvhg33, 5280 }, { 5281 .compatible = "tianma,tm070rvhg71", 5282 .data = &tianma_tm070rvhg71, 5283 }, { 5284 .compatible = "ti,nspire-cx-lcd-panel", 5285 .data = &ti_nspire_cx_lcd_panel, 5286 }, { 5287 .compatible = "ti,nspire-classic-lcd-panel", 5288 .data = &ti_nspire_classic_lcd_panel, 5289 }, { 5290 .compatible = "toshiba,lt089ac29000", 5291 .data = &toshiba_lt089ac29000, 5292 }, { 5293 .compatible = "topland,tian-g07017-01", 5294 .data = &topland_tian_g07017_01, 5295 }, { 5296 .compatible = "tpk,f07a-0102", 5297 .data = &tpk_f07a_0102, 5298 }, { 5299 .compatible = "tpk,f10a-0102", 5300 .data = &tpk_f10a_0102, 5301 }, { 5302 .compatible = "urt,umsh-8596md-t", 5303 .data = &urt_umsh_8596md_parallel, 5304 }, { 5305 .compatible = "urt,umsh-8596md-1t", 5306 .data = &urt_umsh_8596md_parallel, 5307 }, { 5308 .compatible = "urt,umsh-8596md-7t", 5309 .data = &urt_umsh_8596md_parallel, 5310 }, { 5311 .compatible = "urt,umsh-8596md-11t", 5312 .data = &urt_umsh_8596md_lvds, 5313 }, { 5314 .compatible = "urt,umsh-8596md-19t", 5315 .data = &urt_umsh_8596md_lvds, 5316 }, { 5317 .compatible = "urt,umsh-8596md-20t", 5318 .data = &urt_umsh_8596md_parallel, 5319 }, { 5320 .compatible = "vivax,tpc9150-panel", 5321 .data = &vivax_tpc9150_panel, 5322 }, { 5323 .compatible = "vxt,vl050-8048nt-c01", 5324 .data = &vl050_8048nt_c01, 5325 }, { 5326 .compatible = "winstar,wf35ltiacd", 5327 .data = &winstar_wf35ltiacd, 5328 }, { 5329 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 5330 .data = &yes_optoelectronics_ytc700tlag_05_201c, 5331 }, { 5332 .compatible = "microchip,ac69t88a", 5333 .data = &mchp_ac69t88a, 5334 }, { 5335 /* Must be the last entry */ 5336 .compatible = "panel-dpi", 5337 .data = &panel_dpi, 5338 }, { 5339 /* sentinel */ 5340 } 5341 }; 5342 MODULE_DEVICE_TABLE(of, platform_of_match); 5343 5344 static int panel_simple_platform_probe(struct platform_device *pdev) 5345 { 5346 const struct panel_desc *desc; 5347 5348 desc = of_device_get_match_data(&pdev->dev); 5349 if (!desc) 5350 return -ENODEV; 5351 5352 return panel_simple_probe(&pdev->dev, desc); 5353 } 5354 5355 static void panel_simple_platform_remove(struct platform_device *pdev) 5356 { 5357 panel_simple_remove(&pdev->dev); 5358 } 5359 5360 static void panel_simple_platform_shutdown(struct platform_device *pdev) 5361 { 5362 panel_simple_shutdown(&pdev->dev); 5363 } 5364 5365 static const struct dev_pm_ops panel_simple_pm_ops = { 5366 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 5367 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5368 pm_runtime_force_resume) 5369 }; 5370 5371 static struct platform_driver panel_simple_platform_driver = { 5372 .driver = { 5373 .name = "panel-simple", 5374 .of_match_table = platform_of_match, 5375 .pm = &panel_simple_pm_ops, 5376 }, 5377 .probe = panel_simple_platform_probe, 5378 .remove = panel_simple_platform_remove, 5379 .shutdown = panel_simple_platform_shutdown, 5380 }; 5381 5382 struct panel_desc_dsi { 5383 struct panel_desc desc; 5384 5385 unsigned long flags; 5386 enum mipi_dsi_pixel_format format; 5387 unsigned int lanes; 5388 }; 5389 5390 static const struct drm_display_mode auo_b080uan01_mode = { 5391 .clock = 154500, 5392 .hdisplay = 1200, 5393 .hsync_start = 1200 + 62, 5394 .hsync_end = 1200 + 62 + 4, 5395 .htotal = 1200 + 62 + 4 + 62, 5396 .vdisplay = 1920, 5397 .vsync_start = 1920 + 9, 5398 .vsync_end = 1920 + 9 + 2, 5399 .vtotal = 1920 + 9 + 2 + 8, 5400 }; 5401 5402 static const struct panel_desc_dsi auo_b080uan01 = { 5403 .desc = { 5404 .modes = &auo_b080uan01_mode, 5405 .num_modes = 1, 5406 .bpc = 8, 5407 .size = { 5408 .width = 108, 5409 .height = 272, 5410 }, 5411 .connector_type = DRM_MODE_CONNECTOR_DSI, 5412 }, 5413 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5414 .format = MIPI_DSI_FMT_RGB888, 5415 .lanes = 4, 5416 }; 5417 5418 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5419 .clock = 160000, 5420 .hdisplay = 1200, 5421 .hsync_start = 1200 + 120, 5422 .hsync_end = 1200 + 120 + 20, 5423 .htotal = 1200 + 120 + 20 + 21, 5424 .vdisplay = 1920, 5425 .vsync_start = 1920 + 21, 5426 .vsync_end = 1920 + 21 + 3, 5427 .vtotal = 1920 + 21 + 3 + 18, 5428 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5429 }; 5430 5431 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5432 .desc = { 5433 .modes = &boe_tv080wum_nl0_mode, 5434 .num_modes = 1, 5435 .size = { 5436 .width = 107, 5437 .height = 172, 5438 }, 5439 .connector_type = DRM_MODE_CONNECTOR_DSI, 5440 }, 5441 .flags = MIPI_DSI_MODE_VIDEO | 5442 MIPI_DSI_MODE_VIDEO_BURST | 5443 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5444 .format = MIPI_DSI_FMT_RGB888, 5445 .lanes = 4, 5446 }; 5447 5448 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 5449 .clock = 71000, 5450 .hdisplay = 800, 5451 .hsync_start = 800 + 32, 5452 .hsync_end = 800 + 32 + 1, 5453 .htotal = 800 + 32 + 1 + 57, 5454 .vdisplay = 1280, 5455 .vsync_start = 1280 + 28, 5456 .vsync_end = 1280 + 28 + 1, 5457 .vtotal = 1280 + 28 + 1 + 14, 5458 }; 5459 5460 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 5461 .desc = { 5462 .modes = &lg_ld070wx3_sl01_mode, 5463 .num_modes = 1, 5464 .bpc = 8, 5465 .size = { 5466 .width = 94, 5467 .height = 151, 5468 }, 5469 .connector_type = DRM_MODE_CONNECTOR_DSI, 5470 }, 5471 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5472 .format = MIPI_DSI_FMT_RGB888, 5473 .lanes = 4, 5474 }; 5475 5476 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5477 .clock = 67000, 5478 .hdisplay = 720, 5479 .hsync_start = 720 + 12, 5480 .hsync_end = 720 + 12 + 4, 5481 .htotal = 720 + 12 + 4 + 112, 5482 .vdisplay = 1280, 5483 .vsync_start = 1280 + 8, 5484 .vsync_end = 1280 + 8 + 4, 5485 .vtotal = 1280 + 8 + 4 + 12, 5486 }; 5487 5488 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5489 .desc = { 5490 .modes = &lg_lh500wx1_sd03_mode, 5491 .num_modes = 1, 5492 .bpc = 8, 5493 .size = { 5494 .width = 62, 5495 .height = 110, 5496 }, 5497 .connector_type = DRM_MODE_CONNECTOR_DSI, 5498 }, 5499 .flags = MIPI_DSI_MODE_VIDEO, 5500 .format = MIPI_DSI_FMT_RGB888, 5501 .lanes = 4, 5502 }; 5503 5504 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5505 .clock = 157200, 5506 .hdisplay = 1920, 5507 .hsync_start = 1920 + 154, 5508 .hsync_end = 1920 + 154 + 16, 5509 .htotal = 1920 + 154 + 16 + 32, 5510 .vdisplay = 1200, 5511 .vsync_start = 1200 + 17, 5512 .vsync_end = 1200 + 17 + 2, 5513 .vtotal = 1200 + 17 + 2 + 16, 5514 }; 5515 5516 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5517 .desc = { 5518 .modes = &panasonic_vvx10f004b00_mode, 5519 .num_modes = 1, 5520 .bpc = 8, 5521 .size = { 5522 .width = 217, 5523 .height = 136, 5524 }, 5525 .connector_type = DRM_MODE_CONNECTOR_DSI, 5526 }, 5527 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5528 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5529 .format = MIPI_DSI_FMT_RGB888, 5530 .lanes = 4, 5531 }; 5532 5533 static const struct drm_display_mode lg_acx467akm_7_mode = { 5534 .clock = 150000, 5535 .hdisplay = 1080, 5536 .hsync_start = 1080 + 2, 5537 .hsync_end = 1080 + 2 + 2, 5538 .htotal = 1080 + 2 + 2 + 2, 5539 .vdisplay = 1920, 5540 .vsync_start = 1920 + 2, 5541 .vsync_end = 1920 + 2 + 2, 5542 .vtotal = 1920 + 2 + 2 + 2, 5543 }; 5544 5545 static const struct panel_desc_dsi lg_acx467akm_7 = { 5546 .desc = { 5547 .modes = &lg_acx467akm_7_mode, 5548 .num_modes = 1, 5549 .bpc = 8, 5550 .size = { 5551 .width = 62, 5552 .height = 110, 5553 }, 5554 .connector_type = DRM_MODE_CONNECTOR_DSI, 5555 }, 5556 .flags = 0, 5557 .format = MIPI_DSI_FMT_RGB888, 5558 .lanes = 4, 5559 }; 5560 5561 static const struct drm_display_mode osd101t2045_53ts_mode = { 5562 .clock = 154500, 5563 .hdisplay = 1920, 5564 .hsync_start = 1920 + 112, 5565 .hsync_end = 1920 + 112 + 16, 5566 .htotal = 1920 + 112 + 16 + 32, 5567 .vdisplay = 1200, 5568 .vsync_start = 1200 + 16, 5569 .vsync_end = 1200 + 16 + 2, 5570 .vtotal = 1200 + 16 + 2 + 16, 5571 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5572 }; 5573 5574 static const struct panel_desc_dsi osd101t2045_53ts = { 5575 .desc = { 5576 .modes = &osd101t2045_53ts_mode, 5577 .num_modes = 1, 5578 .bpc = 8, 5579 .size = { 5580 .width = 217, 5581 .height = 136, 5582 }, 5583 .connector_type = DRM_MODE_CONNECTOR_DSI, 5584 }, 5585 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5586 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5587 MIPI_DSI_MODE_NO_EOT_PACKET, 5588 .format = MIPI_DSI_FMT_RGB888, 5589 .lanes = 4, 5590 }; 5591 5592 static const struct of_device_id dsi_of_match[] = { 5593 { 5594 .compatible = "auo,b080uan01", 5595 .data = &auo_b080uan01 5596 }, { 5597 .compatible = "boe,tv080wum-nl0", 5598 .data = &boe_tv080wum_nl0 5599 }, { 5600 .compatible = "lg,ld070wx3-sl01", 5601 .data = &lg_ld070wx3_sl01 5602 }, { 5603 .compatible = "lg,lh500wx1-sd03", 5604 .data = &lg_lh500wx1_sd03 5605 }, { 5606 .compatible = "panasonic,vvx10f004b00", 5607 .data = &panasonic_vvx10f004b00 5608 }, { 5609 .compatible = "lg,acx467akm-7", 5610 .data = &lg_acx467akm_7 5611 }, { 5612 .compatible = "osddisplays,osd101t2045-53ts", 5613 .data = &osd101t2045_53ts 5614 }, { 5615 /* sentinel */ 5616 } 5617 }; 5618 MODULE_DEVICE_TABLE(of, dsi_of_match); 5619 5620 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5621 { 5622 const struct panel_desc_dsi *desc; 5623 int err; 5624 5625 desc = of_device_get_match_data(&dsi->dev); 5626 if (!desc) 5627 return -ENODEV; 5628 5629 err = panel_simple_probe(&dsi->dev, &desc->desc); 5630 if (err < 0) 5631 return err; 5632 5633 dsi->mode_flags = desc->flags; 5634 dsi->format = desc->format; 5635 dsi->lanes = desc->lanes; 5636 5637 err = mipi_dsi_attach(dsi); 5638 if (err) { 5639 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5640 5641 drm_panel_remove(&panel->base); 5642 } 5643 5644 return err; 5645 } 5646 5647 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5648 { 5649 int err; 5650 5651 err = mipi_dsi_detach(dsi); 5652 if (err < 0) 5653 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5654 5655 panel_simple_remove(&dsi->dev); 5656 } 5657 5658 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5659 { 5660 panel_simple_shutdown(&dsi->dev); 5661 } 5662 5663 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5664 .driver = { 5665 .name = "panel-simple-dsi", 5666 .of_match_table = dsi_of_match, 5667 .pm = &panel_simple_pm_ops, 5668 }, 5669 .probe = panel_simple_dsi_probe, 5670 .remove = panel_simple_dsi_remove, 5671 .shutdown = panel_simple_dsi_shutdown, 5672 }; 5673 5674 static int __init panel_simple_init(void) 5675 { 5676 int err; 5677 5678 err = platform_driver_register(&panel_simple_platform_driver); 5679 if (err < 0) 5680 return err; 5681 5682 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5683 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5684 if (err < 0) 5685 goto err_did_platform_register; 5686 } 5687 5688 return 0; 5689 5690 err_did_platform_register: 5691 platform_driver_unregister(&panel_simple_platform_driver); 5692 5693 return err; 5694 } 5695 module_init(panel_simple_init); 5696 5697 static void __exit panel_simple_exit(void) 5698 { 5699 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5700 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5701 5702 platform_driver_unregister(&panel_simple_platform_driver); 5703 } 5704 module_exit(panel_simple_exit); 5705 5706 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5707 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5708 MODULE_LICENSE("GPL and additional rights"); 5709