1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/module.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/regulator/consumer.h> 31 32 #include <video/display_timing.h> 33 #include <video/of_display_timing.h> 34 #include <video/videomode.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_device.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_mipi_dsi.h> 40 #include <drm/drm_panel.h> 41 42 /** 43 * struct panel_desc - Describes a simple panel. 44 */ 45 struct panel_desc { 46 /** 47 * @modes: Pointer to array of fixed modes appropriate for this panel. 48 * 49 * If only one mode then this can just be the address of the mode. 50 * NOTE: cannot be used with "timings" and also if this is specified 51 * then you cannot override the mode in the device tree. 52 */ 53 const struct drm_display_mode *modes; 54 55 /** @num_modes: Number of elements in modes array. */ 56 unsigned int num_modes; 57 58 /** 59 * @timings: Pointer to array of display timings 60 * 61 * NOTE: cannot be used with "modes" and also these will be used to 62 * validate a device tree override if one is present. 63 */ 64 const struct display_timing *timings; 65 66 /** @num_timings: Number of elements in timings array. */ 67 unsigned int num_timings; 68 69 /** @bpc: Bits per color. */ 70 unsigned int bpc; 71 72 /** @size: Structure containing the physical size of this panel. */ 73 struct { 74 /** 75 * @size.width: Width (in mm) of the active display area. 76 */ 77 unsigned int width; 78 79 /** 80 * @size.height: Height (in mm) of the active display area. 81 */ 82 unsigned int height; 83 } size; 84 85 /** @delay: Structure containing various delay values for this panel. */ 86 struct { 87 /** 88 * @delay.prepare: Time for the panel to become ready. 89 * 90 * The time (in milliseconds) that it takes for the panel to 91 * become ready and start receiving video data 92 */ 93 unsigned int prepare; 94 95 /** 96 * @delay.enable: Time for the panel to display a valid frame. 97 * 98 * The time (in milliseconds) that it takes for the panel to 99 * display the first valid frame after starting to receive 100 * video data. 101 */ 102 unsigned int enable; 103 104 /** 105 * @delay.disable: Time for the panel to turn the display off. 106 * 107 * The time (in milliseconds) that it takes for the panel to 108 * turn the display off (no content is visible). 109 */ 110 unsigned int disable; 111 112 /** 113 * @delay.unprepare: Time to power down completely. 114 * 115 * The time (in milliseconds) that it takes for the panel 116 * to power itself down completely. 117 * 118 * This time is used to prevent a future "prepare" from 119 * starting until at least this many milliseconds has passed. 120 * If at prepare time less time has passed since unprepare 121 * finished, the driver waits for the remaining time. 122 */ 123 unsigned int unprepare; 124 } delay; 125 126 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 127 u32 bus_format; 128 129 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 130 u32 bus_flags; 131 132 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 133 int connector_type; 134 }; 135 136 struct panel_simple { 137 struct drm_panel base; 138 bool enabled; 139 140 bool prepared; 141 142 ktime_t prepared_time; 143 ktime_t unprepared_time; 144 145 const struct panel_desc *desc; 146 147 struct regulator *supply; 148 struct i2c_adapter *ddc; 149 150 struct gpio_desc *enable_gpio; 151 152 struct edid *edid; 153 154 struct drm_display_mode override_mode; 155 156 enum drm_panel_orientation orientation; 157 }; 158 159 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 160 { 161 return container_of(panel, struct panel_simple, base); 162 } 163 164 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 165 struct drm_connector *connector) 166 { 167 struct drm_display_mode *mode; 168 unsigned int i, num = 0; 169 170 for (i = 0; i < panel->desc->num_timings; i++) { 171 const struct display_timing *dt = &panel->desc->timings[i]; 172 struct videomode vm; 173 174 videomode_from_timing(dt, &vm); 175 mode = drm_mode_create(connector->dev); 176 if (!mode) { 177 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 178 dt->hactive.typ, dt->vactive.typ); 179 continue; 180 } 181 182 drm_display_mode_from_videomode(&vm, mode); 183 184 mode->type |= DRM_MODE_TYPE_DRIVER; 185 186 if (panel->desc->num_timings == 1) 187 mode->type |= DRM_MODE_TYPE_PREFERRED; 188 189 drm_mode_probed_add(connector, mode); 190 num++; 191 } 192 193 return num; 194 } 195 196 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 197 struct drm_connector *connector) 198 { 199 struct drm_display_mode *mode; 200 unsigned int i, num = 0; 201 202 for (i = 0; i < panel->desc->num_modes; i++) { 203 const struct drm_display_mode *m = &panel->desc->modes[i]; 204 205 mode = drm_mode_duplicate(connector->dev, m); 206 if (!mode) { 207 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 208 m->hdisplay, m->vdisplay, 209 drm_mode_vrefresh(m)); 210 continue; 211 } 212 213 mode->type |= DRM_MODE_TYPE_DRIVER; 214 215 if (panel->desc->num_modes == 1) 216 mode->type |= DRM_MODE_TYPE_PREFERRED; 217 218 drm_mode_set_name(mode); 219 220 drm_mode_probed_add(connector, mode); 221 num++; 222 } 223 224 return num; 225 } 226 227 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 228 struct drm_connector *connector) 229 { 230 struct drm_display_mode *mode; 231 bool has_override = panel->override_mode.type; 232 unsigned int num = 0; 233 234 if (!panel->desc) 235 return 0; 236 237 if (has_override) { 238 mode = drm_mode_duplicate(connector->dev, 239 &panel->override_mode); 240 if (mode) { 241 drm_mode_probed_add(connector, mode); 242 num = 1; 243 } else { 244 dev_err(panel->base.dev, "failed to add override mode\n"); 245 } 246 } 247 248 /* Only add timings if override was not there or failed to validate */ 249 if (num == 0 && panel->desc->num_timings) 250 num = panel_simple_get_timings_modes(panel, connector); 251 252 /* 253 * Only add fixed modes if timings/override added no mode. 254 * 255 * We should only ever have either the display timings specified 256 * or a fixed mode. Anything else is rather bogus. 257 */ 258 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 259 if (num == 0) 260 num = panel_simple_get_display_modes(panel, connector); 261 262 connector->display_info.bpc = panel->desc->bpc; 263 connector->display_info.width_mm = panel->desc->size.width; 264 connector->display_info.height_mm = panel->desc->size.height; 265 if (panel->desc->bus_format) 266 drm_display_info_set_bus_formats(&connector->display_info, 267 &panel->desc->bus_format, 1); 268 connector->display_info.bus_flags = panel->desc->bus_flags; 269 270 return num; 271 } 272 273 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 274 { 275 ktime_t now_ktime, min_ktime; 276 277 if (!min_ms) 278 return; 279 280 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 281 now_ktime = ktime_get(); 282 283 if (ktime_before(now_ktime, min_ktime)) 284 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 285 } 286 287 static int panel_simple_disable(struct drm_panel *panel) 288 { 289 struct panel_simple *p = to_panel_simple(panel); 290 291 if (!p->enabled) 292 return 0; 293 294 if (p->desc->delay.disable) 295 msleep(p->desc->delay.disable); 296 297 p->enabled = false; 298 299 return 0; 300 } 301 302 static int panel_simple_suspend(struct device *dev) 303 { 304 struct panel_simple *p = dev_get_drvdata(dev); 305 306 gpiod_set_value_cansleep(p->enable_gpio, 0); 307 regulator_disable(p->supply); 308 p->unprepared_time = ktime_get(); 309 310 kfree(p->edid); 311 p->edid = NULL; 312 313 return 0; 314 } 315 316 static int panel_simple_unprepare(struct drm_panel *panel) 317 { 318 struct panel_simple *p = to_panel_simple(panel); 319 int ret; 320 321 /* Unpreparing when already unprepared is a no-op */ 322 if (!p->prepared) 323 return 0; 324 325 pm_runtime_mark_last_busy(panel->dev); 326 ret = pm_runtime_put_autosuspend(panel->dev); 327 if (ret < 0) 328 return ret; 329 p->prepared = false; 330 331 return 0; 332 } 333 334 static int panel_simple_resume(struct device *dev) 335 { 336 struct panel_simple *p = dev_get_drvdata(dev); 337 int err; 338 339 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 340 341 err = regulator_enable(p->supply); 342 if (err < 0) { 343 dev_err(dev, "failed to enable supply: %d\n", err); 344 return err; 345 } 346 347 gpiod_set_value_cansleep(p->enable_gpio, 1); 348 349 if (p->desc->delay.prepare) 350 msleep(p->desc->delay.prepare); 351 352 p->prepared_time = ktime_get(); 353 354 return 0; 355 } 356 357 static int panel_simple_prepare(struct drm_panel *panel) 358 { 359 struct panel_simple *p = to_panel_simple(panel); 360 int ret; 361 362 /* Preparing when already prepared is a no-op */ 363 if (p->prepared) 364 return 0; 365 366 ret = pm_runtime_get_sync(panel->dev); 367 if (ret < 0) { 368 pm_runtime_put_autosuspend(panel->dev); 369 return ret; 370 } 371 372 p->prepared = true; 373 374 return 0; 375 } 376 377 static int panel_simple_enable(struct drm_panel *panel) 378 { 379 struct panel_simple *p = to_panel_simple(panel); 380 381 if (p->enabled) 382 return 0; 383 384 if (p->desc->delay.enable) 385 msleep(p->desc->delay.enable); 386 387 p->enabled = true; 388 389 return 0; 390 } 391 392 static int panel_simple_get_modes(struct drm_panel *panel, 393 struct drm_connector *connector) 394 { 395 struct panel_simple *p = to_panel_simple(panel); 396 int num = 0; 397 398 /* probe EDID if a DDC bus is available */ 399 if (p->ddc) { 400 pm_runtime_get_sync(panel->dev); 401 402 if (!p->edid) 403 p->edid = drm_get_edid(connector, p->ddc); 404 405 if (p->edid) 406 num += drm_add_edid_modes(connector, p->edid); 407 408 pm_runtime_mark_last_busy(panel->dev); 409 pm_runtime_put_autosuspend(panel->dev); 410 } 411 412 /* add hard-coded panel modes */ 413 num += panel_simple_get_non_edid_modes(p, connector); 414 415 /* 416 * TODO: Remove once all drm drivers call 417 * drm_connector_set_orientation_from_panel() 418 */ 419 drm_connector_set_panel_orientation(connector, p->orientation); 420 421 return num; 422 } 423 424 static int panel_simple_get_timings(struct drm_panel *panel, 425 unsigned int num_timings, 426 struct display_timing *timings) 427 { 428 struct panel_simple *p = to_panel_simple(panel); 429 unsigned int i; 430 431 if (p->desc->num_timings < num_timings) 432 num_timings = p->desc->num_timings; 433 434 if (timings) 435 for (i = 0; i < num_timings; i++) 436 timings[i] = p->desc->timings[i]; 437 438 return p->desc->num_timings; 439 } 440 441 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 442 { 443 struct panel_simple *p = to_panel_simple(panel); 444 445 return p->orientation; 446 } 447 448 static const struct drm_panel_funcs panel_simple_funcs = { 449 .disable = panel_simple_disable, 450 .unprepare = panel_simple_unprepare, 451 .prepare = panel_simple_prepare, 452 .enable = panel_simple_enable, 453 .get_modes = panel_simple_get_modes, 454 .get_orientation = panel_simple_get_orientation, 455 .get_timings = panel_simple_get_timings, 456 }; 457 458 static struct panel_desc panel_dpi; 459 460 static int panel_dpi_probe(struct device *dev, 461 struct panel_simple *panel) 462 { 463 struct display_timing *timing; 464 const struct device_node *np; 465 struct panel_desc *desc; 466 unsigned int bus_flags; 467 struct videomode vm; 468 int ret; 469 470 np = dev->of_node; 471 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 472 if (!desc) 473 return -ENOMEM; 474 475 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 476 if (!timing) 477 return -ENOMEM; 478 479 ret = of_get_display_timing(np, "panel-timing", timing); 480 if (ret < 0) { 481 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 482 np); 483 return ret; 484 } 485 486 desc->timings = timing; 487 desc->num_timings = 1; 488 489 of_property_read_u32(np, "width-mm", &desc->size.width); 490 of_property_read_u32(np, "height-mm", &desc->size.height); 491 492 /* Extract bus_flags from display_timing */ 493 bus_flags = 0; 494 vm.flags = timing->flags; 495 drm_bus_flags_from_videomode(&vm, &bus_flags); 496 desc->bus_flags = bus_flags; 497 498 /* We do not know the connector for the DT node, so guess it */ 499 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 500 501 panel->desc = desc; 502 503 return 0; 504 } 505 506 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 507 (to_check->field.typ >= bounds->field.min && \ 508 to_check->field.typ <= bounds->field.max) 509 static void panel_simple_parse_panel_timing_node(struct device *dev, 510 struct panel_simple *panel, 511 const struct display_timing *ot) 512 { 513 const struct panel_desc *desc = panel->desc; 514 struct videomode vm; 515 unsigned int i; 516 517 if (WARN_ON(desc->num_modes)) { 518 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 519 return; 520 } 521 if (WARN_ON(!desc->num_timings)) { 522 dev_err(dev, "Reject override mode: no timings specified\n"); 523 return; 524 } 525 526 for (i = 0; i < panel->desc->num_timings; i++) { 527 const struct display_timing *dt = &panel->desc->timings[i]; 528 529 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 537 continue; 538 539 if (ot->flags != dt->flags) 540 continue; 541 542 videomode_from_timing(ot, &vm); 543 drm_display_mode_from_videomode(&vm, &panel->override_mode); 544 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 545 DRM_MODE_TYPE_PREFERRED; 546 break; 547 } 548 549 if (WARN_ON(!panel->override_mode.type)) 550 dev_err(dev, "Reject override mode: No display_timing found\n"); 551 } 552 553 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 554 { 555 struct panel_simple *panel; 556 struct display_timing dt; 557 struct device_node *ddc; 558 int connector_type; 559 u32 bus_flags; 560 int err; 561 562 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 563 if (!panel) 564 return -ENOMEM; 565 566 panel->enabled = false; 567 panel->prepared_time = 0; 568 panel->desc = desc; 569 570 panel->supply = devm_regulator_get(dev, "power"); 571 if (IS_ERR(panel->supply)) 572 return PTR_ERR(panel->supply); 573 574 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 575 GPIOD_OUT_LOW); 576 if (IS_ERR(panel->enable_gpio)) { 577 err = PTR_ERR(panel->enable_gpio); 578 if (err != -EPROBE_DEFER) 579 dev_err(dev, "failed to request GPIO: %d\n", err); 580 return err; 581 } 582 583 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 584 if (err) { 585 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 586 return err; 587 } 588 589 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 590 if (ddc) { 591 panel->ddc = of_find_i2c_adapter_by_node(ddc); 592 of_node_put(ddc); 593 594 if (!panel->ddc) 595 return -EPROBE_DEFER; 596 } 597 598 if (desc == &panel_dpi) { 599 /* Handle the generic panel-dpi binding */ 600 err = panel_dpi_probe(dev, panel); 601 if (err) 602 goto free_ddc; 603 desc = panel->desc; 604 } else { 605 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 606 panel_simple_parse_panel_timing_node(dev, panel, &dt); 607 } 608 609 connector_type = desc->connector_type; 610 /* Catch common mistakes for panels. */ 611 switch (connector_type) { 612 case 0: 613 dev_warn(dev, "Specify missing connector_type\n"); 614 connector_type = DRM_MODE_CONNECTOR_DPI; 615 break; 616 case DRM_MODE_CONNECTOR_LVDS: 617 WARN_ON(desc->bus_flags & 618 ~(DRM_BUS_FLAG_DE_LOW | 619 DRM_BUS_FLAG_DE_HIGH | 620 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 621 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 622 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 623 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 624 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 625 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 626 desc->bpc != 6); 627 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 628 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 629 desc->bpc != 8); 630 break; 631 case DRM_MODE_CONNECTOR_eDP: 632 dev_warn(dev, "eDP panels moved to panel-edp\n"); 633 err = -EINVAL; 634 goto free_ddc; 635 case DRM_MODE_CONNECTOR_DSI: 636 if (desc->bpc != 6 && desc->bpc != 8) 637 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 638 break; 639 case DRM_MODE_CONNECTOR_DPI: 640 bus_flags = DRM_BUS_FLAG_DE_LOW | 641 DRM_BUS_FLAG_DE_HIGH | 642 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 643 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 644 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 645 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 646 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 647 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 648 if (desc->bus_flags & ~bus_flags) 649 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 650 if (!(desc->bus_flags & bus_flags)) 651 dev_warn(dev, "Specify missing bus_flags\n"); 652 if (desc->bus_format == 0) 653 dev_warn(dev, "Specify missing bus_format\n"); 654 if (desc->bpc != 6 && desc->bpc != 8) 655 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 656 break; 657 default: 658 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 659 connector_type = DRM_MODE_CONNECTOR_DPI; 660 break; 661 } 662 663 dev_set_drvdata(dev, panel); 664 665 /* 666 * We use runtime PM for prepare / unprepare since those power the panel 667 * on and off and those can be very slow operations. This is important 668 * to optimize powering the panel on briefly to read the EDID before 669 * fully enabling the panel. 670 */ 671 pm_runtime_enable(dev); 672 pm_runtime_set_autosuspend_delay(dev, 1000); 673 pm_runtime_use_autosuspend(dev); 674 675 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 676 677 err = drm_panel_of_backlight(&panel->base); 678 if (err) { 679 dev_err_probe(dev, err, "Could not find backlight\n"); 680 goto disable_pm_runtime; 681 } 682 683 drm_panel_add(&panel->base); 684 685 return 0; 686 687 disable_pm_runtime: 688 pm_runtime_dont_use_autosuspend(dev); 689 pm_runtime_disable(dev); 690 free_ddc: 691 if (panel->ddc) 692 put_device(&panel->ddc->dev); 693 694 return err; 695 } 696 697 static int panel_simple_remove(struct device *dev) 698 { 699 struct panel_simple *panel = dev_get_drvdata(dev); 700 701 drm_panel_remove(&panel->base); 702 drm_panel_disable(&panel->base); 703 drm_panel_unprepare(&panel->base); 704 705 pm_runtime_dont_use_autosuspend(dev); 706 pm_runtime_disable(dev); 707 if (panel->ddc) 708 put_device(&panel->ddc->dev); 709 710 return 0; 711 } 712 713 static void panel_simple_shutdown(struct device *dev) 714 { 715 struct panel_simple *panel = dev_get_drvdata(dev); 716 717 drm_panel_disable(&panel->base); 718 drm_panel_unprepare(&panel->base); 719 } 720 721 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 722 .clock = 71100, 723 .hdisplay = 1280, 724 .hsync_start = 1280 + 40, 725 .hsync_end = 1280 + 40 + 80, 726 .htotal = 1280 + 40 + 80 + 40, 727 .vdisplay = 800, 728 .vsync_start = 800 + 3, 729 .vsync_end = 800 + 3 + 10, 730 .vtotal = 800 + 3 + 10 + 10, 731 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 732 }; 733 734 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 735 .modes = &ire_am_1280800n3tzqw_t00h_mode, 736 .num_modes = 1, 737 .bpc = 8, 738 .size = { 739 .width = 217, 740 .height = 136, 741 }, 742 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 743 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 744 .connector_type = DRM_MODE_CONNECTOR_LVDS, 745 }; 746 747 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 748 .clock = 9000, 749 .hdisplay = 480, 750 .hsync_start = 480 + 2, 751 .hsync_end = 480 + 2 + 41, 752 .htotal = 480 + 2 + 41 + 2, 753 .vdisplay = 272, 754 .vsync_start = 272 + 2, 755 .vsync_end = 272 + 2 + 10, 756 .vtotal = 272 + 2 + 10 + 2, 757 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 758 }; 759 760 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 761 .modes = &ire_am_480272h3tmqw_t01h_mode, 762 .num_modes = 1, 763 .bpc = 8, 764 .size = { 765 .width = 105, 766 .height = 67, 767 }, 768 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 769 }; 770 771 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 772 .clock = 33333, 773 .hdisplay = 800, 774 .hsync_start = 800 + 0, 775 .hsync_end = 800 + 0 + 255, 776 .htotal = 800 + 0 + 255 + 0, 777 .vdisplay = 480, 778 .vsync_start = 480 + 2, 779 .vsync_end = 480 + 2 + 45, 780 .vtotal = 480 + 2 + 45 + 0, 781 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 782 }; 783 784 static const struct panel_desc ampire_am800480r3tmqwa1h = { 785 .modes = &ire_am800480r3tmqwa1h_mode, 786 .num_modes = 1, 787 .bpc = 6, 788 .size = { 789 .width = 152, 790 .height = 91, 791 }, 792 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 793 }; 794 795 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 796 .pixelclock = { 34500000, 39600000, 50400000 }, 797 .hactive = { 800, 800, 800 }, 798 .hfront_porch = { 12, 112, 312 }, 799 .hback_porch = { 87, 87, 48 }, 800 .hsync_len = { 1, 1, 40 }, 801 .vactive = { 600, 600, 600 }, 802 .vfront_porch = { 1, 21, 61 }, 803 .vback_porch = { 38, 38, 19 }, 804 .vsync_len = { 1, 1, 20 }, 805 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 806 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 807 DISPLAY_FLAGS_SYNC_POSEDGE, 808 }; 809 810 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 811 .timings = &ire_am800600p5tmqw_tb8h_timing, 812 .num_timings = 1, 813 .bpc = 6, 814 .size = { 815 .width = 162, 816 .height = 122, 817 }, 818 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 819 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 820 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 821 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 822 .connector_type = DRM_MODE_CONNECTOR_DPI, 823 }; 824 825 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 826 .pixelclock = { 26400000, 33300000, 46800000 }, 827 .hactive = { 800, 800, 800 }, 828 .hfront_porch = { 16, 210, 354 }, 829 .hback_porch = { 45, 36, 6 }, 830 .hsync_len = { 1, 10, 40 }, 831 .vactive = { 480, 480, 480 }, 832 .vfront_porch = { 7, 22, 147 }, 833 .vback_porch = { 22, 13, 3 }, 834 .vsync_len = { 1, 10, 20 }, 835 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 836 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 837 }; 838 839 static const struct panel_desc armadeus_st0700_adapt = { 840 .timings = &santek_st0700i5y_rbslw_f_timing, 841 .num_timings = 1, 842 .bpc = 6, 843 .size = { 844 .width = 154, 845 .height = 86, 846 }, 847 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 848 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 849 }; 850 851 static const struct drm_display_mode auo_b101aw03_mode = { 852 .clock = 51450, 853 .hdisplay = 1024, 854 .hsync_start = 1024 + 156, 855 .hsync_end = 1024 + 156 + 8, 856 .htotal = 1024 + 156 + 8 + 156, 857 .vdisplay = 600, 858 .vsync_start = 600 + 16, 859 .vsync_end = 600 + 16 + 6, 860 .vtotal = 600 + 16 + 6 + 16, 861 }; 862 863 static const struct panel_desc auo_b101aw03 = { 864 .modes = &auo_b101aw03_mode, 865 .num_modes = 1, 866 .bpc = 6, 867 .size = { 868 .width = 223, 869 .height = 125, 870 }, 871 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 872 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 873 .connector_type = DRM_MODE_CONNECTOR_LVDS, 874 }; 875 876 static const struct drm_display_mode auo_b101xtn01_mode = { 877 .clock = 72000, 878 .hdisplay = 1366, 879 .hsync_start = 1366 + 20, 880 .hsync_end = 1366 + 20 + 70, 881 .htotal = 1366 + 20 + 70, 882 .vdisplay = 768, 883 .vsync_start = 768 + 14, 884 .vsync_end = 768 + 14 + 42, 885 .vtotal = 768 + 14 + 42, 886 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 887 }; 888 889 static const struct panel_desc auo_b101xtn01 = { 890 .modes = &auo_b101xtn01_mode, 891 .num_modes = 1, 892 .bpc = 6, 893 .size = { 894 .width = 223, 895 .height = 125, 896 }, 897 }; 898 899 static const struct display_timing auo_g070vvn01_timings = { 900 .pixelclock = { 33300000, 34209000, 45000000 }, 901 .hactive = { 800, 800, 800 }, 902 .hfront_porch = { 20, 40, 200 }, 903 .hback_porch = { 87, 40, 1 }, 904 .hsync_len = { 1, 48, 87 }, 905 .vactive = { 480, 480, 480 }, 906 .vfront_porch = { 5, 13, 200 }, 907 .vback_porch = { 31, 31, 29 }, 908 .vsync_len = { 1, 1, 3 }, 909 }; 910 911 static const struct panel_desc auo_g070vvn01 = { 912 .timings = &auo_g070vvn01_timings, 913 .num_timings = 1, 914 .bpc = 8, 915 .size = { 916 .width = 152, 917 .height = 91, 918 }, 919 .delay = { 920 .prepare = 200, 921 .enable = 50, 922 .disable = 50, 923 .unprepare = 1000, 924 }, 925 }; 926 927 static const struct drm_display_mode auo_g101evn010_mode = { 928 .clock = 68930, 929 .hdisplay = 1280, 930 .hsync_start = 1280 + 82, 931 .hsync_end = 1280 + 82 + 2, 932 .htotal = 1280 + 82 + 2 + 84, 933 .vdisplay = 800, 934 .vsync_start = 800 + 8, 935 .vsync_end = 800 + 8 + 2, 936 .vtotal = 800 + 8 + 2 + 6, 937 }; 938 939 static const struct panel_desc auo_g101evn010 = { 940 .modes = &auo_g101evn010_mode, 941 .num_modes = 1, 942 .bpc = 6, 943 .size = { 944 .width = 216, 945 .height = 135, 946 }, 947 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 948 .connector_type = DRM_MODE_CONNECTOR_LVDS, 949 }; 950 951 static const struct drm_display_mode auo_g104sn02_mode = { 952 .clock = 40000, 953 .hdisplay = 800, 954 .hsync_start = 800 + 40, 955 .hsync_end = 800 + 40 + 216, 956 .htotal = 800 + 40 + 216 + 128, 957 .vdisplay = 600, 958 .vsync_start = 600 + 10, 959 .vsync_end = 600 + 10 + 35, 960 .vtotal = 600 + 10 + 35 + 2, 961 }; 962 963 static const struct panel_desc auo_g104sn02 = { 964 .modes = &auo_g104sn02_mode, 965 .num_modes = 1, 966 .bpc = 8, 967 .size = { 968 .width = 211, 969 .height = 158, 970 }, 971 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 972 .connector_type = DRM_MODE_CONNECTOR_LVDS, 973 }; 974 975 static const struct drm_display_mode auo_g121ean01_mode = { 976 .clock = 66700, 977 .hdisplay = 1280, 978 .hsync_start = 1280 + 58, 979 .hsync_end = 1280 + 58 + 8, 980 .htotal = 1280 + 58 + 8 + 70, 981 .vdisplay = 800, 982 .vsync_start = 800 + 6, 983 .vsync_end = 800 + 6 + 4, 984 .vtotal = 800 + 6 + 4 + 10, 985 }; 986 987 static const struct panel_desc auo_g121ean01 = { 988 .modes = &auo_g121ean01_mode, 989 .num_modes = 1, 990 .bpc = 8, 991 .size = { 992 .width = 261, 993 .height = 163, 994 }, 995 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 996 .connector_type = DRM_MODE_CONNECTOR_LVDS, 997 }; 998 999 static const struct display_timing auo_g133han01_timings = { 1000 .pixelclock = { 134000000, 141200000, 149000000 }, 1001 .hactive = { 1920, 1920, 1920 }, 1002 .hfront_porch = { 39, 58, 77 }, 1003 .hback_porch = { 59, 88, 117 }, 1004 .hsync_len = { 28, 42, 56 }, 1005 .vactive = { 1080, 1080, 1080 }, 1006 .vfront_porch = { 3, 8, 11 }, 1007 .vback_porch = { 5, 14, 19 }, 1008 .vsync_len = { 4, 14, 19 }, 1009 }; 1010 1011 static const struct panel_desc auo_g133han01 = { 1012 .timings = &auo_g133han01_timings, 1013 .num_timings = 1, 1014 .bpc = 8, 1015 .size = { 1016 .width = 293, 1017 .height = 165, 1018 }, 1019 .delay = { 1020 .prepare = 200, 1021 .enable = 50, 1022 .disable = 50, 1023 .unprepare = 1000, 1024 }, 1025 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1026 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1027 }; 1028 1029 static const struct drm_display_mode auo_g156xtn01_mode = { 1030 .clock = 76000, 1031 .hdisplay = 1366, 1032 .hsync_start = 1366 + 33, 1033 .hsync_end = 1366 + 33 + 67, 1034 .htotal = 1560, 1035 .vdisplay = 768, 1036 .vsync_start = 768 + 4, 1037 .vsync_end = 768 + 4 + 4, 1038 .vtotal = 806, 1039 }; 1040 1041 static const struct panel_desc auo_g156xtn01 = { 1042 .modes = &auo_g156xtn01_mode, 1043 .num_modes = 1, 1044 .bpc = 8, 1045 .size = { 1046 .width = 344, 1047 .height = 194, 1048 }, 1049 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1050 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1051 }; 1052 1053 static const struct display_timing auo_g185han01_timings = { 1054 .pixelclock = { 120000000, 144000000, 175000000 }, 1055 .hactive = { 1920, 1920, 1920 }, 1056 .hfront_porch = { 36, 120, 148 }, 1057 .hback_porch = { 24, 88, 108 }, 1058 .hsync_len = { 20, 48, 64 }, 1059 .vactive = { 1080, 1080, 1080 }, 1060 .vfront_porch = { 6, 10, 40 }, 1061 .vback_porch = { 2, 5, 20 }, 1062 .vsync_len = { 2, 5, 20 }, 1063 }; 1064 1065 static const struct panel_desc auo_g185han01 = { 1066 .timings = &auo_g185han01_timings, 1067 .num_timings = 1, 1068 .bpc = 8, 1069 .size = { 1070 .width = 409, 1071 .height = 230, 1072 }, 1073 .delay = { 1074 .prepare = 50, 1075 .enable = 200, 1076 .disable = 110, 1077 .unprepare = 1000, 1078 }, 1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1080 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1081 }; 1082 1083 static const struct display_timing auo_g190ean01_timings = { 1084 .pixelclock = { 90000000, 108000000, 135000000 }, 1085 .hactive = { 1280, 1280, 1280 }, 1086 .hfront_porch = { 126, 184, 1266 }, 1087 .hback_porch = { 84, 122, 844 }, 1088 .hsync_len = { 70, 102, 704 }, 1089 .vactive = { 1024, 1024, 1024 }, 1090 .vfront_porch = { 4, 26, 76 }, 1091 .vback_porch = { 2, 8, 25 }, 1092 .vsync_len = { 2, 8, 25 }, 1093 }; 1094 1095 static const struct panel_desc auo_g190ean01 = { 1096 .timings = &auo_g190ean01_timings, 1097 .num_timings = 1, 1098 .bpc = 8, 1099 .size = { 1100 .width = 376, 1101 .height = 301, 1102 }, 1103 .delay = { 1104 .prepare = 50, 1105 .enable = 200, 1106 .disable = 110, 1107 .unprepare = 1000, 1108 }, 1109 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1110 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1111 }; 1112 1113 static const struct display_timing auo_p320hvn03_timings = { 1114 .pixelclock = { 106000000, 148500000, 164000000 }, 1115 .hactive = { 1920, 1920, 1920 }, 1116 .hfront_porch = { 25, 50, 130 }, 1117 .hback_porch = { 25, 50, 130 }, 1118 .hsync_len = { 20, 40, 105 }, 1119 .vactive = { 1080, 1080, 1080 }, 1120 .vfront_porch = { 8, 17, 150 }, 1121 .vback_porch = { 8, 17, 150 }, 1122 .vsync_len = { 4, 11, 100 }, 1123 }; 1124 1125 static const struct panel_desc auo_p320hvn03 = { 1126 .timings = &auo_p320hvn03_timings, 1127 .num_timings = 1, 1128 .bpc = 8, 1129 .size = { 1130 .width = 698, 1131 .height = 393, 1132 }, 1133 .delay = { 1134 .prepare = 1, 1135 .enable = 450, 1136 .unprepare = 500, 1137 }, 1138 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1139 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1140 }; 1141 1142 static const struct drm_display_mode auo_t215hvn01_mode = { 1143 .clock = 148800, 1144 .hdisplay = 1920, 1145 .hsync_start = 1920 + 88, 1146 .hsync_end = 1920 + 88 + 44, 1147 .htotal = 1920 + 88 + 44 + 148, 1148 .vdisplay = 1080, 1149 .vsync_start = 1080 + 4, 1150 .vsync_end = 1080 + 4 + 5, 1151 .vtotal = 1080 + 4 + 5 + 36, 1152 }; 1153 1154 static const struct panel_desc auo_t215hvn01 = { 1155 .modes = &auo_t215hvn01_mode, 1156 .num_modes = 1, 1157 .bpc = 8, 1158 .size = { 1159 .width = 430, 1160 .height = 270, 1161 }, 1162 .delay = { 1163 .disable = 5, 1164 .unprepare = 1000, 1165 } 1166 }; 1167 1168 static const struct drm_display_mode avic_tm070ddh03_mode = { 1169 .clock = 51200, 1170 .hdisplay = 1024, 1171 .hsync_start = 1024 + 160, 1172 .hsync_end = 1024 + 160 + 4, 1173 .htotal = 1024 + 160 + 4 + 156, 1174 .vdisplay = 600, 1175 .vsync_start = 600 + 17, 1176 .vsync_end = 600 + 17 + 1, 1177 .vtotal = 600 + 17 + 1 + 17, 1178 }; 1179 1180 static const struct panel_desc avic_tm070ddh03 = { 1181 .modes = &avic_tm070ddh03_mode, 1182 .num_modes = 1, 1183 .bpc = 8, 1184 .size = { 1185 .width = 154, 1186 .height = 90, 1187 }, 1188 .delay = { 1189 .prepare = 20, 1190 .enable = 200, 1191 .disable = 200, 1192 }, 1193 }; 1194 1195 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1196 .clock = 30000, 1197 .hdisplay = 800, 1198 .hsync_start = 800 + 40, 1199 .hsync_end = 800 + 40 + 48, 1200 .htotal = 800 + 40 + 48 + 40, 1201 .vdisplay = 480, 1202 .vsync_start = 480 + 13, 1203 .vsync_end = 480 + 13 + 3, 1204 .vtotal = 480 + 13 + 3 + 29, 1205 }; 1206 1207 static const struct panel_desc bananapi_s070wv20_ct16 = { 1208 .modes = &bananapi_s070wv20_ct16_mode, 1209 .num_modes = 1, 1210 .bpc = 6, 1211 .size = { 1212 .width = 154, 1213 .height = 86, 1214 }, 1215 }; 1216 1217 static const struct drm_display_mode boe_hv070wsa_mode = { 1218 .clock = 42105, 1219 .hdisplay = 1024, 1220 .hsync_start = 1024 + 30, 1221 .hsync_end = 1024 + 30 + 30, 1222 .htotal = 1024 + 30 + 30 + 30, 1223 .vdisplay = 600, 1224 .vsync_start = 600 + 10, 1225 .vsync_end = 600 + 10 + 10, 1226 .vtotal = 600 + 10 + 10 + 10, 1227 }; 1228 1229 static const struct panel_desc boe_hv070wsa = { 1230 .modes = &boe_hv070wsa_mode, 1231 .num_modes = 1, 1232 .bpc = 8, 1233 .size = { 1234 .width = 154, 1235 .height = 90, 1236 }, 1237 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1238 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1239 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1240 }; 1241 1242 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1243 .clock = 9000, 1244 .hdisplay = 480, 1245 .hsync_start = 480 + 5, 1246 .hsync_end = 480 + 5 + 5, 1247 .htotal = 480 + 5 + 5 + 40, 1248 .vdisplay = 272, 1249 .vsync_start = 272 + 8, 1250 .vsync_end = 272 + 8 + 8, 1251 .vtotal = 272 + 8 + 8 + 8, 1252 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1253 }; 1254 1255 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1256 .modes = &cdtech_s043wq26h_ct7_mode, 1257 .num_modes = 1, 1258 .bpc = 8, 1259 .size = { 1260 .width = 95, 1261 .height = 54, 1262 }, 1263 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1264 }; 1265 1266 /* S070PWS19HP-FC21 2017/04/22 */ 1267 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1268 .clock = 51200, 1269 .hdisplay = 1024, 1270 .hsync_start = 1024 + 160, 1271 .hsync_end = 1024 + 160 + 20, 1272 .htotal = 1024 + 160 + 20 + 140, 1273 .vdisplay = 600, 1274 .vsync_start = 600 + 12, 1275 .vsync_end = 600 + 12 + 3, 1276 .vtotal = 600 + 12 + 3 + 20, 1277 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1278 }; 1279 1280 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1281 .modes = &cdtech_s070pws19hp_fc21_mode, 1282 .num_modes = 1, 1283 .bpc = 6, 1284 .size = { 1285 .width = 154, 1286 .height = 86, 1287 }, 1288 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1289 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1290 .connector_type = DRM_MODE_CONNECTOR_DPI, 1291 }; 1292 1293 /* S070SWV29HG-DC44 2017/09/21 */ 1294 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1295 .clock = 33300, 1296 .hdisplay = 800, 1297 .hsync_start = 800 + 210, 1298 .hsync_end = 800 + 210 + 2, 1299 .htotal = 800 + 210 + 2 + 44, 1300 .vdisplay = 480, 1301 .vsync_start = 480 + 22, 1302 .vsync_end = 480 + 22 + 2, 1303 .vtotal = 480 + 22 + 2 + 21, 1304 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1305 }; 1306 1307 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1308 .modes = &cdtech_s070swv29hg_dc44_mode, 1309 .num_modes = 1, 1310 .bpc = 6, 1311 .size = { 1312 .width = 154, 1313 .height = 86, 1314 }, 1315 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1316 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1317 .connector_type = DRM_MODE_CONNECTOR_DPI, 1318 }; 1319 1320 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1321 .clock = 35000, 1322 .hdisplay = 800, 1323 .hsync_start = 800 + 40, 1324 .hsync_end = 800 + 40 + 40, 1325 .htotal = 800 + 40 + 40 + 48, 1326 .vdisplay = 480, 1327 .vsync_start = 480 + 29, 1328 .vsync_end = 480 + 29 + 13, 1329 .vtotal = 480 + 29 + 13 + 3, 1330 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1331 }; 1332 1333 static const struct panel_desc cdtech_s070wv95_ct16 = { 1334 .modes = &cdtech_s070wv95_ct16_mode, 1335 .num_modes = 1, 1336 .bpc = 8, 1337 .size = { 1338 .width = 154, 1339 .height = 85, 1340 }, 1341 }; 1342 1343 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1344 .pixelclock = { 68900000, 71100000, 73400000 }, 1345 .hactive = { 1280, 1280, 1280 }, 1346 .hfront_porch = { 65, 80, 95 }, 1347 .hback_porch = { 64, 79, 94 }, 1348 .hsync_len = { 1, 1, 1 }, 1349 .vactive = { 800, 800, 800 }, 1350 .vfront_porch = { 7, 11, 14 }, 1351 .vback_porch = { 7, 11, 14 }, 1352 .vsync_len = { 1, 1, 1 }, 1353 .flags = DISPLAY_FLAGS_DE_HIGH, 1354 }; 1355 1356 static const struct panel_desc chefree_ch101olhlwh_002 = { 1357 .timings = &chefree_ch101olhlwh_002_timing, 1358 .num_timings = 1, 1359 .bpc = 8, 1360 .size = { 1361 .width = 217, 1362 .height = 135, 1363 }, 1364 .delay = { 1365 .enable = 200, 1366 .disable = 200, 1367 }, 1368 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1369 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1370 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1371 }; 1372 1373 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1374 .clock = 66770, 1375 .hdisplay = 800, 1376 .hsync_start = 800 + 49, 1377 .hsync_end = 800 + 49 + 33, 1378 .htotal = 800 + 49 + 33 + 17, 1379 .vdisplay = 1280, 1380 .vsync_start = 1280 + 1, 1381 .vsync_end = 1280 + 1 + 7, 1382 .vtotal = 1280 + 1 + 7 + 15, 1383 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1384 }; 1385 1386 static const struct panel_desc chunghwa_claa070wp03xg = { 1387 .modes = &chunghwa_claa070wp03xg_mode, 1388 .num_modes = 1, 1389 .bpc = 6, 1390 .size = { 1391 .width = 94, 1392 .height = 150, 1393 }, 1394 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1395 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1396 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1397 }; 1398 1399 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1400 .clock = 72070, 1401 .hdisplay = 1366, 1402 .hsync_start = 1366 + 58, 1403 .hsync_end = 1366 + 58 + 58, 1404 .htotal = 1366 + 58 + 58 + 58, 1405 .vdisplay = 768, 1406 .vsync_start = 768 + 4, 1407 .vsync_end = 768 + 4 + 4, 1408 .vtotal = 768 + 4 + 4 + 4, 1409 }; 1410 1411 static const struct panel_desc chunghwa_claa101wa01a = { 1412 .modes = &chunghwa_claa101wa01a_mode, 1413 .num_modes = 1, 1414 .bpc = 6, 1415 .size = { 1416 .width = 220, 1417 .height = 120, 1418 }, 1419 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1420 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1421 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1422 }; 1423 1424 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1425 .clock = 69300, 1426 .hdisplay = 1366, 1427 .hsync_start = 1366 + 48, 1428 .hsync_end = 1366 + 48 + 32, 1429 .htotal = 1366 + 48 + 32 + 20, 1430 .vdisplay = 768, 1431 .vsync_start = 768 + 16, 1432 .vsync_end = 768 + 16 + 8, 1433 .vtotal = 768 + 16 + 8 + 16, 1434 }; 1435 1436 static const struct panel_desc chunghwa_claa101wb01 = { 1437 .modes = &chunghwa_claa101wb01_mode, 1438 .num_modes = 1, 1439 .bpc = 6, 1440 .size = { 1441 .width = 223, 1442 .height = 125, 1443 }, 1444 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1445 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1446 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1447 }; 1448 1449 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1450 .pixelclock = { 5000000, 9000000, 12000000 }, 1451 .hactive = { 480, 480, 480 }, 1452 .hfront_porch = { 12, 12, 12 }, 1453 .hback_porch = { 12, 12, 12 }, 1454 .hsync_len = { 21, 21, 21 }, 1455 .vactive = { 272, 272, 272 }, 1456 .vfront_porch = { 4, 4, 4 }, 1457 .vback_porch = { 4, 4, 4 }, 1458 .vsync_len = { 8, 8, 8 }, 1459 }; 1460 1461 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1462 .timings = &dataimage_fg040346dsswbg04_timing, 1463 .num_timings = 1, 1464 .bpc = 8, 1465 .size = { 1466 .width = 95, 1467 .height = 54, 1468 }, 1469 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1470 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1471 .connector_type = DRM_MODE_CONNECTOR_DPI, 1472 }; 1473 1474 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1475 .pixelclock = { 68900000, 71110000, 73400000 }, 1476 .hactive = { 1280, 1280, 1280 }, 1477 .vactive = { 800, 800, 800 }, 1478 .hback_porch = { 100, 100, 100 }, 1479 .hfront_porch = { 100, 100, 100 }, 1480 .vback_porch = { 5, 5, 5 }, 1481 .vfront_porch = { 5, 5, 5 }, 1482 .hsync_len = { 24, 24, 24 }, 1483 .vsync_len = { 3, 3, 3 }, 1484 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1485 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1486 }; 1487 1488 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1489 .timings = &dataimage_fg1001l0dsswmg01_timing, 1490 .num_timings = 1, 1491 .bpc = 8, 1492 .size = { 1493 .width = 217, 1494 .height = 136, 1495 }, 1496 }; 1497 1498 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1499 .clock = 33260, 1500 .hdisplay = 800, 1501 .hsync_start = 800 + 40, 1502 .hsync_end = 800 + 40 + 128, 1503 .htotal = 800 + 40 + 128 + 88, 1504 .vdisplay = 480, 1505 .vsync_start = 480 + 10, 1506 .vsync_end = 480 + 10 + 2, 1507 .vtotal = 480 + 10 + 2 + 33, 1508 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1509 }; 1510 1511 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1512 .modes = &dataimage_scf0700c48ggu18_mode, 1513 .num_modes = 1, 1514 .bpc = 8, 1515 .size = { 1516 .width = 152, 1517 .height = 91, 1518 }, 1519 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1520 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1521 }; 1522 1523 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1524 .pixelclock = { 45000000, 51200000, 57000000 }, 1525 .hactive = { 1024, 1024, 1024 }, 1526 .hfront_porch = { 100, 106, 113 }, 1527 .hback_porch = { 100, 106, 113 }, 1528 .hsync_len = { 100, 108, 114 }, 1529 .vactive = { 600, 600, 600 }, 1530 .vfront_porch = { 8, 11, 15 }, 1531 .vback_porch = { 8, 11, 15 }, 1532 .vsync_len = { 9, 13, 15 }, 1533 .flags = DISPLAY_FLAGS_DE_HIGH, 1534 }; 1535 1536 static const struct panel_desc dlc_dlc0700yzg_1 = { 1537 .timings = &dlc_dlc0700yzg_1_timing, 1538 .num_timings = 1, 1539 .bpc = 6, 1540 .size = { 1541 .width = 154, 1542 .height = 86, 1543 }, 1544 .delay = { 1545 .prepare = 30, 1546 .enable = 200, 1547 .disable = 200, 1548 }, 1549 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1550 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1551 }; 1552 1553 static const struct display_timing dlc_dlc1010gig_timing = { 1554 .pixelclock = { 68900000, 71100000, 73400000 }, 1555 .hactive = { 1280, 1280, 1280 }, 1556 .hfront_porch = { 43, 53, 63 }, 1557 .hback_porch = { 43, 53, 63 }, 1558 .hsync_len = { 44, 54, 64 }, 1559 .vactive = { 800, 800, 800 }, 1560 .vfront_porch = { 5, 8, 11 }, 1561 .vback_porch = { 5, 8, 11 }, 1562 .vsync_len = { 5, 7, 11 }, 1563 .flags = DISPLAY_FLAGS_DE_HIGH, 1564 }; 1565 1566 static const struct panel_desc dlc_dlc1010gig = { 1567 .timings = &dlc_dlc1010gig_timing, 1568 .num_timings = 1, 1569 .bpc = 8, 1570 .size = { 1571 .width = 216, 1572 .height = 135, 1573 }, 1574 .delay = { 1575 .prepare = 60, 1576 .enable = 150, 1577 .disable = 100, 1578 .unprepare = 60, 1579 }, 1580 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1581 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1582 }; 1583 1584 static const struct drm_display_mode edt_et035012dm6_mode = { 1585 .clock = 6500, 1586 .hdisplay = 320, 1587 .hsync_start = 320 + 20, 1588 .hsync_end = 320 + 20 + 30, 1589 .htotal = 320 + 20 + 68, 1590 .vdisplay = 240, 1591 .vsync_start = 240 + 4, 1592 .vsync_end = 240 + 4 + 4, 1593 .vtotal = 240 + 4 + 4 + 14, 1594 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1595 }; 1596 1597 static const struct panel_desc edt_et035012dm6 = { 1598 .modes = &edt_et035012dm6_mode, 1599 .num_modes = 1, 1600 .bpc = 8, 1601 .size = { 1602 .width = 70, 1603 .height = 52, 1604 }, 1605 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1606 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1607 }; 1608 1609 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1610 .clock = 6520, 1611 .hdisplay = 320, 1612 .hsync_start = 320 + 20, 1613 .hsync_end = 320 + 20 + 68, 1614 .htotal = 320 + 20 + 68, 1615 .vdisplay = 240, 1616 .vsync_start = 240 + 4, 1617 .vsync_end = 240 + 4 + 18, 1618 .vtotal = 240 + 4 + 18, 1619 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1620 }; 1621 1622 static const struct panel_desc edt_etm0350g0dh6 = { 1623 .modes = &edt_etm0350g0dh6_mode, 1624 .num_modes = 1, 1625 .bpc = 6, 1626 .size = { 1627 .width = 70, 1628 .height = 53, 1629 }, 1630 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1631 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1632 .connector_type = DRM_MODE_CONNECTOR_DPI, 1633 }; 1634 1635 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1636 .clock = 10870, 1637 .hdisplay = 480, 1638 .hsync_start = 480 + 8, 1639 .hsync_end = 480 + 8 + 4, 1640 .htotal = 480 + 8 + 4 + 41, 1641 1642 /* 1643 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1644 * fb_align 1645 */ 1646 1647 .vdisplay = 288, 1648 .vsync_start = 288 + 2, 1649 .vsync_end = 288 + 2 + 4, 1650 .vtotal = 288 + 2 + 4 + 10, 1651 }; 1652 1653 static const struct panel_desc edt_etm043080dh6gp = { 1654 .modes = &edt_etm043080dh6gp_mode, 1655 .num_modes = 1, 1656 .bpc = 8, 1657 .size = { 1658 .width = 100, 1659 .height = 65, 1660 }, 1661 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1662 .connector_type = DRM_MODE_CONNECTOR_DPI, 1663 }; 1664 1665 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1666 .clock = 9000, 1667 .hdisplay = 480, 1668 .hsync_start = 480 + 2, 1669 .hsync_end = 480 + 2 + 41, 1670 .htotal = 480 + 2 + 41 + 2, 1671 .vdisplay = 272, 1672 .vsync_start = 272 + 2, 1673 .vsync_end = 272 + 2 + 10, 1674 .vtotal = 272 + 2 + 10 + 2, 1675 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1676 }; 1677 1678 static const struct panel_desc edt_etm0430g0dh6 = { 1679 .modes = &edt_etm0430g0dh6_mode, 1680 .num_modes = 1, 1681 .bpc = 6, 1682 .size = { 1683 .width = 95, 1684 .height = 54, 1685 }, 1686 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1687 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1688 .connector_type = DRM_MODE_CONNECTOR_DPI, 1689 }; 1690 1691 static const struct drm_display_mode edt_et057090dhu_mode = { 1692 .clock = 25175, 1693 .hdisplay = 640, 1694 .hsync_start = 640 + 16, 1695 .hsync_end = 640 + 16 + 30, 1696 .htotal = 640 + 16 + 30 + 114, 1697 .vdisplay = 480, 1698 .vsync_start = 480 + 10, 1699 .vsync_end = 480 + 10 + 3, 1700 .vtotal = 480 + 10 + 3 + 32, 1701 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1702 }; 1703 1704 static const struct panel_desc edt_et057090dhu = { 1705 .modes = &edt_et057090dhu_mode, 1706 .num_modes = 1, 1707 .bpc = 6, 1708 .size = { 1709 .width = 115, 1710 .height = 86, 1711 }, 1712 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1713 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1714 .connector_type = DRM_MODE_CONNECTOR_DPI, 1715 }; 1716 1717 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1718 .clock = 33260, 1719 .hdisplay = 800, 1720 .hsync_start = 800 + 40, 1721 .hsync_end = 800 + 40 + 128, 1722 .htotal = 800 + 40 + 128 + 88, 1723 .vdisplay = 480, 1724 .vsync_start = 480 + 10, 1725 .vsync_end = 480 + 10 + 2, 1726 .vtotal = 480 + 10 + 2 + 33, 1727 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1728 }; 1729 1730 static const struct panel_desc edt_etm0700g0dh6 = { 1731 .modes = &edt_etm0700g0dh6_mode, 1732 .num_modes = 1, 1733 .bpc = 6, 1734 .size = { 1735 .width = 152, 1736 .height = 91, 1737 }, 1738 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1739 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1740 .connector_type = DRM_MODE_CONNECTOR_DPI, 1741 }; 1742 1743 static const struct panel_desc edt_etm0700g0bdh6 = { 1744 .modes = &edt_etm0700g0dh6_mode, 1745 .num_modes = 1, 1746 .bpc = 6, 1747 .size = { 1748 .width = 152, 1749 .height = 91, 1750 }, 1751 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1752 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1753 .connector_type = DRM_MODE_CONNECTOR_DPI, 1754 }; 1755 1756 static const struct display_timing edt_etml0700y5dha_timing = { 1757 .pixelclock = { 40800000, 51200000, 67200000 }, 1758 .hactive = { 1024, 1024, 1024 }, 1759 .hfront_porch = { 30, 106, 125 }, 1760 .hback_porch = { 30, 106, 125 }, 1761 .hsync_len = { 30, 108, 126 }, 1762 .vactive = { 600, 600, 600 }, 1763 .vfront_porch = { 3, 12, 67}, 1764 .vback_porch = { 3, 12, 67 }, 1765 .vsync_len = { 4, 11, 66 }, 1766 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1767 DISPLAY_FLAGS_DE_HIGH, 1768 }; 1769 1770 static const struct panel_desc edt_etml0700y5dha = { 1771 .timings = &edt_etml0700y5dha_timing, 1772 .num_timings = 1, 1773 .bpc = 8, 1774 .size = { 1775 .width = 155, 1776 .height = 86, 1777 }, 1778 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1779 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1780 }; 1781 1782 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1783 .clock = 25175, 1784 .hdisplay = 640, 1785 .hsync_start = 640, 1786 .hsync_end = 640 + 16, 1787 .htotal = 640 + 16 + 30 + 114, 1788 .vdisplay = 480, 1789 .vsync_start = 480 + 10, 1790 .vsync_end = 480 + 10 + 3, 1791 .vtotal = 480 + 10 + 3 + 35, 1792 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1793 }; 1794 1795 static const struct panel_desc edt_etmv570g2dhu = { 1796 .modes = &edt_etmv570g2dhu_mode, 1797 .num_modes = 1, 1798 .bpc = 6, 1799 .size = { 1800 .width = 115, 1801 .height = 86, 1802 }, 1803 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1804 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1805 .connector_type = DRM_MODE_CONNECTOR_DPI, 1806 }; 1807 1808 static const struct display_timing eink_vb3300_kca_timing = { 1809 .pixelclock = { 40000000, 40000000, 40000000 }, 1810 .hactive = { 334, 334, 334 }, 1811 .hfront_porch = { 1, 1, 1 }, 1812 .hback_porch = { 1, 1, 1 }, 1813 .hsync_len = { 1, 1, 1 }, 1814 .vactive = { 1405, 1405, 1405 }, 1815 .vfront_porch = { 1, 1, 1 }, 1816 .vback_porch = { 1, 1, 1 }, 1817 .vsync_len = { 1, 1, 1 }, 1818 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1819 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1820 }; 1821 1822 static const struct panel_desc eink_vb3300_kca = { 1823 .timings = &eink_vb3300_kca_timing, 1824 .num_timings = 1, 1825 .bpc = 6, 1826 .size = { 1827 .width = 157, 1828 .height = 209, 1829 }, 1830 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1831 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1832 .connector_type = DRM_MODE_CONNECTOR_DPI, 1833 }; 1834 1835 static const struct display_timing evervision_vgg804821_timing = { 1836 .pixelclock = { 27600000, 33300000, 50000000 }, 1837 .hactive = { 800, 800, 800 }, 1838 .hfront_porch = { 40, 66, 70 }, 1839 .hback_porch = { 40, 67, 70 }, 1840 .hsync_len = { 40, 67, 70 }, 1841 .vactive = { 480, 480, 480 }, 1842 .vfront_porch = { 6, 10, 10 }, 1843 .vback_porch = { 7, 11, 11 }, 1844 .vsync_len = { 7, 11, 11 }, 1845 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1846 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1847 DISPLAY_FLAGS_SYNC_NEGEDGE, 1848 }; 1849 1850 static const struct panel_desc evervision_vgg804821 = { 1851 .timings = &evervision_vgg804821_timing, 1852 .num_timings = 1, 1853 .bpc = 8, 1854 .size = { 1855 .width = 108, 1856 .height = 64, 1857 }, 1858 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1859 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1860 }; 1861 1862 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1863 .clock = 32260, 1864 .hdisplay = 800, 1865 .hsync_start = 800 + 168, 1866 .hsync_end = 800 + 168 + 64, 1867 .htotal = 800 + 168 + 64 + 88, 1868 .vdisplay = 480, 1869 .vsync_start = 480 + 37, 1870 .vsync_end = 480 + 37 + 2, 1871 .vtotal = 480 + 37 + 2 + 8, 1872 }; 1873 1874 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1875 .modes = &foxlink_fl500wvr00_a0t_mode, 1876 .num_modes = 1, 1877 .bpc = 8, 1878 .size = { 1879 .width = 108, 1880 .height = 65, 1881 }, 1882 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1883 }; 1884 1885 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1886 { /* 60 Hz */ 1887 .clock = 6000, 1888 .hdisplay = 320, 1889 .hsync_start = 320 + 44, 1890 .hsync_end = 320 + 44 + 16, 1891 .htotal = 320 + 44 + 16 + 20, 1892 .vdisplay = 240, 1893 .vsync_start = 240 + 2, 1894 .vsync_end = 240 + 2 + 6, 1895 .vtotal = 240 + 2 + 6 + 2, 1896 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1897 }, 1898 { /* 50 Hz */ 1899 .clock = 5400, 1900 .hdisplay = 320, 1901 .hsync_start = 320 + 56, 1902 .hsync_end = 320 + 56 + 16, 1903 .htotal = 320 + 56 + 16 + 40, 1904 .vdisplay = 240, 1905 .vsync_start = 240 + 2, 1906 .vsync_end = 240 + 2 + 6, 1907 .vtotal = 240 + 2 + 6 + 2, 1908 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1909 }, 1910 }; 1911 1912 static const struct panel_desc frida_frd350h54004 = { 1913 .modes = frida_frd350h54004_modes, 1914 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1915 .bpc = 8, 1916 .size = { 1917 .width = 77, 1918 .height = 64, 1919 }, 1920 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1921 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1922 .connector_type = DRM_MODE_CONNECTOR_DPI, 1923 }; 1924 1925 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1926 .clock = 67185, 1927 .hdisplay = 800, 1928 .hsync_start = 800 + 20, 1929 .hsync_end = 800 + 20 + 24, 1930 .htotal = 800 + 20 + 24 + 20, 1931 .vdisplay = 1280, 1932 .vsync_start = 1280 + 4, 1933 .vsync_end = 1280 + 4 + 8, 1934 .vtotal = 1280 + 4 + 8 + 4, 1935 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1936 }; 1937 1938 static const struct panel_desc friendlyarm_hd702e = { 1939 .modes = &friendlyarm_hd702e_mode, 1940 .num_modes = 1, 1941 .size = { 1942 .width = 94, 1943 .height = 151, 1944 }, 1945 }; 1946 1947 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 1948 .clock = 9000, 1949 .hdisplay = 480, 1950 .hsync_start = 480 + 5, 1951 .hsync_end = 480 + 5 + 1, 1952 .htotal = 480 + 5 + 1 + 40, 1953 .vdisplay = 272, 1954 .vsync_start = 272 + 8, 1955 .vsync_end = 272 + 8 + 1, 1956 .vtotal = 272 + 8 + 1 + 8, 1957 }; 1958 1959 static const struct panel_desc giantplus_gpg482739qs5 = { 1960 .modes = &giantplus_gpg482739qs5_mode, 1961 .num_modes = 1, 1962 .bpc = 8, 1963 .size = { 1964 .width = 95, 1965 .height = 54, 1966 }, 1967 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1968 }; 1969 1970 static const struct display_timing giantplus_gpm940b0_timing = { 1971 .pixelclock = { 13500000, 27000000, 27500000 }, 1972 .hactive = { 320, 320, 320 }, 1973 .hfront_porch = { 14, 686, 718 }, 1974 .hback_porch = { 50, 70, 255 }, 1975 .hsync_len = { 1, 1, 1 }, 1976 .vactive = { 240, 240, 240 }, 1977 .vfront_porch = { 1, 1, 179 }, 1978 .vback_porch = { 1, 21, 31 }, 1979 .vsync_len = { 1, 1, 6 }, 1980 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1981 }; 1982 1983 static const struct panel_desc giantplus_gpm940b0 = { 1984 .timings = &giantplus_gpm940b0_timing, 1985 .num_timings = 1, 1986 .bpc = 8, 1987 .size = { 1988 .width = 60, 1989 .height = 45, 1990 }, 1991 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 1992 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1993 }; 1994 1995 static const struct display_timing hannstar_hsd070pww1_timing = { 1996 .pixelclock = { 64300000, 71100000, 82000000 }, 1997 .hactive = { 1280, 1280, 1280 }, 1998 .hfront_porch = { 1, 1, 10 }, 1999 .hback_porch = { 1, 1, 10 }, 2000 /* 2001 * According to the data sheet, the minimum horizontal blanking interval 2002 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2003 * minimum working horizontal blanking interval to be 60 clocks. 2004 */ 2005 .hsync_len = { 58, 158, 661 }, 2006 .vactive = { 800, 800, 800 }, 2007 .vfront_porch = { 1, 1, 10 }, 2008 .vback_porch = { 1, 1, 10 }, 2009 .vsync_len = { 1, 21, 203 }, 2010 .flags = DISPLAY_FLAGS_DE_HIGH, 2011 }; 2012 2013 static const struct panel_desc hannstar_hsd070pww1 = { 2014 .timings = &hannstar_hsd070pww1_timing, 2015 .num_timings = 1, 2016 .bpc = 6, 2017 .size = { 2018 .width = 151, 2019 .height = 94, 2020 }, 2021 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2022 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2023 }; 2024 2025 static const struct display_timing hannstar_hsd100pxn1_timing = { 2026 .pixelclock = { 55000000, 65000000, 75000000 }, 2027 .hactive = { 1024, 1024, 1024 }, 2028 .hfront_porch = { 40, 40, 40 }, 2029 .hback_porch = { 220, 220, 220 }, 2030 .hsync_len = { 20, 60, 100 }, 2031 .vactive = { 768, 768, 768 }, 2032 .vfront_porch = { 7, 7, 7 }, 2033 .vback_porch = { 21, 21, 21 }, 2034 .vsync_len = { 10, 10, 10 }, 2035 .flags = DISPLAY_FLAGS_DE_HIGH, 2036 }; 2037 2038 static const struct panel_desc hannstar_hsd100pxn1 = { 2039 .timings = &hannstar_hsd100pxn1_timing, 2040 .num_timings = 1, 2041 .bpc = 6, 2042 .size = { 2043 .width = 203, 2044 .height = 152, 2045 }, 2046 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2047 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2048 }; 2049 2050 static const struct display_timing hannstar_hsd101pww2_timing = { 2051 .pixelclock = { 64300000, 71100000, 82000000 }, 2052 .hactive = { 1280, 1280, 1280 }, 2053 .hfront_porch = { 1, 1, 10 }, 2054 .hback_porch = { 1, 1, 10 }, 2055 .hsync_len = { 58, 158, 661 }, 2056 .vactive = { 800, 800, 800 }, 2057 .vfront_porch = { 1, 1, 10 }, 2058 .vback_porch = { 1, 1, 10 }, 2059 .vsync_len = { 1, 21, 203 }, 2060 .flags = DISPLAY_FLAGS_DE_HIGH, 2061 }; 2062 2063 static const struct panel_desc hannstar_hsd101pww2 = { 2064 .timings = &hannstar_hsd101pww2_timing, 2065 .num_timings = 1, 2066 .bpc = 8, 2067 .size = { 2068 .width = 217, 2069 .height = 136, 2070 }, 2071 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2072 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2073 }; 2074 2075 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2076 .clock = 33333, 2077 .hdisplay = 800, 2078 .hsync_start = 800 + 85, 2079 .hsync_end = 800 + 85 + 86, 2080 .htotal = 800 + 85 + 86 + 85, 2081 .vdisplay = 480, 2082 .vsync_start = 480 + 16, 2083 .vsync_end = 480 + 16 + 13, 2084 .vtotal = 480 + 16 + 13 + 16, 2085 }; 2086 2087 static const struct panel_desc hitachi_tx23d38vm0caa = { 2088 .modes = &hitachi_tx23d38vm0caa_mode, 2089 .num_modes = 1, 2090 .bpc = 6, 2091 .size = { 2092 .width = 195, 2093 .height = 117, 2094 }, 2095 .delay = { 2096 .enable = 160, 2097 .disable = 160, 2098 }, 2099 }; 2100 2101 static const struct drm_display_mode innolux_at043tn24_mode = { 2102 .clock = 9000, 2103 .hdisplay = 480, 2104 .hsync_start = 480 + 2, 2105 .hsync_end = 480 + 2 + 41, 2106 .htotal = 480 + 2 + 41 + 2, 2107 .vdisplay = 272, 2108 .vsync_start = 272 + 2, 2109 .vsync_end = 272 + 2 + 10, 2110 .vtotal = 272 + 2 + 10 + 2, 2111 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2112 }; 2113 2114 static const struct panel_desc innolux_at043tn24 = { 2115 .modes = &innolux_at043tn24_mode, 2116 .num_modes = 1, 2117 .bpc = 8, 2118 .size = { 2119 .width = 95, 2120 .height = 54, 2121 }, 2122 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2123 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2124 }; 2125 2126 static const struct drm_display_mode innolux_at070tn92_mode = { 2127 .clock = 33333, 2128 .hdisplay = 800, 2129 .hsync_start = 800 + 210, 2130 .hsync_end = 800 + 210 + 20, 2131 .htotal = 800 + 210 + 20 + 46, 2132 .vdisplay = 480, 2133 .vsync_start = 480 + 22, 2134 .vsync_end = 480 + 22 + 10, 2135 .vtotal = 480 + 22 + 23 + 10, 2136 }; 2137 2138 static const struct panel_desc innolux_at070tn92 = { 2139 .modes = &innolux_at070tn92_mode, 2140 .num_modes = 1, 2141 .size = { 2142 .width = 154, 2143 .height = 86, 2144 }, 2145 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2146 }; 2147 2148 static const struct display_timing innolux_g070y2_l01_timing = { 2149 .pixelclock = { 28000000, 29500000, 32000000 }, 2150 .hactive = { 800, 800, 800 }, 2151 .hfront_porch = { 61, 91, 141 }, 2152 .hback_porch = { 60, 90, 140 }, 2153 .hsync_len = { 12, 12, 12 }, 2154 .vactive = { 480, 480, 480 }, 2155 .vfront_porch = { 4, 9, 30 }, 2156 .vback_porch = { 4, 8, 28 }, 2157 .vsync_len = { 2, 2, 2 }, 2158 .flags = DISPLAY_FLAGS_DE_HIGH, 2159 }; 2160 2161 static const struct panel_desc innolux_g070y2_l01 = { 2162 .timings = &innolux_g070y2_l01_timing, 2163 .num_timings = 1, 2164 .bpc = 8, 2165 .size = { 2166 .width = 152, 2167 .height = 91, 2168 }, 2169 .delay = { 2170 .prepare = 10, 2171 .enable = 100, 2172 .disable = 100, 2173 .unprepare = 800, 2174 }, 2175 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2176 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2177 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2178 }; 2179 2180 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2181 .clock = 33333, 2182 .hdisplay = 800, 2183 .hsync_start = 800 + 210, 2184 .hsync_end = 800 + 210 + 20, 2185 .htotal = 800 + 210 + 20 + 46, 2186 .vdisplay = 480, 2187 .vsync_start = 480 + 22, 2188 .vsync_end = 480 + 22 + 10, 2189 .vtotal = 480 + 22 + 23 + 10, 2190 }; 2191 2192 static const struct panel_desc innolux_g070y2_t02 = { 2193 .modes = &innolux_g070y2_t02_mode, 2194 .num_modes = 1, 2195 .bpc = 8, 2196 .size = { 2197 .width = 152, 2198 .height = 92, 2199 }, 2200 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2201 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2202 .connector_type = DRM_MODE_CONNECTOR_DPI, 2203 }; 2204 2205 static const struct display_timing innolux_g101ice_l01_timing = { 2206 .pixelclock = { 60400000, 71100000, 74700000 }, 2207 .hactive = { 1280, 1280, 1280 }, 2208 .hfront_porch = { 41, 80, 100 }, 2209 .hback_porch = { 40, 79, 99 }, 2210 .hsync_len = { 1, 1, 1 }, 2211 .vactive = { 800, 800, 800 }, 2212 .vfront_porch = { 5, 11, 14 }, 2213 .vback_porch = { 4, 11, 14 }, 2214 .vsync_len = { 1, 1, 1 }, 2215 .flags = DISPLAY_FLAGS_DE_HIGH, 2216 }; 2217 2218 static const struct panel_desc innolux_g101ice_l01 = { 2219 .timings = &innolux_g101ice_l01_timing, 2220 .num_timings = 1, 2221 .bpc = 8, 2222 .size = { 2223 .width = 217, 2224 .height = 135, 2225 }, 2226 .delay = { 2227 .enable = 200, 2228 .disable = 200, 2229 }, 2230 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2231 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2232 }; 2233 2234 static const struct display_timing innolux_g121i1_l01_timing = { 2235 .pixelclock = { 67450000, 71000000, 74550000 }, 2236 .hactive = { 1280, 1280, 1280 }, 2237 .hfront_porch = { 40, 80, 160 }, 2238 .hback_porch = { 39, 79, 159 }, 2239 .hsync_len = { 1, 1, 1 }, 2240 .vactive = { 800, 800, 800 }, 2241 .vfront_porch = { 5, 11, 100 }, 2242 .vback_porch = { 4, 11, 99 }, 2243 .vsync_len = { 1, 1, 1 }, 2244 }; 2245 2246 static const struct panel_desc innolux_g121i1_l01 = { 2247 .timings = &innolux_g121i1_l01_timing, 2248 .num_timings = 1, 2249 .bpc = 6, 2250 .size = { 2251 .width = 261, 2252 .height = 163, 2253 }, 2254 .delay = { 2255 .enable = 200, 2256 .disable = 20, 2257 }, 2258 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2259 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2260 }; 2261 2262 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2263 .clock = 65000, 2264 .hdisplay = 1024, 2265 .hsync_start = 1024 + 0, 2266 .hsync_end = 1024 + 1, 2267 .htotal = 1024 + 0 + 1 + 320, 2268 .vdisplay = 768, 2269 .vsync_start = 768 + 38, 2270 .vsync_end = 768 + 38 + 1, 2271 .vtotal = 768 + 38 + 1 + 0, 2272 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2273 }; 2274 2275 static const struct panel_desc innolux_g121x1_l03 = { 2276 .modes = &innolux_g121x1_l03_mode, 2277 .num_modes = 1, 2278 .bpc = 6, 2279 .size = { 2280 .width = 246, 2281 .height = 185, 2282 }, 2283 .delay = { 2284 .enable = 200, 2285 .unprepare = 200, 2286 .disable = 400, 2287 }, 2288 }; 2289 2290 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2291 .clock = 69300, 2292 .hdisplay = 1366, 2293 .hsync_start = 1366 + 16, 2294 .hsync_end = 1366 + 16 + 34, 2295 .htotal = 1366 + 16 + 34 + 50, 2296 .vdisplay = 768, 2297 .vsync_start = 768 + 2, 2298 .vsync_end = 768 + 2 + 6, 2299 .vtotal = 768 + 2 + 6 + 12, 2300 }; 2301 2302 static const struct panel_desc innolux_n156bge_l21 = { 2303 .modes = &innolux_n156bge_l21_mode, 2304 .num_modes = 1, 2305 .bpc = 6, 2306 .size = { 2307 .width = 344, 2308 .height = 193, 2309 }, 2310 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2311 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2312 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2313 }; 2314 2315 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2316 .clock = 51501, 2317 .hdisplay = 1024, 2318 .hsync_start = 1024 + 128, 2319 .hsync_end = 1024 + 128 + 64, 2320 .htotal = 1024 + 128 + 64 + 128, 2321 .vdisplay = 600, 2322 .vsync_start = 600 + 16, 2323 .vsync_end = 600 + 16 + 4, 2324 .vtotal = 600 + 16 + 4 + 16, 2325 }; 2326 2327 static const struct panel_desc innolux_zj070na_01p = { 2328 .modes = &innolux_zj070na_01p_mode, 2329 .num_modes = 1, 2330 .bpc = 6, 2331 .size = { 2332 .width = 154, 2333 .height = 90, 2334 }, 2335 }; 2336 2337 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2338 .pixelclock = { 5580000, 5850000, 6200000 }, 2339 .hactive = { 320, 320, 320 }, 2340 .hfront_porch = { 30, 30, 30 }, 2341 .hback_porch = { 30, 30, 30 }, 2342 .hsync_len = { 1, 5, 17 }, 2343 .vactive = { 240, 240, 240 }, 2344 .vfront_porch = { 6, 6, 6 }, 2345 .vback_porch = { 5, 5, 5 }, 2346 .vsync_len = { 1, 2, 11 }, 2347 .flags = DISPLAY_FLAGS_DE_HIGH, 2348 }; 2349 2350 static const struct panel_desc koe_tx14d24vm1bpa = { 2351 .timings = &koe_tx14d24vm1bpa_timing, 2352 .num_timings = 1, 2353 .bpc = 6, 2354 .size = { 2355 .width = 115, 2356 .height = 86, 2357 }, 2358 }; 2359 2360 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2361 .pixelclock = { 151820000, 156720000, 159780000 }, 2362 .hactive = { 1920, 1920, 1920 }, 2363 .hfront_porch = { 105, 130, 142 }, 2364 .hback_porch = { 45, 70, 82 }, 2365 .hsync_len = { 30, 30, 30 }, 2366 .vactive = { 1200, 1200, 1200}, 2367 .vfront_porch = { 3, 5, 10 }, 2368 .vback_porch = { 2, 5, 10 }, 2369 .vsync_len = { 5, 5, 5 }, 2370 }; 2371 2372 static const struct panel_desc koe_tx26d202vm0bwa = { 2373 .timings = &koe_tx26d202vm0bwa_timing, 2374 .num_timings = 1, 2375 .bpc = 8, 2376 .size = { 2377 .width = 217, 2378 .height = 136, 2379 }, 2380 .delay = { 2381 .prepare = 1000, 2382 .enable = 1000, 2383 .unprepare = 1000, 2384 .disable = 1000, 2385 }, 2386 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2387 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2388 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2389 }; 2390 2391 static const struct display_timing koe_tx31d200vm0baa_timing = { 2392 .pixelclock = { 39600000, 43200000, 48000000 }, 2393 .hactive = { 1280, 1280, 1280 }, 2394 .hfront_porch = { 16, 36, 56 }, 2395 .hback_porch = { 16, 36, 56 }, 2396 .hsync_len = { 8, 8, 8 }, 2397 .vactive = { 480, 480, 480 }, 2398 .vfront_porch = { 6, 21, 33 }, 2399 .vback_porch = { 6, 21, 33 }, 2400 .vsync_len = { 8, 8, 8 }, 2401 .flags = DISPLAY_FLAGS_DE_HIGH, 2402 }; 2403 2404 static const struct panel_desc koe_tx31d200vm0baa = { 2405 .timings = &koe_tx31d200vm0baa_timing, 2406 .num_timings = 1, 2407 .bpc = 6, 2408 .size = { 2409 .width = 292, 2410 .height = 109, 2411 }, 2412 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2413 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2414 }; 2415 2416 static const struct display_timing kyo_tcg121xglp_timing = { 2417 .pixelclock = { 52000000, 65000000, 71000000 }, 2418 .hactive = { 1024, 1024, 1024 }, 2419 .hfront_porch = { 2, 2, 2 }, 2420 .hback_porch = { 2, 2, 2 }, 2421 .hsync_len = { 86, 124, 244 }, 2422 .vactive = { 768, 768, 768 }, 2423 .vfront_porch = { 2, 2, 2 }, 2424 .vback_porch = { 2, 2, 2 }, 2425 .vsync_len = { 6, 34, 73 }, 2426 .flags = DISPLAY_FLAGS_DE_HIGH, 2427 }; 2428 2429 static const struct panel_desc kyo_tcg121xglp = { 2430 .timings = &kyo_tcg121xglp_timing, 2431 .num_timings = 1, 2432 .bpc = 8, 2433 .size = { 2434 .width = 246, 2435 .height = 184, 2436 }, 2437 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2438 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2439 }; 2440 2441 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2442 .clock = 7000, 2443 .hdisplay = 320, 2444 .hsync_start = 320 + 20, 2445 .hsync_end = 320 + 20 + 30, 2446 .htotal = 320 + 20 + 30 + 38, 2447 .vdisplay = 240, 2448 .vsync_start = 240 + 4, 2449 .vsync_end = 240 + 4 + 3, 2450 .vtotal = 240 + 4 + 3 + 15, 2451 }; 2452 2453 static const struct panel_desc lemaker_bl035_rgb_002 = { 2454 .modes = &lemaker_bl035_rgb_002_mode, 2455 .num_modes = 1, 2456 .size = { 2457 .width = 70, 2458 .height = 52, 2459 }, 2460 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2461 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2462 }; 2463 2464 static const struct drm_display_mode lg_lb070wv8_mode = { 2465 .clock = 33246, 2466 .hdisplay = 800, 2467 .hsync_start = 800 + 88, 2468 .hsync_end = 800 + 88 + 80, 2469 .htotal = 800 + 88 + 80 + 88, 2470 .vdisplay = 480, 2471 .vsync_start = 480 + 10, 2472 .vsync_end = 480 + 10 + 25, 2473 .vtotal = 480 + 10 + 25 + 10, 2474 }; 2475 2476 static const struct panel_desc lg_lb070wv8 = { 2477 .modes = &lg_lb070wv8_mode, 2478 .num_modes = 1, 2479 .bpc = 8, 2480 .size = { 2481 .width = 151, 2482 .height = 91, 2483 }, 2484 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2485 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2486 }; 2487 2488 static const struct display_timing logictechno_lt161010_2nh_timing = { 2489 .pixelclock = { 26400000, 33300000, 46800000 }, 2490 .hactive = { 800, 800, 800 }, 2491 .hfront_porch = { 16, 210, 354 }, 2492 .hback_porch = { 46, 46, 46 }, 2493 .hsync_len = { 1, 20, 40 }, 2494 .vactive = { 480, 480, 480 }, 2495 .vfront_porch = { 7, 22, 147 }, 2496 .vback_porch = { 23, 23, 23 }, 2497 .vsync_len = { 1, 10, 20 }, 2498 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2499 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2500 DISPLAY_FLAGS_SYNC_POSEDGE, 2501 }; 2502 2503 static const struct panel_desc logictechno_lt161010_2nh = { 2504 .timings = &logictechno_lt161010_2nh_timing, 2505 .num_timings = 1, 2506 .size = { 2507 .width = 154, 2508 .height = 86, 2509 }, 2510 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2511 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2512 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2513 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2514 .connector_type = DRM_MODE_CONNECTOR_DPI, 2515 }; 2516 2517 static const struct display_timing logictechno_lt170410_2whc_timing = { 2518 .pixelclock = { 68900000, 71100000, 73400000 }, 2519 .hactive = { 1280, 1280, 1280 }, 2520 .hfront_porch = { 23, 60, 71 }, 2521 .hback_porch = { 23, 60, 71 }, 2522 .hsync_len = { 15, 40, 47 }, 2523 .vactive = { 800, 800, 800 }, 2524 .vfront_porch = { 5, 7, 10 }, 2525 .vback_porch = { 5, 7, 10 }, 2526 .vsync_len = { 6, 9, 12 }, 2527 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2528 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2529 DISPLAY_FLAGS_SYNC_POSEDGE, 2530 }; 2531 2532 static const struct panel_desc logictechno_lt170410_2whc = { 2533 .timings = &logictechno_lt170410_2whc_timing, 2534 .num_timings = 1, 2535 .size = { 2536 .width = 217, 2537 .height = 136, 2538 }, 2539 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2540 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2541 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2542 }; 2543 2544 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2545 .clock = 33000, 2546 .hdisplay = 800, 2547 .hsync_start = 800 + 112, 2548 .hsync_end = 800 + 112 + 3, 2549 .htotal = 800 + 112 + 3 + 85, 2550 .vdisplay = 480, 2551 .vsync_start = 480 + 38, 2552 .vsync_end = 480 + 38 + 3, 2553 .vtotal = 480 + 38 + 3 + 29, 2554 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2555 }; 2556 2557 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2558 .modes = &logictechno_lttd800480070_l2rt_mode, 2559 .num_modes = 1, 2560 .bpc = 8, 2561 .size = { 2562 .width = 154, 2563 .height = 86, 2564 }, 2565 .delay = { 2566 .prepare = 45, 2567 .enable = 100, 2568 .disable = 100, 2569 .unprepare = 45 2570 }, 2571 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2572 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2573 .connector_type = DRM_MODE_CONNECTOR_DPI, 2574 }; 2575 2576 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2577 .clock = 33000, 2578 .hdisplay = 800, 2579 .hsync_start = 800 + 154, 2580 .hsync_end = 800 + 154 + 3, 2581 .htotal = 800 + 154 + 3 + 43, 2582 .vdisplay = 480, 2583 .vsync_start = 480 + 47, 2584 .vsync_end = 480 + 47 + 3, 2585 .vtotal = 480 + 47 + 3 + 20, 2586 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2587 }; 2588 2589 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2590 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2591 .num_modes = 1, 2592 .bpc = 8, 2593 .size = { 2594 .width = 154, 2595 .height = 86, 2596 }, 2597 .delay = { 2598 .prepare = 45, 2599 .enable = 100, 2600 .disable = 100, 2601 .unprepare = 45 2602 }, 2603 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2604 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2605 .connector_type = DRM_MODE_CONNECTOR_DPI, 2606 }; 2607 2608 static const struct drm_display_mode logicpd_type_28_mode = { 2609 .clock = 9107, 2610 .hdisplay = 480, 2611 .hsync_start = 480 + 3, 2612 .hsync_end = 480 + 3 + 42, 2613 .htotal = 480 + 3 + 42 + 2, 2614 2615 .vdisplay = 272, 2616 .vsync_start = 272 + 2, 2617 .vsync_end = 272 + 2 + 11, 2618 .vtotal = 272 + 2 + 11 + 3, 2619 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2620 }; 2621 2622 static const struct panel_desc logicpd_type_28 = { 2623 .modes = &logicpd_type_28_mode, 2624 .num_modes = 1, 2625 .bpc = 8, 2626 .size = { 2627 .width = 105, 2628 .height = 67, 2629 }, 2630 .delay = { 2631 .prepare = 200, 2632 .enable = 200, 2633 .unprepare = 200, 2634 .disable = 200, 2635 }, 2636 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2637 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2638 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2639 .connector_type = DRM_MODE_CONNECTOR_DPI, 2640 }; 2641 2642 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2643 .clock = 30400, 2644 .hdisplay = 800, 2645 .hsync_start = 800 + 0, 2646 .hsync_end = 800 + 1, 2647 .htotal = 800 + 0 + 1 + 160, 2648 .vdisplay = 480, 2649 .vsync_start = 480 + 0, 2650 .vsync_end = 480 + 48 + 1, 2651 .vtotal = 480 + 48 + 1 + 0, 2652 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2653 }; 2654 2655 static const struct panel_desc mitsubishi_aa070mc01 = { 2656 .modes = &mitsubishi_aa070mc01_mode, 2657 .num_modes = 1, 2658 .bpc = 8, 2659 .size = { 2660 .width = 152, 2661 .height = 91, 2662 }, 2663 2664 .delay = { 2665 .enable = 200, 2666 .unprepare = 200, 2667 .disable = 400, 2668 }, 2669 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2670 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2671 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2672 }; 2673 2674 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2675 .pixelclock = { 29000000, 33000000, 38000000 }, 2676 .hactive = { 800, 800, 800 }, 2677 .hfront_porch = { 180, 210, 240 }, 2678 .hback_porch = { 16, 16, 16 }, 2679 .hsync_len = { 30, 30, 30 }, 2680 .vactive = { 480, 480, 480 }, 2681 .vfront_porch = { 12, 22, 32 }, 2682 .vback_porch = { 10, 10, 10 }, 2683 .vsync_len = { 13, 13, 13 }, 2684 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2685 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2686 DISPLAY_FLAGS_SYNC_POSEDGE, 2687 }; 2688 2689 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2690 .timings = &multi_inno_mi0700s4t_6_timing, 2691 .num_timings = 1, 2692 .bpc = 8, 2693 .size = { 2694 .width = 154, 2695 .height = 86, 2696 }, 2697 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2698 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2699 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2700 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2701 .connector_type = DRM_MODE_CONNECTOR_DPI, 2702 }; 2703 2704 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2705 .pixelclock = { 68900000, 70000000, 73400000 }, 2706 .hactive = { 1280, 1280, 1280 }, 2707 .hfront_porch = { 30, 60, 71 }, 2708 .hback_porch = { 30, 60, 71 }, 2709 .hsync_len = { 10, 10, 48 }, 2710 .vactive = { 800, 800, 800 }, 2711 .vfront_porch = { 5, 10, 10 }, 2712 .vback_porch = { 5, 10, 10 }, 2713 .vsync_len = { 5, 6, 13 }, 2714 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2715 DISPLAY_FLAGS_DE_HIGH, 2716 }; 2717 2718 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2719 .timings = &multi_inno_mi1010ait_1cp_timing, 2720 .num_timings = 1, 2721 .bpc = 8, 2722 .size = { 2723 .width = 217, 2724 .height = 136, 2725 }, 2726 .delay = { 2727 .enable = 50, 2728 .disable = 50, 2729 }, 2730 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2731 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2732 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2733 }; 2734 2735 static const struct display_timing nec_nl12880bc20_05_timing = { 2736 .pixelclock = { 67000000, 71000000, 75000000 }, 2737 .hactive = { 1280, 1280, 1280 }, 2738 .hfront_porch = { 2, 30, 30 }, 2739 .hback_porch = { 6, 100, 100 }, 2740 .hsync_len = { 2, 30, 30 }, 2741 .vactive = { 800, 800, 800 }, 2742 .vfront_porch = { 5, 5, 5 }, 2743 .vback_porch = { 11, 11, 11 }, 2744 .vsync_len = { 7, 7, 7 }, 2745 }; 2746 2747 static const struct panel_desc nec_nl12880bc20_05 = { 2748 .timings = &nec_nl12880bc20_05_timing, 2749 .num_timings = 1, 2750 .bpc = 8, 2751 .size = { 2752 .width = 261, 2753 .height = 163, 2754 }, 2755 .delay = { 2756 .enable = 50, 2757 .disable = 50, 2758 }, 2759 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2760 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2761 }; 2762 2763 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2764 .clock = 10870, 2765 .hdisplay = 480, 2766 .hsync_start = 480 + 2, 2767 .hsync_end = 480 + 2 + 41, 2768 .htotal = 480 + 2 + 41 + 2, 2769 .vdisplay = 272, 2770 .vsync_start = 272 + 2, 2771 .vsync_end = 272 + 2 + 4, 2772 .vtotal = 272 + 2 + 4 + 2, 2773 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2774 }; 2775 2776 static const struct panel_desc nec_nl4827hc19_05b = { 2777 .modes = &nec_nl4827hc19_05b_mode, 2778 .num_modes = 1, 2779 .bpc = 8, 2780 .size = { 2781 .width = 95, 2782 .height = 54, 2783 }, 2784 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2785 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2786 }; 2787 2788 static const struct drm_display_mode netron_dy_e231732_mode = { 2789 .clock = 66000, 2790 .hdisplay = 1024, 2791 .hsync_start = 1024 + 160, 2792 .hsync_end = 1024 + 160 + 70, 2793 .htotal = 1024 + 160 + 70 + 90, 2794 .vdisplay = 600, 2795 .vsync_start = 600 + 127, 2796 .vsync_end = 600 + 127 + 20, 2797 .vtotal = 600 + 127 + 20 + 3, 2798 }; 2799 2800 static const struct panel_desc netron_dy_e231732 = { 2801 .modes = &netron_dy_e231732_mode, 2802 .num_modes = 1, 2803 .size = { 2804 .width = 154, 2805 .height = 87, 2806 }, 2807 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2808 }; 2809 2810 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2811 .clock = 9000, 2812 .hdisplay = 480, 2813 .hsync_start = 480 + 2, 2814 .hsync_end = 480 + 2 + 41, 2815 .htotal = 480 + 2 + 41 + 2, 2816 .vdisplay = 272, 2817 .vsync_start = 272 + 2, 2818 .vsync_end = 272 + 2 + 10, 2819 .vtotal = 272 + 2 + 10 + 2, 2820 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2821 }; 2822 2823 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2824 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2825 .num_modes = 1, 2826 .bpc = 8, 2827 .size = { 2828 .width = 95, 2829 .height = 54, 2830 }, 2831 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2832 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2833 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2834 .connector_type = DRM_MODE_CONNECTOR_DPI, 2835 }; 2836 2837 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2838 .pixelclock = { 130000000, 148350000, 163000000 }, 2839 .hactive = { 1920, 1920, 1920 }, 2840 .hfront_porch = { 80, 100, 100 }, 2841 .hback_porch = { 100, 120, 120 }, 2842 .hsync_len = { 50, 60, 60 }, 2843 .vactive = { 1080, 1080, 1080 }, 2844 .vfront_porch = { 12, 30, 30 }, 2845 .vback_porch = { 4, 10, 10 }, 2846 .vsync_len = { 4, 5, 5 }, 2847 }; 2848 2849 static const struct panel_desc nlt_nl192108ac18_02d = { 2850 .timings = &nlt_nl192108ac18_02d_timing, 2851 .num_timings = 1, 2852 .bpc = 8, 2853 .size = { 2854 .width = 344, 2855 .height = 194, 2856 }, 2857 .delay = { 2858 .unprepare = 500, 2859 }, 2860 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2861 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2862 }; 2863 2864 static const struct drm_display_mode nvd_9128_mode = { 2865 .clock = 29500, 2866 .hdisplay = 800, 2867 .hsync_start = 800 + 130, 2868 .hsync_end = 800 + 130 + 98, 2869 .htotal = 800 + 0 + 130 + 98, 2870 .vdisplay = 480, 2871 .vsync_start = 480 + 10, 2872 .vsync_end = 480 + 10 + 50, 2873 .vtotal = 480 + 0 + 10 + 50, 2874 }; 2875 2876 static const struct panel_desc nvd_9128 = { 2877 .modes = &nvd_9128_mode, 2878 .num_modes = 1, 2879 .bpc = 8, 2880 .size = { 2881 .width = 156, 2882 .height = 88, 2883 }, 2884 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2885 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2886 }; 2887 2888 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 2889 .pixelclock = { 30000000, 30000000, 40000000 }, 2890 .hactive = { 800, 800, 800 }, 2891 .hfront_porch = { 40, 40, 40 }, 2892 .hback_porch = { 40, 40, 40 }, 2893 .hsync_len = { 1, 48, 48 }, 2894 .vactive = { 480, 480, 480 }, 2895 .vfront_porch = { 13, 13, 13 }, 2896 .vback_porch = { 29, 29, 29 }, 2897 .vsync_len = { 3, 3, 3 }, 2898 .flags = DISPLAY_FLAGS_DE_HIGH, 2899 }; 2900 2901 static const struct panel_desc okaya_rs800480t_7x0gp = { 2902 .timings = &okaya_rs800480t_7x0gp_timing, 2903 .num_timings = 1, 2904 .bpc = 6, 2905 .size = { 2906 .width = 154, 2907 .height = 87, 2908 }, 2909 .delay = { 2910 .prepare = 41, 2911 .enable = 50, 2912 .unprepare = 41, 2913 .disable = 50, 2914 }, 2915 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2916 }; 2917 2918 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 2919 .clock = 9000, 2920 .hdisplay = 480, 2921 .hsync_start = 480 + 5, 2922 .hsync_end = 480 + 5 + 30, 2923 .htotal = 480 + 5 + 30 + 10, 2924 .vdisplay = 272, 2925 .vsync_start = 272 + 8, 2926 .vsync_end = 272 + 8 + 5, 2927 .vtotal = 272 + 8 + 5 + 3, 2928 }; 2929 2930 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 2931 .modes = &olimex_lcd_olinuxino_43ts_mode, 2932 .num_modes = 1, 2933 .size = { 2934 .width = 95, 2935 .height = 54, 2936 }, 2937 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2938 }; 2939 2940 /* 2941 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 2942 * pixel clocks, but this is the timing that was being used in the Adafruit 2943 * installation instructions. 2944 */ 2945 static const struct drm_display_mode ontat_yx700wv03_mode = { 2946 .clock = 29500, 2947 .hdisplay = 800, 2948 .hsync_start = 824, 2949 .hsync_end = 896, 2950 .htotal = 992, 2951 .vdisplay = 480, 2952 .vsync_start = 483, 2953 .vsync_end = 493, 2954 .vtotal = 500, 2955 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2956 }; 2957 2958 /* 2959 * Specification at: 2960 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 2961 */ 2962 static const struct panel_desc ontat_yx700wv03 = { 2963 .modes = &ontat_yx700wv03_mode, 2964 .num_modes = 1, 2965 .bpc = 8, 2966 .size = { 2967 .width = 154, 2968 .height = 83, 2969 }, 2970 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2971 }; 2972 2973 static const struct drm_display_mode ortustech_com37h3m_mode = { 2974 .clock = 22230, 2975 .hdisplay = 480, 2976 .hsync_start = 480 + 40, 2977 .hsync_end = 480 + 40 + 10, 2978 .htotal = 480 + 40 + 10 + 40, 2979 .vdisplay = 640, 2980 .vsync_start = 640 + 4, 2981 .vsync_end = 640 + 4 + 2, 2982 .vtotal = 640 + 4 + 2 + 4, 2983 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2984 }; 2985 2986 static const struct panel_desc ortustech_com37h3m = { 2987 .modes = &ortustech_com37h3m_mode, 2988 .num_modes = 1, 2989 .bpc = 8, 2990 .size = { 2991 .width = 56, /* 56.16mm */ 2992 .height = 75, /* 74.88mm */ 2993 }, 2994 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2995 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2996 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2997 }; 2998 2999 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3000 .clock = 25000, 3001 .hdisplay = 480, 3002 .hsync_start = 480 + 10, 3003 .hsync_end = 480 + 10 + 10, 3004 .htotal = 480 + 10 + 10 + 15, 3005 .vdisplay = 800, 3006 .vsync_start = 800 + 3, 3007 .vsync_end = 800 + 3 + 3, 3008 .vtotal = 800 + 3 + 3 + 3, 3009 }; 3010 3011 static const struct panel_desc ortustech_com43h4m85ulc = { 3012 .modes = &ortustech_com43h4m85ulc_mode, 3013 .num_modes = 1, 3014 .bpc = 6, 3015 .size = { 3016 .width = 56, 3017 .height = 93, 3018 }, 3019 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3020 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3021 .connector_type = DRM_MODE_CONNECTOR_DPI, 3022 }; 3023 3024 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3025 .clock = 33000, 3026 .hdisplay = 800, 3027 .hsync_start = 800 + 210, 3028 .hsync_end = 800 + 210 + 30, 3029 .htotal = 800 + 210 + 30 + 16, 3030 .vdisplay = 480, 3031 .vsync_start = 480 + 22, 3032 .vsync_end = 480 + 22 + 13, 3033 .vtotal = 480 + 22 + 13 + 10, 3034 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3035 }; 3036 3037 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3038 .modes = &osddisplays_osd070t1718_19ts_mode, 3039 .num_modes = 1, 3040 .bpc = 8, 3041 .size = { 3042 .width = 152, 3043 .height = 91, 3044 }, 3045 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3046 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3047 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3048 .connector_type = DRM_MODE_CONNECTOR_DPI, 3049 }; 3050 3051 static const struct drm_display_mode pda_91_00156_a0_mode = { 3052 .clock = 33300, 3053 .hdisplay = 800, 3054 .hsync_start = 800 + 1, 3055 .hsync_end = 800 + 1 + 64, 3056 .htotal = 800 + 1 + 64 + 64, 3057 .vdisplay = 480, 3058 .vsync_start = 480 + 1, 3059 .vsync_end = 480 + 1 + 23, 3060 .vtotal = 480 + 1 + 23 + 22, 3061 }; 3062 3063 static const struct panel_desc pda_91_00156_a0 = { 3064 .modes = &pda_91_00156_a0_mode, 3065 .num_modes = 1, 3066 .size = { 3067 .width = 152, 3068 .height = 91, 3069 }, 3070 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3071 }; 3072 3073 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3074 .clock = 24750, 3075 .hdisplay = 800, 3076 .hsync_start = 800 + 54, 3077 .hsync_end = 800 + 54 + 2, 3078 .htotal = 800 + 54 + 2 + 44, 3079 .vdisplay = 480, 3080 .vsync_start = 480 + 49, 3081 .vsync_end = 480 + 49 + 2, 3082 .vtotal = 480 + 49 + 2 + 22, 3083 }; 3084 3085 static const struct panel_desc powertip_ph800480t013_idf02 = { 3086 .modes = &powertip_ph800480t013_idf02_mode, 3087 .num_modes = 1, 3088 .size = { 3089 .width = 152, 3090 .height = 91, 3091 }, 3092 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3093 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3094 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3095 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3096 .connector_type = DRM_MODE_CONNECTOR_DPI, 3097 }; 3098 3099 static const struct drm_display_mode qd43003c0_40_mode = { 3100 .clock = 9000, 3101 .hdisplay = 480, 3102 .hsync_start = 480 + 8, 3103 .hsync_end = 480 + 8 + 4, 3104 .htotal = 480 + 8 + 4 + 39, 3105 .vdisplay = 272, 3106 .vsync_start = 272 + 4, 3107 .vsync_end = 272 + 4 + 10, 3108 .vtotal = 272 + 4 + 10 + 2, 3109 }; 3110 3111 static const struct panel_desc qd43003c0_40 = { 3112 .modes = &qd43003c0_40_mode, 3113 .num_modes = 1, 3114 .bpc = 8, 3115 .size = { 3116 .width = 95, 3117 .height = 53, 3118 }, 3119 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3120 }; 3121 3122 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3123 { /* 60 Hz */ 3124 .clock = 10800, 3125 .hdisplay = 480, 3126 .hsync_start = 480 + 77, 3127 .hsync_end = 480 + 77 + 41, 3128 .htotal = 480 + 77 + 41 + 2, 3129 .vdisplay = 272, 3130 .vsync_start = 272 + 16, 3131 .vsync_end = 272 + 16 + 10, 3132 .vtotal = 272 + 16 + 10 + 2, 3133 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3134 }, 3135 { /* 50 Hz */ 3136 .clock = 10800, 3137 .hdisplay = 480, 3138 .hsync_start = 480 + 17, 3139 .hsync_end = 480 + 17 + 41, 3140 .htotal = 480 + 17 + 41 + 2, 3141 .vdisplay = 272, 3142 .vsync_start = 272 + 116, 3143 .vsync_end = 272 + 116 + 10, 3144 .vtotal = 272 + 116 + 10 + 2, 3145 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3146 }, 3147 }; 3148 3149 static const struct panel_desc qishenglong_gopher2b_lcd = { 3150 .modes = qishenglong_gopher2b_lcd_modes, 3151 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3152 .bpc = 8, 3153 .size = { 3154 .width = 95, 3155 .height = 54, 3156 }, 3157 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3158 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3159 .connector_type = DRM_MODE_CONNECTOR_DPI, 3160 }; 3161 3162 static const struct display_timing rocktech_rk070er9427_timing = { 3163 .pixelclock = { 26400000, 33300000, 46800000 }, 3164 .hactive = { 800, 800, 800 }, 3165 .hfront_porch = { 16, 210, 354 }, 3166 .hback_porch = { 46, 46, 46 }, 3167 .hsync_len = { 1, 1, 1 }, 3168 .vactive = { 480, 480, 480 }, 3169 .vfront_porch = { 7, 22, 147 }, 3170 .vback_porch = { 23, 23, 23 }, 3171 .vsync_len = { 1, 1, 1 }, 3172 .flags = DISPLAY_FLAGS_DE_HIGH, 3173 }; 3174 3175 static const struct panel_desc rocktech_rk070er9427 = { 3176 .timings = &rocktech_rk070er9427_timing, 3177 .num_timings = 1, 3178 .bpc = 6, 3179 .size = { 3180 .width = 154, 3181 .height = 86, 3182 }, 3183 .delay = { 3184 .prepare = 41, 3185 .enable = 50, 3186 .unprepare = 41, 3187 .disable = 50, 3188 }, 3189 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3190 }; 3191 3192 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3193 .clock = 71100, 3194 .hdisplay = 1280, 3195 .hsync_start = 1280 + 48, 3196 .hsync_end = 1280 + 48 + 32, 3197 .htotal = 1280 + 48 + 32 + 80, 3198 .vdisplay = 800, 3199 .vsync_start = 800 + 2, 3200 .vsync_end = 800 + 2 + 5, 3201 .vtotal = 800 + 2 + 5 + 16, 3202 }; 3203 3204 static const struct panel_desc rocktech_rk101ii01d_ct = { 3205 .modes = &rocktech_rk101ii01d_ct_mode, 3206 .bpc = 8, 3207 .num_modes = 1, 3208 .size = { 3209 .width = 217, 3210 .height = 136, 3211 }, 3212 .delay = { 3213 .prepare = 50, 3214 .disable = 50, 3215 }, 3216 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3217 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3218 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3219 }; 3220 3221 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3222 .clock = 54030, 3223 .hdisplay = 1024, 3224 .hsync_start = 1024 + 24, 3225 .hsync_end = 1024 + 24 + 136, 3226 .htotal = 1024 + 24 + 136 + 160, 3227 .vdisplay = 600, 3228 .vsync_start = 600 + 3, 3229 .vsync_end = 600 + 3 + 6, 3230 .vtotal = 600 + 3 + 6 + 61, 3231 }; 3232 3233 static const struct panel_desc samsung_ltn101nt05 = { 3234 .modes = &samsung_ltn101nt05_mode, 3235 .num_modes = 1, 3236 .bpc = 6, 3237 .size = { 3238 .width = 223, 3239 .height = 125, 3240 }, 3241 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3242 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3243 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3244 }; 3245 3246 static const struct display_timing satoz_sat050at40h12r2_timing = { 3247 .pixelclock = {33300000, 33300000, 50000000}, 3248 .hactive = {800, 800, 800}, 3249 .hfront_porch = {16, 210, 354}, 3250 .hback_porch = {46, 46, 46}, 3251 .hsync_len = {1, 1, 40}, 3252 .vactive = {480, 480, 480}, 3253 .vfront_porch = {7, 22, 147}, 3254 .vback_porch = {23, 23, 23}, 3255 .vsync_len = {1, 1, 20}, 3256 }; 3257 3258 static const struct panel_desc satoz_sat050at40h12r2 = { 3259 .timings = &satoz_sat050at40h12r2_timing, 3260 .num_timings = 1, 3261 .bpc = 8, 3262 .size = { 3263 .width = 108, 3264 .height = 65, 3265 }, 3266 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3267 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3268 }; 3269 3270 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3271 .clock = 33260, 3272 .hdisplay = 800, 3273 .hsync_start = 800 + 64, 3274 .hsync_end = 800 + 64 + 128, 3275 .htotal = 800 + 64 + 128 + 64, 3276 .vdisplay = 480, 3277 .vsync_start = 480 + 8, 3278 .vsync_end = 480 + 8 + 2, 3279 .vtotal = 480 + 8 + 2 + 35, 3280 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3281 }; 3282 3283 static const struct panel_desc sharp_lq070y3dg3b = { 3284 .modes = &sharp_lq070y3dg3b_mode, 3285 .num_modes = 1, 3286 .bpc = 8, 3287 .size = { 3288 .width = 152, /* 152.4mm */ 3289 .height = 91, /* 91.4mm */ 3290 }, 3291 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3292 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3293 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3294 }; 3295 3296 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3297 .clock = 5500, 3298 .hdisplay = 240, 3299 .hsync_start = 240 + 16, 3300 .hsync_end = 240 + 16 + 7, 3301 .htotal = 240 + 16 + 7 + 5, 3302 .vdisplay = 320, 3303 .vsync_start = 320 + 9, 3304 .vsync_end = 320 + 9 + 1, 3305 .vtotal = 320 + 9 + 1 + 7, 3306 }; 3307 3308 static const struct panel_desc sharp_lq035q7db03 = { 3309 .modes = &sharp_lq035q7db03_mode, 3310 .num_modes = 1, 3311 .bpc = 6, 3312 .size = { 3313 .width = 54, 3314 .height = 72, 3315 }, 3316 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3317 }; 3318 3319 static const struct display_timing sharp_lq101k1ly04_timing = { 3320 .pixelclock = { 60000000, 65000000, 80000000 }, 3321 .hactive = { 1280, 1280, 1280 }, 3322 .hfront_porch = { 20, 20, 20 }, 3323 .hback_porch = { 20, 20, 20 }, 3324 .hsync_len = { 10, 10, 10 }, 3325 .vactive = { 800, 800, 800 }, 3326 .vfront_porch = { 4, 4, 4 }, 3327 .vback_porch = { 4, 4, 4 }, 3328 .vsync_len = { 4, 4, 4 }, 3329 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3330 }; 3331 3332 static const struct panel_desc sharp_lq101k1ly04 = { 3333 .timings = &sharp_lq101k1ly04_timing, 3334 .num_timings = 1, 3335 .bpc = 8, 3336 .size = { 3337 .width = 217, 3338 .height = 136, 3339 }, 3340 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3341 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3342 }; 3343 3344 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3345 { /* 50 Hz */ 3346 .clock = 3000, 3347 .hdisplay = 240, 3348 .hsync_start = 240 + 58, 3349 .hsync_end = 240 + 58 + 1, 3350 .htotal = 240 + 58 + 1 + 1, 3351 .vdisplay = 160, 3352 .vsync_start = 160 + 24, 3353 .vsync_end = 160 + 24 + 10, 3354 .vtotal = 160 + 24 + 10 + 6, 3355 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3356 }, 3357 { /* 60 Hz */ 3358 .clock = 3000, 3359 .hdisplay = 240, 3360 .hsync_start = 240 + 8, 3361 .hsync_end = 240 + 8 + 1, 3362 .htotal = 240 + 8 + 1 + 1, 3363 .vdisplay = 160, 3364 .vsync_start = 160 + 24, 3365 .vsync_end = 160 + 24 + 10, 3366 .vtotal = 160 + 24 + 10 + 6, 3367 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3368 }, 3369 }; 3370 3371 static const struct panel_desc sharp_ls020b1dd01d = { 3372 .modes = sharp_ls020b1dd01d_modes, 3373 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3374 .bpc = 6, 3375 .size = { 3376 .width = 42, 3377 .height = 28, 3378 }, 3379 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3380 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3381 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3382 | DRM_BUS_FLAG_SHARP_SIGNALS, 3383 }; 3384 3385 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3386 .clock = 33300, 3387 .hdisplay = 800, 3388 .hsync_start = 800 + 1, 3389 .hsync_end = 800 + 1 + 64, 3390 .htotal = 800 + 1 + 64 + 64, 3391 .vdisplay = 480, 3392 .vsync_start = 480 + 1, 3393 .vsync_end = 480 + 1 + 23, 3394 .vtotal = 480 + 1 + 23 + 22, 3395 }; 3396 3397 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3398 .modes = &shelly_sca07010_bfn_lnn_mode, 3399 .num_modes = 1, 3400 .size = { 3401 .width = 152, 3402 .height = 91, 3403 }, 3404 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3405 }; 3406 3407 static const struct drm_display_mode starry_kr070pe2t_mode = { 3408 .clock = 33000, 3409 .hdisplay = 800, 3410 .hsync_start = 800 + 209, 3411 .hsync_end = 800 + 209 + 1, 3412 .htotal = 800 + 209 + 1 + 45, 3413 .vdisplay = 480, 3414 .vsync_start = 480 + 22, 3415 .vsync_end = 480 + 22 + 1, 3416 .vtotal = 480 + 22 + 1 + 22, 3417 }; 3418 3419 static const struct panel_desc starry_kr070pe2t = { 3420 .modes = &starry_kr070pe2t_mode, 3421 .num_modes = 1, 3422 .bpc = 8, 3423 .size = { 3424 .width = 152, 3425 .height = 86, 3426 }, 3427 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3428 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3429 .connector_type = DRM_MODE_CONNECTOR_DPI, 3430 }; 3431 3432 static const struct display_timing startek_kd070wvfpa_mode = { 3433 .pixelclock = { 25200000, 27200000, 30500000 }, 3434 .hactive = { 800, 800, 800 }, 3435 .hfront_porch = { 19, 44, 115 }, 3436 .hback_porch = { 5, 16, 101 }, 3437 .hsync_len = { 1, 2, 100 }, 3438 .vactive = { 480, 480, 480 }, 3439 .vfront_porch = { 5, 43, 67 }, 3440 .vback_porch = { 5, 5, 67 }, 3441 .vsync_len = { 1, 2, 66 }, 3442 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3443 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3444 DISPLAY_FLAGS_SYNC_POSEDGE, 3445 }; 3446 3447 static const struct panel_desc startek_kd070wvfpa = { 3448 .timings = &startek_kd070wvfpa_mode, 3449 .num_timings = 1, 3450 .bpc = 8, 3451 .size = { 3452 .width = 152, 3453 .height = 91, 3454 }, 3455 .delay = { 3456 .prepare = 20, 3457 .enable = 200, 3458 .disable = 200, 3459 }, 3460 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3461 .connector_type = DRM_MODE_CONNECTOR_DPI, 3462 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3463 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3464 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3465 }; 3466 3467 static const struct display_timing tsd_tst043015cmhx_timing = { 3468 .pixelclock = { 5000000, 9000000, 12000000 }, 3469 .hactive = { 480, 480, 480 }, 3470 .hfront_porch = { 4, 5, 65 }, 3471 .hback_porch = { 36, 40, 255 }, 3472 .hsync_len = { 1, 1, 1 }, 3473 .vactive = { 272, 272, 272 }, 3474 .vfront_porch = { 2, 8, 97 }, 3475 .vback_porch = { 3, 8, 31 }, 3476 .vsync_len = { 1, 1, 1 }, 3477 3478 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3479 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3480 }; 3481 3482 static const struct panel_desc tsd_tst043015cmhx = { 3483 .timings = &tsd_tst043015cmhx_timing, 3484 .num_timings = 1, 3485 .bpc = 8, 3486 .size = { 3487 .width = 105, 3488 .height = 67, 3489 }, 3490 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3491 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3492 }; 3493 3494 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3495 .clock = 30000, 3496 .hdisplay = 800, 3497 .hsync_start = 800 + 39, 3498 .hsync_end = 800 + 39 + 47, 3499 .htotal = 800 + 39 + 47 + 39, 3500 .vdisplay = 480, 3501 .vsync_start = 480 + 13, 3502 .vsync_end = 480 + 13 + 2, 3503 .vtotal = 480 + 13 + 2 + 29, 3504 }; 3505 3506 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3507 .modes = &tfc_s9700rtwv43tr_01b_mode, 3508 .num_modes = 1, 3509 .bpc = 8, 3510 .size = { 3511 .width = 155, 3512 .height = 90, 3513 }, 3514 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3515 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3516 }; 3517 3518 static const struct display_timing tianma_tm070jdhg30_timing = { 3519 .pixelclock = { 62600000, 68200000, 78100000 }, 3520 .hactive = { 1280, 1280, 1280 }, 3521 .hfront_porch = { 15, 64, 159 }, 3522 .hback_porch = { 5, 5, 5 }, 3523 .hsync_len = { 1, 1, 256 }, 3524 .vactive = { 800, 800, 800 }, 3525 .vfront_porch = { 3, 40, 99 }, 3526 .vback_porch = { 2, 2, 2 }, 3527 .vsync_len = { 1, 1, 128 }, 3528 .flags = DISPLAY_FLAGS_DE_HIGH, 3529 }; 3530 3531 static const struct panel_desc tianma_tm070jdhg30 = { 3532 .timings = &tianma_tm070jdhg30_timing, 3533 .num_timings = 1, 3534 .bpc = 8, 3535 .size = { 3536 .width = 151, 3537 .height = 95, 3538 }, 3539 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3540 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3541 }; 3542 3543 static const struct panel_desc tianma_tm070jvhg33 = { 3544 .timings = &tianma_tm070jdhg30_timing, 3545 .num_timings = 1, 3546 .bpc = 8, 3547 .size = { 3548 .width = 150, 3549 .height = 94, 3550 }, 3551 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3552 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3553 }; 3554 3555 static const struct display_timing tianma_tm070rvhg71_timing = { 3556 .pixelclock = { 27700000, 29200000, 39600000 }, 3557 .hactive = { 800, 800, 800 }, 3558 .hfront_porch = { 12, 40, 212 }, 3559 .hback_porch = { 88, 88, 88 }, 3560 .hsync_len = { 1, 1, 40 }, 3561 .vactive = { 480, 480, 480 }, 3562 .vfront_porch = { 1, 13, 88 }, 3563 .vback_porch = { 32, 32, 32 }, 3564 .vsync_len = { 1, 1, 3 }, 3565 .flags = DISPLAY_FLAGS_DE_HIGH, 3566 }; 3567 3568 static const struct panel_desc tianma_tm070rvhg71 = { 3569 .timings = &tianma_tm070rvhg71_timing, 3570 .num_timings = 1, 3571 .bpc = 8, 3572 .size = { 3573 .width = 154, 3574 .height = 86, 3575 }, 3576 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3577 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3578 }; 3579 3580 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3581 { 3582 .clock = 10000, 3583 .hdisplay = 320, 3584 .hsync_start = 320 + 50, 3585 .hsync_end = 320 + 50 + 6, 3586 .htotal = 320 + 50 + 6 + 38, 3587 .vdisplay = 240, 3588 .vsync_start = 240 + 3, 3589 .vsync_end = 240 + 3 + 1, 3590 .vtotal = 240 + 3 + 1 + 17, 3591 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3592 }, 3593 }; 3594 3595 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3596 .modes = ti_nspire_cx_lcd_mode, 3597 .num_modes = 1, 3598 .bpc = 8, 3599 .size = { 3600 .width = 65, 3601 .height = 49, 3602 }, 3603 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3604 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3605 }; 3606 3607 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3608 { 3609 .clock = 10000, 3610 .hdisplay = 320, 3611 .hsync_start = 320 + 6, 3612 .hsync_end = 320 + 6 + 6, 3613 .htotal = 320 + 6 + 6 + 6, 3614 .vdisplay = 240, 3615 .vsync_start = 240 + 0, 3616 .vsync_end = 240 + 0 + 1, 3617 .vtotal = 240 + 0 + 1 + 0, 3618 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3619 }, 3620 }; 3621 3622 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3623 .modes = ti_nspire_classic_lcd_mode, 3624 .num_modes = 1, 3625 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3626 .bpc = 8, 3627 .size = { 3628 .width = 71, 3629 .height = 53, 3630 }, 3631 /* This is the grayscale bus format */ 3632 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3633 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3634 }; 3635 3636 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3637 .clock = 79500, 3638 .hdisplay = 1280, 3639 .hsync_start = 1280 + 192, 3640 .hsync_end = 1280 + 192 + 128, 3641 .htotal = 1280 + 192 + 128 + 64, 3642 .vdisplay = 768, 3643 .vsync_start = 768 + 20, 3644 .vsync_end = 768 + 20 + 7, 3645 .vtotal = 768 + 20 + 7 + 3, 3646 }; 3647 3648 static const struct panel_desc toshiba_lt089ac29000 = { 3649 .modes = &toshiba_lt089ac29000_mode, 3650 .num_modes = 1, 3651 .size = { 3652 .width = 194, 3653 .height = 116, 3654 }, 3655 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3656 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3657 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3658 }; 3659 3660 static const struct drm_display_mode tpk_f07a_0102_mode = { 3661 .clock = 33260, 3662 .hdisplay = 800, 3663 .hsync_start = 800 + 40, 3664 .hsync_end = 800 + 40 + 128, 3665 .htotal = 800 + 40 + 128 + 88, 3666 .vdisplay = 480, 3667 .vsync_start = 480 + 10, 3668 .vsync_end = 480 + 10 + 2, 3669 .vtotal = 480 + 10 + 2 + 33, 3670 }; 3671 3672 static const struct panel_desc tpk_f07a_0102 = { 3673 .modes = &tpk_f07a_0102_mode, 3674 .num_modes = 1, 3675 .size = { 3676 .width = 152, 3677 .height = 91, 3678 }, 3679 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3680 }; 3681 3682 static const struct drm_display_mode tpk_f10a_0102_mode = { 3683 .clock = 45000, 3684 .hdisplay = 1024, 3685 .hsync_start = 1024 + 176, 3686 .hsync_end = 1024 + 176 + 5, 3687 .htotal = 1024 + 176 + 5 + 88, 3688 .vdisplay = 600, 3689 .vsync_start = 600 + 20, 3690 .vsync_end = 600 + 20 + 5, 3691 .vtotal = 600 + 20 + 5 + 25, 3692 }; 3693 3694 static const struct panel_desc tpk_f10a_0102 = { 3695 .modes = &tpk_f10a_0102_mode, 3696 .num_modes = 1, 3697 .size = { 3698 .width = 223, 3699 .height = 125, 3700 }, 3701 }; 3702 3703 static const struct display_timing urt_umsh_8596md_timing = { 3704 .pixelclock = { 33260000, 33260000, 33260000 }, 3705 .hactive = { 800, 800, 800 }, 3706 .hfront_porch = { 41, 41, 41 }, 3707 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3708 .hsync_len = { 71, 128, 128 }, 3709 .vactive = { 480, 480, 480 }, 3710 .vfront_porch = { 10, 10, 10 }, 3711 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3712 .vsync_len = { 2, 2, 2 }, 3713 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3714 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3715 }; 3716 3717 static const struct panel_desc urt_umsh_8596md_lvds = { 3718 .timings = &urt_umsh_8596md_timing, 3719 .num_timings = 1, 3720 .bpc = 6, 3721 .size = { 3722 .width = 152, 3723 .height = 91, 3724 }, 3725 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3726 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3727 }; 3728 3729 static const struct panel_desc urt_umsh_8596md_parallel = { 3730 .timings = &urt_umsh_8596md_timing, 3731 .num_timings = 1, 3732 .bpc = 6, 3733 .size = { 3734 .width = 152, 3735 .height = 91, 3736 }, 3737 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3738 }; 3739 3740 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 3741 .clock = 60000, 3742 .hdisplay = 1024, 3743 .hsync_start = 1024 + 160, 3744 .hsync_end = 1024 + 160 + 100, 3745 .htotal = 1024 + 160 + 100 + 60, 3746 .vdisplay = 600, 3747 .vsync_start = 600 + 12, 3748 .vsync_end = 600 + 12 + 10, 3749 .vtotal = 600 + 12 + 10 + 13, 3750 }; 3751 3752 static const struct panel_desc vivax_tpc9150_panel = { 3753 .modes = &vivax_tpc9150_panel_mode, 3754 .num_modes = 1, 3755 .bpc = 6, 3756 .size = { 3757 .width = 200, 3758 .height = 115, 3759 }, 3760 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3761 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3762 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3763 }; 3764 3765 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3766 .clock = 33333, 3767 .hdisplay = 800, 3768 .hsync_start = 800 + 210, 3769 .hsync_end = 800 + 210 + 20, 3770 .htotal = 800 + 210 + 20 + 46, 3771 .vdisplay = 480, 3772 .vsync_start = 480 + 22, 3773 .vsync_end = 480 + 22 + 10, 3774 .vtotal = 480 + 22 + 10 + 23, 3775 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3776 }; 3777 3778 static const struct panel_desc vl050_8048nt_c01 = { 3779 .modes = &vl050_8048nt_c01_mode, 3780 .num_modes = 1, 3781 .bpc = 8, 3782 .size = { 3783 .width = 120, 3784 .height = 76, 3785 }, 3786 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3787 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3788 }; 3789 3790 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 3791 .clock = 6410, 3792 .hdisplay = 320, 3793 .hsync_start = 320 + 20, 3794 .hsync_end = 320 + 20 + 30, 3795 .htotal = 320 + 20 + 30 + 38, 3796 .vdisplay = 240, 3797 .vsync_start = 240 + 4, 3798 .vsync_end = 240 + 4 + 3, 3799 .vtotal = 240 + 4 + 3 + 15, 3800 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3801 }; 3802 3803 static const struct panel_desc winstar_wf35ltiacd = { 3804 .modes = &winstar_wf35ltiacd_mode, 3805 .num_modes = 1, 3806 .bpc = 8, 3807 .size = { 3808 .width = 70, 3809 .height = 53, 3810 }, 3811 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3812 }; 3813 3814 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 3815 .clock = 51200, 3816 .hdisplay = 1024, 3817 .hsync_start = 1024 + 100, 3818 .hsync_end = 1024 + 100 + 100, 3819 .htotal = 1024 + 100 + 100 + 120, 3820 .vdisplay = 600, 3821 .vsync_start = 600 + 10, 3822 .vsync_end = 600 + 10 + 10, 3823 .vtotal = 600 + 10 + 10 + 15, 3824 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3825 }; 3826 3827 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 3828 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 3829 .num_modes = 1, 3830 .bpc = 8, 3831 .size = { 3832 .width = 154, 3833 .height = 90, 3834 }, 3835 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3836 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3837 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3838 }; 3839 3840 static const struct drm_display_mode arm_rtsm_mode[] = { 3841 { 3842 .clock = 65000, 3843 .hdisplay = 1024, 3844 .hsync_start = 1024 + 24, 3845 .hsync_end = 1024 + 24 + 136, 3846 .htotal = 1024 + 24 + 136 + 160, 3847 .vdisplay = 768, 3848 .vsync_start = 768 + 3, 3849 .vsync_end = 768 + 3 + 6, 3850 .vtotal = 768 + 3 + 6 + 29, 3851 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3852 }, 3853 }; 3854 3855 static const struct panel_desc arm_rtsm = { 3856 .modes = arm_rtsm_mode, 3857 .num_modes = 1, 3858 .bpc = 8, 3859 .size = { 3860 .width = 400, 3861 .height = 300, 3862 }, 3863 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3864 }; 3865 3866 static const struct of_device_id platform_of_match[] = { 3867 { 3868 .compatible = "ampire,am-1280800n3tzqw-t00h", 3869 .data = &ire_am_1280800n3tzqw_t00h, 3870 }, { 3871 .compatible = "ampire,am-480272h3tmqw-t01h", 3872 .data = &ire_am_480272h3tmqw_t01h, 3873 }, { 3874 .compatible = "ampire,am800480r3tmqwa1h", 3875 .data = &ire_am800480r3tmqwa1h, 3876 }, { 3877 .compatible = "ampire,am800600p5tmqw-tb8h", 3878 .data = &ire_am800600p5tmqwtb8h, 3879 }, { 3880 .compatible = "arm,rtsm-display", 3881 .data = &arm_rtsm, 3882 }, { 3883 .compatible = "armadeus,st0700-adapt", 3884 .data = &armadeus_st0700_adapt, 3885 }, { 3886 .compatible = "auo,b101aw03", 3887 .data = &auo_b101aw03, 3888 }, { 3889 .compatible = "auo,b101xtn01", 3890 .data = &auo_b101xtn01, 3891 }, { 3892 .compatible = "auo,g070vvn01", 3893 .data = &auo_g070vvn01, 3894 }, { 3895 .compatible = "auo,g101evn010", 3896 .data = &auo_g101evn010, 3897 }, { 3898 .compatible = "auo,g104sn02", 3899 .data = &auo_g104sn02, 3900 }, { 3901 .compatible = "auo,g121ean01", 3902 .data = &auo_g121ean01, 3903 }, { 3904 .compatible = "auo,g133han01", 3905 .data = &auo_g133han01, 3906 }, { 3907 .compatible = "auo,g156xtn01", 3908 .data = &auo_g156xtn01, 3909 }, { 3910 .compatible = "auo,g185han01", 3911 .data = &auo_g185han01, 3912 }, { 3913 .compatible = "auo,g190ean01", 3914 .data = &auo_g190ean01, 3915 }, { 3916 .compatible = "auo,p320hvn03", 3917 .data = &auo_p320hvn03, 3918 }, { 3919 .compatible = "auo,t215hvn01", 3920 .data = &auo_t215hvn01, 3921 }, { 3922 .compatible = "avic,tm070ddh03", 3923 .data = &avic_tm070ddh03, 3924 }, { 3925 .compatible = "bananapi,s070wv20-ct16", 3926 .data = &bananapi_s070wv20_ct16, 3927 }, { 3928 .compatible = "boe,hv070wsa-100", 3929 .data = &boe_hv070wsa 3930 }, { 3931 .compatible = "cdtech,s043wq26h-ct7", 3932 .data = &cdtech_s043wq26h_ct7, 3933 }, { 3934 .compatible = "cdtech,s070pws19hp-fc21", 3935 .data = &cdtech_s070pws19hp_fc21, 3936 }, { 3937 .compatible = "cdtech,s070swv29hg-dc44", 3938 .data = &cdtech_s070swv29hg_dc44, 3939 }, { 3940 .compatible = "cdtech,s070wv95-ct16", 3941 .data = &cdtech_s070wv95_ct16, 3942 }, { 3943 .compatible = "chefree,ch101olhlwh-002", 3944 .data = &chefree_ch101olhlwh_002, 3945 }, { 3946 .compatible = "chunghwa,claa070wp03xg", 3947 .data = &chunghwa_claa070wp03xg, 3948 }, { 3949 .compatible = "chunghwa,claa101wa01a", 3950 .data = &chunghwa_claa101wa01a 3951 }, { 3952 .compatible = "chunghwa,claa101wb01", 3953 .data = &chunghwa_claa101wb01 3954 }, { 3955 .compatible = "dataimage,fg040346dsswbg04", 3956 .data = &dataimage_fg040346dsswbg04, 3957 }, { 3958 .compatible = "dataimage,fg1001l0dsswmg01", 3959 .data = &dataimage_fg1001l0dsswmg01, 3960 }, { 3961 .compatible = "dataimage,scf0700c48ggu18", 3962 .data = &dataimage_scf0700c48ggu18, 3963 }, { 3964 .compatible = "dlc,dlc0700yzg-1", 3965 .data = &dlc_dlc0700yzg_1, 3966 }, { 3967 .compatible = "dlc,dlc1010gig", 3968 .data = &dlc_dlc1010gig, 3969 }, { 3970 .compatible = "edt,et035012dm6", 3971 .data = &edt_et035012dm6, 3972 }, { 3973 .compatible = "edt,etm0350g0dh6", 3974 .data = &edt_etm0350g0dh6, 3975 }, { 3976 .compatible = "edt,etm043080dh6gp", 3977 .data = &edt_etm043080dh6gp, 3978 }, { 3979 .compatible = "edt,etm0430g0dh6", 3980 .data = &edt_etm0430g0dh6, 3981 }, { 3982 .compatible = "edt,et057090dhu", 3983 .data = &edt_et057090dhu, 3984 }, { 3985 .compatible = "edt,et070080dh6", 3986 .data = &edt_etm0700g0dh6, 3987 }, { 3988 .compatible = "edt,etm0700g0dh6", 3989 .data = &edt_etm0700g0dh6, 3990 }, { 3991 .compatible = "edt,etm0700g0bdh6", 3992 .data = &edt_etm0700g0bdh6, 3993 }, { 3994 .compatible = "edt,etm0700g0edh6", 3995 .data = &edt_etm0700g0bdh6, 3996 }, { 3997 .compatible = "edt,etml0700y5dha", 3998 .data = &edt_etml0700y5dha, 3999 }, { 4000 .compatible = "edt,etmv570g2dhu", 4001 .data = &edt_etmv570g2dhu, 4002 }, { 4003 .compatible = "eink,vb3300-kca", 4004 .data = &eink_vb3300_kca, 4005 }, { 4006 .compatible = "evervision,vgg804821", 4007 .data = &evervision_vgg804821, 4008 }, { 4009 .compatible = "foxlink,fl500wvr00-a0t", 4010 .data = &foxlink_fl500wvr00_a0t, 4011 }, { 4012 .compatible = "frida,frd350h54004", 4013 .data = &frida_frd350h54004, 4014 }, { 4015 .compatible = "friendlyarm,hd702e", 4016 .data = &friendlyarm_hd702e, 4017 }, { 4018 .compatible = "giantplus,gpg482739qs5", 4019 .data = &giantplus_gpg482739qs5 4020 }, { 4021 .compatible = "giantplus,gpm940b0", 4022 .data = &giantplus_gpm940b0, 4023 }, { 4024 .compatible = "hannstar,hsd070pww1", 4025 .data = &hannstar_hsd070pww1, 4026 }, { 4027 .compatible = "hannstar,hsd100pxn1", 4028 .data = &hannstar_hsd100pxn1, 4029 }, { 4030 .compatible = "hannstar,hsd101pww2", 4031 .data = &hannstar_hsd101pww2, 4032 }, { 4033 .compatible = "hit,tx23d38vm0caa", 4034 .data = &hitachi_tx23d38vm0caa 4035 }, { 4036 .compatible = "innolux,at043tn24", 4037 .data = &innolux_at043tn24, 4038 }, { 4039 .compatible = "innolux,at070tn92", 4040 .data = &innolux_at070tn92, 4041 }, { 4042 .compatible = "innolux,g070y2-l01", 4043 .data = &innolux_g070y2_l01, 4044 }, { 4045 .compatible = "innolux,g070y2-t02", 4046 .data = &innolux_g070y2_t02, 4047 }, { 4048 .compatible = "innolux,g101ice-l01", 4049 .data = &innolux_g101ice_l01 4050 }, { 4051 .compatible = "innolux,g121i1-l01", 4052 .data = &innolux_g121i1_l01 4053 }, { 4054 .compatible = "innolux,g121x1-l03", 4055 .data = &innolux_g121x1_l03, 4056 }, { 4057 .compatible = "innolux,n156bge-l21", 4058 .data = &innolux_n156bge_l21, 4059 }, { 4060 .compatible = "innolux,zj070na-01p", 4061 .data = &innolux_zj070na_01p, 4062 }, { 4063 .compatible = "koe,tx14d24vm1bpa", 4064 .data = &koe_tx14d24vm1bpa, 4065 }, { 4066 .compatible = "koe,tx26d202vm0bwa", 4067 .data = &koe_tx26d202vm0bwa, 4068 }, { 4069 .compatible = "koe,tx31d200vm0baa", 4070 .data = &koe_tx31d200vm0baa, 4071 }, { 4072 .compatible = "kyo,tcg121xglp", 4073 .data = &kyo_tcg121xglp, 4074 }, { 4075 .compatible = "lemaker,bl035-rgb-002", 4076 .data = &lemaker_bl035_rgb_002, 4077 }, { 4078 .compatible = "lg,lb070wv8", 4079 .data = &lg_lb070wv8, 4080 }, { 4081 .compatible = "logicpd,type28", 4082 .data = &logicpd_type_28, 4083 }, { 4084 .compatible = "logictechno,lt161010-2nhc", 4085 .data = &logictechno_lt161010_2nh, 4086 }, { 4087 .compatible = "logictechno,lt161010-2nhr", 4088 .data = &logictechno_lt161010_2nh, 4089 }, { 4090 .compatible = "logictechno,lt170410-2whc", 4091 .data = &logictechno_lt170410_2whc, 4092 }, { 4093 .compatible = "logictechno,lttd800480070-l2rt", 4094 .data = &logictechno_lttd800480070_l2rt, 4095 }, { 4096 .compatible = "logictechno,lttd800480070-l6wh-rt", 4097 .data = &logictechno_lttd800480070_l6wh_rt, 4098 }, { 4099 .compatible = "mitsubishi,aa070mc01-ca1", 4100 .data = &mitsubishi_aa070mc01, 4101 }, { 4102 .compatible = "multi-inno,mi0700s4t-6", 4103 .data = &multi_inno_mi0700s4t_6, 4104 }, { 4105 .compatible = "multi-inno,mi1010ait-1cp", 4106 .data = &multi_inno_mi1010ait_1cp, 4107 }, { 4108 .compatible = "nec,nl12880bc20-05", 4109 .data = &nec_nl12880bc20_05, 4110 }, { 4111 .compatible = "nec,nl4827hc19-05b", 4112 .data = &nec_nl4827hc19_05b, 4113 }, { 4114 .compatible = "netron-dy,e231732", 4115 .data = &netron_dy_e231732, 4116 }, { 4117 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4118 .data = &newhaven_nhd_43_480272ef_atxl, 4119 }, { 4120 .compatible = "nlt,nl192108ac18-02d", 4121 .data = &nlt_nl192108ac18_02d, 4122 }, { 4123 .compatible = "nvd,9128", 4124 .data = &nvd_9128, 4125 }, { 4126 .compatible = "okaya,rs800480t-7x0gp", 4127 .data = &okaya_rs800480t_7x0gp, 4128 }, { 4129 .compatible = "olimex,lcd-olinuxino-43-ts", 4130 .data = &olimex_lcd_olinuxino_43ts, 4131 }, { 4132 .compatible = "ontat,yx700wv03", 4133 .data = &ontat_yx700wv03, 4134 }, { 4135 .compatible = "ortustech,com37h3m05dtc", 4136 .data = &ortustech_com37h3m, 4137 }, { 4138 .compatible = "ortustech,com37h3m99dtc", 4139 .data = &ortustech_com37h3m, 4140 }, { 4141 .compatible = "ortustech,com43h4m85ulc", 4142 .data = &ortustech_com43h4m85ulc, 4143 }, { 4144 .compatible = "osddisplays,osd070t1718-19ts", 4145 .data = &osddisplays_osd070t1718_19ts, 4146 }, { 4147 .compatible = "pda,91-00156-a0", 4148 .data = &pda_91_00156_a0, 4149 }, { 4150 .compatible = "powertip,ph800480t013-idf02", 4151 .data = &powertip_ph800480t013_idf02, 4152 }, { 4153 .compatible = "qiaodian,qd43003c0-40", 4154 .data = &qd43003c0_40, 4155 }, { 4156 .compatible = "qishenglong,gopher2b-lcd", 4157 .data = &qishenglong_gopher2b_lcd, 4158 }, { 4159 .compatible = "rocktech,rk070er9427", 4160 .data = &rocktech_rk070er9427, 4161 }, { 4162 .compatible = "rocktech,rk101ii01d-ct", 4163 .data = &rocktech_rk101ii01d_ct, 4164 }, { 4165 .compatible = "samsung,ltn101nt05", 4166 .data = &samsung_ltn101nt05, 4167 }, { 4168 .compatible = "satoz,sat050at40h12r2", 4169 .data = &satoz_sat050at40h12r2, 4170 }, { 4171 .compatible = "sharp,lq035q7db03", 4172 .data = &sharp_lq035q7db03, 4173 }, { 4174 .compatible = "sharp,lq070y3dg3b", 4175 .data = &sharp_lq070y3dg3b, 4176 }, { 4177 .compatible = "sharp,lq101k1ly04", 4178 .data = &sharp_lq101k1ly04, 4179 }, { 4180 .compatible = "sharp,ls020b1dd01d", 4181 .data = &sharp_ls020b1dd01d, 4182 }, { 4183 .compatible = "shelly,sca07010-bfn-lnn", 4184 .data = &shelly_sca07010_bfn_lnn, 4185 }, { 4186 .compatible = "starry,kr070pe2t", 4187 .data = &starry_kr070pe2t, 4188 }, { 4189 .compatible = "startek,kd070wvfpa", 4190 .data = &startek_kd070wvfpa, 4191 }, { 4192 .compatible = "team-source-display,tst043015cmhx", 4193 .data = &tsd_tst043015cmhx, 4194 }, { 4195 .compatible = "tfc,s9700rtwv43tr-01b", 4196 .data = &tfc_s9700rtwv43tr_01b, 4197 }, { 4198 .compatible = "tianma,tm070jdhg30", 4199 .data = &tianma_tm070jdhg30, 4200 }, { 4201 .compatible = "tianma,tm070jvhg33", 4202 .data = &tianma_tm070jvhg33, 4203 }, { 4204 .compatible = "tianma,tm070rvhg71", 4205 .data = &tianma_tm070rvhg71, 4206 }, { 4207 .compatible = "ti,nspire-cx-lcd-panel", 4208 .data = &ti_nspire_cx_lcd_panel, 4209 }, { 4210 .compatible = "ti,nspire-classic-lcd-panel", 4211 .data = &ti_nspire_classic_lcd_panel, 4212 }, { 4213 .compatible = "toshiba,lt089ac29000", 4214 .data = &toshiba_lt089ac29000, 4215 }, { 4216 .compatible = "tpk,f07a-0102", 4217 .data = &tpk_f07a_0102, 4218 }, { 4219 .compatible = "tpk,f10a-0102", 4220 .data = &tpk_f10a_0102, 4221 }, { 4222 .compatible = "urt,umsh-8596md-t", 4223 .data = &urt_umsh_8596md_parallel, 4224 }, { 4225 .compatible = "urt,umsh-8596md-1t", 4226 .data = &urt_umsh_8596md_parallel, 4227 }, { 4228 .compatible = "urt,umsh-8596md-7t", 4229 .data = &urt_umsh_8596md_parallel, 4230 }, { 4231 .compatible = "urt,umsh-8596md-11t", 4232 .data = &urt_umsh_8596md_lvds, 4233 }, { 4234 .compatible = "urt,umsh-8596md-19t", 4235 .data = &urt_umsh_8596md_lvds, 4236 }, { 4237 .compatible = "urt,umsh-8596md-20t", 4238 .data = &urt_umsh_8596md_parallel, 4239 }, { 4240 .compatible = "vivax,tpc9150-panel", 4241 .data = &vivax_tpc9150_panel, 4242 }, { 4243 .compatible = "vxt,vl050-8048nt-c01", 4244 .data = &vl050_8048nt_c01, 4245 }, { 4246 .compatible = "winstar,wf35ltiacd", 4247 .data = &winstar_wf35ltiacd, 4248 }, { 4249 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4250 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4251 }, { 4252 /* Must be the last entry */ 4253 .compatible = "panel-dpi", 4254 .data = &panel_dpi, 4255 }, { 4256 /* sentinel */ 4257 } 4258 }; 4259 MODULE_DEVICE_TABLE(of, platform_of_match); 4260 4261 static int panel_simple_platform_probe(struct platform_device *pdev) 4262 { 4263 const struct of_device_id *id; 4264 4265 id = of_match_node(platform_of_match, pdev->dev.of_node); 4266 if (!id) 4267 return -ENODEV; 4268 4269 return panel_simple_probe(&pdev->dev, id->data); 4270 } 4271 4272 static int panel_simple_platform_remove(struct platform_device *pdev) 4273 { 4274 return panel_simple_remove(&pdev->dev); 4275 } 4276 4277 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4278 { 4279 panel_simple_shutdown(&pdev->dev); 4280 } 4281 4282 static const struct dev_pm_ops panel_simple_pm_ops = { 4283 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4284 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4285 pm_runtime_force_resume) 4286 }; 4287 4288 static struct platform_driver panel_simple_platform_driver = { 4289 .driver = { 4290 .name = "panel-simple", 4291 .of_match_table = platform_of_match, 4292 .pm = &panel_simple_pm_ops, 4293 }, 4294 .probe = panel_simple_platform_probe, 4295 .remove = panel_simple_platform_remove, 4296 .shutdown = panel_simple_platform_shutdown, 4297 }; 4298 4299 struct panel_desc_dsi { 4300 struct panel_desc desc; 4301 4302 unsigned long flags; 4303 enum mipi_dsi_pixel_format format; 4304 unsigned int lanes; 4305 }; 4306 4307 static const struct drm_display_mode auo_b080uan01_mode = { 4308 .clock = 154500, 4309 .hdisplay = 1200, 4310 .hsync_start = 1200 + 62, 4311 .hsync_end = 1200 + 62 + 4, 4312 .htotal = 1200 + 62 + 4 + 62, 4313 .vdisplay = 1920, 4314 .vsync_start = 1920 + 9, 4315 .vsync_end = 1920 + 9 + 2, 4316 .vtotal = 1920 + 9 + 2 + 8, 4317 }; 4318 4319 static const struct panel_desc_dsi auo_b080uan01 = { 4320 .desc = { 4321 .modes = &auo_b080uan01_mode, 4322 .num_modes = 1, 4323 .bpc = 8, 4324 .size = { 4325 .width = 108, 4326 .height = 272, 4327 }, 4328 .connector_type = DRM_MODE_CONNECTOR_DSI, 4329 }, 4330 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4331 .format = MIPI_DSI_FMT_RGB888, 4332 .lanes = 4, 4333 }; 4334 4335 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4336 .clock = 160000, 4337 .hdisplay = 1200, 4338 .hsync_start = 1200 + 120, 4339 .hsync_end = 1200 + 120 + 20, 4340 .htotal = 1200 + 120 + 20 + 21, 4341 .vdisplay = 1920, 4342 .vsync_start = 1920 + 21, 4343 .vsync_end = 1920 + 21 + 3, 4344 .vtotal = 1920 + 21 + 3 + 18, 4345 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4346 }; 4347 4348 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4349 .desc = { 4350 .modes = &boe_tv080wum_nl0_mode, 4351 .num_modes = 1, 4352 .size = { 4353 .width = 107, 4354 .height = 172, 4355 }, 4356 .connector_type = DRM_MODE_CONNECTOR_DSI, 4357 }, 4358 .flags = MIPI_DSI_MODE_VIDEO | 4359 MIPI_DSI_MODE_VIDEO_BURST | 4360 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4361 .format = MIPI_DSI_FMT_RGB888, 4362 .lanes = 4, 4363 }; 4364 4365 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4366 .clock = 71000, 4367 .hdisplay = 800, 4368 .hsync_start = 800 + 32, 4369 .hsync_end = 800 + 32 + 1, 4370 .htotal = 800 + 32 + 1 + 57, 4371 .vdisplay = 1280, 4372 .vsync_start = 1280 + 28, 4373 .vsync_end = 1280 + 28 + 1, 4374 .vtotal = 1280 + 28 + 1 + 14, 4375 }; 4376 4377 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4378 .desc = { 4379 .modes = &lg_ld070wx3_sl01_mode, 4380 .num_modes = 1, 4381 .bpc = 8, 4382 .size = { 4383 .width = 94, 4384 .height = 151, 4385 }, 4386 .connector_type = DRM_MODE_CONNECTOR_DSI, 4387 }, 4388 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4389 .format = MIPI_DSI_FMT_RGB888, 4390 .lanes = 4, 4391 }; 4392 4393 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4394 .clock = 67000, 4395 .hdisplay = 720, 4396 .hsync_start = 720 + 12, 4397 .hsync_end = 720 + 12 + 4, 4398 .htotal = 720 + 12 + 4 + 112, 4399 .vdisplay = 1280, 4400 .vsync_start = 1280 + 8, 4401 .vsync_end = 1280 + 8 + 4, 4402 .vtotal = 1280 + 8 + 4 + 12, 4403 }; 4404 4405 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4406 .desc = { 4407 .modes = &lg_lh500wx1_sd03_mode, 4408 .num_modes = 1, 4409 .bpc = 8, 4410 .size = { 4411 .width = 62, 4412 .height = 110, 4413 }, 4414 .connector_type = DRM_MODE_CONNECTOR_DSI, 4415 }, 4416 .flags = MIPI_DSI_MODE_VIDEO, 4417 .format = MIPI_DSI_FMT_RGB888, 4418 .lanes = 4, 4419 }; 4420 4421 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4422 .clock = 157200, 4423 .hdisplay = 1920, 4424 .hsync_start = 1920 + 154, 4425 .hsync_end = 1920 + 154 + 16, 4426 .htotal = 1920 + 154 + 16 + 32, 4427 .vdisplay = 1200, 4428 .vsync_start = 1200 + 17, 4429 .vsync_end = 1200 + 17 + 2, 4430 .vtotal = 1200 + 17 + 2 + 16, 4431 }; 4432 4433 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4434 .desc = { 4435 .modes = &panasonic_vvx10f004b00_mode, 4436 .num_modes = 1, 4437 .bpc = 8, 4438 .size = { 4439 .width = 217, 4440 .height = 136, 4441 }, 4442 .connector_type = DRM_MODE_CONNECTOR_DSI, 4443 }, 4444 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4445 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4446 .format = MIPI_DSI_FMT_RGB888, 4447 .lanes = 4, 4448 }; 4449 4450 static const struct drm_display_mode lg_acx467akm_7_mode = { 4451 .clock = 150000, 4452 .hdisplay = 1080, 4453 .hsync_start = 1080 + 2, 4454 .hsync_end = 1080 + 2 + 2, 4455 .htotal = 1080 + 2 + 2 + 2, 4456 .vdisplay = 1920, 4457 .vsync_start = 1920 + 2, 4458 .vsync_end = 1920 + 2 + 2, 4459 .vtotal = 1920 + 2 + 2 + 2, 4460 }; 4461 4462 static const struct panel_desc_dsi lg_acx467akm_7 = { 4463 .desc = { 4464 .modes = &lg_acx467akm_7_mode, 4465 .num_modes = 1, 4466 .bpc = 8, 4467 .size = { 4468 .width = 62, 4469 .height = 110, 4470 }, 4471 .connector_type = DRM_MODE_CONNECTOR_DSI, 4472 }, 4473 .flags = 0, 4474 .format = MIPI_DSI_FMT_RGB888, 4475 .lanes = 4, 4476 }; 4477 4478 static const struct drm_display_mode osd101t2045_53ts_mode = { 4479 .clock = 154500, 4480 .hdisplay = 1920, 4481 .hsync_start = 1920 + 112, 4482 .hsync_end = 1920 + 112 + 16, 4483 .htotal = 1920 + 112 + 16 + 32, 4484 .vdisplay = 1200, 4485 .vsync_start = 1200 + 16, 4486 .vsync_end = 1200 + 16 + 2, 4487 .vtotal = 1200 + 16 + 2 + 16, 4488 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4489 }; 4490 4491 static const struct panel_desc_dsi osd101t2045_53ts = { 4492 .desc = { 4493 .modes = &osd101t2045_53ts_mode, 4494 .num_modes = 1, 4495 .bpc = 8, 4496 .size = { 4497 .width = 217, 4498 .height = 136, 4499 }, 4500 .connector_type = DRM_MODE_CONNECTOR_DSI, 4501 }, 4502 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4503 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4504 MIPI_DSI_MODE_NO_EOT_PACKET, 4505 .format = MIPI_DSI_FMT_RGB888, 4506 .lanes = 4, 4507 }; 4508 4509 static const struct of_device_id dsi_of_match[] = { 4510 { 4511 .compatible = "auo,b080uan01", 4512 .data = &auo_b080uan01 4513 }, { 4514 .compatible = "boe,tv080wum-nl0", 4515 .data = &boe_tv080wum_nl0 4516 }, { 4517 .compatible = "lg,ld070wx3-sl01", 4518 .data = &lg_ld070wx3_sl01 4519 }, { 4520 .compatible = "lg,lh500wx1-sd03", 4521 .data = &lg_lh500wx1_sd03 4522 }, { 4523 .compatible = "panasonic,vvx10f004b00", 4524 .data = &panasonic_vvx10f004b00 4525 }, { 4526 .compatible = "lg,acx467akm-7", 4527 .data = &lg_acx467akm_7 4528 }, { 4529 .compatible = "osddisplays,osd101t2045-53ts", 4530 .data = &osd101t2045_53ts 4531 }, { 4532 /* sentinel */ 4533 } 4534 }; 4535 MODULE_DEVICE_TABLE(of, dsi_of_match); 4536 4537 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4538 { 4539 const struct panel_desc_dsi *desc; 4540 const struct of_device_id *id; 4541 int err; 4542 4543 id = of_match_node(dsi_of_match, dsi->dev.of_node); 4544 if (!id) 4545 return -ENODEV; 4546 4547 desc = id->data; 4548 4549 err = panel_simple_probe(&dsi->dev, &desc->desc); 4550 if (err < 0) 4551 return err; 4552 4553 dsi->mode_flags = desc->flags; 4554 dsi->format = desc->format; 4555 dsi->lanes = desc->lanes; 4556 4557 err = mipi_dsi_attach(dsi); 4558 if (err) { 4559 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4560 4561 drm_panel_remove(&panel->base); 4562 } 4563 4564 return err; 4565 } 4566 4567 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4568 { 4569 int err; 4570 4571 err = mipi_dsi_detach(dsi); 4572 if (err < 0) 4573 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4574 4575 return panel_simple_remove(&dsi->dev); 4576 } 4577 4578 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4579 { 4580 panel_simple_shutdown(&dsi->dev); 4581 } 4582 4583 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4584 .driver = { 4585 .name = "panel-simple-dsi", 4586 .of_match_table = dsi_of_match, 4587 .pm = &panel_simple_pm_ops, 4588 }, 4589 .probe = panel_simple_dsi_probe, 4590 .remove = panel_simple_dsi_remove, 4591 .shutdown = panel_simple_dsi_shutdown, 4592 }; 4593 4594 static int __init panel_simple_init(void) 4595 { 4596 int err; 4597 4598 err = platform_driver_register(&panel_simple_platform_driver); 4599 if (err < 0) 4600 return err; 4601 4602 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4603 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4604 if (err < 0) 4605 goto err_did_platform_register; 4606 } 4607 4608 return 0; 4609 4610 err_did_platform_register: 4611 platform_driver_unregister(&panel_simple_platform_driver); 4612 4613 return err; 4614 } 4615 module_init(panel_simple_init); 4616 4617 static void __exit panel_simple_exit(void) 4618 { 4619 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4620 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4621 4622 platform_driver_unregister(&panel_simple_platform_driver); 4623 } 4624 module_exit(panel_simple_exit); 4625 4626 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4627 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4628 MODULE_LICENSE("GPL and additional rights"); 4629