1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 142 ktime_t unprepared_time; 143 144 const struct panel_desc *desc; 145 146 struct regulator *supply; 147 struct i2c_adapter *ddc; 148 149 struct gpio_desc *enable_gpio; 150 151 const struct drm_edid *drm_edid; 152 153 struct drm_display_mode override_mode; 154 155 enum drm_panel_orientation orientation; 156 }; 157 158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 159 { 160 return container_of(panel, struct panel_simple, base); 161 } 162 163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 164 struct drm_connector *connector) 165 { 166 struct drm_display_mode *mode; 167 unsigned int i, num = 0; 168 169 for (i = 0; i < panel->desc->num_timings; i++) { 170 const struct display_timing *dt = &panel->desc->timings[i]; 171 struct videomode vm; 172 173 videomode_from_timing(dt, &vm); 174 mode = drm_mode_create(connector->dev); 175 if (!mode) { 176 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 177 dt->hactive.typ, dt->vactive.typ); 178 continue; 179 } 180 181 drm_display_mode_from_videomode(&vm, mode); 182 183 mode->type |= DRM_MODE_TYPE_DRIVER; 184 185 if (panel->desc->num_timings == 1) 186 mode->type |= DRM_MODE_TYPE_PREFERRED; 187 188 drm_mode_probed_add(connector, mode); 189 num++; 190 } 191 192 return num; 193 } 194 195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 196 struct drm_connector *connector) 197 { 198 struct drm_display_mode *mode; 199 unsigned int i, num = 0; 200 201 for (i = 0; i < panel->desc->num_modes; i++) { 202 const struct drm_display_mode *m = &panel->desc->modes[i]; 203 204 mode = drm_mode_duplicate(connector->dev, m); 205 if (!mode) { 206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 207 m->hdisplay, m->vdisplay, 208 drm_mode_vrefresh(m)); 209 continue; 210 } 211 212 mode->type |= DRM_MODE_TYPE_DRIVER; 213 214 if (panel->desc->num_modes == 1) 215 mode->type |= DRM_MODE_TYPE_PREFERRED; 216 217 drm_mode_set_name(mode); 218 219 drm_mode_probed_add(connector, mode); 220 num++; 221 } 222 223 return num; 224 } 225 226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 227 struct drm_connector *connector) 228 { 229 struct drm_display_mode *mode; 230 bool has_override = panel->override_mode.type; 231 unsigned int num = 0; 232 233 if (!panel->desc) 234 return 0; 235 236 if (has_override) { 237 mode = drm_mode_duplicate(connector->dev, 238 &panel->override_mode); 239 if (mode) { 240 drm_mode_probed_add(connector, mode); 241 num = 1; 242 } else { 243 dev_err(panel->base.dev, "failed to add override mode\n"); 244 } 245 } 246 247 /* Only add timings if override was not there or failed to validate */ 248 if (num == 0 && panel->desc->num_timings) 249 num = panel_simple_get_timings_modes(panel, connector); 250 251 /* 252 * Only add fixed modes if timings/override added no mode. 253 * 254 * We should only ever have either the display timings specified 255 * or a fixed mode. Anything else is rather bogus. 256 */ 257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 258 if (num == 0) 259 num = panel_simple_get_display_modes(panel, connector); 260 261 connector->display_info.bpc = panel->desc->bpc; 262 connector->display_info.width_mm = panel->desc->size.width; 263 connector->display_info.height_mm = panel->desc->size.height; 264 if (panel->desc->bus_format) 265 drm_display_info_set_bus_formats(&connector->display_info, 266 &panel->desc->bus_format, 1); 267 connector->display_info.bus_flags = panel->desc->bus_flags; 268 269 return num; 270 } 271 272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 273 { 274 ktime_t now_ktime, min_ktime; 275 276 if (!min_ms) 277 return; 278 279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 280 now_ktime = ktime_get_boottime(); 281 282 if (ktime_before(now_ktime, min_ktime)) 283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 284 } 285 286 static int panel_simple_disable(struct drm_panel *panel) 287 { 288 struct panel_simple *p = to_panel_simple(panel); 289 290 if (p->desc->delay.disable) 291 msleep(p->desc->delay.disable); 292 293 return 0; 294 } 295 296 static int panel_simple_suspend(struct device *dev) 297 { 298 struct panel_simple *p = dev_get_drvdata(dev); 299 300 gpiod_set_value_cansleep(p->enable_gpio, 0); 301 regulator_disable(p->supply); 302 p->unprepared_time = ktime_get_boottime(); 303 304 drm_edid_free(p->drm_edid); 305 p->drm_edid = NULL; 306 307 return 0; 308 } 309 310 static int panel_simple_unprepare(struct drm_panel *panel) 311 { 312 int ret; 313 314 pm_runtime_mark_last_busy(panel->dev); 315 ret = pm_runtime_put_autosuspend(panel->dev); 316 if (ret < 0) 317 return ret; 318 319 return 0; 320 } 321 322 static int panel_simple_resume(struct device *dev) 323 { 324 struct panel_simple *p = dev_get_drvdata(dev); 325 int err; 326 327 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 328 329 err = regulator_enable(p->supply); 330 if (err < 0) { 331 dev_err(dev, "failed to enable supply: %d\n", err); 332 return err; 333 } 334 335 gpiod_set_value_cansleep(p->enable_gpio, 1); 336 337 if (p->desc->delay.prepare) 338 msleep(p->desc->delay.prepare); 339 340 return 0; 341 } 342 343 static int panel_simple_prepare(struct drm_panel *panel) 344 { 345 int ret; 346 347 ret = pm_runtime_get_sync(panel->dev); 348 if (ret < 0) { 349 pm_runtime_put_autosuspend(panel->dev); 350 return ret; 351 } 352 353 return 0; 354 } 355 356 static int panel_simple_enable(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 360 if (p->desc->delay.enable) 361 msleep(p->desc->delay.enable); 362 363 return 0; 364 } 365 366 static int panel_simple_get_modes(struct drm_panel *panel, 367 struct drm_connector *connector) 368 { 369 struct panel_simple *p = to_panel_simple(panel); 370 int num = 0; 371 372 /* probe EDID if a DDC bus is available */ 373 if (p->ddc) { 374 pm_runtime_get_sync(panel->dev); 375 376 if (!p->drm_edid) 377 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 378 379 drm_edid_connector_update(connector, p->drm_edid); 380 381 num += drm_edid_connector_add_modes(connector); 382 383 pm_runtime_mark_last_busy(panel->dev); 384 pm_runtime_put_autosuspend(panel->dev); 385 } 386 387 /* add hard-coded panel modes */ 388 num += panel_simple_get_non_edid_modes(p, connector); 389 390 /* 391 * TODO: Remove once all drm drivers call 392 * drm_connector_set_orientation_from_panel() 393 */ 394 drm_connector_set_panel_orientation(connector, p->orientation); 395 396 return num; 397 } 398 399 static int panel_simple_get_timings(struct drm_panel *panel, 400 unsigned int num_timings, 401 struct display_timing *timings) 402 { 403 struct panel_simple *p = to_panel_simple(panel); 404 unsigned int i; 405 406 if (p->desc->num_timings < num_timings) 407 num_timings = p->desc->num_timings; 408 409 if (timings) 410 for (i = 0; i < num_timings; i++) 411 timings[i] = p->desc->timings[i]; 412 413 return p->desc->num_timings; 414 } 415 416 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 417 { 418 struct panel_simple *p = to_panel_simple(panel); 419 420 return p->orientation; 421 } 422 423 static const struct drm_panel_funcs panel_simple_funcs = { 424 .disable = panel_simple_disable, 425 .unprepare = panel_simple_unprepare, 426 .prepare = panel_simple_prepare, 427 .enable = panel_simple_enable, 428 .get_modes = panel_simple_get_modes, 429 .get_orientation = panel_simple_get_orientation, 430 .get_timings = panel_simple_get_timings, 431 }; 432 433 static struct panel_desc panel_dpi; 434 435 static int panel_dpi_probe(struct device *dev, 436 struct panel_simple *panel) 437 { 438 struct display_timing *timing; 439 const struct device_node *np; 440 struct panel_desc *desc; 441 unsigned int bus_flags; 442 struct videomode vm; 443 int ret; 444 445 np = dev->of_node; 446 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 447 if (!desc) 448 return -ENOMEM; 449 450 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 451 if (!timing) 452 return -ENOMEM; 453 454 ret = of_get_display_timing(np, "panel-timing", timing); 455 if (ret < 0) { 456 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 457 np); 458 return ret; 459 } 460 461 desc->timings = timing; 462 desc->num_timings = 1; 463 464 of_property_read_u32(np, "width-mm", &desc->size.width); 465 of_property_read_u32(np, "height-mm", &desc->size.height); 466 467 /* Extract bus_flags from display_timing */ 468 bus_flags = 0; 469 vm.flags = timing->flags; 470 drm_bus_flags_from_videomode(&vm, &bus_flags); 471 desc->bus_flags = bus_flags; 472 473 /* We do not know the connector for the DT node, so guess it */ 474 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 475 476 panel->desc = desc; 477 478 return 0; 479 } 480 481 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 482 (to_check->field.typ >= bounds->field.min && \ 483 to_check->field.typ <= bounds->field.max) 484 static void panel_simple_parse_panel_timing_node(struct device *dev, 485 struct panel_simple *panel, 486 const struct display_timing *ot) 487 { 488 const struct panel_desc *desc = panel->desc; 489 struct videomode vm; 490 unsigned int i; 491 492 if (WARN_ON(desc->num_modes)) { 493 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 494 return; 495 } 496 if (WARN_ON(!desc->num_timings)) { 497 dev_err(dev, "Reject override mode: no timings specified\n"); 498 return; 499 } 500 501 for (i = 0; i < panel->desc->num_timings; i++) { 502 const struct display_timing *dt = &panel->desc->timings[i]; 503 504 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 505 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 506 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 507 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 508 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 512 continue; 513 514 if (ot->flags != dt->flags) 515 continue; 516 517 videomode_from_timing(ot, &vm); 518 drm_display_mode_from_videomode(&vm, &panel->override_mode); 519 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 520 DRM_MODE_TYPE_PREFERRED; 521 break; 522 } 523 524 if (WARN_ON(!panel->override_mode.type)) 525 dev_err(dev, "Reject override mode: No display_timing found\n"); 526 } 527 528 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 529 struct panel_simple *panel) 530 { 531 int ret, bpc; 532 533 ret = drm_of_lvds_get_data_mapping(dev->of_node); 534 if (ret < 0) { 535 if (ret == -EINVAL) 536 dev_warn(dev, "Ignore invalid data-mapping property\n"); 537 538 /* 539 * Ignore non-existing or malformatted property, fallback to 540 * default data-mapping, and return 0. 541 */ 542 return 0; 543 } 544 545 switch (ret) { 546 default: 547 WARN_ON(1); 548 fallthrough; 549 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 550 fallthrough; 551 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 552 bpc = 8; 553 break; 554 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 555 bpc = 6; 556 } 557 558 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 559 struct panel_desc *override_desc; 560 561 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 562 if (!override_desc) 563 return -ENOMEM; 564 565 override_desc->bus_format = ret; 566 override_desc->bpc = bpc; 567 panel->desc = override_desc; 568 } 569 570 return 0; 571 } 572 573 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 574 { 575 struct panel_simple *panel; 576 struct display_timing dt; 577 struct device_node *ddc; 578 int connector_type; 579 u32 bus_flags; 580 int err; 581 582 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 583 if (!panel) 584 return -ENOMEM; 585 586 panel->desc = desc; 587 588 panel->supply = devm_regulator_get(dev, "power"); 589 if (IS_ERR(panel->supply)) 590 return PTR_ERR(panel->supply); 591 592 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 593 GPIOD_OUT_LOW); 594 if (IS_ERR(panel->enable_gpio)) 595 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 596 "failed to request GPIO\n"); 597 598 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 599 if (err) { 600 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 601 return err; 602 } 603 604 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 605 if (ddc) { 606 panel->ddc = of_find_i2c_adapter_by_node(ddc); 607 of_node_put(ddc); 608 609 if (!panel->ddc) 610 return -EPROBE_DEFER; 611 } 612 613 if (desc == &panel_dpi) { 614 /* Handle the generic panel-dpi binding */ 615 err = panel_dpi_probe(dev, panel); 616 if (err) 617 goto free_ddc; 618 desc = panel->desc; 619 } else { 620 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 621 panel_simple_parse_panel_timing_node(dev, panel, &dt); 622 } 623 624 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 625 /* Optional data-mapping property for overriding bus format */ 626 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 627 if (err) 628 goto free_ddc; 629 } 630 631 connector_type = desc->connector_type; 632 /* Catch common mistakes for panels. */ 633 switch (connector_type) { 634 case 0: 635 dev_warn(dev, "Specify missing connector_type\n"); 636 connector_type = DRM_MODE_CONNECTOR_DPI; 637 break; 638 case DRM_MODE_CONNECTOR_LVDS: 639 WARN_ON(desc->bus_flags & 640 ~(DRM_BUS_FLAG_DE_LOW | 641 DRM_BUS_FLAG_DE_HIGH | 642 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 643 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 644 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 645 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 646 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 647 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 648 desc->bpc != 6); 649 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 650 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 651 desc->bpc != 8); 652 break; 653 case DRM_MODE_CONNECTOR_eDP: 654 dev_warn(dev, "eDP panels moved to panel-edp\n"); 655 err = -EINVAL; 656 goto free_ddc; 657 case DRM_MODE_CONNECTOR_DSI: 658 if (desc->bpc != 6 && desc->bpc != 8) 659 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 660 break; 661 case DRM_MODE_CONNECTOR_DPI: 662 bus_flags = DRM_BUS_FLAG_DE_LOW | 663 DRM_BUS_FLAG_DE_HIGH | 664 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 665 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 666 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 667 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 668 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 669 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 670 if (desc->bus_flags & ~bus_flags) 671 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 672 if (!(desc->bus_flags & bus_flags)) 673 dev_warn(dev, "Specify missing bus_flags\n"); 674 if (desc->bus_format == 0) 675 dev_warn(dev, "Specify missing bus_format\n"); 676 if (desc->bpc != 6 && desc->bpc != 8) 677 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 678 break; 679 default: 680 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 681 connector_type = DRM_MODE_CONNECTOR_DPI; 682 break; 683 } 684 685 dev_set_drvdata(dev, panel); 686 687 /* 688 * We use runtime PM for prepare / unprepare since those power the panel 689 * on and off and those can be very slow operations. This is important 690 * to optimize powering the panel on briefly to read the EDID before 691 * fully enabling the panel. 692 */ 693 pm_runtime_enable(dev); 694 pm_runtime_set_autosuspend_delay(dev, 1000); 695 pm_runtime_use_autosuspend(dev); 696 697 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 698 699 err = drm_panel_of_backlight(&panel->base); 700 if (err) { 701 dev_err_probe(dev, err, "Could not find backlight\n"); 702 goto disable_pm_runtime; 703 } 704 705 drm_panel_add(&panel->base); 706 707 return 0; 708 709 disable_pm_runtime: 710 pm_runtime_dont_use_autosuspend(dev); 711 pm_runtime_disable(dev); 712 free_ddc: 713 if (panel->ddc) 714 put_device(&panel->ddc->dev); 715 716 return err; 717 } 718 719 static void panel_simple_shutdown(struct device *dev) 720 { 721 struct panel_simple *panel = dev_get_drvdata(dev); 722 723 /* 724 * NOTE: the following two calls don't really belong here. It is the 725 * responsibility of a correctly written DRM modeset driver to call 726 * drm_atomic_helper_shutdown() at shutdown time and that should 727 * cause the panel to be disabled / unprepared if needed. For now, 728 * however, we'll keep these calls due to the sheer number of 729 * different DRM modeset drivers used with panel-simple. The fact that 730 * we're calling these and _also_ the drm_atomic_helper_shutdown() 731 * will try to disable/unprepare means that we can get a warning about 732 * trying to disable/unprepare an already disabled/unprepared panel, 733 * but that's something we'll have to live with until we've confirmed 734 * that all DRM modeset drivers are properly calling 735 * drm_atomic_helper_shutdown(). 736 */ 737 drm_panel_disable(&panel->base); 738 drm_panel_unprepare(&panel->base); 739 } 740 741 static void panel_simple_remove(struct device *dev) 742 { 743 struct panel_simple *panel = dev_get_drvdata(dev); 744 745 drm_panel_remove(&panel->base); 746 panel_simple_shutdown(dev); 747 748 pm_runtime_dont_use_autosuspend(dev); 749 pm_runtime_disable(dev); 750 if (panel->ddc) 751 put_device(&panel->ddc->dev); 752 } 753 754 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 755 .clock = 71100, 756 .hdisplay = 1280, 757 .hsync_start = 1280 + 40, 758 .hsync_end = 1280 + 40 + 80, 759 .htotal = 1280 + 40 + 80 + 40, 760 .vdisplay = 800, 761 .vsync_start = 800 + 3, 762 .vsync_end = 800 + 3 + 10, 763 .vtotal = 800 + 3 + 10 + 10, 764 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 765 }; 766 767 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 768 .modes = &ire_am_1280800n3tzqw_t00h_mode, 769 .num_modes = 1, 770 .bpc = 8, 771 .size = { 772 .width = 217, 773 .height = 136, 774 }, 775 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 776 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 777 .connector_type = DRM_MODE_CONNECTOR_LVDS, 778 }; 779 780 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 781 .clock = 9000, 782 .hdisplay = 480, 783 .hsync_start = 480 + 2, 784 .hsync_end = 480 + 2 + 41, 785 .htotal = 480 + 2 + 41 + 2, 786 .vdisplay = 272, 787 .vsync_start = 272 + 2, 788 .vsync_end = 272 + 2 + 10, 789 .vtotal = 272 + 2 + 10 + 2, 790 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 791 }; 792 793 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 794 .modes = &ire_am_480272h3tmqw_t01h_mode, 795 .num_modes = 1, 796 .bpc = 8, 797 .size = { 798 .width = 99, 799 .height = 58, 800 }, 801 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 802 }; 803 804 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 805 .clock = 33333, 806 .hdisplay = 800, 807 .hsync_start = 800 + 0, 808 .hsync_end = 800 + 0 + 255, 809 .htotal = 800 + 0 + 255 + 0, 810 .vdisplay = 480, 811 .vsync_start = 480 + 2, 812 .vsync_end = 480 + 2 + 45, 813 .vtotal = 480 + 2 + 45 + 0, 814 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 815 }; 816 817 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 818 .pixelclock = { 29930000, 33260000, 36590000 }, 819 .hactive = { 800, 800, 800 }, 820 .hfront_porch = { 1, 40, 168 }, 821 .hback_porch = { 88, 88, 88 }, 822 .hsync_len = { 1, 128, 128 }, 823 .vactive = { 480, 480, 480 }, 824 .vfront_porch = { 1, 35, 37 }, 825 .vback_porch = { 8, 8, 8 }, 826 .vsync_len = { 1, 2, 2 }, 827 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 828 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 829 DISPLAY_FLAGS_SYNC_POSEDGE, 830 }; 831 832 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 833 .timings = &ire_am_800480l1tmqw_t00h_timing, 834 .num_timings = 1, 835 .bpc = 8, 836 .size = { 837 .width = 111, 838 .height = 67, 839 }, 840 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 841 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 842 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 843 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 844 .connector_type = DRM_MODE_CONNECTOR_DPI, 845 }; 846 847 static const struct panel_desc ampire_am800480r3tmqwa1h = { 848 .modes = &ire_am800480r3tmqwa1h_mode, 849 .num_modes = 1, 850 .bpc = 6, 851 .size = { 852 .width = 152, 853 .height = 91, 854 }, 855 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 856 }; 857 858 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 859 .pixelclock = { 34500000, 39600000, 50400000 }, 860 .hactive = { 800, 800, 800 }, 861 .hfront_porch = { 12, 112, 312 }, 862 .hback_porch = { 87, 87, 48 }, 863 .hsync_len = { 1, 1, 40 }, 864 .vactive = { 600, 600, 600 }, 865 .vfront_porch = { 1, 21, 61 }, 866 .vback_porch = { 38, 38, 19 }, 867 .vsync_len = { 1, 1, 20 }, 868 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 869 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 870 DISPLAY_FLAGS_SYNC_POSEDGE, 871 }; 872 873 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 874 .timings = &ire_am800600p5tmqw_tb8h_timing, 875 .num_timings = 1, 876 .bpc = 6, 877 .size = { 878 .width = 162, 879 .height = 122, 880 }, 881 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 882 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 883 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 884 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 885 .connector_type = DRM_MODE_CONNECTOR_DPI, 886 }; 887 888 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 889 .pixelclock = { 26400000, 33300000, 46800000 }, 890 .hactive = { 800, 800, 800 }, 891 .hfront_porch = { 16, 210, 354 }, 892 .hback_porch = { 45, 36, 6 }, 893 .hsync_len = { 1, 10, 40 }, 894 .vactive = { 480, 480, 480 }, 895 .vfront_porch = { 7, 22, 147 }, 896 .vback_porch = { 22, 13, 3 }, 897 .vsync_len = { 1, 10, 20 }, 898 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 899 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 900 }; 901 902 static const struct panel_desc armadeus_st0700_adapt = { 903 .timings = &santek_st0700i5y_rbslw_f_timing, 904 .num_timings = 1, 905 .bpc = 6, 906 .size = { 907 .width = 154, 908 .height = 86, 909 }, 910 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 911 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 912 }; 913 914 static const struct drm_display_mode auo_b101aw03_mode = { 915 .clock = 51450, 916 .hdisplay = 1024, 917 .hsync_start = 1024 + 156, 918 .hsync_end = 1024 + 156 + 8, 919 .htotal = 1024 + 156 + 8 + 156, 920 .vdisplay = 600, 921 .vsync_start = 600 + 16, 922 .vsync_end = 600 + 16 + 6, 923 .vtotal = 600 + 16 + 6 + 16, 924 }; 925 926 static const struct panel_desc auo_b101aw03 = { 927 .modes = &auo_b101aw03_mode, 928 .num_modes = 1, 929 .bpc = 6, 930 .size = { 931 .width = 223, 932 .height = 125, 933 }, 934 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 935 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 936 .connector_type = DRM_MODE_CONNECTOR_LVDS, 937 }; 938 939 static const struct drm_display_mode auo_b101xtn01_mode = { 940 .clock = 72000, 941 .hdisplay = 1366, 942 .hsync_start = 1366 + 20, 943 .hsync_end = 1366 + 20 + 70, 944 .htotal = 1366 + 20 + 70, 945 .vdisplay = 768, 946 .vsync_start = 768 + 14, 947 .vsync_end = 768 + 14 + 42, 948 .vtotal = 768 + 14 + 42, 949 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 950 }; 951 952 static const struct panel_desc auo_b101xtn01 = { 953 .modes = &auo_b101xtn01_mode, 954 .num_modes = 1, 955 .bpc = 6, 956 .size = { 957 .width = 223, 958 .height = 125, 959 }, 960 }; 961 962 static const struct drm_display_mode auo_b116xw03_mode = { 963 .clock = 70589, 964 .hdisplay = 1366, 965 .hsync_start = 1366 + 40, 966 .hsync_end = 1366 + 40 + 40, 967 .htotal = 1366 + 40 + 40 + 32, 968 .vdisplay = 768, 969 .vsync_start = 768 + 10, 970 .vsync_end = 768 + 10 + 12, 971 .vtotal = 768 + 10 + 12 + 6, 972 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 973 }; 974 975 static const struct panel_desc auo_b116xw03 = { 976 .modes = &auo_b116xw03_mode, 977 .num_modes = 1, 978 .bpc = 6, 979 .size = { 980 .width = 256, 981 .height = 144, 982 }, 983 .delay = { 984 .prepare = 1, 985 .enable = 200, 986 .disable = 200, 987 .unprepare = 500, 988 }, 989 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 990 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 991 .connector_type = DRM_MODE_CONNECTOR_LVDS, 992 }; 993 994 static const struct display_timing auo_g070vvn01_timings = { 995 .pixelclock = { 33300000, 34209000, 45000000 }, 996 .hactive = { 800, 800, 800 }, 997 .hfront_porch = { 20, 40, 200 }, 998 .hback_porch = { 87, 40, 1 }, 999 .hsync_len = { 1, 48, 87 }, 1000 .vactive = { 480, 480, 480 }, 1001 .vfront_porch = { 5, 13, 200 }, 1002 .vback_porch = { 31, 31, 29 }, 1003 .vsync_len = { 1, 1, 3 }, 1004 }; 1005 1006 static const struct panel_desc auo_g070vvn01 = { 1007 .timings = &auo_g070vvn01_timings, 1008 .num_timings = 1, 1009 .bpc = 8, 1010 .size = { 1011 .width = 152, 1012 .height = 91, 1013 }, 1014 .delay = { 1015 .prepare = 200, 1016 .enable = 50, 1017 .disable = 50, 1018 .unprepare = 1000, 1019 }, 1020 }; 1021 1022 static const struct drm_display_mode auo_g101evn010_mode = { 1023 .clock = 68930, 1024 .hdisplay = 1280, 1025 .hsync_start = 1280 + 82, 1026 .hsync_end = 1280 + 82 + 2, 1027 .htotal = 1280 + 82 + 2 + 84, 1028 .vdisplay = 800, 1029 .vsync_start = 800 + 8, 1030 .vsync_end = 800 + 8 + 2, 1031 .vtotal = 800 + 8 + 2 + 6, 1032 }; 1033 1034 static const struct panel_desc auo_g101evn010 = { 1035 .modes = &auo_g101evn010_mode, 1036 .num_modes = 1, 1037 .bpc = 6, 1038 .size = { 1039 .width = 216, 1040 .height = 135, 1041 }, 1042 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1043 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1044 }; 1045 1046 static const struct drm_display_mode auo_g104sn02_mode = { 1047 .clock = 40000, 1048 .hdisplay = 800, 1049 .hsync_start = 800 + 40, 1050 .hsync_end = 800 + 40 + 216, 1051 .htotal = 800 + 40 + 216 + 128, 1052 .vdisplay = 600, 1053 .vsync_start = 600 + 10, 1054 .vsync_end = 600 + 10 + 35, 1055 .vtotal = 600 + 10 + 35 + 2, 1056 }; 1057 1058 static const struct panel_desc auo_g104sn02 = { 1059 .modes = &auo_g104sn02_mode, 1060 .num_modes = 1, 1061 .bpc = 8, 1062 .size = { 1063 .width = 211, 1064 .height = 158, 1065 }, 1066 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1067 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1068 }; 1069 1070 static const struct drm_display_mode auo_g104stn01_mode = { 1071 .clock = 40000, 1072 .hdisplay = 800, 1073 .hsync_start = 800 + 40, 1074 .hsync_end = 800 + 40 + 88, 1075 .htotal = 800 + 40 + 88 + 128, 1076 .vdisplay = 600, 1077 .vsync_start = 600 + 1, 1078 .vsync_end = 600 + 1 + 23, 1079 .vtotal = 600 + 1 + 23 + 4, 1080 }; 1081 1082 static const struct panel_desc auo_g104stn01 = { 1083 .modes = &auo_g104stn01_mode, 1084 .num_modes = 1, 1085 .bpc = 8, 1086 .size = { 1087 .width = 211, 1088 .height = 158, 1089 }, 1090 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1091 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1092 }; 1093 1094 static const struct display_timing auo_g121ean01_timing = { 1095 .pixelclock = { 60000000, 74400000, 90000000 }, 1096 .hactive = { 1280, 1280, 1280 }, 1097 .hfront_porch = { 20, 50, 100 }, 1098 .hback_porch = { 20, 50, 100 }, 1099 .hsync_len = { 30, 100, 200 }, 1100 .vactive = { 800, 800, 800 }, 1101 .vfront_porch = { 2, 10, 25 }, 1102 .vback_porch = { 2, 10, 25 }, 1103 .vsync_len = { 4, 18, 50 }, 1104 }; 1105 1106 static const struct panel_desc auo_g121ean01 = { 1107 .timings = &auo_g121ean01_timing, 1108 .num_timings = 1, 1109 .bpc = 8, 1110 .size = { 1111 .width = 261, 1112 .height = 163, 1113 }, 1114 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1115 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1116 }; 1117 1118 static const struct display_timing auo_g133han01_timings = { 1119 .pixelclock = { 134000000, 141200000, 149000000 }, 1120 .hactive = { 1920, 1920, 1920 }, 1121 .hfront_porch = { 39, 58, 77 }, 1122 .hback_porch = { 59, 88, 117 }, 1123 .hsync_len = { 28, 42, 56 }, 1124 .vactive = { 1080, 1080, 1080 }, 1125 .vfront_porch = { 3, 8, 11 }, 1126 .vback_porch = { 5, 14, 19 }, 1127 .vsync_len = { 4, 14, 19 }, 1128 }; 1129 1130 static const struct panel_desc auo_g133han01 = { 1131 .timings = &auo_g133han01_timings, 1132 .num_timings = 1, 1133 .bpc = 8, 1134 .size = { 1135 .width = 293, 1136 .height = 165, 1137 }, 1138 .delay = { 1139 .prepare = 200, 1140 .enable = 50, 1141 .disable = 50, 1142 .unprepare = 1000, 1143 }, 1144 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1145 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1146 }; 1147 1148 static const struct display_timing auo_g156han04_timings = { 1149 .pixelclock = { 137000000, 141000000, 146000000 }, 1150 .hactive = { 1920, 1920, 1920 }, 1151 .hfront_porch = { 60, 60, 60 }, 1152 .hback_porch = { 90, 92, 111 }, 1153 .hsync_len = { 32, 32, 32 }, 1154 .vactive = { 1080, 1080, 1080 }, 1155 .vfront_porch = { 12, 12, 12 }, 1156 .vback_porch = { 24, 36, 56 }, 1157 .vsync_len = { 8, 8, 8 }, 1158 }; 1159 1160 static const struct panel_desc auo_g156han04 = { 1161 .timings = &auo_g156han04_timings, 1162 .num_timings = 1, 1163 .bpc = 8, 1164 .size = { 1165 .width = 344, 1166 .height = 194, 1167 }, 1168 .delay = { 1169 .prepare = 50, /* T2 */ 1170 .enable = 200, /* T3 */ 1171 .disable = 110, /* T10 */ 1172 .unprepare = 1000, /* T13 */ 1173 }, 1174 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1175 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1176 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1177 }; 1178 1179 static const struct drm_display_mode auo_g156xtn01_mode = { 1180 .clock = 76000, 1181 .hdisplay = 1366, 1182 .hsync_start = 1366 + 33, 1183 .hsync_end = 1366 + 33 + 67, 1184 .htotal = 1560, 1185 .vdisplay = 768, 1186 .vsync_start = 768 + 4, 1187 .vsync_end = 768 + 4 + 4, 1188 .vtotal = 806, 1189 }; 1190 1191 static const struct panel_desc auo_g156xtn01 = { 1192 .modes = &auo_g156xtn01_mode, 1193 .num_modes = 1, 1194 .bpc = 8, 1195 .size = { 1196 .width = 344, 1197 .height = 194, 1198 }, 1199 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1200 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1201 }; 1202 1203 static const struct display_timing auo_g185han01_timings = { 1204 .pixelclock = { 120000000, 144000000, 175000000 }, 1205 .hactive = { 1920, 1920, 1920 }, 1206 .hfront_porch = { 36, 120, 148 }, 1207 .hback_porch = { 24, 88, 108 }, 1208 .hsync_len = { 20, 48, 64 }, 1209 .vactive = { 1080, 1080, 1080 }, 1210 .vfront_porch = { 6, 10, 40 }, 1211 .vback_porch = { 2, 5, 20 }, 1212 .vsync_len = { 2, 5, 20 }, 1213 }; 1214 1215 static const struct panel_desc auo_g185han01 = { 1216 .timings = &auo_g185han01_timings, 1217 .num_timings = 1, 1218 .bpc = 8, 1219 .size = { 1220 .width = 409, 1221 .height = 230, 1222 }, 1223 .delay = { 1224 .prepare = 50, 1225 .enable = 200, 1226 .disable = 110, 1227 .unprepare = 1000, 1228 }, 1229 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1230 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1231 }; 1232 1233 static const struct display_timing auo_g190ean01_timings = { 1234 .pixelclock = { 90000000, 108000000, 135000000 }, 1235 .hactive = { 1280, 1280, 1280 }, 1236 .hfront_porch = { 126, 184, 1266 }, 1237 .hback_porch = { 84, 122, 844 }, 1238 .hsync_len = { 70, 102, 704 }, 1239 .vactive = { 1024, 1024, 1024 }, 1240 .vfront_porch = { 4, 26, 76 }, 1241 .vback_porch = { 2, 8, 25 }, 1242 .vsync_len = { 2, 8, 25 }, 1243 }; 1244 1245 static const struct panel_desc auo_g190ean01 = { 1246 .timings = &auo_g190ean01_timings, 1247 .num_timings = 1, 1248 .bpc = 8, 1249 .size = { 1250 .width = 376, 1251 .height = 301, 1252 }, 1253 .delay = { 1254 .prepare = 50, 1255 .enable = 200, 1256 .disable = 110, 1257 .unprepare = 1000, 1258 }, 1259 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1260 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1261 }; 1262 1263 static const struct display_timing auo_p320hvn03_timings = { 1264 .pixelclock = { 106000000, 148500000, 164000000 }, 1265 .hactive = { 1920, 1920, 1920 }, 1266 .hfront_porch = { 25, 50, 130 }, 1267 .hback_porch = { 25, 50, 130 }, 1268 .hsync_len = { 20, 40, 105 }, 1269 .vactive = { 1080, 1080, 1080 }, 1270 .vfront_porch = { 8, 17, 150 }, 1271 .vback_porch = { 8, 17, 150 }, 1272 .vsync_len = { 4, 11, 100 }, 1273 }; 1274 1275 static const struct panel_desc auo_p320hvn03 = { 1276 .timings = &auo_p320hvn03_timings, 1277 .num_timings = 1, 1278 .bpc = 8, 1279 .size = { 1280 .width = 698, 1281 .height = 393, 1282 }, 1283 .delay = { 1284 .prepare = 1, 1285 .enable = 450, 1286 .unprepare = 500, 1287 }, 1288 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1289 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1290 }; 1291 1292 static const struct drm_display_mode auo_t215hvn01_mode = { 1293 .clock = 148800, 1294 .hdisplay = 1920, 1295 .hsync_start = 1920 + 88, 1296 .hsync_end = 1920 + 88 + 44, 1297 .htotal = 1920 + 88 + 44 + 148, 1298 .vdisplay = 1080, 1299 .vsync_start = 1080 + 4, 1300 .vsync_end = 1080 + 4 + 5, 1301 .vtotal = 1080 + 4 + 5 + 36, 1302 }; 1303 1304 static const struct panel_desc auo_t215hvn01 = { 1305 .modes = &auo_t215hvn01_mode, 1306 .num_modes = 1, 1307 .bpc = 8, 1308 .size = { 1309 .width = 430, 1310 .height = 270, 1311 }, 1312 .delay = { 1313 .disable = 5, 1314 .unprepare = 1000, 1315 }, 1316 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1317 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1318 }; 1319 1320 static const struct drm_display_mode avic_tm070ddh03_mode = { 1321 .clock = 51200, 1322 .hdisplay = 1024, 1323 .hsync_start = 1024 + 160, 1324 .hsync_end = 1024 + 160 + 4, 1325 .htotal = 1024 + 160 + 4 + 156, 1326 .vdisplay = 600, 1327 .vsync_start = 600 + 17, 1328 .vsync_end = 600 + 17 + 1, 1329 .vtotal = 600 + 17 + 1 + 17, 1330 }; 1331 1332 static const struct panel_desc avic_tm070ddh03 = { 1333 .modes = &avic_tm070ddh03_mode, 1334 .num_modes = 1, 1335 .bpc = 8, 1336 .size = { 1337 .width = 154, 1338 .height = 90, 1339 }, 1340 .delay = { 1341 .prepare = 20, 1342 .enable = 200, 1343 .disable = 200, 1344 }, 1345 }; 1346 1347 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1348 .clock = 30000, 1349 .hdisplay = 800, 1350 .hsync_start = 800 + 40, 1351 .hsync_end = 800 + 40 + 48, 1352 .htotal = 800 + 40 + 48 + 40, 1353 .vdisplay = 480, 1354 .vsync_start = 480 + 13, 1355 .vsync_end = 480 + 13 + 3, 1356 .vtotal = 480 + 13 + 3 + 29, 1357 }; 1358 1359 static const struct panel_desc bananapi_s070wv20_ct16 = { 1360 .modes = &bananapi_s070wv20_ct16_mode, 1361 .num_modes = 1, 1362 .bpc = 6, 1363 .size = { 1364 .width = 154, 1365 .height = 86, 1366 }, 1367 }; 1368 1369 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1370 .clock = 78945, 1371 .hdisplay = 1280, 1372 .hsync_start = 1280 + 0, 1373 .hsync_end = 1280 + 0 + 2, 1374 .htotal = 1280 + 62 + 0 + 2, 1375 .vdisplay = 800, 1376 .vsync_start = 800 + 8, 1377 .vsync_end = 800 + 8 + 2, 1378 .vtotal = 800 + 6 + 8 + 2, 1379 }; 1380 1381 static const struct panel_desc boe_bp082wx1_100 = { 1382 .modes = &boe_bp101wx1_100_mode, 1383 .num_modes = 1, 1384 .bpc = 8, 1385 .size = { 1386 .width = 177, 1387 .height = 110, 1388 }, 1389 .delay = { 1390 .enable = 50, 1391 .disable = 50, 1392 }, 1393 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1394 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1395 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1396 }; 1397 1398 static const struct panel_desc boe_bp101wx1_100 = { 1399 .modes = &boe_bp101wx1_100_mode, 1400 .num_modes = 1, 1401 .bpc = 8, 1402 .size = { 1403 .width = 217, 1404 .height = 136, 1405 }, 1406 .delay = { 1407 .enable = 50, 1408 .disable = 50, 1409 }, 1410 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1411 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1412 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1413 }; 1414 1415 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1416 .pixelclock = { 69922000, 71000000, 72293000 }, 1417 .hactive = { 1280, 1280, 1280 }, 1418 .hfront_porch = { 48, 48, 48 }, 1419 .hback_porch = { 80, 80, 80 }, 1420 .hsync_len = { 32, 32, 32 }, 1421 .vactive = { 800, 800, 800 }, 1422 .vfront_porch = { 3, 3, 3 }, 1423 .vback_porch = { 14, 14, 14 }, 1424 .vsync_len = { 6, 6, 6 }, 1425 }; 1426 1427 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1428 .timings = &boe_ev121wxm_n10_1850_timing, 1429 .num_timings = 1, 1430 .bpc = 8, 1431 .size = { 1432 .width = 261, 1433 .height = 163, 1434 }, 1435 .delay = { 1436 .prepare = 9, 1437 .enable = 300, 1438 .unprepare = 300, 1439 .disable = 560, 1440 }, 1441 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1442 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1443 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1444 }; 1445 1446 static const struct drm_display_mode boe_hv070wsa_mode = { 1447 .clock = 42105, 1448 .hdisplay = 1024, 1449 .hsync_start = 1024 + 30, 1450 .hsync_end = 1024 + 30 + 30, 1451 .htotal = 1024 + 30 + 30 + 30, 1452 .vdisplay = 600, 1453 .vsync_start = 600 + 10, 1454 .vsync_end = 600 + 10 + 10, 1455 .vtotal = 600 + 10 + 10 + 10, 1456 }; 1457 1458 static const struct panel_desc boe_hv070wsa = { 1459 .modes = &boe_hv070wsa_mode, 1460 .num_modes = 1, 1461 .bpc = 8, 1462 .size = { 1463 .width = 154, 1464 .height = 90, 1465 }, 1466 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1467 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1468 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1469 }; 1470 1471 static const struct display_timing cct_cmt430b19n00_timing = { 1472 .pixelclock = { 8000000, 9000000, 12000000 }, 1473 .hactive = { 480, 480, 480 }, 1474 .hfront_porch = { 2, 8, 75 }, 1475 .hback_porch = { 3, 43, 43 }, 1476 .hsync_len = { 2, 4, 75 }, 1477 .vactive = { 272, 272, 272 }, 1478 .vfront_porch = { 2, 8, 37 }, 1479 .vback_porch = { 2, 12, 12 }, 1480 .vsync_len = { 2, 4, 37 }, 1481 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1482 }; 1483 1484 static const struct panel_desc cct_cmt430b19n00 = { 1485 .timings = &cct_cmt430b19n00_timing, 1486 .num_timings = 1, 1487 .bpc = 8, 1488 .size = { 1489 .width = 95, 1490 .height = 53, 1491 }, 1492 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1493 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1494 .connector_type = DRM_MODE_CONNECTOR_DPI, 1495 }; 1496 1497 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1498 .clock = 9000, 1499 .hdisplay = 480, 1500 .hsync_start = 480 + 5, 1501 .hsync_end = 480 + 5 + 5, 1502 .htotal = 480 + 5 + 5 + 40, 1503 .vdisplay = 272, 1504 .vsync_start = 272 + 8, 1505 .vsync_end = 272 + 8 + 8, 1506 .vtotal = 272 + 8 + 8 + 8, 1507 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1508 }; 1509 1510 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1511 .modes = &cdtech_s043wq26h_ct7_mode, 1512 .num_modes = 1, 1513 .bpc = 8, 1514 .size = { 1515 .width = 95, 1516 .height = 54, 1517 }, 1518 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1519 }; 1520 1521 /* S070PWS19HP-FC21 2017/04/22 */ 1522 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1523 .clock = 51200, 1524 .hdisplay = 1024, 1525 .hsync_start = 1024 + 160, 1526 .hsync_end = 1024 + 160 + 20, 1527 .htotal = 1024 + 160 + 20 + 140, 1528 .vdisplay = 600, 1529 .vsync_start = 600 + 12, 1530 .vsync_end = 600 + 12 + 3, 1531 .vtotal = 600 + 12 + 3 + 20, 1532 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1533 }; 1534 1535 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1536 .modes = &cdtech_s070pws19hp_fc21_mode, 1537 .num_modes = 1, 1538 .bpc = 6, 1539 .size = { 1540 .width = 154, 1541 .height = 86, 1542 }, 1543 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1544 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1545 .connector_type = DRM_MODE_CONNECTOR_DPI, 1546 }; 1547 1548 /* S070SWV29HG-DC44 2017/09/21 */ 1549 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1550 .clock = 33300, 1551 .hdisplay = 800, 1552 .hsync_start = 800 + 210, 1553 .hsync_end = 800 + 210 + 2, 1554 .htotal = 800 + 210 + 2 + 44, 1555 .vdisplay = 480, 1556 .vsync_start = 480 + 22, 1557 .vsync_end = 480 + 22 + 2, 1558 .vtotal = 480 + 22 + 2 + 21, 1559 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1560 }; 1561 1562 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1563 .modes = &cdtech_s070swv29hg_dc44_mode, 1564 .num_modes = 1, 1565 .bpc = 6, 1566 .size = { 1567 .width = 154, 1568 .height = 86, 1569 }, 1570 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1571 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1572 .connector_type = DRM_MODE_CONNECTOR_DPI, 1573 }; 1574 1575 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1576 .clock = 35000, 1577 .hdisplay = 800, 1578 .hsync_start = 800 + 40, 1579 .hsync_end = 800 + 40 + 40, 1580 .htotal = 800 + 40 + 40 + 48, 1581 .vdisplay = 480, 1582 .vsync_start = 480 + 29, 1583 .vsync_end = 480 + 29 + 13, 1584 .vtotal = 480 + 29 + 13 + 3, 1585 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1586 }; 1587 1588 static const struct panel_desc cdtech_s070wv95_ct16 = { 1589 .modes = &cdtech_s070wv95_ct16_mode, 1590 .num_modes = 1, 1591 .bpc = 8, 1592 .size = { 1593 .width = 154, 1594 .height = 85, 1595 }, 1596 }; 1597 1598 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1599 .pixelclock = { 68900000, 71100000, 73400000 }, 1600 .hactive = { 1280, 1280, 1280 }, 1601 .hfront_porch = { 65, 80, 95 }, 1602 .hback_porch = { 64, 79, 94 }, 1603 .hsync_len = { 1, 1, 1 }, 1604 .vactive = { 800, 800, 800 }, 1605 .vfront_porch = { 7, 11, 14 }, 1606 .vback_porch = { 7, 11, 14 }, 1607 .vsync_len = { 1, 1, 1 }, 1608 .flags = DISPLAY_FLAGS_DE_HIGH, 1609 }; 1610 1611 static const struct panel_desc chefree_ch101olhlwh_002 = { 1612 .timings = &chefree_ch101olhlwh_002_timing, 1613 .num_timings = 1, 1614 .bpc = 8, 1615 .size = { 1616 .width = 217, 1617 .height = 135, 1618 }, 1619 .delay = { 1620 .enable = 200, 1621 .disable = 200, 1622 }, 1623 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1624 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1625 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1626 }; 1627 1628 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1629 .clock = 66770, 1630 .hdisplay = 800, 1631 .hsync_start = 800 + 49, 1632 .hsync_end = 800 + 49 + 33, 1633 .htotal = 800 + 49 + 33 + 17, 1634 .vdisplay = 1280, 1635 .vsync_start = 1280 + 1, 1636 .vsync_end = 1280 + 1 + 7, 1637 .vtotal = 1280 + 1 + 7 + 15, 1638 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1639 }; 1640 1641 static const struct panel_desc chunghwa_claa070wp03xg = { 1642 .modes = &chunghwa_claa070wp03xg_mode, 1643 .num_modes = 1, 1644 .bpc = 6, 1645 .size = { 1646 .width = 94, 1647 .height = 150, 1648 }, 1649 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1650 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1651 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1652 }; 1653 1654 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1655 .clock = 72070, 1656 .hdisplay = 1366, 1657 .hsync_start = 1366 + 58, 1658 .hsync_end = 1366 + 58 + 58, 1659 .htotal = 1366 + 58 + 58 + 58, 1660 .vdisplay = 768, 1661 .vsync_start = 768 + 4, 1662 .vsync_end = 768 + 4 + 4, 1663 .vtotal = 768 + 4 + 4 + 4, 1664 }; 1665 1666 static const struct panel_desc chunghwa_claa101wa01a = { 1667 .modes = &chunghwa_claa101wa01a_mode, 1668 .num_modes = 1, 1669 .bpc = 6, 1670 .size = { 1671 .width = 220, 1672 .height = 120, 1673 }, 1674 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1675 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1676 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1677 }; 1678 1679 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1680 .clock = 69300, 1681 .hdisplay = 1366, 1682 .hsync_start = 1366 + 48, 1683 .hsync_end = 1366 + 48 + 32, 1684 .htotal = 1366 + 48 + 32 + 20, 1685 .vdisplay = 768, 1686 .vsync_start = 768 + 16, 1687 .vsync_end = 768 + 16 + 8, 1688 .vtotal = 768 + 16 + 8 + 16, 1689 }; 1690 1691 static const struct panel_desc chunghwa_claa101wb01 = { 1692 .modes = &chunghwa_claa101wb01_mode, 1693 .num_modes = 1, 1694 .bpc = 6, 1695 .size = { 1696 .width = 223, 1697 .height = 125, 1698 }, 1699 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1700 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1701 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1702 }; 1703 1704 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1705 .pixelclock = { 5000000, 9000000, 12000000 }, 1706 .hactive = { 480, 480, 480 }, 1707 .hfront_porch = { 12, 12, 12 }, 1708 .hback_porch = { 12, 12, 12 }, 1709 .hsync_len = { 21, 21, 21 }, 1710 .vactive = { 272, 272, 272 }, 1711 .vfront_porch = { 4, 4, 4 }, 1712 .vback_porch = { 4, 4, 4 }, 1713 .vsync_len = { 8, 8, 8 }, 1714 }; 1715 1716 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1717 .timings = &dataimage_fg040346dsswbg04_timing, 1718 .num_timings = 1, 1719 .bpc = 8, 1720 .size = { 1721 .width = 95, 1722 .height = 54, 1723 }, 1724 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1725 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1726 .connector_type = DRM_MODE_CONNECTOR_DPI, 1727 }; 1728 1729 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1730 .pixelclock = { 68900000, 71110000, 73400000 }, 1731 .hactive = { 1280, 1280, 1280 }, 1732 .vactive = { 800, 800, 800 }, 1733 .hback_porch = { 100, 100, 100 }, 1734 .hfront_porch = { 100, 100, 100 }, 1735 .vback_porch = { 5, 5, 5 }, 1736 .vfront_porch = { 5, 5, 5 }, 1737 .hsync_len = { 24, 24, 24 }, 1738 .vsync_len = { 3, 3, 3 }, 1739 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1740 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1741 }; 1742 1743 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1744 .timings = &dataimage_fg1001l0dsswmg01_timing, 1745 .num_timings = 1, 1746 .bpc = 8, 1747 .size = { 1748 .width = 217, 1749 .height = 136, 1750 }, 1751 }; 1752 1753 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1754 .clock = 33260, 1755 .hdisplay = 800, 1756 .hsync_start = 800 + 40, 1757 .hsync_end = 800 + 40 + 128, 1758 .htotal = 800 + 40 + 128 + 88, 1759 .vdisplay = 480, 1760 .vsync_start = 480 + 10, 1761 .vsync_end = 480 + 10 + 2, 1762 .vtotal = 480 + 10 + 2 + 33, 1763 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1764 }; 1765 1766 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1767 .modes = &dataimage_scf0700c48ggu18_mode, 1768 .num_modes = 1, 1769 .bpc = 8, 1770 .size = { 1771 .width = 152, 1772 .height = 91, 1773 }, 1774 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1775 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1776 }; 1777 1778 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1779 .pixelclock = { 45000000, 51200000, 57000000 }, 1780 .hactive = { 1024, 1024, 1024 }, 1781 .hfront_porch = { 100, 106, 113 }, 1782 .hback_porch = { 100, 106, 113 }, 1783 .hsync_len = { 100, 108, 114 }, 1784 .vactive = { 600, 600, 600 }, 1785 .vfront_porch = { 8, 11, 15 }, 1786 .vback_porch = { 8, 11, 15 }, 1787 .vsync_len = { 9, 13, 15 }, 1788 .flags = DISPLAY_FLAGS_DE_HIGH, 1789 }; 1790 1791 static const struct panel_desc dlc_dlc0700yzg_1 = { 1792 .timings = &dlc_dlc0700yzg_1_timing, 1793 .num_timings = 1, 1794 .bpc = 6, 1795 .size = { 1796 .width = 154, 1797 .height = 86, 1798 }, 1799 .delay = { 1800 .prepare = 30, 1801 .enable = 200, 1802 .disable = 200, 1803 }, 1804 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1805 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1806 }; 1807 1808 static const struct display_timing dlc_dlc1010gig_timing = { 1809 .pixelclock = { 68900000, 71100000, 73400000 }, 1810 .hactive = { 1280, 1280, 1280 }, 1811 .hfront_porch = { 43, 53, 63 }, 1812 .hback_porch = { 43, 53, 63 }, 1813 .hsync_len = { 44, 54, 64 }, 1814 .vactive = { 800, 800, 800 }, 1815 .vfront_porch = { 5, 8, 11 }, 1816 .vback_porch = { 5, 8, 11 }, 1817 .vsync_len = { 5, 7, 11 }, 1818 .flags = DISPLAY_FLAGS_DE_HIGH, 1819 }; 1820 1821 static const struct panel_desc dlc_dlc1010gig = { 1822 .timings = &dlc_dlc1010gig_timing, 1823 .num_timings = 1, 1824 .bpc = 8, 1825 .size = { 1826 .width = 216, 1827 .height = 135, 1828 }, 1829 .delay = { 1830 .prepare = 60, 1831 .enable = 150, 1832 .disable = 100, 1833 .unprepare = 60, 1834 }, 1835 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1836 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1837 }; 1838 1839 static const struct drm_display_mode edt_et035012dm6_mode = { 1840 .clock = 6500, 1841 .hdisplay = 320, 1842 .hsync_start = 320 + 20, 1843 .hsync_end = 320 + 20 + 30, 1844 .htotal = 320 + 20 + 68, 1845 .vdisplay = 240, 1846 .vsync_start = 240 + 4, 1847 .vsync_end = 240 + 4 + 4, 1848 .vtotal = 240 + 4 + 4 + 14, 1849 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1850 }; 1851 1852 static const struct panel_desc edt_et035012dm6 = { 1853 .modes = &edt_et035012dm6_mode, 1854 .num_modes = 1, 1855 .bpc = 8, 1856 .size = { 1857 .width = 70, 1858 .height = 52, 1859 }, 1860 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1861 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1862 }; 1863 1864 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1865 .clock = 6520, 1866 .hdisplay = 320, 1867 .hsync_start = 320 + 20, 1868 .hsync_end = 320 + 20 + 68, 1869 .htotal = 320 + 20 + 68, 1870 .vdisplay = 240, 1871 .vsync_start = 240 + 4, 1872 .vsync_end = 240 + 4 + 18, 1873 .vtotal = 240 + 4 + 18, 1874 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1875 }; 1876 1877 static const struct panel_desc edt_etm0350g0dh6 = { 1878 .modes = &edt_etm0350g0dh6_mode, 1879 .num_modes = 1, 1880 .bpc = 6, 1881 .size = { 1882 .width = 70, 1883 .height = 53, 1884 }, 1885 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1886 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1887 .connector_type = DRM_MODE_CONNECTOR_DPI, 1888 }; 1889 1890 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1891 .clock = 10870, 1892 .hdisplay = 480, 1893 .hsync_start = 480 + 8, 1894 .hsync_end = 480 + 8 + 4, 1895 .htotal = 480 + 8 + 4 + 41, 1896 1897 /* 1898 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1899 * fb_align 1900 */ 1901 1902 .vdisplay = 288, 1903 .vsync_start = 288 + 2, 1904 .vsync_end = 288 + 2 + 4, 1905 .vtotal = 288 + 2 + 4 + 10, 1906 }; 1907 1908 static const struct panel_desc edt_etm043080dh6gp = { 1909 .modes = &edt_etm043080dh6gp_mode, 1910 .num_modes = 1, 1911 .bpc = 8, 1912 .size = { 1913 .width = 100, 1914 .height = 65, 1915 }, 1916 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1917 .connector_type = DRM_MODE_CONNECTOR_DPI, 1918 }; 1919 1920 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1921 .clock = 9000, 1922 .hdisplay = 480, 1923 .hsync_start = 480 + 2, 1924 .hsync_end = 480 + 2 + 41, 1925 .htotal = 480 + 2 + 41 + 2, 1926 .vdisplay = 272, 1927 .vsync_start = 272 + 2, 1928 .vsync_end = 272 + 2 + 10, 1929 .vtotal = 272 + 2 + 10 + 2, 1930 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1931 }; 1932 1933 static const struct panel_desc edt_etm0430g0dh6 = { 1934 .modes = &edt_etm0430g0dh6_mode, 1935 .num_modes = 1, 1936 .bpc = 6, 1937 .size = { 1938 .width = 95, 1939 .height = 54, 1940 }, 1941 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1942 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1943 .connector_type = DRM_MODE_CONNECTOR_DPI, 1944 }; 1945 1946 static const struct drm_display_mode edt_et057090dhu_mode = { 1947 .clock = 25175, 1948 .hdisplay = 640, 1949 .hsync_start = 640 + 16, 1950 .hsync_end = 640 + 16 + 30, 1951 .htotal = 640 + 16 + 30 + 114, 1952 .vdisplay = 480, 1953 .vsync_start = 480 + 10, 1954 .vsync_end = 480 + 10 + 3, 1955 .vtotal = 480 + 10 + 3 + 32, 1956 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1957 }; 1958 1959 static const struct panel_desc edt_et057090dhu = { 1960 .modes = &edt_et057090dhu_mode, 1961 .num_modes = 1, 1962 .bpc = 6, 1963 .size = { 1964 .width = 115, 1965 .height = 86, 1966 }, 1967 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1968 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1969 .connector_type = DRM_MODE_CONNECTOR_DPI, 1970 }; 1971 1972 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1973 .clock = 33260, 1974 .hdisplay = 800, 1975 .hsync_start = 800 + 40, 1976 .hsync_end = 800 + 40 + 128, 1977 .htotal = 800 + 40 + 128 + 88, 1978 .vdisplay = 480, 1979 .vsync_start = 480 + 10, 1980 .vsync_end = 480 + 10 + 2, 1981 .vtotal = 480 + 10 + 2 + 33, 1982 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1983 }; 1984 1985 static const struct panel_desc edt_etm0700g0dh6 = { 1986 .modes = &edt_etm0700g0dh6_mode, 1987 .num_modes = 1, 1988 .bpc = 6, 1989 .size = { 1990 .width = 152, 1991 .height = 91, 1992 }, 1993 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1994 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1995 .connector_type = DRM_MODE_CONNECTOR_DPI, 1996 }; 1997 1998 static const struct panel_desc edt_etm0700g0bdh6 = { 1999 .modes = &edt_etm0700g0dh6_mode, 2000 .num_modes = 1, 2001 .bpc = 6, 2002 .size = { 2003 .width = 152, 2004 .height = 91, 2005 }, 2006 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2007 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2008 .connector_type = DRM_MODE_CONNECTOR_DPI, 2009 }; 2010 2011 static const struct display_timing edt_etml0700y5dha_timing = { 2012 .pixelclock = { 40800000, 51200000, 67200000 }, 2013 .hactive = { 1024, 1024, 1024 }, 2014 .hfront_porch = { 30, 106, 125 }, 2015 .hback_porch = { 30, 106, 125 }, 2016 .hsync_len = { 30, 108, 126 }, 2017 .vactive = { 600, 600, 600 }, 2018 .vfront_porch = { 3, 12, 67}, 2019 .vback_porch = { 3, 12, 67 }, 2020 .vsync_len = { 4, 11, 66 }, 2021 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2022 DISPLAY_FLAGS_DE_HIGH, 2023 }; 2024 2025 static const struct panel_desc edt_etml0700y5dha = { 2026 .timings = &edt_etml0700y5dha_timing, 2027 .num_timings = 1, 2028 .bpc = 8, 2029 .size = { 2030 .width = 155, 2031 .height = 86, 2032 }, 2033 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2034 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2035 }; 2036 2037 static const struct display_timing edt_etml1010g3dra_timing = { 2038 .pixelclock = { 66300000, 72400000, 78900000 }, 2039 .hactive = { 1280, 1280, 1280 }, 2040 .hfront_porch = { 12, 72, 132 }, 2041 .hback_porch = { 86, 86, 86 }, 2042 .hsync_len = { 2, 2, 2 }, 2043 .vactive = { 800, 800, 800 }, 2044 .vfront_porch = { 1, 15, 49 }, 2045 .vback_porch = { 21, 21, 21 }, 2046 .vsync_len = { 2, 2, 2 }, 2047 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2048 DISPLAY_FLAGS_DE_HIGH, 2049 }; 2050 2051 static const struct panel_desc edt_etml1010g3dra = { 2052 .timings = &edt_etml1010g3dra_timing, 2053 .num_timings = 1, 2054 .bpc = 8, 2055 .size = { 2056 .width = 216, 2057 .height = 135, 2058 }, 2059 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2060 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2061 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2062 }; 2063 2064 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2065 .clock = 25175, 2066 .hdisplay = 640, 2067 .hsync_start = 640, 2068 .hsync_end = 640 + 16, 2069 .htotal = 640 + 16 + 30 + 114, 2070 .vdisplay = 480, 2071 .vsync_start = 480 + 10, 2072 .vsync_end = 480 + 10 + 3, 2073 .vtotal = 480 + 10 + 3 + 35, 2074 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2075 }; 2076 2077 static const struct panel_desc edt_etmv570g2dhu = { 2078 .modes = &edt_etmv570g2dhu_mode, 2079 .num_modes = 1, 2080 .bpc = 6, 2081 .size = { 2082 .width = 115, 2083 .height = 86, 2084 }, 2085 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2086 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2087 .connector_type = DRM_MODE_CONNECTOR_DPI, 2088 }; 2089 2090 static const struct display_timing eink_vb3300_kca_timing = { 2091 .pixelclock = { 40000000, 40000000, 40000000 }, 2092 .hactive = { 334, 334, 334 }, 2093 .hfront_porch = { 1, 1, 1 }, 2094 .hback_porch = { 1, 1, 1 }, 2095 .hsync_len = { 1, 1, 1 }, 2096 .vactive = { 1405, 1405, 1405 }, 2097 .vfront_porch = { 1, 1, 1 }, 2098 .vback_porch = { 1, 1, 1 }, 2099 .vsync_len = { 1, 1, 1 }, 2100 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2101 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2102 }; 2103 2104 static const struct panel_desc eink_vb3300_kca = { 2105 .timings = &eink_vb3300_kca_timing, 2106 .num_timings = 1, 2107 .bpc = 6, 2108 .size = { 2109 .width = 157, 2110 .height = 209, 2111 }, 2112 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2113 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2114 .connector_type = DRM_MODE_CONNECTOR_DPI, 2115 }; 2116 2117 static const struct display_timing evervision_vgg644804_timing = { 2118 .pixelclock = { 25175000, 25175000, 25175000 }, 2119 .hactive = { 640, 640, 640 }, 2120 .hfront_porch = { 16, 16, 16 }, 2121 .hback_porch = { 82, 114, 170 }, 2122 .hsync_len = { 5, 30, 30 }, 2123 .vactive = { 480, 480, 480 }, 2124 .vfront_porch = { 10, 10, 10 }, 2125 .vback_porch = { 30, 32, 34 }, 2126 .vsync_len = { 1, 3, 5 }, 2127 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2128 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2129 DISPLAY_FLAGS_SYNC_POSEDGE, 2130 }; 2131 2132 static const struct panel_desc evervision_vgg644804 = { 2133 .timings = &evervision_vgg644804_timing, 2134 .num_timings = 1, 2135 .bpc = 8, 2136 .size = { 2137 .width = 115, 2138 .height = 86, 2139 }, 2140 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2141 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2142 }; 2143 2144 static const struct display_timing evervision_vgg804821_timing = { 2145 .pixelclock = { 27600000, 33300000, 50000000 }, 2146 .hactive = { 800, 800, 800 }, 2147 .hfront_porch = { 40, 66, 70 }, 2148 .hback_porch = { 40, 67, 70 }, 2149 .hsync_len = { 40, 67, 70 }, 2150 .vactive = { 480, 480, 480 }, 2151 .vfront_porch = { 6, 10, 10 }, 2152 .vback_porch = { 7, 11, 11 }, 2153 .vsync_len = { 7, 11, 11 }, 2154 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2155 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2156 DISPLAY_FLAGS_SYNC_NEGEDGE, 2157 }; 2158 2159 static const struct panel_desc evervision_vgg804821 = { 2160 .timings = &evervision_vgg804821_timing, 2161 .num_timings = 1, 2162 .bpc = 8, 2163 .size = { 2164 .width = 108, 2165 .height = 64, 2166 }, 2167 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2168 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2169 }; 2170 2171 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2172 .clock = 32260, 2173 .hdisplay = 800, 2174 .hsync_start = 800 + 168, 2175 .hsync_end = 800 + 168 + 64, 2176 .htotal = 800 + 168 + 64 + 88, 2177 .vdisplay = 480, 2178 .vsync_start = 480 + 37, 2179 .vsync_end = 480 + 37 + 2, 2180 .vtotal = 480 + 37 + 2 + 8, 2181 }; 2182 2183 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2184 .modes = &foxlink_fl500wvr00_a0t_mode, 2185 .num_modes = 1, 2186 .bpc = 8, 2187 .size = { 2188 .width = 108, 2189 .height = 65, 2190 }, 2191 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2192 }; 2193 2194 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2195 { /* 60 Hz */ 2196 .clock = 6000, 2197 .hdisplay = 320, 2198 .hsync_start = 320 + 44, 2199 .hsync_end = 320 + 44 + 16, 2200 .htotal = 320 + 44 + 16 + 20, 2201 .vdisplay = 240, 2202 .vsync_start = 240 + 2, 2203 .vsync_end = 240 + 2 + 6, 2204 .vtotal = 240 + 2 + 6 + 2, 2205 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2206 }, 2207 { /* 50 Hz */ 2208 .clock = 5400, 2209 .hdisplay = 320, 2210 .hsync_start = 320 + 56, 2211 .hsync_end = 320 + 56 + 16, 2212 .htotal = 320 + 56 + 16 + 40, 2213 .vdisplay = 240, 2214 .vsync_start = 240 + 2, 2215 .vsync_end = 240 + 2 + 6, 2216 .vtotal = 240 + 2 + 6 + 2, 2217 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2218 }, 2219 }; 2220 2221 static const struct panel_desc frida_frd350h54004 = { 2222 .modes = frida_frd350h54004_modes, 2223 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2224 .bpc = 8, 2225 .size = { 2226 .width = 77, 2227 .height = 64, 2228 }, 2229 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2230 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2231 .connector_type = DRM_MODE_CONNECTOR_DPI, 2232 }; 2233 2234 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2235 .clock = 67185, 2236 .hdisplay = 800, 2237 .hsync_start = 800 + 20, 2238 .hsync_end = 800 + 20 + 24, 2239 .htotal = 800 + 20 + 24 + 20, 2240 .vdisplay = 1280, 2241 .vsync_start = 1280 + 4, 2242 .vsync_end = 1280 + 4 + 8, 2243 .vtotal = 1280 + 4 + 8 + 4, 2244 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2245 }; 2246 2247 static const struct panel_desc friendlyarm_hd702e = { 2248 .modes = &friendlyarm_hd702e_mode, 2249 .num_modes = 1, 2250 .size = { 2251 .width = 94, 2252 .height = 151, 2253 }, 2254 }; 2255 2256 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2257 .clock = 9000, 2258 .hdisplay = 480, 2259 .hsync_start = 480 + 5, 2260 .hsync_end = 480 + 5 + 1, 2261 .htotal = 480 + 5 + 1 + 40, 2262 .vdisplay = 272, 2263 .vsync_start = 272 + 8, 2264 .vsync_end = 272 + 8 + 1, 2265 .vtotal = 272 + 8 + 1 + 8, 2266 }; 2267 2268 static const struct panel_desc giantplus_gpg482739qs5 = { 2269 .modes = &giantplus_gpg482739qs5_mode, 2270 .num_modes = 1, 2271 .bpc = 8, 2272 .size = { 2273 .width = 95, 2274 .height = 54, 2275 }, 2276 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2277 }; 2278 2279 static const struct display_timing giantplus_gpm940b0_timing = { 2280 .pixelclock = { 13500000, 27000000, 27500000 }, 2281 .hactive = { 320, 320, 320 }, 2282 .hfront_porch = { 14, 686, 718 }, 2283 .hback_porch = { 50, 70, 255 }, 2284 .hsync_len = { 1, 1, 1 }, 2285 .vactive = { 240, 240, 240 }, 2286 .vfront_porch = { 1, 1, 179 }, 2287 .vback_porch = { 1, 21, 31 }, 2288 .vsync_len = { 1, 1, 6 }, 2289 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2290 }; 2291 2292 static const struct panel_desc giantplus_gpm940b0 = { 2293 .timings = &giantplus_gpm940b0_timing, 2294 .num_timings = 1, 2295 .bpc = 8, 2296 .size = { 2297 .width = 60, 2298 .height = 45, 2299 }, 2300 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2301 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2302 }; 2303 2304 static const struct display_timing hannstar_hsd070pww1_timing = { 2305 .pixelclock = { 64300000, 71100000, 82000000 }, 2306 .hactive = { 1280, 1280, 1280 }, 2307 .hfront_porch = { 1, 1, 10 }, 2308 .hback_porch = { 1, 1, 10 }, 2309 /* 2310 * According to the data sheet, the minimum horizontal blanking interval 2311 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2312 * minimum working horizontal blanking interval to be 60 clocks. 2313 */ 2314 .hsync_len = { 58, 158, 661 }, 2315 .vactive = { 800, 800, 800 }, 2316 .vfront_porch = { 1, 1, 10 }, 2317 .vback_porch = { 1, 1, 10 }, 2318 .vsync_len = { 1, 21, 203 }, 2319 .flags = DISPLAY_FLAGS_DE_HIGH, 2320 }; 2321 2322 static const struct panel_desc hannstar_hsd070pww1 = { 2323 .timings = &hannstar_hsd070pww1_timing, 2324 .num_timings = 1, 2325 .bpc = 6, 2326 .size = { 2327 .width = 151, 2328 .height = 94, 2329 }, 2330 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2331 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2332 }; 2333 2334 static const struct display_timing hannstar_hsd100pxn1_timing = { 2335 .pixelclock = { 55000000, 65000000, 75000000 }, 2336 .hactive = { 1024, 1024, 1024 }, 2337 .hfront_porch = { 40, 40, 40 }, 2338 .hback_porch = { 220, 220, 220 }, 2339 .hsync_len = { 20, 60, 100 }, 2340 .vactive = { 768, 768, 768 }, 2341 .vfront_porch = { 7, 7, 7 }, 2342 .vback_porch = { 21, 21, 21 }, 2343 .vsync_len = { 10, 10, 10 }, 2344 .flags = DISPLAY_FLAGS_DE_HIGH, 2345 }; 2346 2347 static const struct panel_desc hannstar_hsd100pxn1 = { 2348 .timings = &hannstar_hsd100pxn1_timing, 2349 .num_timings = 1, 2350 .bpc = 6, 2351 .size = { 2352 .width = 203, 2353 .height = 152, 2354 }, 2355 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2356 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2357 }; 2358 2359 static const struct display_timing hannstar_hsd101pww2_timing = { 2360 .pixelclock = { 64300000, 71100000, 82000000 }, 2361 .hactive = { 1280, 1280, 1280 }, 2362 .hfront_porch = { 1, 1, 10 }, 2363 .hback_porch = { 1, 1, 10 }, 2364 .hsync_len = { 58, 158, 661 }, 2365 .vactive = { 800, 800, 800 }, 2366 .vfront_porch = { 1, 1, 10 }, 2367 .vback_porch = { 1, 1, 10 }, 2368 .vsync_len = { 1, 21, 203 }, 2369 .flags = DISPLAY_FLAGS_DE_HIGH, 2370 }; 2371 2372 static const struct panel_desc hannstar_hsd101pww2 = { 2373 .timings = &hannstar_hsd101pww2_timing, 2374 .num_timings = 1, 2375 .bpc = 8, 2376 .size = { 2377 .width = 217, 2378 .height = 136, 2379 }, 2380 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2381 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2382 }; 2383 2384 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2385 .clock = 33333, 2386 .hdisplay = 800, 2387 .hsync_start = 800 + 85, 2388 .hsync_end = 800 + 85 + 86, 2389 .htotal = 800 + 85 + 86 + 85, 2390 .vdisplay = 480, 2391 .vsync_start = 480 + 16, 2392 .vsync_end = 480 + 16 + 13, 2393 .vtotal = 480 + 16 + 13 + 16, 2394 }; 2395 2396 static const struct panel_desc hitachi_tx23d38vm0caa = { 2397 .modes = &hitachi_tx23d38vm0caa_mode, 2398 .num_modes = 1, 2399 .bpc = 6, 2400 .size = { 2401 .width = 195, 2402 .height = 117, 2403 }, 2404 .delay = { 2405 .enable = 160, 2406 .disable = 160, 2407 }, 2408 }; 2409 2410 static const struct drm_display_mode innolux_at043tn24_mode = { 2411 .clock = 9000, 2412 .hdisplay = 480, 2413 .hsync_start = 480 + 2, 2414 .hsync_end = 480 + 2 + 41, 2415 .htotal = 480 + 2 + 41 + 2, 2416 .vdisplay = 272, 2417 .vsync_start = 272 + 2, 2418 .vsync_end = 272 + 2 + 10, 2419 .vtotal = 272 + 2 + 10 + 2, 2420 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2421 }; 2422 2423 static const struct panel_desc innolux_at043tn24 = { 2424 .modes = &innolux_at043tn24_mode, 2425 .num_modes = 1, 2426 .bpc = 8, 2427 .size = { 2428 .width = 95, 2429 .height = 54, 2430 }, 2431 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2432 .connector_type = DRM_MODE_CONNECTOR_DPI, 2433 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2434 }; 2435 2436 static const struct drm_display_mode innolux_at070tn92_mode = { 2437 .clock = 33333, 2438 .hdisplay = 800, 2439 .hsync_start = 800 + 210, 2440 .hsync_end = 800 + 210 + 20, 2441 .htotal = 800 + 210 + 20 + 46, 2442 .vdisplay = 480, 2443 .vsync_start = 480 + 22, 2444 .vsync_end = 480 + 22 + 10, 2445 .vtotal = 480 + 22 + 23 + 10, 2446 }; 2447 2448 static const struct panel_desc innolux_at070tn92 = { 2449 .modes = &innolux_at070tn92_mode, 2450 .num_modes = 1, 2451 .size = { 2452 .width = 154, 2453 .height = 86, 2454 }, 2455 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2456 }; 2457 2458 static const struct display_timing innolux_g070ace_l01_timing = { 2459 .pixelclock = { 25200000, 35000000, 35700000 }, 2460 .hactive = { 800, 800, 800 }, 2461 .hfront_porch = { 30, 32, 87 }, 2462 .hback_porch = { 30, 32, 87 }, 2463 .hsync_len = { 1, 1, 1 }, 2464 .vactive = { 480, 480, 480 }, 2465 .vfront_porch = { 3, 3, 3 }, 2466 .vback_porch = { 13, 13, 13 }, 2467 .vsync_len = { 1, 1, 4 }, 2468 .flags = DISPLAY_FLAGS_DE_HIGH, 2469 }; 2470 2471 static const struct panel_desc innolux_g070ace_l01 = { 2472 .timings = &innolux_g070ace_l01_timing, 2473 .num_timings = 1, 2474 .bpc = 8, 2475 .size = { 2476 .width = 152, 2477 .height = 91, 2478 }, 2479 .delay = { 2480 .prepare = 10, 2481 .enable = 50, 2482 .disable = 50, 2483 .unprepare = 500, 2484 }, 2485 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2486 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2487 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2488 }; 2489 2490 static const struct display_timing innolux_g070y2_l01_timing = { 2491 .pixelclock = { 28000000, 29500000, 32000000 }, 2492 .hactive = { 800, 800, 800 }, 2493 .hfront_porch = { 61, 91, 141 }, 2494 .hback_porch = { 60, 90, 140 }, 2495 .hsync_len = { 12, 12, 12 }, 2496 .vactive = { 480, 480, 480 }, 2497 .vfront_porch = { 4, 9, 30 }, 2498 .vback_porch = { 4, 8, 28 }, 2499 .vsync_len = { 2, 2, 2 }, 2500 .flags = DISPLAY_FLAGS_DE_HIGH, 2501 }; 2502 2503 static const struct panel_desc innolux_g070y2_l01 = { 2504 .timings = &innolux_g070y2_l01_timing, 2505 .num_timings = 1, 2506 .bpc = 8, 2507 .size = { 2508 .width = 152, 2509 .height = 91, 2510 }, 2511 .delay = { 2512 .prepare = 10, 2513 .enable = 100, 2514 .disable = 100, 2515 .unprepare = 800, 2516 }, 2517 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2518 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2519 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2520 }; 2521 2522 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2523 .clock = 33333, 2524 .hdisplay = 800, 2525 .hsync_start = 800 + 210, 2526 .hsync_end = 800 + 210 + 20, 2527 .htotal = 800 + 210 + 20 + 46, 2528 .vdisplay = 480, 2529 .vsync_start = 480 + 22, 2530 .vsync_end = 480 + 22 + 10, 2531 .vtotal = 480 + 22 + 23 + 10, 2532 }; 2533 2534 static const struct panel_desc innolux_g070y2_t02 = { 2535 .modes = &innolux_g070y2_t02_mode, 2536 .num_modes = 1, 2537 .bpc = 8, 2538 .size = { 2539 .width = 152, 2540 .height = 92, 2541 }, 2542 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2543 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2544 .connector_type = DRM_MODE_CONNECTOR_DPI, 2545 }; 2546 2547 static const struct display_timing innolux_g101ice_l01_timing = { 2548 .pixelclock = { 60400000, 71100000, 74700000 }, 2549 .hactive = { 1280, 1280, 1280 }, 2550 .hfront_porch = { 30, 60, 70 }, 2551 .hback_porch = { 30, 60, 70 }, 2552 .hsync_len = { 22, 40, 60 }, 2553 .vactive = { 800, 800, 800 }, 2554 .vfront_porch = { 3, 8, 14 }, 2555 .vback_porch = { 3, 8, 14 }, 2556 .vsync_len = { 4, 7, 12 }, 2557 .flags = DISPLAY_FLAGS_DE_HIGH, 2558 }; 2559 2560 static const struct panel_desc innolux_g101ice_l01 = { 2561 .timings = &innolux_g101ice_l01_timing, 2562 .num_timings = 1, 2563 .bpc = 8, 2564 .size = { 2565 .width = 217, 2566 .height = 135, 2567 }, 2568 .delay = { 2569 .enable = 200, 2570 .disable = 200, 2571 }, 2572 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2573 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2574 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2575 }; 2576 2577 static const struct display_timing innolux_g121i1_l01_timing = { 2578 .pixelclock = { 67450000, 71000000, 74550000 }, 2579 .hactive = { 1280, 1280, 1280 }, 2580 .hfront_porch = { 40, 80, 160 }, 2581 .hback_porch = { 39, 79, 159 }, 2582 .hsync_len = { 1, 1, 1 }, 2583 .vactive = { 800, 800, 800 }, 2584 .vfront_porch = { 5, 11, 100 }, 2585 .vback_porch = { 4, 11, 99 }, 2586 .vsync_len = { 1, 1, 1 }, 2587 }; 2588 2589 static const struct panel_desc innolux_g121i1_l01 = { 2590 .timings = &innolux_g121i1_l01_timing, 2591 .num_timings = 1, 2592 .bpc = 6, 2593 .size = { 2594 .width = 261, 2595 .height = 163, 2596 }, 2597 .delay = { 2598 .enable = 200, 2599 .disable = 20, 2600 }, 2601 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2602 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2603 }; 2604 2605 static const struct display_timing innolux_g121x1_l03_timings = { 2606 .pixelclock = { 57500000, 64900000, 74400000 }, 2607 .hactive = { 1024, 1024, 1024 }, 2608 .hfront_porch = { 90, 140, 190 }, 2609 .hback_porch = { 90, 140, 190 }, 2610 .hsync_len = { 36, 40, 60 }, 2611 .vactive = { 768, 768, 768 }, 2612 .vfront_porch = { 2, 15, 30 }, 2613 .vback_porch = { 2, 15, 30 }, 2614 .vsync_len = { 2, 8, 20 }, 2615 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2616 }; 2617 2618 static const struct panel_desc innolux_g121x1_l03 = { 2619 .timings = &innolux_g121x1_l03_timings, 2620 .num_timings = 1, 2621 .bpc = 6, 2622 .size = { 2623 .width = 246, 2624 .height = 185, 2625 }, 2626 .delay = { 2627 .enable = 200, 2628 .unprepare = 200, 2629 .disable = 400, 2630 }, 2631 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2632 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2633 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2634 }; 2635 2636 static const struct panel_desc innolux_g121xce_l01 = { 2637 .timings = &innolux_g121x1_l03_timings, 2638 .num_timings = 1, 2639 .bpc = 8, 2640 .size = { 2641 .width = 246, 2642 .height = 185, 2643 }, 2644 .delay = { 2645 .enable = 200, 2646 .unprepare = 200, 2647 .disable = 400, 2648 }, 2649 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2650 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2651 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2652 }; 2653 2654 static const struct display_timing innolux_g156hce_l01_timings = { 2655 .pixelclock = { 120000000, 141860000, 150000000 }, 2656 .hactive = { 1920, 1920, 1920 }, 2657 .hfront_porch = { 80, 90, 100 }, 2658 .hback_porch = { 80, 90, 100 }, 2659 .hsync_len = { 20, 30, 30 }, 2660 .vactive = { 1080, 1080, 1080 }, 2661 .vfront_porch = { 3, 10, 20 }, 2662 .vback_porch = { 3, 10, 20 }, 2663 .vsync_len = { 4, 10, 10 }, 2664 }; 2665 2666 static const struct panel_desc innolux_g156hce_l01 = { 2667 .timings = &innolux_g156hce_l01_timings, 2668 .num_timings = 1, 2669 .bpc = 8, 2670 .size = { 2671 .width = 344, 2672 .height = 194, 2673 }, 2674 .delay = { 2675 .prepare = 1, /* T1+T2 */ 2676 .enable = 450, /* T5 */ 2677 .disable = 200, /* T6 */ 2678 .unprepare = 10, /* T3+T7 */ 2679 }, 2680 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2681 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2682 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2683 }; 2684 2685 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2686 .clock = 69300, 2687 .hdisplay = 1366, 2688 .hsync_start = 1366 + 16, 2689 .hsync_end = 1366 + 16 + 34, 2690 .htotal = 1366 + 16 + 34 + 50, 2691 .vdisplay = 768, 2692 .vsync_start = 768 + 2, 2693 .vsync_end = 768 + 2 + 6, 2694 .vtotal = 768 + 2 + 6 + 12, 2695 }; 2696 2697 static const struct panel_desc innolux_n156bge_l21 = { 2698 .modes = &innolux_n156bge_l21_mode, 2699 .num_modes = 1, 2700 .bpc = 6, 2701 .size = { 2702 .width = 344, 2703 .height = 193, 2704 }, 2705 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2706 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2707 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2708 }; 2709 2710 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2711 .clock = 51501, 2712 .hdisplay = 1024, 2713 .hsync_start = 1024 + 128, 2714 .hsync_end = 1024 + 128 + 64, 2715 .htotal = 1024 + 128 + 64 + 128, 2716 .vdisplay = 600, 2717 .vsync_start = 600 + 16, 2718 .vsync_end = 600 + 16 + 4, 2719 .vtotal = 600 + 16 + 4 + 16, 2720 }; 2721 2722 static const struct panel_desc innolux_zj070na_01p = { 2723 .modes = &innolux_zj070na_01p_mode, 2724 .num_modes = 1, 2725 .bpc = 6, 2726 .size = { 2727 .width = 154, 2728 .height = 90, 2729 }, 2730 }; 2731 2732 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2733 .pixelclock = { 5580000, 5850000, 6200000 }, 2734 .hactive = { 320, 320, 320 }, 2735 .hfront_porch = { 30, 30, 30 }, 2736 .hback_porch = { 30, 30, 30 }, 2737 .hsync_len = { 1, 5, 17 }, 2738 .vactive = { 240, 240, 240 }, 2739 .vfront_porch = { 6, 6, 6 }, 2740 .vback_porch = { 5, 5, 5 }, 2741 .vsync_len = { 1, 2, 11 }, 2742 .flags = DISPLAY_FLAGS_DE_HIGH, 2743 }; 2744 2745 static const struct panel_desc koe_tx14d24vm1bpa = { 2746 .timings = &koe_tx14d24vm1bpa_timing, 2747 .num_timings = 1, 2748 .bpc = 6, 2749 .size = { 2750 .width = 115, 2751 .height = 86, 2752 }, 2753 }; 2754 2755 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2756 .pixelclock = { 151820000, 156720000, 159780000 }, 2757 .hactive = { 1920, 1920, 1920 }, 2758 .hfront_porch = { 105, 130, 142 }, 2759 .hback_porch = { 45, 70, 82 }, 2760 .hsync_len = { 30, 30, 30 }, 2761 .vactive = { 1200, 1200, 1200}, 2762 .vfront_porch = { 3, 5, 10 }, 2763 .vback_porch = { 2, 5, 10 }, 2764 .vsync_len = { 5, 5, 5 }, 2765 .flags = DISPLAY_FLAGS_DE_HIGH, 2766 }; 2767 2768 static const struct panel_desc koe_tx26d202vm0bwa = { 2769 .timings = &koe_tx26d202vm0bwa_timing, 2770 .num_timings = 1, 2771 .bpc = 8, 2772 .size = { 2773 .width = 217, 2774 .height = 136, 2775 }, 2776 .delay = { 2777 .prepare = 1000, 2778 .enable = 1000, 2779 .unprepare = 1000, 2780 .disable = 1000, 2781 }, 2782 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2783 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2784 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2785 }; 2786 2787 static const struct display_timing koe_tx31d200vm0baa_timing = { 2788 .pixelclock = { 39600000, 43200000, 48000000 }, 2789 .hactive = { 1280, 1280, 1280 }, 2790 .hfront_porch = { 16, 36, 56 }, 2791 .hback_porch = { 16, 36, 56 }, 2792 .hsync_len = { 8, 8, 8 }, 2793 .vactive = { 480, 480, 480 }, 2794 .vfront_porch = { 6, 21, 33 }, 2795 .vback_porch = { 6, 21, 33 }, 2796 .vsync_len = { 8, 8, 8 }, 2797 .flags = DISPLAY_FLAGS_DE_HIGH, 2798 }; 2799 2800 static const struct panel_desc koe_tx31d200vm0baa = { 2801 .timings = &koe_tx31d200vm0baa_timing, 2802 .num_timings = 1, 2803 .bpc = 6, 2804 .size = { 2805 .width = 292, 2806 .height = 109, 2807 }, 2808 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2809 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2810 }; 2811 2812 static const struct display_timing kyo_tcg121xglp_timing = { 2813 .pixelclock = { 52000000, 65000000, 71000000 }, 2814 .hactive = { 1024, 1024, 1024 }, 2815 .hfront_porch = { 2, 2, 2 }, 2816 .hback_porch = { 2, 2, 2 }, 2817 .hsync_len = { 86, 124, 244 }, 2818 .vactive = { 768, 768, 768 }, 2819 .vfront_porch = { 2, 2, 2 }, 2820 .vback_porch = { 2, 2, 2 }, 2821 .vsync_len = { 6, 34, 73 }, 2822 .flags = DISPLAY_FLAGS_DE_HIGH, 2823 }; 2824 2825 static const struct panel_desc kyo_tcg121xglp = { 2826 .timings = &kyo_tcg121xglp_timing, 2827 .num_timings = 1, 2828 .bpc = 8, 2829 .size = { 2830 .width = 246, 2831 .height = 184, 2832 }, 2833 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2834 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2835 }; 2836 2837 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2838 .clock = 7000, 2839 .hdisplay = 320, 2840 .hsync_start = 320 + 20, 2841 .hsync_end = 320 + 20 + 30, 2842 .htotal = 320 + 20 + 30 + 38, 2843 .vdisplay = 240, 2844 .vsync_start = 240 + 4, 2845 .vsync_end = 240 + 4 + 3, 2846 .vtotal = 240 + 4 + 3 + 15, 2847 }; 2848 2849 static const struct panel_desc lemaker_bl035_rgb_002 = { 2850 .modes = &lemaker_bl035_rgb_002_mode, 2851 .num_modes = 1, 2852 .size = { 2853 .width = 70, 2854 .height = 52, 2855 }, 2856 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2857 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2858 }; 2859 2860 static const struct display_timing lg_lb070wv8_timing = { 2861 .pixelclock = { 31950000, 33260000, 34600000 }, 2862 .hactive = { 800, 800, 800 }, 2863 .hfront_porch = { 88, 88, 88 }, 2864 .hback_porch = { 88, 88, 88 }, 2865 .hsync_len = { 80, 80, 80 }, 2866 .vactive = { 480, 480, 480 }, 2867 .vfront_porch = { 10, 10, 10 }, 2868 .vback_porch = { 10, 10, 10 }, 2869 .vsync_len = { 25, 25, 25 }, 2870 }; 2871 2872 static const struct panel_desc lg_lb070wv8 = { 2873 .timings = &lg_lb070wv8_timing, 2874 .num_timings = 1, 2875 .bpc = 8, 2876 .size = { 2877 .width = 151, 2878 .height = 91, 2879 }, 2880 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2881 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2882 }; 2883 2884 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 2885 .clock = 155127, 2886 .hdisplay = 1920, 2887 .hsync_start = 1920 + 128, 2888 .hsync_end = 1920 + 128 + 20, 2889 .htotal = 1920 + 128 + 20 + 12, 2890 .vdisplay = 1200, 2891 .vsync_start = 1200 + 19, 2892 .vsync_end = 1200 + 19 + 4, 2893 .vtotal = 1200 + 19 + 4 + 20, 2894 }; 2895 2896 static const struct panel_desc lincolntech_lcd185_101ct = { 2897 .modes = &lincolntech_lcd185_101ct_mode, 2898 .bpc = 8, 2899 .num_modes = 1, 2900 .size = { 2901 .width = 217, 2902 .height = 136, 2903 }, 2904 .delay = { 2905 .prepare = 50, 2906 .disable = 50, 2907 }, 2908 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2909 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2910 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2911 }; 2912 2913 static const struct display_timing logictechno_lt161010_2nh_timing = { 2914 .pixelclock = { 26400000, 33300000, 46800000 }, 2915 .hactive = { 800, 800, 800 }, 2916 .hfront_porch = { 16, 210, 354 }, 2917 .hback_porch = { 46, 46, 46 }, 2918 .hsync_len = { 1, 20, 40 }, 2919 .vactive = { 480, 480, 480 }, 2920 .vfront_porch = { 7, 22, 147 }, 2921 .vback_porch = { 23, 23, 23 }, 2922 .vsync_len = { 1, 10, 20 }, 2923 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2924 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2925 DISPLAY_FLAGS_SYNC_POSEDGE, 2926 }; 2927 2928 static const struct panel_desc logictechno_lt161010_2nh = { 2929 .timings = &logictechno_lt161010_2nh_timing, 2930 .num_timings = 1, 2931 .bpc = 6, 2932 .size = { 2933 .width = 154, 2934 .height = 86, 2935 }, 2936 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2937 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2938 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2939 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2940 .connector_type = DRM_MODE_CONNECTOR_DPI, 2941 }; 2942 2943 static const struct display_timing logictechno_lt170410_2whc_timing = { 2944 .pixelclock = { 68900000, 71100000, 73400000 }, 2945 .hactive = { 1280, 1280, 1280 }, 2946 .hfront_porch = { 23, 60, 71 }, 2947 .hback_porch = { 23, 60, 71 }, 2948 .hsync_len = { 15, 40, 47 }, 2949 .vactive = { 800, 800, 800 }, 2950 .vfront_porch = { 5, 7, 10 }, 2951 .vback_porch = { 5, 7, 10 }, 2952 .vsync_len = { 6, 9, 12 }, 2953 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2954 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2955 DISPLAY_FLAGS_SYNC_POSEDGE, 2956 }; 2957 2958 static const struct panel_desc logictechno_lt170410_2whc = { 2959 .timings = &logictechno_lt170410_2whc_timing, 2960 .num_timings = 1, 2961 .bpc = 8, 2962 .size = { 2963 .width = 217, 2964 .height = 136, 2965 }, 2966 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2967 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2968 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2969 }; 2970 2971 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2972 .clock = 33000, 2973 .hdisplay = 800, 2974 .hsync_start = 800 + 112, 2975 .hsync_end = 800 + 112 + 3, 2976 .htotal = 800 + 112 + 3 + 85, 2977 .vdisplay = 480, 2978 .vsync_start = 480 + 38, 2979 .vsync_end = 480 + 38 + 3, 2980 .vtotal = 480 + 38 + 3 + 29, 2981 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2982 }; 2983 2984 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2985 .modes = &logictechno_lttd800480070_l2rt_mode, 2986 .num_modes = 1, 2987 .bpc = 8, 2988 .size = { 2989 .width = 154, 2990 .height = 86, 2991 }, 2992 .delay = { 2993 .prepare = 45, 2994 .enable = 100, 2995 .disable = 100, 2996 .unprepare = 45 2997 }, 2998 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2999 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3000 .connector_type = DRM_MODE_CONNECTOR_DPI, 3001 }; 3002 3003 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3004 .clock = 33000, 3005 .hdisplay = 800, 3006 .hsync_start = 800 + 154, 3007 .hsync_end = 800 + 154 + 3, 3008 .htotal = 800 + 154 + 3 + 43, 3009 .vdisplay = 480, 3010 .vsync_start = 480 + 47, 3011 .vsync_end = 480 + 47 + 3, 3012 .vtotal = 480 + 47 + 3 + 20, 3013 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3014 }; 3015 3016 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3017 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3018 .num_modes = 1, 3019 .bpc = 8, 3020 .size = { 3021 .width = 154, 3022 .height = 86, 3023 }, 3024 .delay = { 3025 .prepare = 45, 3026 .enable = 100, 3027 .disable = 100, 3028 .unprepare = 45 3029 }, 3030 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3031 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3032 .connector_type = DRM_MODE_CONNECTOR_DPI, 3033 }; 3034 3035 static const struct drm_display_mode logicpd_type_28_mode = { 3036 .clock = 9107, 3037 .hdisplay = 480, 3038 .hsync_start = 480 + 3, 3039 .hsync_end = 480 + 3 + 42, 3040 .htotal = 480 + 3 + 42 + 2, 3041 3042 .vdisplay = 272, 3043 .vsync_start = 272 + 2, 3044 .vsync_end = 272 + 2 + 11, 3045 .vtotal = 272 + 2 + 11 + 3, 3046 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3047 }; 3048 3049 static const struct panel_desc logicpd_type_28 = { 3050 .modes = &logicpd_type_28_mode, 3051 .num_modes = 1, 3052 .bpc = 8, 3053 .size = { 3054 .width = 105, 3055 .height = 67, 3056 }, 3057 .delay = { 3058 .prepare = 200, 3059 .enable = 200, 3060 .unprepare = 200, 3061 .disable = 200, 3062 }, 3063 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3064 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3065 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3066 .connector_type = DRM_MODE_CONNECTOR_DPI, 3067 }; 3068 3069 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3070 .clock = 150275, 3071 .hdisplay = 1920, 3072 .hsync_start = 1920 + 32, 3073 .hsync_end = 1920 + 32 + 52, 3074 .htotal = 1920 + 32 + 52 + 24, 3075 .vdisplay = 1200, 3076 .vsync_start = 1200 + 24, 3077 .vsync_end = 1200 + 24 + 8, 3078 .vtotal = 1200 + 24 + 8 + 3, 3079 }; 3080 3081 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3082 .modes = µtips_mf_101hiebcaf0_c_mode, 3083 .bpc = 8, 3084 .num_modes = 1, 3085 .size = { 3086 .width = 217, 3087 .height = 136, 3088 }, 3089 .delay = { 3090 .prepare = 50, 3091 .disable = 50, 3092 }, 3093 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3094 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3095 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3096 }; 3097 3098 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3099 .clock = 93301, 3100 .hdisplay = 1920, 3101 .hsync_start = 1920 + 72, 3102 .hsync_end = 1920 + 72 + 72, 3103 .htotal = 1920 + 72 + 72 + 72, 3104 .vdisplay = 720, 3105 .vsync_start = 720 + 3, 3106 .vsync_end = 720 + 3 + 3, 3107 .vtotal = 720 + 3 + 3 + 2, 3108 }; 3109 3110 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3111 .modes = µtips_mf_103hieb0ga0_mode, 3112 .bpc = 8, 3113 .num_modes = 1, 3114 .size = { 3115 .width = 244, 3116 .height = 92, 3117 }, 3118 .delay = { 3119 .prepare = 50, 3120 .disable = 50, 3121 }, 3122 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3123 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3124 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3125 }; 3126 3127 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3128 .clock = 30400, 3129 .hdisplay = 800, 3130 .hsync_start = 800 + 0, 3131 .hsync_end = 800 + 1, 3132 .htotal = 800 + 0 + 1 + 160, 3133 .vdisplay = 480, 3134 .vsync_start = 480 + 0, 3135 .vsync_end = 480 + 48 + 1, 3136 .vtotal = 480 + 48 + 1 + 0, 3137 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3138 }; 3139 3140 static const struct panel_desc mitsubishi_aa070mc01 = { 3141 .modes = &mitsubishi_aa070mc01_mode, 3142 .num_modes = 1, 3143 .bpc = 8, 3144 .size = { 3145 .width = 152, 3146 .height = 91, 3147 }, 3148 3149 .delay = { 3150 .enable = 200, 3151 .unprepare = 200, 3152 .disable = 400, 3153 }, 3154 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3155 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3156 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3157 }; 3158 3159 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3160 .clock = 56234, 3161 .hdisplay = 1024, 3162 .hsync_start = 1024 + 24, 3163 .hsync_end = 1024 + 24 + 63, 3164 .htotal = 1024 + 24 + 63 + 1, 3165 .vdisplay = 768, 3166 .vsync_start = 768 + 3, 3167 .vsync_end = 768 + 3 + 6, 3168 .vtotal = 768 + 3 + 6 + 1, 3169 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3170 }; 3171 3172 static const struct panel_desc mitsubishi_aa084xe01 = { 3173 .modes = &mitsubishi_aa084xe01_mode, 3174 .num_modes = 1, 3175 .bpc = 8, 3176 .size = { 3177 .width = 1024, 3178 .height = 768, 3179 }, 3180 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3181 .connector_type = DRM_MODE_CONNECTOR_DPI, 3182 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3183 }; 3184 3185 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3186 .pixelclock = { 29000000, 33000000, 38000000 }, 3187 .hactive = { 800, 800, 800 }, 3188 .hfront_porch = { 180, 210, 240 }, 3189 .hback_porch = { 16, 16, 16 }, 3190 .hsync_len = { 30, 30, 30 }, 3191 .vactive = { 480, 480, 480 }, 3192 .vfront_porch = { 12, 22, 32 }, 3193 .vback_porch = { 10, 10, 10 }, 3194 .vsync_len = { 13, 13, 13 }, 3195 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3196 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3197 DISPLAY_FLAGS_SYNC_POSEDGE, 3198 }; 3199 3200 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3201 .timings = &multi_inno_mi0700s4t_6_timing, 3202 .num_timings = 1, 3203 .bpc = 8, 3204 .size = { 3205 .width = 154, 3206 .height = 86, 3207 }, 3208 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3209 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3210 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3211 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3212 .connector_type = DRM_MODE_CONNECTOR_DPI, 3213 }; 3214 3215 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3216 .pixelclock = { 32000000, 40000000, 50000000 }, 3217 .hactive = { 800, 800, 800 }, 3218 .hfront_porch = { 16, 210, 354 }, 3219 .hback_porch = { 6, 26, 45 }, 3220 .hsync_len = { 1, 20, 40 }, 3221 .vactive = { 600, 600, 600 }, 3222 .vfront_porch = { 1, 12, 77 }, 3223 .vback_porch = { 3, 13, 22 }, 3224 .vsync_len = { 1, 10, 20 }, 3225 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3226 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3227 DISPLAY_FLAGS_SYNC_POSEDGE, 3228 }; 3229 3230 static const struct panel_desc multi_inno_mi0800ft_9 = { 3231 .timings = &multi_inno_mi0800ft_9_timing, 3232 .num_timings = 1, 3233 .bpc = 8, 3234 .size = { 3235 .width = 162, 3236 .height = 122, 3237 }, 3238 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3239 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3240 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3241 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3242 .connector_type = DRM_MODE_CONNECTOR_DPI, 3243 }; 3244 3245 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3246 .pixelclock = { 68900000, 70000000, 73400000 }, 3247 .hactive = { 1280, 1280, 1280 }, 3248 .hfront_porch = { 30, 60, 71 }, 3249 .hback_porch = { 30, 60, 71 }, 3250 .hsync_len = { 10, 10, 48 }, 3251 .vactive = { 800, 800, 800 }, 3252 .vfront_porch = { 5, 10, 10 }, 3253 .vback_porch = { 5, 10, 10 }, 3254 .vsync_len = { 5, 6, 13 }, 3255 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3256 DISPLAY_FLAGS_DE_HIGH, 3257 }; 3258 3259 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3260 .timings = &multi_inno_mi1010ait_1cp_timing, 3261 .num_timings = 1, 3262 .bpc = 8, 3263 .size = { 3264 .width = 217, 3265 .height = 136, 3266 }, 3267 .delay = { 3268 .enable = 50, 3269 .disable = 50, 3270 }, 3271 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3272 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3273 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3274 }; 3275 3276 static const struct display_timing nec_nl12880bc20_05_timing = { 3277 .pixelclock = { 67000000, 71000000, 75000000 }, 3278 .hactive = { 1280, 1280, 1280 }, 3279 .hfront_porch = { 2, 30, 30 }, 3280 .hback_porch = { 6, 100, 100 }, 3281 .hsync_len = { 2, 30, 30 }, 3282 .vactive = { 800, 800, 800 }, 3283 .vfront_porch = { 5, 5, 5 }, 3284 .vback_porch = { 11, 11, 11 }, 3285 .vsync_len = { 7, 7, 7 }, 3286 }; 3287 3288 static const struct panel_desc nec_nl12880bc20_05 = { 3289 .timings = &nec_nl12880bc20_05_timing, 3290 .num_timings = 1, 3291 .bpc = 8, 3292 .size = { 3293 .width = 261, 3294 .height = 163, 3295 }, 3296 .delay = { 3297 .enable = 50, 3298 .disable = 50, 3299 }, 3300 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3301 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3302 }; 3303 3304 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3305 .clock = 10870, 3306 .hdisplay = 480, 3307 .hsync_start = 480 + 2, 3308 .hsync_end = 480 + 2 + 41, 3309 .htotal = 480 + 2 + 41 + 2, 3310 .vdisplay = 272, 3311 .vsync_start = 272 + 2, 3312 .vsync_end = 272 + 2 + 4, 3313 .vtotal = 272 + 2 + 4 + 2, 3314 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3315 }; 3316 3317 static const struct panel_desc nec_nl4827hc19_05b = { 3318 .modes = &nec_nl4827hc19_05b_mode, 3319 .num_modes = 1, 3320 .bpc = 8, 3321 .size = { 3322 .width = 95, 3323 .height = 54, 3324 }, 3325 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3326 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3327 }; 3328 3329 static const struct drm_display_mode netron_dy_e231732_mode = { 3330 .clock = 66000, 3331 .hdisplay = 1024, 3332 .hsync_start = 1024 + 160, 3333 .hsync_end = 1024 + 160 + 70, 3334 .htotal = 1024 + 160 + 70 + 90, 3335 .vdisplay = 600, 3336 .vsync_start = 600 + 127, 3337 .vsync_end = 600 + 127 + 20, 3338 .vtotal = 600 + 127 + 20 + 3, 3339 }; 3340 3341 static const struct panel_desc netron_dy_e231732 = { 3342 .modes = &netron_dy_e231732_mode, 3343 .num_modes = 1, 3344 .size = { 3345 .width = 154, 3346 .height = 87, 3347 }, 3348 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3349 }; 3350 3351 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3352 .clock = 9000, 3353 .hdisplay = 480, 3354 .hsync_start = 480 + 2, 3355 .hsync_end = 480 + 2 + 41, 3356 .htotal = 480 + 2 + 41 + 2, 3357 .vdisplay = 272, 3358 .vsync_start = 272 + 2, 3359 .vsync_end = 272 + 2 + 10, 3360 .vtotal = 272 + 2 + 10 + 2, 3361 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3362 }; 3363 3364 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3365 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3366 .num_modes = 1, 3367 .bpc = 8, 3368 .size = { 3369 .width = 95, 3370 .height = 54, 3371 }, 3372 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3373 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3374 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3375 .connector_type = DRM_MODE_CONNECTOR_DPI, 3376 }; 3377 3378 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3379 .pixelclock = { 130000000, 148350000, 163000000 }, 3380 .hactive = { 1920, 1920, 1920 }, 3381 .hfront_porch = { 80, 100, 100 }, 3382 .hback_porch = { 100, 120, 120 }, 3383 .hsync_len = { 50, 60, 60 }, 3384 .vactive = { 1080, 1080, 1080 }, 3385 .vfront_porch = { 12, 30, 30 }, 3386 .vback_porch = { 4, 10, 10 }, 3387 .vsync_len = { 4, 5, 5 }, 3388 }; 3389 3390 static const struct panel_desc nlt_nl192108ac18_02d = { 3391 .timings = &nlt_nl192108ac18_02d_timing, 3392 .num_timings = 1, 3393 .bpc = 8, 3394 .size = { 3395 .width = 344, 3396 .height = 194, 3397 }, 3398 .delay = { 3399 .unprepare = 500, 3400 }, 3401 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3402 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3403 }; 3404 3405 static const struct drm_display_mode nvd_9128_mode = { 3406 .clock = 29500, 3407 .hdisplay = 800, 3408 .hsync_start = 800 + 130, 3409 .hsync_end = 800 + 130 + 98, 3410 .htotal = 800 + 0 + 130 + 98, 3411 .vdisplay = 480, 3412 .vsync_start = 480 + 10, 3413 .vsync_end = 480 + 10 + 50, 3414 .vtotal = 480 + 0 + 10 + 50, 3415 }; 3416 3417 static const struct panel_desc nvd_9128 = { 3418 .modes = &nvd_9128_mode, 3419 .num_modes = 1, 3420 .bpc = 8, 3421 .size = { 3422 .width = 156, 3423 .height = 88, 3424 }, 3425 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3426 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3427 }; 3428 3429 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3430 .pixelclock = { 30000000, 30000000, 40000000 }, 3431 .hactive = { 800, 800, 800 }, 3432 .hfront_porch = { 40, 40, 40 }, 3433 .hback_porch = { 40, 40, 40 }, 3434 .hsync_len = { 1, 48, 48 }, 3435 .vactive = { 480, 480, 480 }, 3436 .vfront_porch = { 13, 13, 13 }, 3437 .vback_porch = { 29, 29, 29 }, 3438 .vsync_len = { 3, 3, 3 }, 3439 .flags = DISPLAY_FLAGS_DE_HIGH, 3440 }; 3441 3442 static const struct panel_desc okaya_rs800480t_7x0gp = { 3443 .timings = &okaya_rs800480t_7x0gp_timing, 3444 .num_timings = 1, 3445 .bpc = 6, 3446 .size = { 3447 .width = 154, 3448 .height = 87, 3449 }, 3450 .delay = { 3451 .prepare = 41, 3452 .enable = 50, 3453 .unprepare = 41, 3454 .disable = 50, 3455 }, 3456 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3457 }; 3458 3459 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3460 .clock = 9000, 3461 .hdisplay = 480, 3462 .hsync_start = 480 + 5, 3463 .hsync_end = 480 + 5 + 30, 3464 .htotal = 480 + 5 + 30 + 10, 3465 .vdisplay = 272, 3466 .vsync_start = 272 + 8, 3467 .vsync_end = 272 + 8 + 5, 3468 .vtotal = 272 + 8 + 5 + 3, 3469 }; 3470 3471 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3472 .modes = &olimex_lcd_olinuxino_43ts_mode, 3473 .num_modes = 1, 3474 .size = { 3475 .width = 95, 3476 .height = 54, 3477 }, 3478 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3479 }; 3480 3481 /* 3482 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3483 * pixel clocks, but this is the timing that was being used in the Adafruit 3484 * installation instructions. 3485 */ 3486 static const struct drm_display_mode ontat_yx700wv03_mode = { 3487 .clock = 29500, 3488 .hdisplay = 800, 3489 .hsync_start = 824, 3490 .hsync_end = 896, 3491 .htotal = 992, 3492 .vdisplay = 480, 3493 .vsync_start = 483, 3494 .vsync_end = 493, 3495 .vtotal = 500, 3496 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3497 }; 3498 3499 /* 3500 * Specification at: 3501 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3502 */ 3503 static const struct panel_desc ontat_yx700wv03 = { 3504 .modes = &ontat_yx700wv03_mode, 3505 .num_modes = 1, 3506 .bpc = 8, 3507 .size = { 3508 .width = 154, 3509 .height = 83, 3510 }, 3511 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3512 }; 3513 3514 static const struct drm_display_mode ortustech_com37h3m_mode = { 3515 .clock = 22230, 3516 .hdisplay = 480, 3517 .hsync_start = 480 + 40, 3518 .hsync_end = 480 + 40 + 10, 3519 .htotal = 480 + 40 + 10 + 40, 3520 .vdisplay = 640, 3521 .vsync_start = 640 + 4, 3522 .vsync_end = 640 + 4 + 2, 3523 .vtotal = 640 + 4 + 2 + 4, 3524 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3525 }; 3526 3527 static const struct panel_desc ortustech_com37h3m = { 3528 .modes = &ortustech_com37h3m_mode, 3529 .num_modes = 1, 3530 .bpc = 8, 3531 .size = { 3532 .width = 56, /* 56.16mm */ 3533 .height = 75, /* 74.88mm */ 3534 }, 3535 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3536 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3537 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3538 }; 3539 3540 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3541 .clock = 25000, 3542 .hdisplay = 480, 3543 .hsync_start = 480 + 10, 3544 .hsync_end = 480 + 10 + 10, 3545 .htotal = 480 + 10 + 10 + 15, 3546 .vdisplay = 800, 3547 .vsync_start = 800 + 3, 3548 .vsync_end = 800 + 3 + 3, 3549 .vtotal = 800 + 3 + 3 + 3, 3550 }; 3551 3552 static const struct panel_desc ortustech_com43h4m85ulc = { 3553 .modes = &ortustech_com43h4m85ulc_mode, 3554 .num_modes = 1, 3555 .bpc = 6, 3556 .size = { 3557 .width = 56, 3558 .height = 93, 3559 }, 3560 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3561 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3562 .connector_type = DRM_MODE_CONNECTOR_DPI, 3563 }; 3564 3565 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3566 .clock = 33000, 3567 .hdisplay = 800, 3568 .hsync_start = 800 + 210, 3569 .hsync_end = 800 + 210 + 30, 3570 .htotal = 800 + 210 + 30 + 16, 3571 .vdisplay = 480, 3572 .vsync_start = 480 + 22, 3573 .vsync_end = 480 + 22 + 13, 3574 .vtotal = 480 + 22 + 13 + 10, 3575 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3576 }; 3577 3578 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3579 .modes = &osddisplays_osd070t1718_19ts_mode, 3580 .num_modes = 1, 3581 .bpc = 8, 3582 .size = { 3583 .width = 152, 3584 .height = 91, 3585 }, 3586 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3587 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3588 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3589 .connector_type = DRM_MODE_CONNECTOR_DPI, 3590 }; 3591 3592 static const struct drm_display_mode pda_91_00156_a0_mode = { 3593 .clock = 33300, 3594 .hdisplay = 800, 3595 .hsync_start = 800 + 1, 3596 .hsync_end = 800 + 1 + 64, 3597 .htotal = 800 + 1 + 64 + 64, 3598 .vdisplay = 480, 3599 .vsync_start = 480 + 1, 3600 .vsync_end = 480 + 1 + 23, 3601 .vtotal = 480 + 1 + 23 + 22, 3602 }; 3603 3604 static const struct panel_desc pda_91_00156_a0 = { 3605 .modes = &pda_91_00156_a0_mode, 3606 .num_modes = 1, 3607 .size = { 3608 .width = 152, 3609 .height = 91, 3610 }, 3611 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3612 }; 3613 3614 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 3615 .clock = 66500, 3616 .hdisplay = 1280, 3617 .hsync_start = 1280 + 12, 3618 .hsync_end = 1280 + 12 + 20, 3619 .htotal = 1280 + 12 + 20 + 56, 3620 .vdisplay = 800, 3621 .vsync_start = 800 + 1, 3622 .vsync_end = 800 + 1 + 3, 3623 .vtotal = 800 + 1 + 3 + 20, 3624 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3625 }; 3626 3627 static const struct panel_desc powertip_ph128800t006_zhc01 = { 3628 .modes = &powertip_ph128800t006_zhc01_mode, 3629 .num_modes = 1, 3630 .bpc = 8, 3631 .size = { 3632 .width = 216, 3633 .height = 135, 3634 }, 3635 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3636 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3637 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3638 }; 3639 3640 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3641 .clock = 24750, 3642 .hdisplay = 800, 3643 .hsync_start = 800 + 54, 3644 .hsync_end = 800 + 54 + 2, 3645 .htotal = 800 + 54 + 2 + 44, 3646 .vdisplay = 480, 3647 .vsync_start = 480 + 49, 3648 .vsync_end = 480 + 49 + 2, 3649 .vtotal = 480 + 49 + 2 + 22, 3650 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3651 }; 3652 3653 static const struct panel_desc powertip_ph800480t013_idf02 = { 3654 .modes = &powertip_ph800480t013_idf02_mode, 3655 .num_modes = 1, 3656 .bpc = 8, 3657 .size = { 3658 .width = 152, 3659 .height = 91, 3660 }, 3661 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3662 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3663 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3664 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3665 .connector_type = DRM_MODE_CONNECTOR_DPI, 3666 }; 3667 3668 static const struct drm_display_mode primeview_pm070wl4_mode = { 3669 .clock = 32000, 3670 .hdisplay = 800, 3671 .hsync_start = 800 + 42, 3672 .hsync_end = 800 + 42 + 128, 3673 .htotal = 800 + 42 + 128 + 86, 3674 .vdisplay = 480, 3675 .vsync_start = 480 + 10, 3676 .vsync_end = 480 + 10 + 2, 3677 .vtotal = 480 + 10 + 2 + 33, 3678 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3679 }; 3680 3681 static const struct panel_desc primeview_pm070wl4 = { 3682 .modes = &primeview_pm070wl4_mode, 3683 .num_modes = 1, 3684 .bpc = 6, 3685 .size = { 3686 .width = 152, 3687 .height = 91, 3688 }, 3689 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3690 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3691 .connector_type = DRM_MODE_CONNECTOR_DPI, 3692 }; 3693 3694 static const struct drm_display_mode qd43003c0_40_mode = { 3695 .clock = 9000, 3696 .hdisplay = 480, 3697 .hsync_start = 480 + 8, 3698 .hsync_end = 480 + 8 + 4, 3699 .htotal = 480 + 8 + 4 + 39, 3700 .vdisplay = 272, 3701 .vsync_start = 272 + 4, 3702 .vsync_end = 272 + 4 + 10, 3703 .vtotal = 272 + 4 + 10 + 2, 3704 }; 3705 3706 static const struct panel_desc qd43003c0_40 = { 3707 .modes = &qd43003c0_40_mode, 3708 .num_modes = 1, 3709 .bpc = 8, 3710 .size = { 3711 .width = 95, 3712 .height = 53, 3713 }, 3714 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3715 }; 3716 3717 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3718 { /* 60 Hz */ 3719 .clock = 10800, 3720 .hdisplay = 480, 3721 .hsync_start = 480 + 77, 3722 .hsync_end = 480 + 77 + 41, 3723 .htotal = 480 + 77 + 41 + 2, 3724 .vdisplay = 272, 3725 .vsync_start = 272 + 16, 3726 .vsync_end = 272 + 16 + 10, 3727 .vtotal = 272 + 16 + 10 + 2, 3728 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3729 }, 3730 { /* 50 Hz */ 3731 .clock = 10800, 3732 .hdisplay = 480, 3733 .hsync_start = 480 + 17, 3734 .hsync_end = 480 + 17 + 41, 3735 .htotal = 480 + 17 + 41 + 2, 3736 .vdisplay = 272, 3737 .vsync_start = 272 + 116, 3738 .vsync_end = 272 + 116 + 10, 3739 .vtotal = 272 + 116 + 10 + 2, 3740 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3741 }, 3742 }; 3743 3744 static const struct panel_desc qishenglong_gopher2b_lcd = { 3745 .modes = qishenglong_gopher2b_lcd_modes, 3746 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3747 .bpc = 8, 3748 .size = { 3749 .width = 95, 3750 .height = 54, 3751 }, 3752 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3753 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3754 .connector_type = DRM_MODE_CONNECTOR_DPI, 3755 }; 3756 3757 static const struct display_timing rocktech_rk043fn48h_timing = { 3758 .pixelclock = { 6000000, 9000000, 12000000 }, 3759 .hactive = { 480, 480, 480 }, 3760 .hback_porch = { 8, 43, 43 }, 3761 .hfront_porch = { 2, 8, 10 }, 3762 .hsync_len = { 1, 1, 1 }, 3763 .vactive = { 272, 272, 272 }, 3764 .vback_porch = { 2, 12, 26 }, 3765 .vfront_porch = { 1, 4, 4 }, 3766 .vsync_len = { 1, 10, 10 }, 3767 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3768 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3769 DISPLAY_FLAGS_SYNC_POSEDGE, 3770 }; 3771 3772 static const struct panel_desc rocktech_rk043fn48h = { 3773 .timings = &rocktech_rk043fn48h_timing, 3774 .num_timings = 1, 3775 .bpc = 8, 3776 .size = { 3777 .width = 95, 3778 .height = 54, 3779 }, 3780 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3781 .connector_type = DRM_MODE_CONNECTOR_DPI, 3782 }; 3783 3784 static const struct display_timing rocktech_rk070er9427_timing = { 3785 .pixelclock = { 26400000, 33300000, 46800000 }, 3786 .hactive = { 800, 800, 800 }, 3787 .hfront_porch = { 16, 210, 354 }, 3788 .hback_porch = { 46, 46, 46 }, 3789 .hsync_len = { 1, 1, 1 }, 3790 .vactive = { 480, 480, 480 }, 3791 .vfront_porch = { 7, 22, 147 }, 3792 .vback_porch = { 23, 23, 23 }, 3793 .vsync_len = { 1, 1, 1 }, 3794 .flags = DISPLAY_FLAGS_DE_HIGH, 3795 }; 3796 3797 static const struct panel_desc rocktech_rk070er9427 = { 3798 .timings = &rocktech_rk070er9427_timing, 3799 .num_timings = 1, 3800 .bpc = 6, 3801 .size = { 3802 .width = 154, 3803 .height = 86, 3804 }, 3805 .delay = { 3806 .prepare = 41, 3807 .enable = 50, 3808 .unprepare = 41, 3809 .disable = 50, 3810 }, 3811 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3812 }; 3813 3814 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3815 .clock = 71100, 3816 .hdisplay = 1280, 3817 .hsync_start = 1280 + 48, 3818 .hsync_end = 1280 + 48 + 32, 3819 .htotal = 1280 + 48 + 32 + 80, 3820 .vdisplay = 800, 3821 .vsync_start = 800 + 2, 3822 .vsync_end = 800 + 2 + 5, 3823 .vtotal = 800 + 2 + 5 + 16, 3824 }; 3825 3826 static const struct panel_desc rocktech_rk101ii01d_ct = { 3827 .modes = &rocktech_rk101ii01d_ct_mode, 3828 .bpc = 8, 3829 .num_modes = 1, 3830 .size = { 3831 .width = 217, 3832 .height = 136, 3833 }, 3834 .delay = { 3835 .prepare = 50, 3836 .disable = 50, 3837 }, 3838 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3839 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3840 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3841 }; 3842 3843 static const struct display_timing samsung_ltl101al01_timing = { 3844 .pixelclock = { 66663000, 66663000, 66663000 }, 3845 .hactive = { 1280, 1280, 1280 }, 3846 .hfront_porch = { 18, 18, 18 }, 3847 .hback_porch = { 36, 36, 36 }, 3848 .hsync_len = { 16, 16, 16 }, 3849 .vactive = { 800, 800, 800 }, 3850 .vfront_porch = { 4, 4, 4 }, 3851 .vback_porch = { 16, 16, 16 }, 3852 .vsync_len = { 3, 3, 3 }, 3853 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3854 }; 3855 3856 static const struct panel_desc samsung_ltl101al01 = { 3857 .timings = &samsung_ltl101al01_timing, 3858 .num_timings = 1, 3859 .bpc = 8, 3860 .size = { 3861 .width = 217, 3862 .height = 135, 3863 }, 3864 .delay = { 3865 .prepare = 40, 3866 .enable = 300, 3867 .disable = 200, 3868 .unprepare = 600, 3869 }, 3870 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3871 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3872 }; 3873 3874 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3875 .clock = 54030, 3876 .hdisplay = 1024, 3877 .hsync_start = 1024 + 24, 3878 .hsync_end = 1024 + 24 + 136, 3879 .htotal = 1024 + 24 + 136 + 160, 3880 .vdisplay = 600, 3881 .vsync_start = 600 + 3, 3882 .vsync_end = 600 + 3 + 6, 3883 .vtotal = 600 + 3 + 6 + 61, 3884 }; 3885 3886 static const struct panel_desc samsung_ltn101nt05 = { 3887 .modes = &samsung_ltn101nt05_mode, 3888 .num_modes = 1, 3889 .bpc = 6, 3890 .size = { 3891 .width = 223, 3892 .height = 125, 3893 }, 3894 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3895 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3896 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3897 }; 3898 3899 static const struct display_timing satoz_sat050at40h12r2_timing = { 3900 .pixelclock = {33300000, 33300000, 50000000}, 3901 .hactive = {800, 800, 800}, 3902 .hfront_porch = {16, 210, 354}, 3903 .hback_porch = {46, 46, 46}, 3904 .hsync_len = {1, 1, 40}, 3905 .vactive = {480, 480, 480}, 3906 .vfront_porch = {7, 22, 147}, 3907 .vback_porch = {23, 23, 23}, 3908 .vsync_len = {1, 1, 20}, 3909 }; 3910 3911 static const struct panel_desc satoz_sat050at40h12r2 = { 3912 .timings = &satoz_sat050at40h12r2_timing, 3913 .num_timings = 1, 3914 .bpc = 8, 3915 .size = { 3916 .width = 108, 3917 .height = 65, 3918 }, 3919 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3920 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3921 }; 3922 3923 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3924 .clock = 33260, 3925 .hdisplay = 800, 3926 .hsync_start = 800 + 64, 3927 .hsync_end = 800 + 64 + 128, 3928 .htotal = 800 + 64 + 128 + 64, 3929 .vdisplay = 480, 3930 .vsync_start = 480 + 8, 3931 .vsync_end = 480 + 8 + 2, 3932 .vtotal = 480 + 8 + 2 + 35, 3933 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3934 }; 3935 3936 static const struct panel_desc sharp_lq070y3dg3b = { 3937 .modes = &sharp_lq070y3dg3b_mode, 3938 .num_modes = 1, 3939 .bpc = 8, 3940 .size = { 3941 .width = 152, /* 152.4mm */ 3942 .height = 91, /* 91.4mm */ 3943 }, 3944 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3945 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3946 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3947 }; 3948 3949 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3950 .clock = 5500, 3951 .hdisplay = 240, 3952 .hsync_start = 240 + 16, 3953 .hsync_end = 240 + 16 + 7, 3954 .htotal = 240 + 16 + 7 + 5, 3955 .vdisplay = 320, 3956 .vsync_start = 320 + 9, 3957 .vsync_end = 320 + 9 + 1, 3958 .vtotal = 320 + 9 + 1 + 7, 3959 }; 3960 3961 static const struct panel_desc sharp_lq035q7db03 = { 3962 .modes = &sharp_lq035q7db03_mode, 3963 .num_modes = 1, 3964 .bpc = 6, 3965 .size = { 3966 .width = 54, 3967 .height = 72, 3968 }, 3969 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3970 }; 3971 3972 static const struct display_timing sharp_lq101k1ly04_timing = { 3973 .pixelclock = { 60000000, 65000000, 80000000 }, 3974 .hactive = { 1280, 1280, 1280 }, 3975 .hfront_porch = { 20, 20, 20 }, 3976 .hback_porch = { 20, 20, 20 }, 3977 .hsync_len = { 10, 10, 10 }, 3978 .vactive = { 800, 800, 800 }, 3979 .vfront_porch = { 4, 4, 4 }, 3980 .vback_porch = { 4, 4, 4 }, 3981 .vsync_len = { 4, 4, 4 }, 3982 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3983 }; 3984 3985 static const struct panel_desc sharp_lq101k1ly04 = { 3986 .timings = &sharp_lq101k1ly04_timing, 3987 .num_timings = 1, 3988 .bpc = 8, 3989 .size = { 3990 .width = 217, 3991 .height = 136, 3992 }, 3993 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3994 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3995 }; 3996 3997 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3998 { /* 50 Hz */ 3999 .clock = 3000, 4000 .hdisplay = 240, 4001 .hsync_start = 240 + 58, 4002 .hsync_end = 240 + 58 + 1, 4003 .htotal = 240 + 58 + 1 + 1, 4004 .vdisplay = 160, 4005 .vsync_start = 160 + 24, 4006 .vsync_end = 160 + 24 + 10, 4007 .vtotal = 160 + 24 + 10 + 6, 4008 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4009 }, 4010 { /* 60 Hz */ 4011 .clock = 3000, 4012 .hdisplay = 240, 4013 .hsync_start = 240 + 8, 4014 .hsync_end = 240 + 8 + 1, 4015 .htotal = 240 + 8 + 1 + 1, 4016 .vdisplay = 160, 4017 .vsync_start = 160 + 24, 4018 .vsync_end = 160 + 24 + 10, 4019 .vtotal = 160 + 24 + 10 + 6, 4020 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4021 }, 4022 }; 4023 4024 static const struct panel_desc sharp_ls020b1dd01d = { 4025 .modes = sharp_ls020b1dd01d_modes, 4026 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4027 .bpc = 6, 4028 .size = { 4029 .width = 42, 4030 .height = 28, 4031 }, 4032 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4033 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4034 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4035 | DRM_BUS_FLAG_SHARP_SIGNALS, 4036 }; 4037 4038 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4039 .clock = 33300, 4040 .hdisplay = 800, 4041 .hsync_start = 800 + 1, 4042 .hsync_end = 800 + 1 + 64, 4043 .htotal = 800 + 1 + 64 + 64, 4044 .vdisplay = 480, 4045 .vsync_start = 480 + 1, 4046 .vsync_end = 480 + 1 + 23, 4047 .vtotal = 480 + 1 + 23 + 22, 4048 }; 4049 4050 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4051 .modes = &shelly_sca07010_bfn_lnn_mode, 4052 .num_modes = 1, 4053 .size = { 4054 .width = 152, 4055 .height = 91, 4056 }, 4057 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4058 }; 4059 4060 static const struct drm_display_mode starry_kr070pe2t_mode = { 4061 .clock = 33000, 4062 .hdisplay = 800, 4063 .hsync_start = 800 + 209, 4064 .hsync_end = 800 + 209 + 1, 4065 .htotal = 800 + 209 + 1 + 45, 4066 .vdisplay = 480, 4067 .vsync_start = 480 + 22, 4068 .vsync_end = 480 + 22 + 1, 4069 .vtotal = 480 + 22 + 1 + 22, 4070 }; 4071 4072 static const struct panel_desc starry_kr070pe2t = { 4073 .modes = &starry_kr070pe2t_mode, 4074 .num_modes = 1, 4075 .bpc = 8, 4076 .size = { 4077 .width = 152, 4078 .height = 86, 4079 }, 4080 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4081 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4082 .connector_type = DRM_MODE_CONNECTOR_DPI, 4083 }; 4084 4085 static const struct display_timing startek_kd070wvfpa_mode = { 4086 .pixelclock = { 25200000, 27200000, 30500000 }, 4087 .hactive = { 800, 800, 800 }, 4088 .hfront_porch = { 19, 44, 115 }, 4089 .hback_porch = { 5, 16, 101 }, 4090 .hsync_len = { 1, 2, 100 }, 4091 .vactive = { 480, 480, 480 }, 4092 .vfront_porch = { 5, 43, 67 }, 4093 .vback_porch = { 5, 5, 67 }, 4094 .vsync_len = { 1, 2, 66 }, 4095 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4096 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4097 DISPLAY_FLAGS_SYNC_POSEDGE, 4098 }; 4099 4100 static const struct panel_desc startek_kd070wvfpa = { 4101 .timings = &startek_kd070wvfpa_mode, 4102 .num_timings = 1, 4103 .bpc = 8, 4104 .size = { 4105 .width = 152, 4106 .height = 91, 4107 }, 4108 .delay = { 4109 .prepare = 20, 4110 .enable = 200, 4111 .disable = 200, 4112 }, 4113 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4114 .connector_type = DRM_MODE_CONNECTOR_DPI, 4115 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4116 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4117 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4118 }; 4119 4120 static const struct display_timing tsd_tst043015cmhx_timing = { 4121 .pixelclock = { 5000000, 9000000, 12000000 }, 4122 .hactive = { 480, 480, 480 }, 4123 .hfront_porch = { 4, 5, 65 }, 4124 .hback_porch = { 36, 40, 255 }, 4125 .hsync_len = { 1, 1, 1 }, 4126 .vactive = { 272, 272, 272 }, 4127 .vfront_porch = { 2, 8, 97 }, 4128 .vback_porch = { 3, 8, 31 }, 4129 .vsync_len = { 1, 1, 1 }, 4130 4131 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4132 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4133 }; 4134 4135 static const struct panel_desc tsd_tst043015cmhx = { 4136 .timings = &tsd_tst043015cmhx_timing, 4137 .num_timings = 1, 4138 .bpc = 8, 4139 .size = { 4140 .width = 105, 4141 .height = 67, 4142 }, 4143 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4144 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4145 }; 4146 4147 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4148 .clock = 30000, 4149 .hdisplay = 800, 4150 .hsync_start = 800 + 39, 4151 .hsync_end = 800 + 39 + 47, 4152 .htotal = 800 + 39 + 47 + 39, 4153 .vdisplay = 480, 4154 .vsync_start = 480 + 13, 4155 .vsync_end = 480 + 13 + 2, 4156 .vtotal = 480 + 13 + 2 + 29, 4157 }; 4158 4159 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4160 .modes = &tfc_s9700rtwv43tr_01b_mode, 4161 .num_modes = 1, 4162 .bpc = 8, 4163 .size = { 4164 .width = 155, 4165 .height = 90, 4166 }, 4167 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4168 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4169 }; 4170 4171 static const struct display_timing tianma_tm070jdhg30_timing = { 4172 .pixelclock = { 62600000, 68200000, 78100000 }, 4173 .hactive = { 1280, 1280, 1280 }, 4174 .hfront_porch = { 15, 64, 159 }, 4175 .hback_porch = { 5, 5, 5 }, 4176 .hsync_len = { 1, 1, 256 }, 4177 .vactive = { 800, 800, 800 }, 4178 .vfront_porch = { 3, 40, 99 }, 4179 .vback_porch = { 2, 2, 2 }, 4180 .vsync_len = { 1, 1, 128 }, 4181 .flags = DISPLAY_FLAGS_DE_HIGH, 4182 }; 4183 4184 static const struct panel_desc tianma_tm070jdhg30 = { 4185 .timings = &tianma_tm070jdhg30_timing, 4186 .num_timings = 1, 4187 .bpc = 8, 4188 .size = { 4189 .width = 151, 4190 .height = 95, 4191 }, 4192 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4193 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4194 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4195 }; 4196 4197 static const struct panel_desc tianma_tm070jvhg33 = { 4198 .timings = &tianma_tm070jdhg30_timing, 4199 .num_timings = 1, 4200 .bpc = 8, 4201 .size = { 4202 .width = 150, 4203 .height = 94, 4204 }, 4205 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4206 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4207 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4208 }; 4209 4210 static const struct display_timing tianma_tm070rvhg71_timing = { 4211 .pixelclock = { 27700000, 29200000, 39600000 }, 4212 .hactive = { 800, 800, 800 }, 4213 .hfront_porch = { 12, 40, 212 }, 4214 .hback_porch = { 88, 88, 88 }, 4215 .hsync_len = { 1, 1, 40 }, 4216 .vactive = { 480, 480, 480 }, 4217 .vfront_porch = { 1, 13, 88 }, 4218 .vback_porch = { 32, 32, 32 }, 4219 .vsync_len = { 1, 1, 3 }, 4220 .flags = DISPLAY_FLAGS_DE_HIGH, 4221 }; 4222 4223 static const struct panel_desc tianma_tm070rvhg71 = { 4224 .timings = &tianma_tm070rvhg71_timing, 4225 .num_timings = 1, 4226 .bpc = 8, 4227 .size = { 4228 .width = 154, 4229 .height = 86, 4230 }, 4231 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4232 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4233 }; 4234 4235 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4236 { 4237 .clock = 10000, 4238 .hdisplay = 320, 4239 .hsync_start = 320 + 50, 4240 .hsync_end = 320 + 50 + 6, 4241 .htotal = 320 + 50 + 6 + 38, 4242 .vdisplay = 240, 4243 .vsync_start = 240 + 3, 4244 .vsync_end = 240 + 3 + 1, 4245 .vtotal = 240 + 3 + 1 + 17, 4246 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4247 }, 4248 }; 4249 4250 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4251 .modes = ti_nspire_cx_lcd_mode, 4252 .num_modes = 1, 4253 .bpc = 8, 4254 .size = { 4255 .width = 65, 4256 .height = 49, 4257 }, 4258 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4259 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4260 }; 4261 4262 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4263 { 4264 .clock = 10000, 4265 .hdisplay = 320, 4266 .hsync_start = 320 + 6, 4267 .hsync_end = 320 + 6 + 6, 4268 .htotal = 320 + 6 + 6 + 6, 4269 .vdisplay = 240, 4270 .vsync_start = 240 + 0, 4271 .vsync_end = 240 + 0 + 1, 4272 .vtotal = 240 + 0 + 1 + 0, 4273 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4274 }, 4275 }; 4276 4277 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4278 .modes = ti_nspire_classic_lcd_mode, 4279 .num_modes = 1, 4280 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4281 .bpc = 8, 4282 .size = { 4283 .width = 71, 4284 .height = 53, 4285 }, 4286 /* This is the grayscale bus format */ 4287 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4288 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4289 }; 4290 4291 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4292 .clock = 79500, 4293 .hdisplay = 1280, 4294 .hsync_start = 1280 + 192, 4295 .hsync_end = 1280 + 192 + 128, 4296 .htotal = 1280 + 192 + 128 + 64, 4297 .vdisplay = 768, 4298 .vsync_start = 768 + 20, 4299 .vsync_end = 768 + 20 + 7, 4300 .vtotal = 768 + 20 + 7 + 3, 4301 }; 4302 4303 static const struct panel_desc toshiba_lt089ac29000 = { 4304 .modes = &toshiba_lt089ac29000_mode, 4305 .num_modes = 1, 4306 .size = { 4307 .width = 194, 4308 .height = 116, 4309 }, 4310 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4311 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4312 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4313 }; 4314 4315 static const struct drm_display_mode tpk_f07a_0102_mode = { 4316 .clock = 33260, 4317 .hdisplay = 800, 4318 .hsync_start = 800 + 40, 4319 .hsync_end = 800 + 40 + 128, 4320 .htotal = 800 + 40 + 128 + 88, 4321 .vdisplay = 480, 4322 .vsync_start = 480 + 10, 4323 .vsync_end = 480 + 10 + 2, 4324 .vtotal = 480 + 10 + 2 + 33, 4325 }; 4326 4327 static const struct panel_desc tpk_f07a_0102 = { 4328 .modes = &tpk_f07a_0102_mode, 4329 .num_modes = 1, 4330 .size = { 4331 .width = 152, 4332 .height = 91, 4333 }, 4334 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4335 }; 4336 4337 static const struct drm_display_mode tpk_f10a_0102_mode = { 4338 .clock = 45000, 4339 .hdisplay = 1024, 4340 .hsync_start = 1024 + 176, 4341 .hsync_end = 1024 + 176 + 5, 4342 .htotal = 1024 + 176 + 5 + 88, 4343 .vdisplay = 600, 4344 .vsync_start = 600 + 20, 4345 .vsync_end = 600 + 20 + 5, 4346 .vtotal = 600 + 20 + 5 + 25, 4347 }; 4348 4349 static const struct panel_desc tpk_f10a_0102 = { 4350 .modes = &tpk_f10a_0102_mode, 4351 .num_modes = 1, 4352 .size = { 4353 .width = 223, 4354 .height = 125, 4355 }, 4356 }; 4357 4358 static const struct display_timing urt_umsh_8596md_timing = { 4359 .pixelclock = { 33260000, 33260000, 33260000 }, 4360 .hactive = { 800, 800, 800 }, 4361 .hfront_porch = { 41, 41, 41 }, 4362 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4363 .hsync_len = { 71, 128, 128 }, 4364 .vactive = { 480, 480, 480 }, 4365 .vfront_porch = { 10, 10, 10 }, 4366 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4367 .vsync_len = { 2, 2, 2 }, 4368 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4369 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4370 }; 4371 4372 static const struct panel_desc urt_umsh_8596md_lvds = { 4373 .timings = &urt_umsh_8596md_timing, 4374 .num_timings = 1, 4375 .bpc = 6, 4376 .size = { 4377 .width = 152, 4378 .height = 91, 4379 }, 4380 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4381 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4382 }; 4383 4384 static const struct panel_desc urt_umsh_8596md_parallel = { 4385 .timings = &urt_umsh_8596md_timing, 4386 .num_timings = 1, 4387 .bpc = 6, 4388 .size = { 4389 .width = 152, 4390 .height = 91, 4391 }, 4392 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4393 }; 4394 4395 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4396 .clock = 60000, 4397 .hdisplay = 1024, 4398 .hsync_start = 1024 + 160, 4399 .hsync_end = 1024 + 160 + 100, 4400 .htotal = 1024 + 160 + 100 + 60, 4401 .vdisplay = 600, 4402 .vsync_start = 600 + 12, 4403 .vsync_end = 600 + 12 + 10, 4404 .vtotal = 600 + 12 + 10 + 13, 4405 }; 4406 4407 static const struct panel_desc vivax_tpc9150_panel = { 4408 .modes = &vivax_tpc9150_panel_mode, 4409 .num_modes = 1, 4410 .bpc = 6, 4411 .size = { 4412 .width = 200, 4413 .height = 115, 4414 }, 4415 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4416 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4417 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4418 }; 4419 4420 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4421 .clock = 33333, 4422 .hdisplay = 800, 4423 .hsync_start = 800 + 210, 4424 .hsync_end = 800 + 210 + 20, 4425 .htotal = 800 + 210 + 20 + 46, 4426 .vdisplay = 480, 4427 .vsync_start = 480 + 22, 4428 .vsync_end = 480 + 22 + 10, 4429 .vtotal = 480 + 22 + 10 + 23, 4430 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4431 }; 4432 4433 static const struct panel_desc vl050_8048nt_c01 = { 4434 .modes = &vl050_8048nt_c01_mode, 4435 .num_modes = 1, 4436 .bpc = 8, 4437 .size = { 4438 .width = 120, 4439 .height = 76, 4440 }, 4441 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4442 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4443 }; 4444 4445 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4446 .clock = 6410, 4447 .hdisplay = 320, 4448 .hsync_start = 320 + 20, 4449 .hsync_end = 320 + 20 + 30, 4450 .htotal = 320 + 20 + 30 + 38, 4451 .vdisplay = 240, 4452 .vsync_start = 240 + 4, 4453 .vsync_end = 240 + 4 + 3, 4454 .vtotal = 240 + 4 + 3 + 15, 4455 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4456 }; 4457 4458 static const struct panel_desc winstar_wf35ltiacd = { 4459 .modes = &winstar_wf35ltiacd_mode, 4460 .num_modes = 1, 4461 .bpc = 8, 4462 .size = { 4463 .width = 70, 4464 .height = 53, 4465 }, 4466 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4467 }; 4468 4469 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4470 .clock = 51200, 4471 .hdisplay = 1024, 4472 .hsync_start = 1024 + 100, 4473 .hsync_end = 1024 + 100 + 100, 4474 .htotal = 1024 + 100 + 100 + 120, 4475 .vdisplay = 600, 4476 .vsync_start = 600 + 10, 4477 .vsync_end = 600 + 10 + 10, 4478 .vtotal = 600 + 10 + 10 + 15, 4479 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4480 }; 4481 4482 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4483 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4484 .num_modes = 1, 4485 .bpc = 8, 4486 .size = { 4487 .width = 154, 4488 .height = 90, 4489 }, 4490 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4491 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4492 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4493 }; 4494 4495 static const struct drm_display_mode arm_rtsm_mode[] = { 4496 { 4497 .clock = 65000, 4498 .hdisplay = 1024, 4499 .hsync_start = 1024 + 24, 4500 .hsync_end = 1024 + 24 + 136, 4501 .htotal = 1024 + 24 + 136 + 160, 4502 .vdisplay = 768, 4503 .vsync_start = 768 + 3, 4504 .vsync_end = 768 + 3 + 6, 4505 .vtotal = 768 + 3 + 6 + 29, 4506 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4507 }, 4508 }; 4509 4510 static const struct panel_desc arm_rtsm = { 4511 .modes = arm_rtsm_mode, 4512 .num_modes = 1, 4513 .bpc = 8, 4514 .size = { 4515 .width = 400, 4516 .height = 300, 4517 }, 4518 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4519 }; 4520 4521 static const struct of_device_id platform_of_match[] = { 4522 { 4523 .compatible = "ampire,am-1280800n3tzqw-t00h", 4524 .data = &ire_am_1280800n3tzqw_t00h, 4525 }, { 4526 .compatible = "ampire,am-480272h3tmqw-t01h", 4527 .data = &ire_am_480272h3tmqw_t01h, 4528 }, { 4529 .compatible = "ampire,am-800480l1tmqw-t00h", 4530 .data = &ire_am_800480l1tmqw_t00h, 4531 }, { 4532 .compatible = "ampire,am800480r3tmqwa1h", 4533 .data = &ire_am800480r3tmqwa1h, 4534 }, { 4535 .compatible = "ampire,am800600p5tmqw-tb8h", 4536 .data = &ire_am800600p5tmqwtb8h, 4537 }, { 4538 .compatible = "arm,rtsm-display", 4539 .data = &arm_rtsm, 4540 }, { 4541 .compatible = "armadeus,st0700-adapt", 4542 .data = &armadeus_st0700_adapt, 4543 }, { 4544 .compatible = "auo,b101aw03", 4545 .data = &auo_b101aw03, 4546 }, { 4547 .compatible = "auo,b101xtn01", 4548 .data = &auo_b101xtn01, 4549 }, { 4550 .compatible = "auo,b116xw03", 4551 .data = &auo_b116xw03, 4552 }, { 4553 .compatible = "auo,g070vvn01", 4554 .data = &auo_g070vvn01, 4555 }, { 4556 .compatible = "auo,g101evn010", 4557 .data = &auo_g101evn010, 4558 }, { 4559 .compatible = "auo,g104sn02", 4560 .data = &auo_g104sn02, 4561 }, { 4562 .compatible = "auo,g104stn01", 4563 .data = &auo_g104stn01, 4564 }, { 4565 .compatible = "auo,g121ean01", 4566 .data = &auo_g121ean01, 4567 }, { 4568 .compatible = "auo,g133han01", 4569 .data = &auo_g133han01, 4570 }, { 4571 .compatible = "auo,g156han04", 4572 .data = &auo_g156han04, 4573 }, { 4574 .compatible = "auo,g156xtn01", 4575 .data = &auo_g156xtn01, 4576 }, { 4577 .compatible = "auo,g185han01", 4578 .data = &auo_g185han01, 4579 }, { 4580 .compatible = "auo,g190ean01", 4581 .data = &auo_g190ean01, 4582 }, { 4583 .compatible = "auo,p320hvn03", 4584 .data = &auo_p320hvn03, 4585 }, { 4586 .compatible = "auo,t215hvn01", 4587 .data = &auo_t215hvn01, 4588 }, { 4589 .compatible = "avic,tm070ddh03", 4590 .data = &avic_tm070ddh03, 4591 }, { 4592 .compatible = "bananapi,s070wv20-ct16", 4593 .data = &bananapi_s070wv20_ct16, 4594 }, { 4595 .compatible = "boe,bp082wx1-100", 4596 .data = &boe_bp082wx1_100, 4597 }, { 4598 .compatible = "boe,bp101wx1-100", 4599 .data = &boe_bp101wx1_100, 4600 }, { 4601 .compatible = "boe,ev121wxm-n10-1850", 4602 .data = &boe_ev121wxm_n10_1850, 4603 }, { 4604 .compatible = "boe,hv070wsa-100", 4605 .data = &boe_hv070wsa 4606 }, { 4607 .compatible = "cct,cmt430b19n00", 4608 .data = &cct_cmt430b19n00, 4609 }, { 4610 .compatible = "cdtech,s043wq26h-ct7", 4611 .data = &cdtech_s043wq26h_ct7, 4612 }, { 4613 .compatible = "cdtech,s070pws19hp-fc21", 4614 .data = &cdtech_s070pws19hp_fc21, 4615 }, { 4616 .compatible = "cdtech,s070swv29hg-dc44", 4617 .data = &cdtech_s070swv29hg_dc44, 4618 }, { 4619 .compatible = "cdtech,s070wv95-ct16", 4620 .data = &cdtech_s070wv95_ct16, 4621 }, { 4622 .compatible = "chefree,ch101olhlwh-002", 4623 .data = &chefree_ch101olhlwh_002, 4624 }, { 4625 .compatible = "chunghwa,claa070wp03xg", 4626 .data = &chunghwa_claa070wp03xg, 4627 }, { 4628 .compatible = "chunghwa,claa101wa01a", 4629 .data = &chunghwa_claa101wa01a 4630 }, { 4631 .compatible = "chunghwa,claa101wb01", 4632 .data = &chunghwa_claa101wb01 4633 }, { 4634 .compatible = "dataimage,fg040346dsswbg04", 4635 .data = &dataimage_fg040346dsswbg04, 4636 }, { 4637 .compatible = "dataimage,fg1001l0dsswmg01", 4638 .data = &dataimage_fg1001l0dsswmg01, 4639 }, { 4640 .compatible = "dataimage,scf0700c48ggu18", 4641 .data = &dataimage_scf0700c48ggu18, 4642 }, { 4643 .compatible = "dlc,dlc0700yzg-1", 4644 .data = &dlc_dlc0700yzg_1, 4645 }, { 4646 .compatible = "dlc,dlc1010gig", 4647 .data = &dlc_dlc1010gig, 4648 }, { 4649 .compatible = "edt,et035012dm6", 4650 .data = &edt_et035012dm6, 4651 }, { 4652 .compatible = "edt,etm0350g0dh6", 4653 .data = &edt_etm0350g0dh6, 4654 }, { 4655 .compatible = "edt,etm043080dh6gp", 4656 .data = &edt_etm043080dh6gp, 4657 }, { 4658 .compatible = "edt,etm0430g0dh6", 4659 .data = &edt_etm0430g0dh6, 4660 }, { 4661 .compatible = "edt,et057090dhu", 4662 .data = &edt_et057090dhu, 4663 }, { 4664 .compatible = "edt,et070080dh6", 4665 .data = &edt_etm0700g0dh6, 4666 }, { 4667 .compatible = "edt,etm0700g0dh6", 4668 .data = &edt_etm0700g0dh6, 4669 }, { 4670 .compatible = "edt,etm0700g0bdh6", 4671 .data = &edt_etm0700g0bdh6, 4672 }, { 4673 .compatible = "edt,etm0700g0edh6", 4674 .data = &edt_etm0700g0bdh6, 4675 }, { 4676 .compatible = "edt,etml0700y5dha", 4677 .data = &edt_etml0700y5dha, 4678 }, { 4679 .compatible = "edt,etml1010g3dra", 4680 .data = &edt_etml1010g3dra, 4681 }, { 4682 .compatible = "edt,etmv570g2dhu", 4683 .data = &edt_etmv570g2dhu, 4684 }, { 4685 .compatible = "eink,vb3300-kca", 4686 .data = &eink_vb3300_kca, 4687 }, { 4688 .compatible = "evervision,vgg644804", 4689 .data = &evervision_vgg644804, 4690 }, { 4691 .compatible = "evervision,vgg804821", 4692 .data = &evervision_vgg804821, 4693 }, { 4694 .compatible = "foxlink,fl500wvr00-a0t", 4695 .data = &foxlink_fl500wvr00_a0t, 4696 }, { 4697 .compatible = "frida,frd350h54004", 4698 .data = &frida_frd350h54004, 4699 }, { 4700 .compatible = "friendlyarm,hd702e", 4701 .data = &friendlyarm_hd702e, 4702 }, { 4703 .compatible = "giantplus,gpg482739qs5", 4704 .data = &giantplus_gpg482739qs5 4705 }, { 4706 .compatible = "giantplus,gpm940b0", 4707 .data = &giantplus_gpm940b0, 4708 }, { 4709 .compatible = "hannstar,hsd070pww1", 4710 .data = &hannstar_hsd070pww1, 4711 }, { 4712 .compatible = "hannstar,hsd100pxn1", 4713 .data = &hannstar_hsd100pxn1, 4714 }, { 4715 .compatible = "hannstar,hsd101pww2", 4716 .data = &hannstar_hsd101pww2, 4717 }, { 4718 .compatible = "hit,tx23d38vm0caa", 4719 .data = &hitachi_tx23d38vm0caa 4720 }, { 4721 .compatible = "innolux,at043tn24", 4722 .data = &innolux_at043tn24, 4723 }, { 4724 .compatible = "innolux,at070tn92", 4725 .data = &innolux_at070tn92, 4726 }, { 4727 .compatible = "innolux,g070ace-l01", 4728 .data = &innolux_g070ace_l01, 4729 }, { 4730 .compatible = "innolux,g070y2-l01", 4731 .data = &innolux_g070y2_l01, 4732 }, { 4733 .compatible = "innolux,g070y2-t02", 4734 .data = &innolux_g070y2_t02, 4735 }, { 4736 .compatible = "innolux,g101ice-l01", 4737 .data = &innolux_g101ice_l01 4738 }, { 4739 .compatible = "innolux,g121i1-l01", 4740 .data = &innolux_g121i1_l01 4741 }, { 4742 .compatible = "innolux,g121x1-l03", 4743 .data = &innolux_g121x1_l03, 4744 }, { 4745 .compatible = "innolux,g121xce-l01", 4746 .data = &innolux_g121xce_l01, 4747 }, { 4748 .compatible = "innolux,g156hce-l01", 4749 .data = &innolux_g156hce_l01, 4750 }, { 4751 .compatible = "innolux,n156bge-l21", 4752 .data = &innolux_n156bge_l21, 4753 }, { 4754 .compatible = "innolux,zj070na-01p", 4755 .data = &innolux_zj070na_01p, 4756 }, { 4757 .compatible = "koe,tx14d24vm1bpa", 4758 .data = &koe_tx14d24vm1bpa, 4759 }, { 4760 .compatible = "koe,tx26d202vm0bwa", 4761 .data = &koe_tx26d202vm0bwa, 4762 }, { 4763 .compatible = "koe,tx31d200vm0baa", 4764 .data = &koe_tx31d200vm0baa, 4765 }, { 4766 .compatible = "kyo,tcg121xglp", 4767 .data = &kyo_tcg121xglp, 4768 }, { 4769 .compatible = "lemaker,bl035-rgb-002", 4770 .data = &lemaker_bl035_rgb_002, 4771 }, { 4772 .compatible = "lg,lb070wv8", 4773 .data = &lg_lb070wv8, 4774 }, { 4775 .compatible = "lincolntech,lcd185-101ct", 4776 .data = &lincolntech_lcd185_101ct, 4777 }, { 4778 .compatible = "logicpd,type28", 4779 .data = &logicpd_type_28, 4780 }, { 4781 .compatible = "logictechno,lt161010-2nhc", 4782 .data = &logictechno_lt161010_2nh, 4783 }, { 4784 .compatible = "logictechno,lt161010-2nhr", 4785 .data = &logictechno_lt161010_2nh, 4786 }, { 4787 .compatible = "logictechno,lt170410-2whc", 4788 .data = &logictechno_lt170410_2whc, 4789 }, { 4790 .compatible = "logictechno,lttd800480070-l2rt", 4791 .data = &logictechno_lttd800480070_l2rt, 4792 }, { 4793 .compatible = "logictechno,lttd800480070-l6wh-rt", 4794 .data = &logictechno_lttd800480070_l6wh_rt, 4795 }, { 4796 .compatible = "microtips,mf-101hiebcaf0", 4797 .data = µtips_mf_101hiebcaf0_c, 4798 }, { 4799 .compatible = "microtips,mf-103hieb0ga0", 4800 .data = µtips_mf_103hieb0ga0, 4801 }, { 4802 .compatible = "mitsubishi,aa070mc01-ca1", 4803 .data = &mitsubishi_aa070mc01, 4804 }, { 4805 .compatible = "mitsubishi,aa084xe01", 4806 .data = &mitsubishi_aa084xe01, 4807 }, { 4808 .compatible = "multi-inno,mi0700s4t-6", 4809 .data = &multi_inno_mi0700s4t_6, 4810 }, { 4811 .compatible = "multi-inno,mi0800ft-9", 4812 .data = &multi_inno_mi0800ft_9, 4813 }, { 4814 .compatible = "multi-inno,mi1010ait-1cp", 4815 .data = &multi_inno_mi1010ait_1cp, 4816 }, { 4817 .compatible = "nec,nl12880bc20-05", 4818 .data = &nec_nl12880bc20_05, 4819 }, { 4820 .compatible = "nec,nl4827hc19-05b", 4821 .data = &nec_nl4827hc19_05b, 4822 }, { 4823 .compatible = "netron-dy,e231732", 4824 .data = &netron_dy_e231732, 4825 }, { 4826 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4827 .data = &newhaven_nhd_43_480272ef_atxl, 4828 }, { 4829 .compatible = "nlt,nl192108ac18-02d", 4830 .data = &nlt_nl192108ac18_02d, 4831 }, { 4832 .compatible = "nvd,9128", 4833 .data = &nvd_9128, 4834 }, { 4835 .compatible = "okaya,rs800480t-7x0gp", 4836 .data = &okaya_rs800480t_7x0gp, 4837 }, { 4838 .compatible = "olimex,lcd-olinuxino-43-ts", 4839 .data = &olimex_lcd_olinuxino_43ts, 4840 }, { 4841 .compatible = "ontat,yx700wv03", 4842 .data = &ontat_yx700wv03, 4843 }, { 4844 .compatible = "ortustech,com37h3m05dtc", 4845 .data = &ortustech_com37h3m, 4846 }, { 4847 .compatible = "ortustech,com37h3m99dtc", 4848 .data = &ortustech_com37h3m, 4849 }, { 4850 .compatible = "ortustech,com43h4m85ulc", 4851 .data = &ortustech_com43h4m85ulc, 4852 }, { 4853 .compatible = "osddisplays,osd070t1718-19ts", 4854 .data = &osddisplays_osd070t1718_19ts, 4855 }, { 4856 .compatible = "pda,91-00156-a0", 4857 .data = &pda_91_00156_a0, 4858 }, { 4859 .compatible = "powertip,ph128800t006-zhc01", 4860 .data = &powertip_ph128800t006_zhc01, 4861 }, { 4862 .compatible = "powertip,ph800480t013-idf02", 4863 .data = &powertip_ph800480t013_idf02, 4864 }, { 4865 .compatible = "primeview,pm070wl4", 4866 .data = &primeview_pm070wl4, 4867 }, { 4868 .compatible = "qiaodian,qd43003c0-40", 4869 .data = &qd43003c0_40, 4870 }, { 4871 .compatible = "qishenglong,gopher2b-lcd", 4872 .data = &qishenglong_gopher2b_lcd, 4873 }, { 4874 .compatible = "rocktech,rk043fn48h", 4875 .data = &rocktech_rk043fn48h, 4876 }, { 4877 .compatible = "rocktech,rk070er9427", 4878 .data = &rocktech_rk070er9427, 4879 }, { 4880 .compatible = "rocktech,rk101ii01d-ct", 4881 .data = &rocktech_rk101ii01d_ct, 4882 }, { 4883 .compatible = "samsung,ltl101al01", 4884 .data = &samsung_ltl101al01, 4885 }, { 4886 .compatible = "samsung,ltn101nt05", 4887 .data = &samsung_ltn101nt05, 4888 }, { 4889 .compatible = "satoz,sat050at40h12r2", 4890 .data = &satoz_sat050at40h12r2, 4891 }, { 4892 .compatible = "sharp,lq035q7db03", 4893 .data = &sharp_lq035q7db03, 4894 }, { 4895 .compatible = "sharp,lq070y3dg3b", 4896 .data = &sharp_lq070y3dg3b, 4897 }, { 4898 .compatible = "sharp,lq101k1ly04", 4899 .data = &sharp_lq101k1ly04, 4900 }, { 4901 .compatible = "sharp,ls020b1dd01d", 4902 .data = &sharp_ls020b1dd01d, 4903 }, { 4904 .compatible = "shelly,sca07010-bfn-lnn", 4905 .data = &shelly_sca07010_bfn_lnn, 4906 }, { 4907 .compatible = "starry,kr070pe2t", 4908 .data = &starry_kr070pe2t, 4909 }, { 4910 .compatible = "startek,kd070wvfpa", 4911 .data = &startek_kd070wvfpa, 4912 }, { 4913 .compatible = "team-source-display,tst043015cmhx", 4914 .data = &tsd_tst043015cmhx, 4915 }, { 4916 .compatible = "tfc,s9700rtwv43tr-01b", 4917 .data = &tfc_s9700rtwv43tr_01b, 4918 }, { 4919 .compatible = "tianma,tm070jdhg30", 4920 .data = &tianma_tm070jdhg30, 4921 }, { 4922 .compatible = "tianma,tm070jvhg33", 4923 .data = &tianma_tm070jvhg33, 4924 }, { 4925 .compatible = "tianma,tm070rvhg71", 4926 .data = &tianma_tm070rvhg71, 4927 }, { 4928 .compatible = "ti,nspire-cx-lcd-panel", 4929 .data = &ti_nspire_cx_lcd_panel, 4930 }, { 4931 .compatible = "ti,nspire-classic-lcd-panel", 4932 .data = &ti_nspire_classic_lcd_panel, 4933 }, { 4934 .compatible = "toshiba,lt089ac29000", 4935 .data = &toshiba_lt089ac29000, 4936 }, { 4937 .compatible = "tpk,f07a-0102", 4938 .data = &tpk_f07a_0102, 4939 }, { 4940 .compatible = "tpk,f10a-0102", 4941 .data = &tpk_f10a_0102, 4942 }, { 4943 .compatible = "urt,umsh-8596md-t", 4944 .data = &urt_umsh_8596md_parallel, 4945 }, { 4946 .compatible = "urt,umsh-8596md-1t", 4947 .data = &urt_umsh_8596md_parallel, 4948 }, { 4949 .compatible = "urt,umsh-8596md-7t", 4950 .data = &urt_umsh_8596md_parallel, 4951 }, { 4952 .compatible = "urt,umsh-8596md-11t", 4953 .data = &urt_umsh_8596md_lvds, 4954 }, { 4955 .compatible = "urt,umsh-8596md-19t", 4956 .data = &urt_umsh_8596md_lvds, 4957 }, { 4958 .compatible = "urt,umsh-8596md-20t", 4959 .data = &urt_umsh_8596md_parallel, 4960 }, { 4961 .compatible = "vivax,tpc9150-panel", 4962 .data = &vivax_tpc9150_panel, 4963 }, { 4964 .compatible = "vxt,vl050-8048nt-c01", 4965 .data = &vl050_8048nt_c01, 4966 }, { 4967 .compatible = "winstar,wf35ltiacd", 4968 .data = &winstar_wf35ltiacd, 4969 }, { 4970 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4971 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4972 }, { 4973 /* Must be the last entry */ 4974 .compatible = "panel-dpi", 4975 .data = &panel_dpi, 4976 }, { 4977 /* sentinel */ 4978 } 4979 }; 4980 MODULE_DEVICE_TABLE(of, platform_of_match); 4981 4982 static int panel_simple_platform_probe(struct platform_device *pdev) 4983 { 4984 const struct panel_desc *desc; 4985 4986 desc = of_device_get_match_data(&pdev->dev); 4987 if (!desc) 4988 return -ENODEV; 4989 4990 return panel_simple_probe(&pdev->dev, desc); 4991 } 4992 4993 static void panel_simple_platform_remove(struct platform_device *pdev) 4994 { 4995 panel_simple_remove(&pdev->dev); 4996 } 4997 4998 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4999 { 5000 panel_simple_shutdown(&pdev->dev); 5001 } 5002 5003 static const struct dev_pm_ops panel_simple_pm_ops = { 5004 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 5005 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5006 pm_runtime_force_resume) 5007 }; 5008 5009 static struct platform_driver panel_simple_platform_driver = { 5010 .driver = { 5011 .name = "panel-simple", 5012 .of_match_table = platform_of_match, 5013 .pm = &panel_simple_pm_ops, 5014 }, 5015 .probe = panel_simple_platform_probe, 5016 .remove_new = panel_simple_platform_remove, 5017 .shutdown = panel_simple_platform_shutdown, 5018 }; 5019 5020 struct panel_desc_dsi { 5021 struct panel_desc desc; 5022 5023 unsigned long flags; 5024 enum mipi_dsi_pixel_format format; 5025 unsigned int lanes; 5026 }; 5027 5028 static const struct drm_display_mode auo_b080uan01_mode = { 5029 .clock = 154500, 5030 .hdisplay = 1200, 5031 .hsync_start = 1200 + 62, 5032 .hsync_end = 1200 + 62 + 4, 5033 .htotal = 1200 + 62 + 4 + 62, 5034 .vdisplay = 1920, 5035 .vsync_start = 1920 + 9, 5036 .vsync_end = 1920 + 9 + 2, 5037 .vtotal = 1920 + 9 + 2 + 8, 5038 }; 5039 5040 static const struct panel_desc_dsi auo_b080uan01 = { 5041 .desc = { 5042 .modes = &auo_b080uan01_mode, 5043 .num_modes = 1, 5044 .bpc = 8, 5045 .size = { 5046 .width = 108, 5047 .height = 272, 5048 }, 5049 .connector_type = DRM_MODE_CONNECTOR_DSI, 5050 }, 5051 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5052 .format = MIPI_DSI_FMT_RGB888, 5053 .lanes = 4, 5054 }; 5055 5056 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5057 .clock = 160000, 5058 .hdisplay = 1200, 5059 .hsync_start = 1200 + 120, 5060 .hsync_end = 1200 + 120 + 20, 5061 .htotal = 1200 + 120 + 20 + 21, 5062 .vdisplay = 1920, 5063 .vsync_start = 1920 + 21, 5064 .vsync_end = 1920 + 21 + 3, 5065 .vtotal = 1920 + 21 + 3 + 18, 5066 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5067 }; 5068 5069 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5070 .desc = { 5071 .modes = &boe_tv080wum_nl0_mode, 5072 .num_modes = 1, 5073 .size = { 5074 .width = 107, 5075 .height = 172, 5076 }, 5077 .connector_type = DRM_MODE_CONNECTOR_DSI, 5078 }, 5079 .flags = MIPI_DSI_MODE_VIDEO | 5080 MIPI_DSI_MODE_VIDEO_BURST | 5081 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5082 .format = MIPI_DSI_FMT_RGB888, 5083 .lanes = 4, 5084 }; 5085 5086 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 5087 .clock = 71000, 5088 .hdisplay = 800, 5089 .hsync_start = 800 + 32, 5090 .hsync_end = 800 + 32 + 1, 5091 .htotal = 800 + 32 + 1 + 57, 5092 .vdisplay = 1280, 5093 .vsync_start = 1280 + 28, 5094 .vsync_end = 1280 + 28 + 1, 5095 .vtotal = 1280 + 28 + 1 + 14, 5096 }; 5097 5098 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 5099 .desc = { 5100 .modes = &lg_ld070wx3_sl01_mode, 5101 .num_modes = 1, 5102 .bpc = 8, 5103 .size = { 5104 .width = 94, 5105 .height = 151, 5106 }, 5107 .connector_type = DRM_MODE_CONNECTOR_DSI, 5108 }, 5109 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5110 .format = MIPI_DSI_FMT_RGB888, 5111 .lanes = 4, 5112 }; 5113 5114 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5115 .clock = 67000, 5116 .hdisplay = 720, 5117 .hsync_start = 720 + 12, 5118 .hsync_end = 720 + 12 + 4, 5119 .htotal = 720 + 12 + 4 + 112, 5120 .vdisplay = 1280, 5121 .vsync_start = 1280 + 8, 5122 .vsync_end = 1280 + 8 + 4, 5123 .vtotal = 1280 + 8 + 4 + 12, 5124 }; 5125 5126 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5127 .desc = { 5128 .modes = &lg_lh500wx1_sd03_mode, 5129 .num_modes = 1, 5130 .bpc = 8, 5131 .size = { 5132 .width = 62, 5133 .height = 110, 5134 }, 5135 .connector_type = DRM_MODE_CONNECTOR_DSI, 5136 }, 5137 .flags = MIPI_DSI_MODE_VIDEO, 5138 .format = MIPI_DSI_FMT_RGB888, 5139 .lanes = 4, 5140 }; 5141 5142 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5143 .clock = 157200, 5144 .hdisplay = 1920, 5145 .hsync_start = 1920 + 154, 5146 .hsync_end = 1920 + 154 + 16, 5147 .htotal = 1920 + 154 + 16 + 32, 5148 .vdisplay = 1200, 5149 .vsync_start = 1200 + 17, 5150 .vsync_end = 1200 + 17 + 2, 5151 .vtotal = 1200 + 17 + 2 + 16, 5152 }; 5153 5154 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5155 .desc = { 5156 .modes = &panasonic_vvx10f004b00_mode, 5157 .num_modes = 1, 5158 .bpc = 8, 5159 .size = { 5160 .width = 217, 5161 .height = 136, 5162 }, 5163 .connector_type = DRM_MODE_CONNECTOR_DSI, 5164 }, 5165 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5166 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5167 .format = MIPI_DSI_FMT_RGB888, 5168 .lanes = 4, 5169 }; 5170 5171 static const struct drm_display_mode lg_acx467akm_7_mode = { 5172 .clock = 150000, 5173 .hdisplay = 1080, 5174 .hsync_start = 1080 + 2, 5175 .hsync_end = 1080 + 2 + 2, 5176 .htotal = 1080 + 2 + 2 + 2, 5177 .vdisplay = 1920, 5178 .vsync_start = 1920 + 2, 5179 .vsync_end = 1920 + 2 + 2, 5180 .vtotal = 1920 + 2 + 2 + 2, 5181 }; 5182 5183 static const struct panel_desc_dsi lg_acx467akm_7 = { 5184 .desc = { 5185 .modes = &lg_acx467akm_7_mode, 5186 .num_modes = 1, 5187 .bpc = 8, 5188 .size = { 5189 .width = 62, 5190 .height = 110, 5191 }, 5192 .connector_type = DRM_MODE_CONNECTOR_DSI, 5193 }, 5194 .flags = 0, 5195 .format = MIPI_DSI_FMT_RGB888, 5196 .lanes = 4, 5197 }; 5198 5199 static const struct drm_display_mode osd101t2045_53ts_mode = { 5200 .clock = 154500, 5201 .hdisplay = 1920, 5202 .hsync_start = 1920 + 112, 5203 .hsync_end = 1920 + 112 + 16, 5204 .htotal = 1920 + 112 + 16 + 32, 5205 .vdisplay = 1200, 5206 .vsync_start = 1200 + 16, 5207 .vsync_end = 1200 + 16 + 2, 5208 .vtotal = 1200 + 16 + 2 + 16, 5209 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5210 }; 5211 5212 static const struct panel_desc_dsi osd101t2045_53ts = { 5213 .desc = { 5214 .modes = &osd101t2045_53ts_mode, 5215 .num_modes = 1, 5216 .bpc = 8, 5217 .size = { 5218 .width = 217, 5219 .height = 136, 5220 }, 5221 .connector_type = DRM_MODE_CONNECTOR_DSI, 5222 }, 5223 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5224 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5225 MIPI_DSI_MODE_NO_EOT_PACKET, 5226 .format = MIPI_DSI_FMT_RGB888, 5227 .lanes = 4, 5228 }; 5229 5230 static const struct of_device_id dsi_of_match[] = { 5231 { 5232 .compatible = "auo,b080uan01", 5233 .data = &auo_b080uan01 5234 }, { 5235 .compatible = "boe,tv080wum-nl0", 5236 .data = &boe_tv080wum_nl0 5237 }, { 5238 .compatible = "lg,ld070wx3-sl01", 5239 .data = &lg_ld070wx3_sl01 5240 }, { 5241 .compatible = "lg,lh500wx1-sd03", 5242 .data = &lg_lh500wx1_sd03 5243 }, { 5244 .compatible = "panasonic,vvx10f004b00", 5245 .data = &panasonic_vvx10f004b00 5246 }, { 5247 .compatible = "lg,acx467akm-7", 5248 .data = &lg_acx467akm_7 5249 }, { 5250 .compatible = "osddisplays,osd101t2045-53ts", 5251 .data = &osd101t2045_53ts 5252 }, { 5253 /* sentinel */ 5254 } 5255 }; 5256 MODULE_DEVICE_TABLE(of, dsi_of_match); 5257 5258 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5259 { 5260 const struct panel_desc_dsi *desc; 5261 int err; 5262 5263 desc = of_device_get_match_data(&dsi->dev); 5264 if (!desc) 5265 return -ENODEV; 5266 5267 err = panel_simple_probe(&dsi->dev, &desc->desc); 5268 if (err < 0) 5269 return err; 5270 5271 dsi->mode_flags = desc->flags; 5272 dsi->format = desc->format; 5273 dsi->lanes = desc->lanes; 5274 5275 err = mipi_dsi_attach(dsi); 5276 if (err) { 5277 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5278 5279 drm_panel_remove(&panel->base); 5280 } 5281 5282 return err; 5283 } 5284 5285 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5286 { 5287 int err; 5288 5289 err = mipi_dsi_detach(dsi); 5290 if (err < 0) 5291 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5292 5293 panel_simple_remove(&dsi->dev); 5294 } 5295 5296 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5297 { 5298 panel_simple_shutdown(&dsi->dev); 5299 } 5300 5301 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5302 .driver = { 5303 .name = "panel-simple-dsi", 5304 .of_match_table = dsi_of_match, 5305 .pm = &panel_simple_pm_ops, 5306 }, 5307 .probe = panel_simple_dsi_probe, 5308 .remove = panel_simple_dsi_remove, 5309 .shutdown = panel_simple_dsi_shutdown, 5310 }; 5311 5312 static int __init panel_simple_init(void) 5313 { 5314 int err; 5315 5316 err = platform_driver_register(&panel_simple_platform_driver); 5317 if (err < 0) 5318 return err; 5319 5320 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5321 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5322 if (err < 0) 5323 goto err_did_platform_register; 5324 } 5325 5326 return 0; 5327 5328 err_did_platform_register: 5329 platform_driver_unregister(&panel_simple_platform_driver); 5330 5331 return err; 5332 } 5333 module_init(panel_simple_init); 5334 5335 static void __exit panel_simple_exit(void) 5336 { 5337 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5338 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5339 5340 platform_driver_unregister(&panel_simple_platform_driver); 5341 } 5342 module_exit(panel_simple_exit); 5343 5344 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5345 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5346 MODULE_LICENSE("GPL and additional rights"); 5347