1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 142 ktime_t unprepared_time; 143 144 const struct panel_desc *desc; 145 146 struct regulator *supply; 147 struct i2c_adapter *ddc; 148 149 struct gpio_desc *enable_gpio; 150 151 const struct drm_edid *drm_edid; 152 153 struct drm_display_mode override_mode; 154 155 enum drm_panel_orientation orientation; 156 }; 157 158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 159 { 160 return container_of(panel, struct panel_simple, base); 161 } 162 163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 164 struct drm_connector *connector) 165 { 166 struct drm_display_mode *mode; 167 unsigned int i, num = 0; 168 169 for (i = 0; i < panel->desc->num_timings; i++) { 170 const struct display_timing *dt = &panel->desc->timings[i]; 171 struct videomode vm; 172 173 videomode_from_timing(dt, &vm); 174 mode = drm_mode_create(connector->dev); 175 if (!mode) { 176 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 177 dt->hactive.typ, dt->vactive.typ); 178 continue; 179 } 180 181 drm_display_mode_from_videomode(&vm, mode); 182 183 mode->type |= DRM_MODE_TYPE_DRIVER; 184 185 if (panel->desc->num_timings == 1) 186 mode->type |= DRM_MODE_TYPE_PREFERRED; 187 188 drm_mode_probed_add(connector, mode); 189 num++; 190 } 191 192 return num; 193 } 194 195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 196 struct drm_connector *connector) 197 { 198 struct drm_display_mode *mode; 199 unsigned int i, num = 0; 200 201 for (i = 0; i < panel->desc->num_modes; i++) { 202 const struct drm_display_mode *m = &panel->desc->modes[i]; 203 204 mode = drm_mode_duplicate(connector->dev, m); 205 if (!mode) { 206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 207 m->hdisplay, m->vdisplay, 208 drm_mode_vrefresh(m)); 209 continue; 210 } 211 212 mode->type |= DRM_MODE_TYPE_DRIVER; 213 214 if (panel->desc->num_modes == 1) 215 mode->type |= DRM_MODE_TYPE_PREFERRED; 216 217 drm_mode_set_name(mode); 218 219 drm_mode_probed_add(connector, mode); 220 num++; 221 } 222 223 return num; 224 } 225 226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 227 struct drm_connector *connector) 228 { 229 struct drm_display_mode *mode; 230 bool has_override = panel->override_mode.type; 231 unsigned int num = 0; 232 233 if (!panel->desc) 234 return 0; 235 236 if (has_override) { 237 mode = drm_mode_duplicate(connector->dev, 238 &panel->override_mode); 239 if (mode) { 240 drm_mode_probed_add(connector, mode); 241 num = 1; 242 } else { 243 dev_err(panel->base.dev, "failed to add override mode\n"); 244 } 245 } 246 247 /* Only add timings if override was not there or failed to validate */ 248 if (num == 0 && panel->desc->num_timings) 249 num = panel_simple_get_timings_modes(panel, connector); 250 251 /* 252 * Only add fixed modes if timings/override added no mode. 253 * 254 * We should only ever have either the display timings specified 255 * or a fixed mode. Anything else is rather bogus. 256 */ 257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 258 if (num == 0) 259 num = panel_simple_get_display_modes(panel, connector); 260 261 connector->display_info.bpc = panel->desc->bpc; 262 connector->display_info.width_mm = panel->desc->size.width; 263 connector->display_info.height_mm = panel->desc->size.height; 264 if (panel->desc->bus_format) 265 drm_display_info_set_bus_formats(&connector->display_info, 266 &panel->desc->bus_format, 1); 267 connector->display_info.bus_flags = panel->desc->bus_flags; 268 269 return num; 270 } 271 272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 273 { 274 ktime_t now_ktime, min_ktime; 275 276 if (!min_ms) 277 return; 278 279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 280 now_ktime = ktime_get_boottime(); 281 282 if (ktime_before(now_ktime, min_ktime)) 283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 284 } 285 286 static int panel_simple_disable(struct drm_panel *panel) 287 { 288 struct panel_simple *p = to_panel_simple(panel); 289 290 if (p->desc->delay.disable) 291 msleep(p->desc->delay.disable); 292 293 return 0; 294 } 295 296 static int panel_simple_suspend(struct device *dev) 297 { 298 struct panel_simple *p = dev_get_drvdata(dev); 299 300 gpiod_set_value_cansleep(p->enable_gpio, 0); 301 regulator_disable(p->supply); 302 p->unprepared_time = ktime_get_boottime(); 303 304 drm_edid_free(p->drm_edid); 305 p->drm_edid = NULL; 306 307 return 0; 308 } 309 310 static int panel_simple_unprepare(struct drm_panel *panel) 311 { 312 int ret; 313 314 pm_runtime_mark_last_busy(panel->dev); 315 ret = pm_runtime_put_autosuspend(panel->dev); 316 if (ret < 0) 317 return ret; 318 319 return 0; 320 } 321 322 static int panel_simple_resume(struct device *dev) 323 { 324 struct panel_simple *p = dev_get_drvdata(dev); 325 int err; 326 327 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 328 329 err = regulator_enable(p->supply); 330 if (err < 0) { 331 dev_err(dev, "failed to enable supply: %d\n", err); 332 return err; 333 } 334 335 gpiod_set_value_cansleep(p->enable_gpio, 1); 336 337 if (p->desc->delay.prepare) 338 msleep(p->desc->delay.prepare); 339 340 return 0; 341 } 342 343 static int panel_simple_prepare(struct drm_panel *panel) 344 { 345 int ret; 346 347 ret = pm_runtime_get_sync(panel->dev); 348 if (ret < 0) { 349 pm_runtime_put_autosuspend(panel->dev); 350 return ret; 351 } 352 353 return 0; 354 } 355 356 static int panel_simple_enable(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 360 if (p->desc->delay.enable) 361 msleep(p->desc->delay.enable); 362 363 return 0; 364 } 365 366 static int panel_simple_get_modes(struct drm_panel *panel, 367 struct drm_connector *connector) 368 { 369 struct panel_simple *p = to_panel_simple(panel); 370 int num = 0; 371 372 /* probe EDID if a DDC bus is available */ 373 if (p->ddc) { 374 pm_runtime_get_sync(panel->dev); 375 376 if (!p->drm_edid) 377 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 378 379 drm_edid_connector_update(connector, p->drm_edid); 380 381 num += drm_edid_connector_add_modes(connector); 382 383 pm_runtime_mark_last_busy(panel->dev); 384 pm_runtime_put_autosuspend(panel->dev); 385 } 386 387 /* add hard-coded panel modes */ 388 num += panel_simple_get_non_edid_modes(p, connector); 389 390 /* 391 * TODO: Remove once all drm drivers call 392 * drm_connector_set_orientation_from_panel() 393 */ 394 drm_connector_set_panel_orientation(connector, p->orientation); 395 396 return num; 397 } 398 399 static int panel_simple_get_timings(struct drm_panel *panel, 400 unsigned int num_timings, 401 struct display_timing *timings) 402 { 403 struct panel_simple *p = to_panel_simple(panel); 404 unsigned int i; 405 406 if (p->desc->num_timings < num_timings) 407 num_timings = p->desc->num_timings; 408 409 if (timings) 410 for (i = 0; i < num_timings; i++) 411 timings[i] = p->desc->timings[i]; 412 413 return p->desc->num_timings; 414 } 415 416 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 417 { 418 struct panel_simple *p = to_panel_simple(panel); 419 420 return p->orientation; 421 } 422 423 static const struct drm_panel_funcs panel_simple_funcs = { 424 .disable = panel_simple_disable, 425 .unprepare = panel_simple_unprepare, 426 .prepare = panel_simple_prepare, 427 .enable = panel_simple_enable, 428 .get_modes = panel_simple_get_modes, 429 .get_orientation = panel_simple_get_orientation, 430 .get_timings = panel_simple_get_timings, 431 }; 432 433 static struct panel_desc panel_dpi; 434 435 static int panel_dpi_probe(struct device *dev, 436 struct panel_simple *panel) 437 { 438 struct display_timing *timing; 439 const struct device_node *np; 440 struct panel_desc *desc; 441 unsigned int bus_flags; 442 struct videomode vm; 443 int ret; 444 445 np = dev->of_node; 446 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 447 if (!desc) 448 return -ENOMEM; 449 450 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 451 if (!timing) 452 return -ENOMEM; 453 454 ret = of_get_display_timing(np, "panel-timing", timing); 455 if (ret < 0) { 456 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 457 np); 458 return ret; 459 } 460 461 desc->timings = timing; 462 desc->num_timings = 1; 463 464 of_property_read_u32(np, "width-mm", &desc->size.width); 465 of_property_read_u32(np, "height-mm", &desc->size.height); 466 467 /* Extract bus_flags from display_timing */ 468 bus_flags = 0; 469 vm.flags = timing->flags; 470 drm_bus_flags_from_videomode(&vm, &bus_flags); 471 desc->bus_flags = bus_flags; 472 473 /* We do not know the connector for the DT node, so guess it */ 474 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 475 476 panel->desc = desc; 477 478 return 0; 479 } 480 481 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 482 (to_check->field.typ >= bounds->field.min && \ 483 to_check->field.typ <= bounds->field.max) 484 static void panel_simple_parse_panel_timing_node(struct device *dev, 485 struct panel_simple *panel, 486 const struct display_timing *ot) 487 { 488 const struct panel_desc *desc = panel->desc; 489 struct videomode vm; 490 unsigned int i; 491 492 if (WARN_ON(desc->num_modes)) { 493 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 494 return; 495 } 496 if (WARN_ON(!desc->num_timings)) { 497 dev_err(dev, "Reject override mode: no timings specified\n"); 498 return; 499 } 500 501 for (i = 0; i < panel->desc->num_timings; i++) { 502 const struct display_timing *dt = &panel->desc->timings[i]; 503 504 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 505 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 506 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 507 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 508 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 512 continue; 513 514 if (ot->flags != dt->flags) 515 continue; 516 517 videomode_from_timing(ot, &vm); 518 drm_display_mode_from_videomode(&vm, &panel->override_mode); 519 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 520 DRM_MODE_TYPE_PREFERRED; 521 break; 522 } 523 524 if (WARN_ON(!panel->override_mode.type)) 525 dev_err(dev, "Reject override mode: No display_timing found\n"); 526 } 527 528 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 529 struct panel_simple *panel) 530 { 531 int ret, bpc; 532 533 ret = drm_of_lvds_get_data_mapping(dev->of_node); 534 if (ret < 0) { 535 if (ret == -EINVAL) 536 dev_warn(dev, "Ignore invalid data-mapping property\n"); 537 538 /* 539 * Ignore non-existing or malformatted property, fallback to 540 * default data-mapping, and return 0. 541 */ 542 return 0; 543 } 544 545 switch (ret) { 546 default: 547 WARN_ON(1); 548 fallthrough; 549 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 550 fallthrough; 551 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 552 bpc = 8; 553 break; 554 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 555 bpc = 6; 556 } 557 558 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 559 struct panel_desc *override_desc; 560 561 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 562 if (!override_desc) 563 return -ENOMEM; 564 565 override_desc->bus_format = ret; 566 override_desc->bpc = bpc; 567 panel->desc = override_desc; 568 } 569 570 return 0; 571 } 572 573 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 574 { 575 struct panel_simple *panel; 576 struct display_timing dt; 577 struct device_node *ddc; 578 int connector_type; 579 u32 bus_flags; 580 int err; 581 582 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 583 if (!panel) 584 return -ENOMEM; 585 586 panel->desc = desc; 587 588 panel->supply = devm_regulator_get(dev, "power"); 589 if (IS_ERR(panel->supply)) 590 return PTR_ERR(panel->supply); 591 592 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 593 GPIOD_OUT_LOW); 594 if (IS_ERR(panel->enable_gpio)) 595 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 596 "failed to request GPIO\n"); 597 598 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 599 if (err) { 600 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 601 return err; 602 } 603 604 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 605 if (ddc) { 606 panel->ddc = of_find_i2c_adapter_by_node(ddc); 607 of_node_put(ddc); 608 609 if (!panel->ddc) 610 return -EPROBE_DEFER; 611 } 612 613 if (desc == &panel_dpi) { 614 /* Handle the generic panel-dpi binding */ 615 err = panel_dpi_probe(dev, panel); 616 if (err) 617 goto free_ddc; 618 desc = panel->desc; 619 } else { 620 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 621 panel_simple_parse_panel_timing_node(dev, panel, &dt); 622 } 623 624 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 625 /* Optional data-mapping property for overriding bus format */ 626 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 627 if (err) 628 goto free_ddc; 629 } 630 631 connector_type = desc->connector_type; 632 /* Catch common mistakes for panels. */ 633 switch (connector_type) { 634 case 0: 635 dev_warn(dev, "Specify missing connector_type\n"); 636 connector_type = DRM_MODE_CONNECTOR_DPI; 637 break; 638 case DRM_MODE_CONNECTOR_LVDS: 639 WARN_ON(desc->bus_flags & 640 ~(DRM_BUS_FLAG_DE_LOW | 641 DRM_BUS_FLAG_DE_HIGH | 642 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 643 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 644 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 645 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 646 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 647 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 648 desc->bpc != 6); 649 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 650 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 651 desc->bpc != 8); 652 break; 653 case DRM_MODE_CONNECTOR_eDP: 654 dev_warn(dev, "eDP panels moved to panel-edp\n"); 655 err = -EINVAL; 656 goto free_ddc; 657 case DRM_MODE_CONNECTOR_DSI: 658 if (desc->bpc != 6 && desc->bpc != 8) 659 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 660 break; 661 case DRM_MODE_CONNECTOR_DPI: 662 bus_flags = DRM_BUS_FLAG_DE_LOW | 663 DRM_BUS_FLAG_DE_HIGH | 664 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 665 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 666 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 667 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 668 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 669 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 670 if (desc->bus_flags & ~bus_flags) 671 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 672 if (!(desc->bus_flags & bus_flags)) 673 dev_warn(dev, "Specify missing bus_flags\n"); 674 if (desc->bus_format == 0) 675 dev_warn(dev, "Specify missing bus_format\n"); 676 if (desc->bpc != 6 && desc->bpc != 8) 677 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 678 break; 679 default: 680 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 681 connector_type = DRM_MODE_CONNECTOR_DPI; 682 break; 683 } 684 685 dev_set_drvdata(dev, panel); 686 687 /* 688 * We use runtime PM for prepare / unprepare since those power the panel 689 * on and off and those can be very slow operations. This is important 690 * to optimize powering the panel on briefly to read the EDID before 691 * fully enabling the panel. 692 */ 693 pm_runtime_enable(dev); 694 pm_runtime_set_autosuspend_delay(dev, 1000); 695 pm_runtime_use_autosuspend(dev); 696 697 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 698 699 err = drm_panel_of_backlight(&panel->base); 700 if (err) { 701 dev_err_probe(dev, err, "Could not find backlight\n"); 702 goto disable_pm_runtime; 703 } 704 705 drm_panel_add(&panel->base); 706 707 return 0; 708 709 disable_pm_runtime: 710 pm_runtime_dont_use_autosuspend(dev); 711 pm_runtime_disable(dev); 712 free_ddc: 713 if (panel->ddc) 714 put_device(&panel->ddc->dev); 715 716 return err; 717 } 718 719 static void panel_simple_shutdown(struct device *dev) 720 { 721 struct panel_simple *panel = dev_get_drvdata(dev); 722 723 /* 724 * NOTE: the following two calls don't really belong here. It is the 725 * responsibility of a correctly written DRM modeset driver to call 726 * drm_atomic_helper_shutdown() at shutdown time and that should 727 * cause the panel to be disabled / unprepared if needed. For now, 728 * however, we'll keep these calls due to the sheer number of 729 * different DRM modeset drivers used with panel-simple. The fact that 730 * we're calling these and _also_ the drm_atomic_helper_shutdown() 731 * will try to disable/unprepare means that we can get a warning about 732 * trying to disable/unprepare an already disabled/unprepared panel, 733 * but that's something we'll have to live with until we've confirmed 734 * that all DRM modeset drivers are properly calling 735 * drm_atomic_helper_shutdown(). 736 */ 737 drm_panel_disable(&panel->base); 738 drm_panel_unprepare(&panel->base); 739 } 740 741 static void panel_simple_remove(struct device *dev) 742 { 743 struct panel_simple *panel = dev_get_drvdata(dev); 744 745 drm_panel_remove(&panel->base); 746 panel_simple_shutdown(dev); 747 748 pm_runtime_dont_use_autosuspend(dev); 749 pm_runtime_disable(dev); 750 if (panel->ddc) 751 put_device(&panel->ddc->dev); 752 } 753 754 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 755 .clock = 71100, 756 .hdisplay = 1280, 757 .hsync_start = 1280 + 40, 758 .hsync_end = 1280 + 40 + 80, 759 .htotal = 1280 + 40 + 80 + 40, 760 .vdisplay = 800, 761 .vsync_start = 800 + 3, 762 .vsync_end = 800 + 3 + 10, 763 .vtotal = 800 + 3 + 10 + 10, 764 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 765 }; 766 767 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 768 .modes = &ire_am_1280800n3tzqw_t00h_mode, 769 .num_modes = 1, 770 .bpc = 8, 771 .size = { 772 .width = 217, 773 .height = 136, 774 }, 775 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 776 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 777 .connector_type = DRM_MODE_CONNECTOR_LVDS, 778 }; 779 780 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 781 .clock = 9000, 782 .hdisplay = 480, 783 .hsync_start = 480 + 2, 784 .hsync_end = 480 + 2 + 41, 785 .htotal = 480 + 2 + 41 + 2, 786 .vdisplay = 272, 787 .vsync_start = 272 + 2, 788 .vsync_end = 272 + 2 + 10, 789 .vtotal = 272 + 2 + 10 + 2, 790 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 791 }; 792 793 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 794 .modes = &ire_am_480272h3tmqw_t01h_mode, 795 .num_modes = 1, 796 .bpc = 8, 797 .size = { 798 .width = 99, 799 .height = 58, 800 }, 801 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 802 }; 803 804 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 805 .clock = 33333, 806 .hdisplay = 800, 807 .hsync_start = 800 + 0, 808 .hsync_end = 800 + 0 + 255, 809 .htotal = 800 + 0 + 255 + 0, 810 .vdisplay = 480, 811 .vsync_start = 480 + 2, 812 .vsync_end = 480 + 2 + 45, 813 .vtotal = 480 + 2 + 45 + 0, 814 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 815 }; 816 817 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 818 .pixelclock = { 29930000, 33260000, 36590000 }, 819 .hactive = { 800, 800, 800 }, 820 .hfront_porch = { 1, 40, 168 }, 821 .hback_porch = { 88, 88, 88 }, 822 .hsync_len = { 1, 128, 128 }, 823 .vactive = { 480, 480, 480 }, 824 .vfront_porch = { 1, 35, 37 }, 825 .vback_porch = { 8, 8, 8 }, 826 .vsync_len = { 1, 2, 2 }, 827 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 828 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 829 DISPLAY_FLAGS_SYNC_POSEDGE, 830 }; 831 832 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 833 .timings = &ire_am_800480l1tmqw_t00h_timing, 834 .num_timings = 1, 835 .bpc = 8, 836 .size = { 837 .width = 111, 838 .height = 67, 839 }, 840 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 841 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 842 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 843 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 844 .connector_type = DRM_MODE_CONNECTOR_DPI, 845 }; 846 847 static const struct panel_desc ampire_am800480r3tmqwa1h = { 848 .modes = &ire_am800480r3tmqwa1h_mode, 849 .num_modes = 1, 850 .bpc = 6, 851 .size = { 852 .width = 152, 853 .height = 91, 854 }, 855 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 856 }; 857 858 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 859 .pixelclock = { 34500000, 39600000, 50400000 }, 860 .hactive = { 800, 800, 800 }, 861 .hfront_porch = { 12, 112, 312 }, 862 .hback_porch = { 87, 87, 48 }, 863 .hsync_len = { 1, 1, 40 }, 864 .vactive = { 600, 600, 600 }, 865 .vfront_porch = { 1, 21, 61 }, 866 .vback_porch = { 38, 38, 19 }, 867 .vsync_len = { 1, 1, 20 }, 868 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 869 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 870 DISPLAY_FLAGS_SYNC_POSEDGE, 871 }; 872 873 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 874 .timings = &ire_am800600p5tmqw_tb8h_timing, 875 .num_timings = 1, 876 .bpc = 6, 877 .size = { 878 .width = 162, 879 .height = 122, 880 }, 881 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 882 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 883 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 884 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 885 .connector_type = DRM_MODE_CONNECTOR_DPI, 886 }; 887 888 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 889 .pixelclock = { 26400000, 33300000, 46800000 }, 890 .hactive = { 800, 800, 800 }, 891 .hfront_porch = { 16, 210, 354 }, 892 .hback_porch = { 45, 36, 6 }, 893 .hsync_len = { 1, 10, 40 }, 894 .vactive = { 480, 480, 480 }, 895 .vfront_porch = { 7, 22, 147 }, 896 .vback_porch = { 22, 13, 3 }, 897 .vsync_len = { 1, 10, 20 }, 898 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 899 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 900 }; 901 902 static const struct panel_desc armadeus_st0700_adapt = { 903 .timings = &santek_st0700i5y_rbslw_f_timing, 904 .num_timings = 1, 905 .bpc = 6, 906 .size = { 907 .width = 154, 908 .height = 86, 909 }, 910 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 911 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 912 }; 913 914 static const struct drm_display_mode auo_b101aw03_mode = { 915 .clock = 51450, 916 .hdisplay = 1024, 917 .hsync_start = 1024 + 156, 918 .hsync_end = 1024 + 156 + 8, 919 .htotal = 1024 + 156 + 8 + 156, 920 .vdisplay = 600, 921 .vsync_start = 600 + 16, 922 .vsync_end = 600 + 16 + 6, 923 .vtotal = 600 + 16 + 6 + 16, 924 }; 925 926 static const struct panel_desc auo_b101aw03 = { 927 .modes = &auo_b101aw03_mode, 928 .num_modes = 1, 929 .bpc = 6, 930 .size = { 931 .width = 223, 932 .height = 125, 933 }, 934 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 935 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 936 .connector_type = DRM_MODE_CONNECTOR_LVDS, 937 }; 938 939 static const struct drm_display_mode auo_b101xtn01_mode = { 940 .clock = 72000, 941 .hdisplay = 1366, 942 .hsync_start = 1366 + 20, 943 .hsync_end = 1366 + 20 + 70, 944 .htotal = 1366 + 20 + 70, 945 .vdisplay = 768, 946 .vsync_start = 768 + 14, 947 .vsync_end = 768 + 14 + 42, 948 .vtotal = 768 + 14 + 42, 949 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 950 }; 951 952 static const struct panel_desc auo_b101xtn01 = { 953 .modes = &auo_b101xtn01_mode, 954 .num_modes = 1, 955 .bpc = 6, 956 .size = { 957 .width = 223, 958 .height = 125, 959 }, 960 }; 961 962 static const struct drm_display_mode auo_b116xw03_mode = { 963 .clock = 70589, 964 .hdisplay = 1366, 965 .hsync_start = 1366 + 40, 966 .hsync_end = 1366 + 40 + 40, 967 .htotal = 1366 + 40 + 40 + 32, 968 .vdisplay = 768, 969 .vsync_start = 768 + 10, 970 .vsync_end = 768 + 10 + 12, 971 .vtotal = 768 + 10 + 12 + 6, 972 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 973 }; 974 975 static const struct panel_desc auo_b116xw03 = { 976 .modes = &auo_b116xw03_mode, 977 .num_modes = 1, 978 .bpc = 6, 979 .size = { 980 .width = 256, 981 .height = 144, 982 }, 983 .delay = { 984 .prepare = 1, 985 .enable = 200, 986 .disable = 200, 987 .unprepare = 500, 988 }, 989 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 990 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 991 .connector_type = DRM_MODE_CONNECTOR_LVDS, 992 }; 993 994 static const struct display_timing auo_g070vvn01_timings = { 995 .pixelclock = { 33300000, 34209000, 45000000 }, 996 .hactive = { 800, 800, 800 }, 997 .hfront_porch = { 20, 40, 200 }, 998 .hback_porch = { 87, 40, 1 }, 999 .hsync_len = { 1, 48, 87 }, 1000 .vactive = { 480, 480, 480 }, 1001 .vfront_porch = { 5, 13, 200 }, 1002 .vback_porch = { 31, 31, 29 }, 1003 .vsync_len = { 1, 1, 3 }, 1004 }; 1005 1006 static const struct panel_desc auo_g070vvn01 = { 1007 .timings = &auo_g070vvn01_timings, 1008 .num_timings = 1, 1009 .bpc = 8, 1010 .size = { 1011 .width = 152, 1012 .height = 91, 1013 }, 1014 .delay = { 1015 .prepare = 200, 1016 .enable = 50, 1017 .disable = 50, 1018 .unprepare = 1000, 1019 }, 1020 }; 1021 1022 static const struct drm_display_mode auo_g101evn010_mode = { 1023 .clock = 68930, 1024 .hdisplay = 1280, 1025 .hsync_start = 1280 + 82, 1026 .hsync_end = 1280 + 82 + 2, 1027 .htotal = 1280 + 82 + 2 + 84, 1028 .vdisplay = 800, 1029 .vsync_start = 800 + 8, 1030 .vsync_end = 800 + 8 + 2, 1031 .vtotal = 800 + 8 + 2 + 6, 1032 }; 1033 1034 static const struct panel_desc auo_g101evn010 = { 1035 .modes = &auo_g101evn010_mode, 1036 .num_modes = 1, 1037 .bpc = 6, 1038 .size = { 1039 .width = 216, 1040 .height = 135, 1041 }, 1042 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1043 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1044 }; 1045 1046 static const struct drm_display_mode auo_g104sn02_mode = { 1047 .clock = 40000, 1048 .hdisplay = 800, 1049 .hsync_start = 800 + 40, 1050 .hsync_end = 800 + 40 + 216, 1051 .htotal = 800 + 40 + 216 + 128, 1052 .vdisplay = 600, 1053 .vsync_start = 600 + 10, 1054 .vsync_end = 600 + 10 + 35, 1055 .vtotal = 600 + 10 + 35 + 2, 1056 }; 1057 1058 static const struct panel_desc auo_g104sn02 = { 1059 .modes = &auo_g104sn02_mode, 1060 .num_modes = 1, 1061 .bpc = 8, 1062 .size = { 1063 .width = 211, 1064 .height = 158, 1065 }, 1066 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1067 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1068 }; 1069 1070 static const struct drm_display_mode auo_g104stn01_mode = { 1071 .clock = 40000, 1072 .hdisplay = 800, 1073 .hsync_start = 800 + 40, 1074 .hsync_end = 800 + 40 + 88, 1075 .htotal = 800 + 40 + 88 + 128, 1076 .vdisplay = 600, 1077 .vsync_start = 600 + 1, 1078 .vsync_end = 600 + 1 + 23, 1079 .vtotal = 600 + 1 + 23 + 4, 1080 }; 1081 1082 static const struct panel_desc auo_g104stn01 = { 1083 .modes = &auo_g104stn01_mode, 1084 .num_modes = 1, 1085 .bpc = 8, 1086 .size = { 1087 .width = 211, 1088 .height = 158, 1089 }, 1090 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1091 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1092 }; 1093 1094 static const struct display_timing auo_g121ean01_timing = { 1095 .pixelclock = { 60000000, 74400000, 90000000 }, 1096 .hactive = { 1280, 1280, 1280 }, 1097 .hfront_porch = { 20, 50, 100 }, 1098 .hback_porch = { 20, 50, 100 }, 1099 .hsync_len = { 30, 100, 200 }, 1100 .vactive = { 800, 800, 800 }, 1101 .vfront_porch = { 2, 10, 25 }, 1102 .vback_porch = { 2, 10, 25 }, 1103 .vsync_len = { 4, 18, 50 }, 1104 }; 1105 1106 static const struct panel_desc auo_g121ean01 = { 1107 .timings = &auo_g121ean01_timing, 1108 .num_timings = 1, 1109 .bpc = 8, 1110 .size = { 1111 .width = 261, 1112 .height = 163, 1113 }, 1114 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1115 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1116 }; 1117 1118 static const struct display_timing auo_g133han01_timings = { 1119 .pixelclock = { 134000000, 141200000, 149000000 }, 1120 .hactive = { 1920, 1920, 1920 }, 1121 .hfront_porch = { 39, 58, 77 }, 1122 .hback_porch = { 59, 88, 117 }, 1123 .hsync_len = { 28, 42, 56 }, 1124 .vactive = { 1080, 1080, 1080 }, 1125 .vfront_porch = { 3, 8, 11 }, 1126 .vback_porch = { 5, 14, 19 }, 1127 .vsync_len = { 4, 14, 19 }, 1128 }; 1129 1130 static const struct panel_desc auo_g133han01 = { 1131 .timings = &auo_g133han01_timings, 1132 .num_timings = 1, 1133 .bpc = 8, 1134 .size = { 1135 .width = 293, 1136 .height = 165, 1137 }, 1138 .delay = { 1139 .prepare = 200, 1140 .enable = 50, 1141 .disable = 50, 1142 .unprepare = 1000, 1143 }, 1144 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1145 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1146 }; 1147 1148 static const struct display_timing auo_g156han04_timings = { 1149 .pixelclock = { 137000000, 141000000, 146000000 }, 1150 .hactive = { 1920, 1920, 1920 }, 1151 .hfront_porch = { 60, 60, 60 }, 1152 .hback_porch = { 90, 92, 111 }, 1153 .hsync_len = { 32, 32, 32 }, 1154 .vactive = { 1080, 1080, 1080 }, 1155 .vfront_porch = { 12, 12, 12 }, 1156 .vback_porch = { 24, 36, 56 }, 1157 .vsync_len = { 8, 8, 8 }, 1158 }; 1159 1160 static const struct panel_desc auo_g156han04 = { 1161 .timings = &auo_g156han04_timings, 1162 .num_timings = 1, 1163 .bpc = 8, 1164 .size = { 1165 .width = 344, 1166 .height = 194, 1167 }, 1168 .delay = { 1169 .prepare = 50, /* T2 */ 1170 .enable = 200, /* T3 */ 1171 .disable = 110, /* T10 */ 1172 .unprepare = 1000, /* T13 */ 1173 }, 1174 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1175 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1176 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1177 }; 1178 1179 static const struct drm_display_mode auo_g156xtn01_mode = { 1180 .clock = 76000, 1181 .hdisplay = 1366, 1182 .hsync_start = 1366 + 33, 1183 .hsync_end = 1366 + 33 + 67, 1184 .htotal = 1560, 1185 .vdisplay = 768, 1186 .vsync_start = 768 + 4, 1187 .vsync_end = 768 + 4 + 4, 1188 .vtotal = 806, 1189 }; 1190 1191 static const struct panel_desc auo_g156xtn01 = { 1192 .modes = &auo_g156xtn01_mode, 1193 .num_modes = 1, 1194 .bpc = 8, 1195 .size = { 1196 .width = 344, 1197 .height = 194, 1198 }, 1199 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1200 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1201 }; 1202 1203 static const struct display_timing auo_g185han01_timings = { 1204 .pixelclock = { 120000000, 144000000, 175000000 }, 1205 .hactive = { 1920, 1920, 1920 }, 1206 .hfront_porch = { 36, 120, 148 }, 1207 .hback_porch = { 24, 88, 108 }, 1208 .hsync_len = { 20, 48, 64 }, 1209 .vactive = { 1080, 1080, 1080 }, 1210 .vfront_porch = { 6, 10, 40 }, 1211 .vback_porch = { 2, 5, 20 }, 1212 .vsync_len = { 2, 5, 20 }, 1213 }; 1214 1215 static const struct panel_desc auo_g185han01 = { 1216 .timings = &auo_g185han01_timings, 1217 .num_timings = 1, 1218 .bpc = 8, 1219 .size = { 1220 .width = 409, 1221 .height = 230, 1222 }, 1223 .delay = { 1224 .prepare = 50, 1225 .enable = 200, 1226 .disable = 110, 1227 .unprepare = 1000, 1228 }, 1229 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1230 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1231 }; 1232 1233 static const struct display_timing auo_g190ean01_timings = { 1234 .pixelclock = { 90000000, 108000000, 135000000 }, 1235 .hactive = { 1280, 1280, 1280 }, 1236 .hfront_porch = { 126, 184, 1266 }, 1237 .hback_porch = { 84, 122, 844 }, 1238 .hsync_len = { 70, 102, 704 }, 1239 .vactive = { 1024, 1024, 1024 }, 1240 .vfront_porch = { 4, 26, 76 }, 1241 .vback_porch = { 2, 8, 25 }, 1242 .vsync_len = { 2, 8, 25 }, 1243 }; 1244 1245 static const struct panel_desc auo_g190ean01 = { 1246 .timings = &auo_g190ean01_timings, 1247 .num_timings = 1, 1248 .bpc = 8, 1249 .size = { 1250 .width = 376, 1251 .height = 301, 1252 }, 1253 .delay = { 1254 .prepare = 50, 1255 .enable = 200, 1256 .disable = 110, 1257 .unprepare = 1000, 1258 }, 1259 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1260 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1261 }; 1262 1263 static const struct display_timing auo_p320hvn03_timings = { 1264 .pixelclock = { 106000000, 148500000, 164000000 }, 1265 .hactive = { 1920, 1920, 1920 }, 1266 .hfront_porch = { 25, 50, 130 }, 1267 .hback_porch = { 25, 50, 130 }, 1268 .hsync_len = { 20, 40, 105 }, 1269 .vactive = { 1080, 1080, 1080 }, 1270 .vfront_porch = { 8, 17, 150 }, 1271 .vback_porch = { 8, 17, 150 }, 1272 .vsync_len = { 4, 11, 100 }, 1273 }; 1274 1275 static const struct panel_desc auo_p320hvn03 = { 1276 .timings = &auo_p320hvn03_timings, 1277 .num_timings = 1, 1278 .bpc = 8, 1279 .size = { 1280 .width = 698, 1281 .height = 393, 1282 }, 1283 .delay = { 1284 .prepare = 1, 1285 .enable = 450, 1286 .unprepare = 500, 1287 }, 1288 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1289 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1290 }; 1291 1292 static const struct drm_display_mode auo_t215hvn01_mode = { 1293 .clock = 148800, 1294 .hdisplay = 1920, 1295 .hsync_start = 1920 + 88, 1296 .hsync_end = 1920 + 88 + 44, 1297 .htotal = 1920 + 88 + 44 + 148, 1298 .vdisplay = 1080, 1299 .vsync_start = 1080 + 4, 1300 .vsync_end = 1080 + 4 + 5, 1301 .vtotal = 1080 + 4 + 5 + 36, 1302 }; 1303 1304 static const struct panel_desc auo_t215hvn01 = { 1305 .modes = &auo_t215hvn01_mode, 1306 .num_modes = 1, 1307 .bpc = 8, 1308 .size = { 1309 .width = 430, 1310 .height = 270, 1311 }, 1312 .delay = { 1313 .disable = 5, 1314 .unprepare = 1000, 1315 }, 1316 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1317 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1318 }; 1319 1320 static const struct drm_display_mode avic_tm070ddh03_mode = { 1321 .clock = 51200, 1322 .hdisplay = 1024, 1323 .hsync_start = 1024 + 160, 1324 .hsync_end = 1024 + 160 + 4, 1325 .htotal = 1024 + 160 + 4 + 156, 1326 .vdisplay = 600, 1327 .vsync_start = 600 + 17, 1328 .vsync_end = 600 + 17 + 1, 1329 .vtotal = 600 + 17 + 1 + 17, 1330 }; 1331 1332 static const struct panel_desc avic_tm070ddh03 = { 1333 .modes = &avic_tm070ddh03_mode, 1334 .num_modes = 1, 1335 .bpc = 8, 1336 .size = { 1337 .width = 154, 1338 .height = 90, 1339 }, 1340 .delay = { 1341 .prepare = 20, 1342 .enable = 200, 1343 .disable = 200, 1344 }, 1345 }; 1346 1347 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1348 .clock = 30000, 1349 .hdisplay = 800, 1350 .hsync_start = 800 + 40, 1351 .hsync_end = 800 + 40 + 48, 1352 .htotal = 800 + 40 + 48 + 40, 1353 .vdisplay = 480, 1354 .vsync_start = 480 + 13, 1355 .vsync_end = 480 + 13 + 3, 1356 .vtotal = 480 + 13 + 3 + 29, 1357 }; 1358 1359 static const struct panel_desc bananapi_s070wv20_ct16 = { 1360 .modes = &bananapi_s070wv20_ct16_mode, 1361 .num_modes = 1, 1362 .bpc = 6, 1363 .size = { 1364 .width = 154, 1365 .height = 86, 1366 }, 1367 }; 1368 1369 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1370 .clock = 78945, 1371 .hdisplay = 1280, 1372 .hsync_start = 1280 + 0, 1373 .hsync_end = 1280 + 0 + 2, 1374 .htotal = 1280 + 62 + 0 + 2, 1375 .vdisplay = 800, 1376 .vsync_start = 800 + 8, 1377 .vsync_end = 800 + 8 + 2, 1378 .vtotal = 800 + 6 + 8 + 2, 1379 }; 1380 1381 static const struct panel_desc boe_bp082wx1_100 = { 1382 .modes = &boe_bp101wx1_100_mode, 1383 .num_modes = 1, 1384 .bpc = 8, 1385 .size = { 1386 .width = 177, 1387 .height = 110, 1388 }, 1389 .delay = { 1390 .enable = 50, 1391 .disable = 50, 1392 }, 1393 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1394 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1395 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1396 }; 1397 1398 static const struct panel_desc boe_bp101wx1_100 = { 1399 .modes = &boe_bp101wx1_100_mode, 1400 .num_modes = 1, 1401 .bpc = 8, 1402 .size = { 1403 .width = 217, 1404 .height = 136, 1405 }, 1406 .delay = { 1407 .enable = 50, 1408 .disable = 50, 1409 }, 1410 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1411 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1412 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1413 }; 1414 1415 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1416 .pixelclock = { 69922000, 71000000, 72293000 }, 1417 .hactive = { 1280, 1280, 1280 }, 1418 .hfront_porch = { 48, 48, 48 }, 1419 .hback_porch = { 80, 80, 80 }, 1420 .hsync_len = { 32, 32, 32 }, 1421 .vactive = { 800, 800, 800 }, 1422 .vfront_porch = { 3, 3, 3 }, 1423 .vback_porch = { 14, 14, 14 }, 1424 .vsync_len = { 6, 6, 6 }, 1425 }; 1426 1427 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1428 .timings = &boe_ev121wxm_n10_1850_timing, 1429 .num_timings = 1, 1430 .bpc = 8, 1431 .size = { 1432 .width = 261, 1433 .height = 163, 1434 }, 1435 .delay = { 1436 .prepare = 9, 1437 .enable = 300, 1438 .unprepare = 300, 1439 .disable = 560, 1440 }, 1441 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1442 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1443 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1444 }; 1445 1446 static const struct drm_display_mode boe_hv070wsa_mode = { 1447 .clock = 42105, 1448 .hdisplay = 1024, 1449 .hsync_start = 1024 + 30, 1450 .hsync_end = 1024 + 30 + 30, 1451 .htotal = 1024 + 30 + 30 + 30, 1452 .vdisplay = 600, 1453 .vsync_start = 600 + 10, 1454 .vsync_end = 600 + 10 + 10, 1455 .vtotal = 600 + 10 + 10 + 10, 1456 }; 1457 1458 static const struct panel_desc boe_hv070wsa = { 1459 .modes = &boe_hv070wsa_mode, 1460 .num_modes = 1, 1461 .bpc = 8, 1462 .size = { 1463 .width = 154, 1464 .height = 90, 1465 }, 1466 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1467 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1468 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1469 }; 1470 1471 static const struct display_timing cct_cmt430b19n00_timing = { 1472 .pixelclock = { 8000000, 9000000, 12000000 }, 1473 .hactive = { 480, 480, 480 }, 1474 .hfront_porch = { 2, 8, 75 }, 1475 .hback_porch = { 3, 43, 43 }, 1476 .hsync_len = { 2, 4, 75 }, 1477 .vactive = { 272, 272, 272 }, 1478 .vfront_porch = { 2, 8, 37 }, 1479 .vback_porch = { 2, 12, 12 }, 1480 .vsync_len = { 2, 4, 37 }, 1481 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1482 }; 1483 1484 static const struct panel_desc cct_cmt430b19n00 = { 1485 .timings = &cct_cmt430b19n00_timing, 1486 .num_timings = 1, 1487 .bpc = 8, 1488 .size = { 1489 .width = 95, 1490 .height = 53, 1491 }, 1492 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1493 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1494 .connector_type = DRM_MODE_CONNECTOR_DPI, 1495 }; 1496 1497 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1498 .clock = 9000, 1499 .hdisplay = 480, 1500 .hsync_start = 480 + 5, 1501 .hsync_end = 480 + 5 + 5, 1502 .htotal = 480 + 5 + 5 + 40, 1503 .vdisplay = 272, 1504 .vsync_start = 272 + 8, 1505 .vsync_end = 272 + 8 + 8, 1506 .vtotal = 272 + 8 + 8 + 8, 1507 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1508 }; 1509 1510 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1511 .modes = &cdtech_s043wq26h_ct7_mode, 1512 .num_modes = 1, 1513 .bpc = 8, 1514 .size = { 1515 .width = 95, 1516 .height = 54, 1517 }, 1518 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1519 }; 1520 1521 /* S070PWS19HP-FC21 2017/04/22 */ 1522 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1523 .clock = 51200, 1524 .hdisplay = 1024, 1525 .hsync_start = 1024 + 160, 1526 .hsync_end = 1024 + 160 + 20, 1527 .htotal = 1024 + 160 + 20 + 140, 1528 .vdisplay = 600, 1529 .vsync_start = 600 + 12, 1530 .vsync_end = 600 + 12 + 3, 1531 .vtotal = 600 + 12 + 3 + 20, 1532 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1533 }; 1534 1535 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1536 .modes = &cdtech_s070pws19hp_fc21_mode, 1537 .num_modes = 1, 1538 .bpc = 6, 1539 .size = { 1540 .width = 154, 1541 .height = 86, 1542 }, 1543 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1544 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1545 .connector_type = DRM_MODE_CONNECTOR_DPI, 1546 }; 1547 1548 /* S070SWV29HG-DC44 2017/09/21 */ 1549 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1550 .clock = 33300, 1551 .hdisplay = 800, 1552 .hsync_start = 800 + 210, 1553 .hsync_end = 800 + 210 + 2, 1554 .htotal = 800 + 210 + 2 + 44, 1555 .vdisplay = 480, 1556 .vsync_start = 480 + 22, 1557 .vsync_end = 480 + 22 + 2, 1558 .vtotal = 480 + 22 + 2 + 21, 1559 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1560 }; 1561 1562 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1563 .modes = &cdtech_s070swv29hg_dc44_mode, 1564 .num_modes = 1, 1565 .bpc = 6, 1566 .size = { 1567 .width = 154, 1568 .height = 86, 1569 }, 1570 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1571 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1572 .connector_type = DRM_MODE_CONNECTOR_DPI, 1573 }; 1574 1575 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1576 .clock = 35000, 1577 .hdisplay = 800, 1578 .hsync_start = 800 + 40, 1579 .hsync_end = 800 + 40 + 40, 1580 .htotal = 800 + 40 + 40 + 48, 1581 .vdisplay = 480, 1582 .vsync_start = 480 + 29, 1583 .vsync_end = 480 + 29 + 13, 1584 .vtotal = 480 + 29 + 13 + 3, 1585 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1586 }; 1587 1588 static const struct panel_desc cdtech_s070wv95_ct16 = { 1589 .modes = &cdtech_s070wv95_ct16_mode, 1590 .num_modes = 1, 1591 .bpc = 8, 1592 .size = { 1593 .width = 154, 1594 .height = 85, 1595 }, 1596 }; 1597 1598 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1599 .pixelclock = { 68900000, 71100000, 73400000 }, 1600 .hactive = { 1280, 1280, 1280 }, 1601 .hfront_porch = { 65, 80, 95 }, 1602 .hback_porch = { 64, 79, 94 }, 1603 .hsync_len = { 1, 1, 1 }, 1604 .vactive = { 800, 800, 800 }, 1605 .vfront_porch = { 7, 11, 14 }, 1606 .vback_porch = { 7, 11, 14 }, 1607 .vsync_len = { 1, 1, 1 }, 1608 .flags = DISPLAY_FLAGS_DE_HIGH, 1609 }; 1610 1611 static const struct panel_desc chefree_ch101olhlwh_002 = { 1612 .timings = &chefree_ch101olhlwh_002_timing, 1613 .num_timings = 1, 1614 .bpc = 8, 1615 .size = { 1616 .width = 217, 1617 .height = 135, 1618 }, 1619 .delay = { 1620 .enable = 200, 1621 .disable = 200, 1622 }, 1623 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1624 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1625 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1626 }; 1627 1628 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1629 .clock = 66770, 1630 .hdisplay = 800, 1631 .hsync_start = 800 + 49, 1632 .hsync_end = 800 + 49 + 33, 1633 .htotal = 800 + 49 + 33 + 17, 1634 .vdisplay = 1280, 1635 .vsync_start = 1280 + 1, 1636 .vsync_end = 1280 + 1 + 7, 1637 .vtotal = 1280 + 1 + 7 + 15, 1638 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1639 }; 1640 1641 static const struct panel_desc chunghwa_claa070wp03xg = { 1642 .modes = &chunghwa_claa070wp03xg_mode, 1643 .num_modes = 1, 1644 .bpc = 6, 1645 .size = { 1646 .width = 94, 1647 .height = 150, 1648 }, 1649 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1650 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1651 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1652 }; 1653 1654 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1655 .clock = 72070, 1656 .hdisplay = 1366, 1657 .hsync_start = 1366 + 58, 1658 .hsync_end = 1366 + 58 + 58, 1659 .htotal = 1366 + 58 + 58 + 58, 1660 .vdisplay = 768, 1661 .vsync_start = 768 + 4, 1662 .vsync_end = 768 + 4 + 4, 1663 .vtotal = 768 + 4 + 4 + 4, 1664 }; 1665 1666 static const struct panel_desc chunghwa_claa101wa01a = { 1667 .modes = &chunghwa_claa101wa01a_mode, 1668 .num_modes = 1, 1669 .bpc = 6, 1670 .size = { 1671 .width = 220, 1672 .height = 120, 1673 }, 1674 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1675 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1676 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1677 }; 1678 1679 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1680 .clock = 69300, 1681 .hdisplay = 1366, 1682 .hsync_start = 1366 + 48, 1683 .hsync_end = 1366 + 48 + 32, 1684 .htotal = 1366 + 48 + 32 + 20, 1685 .vdisplay = 768, 1686 .vsync_start = 768 + 16, 1687 .vsync_end = 768 + 16 + 8, 1688 .vtotal = 768 + 16 + 8 + 16, 1689 }; 1690 1691 static const struct panel_desc chunghwa_claa101wb01 = { 1692 .modes = &chunghwa_claa101wb01_mode, 1693 .num_modes = 1, 1694 .bpc = 6, 1695 .size = { 1696 .width = 223, 1697 .height = 125, 1698 }, 1699 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1700 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1701 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1702 }; 1703 1704 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1705 .pixelclock = { 5000000, 9000000, 12000000 }, 1706 .hactive = { 480, 480, 480 }, 1707 .hfront_porch = { 12, 12, 12 }, 1708 .hback_porch = { 12, 12, 12 }, 1709 .hsync_len = { 21, 21, 21 }, 1710 .vactive = { 272, 272, 272 }, 1711 .vfront_porch = { 4, 4, 4 }, 1712 .vback_porch = { 4, 4, 4 }, 1713 .vsync_len = { 8, 8, 8 }, 1714 }; 1715 1716 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1717 .timings = &dataimage_fg040346dsswbg04_timing, 1718 .num_timings = 1, 1719 .bpc = 8, 1720 .size = { 1721 .width = 95, 1722 .height = 54, 1723 }, 1724 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1725 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1726 .connector_type = DRM_MODE_CONNECTOR_DPI, 1727 }; 1728 1729 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1730 .pixelclock = { 68900000, 71110000, 73400000 }, 1731 .hactive = { 1280, 1280, 1280 }, 1732 .vactive = { 800, 800, 800 }, 1733 .hback_porch = { 100, 100, 100 }, 1734 .hfront_porch = { 100, 100, 100 }, 1735 .vback_porch = { 5, 5, 5 }, 1736 .vfront_porch = { 5, 5, 5 }, 1737 .hsync_len = { 24, 24, 24 }, 1738 .vsync_len = { 3, 3, 3 }, 1739 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1740 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1741 }; 1742 1743 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1744 .timings = &dataimage_fg1001l0dsswmg01_timing, 1745 .num_timings = 1, 1746 .bpc = 8, 1747 .size = { 1748 .width = 217, 1749 .height = 136, 1750 }, 1751 }; 1752 1753 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1754 .clock = 33260, 1755 .hdisplay = 800, 1756 .hsync_start = 800 + 40, 1757 .hsync_end = 800 + 40 + 128, 1758 .htotal = 800 + 40 + 128 + 88, 1759 .vdisplay = 480, 1760 .vsync_start = 480 + 10, 1761 .vsync_end = 480 + 10 + 2, 1762 .vtotal = 480 + 10 + 2 + 33, 1763 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1764 }; 1765 1766 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1767 .modes = &dataimage_scf0700c48ggu18_mode, 1768 .num_modes = 1, 1769 .bpc = 8, 1770 .size = { 1771 .width = 152, 1772 .height = 91, 1773 }, 1774 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1775 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1776 }; 1777 1778 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1779 .pixelclock = { 45000000, 51200000, 57000000 }, 1780 .hactive = { 1024, 1024, 1024 }, 1781 .hfront_porch = { 100, 106, 113 }, 1782 .hback_porch = { 100, 106, 113 }, 1783 .hsync_len = { 100, 108, 114 }, 1784 .vactive = { 600, 600, 600 }, 1785 .vfront_porch = { 8, 11, 15 }, 1786 .vback_porch = { 8, 11, 15 }, 1787 .vsync_len = { 9, 13, 15 }, 1788 .flags = DISPLAY_FLAGS_DE_HIGH, 1789 }; 1790 1791 static const struct panel_desc dlc_dlc0700yzg_1 = { 1792 .timings = &dlc_dlc0700yzg_1_timing, 1793 .num_timings = 1, 1794 .bpc = 6, 1795 .size = { 1796 .width = 154, 1797 .height = 86, 1798 }, 1799 .delay = { 1800 .prepare = 30, 1801 .enable = 200, 1802 .disable = 200, 1803 }, 1804 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1805 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1806 }; 1807 1808 static const struct display_timing dlc_dlc1010gig_timing = { 1809 .pixelclock = { 68900000, 71100000, 73400000 }, 1810 .hactive = { 1280, 1280, 1280 }, 1811 .hfront_porch = { 43, 53, 63 }, 1812 .hback_porch = { 43, 53, 63 }, 1813 .hsync_len = { 44, 54, 64 }, 1814 .vactive = { 800, 800, 800 }, 1815 .vfront_porch = { 5, 8, 11 }, 1816 .vback_porch = { 5, 8, 11 }, 1817 .vsync_len = { 5, 7, 11 }, 1818 .flags = DISPLAY_FLAGS_DE_HIGH, 1819 }; 1820 1821 static const struct panel_desc dlc_dlc1010gig = { 1822 .timings = &dlc_dlc1010gig_timing, 1823 .num_timings = 1, 1824 .bpc = 8, 1825 .size = { 1826 .width = 216, 1827 .height = 135, 1828 }, 1829 .delay = { 1830 .prepare = 60, 1831 .enable = 150, 1832 .disable = 100, 1833 .unprepare = 60, 1834 }, 1835 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1836 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1837 }; 1838 1839 static const struct drm_display_mode edt_et035012dm6_mode = { 1840 .clock = 6500, 1841 .hdisplay = 320, 1842 .hsync_start = 320 + 20, 1843 .hsync_end = 320 + 20 + 30, 1844 .htotal = 320 + 20 + 68, 1845 .vdisplay = 240, 1846 .vsync_start = 240 + 4, 1847 .vsync_end = 240 + 4 + 4, 1848 .vtotal = 240 + 4 + 4 + 14, 1849 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1850 }; 1851 1852 static const struct panel_desc edt_et035012dm6 = { 1853 .modes = &edt_et035012dm6_mode, 1854 .num_modes = 1, 1855 .bpc = 8, 1856 .size = { 1857 .width = 70, 1858 .height = 52, 1859 }, 1860 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1861 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1862 }; 1863 1864 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1865 .clock = 6520, 1866 .hdisplay = 320, 1867 .hsync_start = 320 + 20, 1868 .hsync_end = 320 + 20 + 68, 1869 .htotal = 320 + 20 + 68, 1870 .vdisplay = 240, 1871 .vsync_start = 240 + 4, 1872 .vsync_end = 240 + 4 + 18, 1873 .vtotal = 240 + 4 + 18, 1874 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1875 }; 1876 1877 static const struct panel_desc edt_etm0350g0dh6 = { 1878 .modes = &edt_etm0350g0dh6_mode, 1879 .num_modes = 1, 1880 .bpc = 6, 1881 .size = { 1882 .width = 70, 1883 .height = 53, 1884 }, 1885 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1886 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1887 .connector_type = DRM_MODE_CONNECTOR_DPI, 1888 }; 1889 1890 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1891 .clock = 10870, 1892 .hdisplay = 480, 1893 .hsync_start = 480 + 8, 1894 .hsync_end = 480 + 8 + 4, 1895 .htotal = 480 + 8 + 4 + 41, 1896 1897 /* 1898 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1899 * fb_align 1900 */ 1901 1902 .vdisplay = 288, 1903 .vsync_start = 288 + 2, 1904 .vsync_end = 288 + 2 + 4, 1905 .vtotal = 288 + 2 + 4 + 10, 1906 }; 1907 1908 static const struct panel_desc edt_etm043080dh6gp = { 1909 .modes = &edt_etm043080dh6gp_mode, 1910 .num_modes = 1, 1911 .bpc = 8, 1912 .size = { 1913 .width = 100, 1914 .height = 65, 1915 }, 1916 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1917 .connector_type = DRM_MODE_CONNECTOR_DPI, 1918 }; 1919 1920 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1921 .clock = 9000, 1922 .hdisplay = 480, 1923 .hsync_start = 480 + 2, 1924 .hsync_end = 480 + 2 + 41, 1925 .htotal = 480 + 2 + 41 + 2, 1926 .vdisplay = 272, 1927 .vsync_start = 272 + 2, 1928 .vsync_end = 272 + 2 + 10, 1929 .vtotal = 272 + 2 + 10 + 2, 1930 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1931 }; 1932 1933 static const struct panel_desc edt_etm0430g0dh6 = { 1934 .modes = &edt_etm0430g0dh6_mode, 1935 .num_modes = 1, 1936 .bpc = 6, 1937 .size = { 1938 .width = 95, 1939 .height = 54, 1940 }, 1941 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1942 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1943 .connector_type = DRM_MODE_CONNECTOR_DPI, 1944 }; 1945 1946 static const struct drm_display_mode edt_et057090dhu_mode = { 1947 .clock = 25175, 1948 .hdisplay = 640, 1949 .hsync_start = 640 + 16, 1950 .hsync_end = 640 + 16 + 30, 1951 .htotal = 640 + 16 + 30 + 114, 1952 .vdisplay = 480, 1953 .vsync_start = 480 + 10, 1954 .vsync_end = 480 + 10 + 3, 1955 .vtotal = 480 + 10 + 3 + 32, 1956 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1957 }; 1958 1959 static const struct panel_desc edt_et057090dhu = { 1960 .modes = &edt_et057090dhu_mode, 1961 .num_modes = 1, 1962 .bpc = 6, 1963 .size = { 1964 .width = 115, 1965 .height = 86, 1966 }, 1967 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1968 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1969 .connector_type = DRM_MODE_CONNECTOR_DPI, 1970 }; 1971 1972 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1973 .clock = 33260, 1974 .hdisplay = 800, 1975 .hsync_start = 800 + 40, 1976 .hsync_end = 800 + 40 + 128, 1977 .htotal = 800 + 40 + 128 + 88, 1978 .vdisplay = 480, 1979 .vsync_start = 480 + 10, 1980 .vsync_end = 480 + 10 + 2, 1981 .vtotal = 480 + 10 + 2 + 33, 1982 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1983 }; 1984 1985 static const struct panel_desc edt_etm0700g0dh6 = { 1986 .modes = &edt_etm0700g0dh6_mode, 1987 .num_modes = 1, 1988 .bpc = 6, 1989 .size = { 1990 .width = 152, 1991 .height = 91, 1992 }, 1993 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1994 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1995 .connector_type = DRM_MODE_CONNECTOR_DPI, 1996 }; 1997 1998 static const struct panel_desc edt_etm0700g0bdh6 = { 1999 .modes = &edt_etm0700g0dh6_mode, 2000 .num_modes = 1, 2001 .bpc = 6, 2002 .size = { 2003 .width = 152, 2004 .height = 91, 2005 }, 2006 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2007 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2008 .connector_type = DRM_MODE_CONNECTOR_DPI, 2009 }; 2010 2011 static const struct display_timing edt_etml0700y5dha_timing = { 2012 .pixelclock = { 40800000, 51200000, 67200000 }, 2013 .hactive = { 1024, 1024, 1024 }, 2014 .hfront_porch = { 30, 106, 125 }, 2015 .hback_porch = { 30, 106, 125 }, 2016 .hsync_len = { 30, 108, 126 }, 2017 .vactive = { 600, 600, 600 }, 2018 .vfront_porch = { 3, 12, 67}, 2019 .vback_porch = { 3, 12, 67 }, 2020 .vsync_len = { 4, 11, 66 }, 2021 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2022 DISPLAY_FLAGS_DE_HIGH, 2023 }; 2024 2025 static const struct panel_desc edt_etml0700y5dha = { 2026 .timings = &edt_etml0700y5dha_timing, 2027 .num_timings = 1, 2028 .bpc = 8, 2029 .size = { 2030 .width = 155, 2031 .height = 86, 2032 }, 2033 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2034 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2035 }; 2036 2037 static const struct display_timing edt_etml1010g3dra_timing = { 2038 .pixelclock = { 66300000, 72400000, 78900000 }, 2039 .hactive = { 1280, 1280, 1280 }, 2040 .hfront_porch = { 12, 72, 132 }, 2041 .hback_porch = { 86, 86, 86 }, 2042 .hsync_len = { 2, 2, 2 }, 2043 .vactive = { 800, 800, 800 }, 2044 .vfront_porch = { 1, 15, 49 }, 2045 .vback_porch = { 21, 21, 21 }, 2046 .vsync_len = { 2, 2, 2 }, 2047 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2048 DISPLAY_FLAGS_DE_HIGH, 2049 }; 2050 2051 static const struct panel_desc edt_etml1010g3dra = { 2052 .timings = &edt_etml1010g3dra_timing, 2053 .num_timings = 1, 2054 .bpc = 8, 2055 .size = { 2056 .width = 216, 2057 .height = 135, 2058 }, 2059 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2060 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2061 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2062 }; 2063 2064 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2065 .clock = 25175, 2066 .hdisplay = 640, 2067 .hsync_start = 640, 2068 .hsync_end = 640 + 16, 2069 .htotal = 640 + 16 + 30 + 114, 2070 .vdisplay = 480, 2071 .vsync_start = 480 + 10, 2072 .vsync_end = 480 + 10 + 3, 2073 .vtotal = 480 + 10 + 3 + 35, 2074 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2075 }; 2076 2077 static const struct panel_desc edt_etmv570g2dhu = { 2078 .modes = &edt_etmv570g2dhu_mode, 2079 .num_modes = 1, 2080 .bpc = 6, 2081 .size = { 2082 .width = 115, 2083 .height = 86, 2084 }, 2085 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2086 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2087 .connector_type = DRM_MODE_CONNECTOR_DPI, 2088 }; 2089 2090 static const struct display_timing eink_vb3300_kca_timing = { 2091 .pixelclock = { 40000000, 40000000, 40000000 }, 2092 .hactive = { 334, 334, 334 }, 2093 .hfront_porch = { 1, 1, 1 }, 2094 .hback_porch = { 1, 1, 1 }, 2095 .hsync_len = { 1, 1, 1 }, 2096 .vactive = { 1405, 1405, 1405 }, 2097 .vfront_porch = { 1, 1, 1 }, 2098 .vback_porch = { 1, 1, 1 }, 2099 .vsync_len = { 1, 1, 1 }, 2100 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2101 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2102 }; 2103 2104 static const struct panel_desc eink_vb3300_kca = { 2105 .timings = &eink_vb3300_kca_timing, 2106 .num_timings = 1, 2107 .bpc = 6, 2108 .size = { 2109 .width = 157, 2110 .height = 209, 2111 }, 2112 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2113 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2114 .connector_type = DRM_MODE_CONNECTOR_DPI, 2115 }; 2116 2117 static const struct display_timing evervision_vgg644804_timing = { 2118 .pixelclock = { 25175000, 25175000, 25175000 }, 2119 .hactive = { 640, 640, 640 }, 2120 .hfront_porch = { 16, 16, 16 }, 2121 .hback_porch = { 82, 114, 170 }, 2122 .hsync_len = { 5, 30, 30 }, 2123 .vactive = { 480, 480, 480 }, 2124 .vfront_porch = { 10, 10, 10 }, 2125 .vback_porch = { 30, 32, 34 }, 2126 .vsync_len = { 1, 3, 5 }, 2127 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2128 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2129 DISPLAY_FLAGS_SYNC_POSEDGE, 2130 }; 2131 2132 static const struct panel_desc evervision_vgg644804 = { 2133 .timings = &evervision_vgg644804_timing, 2134 .num_timings = 1, 2135 .bpc = 8, 2136 .size = { 2137 .width = 115, 2138 .height = 86, 2139 }, 2140 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2141 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2142 }; 2143 2144 static const struct display_timing evervision_vgg804821_timing = { 2145 .pixelclock = { 27600000, 33300000, 50000000 }, 2146 .hactive = { 800, 800, 800 }, 2147 .hfront_porch = { 40, 66, 70 }, 2148 .hback_porch = { 40, 67, 70 }, 2149 .hsync_len = { 40, 67, 70 }, 2150 .vactive = { 480, 480, 480 }, 2151 .vfront_porch = { 6, 10, 10 }, 2152 .vback_porch = { 7, 11, 11 }, 2153 .vsync_len = { 7, 11, 11 }, 2154 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2155 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2156 DISPLAY_FLAGS_SYNC_NEGEDGE, 2157 }; 2158 2159 static const struct panel_desc evervision_vgg804821 = { 2160 .timings = &evervision_vgg804821_timing, 2161 .num_timings = 1, 2162 .bpc = 8, 2163 .size = { 2164 .width = 108, 2165 .height = 64, 2166 }, 2167 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2168 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2169 }; 2170 2171 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2172 .clock = 32260, 2173 .hdisplay = 800, 2174 .hsync_start = 800 + 168, 2175 .hsync_end = 800 + 168 + 64, 2176 .htotal = 800 + 168 + 64 + 88, 2177 .vdisplay = 480, 2178 .vsync_start = 480 + 37, 2179 .vsync_end = 480 + 37 + 2, 2180 .vtotal = 480 + 37 + 2 + 8, 2181 }; 2182 2183 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2184 .modes = &foxlink_fl500wvr00_a0t_mode, 2185 .num_modes = 1, 2186 .bpc = 8, 2187 .size = { 2188 .width = 108, 2189 .height = 65, 2190 }, 2191 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2192 }; 2193 2194 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2195 { /* 60 Hz */ 2196 .clock = 6000, 2197 .hdisplay = 320, 2198 .hsync_start = 320 + 44, 2199 .hsync_end = 320 + 44 + 16, 2200 .htotal = 320 + 44 + 16 + 20, 2201 .vdisplay = 240, 2202 .vsync_start = 240 + 2, 2203 .vsync_end = 240 + 2 + 6, 2204 .vtotal = 240 + 2 + 6 + 2, 2205 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2206 }, 2207 { /* 50 Hz */ 2208 .clock = 5400, 2209 .hdisplay = 320, 2210 .hsync_start = 320 + 56, 2211 .hsync_end = 320 + 56 + 16, 2212 .htotal = 320 + 56 + 16 + 40, 2213 .vdisplay = 240, 2214 .vsync_start = 240 + 2, 2215 .vsync_end = 240 + 2 + 6, 2216 .vtotal = 240 + 2 + 6 + 2, 2217 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2218 }, 2219 }; 2220 2221 static const struct panel_desc frida_frd350h54004 = { 2222 .modes = frida_frd350h54004_modes, 2223 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2224 .bpc = 8, 2225 .size = { 2226 .width = 77, 2227 .height = 64, 2228 }, 2229 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2230 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2231 .connector_type = DRM_MODE_CONNECTOR_DPI, 2232 }; 2233 2234 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2235 .clock = 67185, 2236 .hdisplay = 800, 2237 .hsync_start = 800 + 20, 2238 .hsync_end = 800 + 20 + 24, 2239 .htotal = 800 + 20 + 24 + 20, 2240 .vdisplay = 1280, 2241 .vsync_start = 1280 + 4, 2242 .vsync_end = 1280 + 4 + 8, 2243 .vtotal = 1280 + 4 + 8 + 4, 2244 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2245 }; 2246 2247 static const struct panel_desc friendlyarm_hd702e = { 2248 .modes = &friendlyarm_hd702e_mode, 2249 .num_modes = 1, 2250 .size = { 2251 .width = 94, 2252 .height = 151, 2253 }, 2254 }; 2255 2256 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2257 .clock = 9000, 2258 .hdisplay = 480, 2259 .hsync_start = 480 + 5, 2260 .hsync_end = 480 + 5 + 1, 2261 .htotal = 480 + 5 + 1 + 40, 2262 .vdisplay = 272, 2263 .vsync_start = 272 + 8, 2264 .vsync_end = 272 + 8 + 1, 2265 .vtotal = 272 + 8 + 1 + 8, 2266 }; 2267 2268 static const struct panel_desc giantplus_gpg482739qs5 = { 2269 .modes = &giantplus_gpg482739qs5_mode, 2270 .num_modes = 1, 2271 .bpc = 8, 2272 .size = { 2273 .width = 95, 2274 .height = 54, 2275 }, 2276 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2277 }; 2278 2279 static const struct display_timing giantplus_gpm940b0_timing = { 2280 .pixelclock = { 13500000, 27000000, 27500000 }, 2281 .hactive = { 320, 320, 320 }, 2282 .hfront_porch = { 14, 686, 718 }, 2283 .hback_porch = { 50, 70, 255 }, 2284 .hsync_len = { 1, 1, 1 }, 2285 .vactive = { 240, 240, 240 }, 2286 .vfront_porch = { 1, 1, 179 }, 2287 .vback_porch = { 1, 21, 31 }, 2288 .vsync_len = { 1, 1, 6 }, 2289 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2290 }; 2291 2292 static const struct panel_desc giantplus_gpm940b0 = { 2293 .timings = &giantplus_gpm940b0_timing, 2294 .num_timings = 1, 2295 .bpc = 8, 2296 .size = { 2297 .width = 60, 2298 .height = 45, 2299 }, 2300 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2301 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2302 }; 2303 2304 static const struct display_timing hannstar_hsd070pww1_timing = { 2305 .pixelclock = { 64300000, 71100000, 82000000 }, 2306 .hactive = { 1280, 1280, 1280 }, 2307 .hfront_porch = { 1, 1, 10 }, 2308 .hback_porch = { 1, 1, 10 }, 2309 /* 2310 * According to the data sheet, the minimum horizontal blanking interval 2311 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2312 * minimum working horizontal blanking interval to be 60 clocks. 2313 */ 2314 .hsync_len = { 58, 158, 661 }, 2315 .vactive = { 800, 800, 800 }, 2316 .vfront_porch = { 1, 1, 10 }, 2317 .vback_porch = { 1, 1, 10 }, 2318 .vsync_len = { 1, 21, 203 }, 2319 .flags = DISPLAY_FLAGS_DE_HIGH, 2320 }; 2321 2322 static const struct panel_desc hannstar_hsd070pww1 = { 2323 .timings = &hannstar_hsd070pww1_timing, 2324 .num_timings = 1, 2325 .bpc = 6, 2326 .size = { 2327 .width = 151, 2328 .height = 94, 2329 }, 2330 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2331 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2332 }; 2333 2334 static const struct display_timing hannstar_hsd100pxn1_timing = { 2335 .pixelclock = { 55000000, 65000000, 75000000 }, 2336 .hactive = { 1024, 1024, 1024 }, 2337 .hfront_porch = { 40, 40, 40 }, 2338 .hback_porch = { 220, 220, 220 }, 2339 .hsync_len = { 20, 60, 100 }, 2340 .vactive = { 768, 768, 768 }, 2341 .vfront_porch = { 7, 7, 7 }, 2342 .vback_porch = { 21, 21, 21 }, 2343 .vsync_len = { 10, 10, 10 }, 2344 .flags = DISPLAY_FLAGS_DE_HIGH, 2345 }; 2346 2347 static const struct panel_desc hannstar_hsd100pxn1 = { 2348 .timings = &hannstar_hsd100pxn1_timing, 2349 .num_timings = 1, 2350 .bpc = 6, 2351 .size = { 2352 .width = 203, 2353 .height = 152, 2354 }, 2355 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2356 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2357 }; 2358 2359 static const struct display_timing hannstar_hsd101pww2_timing = { 2360 .pixelclock = { 64300000, 71100000, 82000000 }, 2361 .hactive = { 1280, 1280, 1280 }, 2362 .hfront_porch = { 1, 1, 10 }, 2363 .hback_porch = { 1, 1, 10 }, 2364 .hsync_len = { 58, 158, 661 }, 2365 .vactive = { 800, 800, 800 }, 2366 .vfront_porch = { 1, 1, 10 }, 2367 .vback_porch = { 1, 1, 10 }, 2368 .vsync_len = { 1, 21, 203 }, 2369 .flags = DISPLAY_FLAGS_DE_HIGH, 2370 }; 2371 2372 static const struct panel_desc hannstar_hsd101pww2 = { 2373 .timings = &hannstar_hsd101pww2_timing, 2374 .num_timings = 1, 2375 .bpc = 8, 2376 .size = { 2377 .width = 217, 2378 .height = 136, 2379 }, 2380 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2381 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2382 }; 2383 2384 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2385 .clock = 33333, 2386 .hdisplay = 800, 2387 .hsync_start = 800 + 85, 2388 .hsync_end = 800 + 85 + 86, 2389 .htotal = 800 + 85 + 86 + 85, 2390 .vdisplay = 480, 2391 .vsync_start = 480 + 16, 2392 .vsync_end = 480 + 16 + 13, 2393 .vtotal = 480 + 16 + 13 + 16, 2394 }; 2395 2396 static const struct panel_desc hitachi_tx23d38vm0caa = { 2397 .modes = &hitachi_tx23d38vm0caa_mode, 2398 .num_modes = 1, 2399 .bpc = 6, 2400 .size = { 2401 .width = 195, 2402 .height = 117, 2403 }, 2404 .delay = { 2405 .enable = 160, 2406 .disable = 160, 2407 }, 2408 }; 2409 2410 static const struct drm_display_mode innolux_at043tn24_mode = { 2411 .clock = 9000, 2412 .hdisplay = 480, 2413 .hsync_start = 480 + 2, 2414 .hsync_end = 480 + 2 + 41, 2415 .htotal = 480 + 2 + 41 + 2, 2416 .vdisplay = 272, 2417 .vsync_start = 272 + 2, 2418 .vsync_end = 272 + 2 + 10, 2419 .vtotal = 272 + 2 + 10 + 2, 2420 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2421 }; 2422 2423 static const struct panel_desc innolux_at043tn24 = { 2424 .modes = &innolux_at043tn24_mode, 2425 .num_modes = 1, 2426 .bpc = 8, 2427 .size = { 2428 .width = 95, 2429 .height = 54, 2430 }, 2431 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2432 .connector_type = DRM_MODE_CONNECTOR_DPI, 2433 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2434 }; 2435 2436 static const struct drm_display_mode innolux_at070tn92_mode = { 2437 .clock = 33333, 2438 .hdisplay = 800, 2439 .hsync_start = 800 + 210, 2440 .hsync_end = 800 + 210 + 20, 2441 .htotal = 800 + 210 + 20 + 46, 2442 .vdisplay = 480, 2443 .vsync_start = 480 + 22, 2444 .vsync_end = 480 + 22 + 10, 2445 .vtotal = 480 + 22 + 23 + 10, 2446 }; 2447 2448 static const struct panel_desc innolux_at070tn92 = { 2449 .modes = &innolux_at070tn92_mode, 2450 .num_modes = 1, 2451 .size = { 2452 .width = 154, 2453 .height = 86, 2454 }, 2455 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2456 }; 2457 2458 static const struct display_timing innolux_g070ace_l01_timing = { 2459 .pixelclock = { 25200000, 35000000, 35700000 }, 2460 .hactive = { 800, 800, 800 }, 2461 .hfront_porch = { 30, 32, 87 }, 2462 .hback_porch = { 30, 32, 87 }, 2463 .hsync_len = { 1, 1, 1 }, 2464 .vactive = { 480, 480, 480 }, 2465 .vfront_porch = { 3, 3, 3 }, 2466 .vback_porch = { 13, 13, 13 }, 2467 .vsync_len = { 1, 1, 4 }, 2468 .flags = DISPLAY_FLAGS_DE_HIGH, 2469 }; 2470 2471 static const struct panel_desc innolux_g070ace_l01 = { 2472 .timings = &innolux_g070ace_l01_timing, 2473 .num_timings = 1, 2474 .bpc = 8, 2475 .size = { 2476 .width = 152, 2477 .height = 91, 2478 }, 2479 .delay = { 2480 .prepare = 10, 2481 .enable = 50, 2482 .disable = 50, 2483 .unprepare = 500, 2484 }, 2485 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2486 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2487 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2488 }; 2489 2490 static const struct display_timing innolux_g070y2_l01_timing = { 2491 .pixelclock = { 28000000, 29500000, 32000000 }, 2492 .hactive = { 800, 800, 800 }, 2493 .hfront_porch = { 61, 91, 141 }, 2494 .hback_porch = { 60, 90, 140 }, 2495 .hsync_len = { 12, 12, 12 }, 2496 .vactive = { 480, 480, 480 }, 2497 .vfront_porch = { 4, 9, 30 }, 2498 .vback_porch = { 4, 8, 28 }, 2499 .vsync_len = { 2, 2, 2 }, 2500 .flags = DISPLAY_FLAGS_DE_HIGH, 2501 }; 2502 2503 static const struct panel_desc innolux_g070y2_l01 = { 2504 .timings = &innolux_g070y2_l01_timing, 2505 .num_timings = 1, 2506 .bpc = 8, 2507 .size = { 2508 .width = 152, 2509 .height = 91, 2510 }, 2511 .delay = { 2512 .prepare = 10, 2513 .enable = 100, 2514 .disable = 100, 2515 .unprepare = 800, 2516 }, 2517 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2518 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2519 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2520 }; 2521 2522 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2523 .clock = 33333, 2524 .hdisplay = 800, 2525 .hsync_start = 800 + 210, 2526 .hsync_end = 800 + 210 + 20, 2527 .htotal = 800 + 210 + 20 + 46, 2528 .vdisplay = 480, 2529 .vsync_start = 480 + 22, 2530 .vsync_end = 480 + 22 + 10, 2531 .vtotal = 480 + 22 + 23 + 10, 2532 }; 2533 2534 static const struct panel_desc innolux_g070y2_t02 = { 2535 .modes = &innolux_g070y2_t02_mode, 2536 .num_modes = 1, 2537 .bpc = 8, 2538 .size = { 2539 .width = 152, 2540 .height = 92, 2541 }, 2542 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2543 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2544 .connector_type = DRM_MODE_CONNECTOR_DPI, 2545 }; 2546 2547 static const struct display_timing innolux_g101ice_l01_timing = { 2548 .pixelclock = { 60400000, 71100000, 74700000 }, 2549 .hactive = { 1280, 1280, 1280 }, 2550 .hfront_porch = { 30, 60, 70 }, 2551 .hback_porch = { 30, 60, 70 }, 2552 .hsync_len = { 22, 40, 60 }, 2553 .vactive = { 800, 800, 800 }, 2554 .vfront_porch = { 3, 8, 14 }, 2555 .vback_porch = { 3, 8, 14 }, 2556 .vsync_len = { 4, 7, 12 }, 2557 .flags = DISPLAY_FLAGS_DE_HIGH, 2558 }; 2559 2560 static const struct panel_desc innolux_g101ice_l01 = { 2561 .timings = &innolux_g101ice_l01_timing, 2562 .num_timings = 1, 2563 .bpc = 8, 2564 .size = { 2565 .width = 217, 2566 .height = 135, 2567 }, 2568 .delay = { 2569 .enable = 200, 2570 .disable = 200, 2571 }, 2572 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2573 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2574 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2575 }; 2576 2577 static const struct display_timing innolux_g121i1_l01_timing = { 2578 .pixelclock = { 67450000, 71000000, 74550000 }, 2579 .hactive = { 1280, 1280, 1280 }, 2580 .hfront_porch = { 40, 80, 160 }, 2581 .hback_porch = { 39, 79, 159 }, 2582 .hsync_len = { 1, 1, 1 }, 2583 .vactive = { 800, 800, 800 }, 2584 .vfront_porch = { 5, 11, 100 }, 2585 .vback_porch = { 4, 11, 99 }, 2586 .vsync_len = { 1, 1, 1 }, 2587 }; 2588 2589 static const struct panel_desc innolux_g121i1_l01 = { 2590 .timings = &innolux_g121i1_l01_timing, 2591 .num_timings = 1, 2592 .bpc = 6, 2593 .size = { 2594 .width = 261, 2595 .height = 163, 2596 }, 2597 .delay = { 2598 .enable = 200, 2599 .disable = 20, 2600 }, 2601 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2602 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2603 }; 2604 2605 static const struct display_timing innolux_g121x1_l03_timings = { 2606 .pixelclock = { 57500000, 64900000, 74400000 }, 2607 .hactive = { 1024, 1024, 1024 }, 2608 .hfront_porch = { 90, 140, 190 }, 2609 .hback_porch = { 90, 140, 190 }, 2610 .hsync_len = { 36, 40, 60 }, 2611 .vactive = { 768, 768, 768 }, 2612 .vfront_porch = { 2, 15, 30 }, 2613 .vback_porch = { 2, 15, 30 }, 2614 .vsync_len = { 2, 8, 20 }, 2615 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2616 }; 2617 2618 static const struct panel_desc innolux_g121x1_l03 = { 2619 .timings = &innolux_g121x1_l03_timings, 2620 .num_timings = 1, 2621 .bpc = 6, 2622 .size = { 2623 .width = 246, 2624 .height = 185, 2625 }, 2626 .delay = { 2627 .enable = 200, 2628 .unprepare = 200, 2629 .disable = 400, 2630 }, 2631 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2632 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2633 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2634 }; 2635 2636 static const struct panel_desc innolux_g121xce_l01 = { 2637 .timings = &innolux_g121x1_l03_timings, 2638 .num_timings = 1, 2639 .bpc = 8, 2640 .size = { 2641 .width = 246, 2642 .height = 185, 2643 }, 2644 .delay = { 2645 .enable = 200, 2646 .unprepare = 200, 2647 .disable = 400, 2648 }, 2649 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2650 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2651 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2652 }; 2653 2654 static const struct display_timing innolux_g156hce_l01_timings = { 2655 .pixelclock = { 120000000, 141860000, 150000000 }, 2656 .hactive = { 1920, 1920, 1920 }, 2657 .hfront_porch = { 80, 90, 100 }, 2658 .hback_porch = { 80, 90, 100 }, 2659 .hsync_len = { 20, 30, 30 }, 2660 .vactive = { 1080, 1080, 1080 }, 2661 .vfront_porch = { 3, 10, 20 }, 2662 .vback_porch = { 3, 10, 20 }, 2663 .vsync_len = { 4, 10, 10 }, 2664 }; 2665 2666 static const struct panel_desc innolux_g156hce_l01 = { 2667 .timings = &innolux_g156hce_l01_timings, 2668 .num_timings = 1, 2669 .bpc = 8, 2670 .size = { 2671 .width = 344, 2672 .height = 194, 2673 }, 2674 .delay = { 2675 .prepare = 1, /* T1+T2 */ 2676 .enable = 450, /* T5 */ 2677 .disable = 200, /* T6 */ 2678 .unprepare = 10, /* T3+T7 */ 2679 }, 2680 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2681 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2682 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2683 }; 2684 2685 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2686 .clock = 69300, 2687 .hdisplay = 1366, 2688 .hsync_start = 1366 + 16, 2689 .hsync_end = 1366 + 16 + 34, 2690 .htotal = 1366 + 16 + 34 + 50, 2691 .vdisplay = 768, 2692 .vsync_start = 768 + 2, 2693 .vsync_end = 768 + 2 + 6, 2694 .vtotal = 768 + 2 + 6 + 12, 2695 }; 2696 2697 static const struct panel_desc innolux_n156bge_l21 = { 2698 .modes = &innolux_n156bge_l21_mode, 2699 .num_modes = 1, 2700 .bpc = 6, 2701 .size = { 2702 .width = 344, 2703 .height = 193, 2704 }, 2705 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2706 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2707 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2708 }; 2709 2710 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2711 .clock = 51501, 2712 .hdisplay = 1024, 2713 .hsync_start = 1024 + 128, 2714 .hsync_end = 1024 + 128 + 64, 2715 .htotal = 1024 + 128 + 64 + 128, 2716 .vdisplay = 600, 2717 .vsync_start = 600 + 16, 2718 .vsync_end = 600 + 16 + 4, 2719 .vtotal = 600 + 16 + 4 + 16, 2720 }; 2721 2722 static const struct panel_desc innolux_zj070na_01p = { 2723 .modes = &innolux_zj070na_01p_mode, 2724 .num_modes = 1, 2725 .bpc = 6, 2726 .size = { 2727 .width = 154, 2728 .height = 90, 2729 }, 2730 }; 2731 2732 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2733 .pixelclock = { 5580000, 5850000, 6200000 }, 2734 .hactive = { 320, 320, 320 }, 2735 .hfront_porch = { 30, 30, 30 }, 2736 .hback_porch = { 30, 30, 30 }, 2737 .hsync_len = { 1, 5, 17 }, 2738 .vactive = { 240, 240, 240 }, 2739 .vfront_porch = { 6, 6, 6 }, 2740 .vback_porch = { 5, 5, 5 }, 2741 .vsync_len = { 1, 2, 11 }, 2742 .flags = DISPLAY_FLAGS_DE_HIGH, 2743 }; 2744 2745 static const struct panel_desc koe_tx14d24vm1bpa = { 2746 .timings = &koe_tx14d24vm1bpa_timing, 2747 .num_timings = 1, 2748 .bpc = 6, 2749 .size = { 2750 .width = 115, 2751 .height = 86, 2752 }, 2753 }; 2754 2755 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2756 .pixelclock = { 151820000, 156720000, 159780000 }, 2757 .hactive = { 1920, 1920, 1920 }, 2758 .hfront_porch = { 105, 130, 142 }, 2759 .hback_porch = { 45, 70, 82 }, 2760 .hsync_len = { 30, 30, 30 }, 2761 .vactive = { 1200, 1200, 1200}, 2762 .vfront_porch = { 3, 5, 10 }, 2763 .vback_porch = { 2, 5, 10 }, 2764 .vsync_len = { 5, 5, 5 }, 2765 }; 2766 2767 static const struct panel_desc koe_tx26d202vm0bwa = { 2768 .timings = &koe_tx26d202vm0bwa_timing, 2769 .num_timings = 1, 2770 .bpc = 8, 2771 .size = { 2772 .width = 217, 2773 .height = 136, 2774 }, 2775 .delay = { 2776 .prepare = 1000, 2777 .enable = 1000, 2778 .unprepare = 1000, 2779 .disable = 1000, 2780 }, 2781 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2782 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2783 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2784 }; 2785 2786 static const struct display_timing koe_tx31d200vm0baa_timing = { 2787 .pixelclock = { 39600000, 43200000, 48000000 }, 2788 .hactive = { 1280, 1280, 1280 }, 2789 .hfront_porch = { 16, 36, 56 }, 2790 .hback_porch = { 16, 36, 56 }, 2791 .hsync_len = { 8, 8, 8 }, 2792 .vactive = { 480, 480, 480 }, 2793 .vfront_porch = { 6, 21, 33 }, 2794 .vback_porch = { 6, 21, 33 }, 2795 .vsync_len = { 8, 8, 8 }, 2796 .flags = DISPLAY_FLAGS_DE_HIGH, 2797 }; 2798 2799 static const struct panel_desc koe_tx31d200vm0baa = { 2800 .timings = &koe_tx31d200vm0baa_timing, 2801 .num_timings = 1, 2802 .bpc = 6, 2803 .size = { 2804 .width = 292, 2805 .height = 109, 2806 }, 2807 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2808 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2809 }; 2810 2811 static const struct display_timing kyo_tcg121xglp_timing = { 2812 .pixelclock = { 52000000, 65000000, 71000000 }, 2813 .hactive = { 1024, 1024, 1024 }, 2814 .hfront_porch = { 2, 2, 2 }, 2815 .hback_porch = { 2, 2, 2 }, 2816 .hsync_len = { 86, 124, 244 }, 2817 .vactive = { 768, 768, 768 }, 2818 .vfront_porch = { 2, 2, 2 }, 2819 .vback_porch = { 2, 2, 2 }, 2820 .vsync_len = { 6, 34, 73 }, 2821 .flags = DISPLAY_FLAGS_DE_HIGH, 2822 }; 2823 2824 static const struct panel_desc kyo_tcg121xglp = { 2825 .timings = &kyo_tcg121xglp_timing, 2826 .num_timings = 1, 2827 .bpc = 8, 2828 .size = { 2829 .width = 246, 2830 .height = 184, 2831 }, 2832 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2833 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2834 }; 2835 2836 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2837 .clock = 7000, 2838 .hdisplay = 320, 2839 .hsync_start = 320 + 20, 2840 .hsync_end = 320 + 20 + 30, 2841 .htotal = 320 + 20 + 30 + 38, 2842 .vdisplay = 240, 2843 .vsync_start = 240 + 4, 2844 .vsync_end = 240 + 4 + 3, 2845 .vtotal = 240 + 4 + 3 + 15, 2846 }; 2847 2848 static const struct panel_desc lemaker_bl035_rgb_002 = { 2849 .modes = &lemaker_bl035_rgb_002_mode, 2850 .num_modes = 1, 2851 .size = { 2852 .width = 70, 2853 .height = 52, 2854 }, 2855 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2856 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2857 }; 2858 2859 static const struct display_timing lg_lb070wv8_timing = { 2860 .pixelclock = { 31950000, 33260000, 34600000 }, 2861 .hactive = { 800, 800, 800 }, 2862 .hfront_porch = { 88, 88, 88 }, 2863 .hback_porch = { 88, 88, 88 }, 2864 .hsync_len = { 80, 80, 80 }, 2865 .vactive = { 480, 480, 480 }, 2866 .vfront_porch = { 10, 10, 10 }, 2867 .vback_porch = { 10, 10, 10 }, 2868 .vsync_len = { 25, 25, 25 }, 2869 }; 2870 2871 static const struct panel_desc lg_lb070wv8 = { 2872 .timings = &lg_lb070wv8_timing, 2873 .num_timings = 1, 2874 .bpc = 8, 2875 .size = { 2876 .width = 151, 2877 .height = 91, 2878 }, 2879 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2880 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2881 }; 2882 2883 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 2884 .clock = 155127, 2885 .hdisplay = 1920, 2886 .hsync_start = 1920 + 128, 2887 .hsync_end = 1920 + 128 + 20, 2888 .htotal = 1920 + 128 + 20 + 12, 2889 .vdisplay = 1200, 2890 .vsync_start = 1200 + 19, 2891 .vsync_end = 1200 + 19 + 4, 2892 .vtotal = 1200 + 19 + 4 + 20, 2893 }; 2894 2895 static const struct panel_desc lincolntech_lcd185_101ct = { 2896 .modes = &lincolntech_lcd185_101ct_mode, 2897 .bpc = 8, 2898 .num_modes = 1, 2899 .size = { 2900 .width = 217, 2901 .height = 136, 2902 }, 2903 .delay = { 2904 .prepare = 50, 2905 .disable = 50, 2906 }, 2907 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2908 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2909 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2910 }; 2911 2912 static const struct display_timing logictechno_lt161010_2nh_timing = { 2913 .pixelclock = { 26400000, 33300000, 46800000 }, 2914 .hactive = { 800, 800, 800 }, 2915 .hfront_porch = { 16, 210, 354 }, 2916 .hback_porch = { 46, 46, 46 }, 2917 .hsync_len = { 1, 20, 40 }, 2918 .vactive = { 480, 480, 480 }, 2919 .vfront_porch = { 7, 22, 147 }, 2920 .vback_porch = { 23, 23, 23 }, 2921 .vsync_len = { 1, 10, 20 }, 2922 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2923 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2924 DISPLAY_FLAGS_SYNC_POSEDGE, 2925 }; 2926 2927 static const struct panel_desc logictechno_lt161010_2nh = { 2928 .timings = &logictechno_lt161010_2nh_timing, 2929 .num_timings = 1, 2930 .bpc = 6, 2931 .size = { 2932 .width = 154, 2933 .height = 86, 2934 }, 2935 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2936 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2937 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2938 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2939 .connector_type = DRM_MODE_CONNECTOR_DPI, 2940 }; 2941 2942 static const struct display_timing logictechno_lt170410_2whc_timing = { 2943 .pixelclock = { 68900000, 71100000, 73400000 }, 2944 .hactive = { 1280, 1280, 1280 }, 2945 .hfront_porch = { 23, 60, 71 }, 2946 .hback_porch = { 23, 60, 71 }, 2947 .hsync_len = { 15, 40, 47 }, 2948 .vactive = { 800, 800, 800 }, 2949 .vfront_porch = { 5, 7, 10 }, 2950 .vback_porch = { 5, 7, 10 }, 2951 .vsync_len = { 6, 9, 12 }, 2952 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2953 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2954 DISPLAY_FLAGS_SYNC_POSEDGE, 2955 }; 2956 2957 static const struct panel_desc logictechno_lt170410_2whc = { 2958 .timings = &logictechno_lt170410_2whc_timing, 2959 .num_timings = 1, 2960 .bpc = 8, 2961 .size = { 2962 .width = 217, 2963 .height = 136, 2964 }, 2965 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2966 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2967 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2968 }; 2969 2970 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2971 .clock = 33000, 2972 .hdisplay = 800, 2973 .hsync_start = 800 + 112, 2974 .hsync_end = 800 + 112 + 3, 2975 .htotal = 800 + 112 + 3 + 85, 2976 .vdisplay = 480, 2977 .vsync_start = 480 + 38, 2978 .vsync_end = 480 + 38 + 3, 2979 .vtotal = 480 + 38 + 3 + 29, 2980 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2981 }; 2982 2983 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2984 .modes = &logictechno_lttd800480070_l2rt_mode, 2985 .num_modes = 1, 2986 .bpc = 8, 2987 .size = { 2988 .width = 154, 2989 .height = 86, 2990 }, 2991 .delay = { 2992 .prepare = 45, 2993 .enable = 100, 2994 .disable = 100, 2995 .unprepare = 45 2996 }, 2997 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2998 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2999 .connector_type = DRM_MODE_CONNECTOR_DPI, 3000 }; 3001 3002 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3003 .clock = 33000, 3004 .hdisplay = 800, 3005 .hsync_start = 800 + 154, 3006 .hsync_end = 800 + 154 + 3, 3007 .htotal = 800 + 154 + 3 + 43, 3008 .vdisplay = 480, 3009 .vsync_start = 480 + 47, 3010 .vsync_end = 480 + 47 + 3, 3011 .vtotal = 480 + 47 + 3 + 20, 3012 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3013 }; 3014 3015 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3016 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3017 .num_modes = 1, 3018 .bpc = 8, 3019 .size = { 3020 .width = 154, 3021 .height = 86, 3022 }, 3023 .delay = { 3024 .prepare = 45, 3025 .enable = 100, 3026 .disable = 100, 3027 .unprepare = 45 3028 }, 3029 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3030 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3031 .connector_type = DRM_MODE_CONNECTOR_DPI, 3032 }; 3033 3034 static const struct drm_display_mode logicpd_type_28_mode = { 3035 .clock = 9107, 3036 .hdisplay = 480, 3037 .hsync_start = 480 + 3, 3038 .hsync_end = 480 + 3 + 42, 3039 .htotal = 480 + 3 + 42 + 2, 3040 3041 .vdisplay = 272, 3042 .vsync_start = 272 + 2, 3043 .vsync_end = 272 + 2 + 11, 3044 .vtotal = 272 + 2 + 11 + 3, 3045 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3046 }; 3047 3048 static const struct panel_desc logicpd_type_28 = { 3049 .modes = &logicpd_type_28_mode, 3050 .num_modes = 1, 3051 .bpc = 8, 3052 .size = { 3053 .width = 105, 3054 .height = 67, 3055 }, 3056 .delay = { 3057 .prepare = 200, 3058 .enable = 200, 3059 .unprepare = 200, 3060 .disable = 200, 3061 }, 3062 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3063 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3064 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3065 .connector_type = DRM_MODE_CONNECTOR_DPI, 3066 }; 3067 3068 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3069 .clock = 150275, 3070 .hdisplay = 1920, 3071 .hsync_start = 1920 + 32, 3072 .hsync_end = 1920 + 32 + 52, 3073 .htotal = 1920 + 32 + 52 + 24, 3074 .vdisplay = 1200, 3075 .vsync_start = 1200 + 24, 3076 .vsync_end = 1200 + 24 + 8, 3077 .vtotal = 1200 + 24 + 8 + 3, 3078 }; 3079 3080 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3081 .modes = µtips_mf_101hiebcaf0_c_mode, 3082 .bpc = 8, 3083 .num_modes = 1, 3084 .size = { 3085 .width = 217, 3086 .height = 136, 3087 }, 3088 .delay = { 3089 .prepare = 50, 3090 .disable = 50, 3091 }, 3092 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3093 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3094 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3095 }; 3096 3097 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3098 .clock = 93301, 3099 .hdisplay = 1920, 3100 .hsync_start = 1920 + 72, 3101 .hsync_end = 1920 + 72 + 72, 3102 .htotal = 1920 + 72 + 72 + 72, 3103 .vdisplay = 720, 3104 .vsync_start = 720 + 3, 3105 .vsync_end = 720 + 3 + 3, 3106 .vtotal = 720 + 3 + 3 + 2, 3107 }; 3108 3109 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3110 .modes = µtips_mf_103hieb0ga0_mode, 3111 .bpc = 8, 3112 .num_modes = 1, 3113 .size = { 3114 .width = 244, 3115 .height = 92, 3116 }, 3117 .delay = { 3118 .prepare = 50, 3119 .disable = 50, 3120 }, 3121 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3122 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3123 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3124 }; 3125 3126 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3127 .clock = 30400, 3128 .hdisplay = 800, 3129 .hsync_start = 800 + 0, 3130 .hsync_end = 800 + 1, 3131 .htotal = 800 + 0 + 1 + 160, 3132 .vdisplay = 480, 3133 .vsync_start = 480 + 0, 3134 .vsync_end = 480 + 48 + 1, 3135 .vtotal = 480 + 48 + 1 + 0, 3136 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3137 }; 3138 3139 static const struct panel_desc mitsubishi_aa070mc01 = { 3140 .modes = &mitsubishi_aa070mc01_mode, 3141 .num_modes = 1, 3142 .bpc = 8, 3143 .size = { 3144 .width = 152, 3145 .height = 91, 3146 }, 3147 3148 .delay = { 3149 .enable = 200, 3150 .unprepare = 200, 3151 .disable = 400, 3152 }, 3153 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3154 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3155 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3156 }; 3157 3158 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3159 .clock = 56234, 3160 .hdisplay = 1024, 3161 .hsync_start = 1024 + 24, 3162 .hsync_end = 1024 + 24 + 63, 3163 .htotal = 1024 + 24 + 63 + 1, 3164 .vdisplay = 768, 3165 .vsync_start = 768 + 3, 3166 .vsync_end = 768 + 3 + 6, 3167 .vtotal = 768 + 3 + 6 + 1, 3168 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3169 }; 3170 3171 static const struct panel_desc mitsubishi_aa084xe01 = { 3172 .modes = &mitsubishi_aa084xe01_mode, 3173 .num_modes = 1, 3174 .bpc = 8, 3175 .size = { 3176 .width = 1024, 3177 .height = 768, 3178 }, 3179 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3180 .connector_type = DRM_MODE_CONNECTOR_DPI, 3181 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3182 }; 3183 3184 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3185 .pixelclock = { 29000000, 33000000, 38000000 }, 3186 .hactive = { 800, 800, 800 }, 3187 .hfront_porch = { 180, 210, 240 }, 3188 .hback_porch = { 16, 16, 16 }, 3189 .hsync_len = { 30, 30, 30 }, 3190 .vactive = { 480, 480, 480 }, 3191 .vfront_porch = { 12, 22, 32 }, 3192 .vback_porch = { 10, 10, 10 }, 3193 .vsync_len = { 13, 13, 13 }, 3194 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3195 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3196 DISPLAY_FLAGS_SYNC_POSEDGE, 3197 }; 3198 3199 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3200 .timings = &multi_inno_mi0700s4t_6_timing, 3201 .num_timings = 1, 3202 .bpc = 8, 3203 .size = { 3204 .width = 154, 3205 .height = 86, 3206 }, 3207 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3208 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3209 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3210 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3211 .connector_type = DRM_MODE_CONNECTOR_DPI, 3212 }; 3213 3214 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3215 .pixelclock = { 32000000, 40000000, 50000000 }, 3216 .hactive = { 800, 800, 800 }, 3217 .hfront_porch = { 16, 210, 354 }, 3218 .hback_porch = { 6, 26, 45 }, 3219 .hsync_len = { 1, 20, 40 }, 3220 .vactive = { 600, 600, 600 }, 3221 .vfront_porch = { 1, 12, 77 }, 3222 .vback_porch = { 3, 13, 22 }, 3223 .vsync_len = { 1, 10, 20 }, 3224 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3225 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3226 DISPLAY_FLAGS_SYNC_POSEDGE, 3227 }; 3228 3229 static const struct panel_desc multi_inno_mi0800ft_9 = { 3230 .timings = &multi_inno_mi0800ft_9_timing, 3231 .num_timings = 1, 3232 .bpc = 8, 3233 .size = { 3234 .width = 162, 3235 .height = 122, 3236 }, 3237 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3238 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3239 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3240 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3241 .connector_type = DRM_MODE_CONNECTOR_DPI, 3242 }; 3243 3244 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3245 .pixelclock = { 68900000, 70000000, 73400000 }, 3246 .hactive = { 1280, 1280, 1280 }, 3247 .hfront_porch = { 30, 60, 71 }, 3248 .hback_porch = { 30, 60, 71 }, 3249 .hsync_len = { 10, 10, 48 }, 3250 .vactive = { 800, 800, 800 }, 3251 .vfront_porch = { 5, 10, 10 }, 3252 .vback_porch = { 5, 10, 10 }, 3253 .vsync_len = { 5, 6, 13 }, 3254 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3255 DISPLAY_FLAGS_DE_HIGH, 3256 }; 3257 3258 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3259 .timings = &multi_inno_mi1010ait_1cp_timing, 3260 .num_timings = 1, 3261 .bpc = 8, 3262 .size = { 3263 .width = 217, 3264 .height = 136, 3265 }, 3266 .delay = { 3267 .enable = 50, 3268 .disable = 50, 3269 }, 3270 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3271 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3272 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3273 }; 3274 3275 static const struct display_timing nec_nl12880bc20_05_timing = { 3276 .pixelclock = { 67000000, 71000000, 75000000 }, 3277 .hactive = { 1280, 1280, 1280 }, 3278 .hfront_porch = { 2, 30, 30 }, 3279 .hback_porch = { 6, 100, 100 }, 3280 .hsync_len = { 2, 30, 30 }, 3281 .vactive = { 800, 800, 800 }, 3282 .vfront_porch = { 5, 5, 5 }, 3283 .vback_porch = { 11, 11, 11 }, 3284 .vsync_len = { 7, 7, 7 }, 3285 }; 3286 3287 static const struct panel_desc nec_nl12880bc20_05 = { 3288 .timings = &nec_nl12880bc20_05_timing, 3289 .num_timings = 1, 3290 .bpc = 8, 3291 .size = { 3292 .width = 261, 3293 .height = 163, 3294 }, 3295 .delay = { 3296 .enable = 50, 3297 .disable = 50, 3298 }, 3299 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3300 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3301 }; 3302 3303 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3304 .clock = 10870, 3305 .hdisplay = 480, 3306 .hsync_start = 480 + 2, 3307 .hsync_end = 480 + 2 + 41, 3308 .htotal = 480 + 2 + 41 + 2, 3309 .vdisplay = 272, 3310 .vsync_start = 272 + 2, 3311 .vsync_end = 272 + 2 + 4, 3312 .vtotal = 272 + 2 + 4 + 2, 3313 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3314 }; 3315 3316 static const struct panel_desc nec_nl4827hc19_05b = { 3317 .modes = &nec_nl4827hc19_05b_mode, 3318 .num_modes = 1, 3319 .bpc = 8, 3320 .size = { 3321 .width = 95, 3322 .height = 54, 3323 }, 3324 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3325 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3326 }; 3327 3328 static const struct drm_display_mode netron_dy_e231732_mode = { 3329 .clock = 66000, 3330 .hdisplay = 1024, 3331 .hsync_start = 1024 + 160, 3332 .hsync_end = 1024 + 160 + 70, 3333 .htotal = 1024 + 160 + 70 + 90, 3334 .vdisplay = 600, 3335 .vsync_start = 600 + 127, 3336 .vsync_end = 600 + 127 + 20, 3337 .vtotal = 600 + 127 + 20 + 3, 3338 }; 3339 3340 static const struct panel_desc netron_dy_e231732 = { 3341 .modes = &netron_dy_e231732_mode, 3342 .num_modes = 1, 3343 .size = { 3344 .width = 154, 3345 .height = 87, 3346 }, 3347 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3348 }; 3349 3350 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3351 .clock = 9000, 3352 .hdisplay = 480, 3353 .hsync_start = 480 + 2, 3354 .hsync_end = 480 + 2 + 41, 3355 .htotal = 480 + 2 + 41 + 2, 3356 .vdisplay = 272, 3357 .vsync_start = 272 + 2, 3358 .vsync_end = 272 + 2 + 10, 3359 .vtotal = 272 + 2 + 10 + 2, 3360 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3361 }; 3362 3363 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3364 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3365 .num_modes = 1, 3366 .bpc = 8, 3367 .size = { 3368 .width = 95, 3369 .height = 54, 3370 }, 3371 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3372 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3373 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3374 .connector_type = DRM_MODE_CONNECTOR_DPI, 3375 }; 3376 3377 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3378 .pixelclock = { 130000000, 148350000, 163000000 }, 3379 .hactive = { 1920, 1920, 1920 }, 3380 .hfront_porch = { 80, 100, 100 }, 3381 .hback_porch = { 100, 120, 120 }, 3382 .hsync_len = { 50, 60, 60 }, 3383 .vactive = { 1080, 1080, 1080 }, 3384 .vfront_porch = { 12, 30, 30 }, 3385 .vback_porch = { 4, 10, 10 }, 3386 .vsync_len = { 4, 5, 5 }, 3387 }; 3388 3389 static const struct panel_desc nlt_nl192108ac18_02d = { 3390 .timings = &nlt_nl192108ac18_02d_timing, 3391 .num_timings = 1, 3392 .bpc = 8, 3393 .size = { 3394 .width = 344, 3395 .height = 194, 3396 }, 3397 .delay = { 3398 .unprepare = 500, 3399 }, 3400 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3401 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3402 }; 3403 3404 static const struct drm_display_mode nvd_9128_mode = { 3405 .clock = 29500, 3406 .hdisplay = 800, 3407 .hsync_start = 800 + 130, 3408 .hsync_end = 800 + 130 + 98, 3409 .htotal = 800 + 0 + 130 + 98, 3410 .vdisplay = 480, 3411 .vsync_start = 480 + 10, 3412 .vsync_end = 480 + 10 + 50, 3413 .vtotal = 480 + 0 + 10 + 50, 3414 }; 3415 3416 static const struct panel_desc nvd_9128 = { 3417 .modes = &nvd_9128_mode, 3418 .num_modes = 1, 3419 .bpc = 8, 3420 .size = { 3421 .width = 156, 3422 .height = 88, 3423 }, 3424 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3425 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3426 }; 3427 3428 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3429 .pixelclock = { 30000000, 30000000, 40000000 }, 3430 .hactive = { 800, 800, 800 }, 3431 .hfront_porch = { 40, 40, 40 }, 3432 .hback_porch = { 40, 40, 40 }, 3433 .hsync_len = { 1, 48, 48 }, 3434 .vactive = { 480, 480, 480 }, 3435 .vfront_porch = { 13, 13, 13 }, 3436 .vback_porch = { 29, 29, 29 }, 3437 .vsync_len = { 3, 3, 3 }, 3438 .flags = DISPLAY_FLAGS_DE_HIGH, 3439 }; 3440 3441 static const struct panel_desc okaya_rs800480t_7x0gp = { 3442 .timings = &okaya_rs800480t_7x0gp_timing, 3443 .num_timings = 1, 3444 .bpc = 6, 3445 .size = { 3446 .width = 154, 3447 .height = 87, 3448 }, 3449 .delay = { 3450 .prepare = 41, 3451 .enable = 50, 3452 .unprepare = 41, 3453 .disable = 50, 3454 }, 3455 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3456 }; 3457 3458 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3459 .clock = 9000, 3460 .hdisplay = 480, 3461 .hsync_start = 480 + 5, 3462 .hsync_end = 480 + 5 + 30, 3463 .htotal = 480 + 5 + 30 + 10, 3464 .vdisplay = 272, 3465 .vsync_start = 272 + 8, 3466 .vsync_end = 272 + 8 + 5, 3467 .vtotal = 272 + 8 + 5 + 3, 3468 }; 3469 3470 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3471 .modes = &olimex_lcd_olinuxino_43ts_mode, 3472 .num_modes = 1, 3473 .size = { 3474 .width = 95, 3475 .height = 54, 3476 }, 3477 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3478 }; 3479 3480 /* 3481 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3482 * pixel clocks, but this is the timing that was being used in the Adafruit 3483 * installation instructions. 3484 */ 3485 static const struct drm_display_mode ontat_yx700wv03_mode = { 3486 .clock = 29500, 3487 .hdisplay = 800, 3488 .hsync_start = 824, 3489 .hsync_end = 896, 3490 .htotal = 992, 3491 .vdisplay = 480, 3492 .vsync_start = 483, 3493 .vsync_end = 493, 3494 .vtotal = 500, 3495 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3496 }; 3497 3498 /* 3499 * Specification at: 3500 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3501 */ 3502 static const struct panel_desc ontat_yx700wv03 = { 3503 .modes = &ontat_yx700wv03_mode, 3504 .num_modes = 1, 3505 .bpc = 8, 3506 .size = { 3507 .width = 154, 3508 .height = 83, 3509 }, 3510 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3511 }; 3512 3513 static const struct drm_display_mode ortustech_com37h3m_mode = { 3514 .clock = 22230, 3515 .hdisplay = 480, 3516 .hsync_start = 480 + 40, 3517 .hsync_end = 480 + 40 + 10, 3518 .htotal = 480 + 40 + 10 + 40, 3519 .vdisplay = 640, 3520 .vsync_start = 640 + 4, 3521 .vsync_end = 640 + 4 + 2, 3522 .vtotal = 640 + 4 + 2 + 4, 3523 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3524 }; 3525 3526 static const struct panel_desc ortustech_com37h3m = { 3527 .modes = &ortustech_com37h3m_mode, 3528 .num_modes = 1, 3529 .bpc = 8, 3530 .size = { 3531 .width = 56, /* 56.16mm */ 3532 .height = 75, /* 74.88mm */ 3533 }, 3534 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3535 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3536 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3537 }; 3538 3539 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3540 .clock = 25000, 3541 .hdisplay = 480, 3542 .hsync_start = 480 + 10, 3543 .hsync_end = 480 + 10 + 10, 3544 .htotal = 480 + 10 + 10 + 15, 3545 .vdisplay = 800, 3546 .vsync_start = 800 + 3, 3547 .vsync_end = 800 + 3 + 3, 3548 .vtotal = 800 + 3 + 3 + 3, 3549 }; 3550 3551 static const struct panel_desc ortustech_com43h4m85ulc = { 3552 .modes = &ortustech_com43h4m85ulc_mode, 3553 .num_modes = 1, 3554 .bpc = 6, 3555 .size = { 3556 .width = 56, 3557 .height = 93, 3558 }, 3559 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3560 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3561 .connector_type = DRM_MODE_CONNECTOR_DPI, 3562 }; 3563 3564 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3565 .clock = 33000, 3566 .hdisplay = 800, 3567 .hsync_start = 800 + 210, 3568 .hsync_end = 800 + 210 + 30, 3569 .htotal = 800 + 210 + 30 + 16, 3570 .vdisplay = 480, 3571 .vsync_start = 480 + 22, 3572 .vsync_end = 480 + 22 + 13, 3573 .vtotal = 480 + 22 + 13 + 10, 3574 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3575 }; 3576 3577 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3578 .modes = &osddisplays_osd070t1718_19ts_mode, 3579 .num_modes = 1, 3580 .bpc = 8, 3581 .size = { 3582 .width = 152, 3583 .height = 91, 3584 }, 3585 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3586 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3587 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3588 .connector_type = DRM_MODE_CONNECTOR_DPI, 3589 }; 3590 3591 static const struct drm_display_mode pda_91_00156_a0_mode = { 3592 .clock = 33300, 3593 .hdisplay = 800, 3594 .hsync_start = 800 + 1, 3595 .hsync_end = 800 + 1 + 64, 3596 .htotal = 800 + 1 + 64 + 64, 3597 .vdisplay = 480, 3598 .vsync_start = 480 + 1, 3599 .vsync_end = 480 + 1 + 23, 3600 .vtotal = 480 + 1 + 23 + 22, 3601 }; 3602 3603 static const struct panel_desc pda_91_00156_a0 = { 3604 .modes = &pda_91_00156_a0_mode, 3605 .num_modes = 1, 3606 .size = { 3607 .width = 152, 3608 .height = 91, 3609 }, 3610 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3611 }; 3612 3613 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 3614 .clock = 66500, 3615 .hdisplay = 1280, 3616 .hsync_start = 1280 + 12, 3617 .hsync_end = 1280 + 12 + 20, 3618 .htotal = 1280 + 12 + 20 + 56, 3619 .vdisplay = 800, 3620 .vsync_start = 800 + 1, 3621 .vsync_end = 800 + 1 + 3, 3622 .vtotal = 800 + 1 + 3 + 20, 3623 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3624 }; 3625 3626 static const struct panel_desc powertip_ph128800t006_zhc01 = { 3627 .modes = &powertip_ph128800t006_zhc01_mode, 3628 .num_modes = 1, 3629 .bpc = 8, 3630 .size = { 3631 .width = 216, 3632 .height = 135, 3633 }, 3634 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3635 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3636 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3637 }; 3638 3639 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3640 .clock = 24750, 3641 .hdisplay = 800, 3642 .hsync_start = 800 + 54, 3643 .hsync_end = 800 + 54 + 2, 3644 .htotal = 800 + 54 + 2 + 44, 3645 .vdisplay = 480, 3646 .vsync_start = 480 + 49, 3647 .vsync_end = 480 + 49 + 2, 3648 .vtotal = 480 + 49 + 2 + 22, 3649 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3650 }; 3651 3652 static const struct panel_desc powertip_ph800480t013_idf02 = { 3653 .modes = &powertip_ph800480t013_idf02_mode, 3654 .num_modes = 1, 3655 .bpc = 8, 3656 .size = { 3657 .width = 152, 3658 .height = 91, 3659 }, 3660 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3661 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3662 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3663 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3664 .connector_type = DRM_MODE_CONNECTOR_DPI, 3665 }; 3666 3667 static const struct drm_display_mode primeview_pm070wl4_mode = { 3668 .clock = 32000, 3669 .hdisplay = 800, 3670 .hsync_start = 800 + 42, 3671 .hsync_end = 800 + 42 + 128, 3672 .htotal = 800 + 42 + 128 + 86, 3673 .vdisplay = 480, 3674 .vsync_start = 480 + 10, 3675 .vsync_end = 480 + 10 + 2, 3676 .vtotal = 480 + 10 + 2 + 33, 3677 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3678 }; 3679 3680 static const struct panel_desc primeview_pm070wl4 = { 3681 .modes = &primeview_pm070wl4_mode, 3682 .num_modes = 1, 3683 .bpc = 6, 3684 .size = { 3685 .width = 152, 3686 .height = 91, 3687 }, 3688 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3689 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3690 .connector_type = DRM_MODE_CONNECTOR_DPI, 3691 }; 3692 3693 static const struct drm_display_mode qd43003c0_40_mode = { 3694 .clock = 9000, 3695 .hdisplay = 480, 3696 .hsync_start = 480 + 8, 3697 .hsync_end = 480 + 8 + 4, 3698 .htotal = 480 + 8 + 4 + 39, 3699 .vdisplay = 272, 3700 .vsync_start = 272 + 4, 3701 .vsync_end = 272 + 4 + 10, 3702 .vtotal = 272 + 4 + 10 + 2, 3703 }; 3704 3705 static const struct panel_desc qd43003c0_40 = { 3706 .modes = &qd43003c0_40_mode, 3707 .num_modes = 1, 3708 .bpc = 8, 3709 .size = { 3710 .width = 95, 3711 .height = 53, 3712 }, 3713 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3714 }; 3715 3716 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3717 { /* 60 Hz */ 3718 .clock = 10800, 3719 .hdisplay = 480, 3720 .hsync_start = 480 + 77, 3721 .hsync_end = 480 + 77 + 41, 3722 .htotal = 480 + 77 + 41 + 2, 3723 .vdisplay = 272, 3724 .vsync_start = 272 + 16, 3725 .vsync_end = 272 + 16 + 10, 3726 .vtotal = 272 + 16 + 10 + 2, 3727 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3728 }, 3729 { /* 50 Hz */ 3730 .clock = 10800, 3731 .hdisplay = 480, 3732 .hsync_start = 480 + 17, 3733 .hsync_end = 480 + 17 + 41, 3734 .htotal = 480 + 17 + 41 + 2, 3735 .vdisplay = 272, 3736 .vsync_start = 272 + 116, 3737 .vsync_end = 272 + 116 + 10, 3738 .vtotal = 272 + 116 + 10 + 2, 3739 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3740 }, 3741 }; 3742 3743 static const struct panel_desc qishenglong_gopher2b_lcd = { 3744 .modes = qishenglong_gopher2b_lcd_modes, 3745 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3746 .bpc = 8, 3747 .size = { 3748 .width = 95, 3749 .height = 54, 3750 }, 3751 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3752 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3753 .connector_type = DRM_MODE_CONNECTOR_DPI, 3754 }; 3755 3756 static const struct display_timing rocktech_rk043fn48h_timing = { 3757 .pixelclock = { 6000000, 9000000, 12000000 }, 3758 .hactive = { 480, 480, 480 }, 3759 .hback_porch = { 8, 43, 43 }, 3760 .hfront_porch = { 2, 8, 10 }, 3761 .hsync_len = { 1, 1, 1 }, 3762 .vactive = { 272, 272, 272 }, 3763 .vback_porch = { 2, 12, 26 }, 3764 .vfront_porch = { 1, 4, 4 }, 3765 .vsync_len = { 1, 10, 10 }, 3766 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3767 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3768 DISPLAY_FLAGS_SYNC_POSEDGE, 3769 }; 3770 3771 static const struct panel_desc rocktech_rk043fn48h = { 3772 .timings = &rocktech_rk043fn48h_timing, 3773 .num_timings = 1, 3774 .bpc = 8, 3775 .size = { 3776 .width = 95, 3777 .height = 54, 3778 }, 3779 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3780 .connector_type = DRM_MODE_CONNECTOR_DPI, 3781 }; 3782 3783 static const struct display_timing rocktech_rk070er9427_timing = { 3784 .pixelclock = { 26400000, 33300000, 46800000 }, 3785 .hactive = { 800, 800, 800 }, 3786 .hfront_porch = { 16, 210, 354 }, 3787 .hback_porch = { 46, 46, 46 }, 3788 .hsync_len = { 1, 1, 1 }, 3789 .vactive = { 480, 480, 480 }, 3790 .vfront_porch = { 7, 22, 147 }, 3791 .vback_porch = { 23, 23, 23 }, 3792 .vsync_len = { 1, 1, 1 }, 3793 .flags = DISPLAY_FLAGS_DE_HIGH, 3794 }; 3795 3796 static const struct panel_desc rocktech_rk070er9427 = { 3797 .timings = &rocktech_rk070er9427_timing, 3798 .num_timings = 1, 3799 .bpc = 6, 3800 .size = { 3801 .width = 154, 3802 .height = 86, 3803 }, 3804 .delay = { 3805 .prepare = 41, 3806 .enable = 50, 3807 .unprepare = 41, 3808 .disable = 50, 3809 }, 3810 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3811 }; 3812 3813 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3814 .clock = 71100, 3815 .hdisplay = 1280, 3816 .hsync_start = 1280 + 48, 3817 .hsync_end = 1280 + 48 + 32, 3818 .htotal = 1280 + 48 + 32 + 80, 3819 .vdisplay = 800, 3820 .vsync_start = 800 + 2, 3821 .vsync_end = 800 + 2 + 5, 3822 .vtotal = 800 + 2 + 5 + 16, 3823 }; 3824 3825 static const struct panel_desc rocktech_rk101ii01d_ct = { 3826 .modes = &rocktech_rk101ii01d_ct_mode, 3827 .bpc = 8, 3828 .num_modes = 1, 3829 .size = { 3830 .width = 217, 3831 .height = 136, 3832 }, 3833 .delay = { 3834 .prepare = 50, 3835 .disable = 50, 3836 }, 3837 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3838 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3839 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3840 }; 3841 3842 static const struct display_timing samsung_ltl101al01_timing = { 3843 .pixelclock = { 66663000, 66663000, 66663000 }, 3844 .hactive = { 1280, 1280, 1280 }, 3845 .hfront_porch = { 18, 18, 18 }, 3846 .hback_porch = { 36, 36, 36 }, 3847 .hsync_len = { 16, 16, 16 }, 3848 .vactive = { 800, 800, 800 }, 3849 .vfront_porch = { 4, 4, 4 }, 3850 .vback_porch = { 16, 16, 16 }, 3851 .vsync_len = { 3, 3, 3 }, 3852 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3853 }; 3854 3855 static const struct panel_desc samsung_ltl101al01 = { 3856 .timings = &samsung_ltl101al01_timing, 3857 .num_timings = 1, 3858 .bpc = 8, 3859 .size = { 3860 .width = 217, 3861 .height = 135, 3862 }, 3863 .delay = { 3864 .prepare = 40, 3865 .enable = 300, 3866 .disable = 200, 3867 .unprepare = 600, 3868 }, 3869 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3870 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3871 }; 3872 3873 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3874 .clock = 54030, 3875 .hdisplay = 1024, 3876 .hsync_start = 1024 + 24, 3877 .hsync_end = 1024 + 24 + 136, 3878 .htotal = 1024 + 24 + 136 + 160, 3879 .vdisplay = 600, 3880 .vsync_start = 600 + 3, 3881 .vsync_end = 600 + 3 + 6, 3882 .vtotal = 600 + 3 + 6 + 61, 3883 }; 3884 3885 static const struct panel_desc samsung_ltn101nt05 = { 3886 .modes = &samsung_ltn101nt05_mode, 3887 .num_modes = 1, 3888 .bpc = 6, 3889 .size = { 3890 .width = 223, 3891 .height = 125, 3892 }, 3893 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3894 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3895 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3896 }; 3897 3898 static const struct display_timing satoz_sat050at40h12r2_timing = { 3899 .pixelclock = {33300000, 33300000, 50000000}, 3900 .hactive = {800, 800, 800}, 3901 .hfront_porch = {16, 210, 354}, 3902 .hback_porch = {46, 46, 46}, 3903 .hsync_len = {1, 1, 40}, 3904 .vactive = {480, 480, 480}, 3905 .vfront_porch = {7, 22, 147}, 3906 .vback_porch = {23, 23, 23}, 3907 .vsync_len = {1, 1, 20}, 3908 }; 3909 3910 static const struct panel_desc satoz_sat050at40h12r2 = { 3911 .timings = &satoz_sat050at40h12r2_timing, 3912 .num_timings = 1, 3913 .bpc = 8, 3914 .size = { 3915 .width = 108, 3916 .height = 65, 3917 }, 3918 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3919 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3920 }; 3921 3922 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3923 .clock = 33260, 3924 .hdisplay = 800, 3925 .hsync_start = 800 + 64, 3926 .hsync_end = 800 + 64 + 128, 3927 .htotal = 800 + 64 + 128 + 64, 3928 .vdisplay = 480, 3929 .vsync_start = 480 + 8, 3930 .vsync_end = 480 + 8 + 2, 3931 .vtotal = 480 + 8 + 2 + 35, 3932 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3933 }; 3934 3935 static const struct panel_desc sharp_lq070y3dg3b = { 3936 .modes = &sharp_lq070y3dg3b_mode, 3937 .num_modes = 1, 3938 .bpc = 8, 3939 .size = { 3940 .width = 152, /* 152.4mm */ 3941 .height = 91, /* 91.4mm */ 3942 }, 3943 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3944 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3945 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3946 }; 3947 3948 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3949 .clock = 5500, 3950 .hdisplay = 240, 3951 .hsync_start = 240 + 16, 3952 .hsync_end = 240 + 16 + 7, 3953 .htotal = 240 + 16 + 7 + 5, 3954 .vdisplay = 320, 3955 .vsync_start = 320 + 9, 3956 .vsync_end = 320 + 9 + 1, 3957 .vtotal = 320 + 9 + 1 + 7, 3958 }; 3959 3960 static const struct panel_desc sharp_lq035q7db03 = { 3961 .modes = &sharp_lq035q7db03_mode, 3962 .num_modes = 1, 3963 .bpc = 6, 3964 .size = { 3965 .width = 54, 3966 .height = 72, 3967 }, 3968 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3969 }; 3970 3971 static const struct display_timing sharp_lq101k1ly04_timing = { 3972 .pixelclock = { 60000000, 65000000, 80000000 }, 3973 .hactive = { 1280, 1280, 1280 }, 3974 .hfront_porch = { 20, 20, 20 }, 3975 .hback_porch = { 20, 20, 20 }, 3976 .hsync_len = { 10, 10, 10 }, 3977 .vactive = { 800, 800, 800 }, 3978 .vfront_porch = { 4, 4, 4 }, 3979 .vback_porch = { 4, 4, 4 }, 3980 .vsync_len = { 4, 4, 4 }, 3981 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3982 }; 3983 3984 static const struct panel_desc sharp_lq101k1ly04 = { 3985 .timings = &sharp_lq101k1ly04_timing, 3986 .num_timings = 1, 3987 .bpc = 8, 3988 .size = { 3989 .width = 217, 3990 .height = 136, 3991 }, 3992 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3993 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3994 }; 3995 3996 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3997 { /* 50 Hz */ 3998 .clock = 3000, 3999 .hdisplay = 240, 4000 .hsync_start = 240 + 58, 4001 .hsync_end = 240 + 58 + 1, 4002 .htotal = 240 + 58 + 1 + 1, 4003 .vdisplay = 160, 4004 .vsync_start = 160 + 24, 4005 .vsync_end = 160 + 24 + 10, 4006 .vtotal = 160 + 24 + 10 + 6, 4007 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4008 }, 4009 { /* 60 Hz */ 4010 .clock = 3000, 4011 .hdisplay = 240, 4012 .hsync_start = 240 + 8, 4013 .hsync_end = 240 + 8 + 1, 4014 .htotal = 240 + 8 + 1 + 1, 4015 .vdisplay = 160, 4016 .vsync_start = 160 + 24, 4017 .vsync_end = 160 + 24 + 10, 4018 .vtotal = 160 + 24 + 10 + 6, 4019 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4020 }, 4021 }; 4022 4023 static const struct panel_desc sharp_ls020b1dd01d = { 4024 .modes = sharp_ls020b1dd01d_modes, 4025 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4026 .bpc = 6, 4027 .size = { 4028 .width = 42, 4029 .height = 28, 4030 }, 4031 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4032 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4033 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4034 | DRM_BUS_FLAG_SHARP_SIGNALS, 4035 }; 4036 4037 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4038 .clock = 33300, 4039 .hdisplay = 800, 4040 .hsync_start = 800 + 1, 4041 .hsync_end = 800 + 1 + 64, 4042 .htotal = 800 + 1 + 64 + 64, 4043 .vdisplay = 480, 4044 .vsync_start = 480 + 1, 4045 .vsync_end = 480 + 1 + 23, 4046 .vtotal = 480 + 1 + 23 + 22, 4047 }; 4048 4049 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4050 .modes = &shelly_sca07010_bfn_lnn_mode, 4051 .num_modes = 1, 4052 .size = { 4053 .width = 152, 4054 .height = 91, 4055 }, 4056 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4057 }; 4058 4059 static const struct drm_display_mode starry_kr070pe2t_mode = { 4060 .clock = 33000, 4061 .hdisplay = 800, 4062 .hsync_start = 800 + 209, 4063 .hsync_end = 800 + 209 + 1, 4064 .htotal = 800 + 209 + 1 + 45, 4065 .vdisplay = 480, 4066 .vsync_start = 480 + 22, 4067 .vsync_end = 480 + 22 + 1, 4068 .vtotal = 480 + 22 + 1 + 22, 4069 }; 4070 4071 static const struct panel_desc starry_kr070pe2t = { 4072 .modes = &starry_kr070pe2t_mode, 4073 .num_modes = 1, 4074 .bpc = 8, 4075 .size = { 4076 .width = 152, 4077 .height = 86, 4078 }, 4079 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4080 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4081 .connector_type = DRM_MODE_CONNECTOR_DPI, 4082 }; 4083 4084 static const struct display_timing startek_kd070wvfpa_mode = { 4085 .pixelclock = { 25200000, 27200000, 30500000 }, 4086 .hactive = { 800, 800, 800 }, 4087 .hfront_porch = { 19, 44, 115 }, 4088 .hback_porch = { 5, 16, 101 }, 4089 .hsync_len = { 1, 2, 100 }, 4090 .vactive = { 480, 480, 480 }, 4091 .vfront_porch = { 5, 43, 67 }, 4092 .vback_porch = { 5, 5, 67 }, 4093 .vsync_len = { 1, 2, 66 }, 4094 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4095 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4096 DISPLAY_FLAGS_SYNC_POSEDGE, 4097 }; 4098 4099 static const struct panel_desc startek_kd070wvfpa = { 4100 .timings = &startek_kd070wvfpa_mode, 4101 .num_timings = 1, 4102 .bpc = 8, 4103 .size = { 4104 .width = 152, 4105 .height = 91, 4106 }, 4107 .delay = { 4108 .prepare = 20, 4109 .enable = 200, 4110 .disable = 200, 4111 }, 4112 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4113 .connector_type = DRM_MODE_CONNECTOR_DPI, 4114 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4115 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4116 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4117 }; 4118 4119 static const struct display_timing tsd_tst043015cmhx_timing = { 4120 .pixelclock = { 5000000, 9000000, 12000000 }, 4121 .hactive = { 480, 480, 480 }, 4122 .hfront_porch = { 4, 5, 65 }, 4123 .hback_porch = { 36, 40, 255 }, 4124 .hsync_len = { 1, 1, 1 }, 4125 .vactive = { 272, 272, 272 }, 4126 .vfront_porch = { 2, 8, 97 }, 4127 .vback_porch = { 3, 8, 31 }, 4128 .vsync_len = { 1, 1, 1 }, 4129 4130 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4131 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4132 }; 4133 4134 static const struct panel_desc tsd_tst043015cmhx = { 4135 .timings = &tsd_tst043015cmhx_timing, 4136 .num_timings = 1, 4137 .bpc = 8, 4138 .size = { 4139 .width = 105, 4140 .height = 67, 4141 }, 4142 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4143 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4144 }; 4145 4146 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4147 .clock = 30000, 4148 .hdisplay = 800, 4149 .hsync_start = 800 + 39, 4150 .hsync_end = 800 + 39 + 47, 4151 .htotal = 800 + 39 + 47 + 39, 4152 .vdisplay = 480, 4153 .vsync_start = 480 + 13, 4154 .vsync_end = 480 + 13 + 2, 4155 .vtotal = 480 + 13 + 2 + 29, 4156 }; 4157 4158 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4159 .modes = &tfc_s9700rtwv43tr_01b_mode, 4160 .num_modes = 1, 4161 .bpc = 8, 4162 .size = { 4163 .width = 155, 4164 .height = 90, 4165 }, 4166 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4167 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4168 }; 4169 4170 static const struct display_timing tianma_tm070jdhg30_timing = { 4171 .pixelclock = { 62600000, 68200000, 78100000 }, 4172 .hactive = { 1280, 1280, 1280 }, 4173 .hfront_porch = { 15, 64, 159 }, 4174 .hback_porch = { 5, 5, 5 }, 4175 .hsync_len = { 1, 1, 256 }, 4176 .vactive = { 800, 800, 800 }, 4177 .vfront_porch = { 3, 40, 99 }, 4178 .vback_porch = { 2, 2, 2 }, 4179 .vsync_len = { 1, 1, 128 }, 4180 .flags = DISPLAY_FLAGS_DE_HIGH, 4181 }; 4182 4183 static const struct panel_desc tianma_tm070jdhg30 = { 4184 .timings = &tianma_tm070jdhg30_timing, 4185 .num_timings = 1, 4186 .bpc = 8, 4187 .size = { 4188 .width = 151, 4189 .height = 95, 4190 }, 4191 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4192 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4193 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4194 }; 4195 4196 static const struct panel_desc tianma_tm070jvhg33 = { 4197 .timings = &tianma_tm070jdhg30_timing, 4198 .num_timings = 1, 4199 .bpc = 8, 4200 .size = { 4201 .width = 150, 4202 .height = 94, 4203 }, 4204 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4205 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4206 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4207 }; 4208 4209 static const struct display_timing tianma_tm070rvhg71_timing = { 4210 .pixelclock = { 27700000, 29200000, 39600000 }, 4211 .hactive = { 800, 800, 800 }, 4212 .hfront_porch = { 12, 40, 212 }, 4213 .hback_porch = { 88, 88, 88 }, 4214 .hsync_len = { 1, 1, 40 }, 4215 .vactive = { 480, 480, 480 }, 4216 .vfront_porch = { 1, 13, 88 }, 4217 .vback_porch = { 32, 32, 32 }, 4218 .vsync_len = { 1, 1, 3 }, 4219 .flags = DISPLAY_FLAGS_DE_HIGH, 4220 }; 4221 4222 static const struct panel_desc tianma_tm070rvhg71 = { 4223 .timings = &tianma_tm070rvhg71_timing, 4224 .num_timings = 1, 4225 .bpc = 8, 4226 .size = { 4227 .width = 154, 4228 .height = 86, 4229 }, 4230 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4231 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4232 }; 4233 4234 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4235 { 4236 .clock = 10000, 4237 .hdisplay = 320, 4238 .hsync_start = 320 + 50, 4239 .hsync_end = 320 + 50 + 6, 4240 .htotal = 320 + 50 + 6 + 38, 4241 .vdisplay = 240, 4242 .vsync_start = 240 + 3, 4243 .vsync_end = 240 + 3 + 1, 4244 .vtotal = 240 + 3 + 1 + 17, 4245 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4246 }, 4247 }; 4248 4249 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4250 .modes = ti_nspire_cx_lcd_mode, 4251 .num_modes = 1, 4252 .bpc = 8, 4253 .size = { 4254 .width = 65, 4255 .height = 49, 4256 }, 4257 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4258 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4259 }; 4260 4261 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4262 { 4263 .clock = 10000, 4264 .hdisplay = 320, 4265 .hsync_start = 320 + 6, 4266 .hsync_end = 320 + 6 + 6, 4267 .htotal = 320 + 6 + 6 + 6, 4268 .vdisplay = 240, 4269 .vsync_start = 240 + 0, 4270 .vsync_end = 240 + 0 + 1, 4271 .vtotal = 240 + 0 + 1 + 0, 4272 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4273 }, 4274 }; 4275 4276 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4277 .modes = ti_nspire_classic_lcd_mode, 4278 .num_modes = 1, 4279 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4280 .bpc = 8, 4281 .size = { 4282 .width = 71, 4283 .height = 53, 4284 }, 4285 /* This is the grayscale bus format */ 4286 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4287 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4288 }; 4289 4290 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4291 .clock = 79500, 4292 .hdisplay = 1280, 4293 .hsync_start = 1280 + 192, 4294 .hsync_end = 1280 + 192 + 128, 4295 .htotal = 1280 + 192 + 128 + 64, 4296 .vdisplay = 768, 4297 .vsync_start = 768 + 20, 4298 .vsync_end = 768 + 20 + 7, 4299 .vtotal = 768 + 20 + 7 + 3, 4300 }; 4301 4302 static const struct panel_desc toshiba_lt089ac29000 = { 4303 .modes = &toshiba_lt089ac29000_mode, 4304 .num_modes = 1, 4305 .size = { 4306 .width = 194, 4307 .height = 116, 4308 }, 4309 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4310 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4311 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4312 }; 4313 4314 static const struct drm_display_mode tpk_f07a_0102_mode = { 4315 .clock = 33260, 4316 .hdisplay = 800, 4317 .hsync_start = 800 + 40, 4318 .hsync_end = 800 + 40 + 128, 4319 .htotal = 800 + 40 + 128 + 88, 4320 .vdisplay = 480, 4321 .vsync_start = 480 + 10, 4322 .vsync_end = 480 + 10 + 2, 4323 .vtotal = 480 + 10 + 2 + 33, 4324 }; 4325 4326 static const struct panel_desc tpk_f07a_0102 = { 4327 .modes = &tpk_f07a_0102_mode, 4328 .num_modes = 1, 4329 .size = { 4330 .width = 152, 4331 .height = 91, 4332 }, 4333 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4334 }; 4335 4336 static const struct drm_display_mode tpk_f10a_0102_mode = { 4337 .clock = 45000, 4338 .hdisplay = 1024, 4339 .hsync_start = 1024 + 176, 4340 .hsync_end = 1024 + 176 + 5, 4341 .htotal = 1024 + 176 + 5 + 88, 4342 .vdisplay = 600, 4343 .vsync_start = 600 + 20, 4344 .vsync_end = 600 + 20 + 5, 4345 .vtotal = 600 + 20 + 5 + 25, 4346 }; 4347 4348 static const struct panel_desc tpk_f10a_0102 = { 4349 .modes = &tpk_f10a_0102_mode, 4350 .num_modes = 1, 4351 .size = { 4352 .width = 223, 4353 .height = 125, 4354 }, 4355 }; 4356 4357 static const struct display_timing urt_umsh_8596md_timing = { 4358 .pixelclock = { 33260000, 33260000, 33260000 }, 4359 .hactive = { 800, 800, 800 }, 4360 .hfront_porch = { 41, 41, 41 }, 4361 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4362 .hsync_len = { 71, 128, 128 }, 4363 .vactive = { 480, 480, 480 }, 4364 .vfront_porch = { 10, 10, 10 }, 4365 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4366 .vsync_len = { 2, 2, 2 }, 4367 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4368 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4369 }; 4370 4371 static const struct panel_desc urt_umsh_8596md_lvds = { 4372 .timings = &urt_umsh_8596md_timing, 4373 .num_timings = 1, 4374 .bpc = 6, 4375 .size = { 4376 .width = 152, 4377 .height = 91, 4378 }, 4379 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4380 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4381 }; 4382 4383 static const struct panel_desc urt_umsh_8596md_parallel = { 4384 .timings = &urt_umsh_8596md_timing, 4385 .num_timings = 1, 4386 .bpc = 6, 4387 .size = { 4388 .width = 152, 4389 .height = 91, 4390 }, 4391 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4392 }; 4393 4394 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4395 .clock = 60000, 4396 .hdisplay = 1024, 4397 .hsync_start = 1024 + 160, 4398 .hsync_end = 1024 + 160 + 100, 4399 .htotal = 1024 + 160 + 100 + 60, 4400 .vdisplay = 600, 4401 .vsync_start = 600 + 12, 4402 .vsync_end = 600 + 12 + 10, 4403 .vtotal = 600 + 12 + 10 + 13, 4404 }; 4405 4406 static const struct panel_desc vivax_tpc9150_panel = { 4407 .modes = &vivax_tpc9150_panel_mode, 4408 .num_modes = 1, 4409 .bpc = 6, 4410 .size = { 4411 .width = 200, 4412 .height = 115, 4413 }, 4414 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4415 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4416 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4417 }; 4418 4419 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4420 .clock = 33333, 4421 .hdisplay = 800, 4422 .hsync_start = 800 + 210, 4423 .hsync_end = 800 + 210 + 20, 4424 .htotal = 800 + 210 + 20 + 46, 4425 .vdisplay = 480, 4426 .vsync_start = 480 + 22, 4427 .vsync_end = 480 + 22 + 10, 4428 .vtotal = 480 + 22 + 10 + 23, 4429 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4430 }; 4431 4432 static const struct panel_desc vl050_8048nt_c01 = { 4433 .modes = &vl050_8048nt_c01_mode, 4434 .num_modes = 1, 4435 .bpc = 8, 4436 .size = { 4437 .width = 120, 4438 .height = 76, 4439 }, 4440 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4441 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4442 }; 4443 4444 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4445 .clock = 6410, 4446 .hdisplay = 320, 4447 .hsync_start = 320 + 20, 4448 .hsync_end = 320 + 20 + 30, 4449 .htotal = 320 + 20 + 30 + 38, 4450 .vdisplay = 240, 4451 .vsync_start = 240 + 4, 4452 .vsync_end = 240 + 4 + 3, 4453 .vtotal = 240 + 4 + 3 + 15, 4454 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4455 }; 4456 4457 static const struct panel_desc winstar_wf35ltiacd = { 4458 .modes = &winstar_wf35ltiacd_mode, 4459 .num_modes = 1, 4460 .bpc = 8, 4461 .size = { 4462 .width = 70, 4463 .height = 53, 4464 }, 4465 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4466 }; 4467 4468 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4469 .clock = 51200, 4470 .hdisplay = 1024, 4471 .hsync_start = 1024 + 100, 4472 .hsync_end = 1024 + 100 + 100, 4473 .htotal = 1024 + 100 + 100 + 120, 4474 .vdisplay = 600, 4475 .vsync_start = 600 + 10, 4476 .vsync_end = 600 + 10 + 10, 4477 .vtotal = 600 + 10 + 10 + 15, 4478 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4479 }; 4480 4481 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4482 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4483 .num_modes = 1, 4484 .bpc = 8, 4485 .size = { 4486 .width = 154, 4487 .height = 90, 4488 }, 4489 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4490 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4491 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4492 }; 4493 4494 static const struct drm_display_mode arm_rtsm_mode[] = { 4495 { 4496 .clock = 65000, 4497 .hdisplay = 1024, 4498 .hsync_start = 1024 + 24, 4499 .hsync_end = 1024 + 24 + 136, 4500 .htotal = 1024 + 24 + 136 + 160, 4501 .vdisplay = 768, 4502 .vsync_start = 768 + 3, 4503 .vsync_end = 768 + 3 + 6, 4504 .vtotal = 768 + 3 + 6 + 29, 4505 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4506 }, 4507 }; 4508 4509 static const struct panel_desc arm_rtsm = { 4510 .modes = arm_rtsm_mode, 4511 .num_modes = 1, 4512 .bpc = 8, 4513 .size = { 4514 .width = 400, 4515 .height = 300, 4516 }, 4517 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4518 }; 4519 4520 static const struct of_device_id platform_of_match[] = { 4521 { 4522 .compatible = "ampire,am-1280800n3tzqw-t00h", 4523 .data = &ire_am_1280800n3tzqw_t00h, 4524 }, { 4525 .compatible = "ampire,am-480272h3tmqw-t01h", 4526 .data = &ire_am_480272h3tmqw_t01h, 4527 }, { 4528 .compatible = "ampire,am-800480l1tmqw-t00h", 4529 .data = &ire_am_800480l1tmqw_t00h, 4530 }, { 4531 .compatible = "ampire,am800480r3tmqwa1h", 4532 .data = &ire_am800480r3tmqwa1h, 4533 }, { 4534 .compatible = "ampire,am800600p5tmqw-tb8h", 4535 .data = &ire_am800600p5tmqwtb8h, 4536 }, { 4537 .compatible = "arm,rtsm-display", 4538 .data = &arm_rtsm, 4539 }, { 4540 .compatible = "armadeus,st0700-adapt", 4541 .data = &armadeus_st0700_adapt, 4542 }, { 4543 .compatible = "auo,b101aw03", 4544 .data = &auo_b101aw03, 4545 }, { 4546 .compatible = "auo,b101xtn01", 4547 .data = &auo_b101xtn01, 4548 }, { 4549 .compatible = "auo,b116xw03", 4550 .data = &auo_b116xw03, 4551 }, { 4552 .compatible = "auo,g070vvn01", 4553 .data = &auo_g070vvn01, 4554 }, { 4555 .compatible = "auo,g101evn010", 4556 .data = &auo_g101evn010, 4557 }, { 4558 .compatible = "auo,g104sn02", 4559 .data = &auo_g104sn02, 4560 }, { 4561 .compatible = "auo,g104stn01", 4562 .data = &auo_g104stn01, 4563 }, { 4564 .compatible = "auo,g121ean01", 4565 .data = &auo_g121ean01, 4566 }, { 4567 .compatible = "auo,g133han01", 4568 .data = &auo_g133han01, 4569 }, { 4570 .compatible = "auo,g156han04", 4571 .data = &auo_g156han04, 4572 }, { 4573 .compatible = "auo,g156xtn01", 4574 .data = &auo_g156xtn01, 4575 }, { 4576 .compatible = "auo,g185han01", 4577 .data = &auo_g185han01, 4578 }, { 4579 .compatible = "auo,g190ean01", 4580 .data = &auo_g190ean01, 4581 }, { 4582 .compatible = "auo,p320hvn03", 4583 .data = &auo_p320hvn03, 4584 }, { 4585 .compatible = "auo,t215hvn01", 4586 .data = &auo_t215hvn01, 4587 }, { 4588 .compatible = "avic,tm070ddh03", 4589 .data = &avic_tm070ddh03, 4590 }, { 4591 .compatible = "bananapi,s070wv20-ct16", 4592 .data = &bananapi_s070wv20_ct16, 4593 }, { 4594 .compatible = "boe,bp082wx1-100", 4595 .data = &boe_bp082wx1_100, 4596 }, { 4597 .compatible = "boe,bp101wx1-100", 4598 .data = &boe_bp101wx1_100, 4599 }, { 4600 .compatible = "boe,ev121wxm-n10-1850", 4601 .data = &boe_ev121wxm_n10_1850, 4602 }, { 4603 .compatible = "boe,hv070wsa-100", 4604 .data = &boe_hv070wsa 4605 }, { 4606 .compatible = "cct,cmt430b19n00", 4607 .data = &cct_cmt430b19n00, 4608 }, { 4609 .compatible = "cdtech,s043wq26h-ct7", 4610 .data = &cdtech_s043wq26h_ct7, 4611 }, { 4612 .compatible = "cdtech,s070pws19hp-fc21", 4613 .data = &cdtech_s070pws19hp_fc21, 4614 }, { 4615 .compatible = "cdtech,s070swv29hg-dc44", 4616 .data = &cdtech_s070swv29hg_dc44, 4617 }, { 4618 .compatible = "cdtech,s070wv95-ct16", 4619 .data = &cdtech_s070wv95_ct16, 4620 }, { 4621 .compatible = "chefree,ch101olhlwh-002", 4622 .data = &chefree_ch101olhlwh_002, 4623 }, { 4624 .compatible = "chunghwa,claa070wp03xg", 4625 .data = &chunghwa_claa070wp03xg, 4626 }, { 4627 .compatible = "chunghwa,claa101wa01a", 4628 .data = &chunghwa_claa101wa01a 4629 }, { 4630 .compatible = "chunghwa,claa101wb01", 4631 .data = &chunghwa_claa101wb01 4632 }, { 4633 .compatible = "dataimage,fg040346dsswbg04", 4634 .data = &dataimage_fg040346dsswbg04, 4635 }, { 4636 .compatible = "dataimage,fg1001l0dsswmg01", 4637 .data = &dataimage_fg1001l0dsswmg01, 4638 }, { 4639 .compatible = "dataimage,scf0700c48ggu18", 4640 .data = &dataimage_scf0700c48ggu18, 4641 }, { 4642 .compatible = "dlc,dlc0700yzg-1", 4643 .data = &dlc_dlc0700yzg_1, 4644 }, { 4645 .compatible = "dlc,dlc1010gig", 4646 .data = &dlc_dlc1010gig, 4647 }, { 4648 .compatible = "edt,et035012dm6", 4649 .data = &edt_et035012dm6, 4650 }, { 4651 .compatible = "edt,etm0350g0dh6", 4652 .data = &edt_etm0350g0dh6, 4653 }, { 4654 .compatible = "edt,etm043080dh6gp", 4655 .data = &edt_etm043080dh6gp, 4656 }, { 4657 .compatible = "edt,etm0430g0dh6", 4658 .data = &edt_etm0430g0dh6, 4659 }, { 4660 .compatible = "edt,et057090dhu", 4661 .data = &edt_et057090dhu, 4662 }, { 4663 .compatible = "edt,et070080dh6", 4664 .data = &edt_etm0700g0dh6, 4665 }, { 4666 .compatible = "edt,etm0700g0dh6", 4667 .data = &edt_etm0700g0dh6, 4668 }, { 4669 .compatible = "edt,etm0700g0bdh6", 4670 .data = &edt_etm0700g0bdh6, 4671 }, { 4672 .compatible = "edt,etm0700g0edh6", 4673 .data = &edt_etm0700g0bdh6, 4674 }, { 4675 .compatible = "edt,etml0700y5dha", 4676 .data = &edt_etml0700y5dha, 4677 }, { 4678 .compatible = "edt,etml1010g3dra", 4679 .data = &edt_etml1010g3dra, 4680 }, { 4681 .compatible = "edt,etmv570g2dhu", 4682 .data = &edt_etmv570g2dhu, 4683 }, { 4684 .compatible = "eink,vb3300-kca", 4685 .data = &eink_vb3300_kca, 4686 }, { 4687 .compatible = "evervision,vgg644804", 4688 .data = &evervision_vgg644804, 4689 }, { 4690 .compatible = "evervision,vgg804821", 4691 .data = &evervision_vgg804821, 4692 }, { 4693 .compatible = "foxlink,fl500wvr00-a0t", 4694 .data = &foxlink_fl500wvr00_a0t, 4695 }, { 4696 .compatible = "frida,frd350h54004", 4697 .data = &frida_frd350h54004, 4698 }, { 4699 .compatible = "friendlyarm,hd702e", 4700 .data = &friendlyarm_hd702e, 4701 }, { 4702 .compatible = "giantplus,gpg482739qs5", 4703 .data = &giantplus_gpg482739qs5 4704 }, { 4705 .compatible = "giantplus,gpm940b0", 4706 .data = &giantplus_gpm940b0, 4707 }, { 4708 .compatible = "hannstar,hsd070pww1", 4709 .data = &hannstar_hsd070pww1, 4710 }, { 4711 .compatible = "hannstar,hsd100pxn1", 4712 .data = &hannstar_hsd100pxn1, 4713 }, { 4714 .compatible = "hannstar,hsd101pww2", 4715 .data = &hannstar_hsd101pww2, 4716 }, { 4717 .compatible = "hit,tx23d38vm0caa", 4718 .data = &hitachi_tx23d38vm0caa 4719 }, { 4720 .compatible = "innolux,at043tn24", 4721 .data = &innolux_at043tn24, 4722 }, { 4723 .compatible = "innolux,at070tn92", 4724 .data = &innolux_at070tn92, 4725 }, { 4726 .compatible = "innolux,g070ace-l01", 4727 .data = &innolux_g070ace_l01, 4728 }, { 4729 .compatible = "innolux,g070y2-l01", 4730 .data = &innolux_g070y2_l01, 4731 }, { 4732 .compatible = "innolux,g070y2-t02", 4733 .data = &innolux_g070y2_t02, 4734 }, { 4735 .compatible = "innolux,g101ice-l01", 4736 .data = &innolux_g101ice_l01 4737 }, { 4738 .compatible = "innolux,g121i1-l01", 4739 .data = &innolux_g121i1_l01 4740 }, { 4741 .compatible = "innolux,g121x1-l03", 4742 .data = &innolux_g121x1_l03, 4743 }, { 4744 .compatible = "innolux,g121xce-l01", 4745 .data = &innolux_g121xce_l01, 4746 }, { 4747 .compatible = "innolux,g156hce-l01", 4748 .data = &innolux_g156hce_l01, 4749 }, { 4750 .compatible = "innolux,n156bge-l21", 4751 .data = &innolux_n156bge_l21, 4752 }, { 4753 .compatible = "innolux,zj070na-01p", 4754 .data = &innolux_zj070na_01p, 4755 }, { 4756 .compatible = "koe,tx14d24vm1bpa", 4757 .data = &koe_tx14d24vm1bpa, 4758 }, { 4759 .compatible = "koe,tx26d202vm0bwa", 4760 .data = &koe_tx26d202vm0bwa, 4761 }, { 4762 .compatible = "koe,tx31d200vm0baa", 4763 .data = &koe_tx31d200vm0baa, 4764 }, { 4765 .compatible = "kyo,tcg121xglp", 4766 .data = &kyo_tcg121xglp, 4767 }, { 4768 .compatible = "lemaker,bl035-rgb-002", 4769 .data = &lemaker_bl035_rgb_002, 4770 }, { 4771 .compatible = "lg,lb070wv8", 4772 .data = &lg_lb070wv8, 4773 }, { 4774 .compatible = "lincolntech,lcd185-101ct", 4775 .data = &lincolntech_lcd185_101ct, 4776 }, { 4777 .compatible = "logicpd,type28", 4778 .data = &logicpd_type_28, 4779 }, { 4780 .compatible = "logictechno,lt161010-2nhc", 4781 .data = &logictechno_lt161010_2nh, 4782 }, { 4783 .compatible = "logictechno,lt161010-2nhr", 4784 .data = &logictechno_lt161010_2nh, 4785 }, { 4786 .compatible = "logictechno,lt170410-2whc", 4787 .data = &logictechno_lt170410_2whc, 4788 }, { 4789 .compatible = "logictechno,lttd800480070-l2rt", 4790 .data = &logictechno_lttd800480070_l2rt, 4791 }, { 4792 .compatible = "logictechno,lttd800480070-l6wh-rt", 4793 .data = &logictechno_lttd800480070_l6wh_rt, 4794 }, { 4795 .compatible = "microtips,mf-101hiebcaf0", 4796 .data = µtips_mf_101hiebcaf0_c, 4797 }, { 4798 .compatible = "microtips,mf-103hieb0ga0", 4799 .data = µtips_mf_103hieb0ga0, 4800 }, { 4801 .compatible = "mitsubishi,aa070mc01-ca1", 4802 .data = &mitsubishi_aa070mc01, 4803 }, { 4804 .compatible = "mitsubishi,aa084xe01", 4805 .data = &mitsubishi_aa084xe01, 4806 }, { 4807 .compatible = "multi-inno,mi0700s4t-6", 4808 .data = &multi_inno_mi0700s4t_6, 4809 }, { 4810 .compatible = "multi-inno,mi0800ft-9", 4811 .data = &multi_inno_mi0800ft_9, 4812 }, { 4813 .compatible = "multi-inno,mi1010ait-1cp", 4814 .data = &multi_inno_mi1010ait_1cp, 4815 }, { 4816 .compatible = "nec,nl12880bc20-05", 4817 .data = &nec_nl12880bc20_05, 4818 }, { 4819 .compatible = "nec,nl4827hc19-05b", 4820 .data = &nec_nl4827hc19_05b, 4821 }, { 4822 .compatible = "netron-dy,e231732", 4823 .data = &netron_dy_e231732, 4824 }, { 4825 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4826 .data = &newhaven_nhd_43_480272ef_atxl, 4827 }, { 4828 .compatible = "nlt,nl192108ac18-02d", 4829 .data = &nlt_nl192108ac18_02d, 4830 }, { 4831 .compatible = "nvd,9128", 4832 .data = &nvd_9128, 4833 }, { 4834 .compatible = "okaya,rs800480t-7x0gp", 4835 .data = &okaya_rs800480t_7x0gp, 4836 }, { 4837 .compatible = "olimex,lcd-olinuxino-43-ts", 4838 .data = &olimex_lcd_olinuxino_43ts, 4839 }, { 4840 .compatible = "ontat,yx700wv03", 4841 .data = &ontat_yx700wv03, 4842 }, { 4843 .compatible = "ortustech,com37h3m05dtc", 4844 .data = &ortustech_com37h3m, 4845 }, { 4846 .compatible = "ortustech,com37h3m99dtc", 4847 .data = &ortustech_com37h3m, 4848 }, { 4849 .compatible = "ortustech,com43h4m85ulc", 4850 .data = &ortustech_com43h4m85ulc, 4851 }, { 4852 .compatible = "osddisplays,osd070t1718-19ts", 4853 .data = &osddisplays_osd070t1718_19ts, 4854 }, { 4855 .compatible = "pda,91-00156-a0", 4856 .data = &pda_91_00156_a0, 4857 }, { 4858 .compatible = "powertip,ph128800t006-zhc01", 4859 .data = &powertip_ph128800t006_zhc01, 4860 }, { 4861 .compatible = "powertip,ph800480t013-idf02", 4862 .data = &powertip_ph800480t013_idf02, 4863 }, { 4864 .compatible = "primeview,pm070wl4", 4865 .data = &primeview_pm070wl4, 4866 }, { 4867 .compatible = "qiaodian,qd43003c0-40", 4868 .data = &qd43003c0_40, 4869 }, { 4870 .compatible = "qishenglong,gopher2b-lcd", 4871 .data = &qishenglong_gopher2b_lcd, 4872 }, { 4873 .compatible = "rocktech,rk043fn48h", 4874 .data = &rocktech_rk043fn48h, 4875 }, { 4876 .compatible = "rocktech,rk070er9427", 4877 .data = &rocktech_rk070er9427, 4878 }, { 4879 .compatible = "rocktech,rk101ii01d-ct", 4880 .data = &rocktech_rk101ii01d_ct, 4881 }, { 4882 .compatible = "samsung,ltl101al01", 4883 .data = &samsung_ltl101al01, 4884 }, { 4885 .compatible = "samsung,ltn101nt05", 4886 .data = &samsung_ltn101nt05, 4887 }, { 4888 .compatible = "satoz,sat050at40h12r2", 4889 .data = &satoz_sat050at40h12r2, 4890 }, { 4891 .compatible = "sharp,lq035q7db03", 4892 .data = &sharp_lq035q7db03, 4893 }, { 4894 .compatible = "sharp,lq070y3dg3b", 4895 .data = &sharp_lq070y3dg3b, 4896 }, { 4897 .compatible = "sharp,lq101k1ly04", 4898 .data = &sharp_lq101k1ly04, 4899 }, { 4900 .compatible = "sharp,ls020b1dd01d", 4901 .data = &sharp_ls020b1dd01d, 4902 }, { 4903 .compatible = "shelly,sca07010-bfn-lnn", 4904 .data = &shelly_sca07010_bfn_lnn, 4905 }, { 4906 .compatible = "starry,kr070pe2t", 4907 .data = &starry_kr070pe2t, 4908 }, { 4909 .compatible = "startek,kd070wvfpa", 4910 .data = &startek_kd070wvfpa, 4911 }, { 4912 .compatible = "team-source-display,tst043015cmhx", 4913 .data = &tsd_tst043015cmhx, 4914 }, { 4915 .compatible = "tfc,s9700rtwv43tr-01b", 4916 .data = &tfc_s9700rtwv43tr_01b, 4917 }, { 4918 .compatible = "tianma,tm070jdhg30", 4919 .data = &tianma_tm070jdhg30, 4920 }, { 4921 .compatible = "tianma,tm070jvhg33", 4922 .data = &tianma_tm070jvhg33, 4923 }, { 4924 .compatible = "tianma,tm070rvhg71", 4925 .data = &tianma_tm070rvhg71, 4926 }, { 4927 .compatible = "ti,nspire-cx-lcd-panel", 4928 .data = &ti_nspire_cx_lcd_panel, 4929 }, { 4930 .compatible = "ti,nspire-classic-lcd-panel", 4931 .data = &ti_nspire_classic_lcd_panel, 4932 }, { 4933 .compatible = "toshiba,lt089ac29000", 4934 .data = &toshiba_lt089ac29000, 4935 }, { 4936 .compatible = "tpk,f07a-0102", 4937 .data = &tpk_f07a_0102, 4938 }, { 4939 .compatible = "tpk,f10a-0102", 4940 .data = &tpk_f10a_0102, 4941 }, { 4942 .compatible = "urt,umsh-8596md-t", 4943 .data = &urt_umsh_8596md_parallel, 4944 }, { 4945 .compatible = "urt,umsh-8596md-1t", 4946 .data = &urt_umsh_8596md_parallel, 4947 }, { 4948 .compatible = "urt,umsh-8596md-7t", 4949 .data = &urt_umsh_8596md_parallel, 4950 }, { 4951 .compatible = "urt,umsh-8596md-11t", 4952 .data = &urt_umsh_8596md_lvds, 4953 }, { 4954 .compatible = "urt,umsh-8596md-19t", 4955 .data = &urt_umsh_8596md_lvds, 4956 }, { 4957 .compatible = "urt,umsh-8596md-20t", 4958 .data = &urt_umsh_8596md_parallel, 4959 }, { 4960 .compatible = "vivax,tpc9150-panel", 4961 .data = &vivax_tpc9150_panel, 4962 }, { 4963 .compatible = "vxt,vl050-8048nt-c01", 4964 .data = &vl050_8048nt_c01, 4965 }, { 4966 .compatible = "winstar,wf35ltiacd", 4967 .data = &winstar_wf35ltiacd, 4968 }, { 4969 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4970 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4971 }, { 4972 /* Must be the last entry */ 4973 .compatible = "panel-dpi", 4974 .data = &panel_dpi, 4975 }, { 4976 /* sentinel */ 4977 } 4978 }; 4979 MODULE_DEVICE_TABLE(of, platform_of_match); 4980 4981 static int panel_simple_platform_probe(struct platform_device *pdev) 4982 { 4983 const struct panel_desc *desc; 4984 4985 desc = of_device_get_match_data(&pdev->dev); 4986 if (!desc) 4987 return -ENODEV; 4988 4989 return panel_simple_probe(&pdev->dev, desc); 4990 } 4991 4992 static void panel_simple_platform_remove(struct platform_device *pdev) 4993 { 4994 panel_simple_remove(&pdev->dev); 4995 } 4996 4997 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4998 { 4999 panel_simple_shutdown(&pdev->dev); 5000 } 5001 5002 static const struct dev_pm_ops panel_simple_pm_ops = { 5003 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 5004 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5005 pm_runtime_force_resume) 5006 }; 5007 5008 static struct platform_driver panel_simple_platform_driver = { 5009 .driver = { 5010 .name = "panel-simple", 5011 .of_match_table = platform_of_match, 5012 .pm = &panel_simple_pm_ops, 5013 }, 5014 .probe = panel_simple_platform_probe, 5015 .remove_new = panel_simple_platform_remove, 5016 .shutdown = panel_simple_platform_shutdown, 5017 }; 5018 5019 struct panel_desc_dsi { 5020 struct panel_desc desc; 5021 5022 unsigned long flags; 5023 enum mipi_dsi_pixel_format format; 5024 unsigned int lanes; 5025 }; 5026 5027 static const struct drm_display_mode auo_b080uan01_mode = { 5028 .clock = 154500, 5029 .hdisplay = 1200, 5030 .hsync_start = 1200 + 62, 5031 .hsync_end = 1200 + 62 + 4, 5032 .htotal = 1200 + 62 + 4 + 62, 5033 .vdisplay = 1920, 5034 .vsync_start = 1920 + 9, 5035 .vsync_end = 1920 + 9 + 2, 5036 .vtotal = 1920 + 9 + 2 + 8, 5037 }; 5038 5039 static const struct panel_desc_dsi auo_b080uan01 = { 5040 .desc = { 5041 .modes = &auo_b080uan01_mode, 5042 .num_modes = 1, 5043 .bpc = 8, 5044 .size = { 5045 .width = 108, 5046 .height = 272, 5047 }, 5048 .connector_type = DRM_MODE_CONNECTOR_DSI, 5049 }, 5050 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5051 .format = MIPI_DSI_FMT_RGB888, 5052 .lanes = 4, 5053 }; 5054 5055 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5056 .clock = 160000, 5057 .hdisplay = 1200, 5058 .hsync_start = 1200 + 120, 5059 .hsync_end = 1200 + 120 + 20, 5060 .htotal = 1200 + 120 + 20 + 21, 5061 .vdisplay = 1920, 5062 .vsync_start = 1920 + 21, 5063 .vsync_end = 1920 + 21 + 3, 5064 .vtotal = 1920 + 21 + 3 + 18, 5065 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5066 }; 5067 5068 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5069 .desc = { 5070 .modes = &boe_tv080wum_nl0_mode, 5071 .num_modes = 1, 5072 .size = { 5073 .width = 107, 5074 .height = 172, 5075 }, 5076 .connector_type = DRM_MODE_CONNECTOR_DSI, 5077 }, 5078 .flags = MIPI_DSI_MODE_VIDEO | 5079 MIPI_DSI_MODE_VIDEO_BURST | 5080 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5081 .format = MIPI_DSI_FMT_RGB888, 5082 .lanes = 4, 5083 }; 5084 5085 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 5086 .clock = 71000, 5087 .hdisplay = 800, 5088 .hsync_start = 800 + 32, 5089 .hsync_end = 800 + 32 + 1, 5090 .htotal = 800 + 32 + 1 + 57, 5091 .vdisplay = 1280, 5092 .vsync_start = 1280 + 28, 5093 .vsync_end = 1280 + 28 + 1, 5094 .vtotal = 1280 + 28 + 1 + 14, 5095 }; 5096 5097 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 5098 .desc = { 5099 .modes = &lg_ld070wx3_sl01_mode, 5100 .num_modes = 1, 5101 .bpc = 8, 5102 .size = { 5103 .width = 94, 5104 .height = 151, 5105 }, 5106 .connector_type = DRM_MODE_CONNECTOR_DSI, 5107 }, 5108 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5109 .format = MIPI_DSI_FMT_RGB888, 5110 .lanes = 4, 5111 }; 5112 5113 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5114 .clock = 67000, 5115 .hdisplay = 720, 5116 .hsync_start = 720 + 12, 5117 .hsync_end = 720 + 12 + 4, 5118 .htotal = 720 + 12 + 4 + 112, 5119 .vdisplay = 1280, 5120 .vsync_start = 1280 + 8, 5121 .vsync_end = 1280 + 8 + 4, 5122 .vtotal = 1280 + 8 + 4 + 12, 5123 }; 5124 5125 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5126 .desc = { 5127 .modes = &lg_lh500wx1_sd03_mode, 5128 .num_modes = 1, 5129 .bpc = 8, 5130 .size = { 5131 .width = 62, 5132 .height = 110, 5133 }, 5134 .connector_type = DRM_MODE_CONNECTOR_DSI, 5135 }, 5136 .flags = MIPI_DSI_MODE_VIDEO, 5137 .format = MIPI_DSI_FMT_RGB888, 5138 .lanes = 4, 5139 }; 5140 5141 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5142 .clock = 157200, 5143 .hdisplay = 1920, 5144 .hsync_start = 1920 + 154, 5145 .hsync_end = 1920 + 154 + 16, 5146 .htotal = 1920 + 154 + 16 + 32, 5147 .vdisplay = 1200, 5148 .vsync_start = 1200 + 17, 5149 .vsync_end = 1200 + 17 + 2, 5150 .vtotal = 1200 + 17 + 2 + 16, 5151 }; 5152 5153 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5154 .desc = { 5155 .modes = &panasonic_vvx10f004b00_mode, 5156 .num_modes = 1, 5157 .bpc = 8, 5158 .size = { 5159 .width = 217, 5160 .height = 136, 5161 }, 5162 .connector_type = DRM_MODE_CONNECTOR_DSI, 5163 }, 5164 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5165 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5166 .format = MIPI_DSI_FMT_RGB888, 5167 .lanes = 4, 5168 }; 5169 5170 static const struct drm_display_mode lg_acx467akm_7_mode = { 5171 .clock = 150000, 5172 .hdisplay = 1080, 5173 .hsync_start = 1080 + 2, 5174 .hsync_end = 1080 + 2 + 2, 5175 .htotal = 1080 + 2 + 2 + 2, 5176 .vdisplay = 1920, 5177 .vsync_start = 1920 + 2, 5178 .vsync_end = 1920 + 2 + 2, 5179 .vtotal = 1920 + 2 + 2 + 2, 5180 }; 5181 5182 static const struct panel_desc_dsi lg_acx467akm_7 = { 5183 .desc = { 5184 .modes = &lg_acx467akm_7_mode, 5185 .num_modes = 1, 5186 .bpc = 8, 5187 .size = { 5188 .width = 62, 5189 .height = 110, 5190 }, 5191 .connector_type = DRM_MODE_CONNECTOR_DSI, 5192 }, 5193 .flags = 0, 5194 .format = MIPI_DSI_FMT_RGB888, 5195 .lanes = 4, 5196 }; 5197 5198 static const struct drm_display_mode osd101t2045_53ts_mode = { 5199 .clock = 154500, 5200 .hdisplay = 1920, 5201 .hsync_start = 1920 + 112, 5202 .hsync_end = 1920 + 112 + 16, 5203 .htotal = 1920 + 112 + 16 + 32, 5204 .vdisplay = 1200, 5205 .vsync_start = 1200 + 16, 5206 .vsync_end = 1200 + 16 + 2, 5207 .vtotal = 1200 + 16 + 2 + 16, 5208 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5209 }; 5210 5211 static const struct panel_desc_dsi osd101t2045_53ts = { 5212 .desc = { 5213 .modes = &osd101t2045_53ts_mode, 5214 .num_modes = 1, 5215 .bpc = 8, 5216 .size = { 5217 .width = 217, 5218 .height = 136, 5219 }, 5220 .connector_type = DRM_MODE_CONNECTOR_DSI, 5221 }, 5222 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5223 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5224 MIPI_DSI_MODE_NO_EOT_PACKET, 5225 .format = MIPI_DSI_FMT_RGB888, 5226 .lanes = 4, 5227 }; 5228 5229 static const struct of_device_id dsi_of_match[] = { 5230 { 5231 .compatible = "auo,b080uan01", 5232 .data = &auo_b080uan01 5233 }, { 5234 .compatible = "boe,tv080wum-nl0", 5235 .data = &boe_tv080wum_nl0 5236 }, { 5237 .compatible = "lg,ld070wx3-sl01", 5238 .data = &lg_ld070wx3_sl01 5239 }, { 5240 .compatible = "lg,lh500wx1-sd03", 5241 .data = &lg_lh500wx1_sd03 5242 }, { 5243 .compatible = "panasonic,vvx10f004b00", 5244 .data = &panasonic_vvx10f004b00 5245 }, { 5246 .compatible = "lg,acx467akm-7", 5247 .data = &lg_acx467akm_7 5248 }, { 5249 .compatible = "osddisplays,osd101t2045-53ts", 5250 .data = &osd101t2045_53ts 5251 }, { 5252 /* sentinel */ 5253 } 5254 }; 5255 MODULE_DEVICE_TABLE(of, dsi_of_match); 5256 5257 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5258 { 5259 const struct panel_desc_dsi *desc; 5260 int err; 5261 5262 desc = of_device_get_match_data(&dsi->dev); 5263 if (!desc) 5264 return -ENODEV; 5265 5266 err = panel_simple_probe(&dsi->dev, &desc->desc); 5267 if (err < 0) 5268 return err; 5269 5270 dsi->mode_flags = desc->flags; 5271 dsi->format = desc->format; 5272 dsi->lanes = desc->lanes; 5273 5274 err = mipi_dsi_attach(dsi); 5275 if (err) { 5276 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5277 5278 drm_panel_remove(&panel->base); 5279 } 5280 5281 return err; 5282 } 5283 5284 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5285 { 5286 int err; 5287 5288 err = mipi_dsi_detach(dsi); 5289 if (err < 0) 5290 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5291 5292 panel_simple_remove(&dsi->dev); 5293 } 5294 5295 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5296 { 5297 panel_simple_shutdown(&dsi->dev); 5298 } 5299 5300 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5301 .driver = { 5302 .name = "panel-simple-dsi", 5303 .of_match_table = dsi_of_match, 5304 .pm = &panel_simple_pm_ops, 5305 }, 5306 .probe = panel_simple_dsi_probe, 5307 .remove = panel_simple_dsi_remove, 5308 .shutdown = panel_simple_dsi_shutdown, 5309 }; 5310 5311 static int __init panel_simple_init(void) 5312 { 5313 int err; 5314 5315 err = platform_driver_register(&panel_simple_platform_driver); 5316 if (err < 0) 5317 return err; 5318 5319 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5320 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5321 if (err < 0) 5322 goto err_did_platform_register; 5323 } 5324 5325 return 0; 5326 5327 err_did_platform_register: 5328 platform_driver_unregister(&panel_simple_platform_driver); 5329 5330 return err; 5331 } 5332 module_init(panel_simple_init); 5333 5334 static void __exit panel_simple_exit(void) 5335 { 5336 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5337 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5338 5339 platform_driver_unregister(&panel_simple_platform_driver); 5340 } 5341 module_exit(panel_simple_exit); 5342 5343 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5344 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5345 MODULE_LICENSE("GPL and additional rights"); 5346