1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_device.h> 30 #include <linux/of_platform.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/regulator/consumer.h> 34 35 #include <video/display_timing.h> 36 #include <video/of_display_timing.h> 37 #include <video/videomode.h> 38 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_device.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_mipi_dsi.h> 43 #include <drm/drm_panel.h> 44 #include <drm/drm_of.h> 45 46 /** 47 * struct panel_desc - Describes a simple panel. 48 */ 49 struct panel_desc { 50 /** 51 * @modes: Pointer to array of fixed modes appropriate for this panel. 52 * 53 * If only one mode then this can just be the address of the mode. 54 * NOTE: cannot be used with "timings" and also if this is specified 55 * then you cannot override the mode in the device tree. 56 */ 57 const struct drm_display_mode *modes; 58 59 /** @num_modes: Number of elements in modes array. */ 60 unsigned int num_modes; 61 62 /** 63 * @timings: Pointer to array of display timings 64 * 65 * NOTE: cannot be used with "modes" and also these will be used to 66 * validate a device tree override if one is present. 67 */ 68 const struct display_timing *timings; 69 70 /** @num_timings: Number of elements in timings array. */ 71 unsigned int num_timings; 72 73 /** @bpc: Bits per color. */ 74 unsigned int bpc; 75 76 /** @size: Structure containing the physical size of this panel. */ 77 struct { 78 /** 79 * @size.width: Width (in mm) of the active display area. 80 */ 81 unsigned int width; 82 83 /** 84 * @size.height: Height (in mm) of the active display area. 85 */ 86 unsigned int height; 87 } size; 88 89 /** @delay: Structure containing various delay values for this panel. */ 90 struct { 91 /** 92 * @delay.prepare: Time for the panel to become ready. 93 * 94 * The time (in milliseconds) that it takes for the panel to 95 * become ready and start receiving video data 96 */ 97 unsigned int prepare; 98 99 /** 100 * @delay.enable: Time for the panel to display a valid frame. 101 * 102 * The time (in milliseconds) that it takes for the panel to 103 * display the first valid frame after starting to receive 104 * video data. 105 */ 106 unsigned int enable; 107 108 /** 109 * @delay.disable: Time for the panel to turn the display off. 110 * 111 * The time (in milliseconds) that it takes for the panel to 112 * turn the display off (no content is visible). 113 */ 114 unsigned int disable; 115 116 /** 117 * @delay.unprepare: Time to power down completely. 118 * 119 * The time (in milliseconds) that it takes for the panel 120 * to power itself down completely. 121 * 122 * This time is used to prevent a future "prepare" from 123 * starting until at least this many milliseconds has passed. 124 * If at prepare time less time has passed since unprepare 125 * finished, the driver waits for the remaining time. 126 */ 127 unsigned int unprepare; 128 } delay; 129 130 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 131 u32 bus_format; 132 133 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 134 u32 bus_flags; 135 136 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 137 int connector_type; 138 }; 139 140 struct panel_desc_dsi { 141 struct panel_desc desc; 142 143 unsigned long flags; 144 enum mipi_dsi_pixel_format format; 145 unsigned int lanes; 146 }; 147 148 struct panel_simple { 149 struct drm_panel base; 150 151 ktime_t unprepared_time; 152 153 const struct panel_desc *desc; 154 155 struct regulator *supply; 156 struct i2c_adapter *ddc; 157 158 struct gpio_desc *enable_gpio; 159 160 const struct drm_edid *drm_edid; 161 162 struct drm_display_mode override_mode; 163 164 enum drm_panel_orientation orientation; 165 }; 166 167 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 168 { 169 return container_of(panel, struct panel_simple, base); 170 } 171 172 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 173 struct drm_connector *connector) 174 { 175 struct drm_display_mode *mode; 176 unsigned int i, num = 0; 177 178 for (i = 0; i < panel->desc->num_timings; i++) { 179 const struct display_timing *dt = &panel->desc->timings[i]; 180 struct videomode vm; 181 182 videomode_from_timing(dt, &vm); 183 mode = drm_mode_create(connector->dev); 184 if (!mode) { 185 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 186 dt->hactive.typ, dt->vactive.typ); 187 continue; 188 } 189 190 drm_display_mode_from_videomode(&vm, mode); 191 192 mode->type |= DRM_MODE_TYPE_DRIVER; 193 194 if (panel->desc->num_timings == 1) 195 mode->type |= DRM_MODE_TYPE_PREFERRED; 196 197 drm_mode_probed_add(connector, mode); 198 num++; 199 } 200 201 return num; 202 } 203 204 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 205 struct drm_connector *connector) 206 { 207 struct drm_display_mode *mode; 208 unsigned int i, num = 0; 209 210 for (i = 0; i < panel->desc->num_modes; i++) { 211 const struct drm_display_mode *m = &panel->desc->modes[i]; 212 213 mode = drm_mode_duplicate(connector->dev, m); 214 if (!mode) { 215 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 216 m->hdisplay, m->vdisplay, 217 drm_mode_vrefresh(m)); 218 continue; 219 } 220 221 mode->type |= DRM_MODE_TYPE_DRIVER; 222 223 if (panel->desc->num_modes == 1) 224 mode->type |= DRM_MODE_TYPE_PREFERRED; 225 226 drm_mode_set_name(mode); 227 228 drm_mode_probed_add(connector, mode); 229 num++; 230 } 231 232 return num; 233 } 234 235 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 236 struct drm_connector *connector) 237 { 238 struct drm_display_mode *mode; 239 bool has_override = panel->override_mode.type; 240 unsigned int num = 0; 241 242 if (!panel->desc) 243 return 0; 244 245 if (has_override) { 246 mode = drm_mode_duplicate(connector->dev, 247 &panel->override_mode); 248 if (mode) { 249 drm_mode_probed_add(connector, mode); 250 num = 1; 251 } else { 252 dev_err(panel->base.dev, "failed to add override mode\n"); 253 } 254 } 255 256 /* Only add timings if override was not there or failed to validate */ 257 if (num == 0 && panel->desc->num_timings) 258 num = panel_simple_get_timings_modes(panel, connector); 259 260 /* 261 * Only add fixed modes if timings/override added no mode. 262 * 263 * We should only ever have either the display timings specified 264 * or a fixed mode. Anything else is rather bogus. 265 */ 266 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 267 if (num == 0) 268 num = panel_simple_get_display_modes(panel, connector); 269 270 connector->display_info.bpc = panel->desc->bpc; 271 connector->display_info.width_mm = panel->desc->size.width; 272 connector->display_info.height_mm = panel->desc->size.height; 273 if (panel->desc->bus_format) 274 drm_display_info_set_bus_formats(&connector->display_info, 275 &panel->desc->bus_format, 1); 276 connector->display_info.bus_flags = panel->desc->bus_flags; 277 278 return num; 279 } 280 281 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 282 { 283 ktime_t now_ktime, min_ktime; 284 285 if (!min_ms) 286 return; 287 288 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 289 now_ktime = ktime_get_boottime(); 290 291 if (ktime_before(now_ktime, min_ktime)) 292 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 293 } 294 295 static int panel_simple_disable(struct drm_panel *panel) 296 { 297 struct panel_simple *p = to_panel_simple(panel); 298 299 if (p->desc->delay.disable) 300 msleep(p->desc->delay.disable); 301 302 return 0; 303 } 304 305 static int panel_simple_suspend(struct device *dev) 306 { 307 struct panel_simple *p = dev_get_drvdata(dev); 308 309 gpiod_set_value_cansleep(p->enable_gpio, 0); 310 regulator_disable(p->supply); 311 p->unprepared_time = ktime_get_boottime(); 312 313 drm_edid_free(p->drm_edid); 314 p->drm_edid = NULL; 315 316 return 0; 317 } 318 319 static int panel_simple_unprepare(struct drm_panel *panel) 320 { 321 int ret; 322 323 pm_runtime_mark_last_busy(panel->dev); 324 ret = pm_runtime_put_autosuspend(panel->dev); 325 if (ret < 0) 326 return ret; 327 328 return 0; 329 } 330 331 static int panel_simple_resume(struct device *dev) 332 { 333 struct panel_simple *p = dev_get_drvdata(dev); 334 int err; 335 336 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 337 338 err = regulator_enable(p->supply); 339 if (err < 0) { 340 dev_err(dev, "failed to enable supply: %d\n", err); 341 return err; 342 } 343 344 gpiod_set_value_cansleep(p->enable_gpio, 1); 345 346 if (p->desc->delay.prepare) 347 msleep(p->desc->delay.prepare); 348 349 return 0; 350 } 351 352 static int panel_simple_prepare(struct drm_panel *panel) 353 { 354 int ret; 355 356 ret = pm_runtime_get_sync(panel->dev); 357 if (ret < 0) { 358 pm_runtime_put_autosuspend(panel->dev); 359 return ret; 360 } 361 362 return 0; 363 } 364 365 static int panel_simple_enable(struct drm_panel *panel) 366 { 367 struct panel_simple *p = to_panel_simple(panel); 368 369 if (p->desc->delay.enable) 370 msleep(p->desc->delay.enable); 371 372 return 0; 373 } 374 375 static int panel_simple_get_modes(struct drm_panel *panel, 376 struct drm_connector *connector) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 int num = 0; 380 381 /* probe EDID if a DDC bus is available */ 382 if (p->ddc) { 383 pm_runtime_get_sync(panel->dev); 384 385 if (!p->drm_edid) 386 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 387 388 drm_edid_connector_update(connector, p->drm_edid); 389 390 num += drm_edid_connector_add_modes(connector); 391 392 pm_runtime_mark_last_busy(panel->dev); 393 pm_runtime_put_autosuspend(panel->dev); 394 } 395 396 /* add hard-coded panel modes */ 397 num += panel_simple_get_non_edid_modes(p, connector); 398 399 /* 400 * TODO: Remove once all drm drivers call 401 * drm_connector_set_orientation_from_panel() 402 */ 403 drm_connector_set_panel_orientation(connector, p->orientation); 404 405 return num; 406 } 407 408 static int panel_simple_get_timings(struct drm_panel *panel, 409 unsigned int num_timings, 410 struct display_timing *timings) 411 { 412 struct panel_simple *p = to_panel_simple(panel); 413 unsigned int i; 414 415 if (p->desc->num_timings < num_timings) 416 num_timings = p->desc->num_timings; 417 418 if (timings) 419 for (i = 0; i < num_timings; i++) 420 timings[i] = p->desc->timings[i]; 421 422 return p->desc->num_timings; 423 } 424 425 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 426 { 427 struct panel_simple *p = to_panel_simple(panel); 428 429 return p->orientation; 430 } 431 432 static const struct drm_panel_funcs panel_simple_funcs = { 433 .disable = panel_simple_disable, 434 .unprepare = panel_simple_unprepare, 435 .prepare = panel_simple_prepare, 436 .enable = panel_simple_enable, 437 .get_modes = panel_simple_get_modes, 438 .get_orientation = panel_simple_get_orientation, 439 .get_timings = panel_simple_get_timings, 440 }; 441 442 static struct panel_desc *panel_dpi_probe(struct device *dev) 443 { 444 struct display_timing *timing; 445 const struct device_node *np; 446 struct panel_desc *desc; 447 unsigned int bus_flags; 448 struct videomode vm; 449 int ret; 450 451 np = dev->of_node; 452 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 453 if (!desc) 454 return ERR_PTR(-ENOMEM); 455 456 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 457 if (!timing) 458 return ERR_PTR(-ENOMEM); 459 460 ret = of_get_display_timing(np, "panel-timing", timing); 461 if (ret < 0) { 462 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 463 np); 464 return ERR_PTR(ret); 465 } 466 467 desc->timings = timing; 468 desc->num_timings = 1; 469 470 of_property_read_u32(np, "width-mm", &desc->size.width); 471 of_property_read_u32(np, "height-mm", &desc->size.height); 472 473 /* Extract bus_flags from display_timing */ 474 bus_flags = 0; 475 vm.flags = timing->flags; 476 drm_bus_flags_from_videomode(&vm, &bus_flags); 477 desc->bus_flags = bus_flags; 478 479 /* We do not know the connector for the DT node, so guess it */ 480 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 481 482 return desc; 483 } 484 485 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 486 (to_check->field.typ >= bounds->field.min && \ 487 to_check->field.typ <= bounds->field.max) 488 static void panel_simple_parse_panel_timing_node(struct device *dev, 489 struct panel_simple *panel, 490 const struct display_timing *ot) 491 { 492 const struct panel_desc *desc = panel->desc; 493 struct videomode vm; 494 unsigned int i; 495 496 if (WARN_ON(desc->num_modes)) { 497 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 498 return; 499 } 500 if (WARN_ON(!desc->num_timings)) { 501 dev_err(dev, "Reject override mode: no timings specified\n"); 502 return; 503 } 504 505 for (i = 0; i < panel->desc->num_timings; i++) { 506 const struct display_timing *dt = &panel->desc->timings[i]; 507 508 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 512 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 513 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 514 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 515 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 516 continue; 517 518 if (ot->flags != dt->flags) 519 continue; 520 521 videomode_from_timing(ot, &vm); 522 drm_display_mode_from_videomode(&vm, &panel->override_mode); 523 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 524 DRM_MODE_TYPE_PREFERRED; 525 break; 526 } 527 528 if (WARN_ON(!panel->override_mode.type)) 529 dev_err(dev, "Reject override mode: No display_timing found\n"); 530 } 531 532 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 533 struct panel_simple *panel) 534 { 535 int ret, bpc; 536 537 ret = drm_of_lvds_get_data_mapping(dev->of_node); 538 if (ret < 0) { 539 if (ret == -EINVAL) 540 dev_warn(dev, "Ignore invalid data-mapping property\n"); 541 542 /* 543 * Ignore non-existing or malformatted property, fallback to 544 * default data-mapping, and return 0. 545 */ 546 return 0; 547 } 548 549 switch (ret) { 550 default: 551 WARN_ON(1); 552 fallthrough; 553 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 554 fallthrough; 555 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 556 bpc = 8; 557 break; 558 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 559 bpc = 6; 560 } 561 562 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 563 struct panel_desc *override_desc; 564 565 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 566 if (!override_desc) 567 return -ENOMEM; 568 569 override_desc->bus_format = ret; 570 override_desc->bpc = bpc; 571 panel->desc = override_desc; 572 } 573 574 return 0; 575 } 576 577 static const struct panel_desc *panel_simple_get_desc(struct device *dev) 578 { 579 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI) && 580 dev_is_mipi_dsi(dev)) { 581 const struct panel_desc_dsi *dsi_desc; 582 583 dsi_desc = of_device_get_match_data(dev); 584 if (!dsi_desc) 585 return ERR_PTR(-ENODEV); 586 587 return &dsi_desc->desc; 588 } 589 590 if (dev_is_platform(dev)) { 591 const struct panel_desc *desc; 592 593 desc = of_device_get_match_data(dev); 594 if (!desc) { 595 /* 596 * panel-dpi probes without a descriptor and 597 * panel_dpi_probe() will initialize one for us 598 * based on the device tree. 599 */ 600 if (of_device_is_compatible(dev->of_node, "panel-dpi")) 601 return panel_dpi_probe(dev); 602 else 603 return ERR_PTR(-ENODEV); 604 } 605 606 return desc; 607 } 608 609 return ERR_PTR(-ENODEV); 610 } 611 612 static struct panel_simple *panel_simple_probe(struct device *dev) 613 { 614 const struct panel_desc *desc; 615 struct panel_simple *panel; 616 struct display_timing dt; 617 struct device_node *ddc; 618 int connector_type; 619 u32 bus_flags; 620 int err; 621 622 desc = panel_simple_get_desc(dev); 623 if (IS_ERR(desc)) 624 return ERR_CAST(desc); 625 626 connector_type = desc->connector_type; 627 /* Catch common mistakes for panels. */ 628 switch (connector_type) { 629 case 0: 630 dev_warn(dev, "Specify missing connector_type\n"); 631 connector_type = DRM_MODE_CONNECTOR_DPI; 632 break; 633 case DRM_MODE_CONNECTOR_LVDS: 634 WARN_ON(desc->bus_flags & 635 ~(DRM_BUS_FLAG_DE_LOW | 636 DRM_BUS_FLAG_DE_HIGH | 637 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 638 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 639 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 640 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 641 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 642 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 643 desc->bpc != 6); 644 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 645 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 646 desc->bpc != 8); 647 break; 648 case DRM_MODE_CONNECTOR_eDP: 649 dev_warn(dev, "eDP panels moved to panel-edp\n"); 650 return ERR_PTR(-EINVAL); 651 case DRM_MODE_CONNECTOR_DSI: 652 if (desc->bpc != 6 && desc->bpc != 8) 653 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 654 break; 655 case DRM_MODE_CONNECTOR_DPI: 656 bus_flags = DRM_BUS_FLAG_DE_LOW | 657 DRM_BUS_FLAG_DE_HIGH | 658 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 659 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 660 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 661 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 662 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 663 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 664 if (desc->bus_flags & ~bus_flags) 665 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 666 if (!(desc->bus_flags & bus_flags)) 667 dev_warn(dev, "Specify missing bus_flags\n"); 668 if (desc->bus_format == 0) 669 dev_warn(dev, "Specify missing bus_format\n"); 670 if (desc->bpc != 6 && desc->bpc != 8) 671 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 672 break; 673 default: 674 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 675 connector_type = DRM_MODE_CONNECTOR_DPI; 676 break; 677 } 678 679 panel = devm_drm_panel_alloc(dev, struct panel_simple, base, 680 &panel_simple_funcs, connector_type); 681 if (IS_ERR(panel)) 682 return ERR_CAST(panel); 683 684 panel->desc = desc; 685 686 panel->supply = devm_regulator_get(dev, "power"); 687 if (IS_ERR(panel->supply)) 688 return ERR_CAST(panel->supply); 689 690 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 691 GPIOD_OUT_LOW); 692 if (IS_ERR(panel->enable_gpio)) 693 return dev_err_cast_probe(dev, panel->enable_gpio, 694 "failed to request GPIO\n"); 695 696 err = drm_of_get_panel_orientation(dev->of_node, &panel->orientation); 697 if (err) { 698 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 699 return ERR_PTR(err); 700 } 701 702 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 703 if (ddc) { 704 panel->ddc = of_find_i2c_adapter_by_node(ddc); 705 of_node_put(ddc); 706 707 if (!panel->ddc) 708 return ERR_PTR(-EPROBE_DEFER); 709 } 710 711 if (!of_device_is_compatible(dev->of_node, "panel-dpi") && 712 !of_get_display_timing(dev->of_node, "panel-timing", &dt)) 713 panel_simple_parse_panel_timing_node(dev, panel, &dt); 714 715 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 716 /* Optional data-mapping property for overriding bus format */ 717 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 718 if (err) 719 goto free_ddc; 720 } 721 722 dev_set_drvdata(dev, panel); 723 724 /* 725 * We use runtime PM for prepare / unprepare since those power the panel 726 * on and off and those can be very slow operations. This is important 727 * to optimize powering the panel on briefly to read the EDID before 728 * fully enabling the panel. 729 */ 730 pm_runtime_enable(dev); 731 pm_runtime_set_autosuspend_delay(dev, 1000); 732 pm_runtime_use_autosuspend(dev); 733 734 err = drm_panel_of_backlight(&panel->base); 735 if (err) { 736 dev_err_probe(dev, err, "Could not find backlight\n"); 737 goto disable_pm_runtime; 738 } 739 740 drm_panel_add(&panel->base); 741 742 return panel; 743 744 disable_pm_runtime: 745 pm_runtime_dont_use_autosuspend(dev); 746 pm_runtime_disable(dev); 747 free_ddc: 748 if (panel->ddc) 749 put_device(&panel->ddc->dev); 750 751 return ERR_PTR(err); 752 } 753 754 static void panel_simple_shutdown(struct device *dev) 755 { 756 struct panel_simple *panel = dev_get_drvdata(dev); 757 758 /* 759 * NOTE: the following two calls don't really belong here. It is the 760 * responsibility of a correctly written DRM modeset driver to call 761 * drm_atomic_helper_shutdown() at shutdown time and that should 762 * cause the panel to be disabled / unprepared if needed. For now, 763 * however, we'll keep these calls due to the sheer number of 764 * different DRM modeset drivers used with panel-simple. Once we've 765 * confirmed that all DRM modeset drivers using this panel properly 766 * call drm_atomic_helper_shutdown() we can simply delete the two 767 * calls below. 768 * 769 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 770 * PANEL DRIVERS. 771 * 772 * FIXME: If we're still haven't figured out if all DRM modeset 773 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 774 * managed to make sure that DRM modeset drivers get their shutdown() 775 * callback before the panel's shutdown() callback (perhaps using 776 * device link), we could add a WARN_ON here to help move forward. 777 */ 778 if (panel->base.enabled) 779 drm_panel_disable(&panel->base); 780 if (panel->base.prepared) 781 drm_panel_unprepare(&panel->base); 782 } 783 784 static void panel_simple_remove(struct device *dev) 785 { 786 struct panel_simple *panel = dev_get_drvdata(dev); 787 788 drm_panel_remove(&panel->base); 789 panel_simple_shutdown(dev); 790 791 pm_runtime_dont_use_autosuspend(dev); 792 pm_runtime_disable(dev); 793 if (panel->ddc) 794 put_device(&panel->ddc->dev); 795 } 796 797 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 798 .clock = 71100, 799 .hdisplay = 1280, 800 .hsync_start = 1280 + 40, 801 .hsync_end = 1280 + 40 + 80, 802 .htotal = 1280 + 40 + 80 + 40, 803 .vdisplay = 800, 804 .vsync_start = 800 + 3, 805 .vsync_end = 800 + 3 + 10, 806 .vtotal = 800 + 3 + 10 + 10, 807 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 808 }; 809 810 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 811 .modes = &ire_am_1280800n3tzqw_t00h_mode, 812 .num_modes = 1, 813 .bpc = 8, 814 .size = { 815 .width = 217, 816 .height = 136, 817 }, 818 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 819 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 820 .connector_type = DRM_MODE_CONNECTOR_LVDS, 821 }; 822 823 static const struct drm_display_mode ampire_am_1280800w8tzqw_t00h_mode = { 824 .clock = 72400, 825 .hdisplay = 1280, 826 .hsync_start = 1280 + 40, 827 .hsync_end = 1280 + 40 + 80, 828 .htotal = 1280 + 40 + 80 + 40, 829 .vdisplay = 800, 830 .vsync_start = 800 + 10, 831 .vsync_end = 800 + 10 + 18, 832 .vtotal = 800 + 10 + 18 + 10, 833 }; 834 835 static const struct panel_desc ampire_am_1280800w8tzqw_t00h = { 836 .modes = &ire_am_1280800w8tzqw_t00h_mode, 837 .num_modes = 1, 838 .bpc = 8, 839 .size = { 840 .width = 217, 841 .height = 136, 842 }, 843 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 844 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 845 .connector_type = DRM_MODE_CONNECTOR_LVDS, 846 }; 847 848 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 849 .clock = 9000, 850 .hdisplay = 480, 851 .hsync_start = 480 + 2, 852 .hsync_end = 480 + 2 + 41, 853 .htotal = 480 + 2 + 41 + 2, 854 .vdisplay = 272, 855 .vsync_start = 272 + 2, 856 .vsync_end = 272 + 2 + 10, 857 .vtotal = 272 + 2 + 10 + 2, 858 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 859 }; 860 861 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 862 .modes = &ire_am_480272h3tmqw_t01h_mode, 863 .num_modes = 1, 864 .bpc = 8, 865 .size = { 866 .width = 99, 867 .height = 58, 868 }, 869 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 870 }; 871 872 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 873 .clock = 33333, 874 .hdisplay = 800, 875 .hsync_start = 800 + 0, 876 .hsync_end = 800 + 0 + 255, 877 .htotal = 800 + 0 + 255 + 0, 878 .vdisplay = 480, 879 .vsync_start = 480 + 2, 880 .vsync_end = 480 + 2 + 45, 881 .vtotal = 480 + 2 + 45 + 0, 882 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 883 }; 884 885 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 886 .pixelclock = { 29930000, 33260000, 36590000 }, 887 .hactive = { 800, 800, 800 }, 888 .hfront_porch = { 1, 40, 168 }, 889 .hback_porch = { 88, 88, 88 }, 890 .hsync_len = { 1, 128, 128 }, 891 .vactive = { 480, 480, 480 }, 892 .vfront_porch = { 1, 35, 37 }, 893 .vback_porch = { 8, 8, 8 }, 894 .vsync_len = { 1, 2, 2 }, 895 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 896 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 897 DISPLAY_FLAGS_SYNC_POSEDGE, 898 }; 899 900 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 901 .timings = &ire_am_800480l1tmqw_t00h_timing, 902 .num_timings = 1, 903 .bpc = 8, 904 .size = { 905 .width = 111, 906 .height = 67, 907 }, 908 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 909 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 910 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 911 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 912 .connector_type = DRM_MODE_CONNECTOR_DPI, 913 }; 914 915 static const struct display_timing ampire_am_800480n3tzqw_00h_timing = { 916 .pixelclock = {23000000, 25000000, 27000000}, 917 .hactive = { 800, 800, 800 }, 918 .hfront_porch = { 4, 8, 48 }, 919 .hback_porch = { 4, 8, 48 }, 920 .hsync_len = { 2, 8, 8 }, 921 .vactive = { 480, 480, 480 }, 922 .vfront_porch = { 4, 8, 12 }, 923 .vback_porch = { 4, 8, 12 }, 924 .vsync_len = { 2, 4, 8 }, 925 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 926 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 927 DISPLAY_FLAGS_SYNC_POSEDGE, 928 }; 929 930 static const struct panel_desc ampire_am_800480n3tzqw_00h = { 931 .timings = &ire_am_800480n3tzqw_00h_timing, 932 .num_timings = 1, 933 .bpc = 8, 934 .size = { 935 .width = 108, 936 .height = 65, 937 }, 938 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 939 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 940 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 941 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 942 .connector_type = DRM_MODE_CONNECTOR_DPI, 943 }; 944 945 static const struct panel_desc ampire_am800480r3tmqwa1h = { 946 .modes = &ire_am800480r3tmqwa1h_mode, 947 .num_modes = 1, 948 .bpc = 6, 949 .size = { 950 .width = 152, 951 .height = 91, 952 }, 953 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 954 }; 955 956 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 957 .pixelclock = { 34500000, 39600000, 50400000 }, 958 .hactive = { 800, 800, 800 }, 959 .hfront_porch = { 12, 112, 312 }, 960 .hback_porch = { 87, 87, 48 }, 961 .hsync_len = { 1, 1, 40 }, 962 .vactive = { 600, 600, 600 }, 963 .vfront_porch = { 1, 21, 61 }, 964 .vback_porch = { 38, 38, 19 }, 965 .vsync_len = { 1, 1, 20 }, 966 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 967 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 968 DISPLAY_FLAGS_SYNC_POSEDGE, 969 }; 970 971 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 972 .timings = &ire_am800600p5tmqw_tb8h_timing, 973 .num_timings = 1, 974 .bpc = 6, 975 .size = { 976 .width = 162, 977 .height = 122, 978 }, 979 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 980 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 981 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 982 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 983 .connector_type = DRM_MODE_CONNECTOR_DPI, 984 }; 985 986 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 987 .pixelclock = { 26400000, 33300000, 46800000 }, 988 .hactive = { 800, 800, 800 }, 989 .hfront_porch = { 16, 210, 354 }, 990 .hback_porch = { 45, 36, 6 }, 991 .hsync_len = { 1, 10, 40 }, 992 .vactive = { 480, 480, 480 }, 993 .vfront_porch = { 7, 22, 147 }, 994 .vback_porch = { 22, 13, 3 }, 995 .vsync_len = { 1, 10, 20 }, 996 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 997 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 998 }; 999 1000 static const struct panel_desc armadeus_st0700_adapt = { 1001 .timings = &santek_st0700i5y_rbslw_f_timing, 1002 .num_timings = 1, 1003 .bpc = 6, 1004 .size = { 1005 .width = 154, 1006 .height = 86, 1007 }, 1008 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1009 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1010 }; 1011 1012 static const struct drm_display_mode auo_b101aw03_mode = { 1013 .clock = 51450, 1014 .hdisplay = 1024, 1015 .hsync_start = 1024 + 156, 1016 .hsync_end = 1024 + 156 + 8, 1017 .htotal = 1024 + 156 + 8 + 156, 1018 .vdisplay = 600, 1019 .vsync_start = 600 + 16, 1020 .vsync_end = 600 + 16 + 6, 1021 .vtotal = 600 + 16 + 6 + 16, 1022 }; 1023 1024 static const struct panel_desc auo_b101aw03 = { 1025 .modes = &auo_b101aw03_mode, 1026 .num_modes = 1, 1027 .bpc = 6, 1028 .size = { 1029 .width = 223, 1030 .height = 125, 1031 }, 1032 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1033 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1034 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1035 }; 1036 1037 static const struct drm_display_mode auo_b101xtn01_mode = { 1038 .clock = 72000, 1039 .hdisplay = 1366, 1040 .hsync_start = 1366 + 20, 1041 .hsync_end = 1366 + 20 + 70, 1042 .htotal = 1366 + 20 + 70, 1043 .vdisplay = 768, 1044 .vsync_start = 768 + 14, 1045 .vsync_end = 768 + 14 + 42, 1046 .vtotal = 768 + 14 + 42, 1047 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1048 }; 1049 1050 static const struct panel_desc auo_b101xtn01 = { 1051 .modes = &auo_b101xtn01_mode, 1052 .num_modes = 1, 1053 .bpc = 6, 1054 .size = { 1055 .width = 223, 1056 .height = 125, 1057 }, 1058 }; 1059 1060 static const struct drm_display_mode auo_b116xw03_mode = { 1061 .clock = 70589, 1062 .hdisplay = 1366, 1063 .hsync_start = 1366 + 40, 1064 .hsync_end = 1366 + 40 + 40, 1065 .htotal = 1366 + 40 + 40 + 32, 1066 .vdisplay = 768, 1067 .vsync_start = 768 + 10, 1068 .vsync_end = 768 + 10 + 12, 1069 .vtotal = 768 + 10 + 12 + 6, 1070 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1071 }; 1072 1073 static const struct panel_desc auo_b116xw03 = { 1074 .modes = &auo_b116xw03_mode, 1075 .num_modes = 1, 1076 .bpc = 6, 1077 .size = { 1078 .width = 256, 1079 .height = 144, 1080 }, 1081 .delay = { 1082 .prepare = 1, 1083 .enable = 200, 1084 .disable = 200, 1085 .unprepare = 500, 1086 }, 1087 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1088 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1089 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1090 }; 1091 1092 static const struct display_timing auo_g070vvn01_timings = { 1093 .pixelclock = { 33300000, 34209000, 45000000 }, 1094 .hactive = { 800, 800, 800 }, 1095 .hfront_porch = { 20, 40, 200 }, 1096 .hback_porch = { 87, 40, 1 }, 1097 .hsync_len = { 1, 48, 87 }, 1098 .vactive = { 480, 480, 480 }, 1099 .vfront_porch = { 5, 13, 200 }, 1100 .vback_porch = { 31, 31, 29 }, 1101 .vsync_len = { 1, 1, 3 }, 1102 }; 1103 1104 static const struct panel_desc auo_g070vvn01 = { 1105 .timings = &auo_g070vvn01_timings, 1106 .num_timings = 1, 1107 .bpc = 8, 1108 .size = { 1109 .width = 152, 1110 .height = 91, 1111 }, 1112 .delay = { 1113 .prepare = 200, 1114 .enable = 50, 1115 .disable = 50, 1116 .unprepare = 1000, 1117 }, 1118 }; 1119 1120 static const struct display_timing auo_g101evn010_timing = { 1121 .pixelclock = { 64000000, 68930000, 85000000 }, 1122 .hactive = { 1280, 1280, 1280 }, 1123 .hfront_porch = { 8, 64, 256 }, 1124 .hback_porch = { 8, 64, 256 }, 1125 .hsync_len = { 40, 168, 767 }, 1126 .vactive = { 800, 800, 800 }, 1127 .vfront_porch = { 4, 8, 100 }, 1128 .vback_porch = { 4, 8, 100 }, 1129 .vsync_len = { 8, 16, 223 }, 1130 }; 1131 1132 static const struct panel_desc auo_g101evn010 = { 1133 .timings = &auo_g101evn010_timing, 1134 .num_timings = 1, 1135 .bpc = 6, 1136 .size = { 1137 .width = 216, 1138 .height = 135, 1139 }, 1140 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1141 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1142 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1143 }; 1144 1145 static const struct drm_display_mode auo_g104sn02_mode = { 1146 .clock = 40000, 1147 .hdisplay = 800, 1148 .hsync_start = 800 + 40, 1149 .hsync_end = 800 + 40 + 216, 1150 .htotal = 800 + 40 + 216 + 128, 1151 .vdisplay = 600, 1152 .vsync_start = 600 + 10, 1153 .vsync_end = 600 + 10 + 35, 1154 .vtotal = 600 + 10 + 35 + 2, 1155 }; 1156 1157 static const struct panel_desc auo_g104sn02 = { 1158 .modes = &auo_g104sn02_mode, 1159 .num_modes = 1, 1160 .bpc = 8, 1161 .size = { 1162 .width = 211, 1163 .height = 158, 1164 }, 1165 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1166 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1167 }; 1168 1169 static const struct drm_display_mode auo_g104stn01_mode = { 1170 .clock = 40000, 1171 .hdisplay = 800, 1172 .hsync_start = 800 + 40, 1173 .hsync_end = 800 + 40 + 88, 1174 .htotal = 800 + 40 + 88 + 128, 1175 .vdisplay = 600, 1176 .vsync_start = 600 + 1, 1177 .vsync_end = 600 + 1 + 23, 1178 .vtotal = 600 + 1 + 23 + 4, 1179 }; 1180 1181 static const struct panel_desc auo_g104stn01 = { 1182 .modes = &auo_g104stn01_mode, 1183 .num_modes = 1, 1184 .bpc = 8, 1185 .size = { 1186 .width = 211, 1187 .height = 158, 1188 }, 1189 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1190 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1191 }; 1192 1193 static const struct display_timing auo_g121ean01_timing = { 1194 .pixelclock = { 60000000, 74400000, 90000000 }, 1195 .hactive = { 1280, 1280, 1280 }, 1196 .hfront_porch = { 20, 50, 100 }, 1197 .hback_porch = { 20, 50, 100 }, 1198 .hsync_len = { 30, 100, 200 }, 1199 .vactive = { 800, 800, 800 }, 1200 .vfront_porch = { 2, 10, 25 }, 1201 .vback_porch = { 2, 10, 25 }, 1202 .vsync_len = { 4, 18, 50 }, 1203 }; 1204 1205 static const struct panel_desc auo_g121ean01 = { 1206 .timings = &auo_g121ean01_timing, 1207 .num_timings = 1, 1208 .bpc = 8, 1209 .size = { 1210 .width = 261, 1211 .height = 163, 1212 }, 1213 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1214 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1215 }; 1216 1217 static const struct display_timing auo_g133han01_timings = { 1218 .pixelclock = { 134000000, 141200000, 149000000 }, 1219 .hactive = { 1920, 1920, 1920 }, 1220 .hfront_porch = { 39, 58, 77 }, 1221 .hback_porch = { 59, 88, 117 }, 1222 .hsync_len = { 28, 42, 56 }, 1223 .vactive = { 1080, 1080, 1080 }, 1224 .vfront_porch = { 3, 8, 11 }, 1225 .vback_porch = { 5, 14, 19 }, 1226 .vsync_len = { 4, 14, 19 }, 1227 }; 1228 1229 static const struct panel_desc auo_g133han01 = { 1230 .timings = &auo_g133han01_timings, 1231 .num_timings = 1, 1232 .bpc = 8, 1233 .size = { 1234 .width = 293, 1235 .height = 165, 1236 }, 1237 .delay = { 1238 .prepare = 200, 1239 .enable = 50, 1240 .disable = 50, 1241 .unprepare = 1000, 1242 }, 1243 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1244 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1245 }; 1246 1247 static const struct display_timing auo_g156han04_timings = { 1248 .pixelclock = { 137000000, 141000000, 146000000 }, 1249 .hactive = { 1920, 1920, 1920 }, 1250 .hfront_porch = { 60, 60, 60 }, 1251 .hback_porch = { 90, 92, 111 }, 1252 .hsync_len = { 32, 32, 32 }, 1253 .vactive = { 1080, 1080, 1080 }, 1254 .vfront_porch = { 12, 12, 12 }, 1255 .vback_porch = { 24, 36, 56 }, 1256 .vsync_len = { 8, 8, 8 }, 1257 }; 1258 1259 static const struct panel_desc auo_g156han04 = { 1260 .timings = &auo_g156han04_timings, 1261 .num_timings = 1, 1262 .bpc = 8, 1263 .size = { 1264 .width = 344, 1265 .height = 194, 1266 }, 1267 .delay = { 1268 .prepare = 50, /* T2 */ 1269 .enable = 200, /* T3 */ 1270 .disable = 110, /* T10 */ 1271 .unprepare = 1000, /* T13 */ 1272 }, 1273 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1274 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1275 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1276 }; 1277 1278 static const struct drm_display_mode auo_g156xtn01_mode = { 1279 .clock = 76000, 1280 .hdisplay = 1366, 1281 .hsync_start = 1366 + 33, 1282 .hsync_end = 1366 + 33 + 67, 1283 .htotal = 1560, 1284 .vdisplay = 768, 1285 .vsync_start = 768 + 4, 1286 .vsync_end = 768 + 4 + 4, 1287 .vtotal = 806, 1288 }; 1289 1290 static const struct panel_desc auo_g156xtn01 = { 1291 .modes = &auo_g156xtn01_mode, 1292 .num_modes = 1, 1293 .bpc = 8, 1294 .size = { 1295 .width = 344, 1296 .height = 194, 1297 }, 1298 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1299 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1300 }; 1301 1302 static const struct display_timing auo_g185han01_timings = { 1303 .pixelclock = { 120000000, 144000000, 175000000 }, 1304 .hactive = { 1920, 1920, 1920 }, 1305 .hfront_porch = { 36, 120, 148 }, 1306 .hback_porch = { 24, 88, 108 }, 1307 .hsync_len = { 20, 48, 64 }, 1308 .vactive = { 1080, 1080, 1080 }, 1309 .vfront_porch = { 6, 10, 40 }, 1310 .vback_porch = { 2, 5, 20 }, 1311 .vsync_len = { 2, 5, 20 }, 1312 }; 1313 1314 static const struct panel_desc auo_g185han01 = { 1315 .timings = &auo_g185han01_timings, 1316 .num_timings = 1, 1317 .bpc = 8, 1318 .size = { 1319 .width = 409, 1320 .height = 230, 1321 }, 1322 .delay = { 1323 .prepare = 50, 1324 .enable = 200, 1325 .disable = 110, 1326 .unprepare = 1000, 1327 }, 1328 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1329 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1330 }; 1331 1332 static const struct display_timing auo_g190ean01_timings = { 1333 .pixelclock = { 90000000, 108000000, 135000000 }, 1334 .hactive = { 1280, 1280, 1280 }, 1335 .hfront_porch = { 126, 184, 1266 }, 1336 .hback_porch = { 84, 122, 844 }, 1337 .hsync_len = { 70, 102, 704 }, 1338 .vactive = { 1024, 1024, 1024 }, 1339 .vfront_porch = { 4, 26, 76 }, 1340 .vback_porch = { 2, 8, 25 }, 1341 .vsync_len = { 2, 8, 25 }, 1342 }; 1343 1344 static const struct panel_desc auo_g190ean01 = { 1345 .timings = &auo_g190ean01_timings, 1346 .num_timings = 1, 1347 .bpc = 8, 1348 .size = { 1349 .width = 376, 1350 .height = 301, 1351 }, 1352 .delay = { 1353 .prepare = 30, 1354 .enable = 200, 1355 .disable = 110, 1356 .unprepare = 1000, 1357 }, 1358 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1359 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1360 }; 1361 1362 static const struct display_timing auo_p238han01_timings = { 1363 .pixelclock = { 107400000, 142400000, 180000000 }, 1364 .hactive = { 1920, 1920, 1920 }, 1365 .hfront_porch = { 30, 70, 650 }, 1366 .hback_porch = { 30, 70, 650 }, 1367 .hsync_len = { 20, 40, 136 }, 1368 .vactive = { 1080, 1080, 1080 }, 1369 .vfront_porch = { 5, 19, 318 }, 1370 .vback_porch = { 5, 19, 318 }, 1371 .vsync_len = { 4, 12, 120 }, 1372 }; 1373 1374 static const struct panel_desc auo_p238han01 = { 1375 .timings = &auo_p238han01_timings, 1376 .num_timings = 1, 1377 .bpc = 8, 1378 .size = { 1379 .width = 527, 1380 .height = 296, 1381 }, 1382 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1383 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1384 }; 1385 1386 static const struct display_timing auo_p320hvn03_timings = { 1387 .pixelclock = { 106000000, 148500000, 164000000 }, 1388 .hactive = { 1920, 1920, 1920 }, 1389 .hfront_porch = { 25, 50, 130 }, 1390 .hback_porch = { 25, 50, 130 }, 1391 .hsync_len = { 20, 40, 105 }, 1392 .vactive = { 1080, 1080, 1080 }, 1393 .vfront_porch = { 8, 17, 150 }, 1394 .vback_porch = { 8, 17, 150 }, 1395 .vsync_len = { 4, 11, 100 }, 1396 }; 1397 1398 static const struct panel_desc auo_p320hvn03 = { 1399 .timings = &auo_p320hvn03_timings, 1400 .num_timings = 1, 1401 .bpc = 8, 1402 .size = { 1403 .width = 698, 1404 .height = 393, 1405 }, 1406 .delay = { 1407 .prepare = 1, 1408 .enable = 450, 1409 .unprepare = 500, 1410 }, 1411 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1412 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1413 }; 1414 1415 static const struct drm_display_mode auo_t215hvn01_mode = { 1416 .clock = 148800, 1417 .hdisplay = 1920, 1418 .hsync_start = 1920 + 88, 1419 .hsync_end = 1920 + 88 + 44, 1420 .htotal = 1920 + 88 + 44 + 148, 1421 .vdisplay = 1080, 1422 .vsync_start = 1080 + 4, 1423 .vsync_end = 1080 + 4 + 5, 1424 .vtotal = 1080 + 4 + 5 + 36, 1425 }; 1426 1427 static const struct panel_desc auo_t215hvn01 = { 1428 .modes = &auo_t215hvn01_mode, 1429 .num_modes = 1, 1430 .bpc = 8, 1431 .size = { 1432 .width = 430, 1433 .height = 270, 1434 }, 1435 .delay = { 1436 .disable = 5, 1437 .unprepare = 1000, 1438 }, 1439 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1440 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1441 }; 1442 1443 static const struct drm_display_mode avic_tm070ddh03_mode = { 1444 .clock = 51200, 1445 .hdisplay = 1024, 1446 .hsync_start = 1024 + 160, 1447 .hsync_end = 1024 + 160 + 4, 1448 .htotal = 1024 + 160 + 4 + 156, 1449 .vdisplay = 600, 1450 .vsync_start = 600 + 17, 1451 .vsync_end = 600 + 17 + 1, 1452 .vtotal = 600 + 17 + 1 + 17, 1453 }; 1454 1455 static const struct panel_desc avic_tm070ddh03 = { 1456 .modes = &avic_tm070ddh03_mode, 1457 .num_modes = 1, 1458 .bpc = 8, 1459 .size = { 1460 .width = 154, 1461 .height = 90, 1462 }, 1463 .delay = { 1464 .prepare = 20, 1465 .enable = 200, 1466 .disable = 200, 1467 }, 1468 }; 1469 1470 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1471 .clock = 30000, 1472 .hdisplay = 800, 1473 .hsync_start = 800 + 40, 1474 .hsync_end = 800 + 40 + 48, 1475 .htotal = 800 + 40 + 48 + 40, 1476 .vdisplay = 480, 1477 .vsync_start = 480 + 13, 1478 .vsync_end = 480 + 13 + 3, 1479 .vtotal = 480 + 13 + 3 + 29, 1480 }; 1481 1482 static const struct panel_desc bananapi_s070wv20_ct16 = { 1483 .modes = &bananapi_s070wv20_ct16_mode, 1484 .num_modes = 1, 1485 .bpc = 6, 1486 .size = { 1487 .width = 154, 1488 .height = 86, 1489 }, 1490 }; 1491 1492 static const struct display_timing boe_av101hdt_a10_timing = { 1493 .pixelclock = { 74210000, 75330000, 76780000, }, 1494 .hactive = { 1280, 1280, 1280, }, 1495 .hfront_porch = { 10, 42, 33, }, 1496 .hback_porch = { 10, 18, 33, }, 1497 .hsync_len = { 30, 10, 30, }, 1498 .vactive = { 720, 720, 720, }, 1499 .vfront_porch = { 200, 183, 200, }, 1500 .vback_porch = { 8, 8, 8, }, 1501 .vsync_len = { 2, 19, 2, }, 1502 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1503 }; 1504 1505 static const struct panel_desc boe_av101hdt_a10 = { 1506 .timings = &boe_av101hdt_a10_timing, 1507 .num_timings = 1, 1508 .bpc = 8, 1509 .size = { 1510 .width = 224, 1511 .height = 126, 1512 }, 1513 .delay = { 1514 .enable = 50, 1515 .disable = 50, 1516 }, 1517 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1518 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1519 }; 1520 1521 static const struct display_timing boe_av123z7m_n17_timing = { 1522 .pixelclock = { 86600000, 88000000, 90800000, }, 1523 .hactive = { 1920, 1920, 1920, }, 1524 .hfront_porch = { 10, 10, 10, }, 1525 .hback_porch = { 10, 10, 10, }, 1526 .hsync_len = { 9, 12, 25, }, 1527 .vactive = { 720, 720, 720, }, 1528 .vfront_porch = { 7, 10, 13, }, 1529 .vback_porch = { 7, 10, 13, }, 1530 .vsync_len = { 7, 11, 14, }, 1531 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1532 }; 1533 1534 static const struct panel_desc boe_av123z7m_n17 = { 1535 .timings = &boe_av123z7m_n17_timing, 1536 .bpc = 8, 1537 .num_timings = 1, 1538 .size = { 1539 .width = 292, 1540 .height = 110, 1541 }, 1542 .delay = { 1543 .prepare = 50, 1544 .disable = 50, 1545 }, 1546 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1547 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1548 }; 1549 1550 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1551 .clock = 78945, 1552 .hdisplay = 1280, 1553 .hsync_start = 1280 + 0, 1554 .hsync_end = 1280 + 0 + 2, 1555 .htotal = 1280 + 62 + 0 + 2, 1556 .vdisplay = 800, 1557 .vsync_start = 800 + 8, 1558 .vsync_end = 800 + 8 + 2, 1559 .vtotal = 800 + 6 + 8 + 2, 1560 }; 1561 1562 static const struct panel_desc boe_bp082wx1_100 = { 1563 .modes = &boe_bp101wx1_100_mode, 1564 .num_modes = 1, 1565 .bpc = 8, 1566 .size = { 1567 .width = 177, 1568 .height = 110, 1569 }, 1570 .delay = { 1571 .enable = 50, 1572 .disable = 50, 1573 }, 1574 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1575 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1576 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1577 }; 1578 1579 static const struct panel_desc boe_bp101wx1_100 = { 1580 .modes = &boe_bp101wx1_100_mode, 1581 .num_modes = 1, 1582 .bpc = 8, 1583 .size = { 1584 .width = 217, 1585 .height = 136, 1586 }, 1587 .delay = { 1588 .enable = 50, 1589 .disable = 50, 1590 }, 1591 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1592 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1593 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1594 }; 1595 1596 static const struct display_timing boe_dv215fhm_r01_timing = { 1597 .pixelclock = { 148500000, 148500000, 148500000 }, 1598 .hactive = { 1920, 1920, 1920 }, 1599 .hfront_porch = { 88, 88, 88 }, 1600 .hback_porch = { 148, 148, 148 }, 1601 .hsync_len = { 44, 44, 44 }, 1602 .vactive = { 1080, 1080, 1080 }, 1603 .vfront_porch = { 4, 4, 4 }, 1604 .vback_porch = { 36, 36, 36 }, 1605 .vsync_len = { 5, 5, 5 }, 1606 .flags = DISPLAY_FLAGS_DE_HIGH, 1607 }; 1608 1609 static const struct panel_desc boe_dv215fhm_r01 = { 1610 .timings = &boe_dv215fhm_r01_timing, 1611 .num_timings = 1, 1612 .bpc = 8, 1613 .size = { 1614 .width = 476, 1615 .height = 268, 1616 }, 1617 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1618 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1619 }; 1620 1621 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1622 .pixelclock = { 69922000, 71000000, 72293000 }, 1623 .hactive = { 1280, 1280, 1280 }, 1624 .hfront_porch = { 48, 48, 48 }, 1625 .hback_porch = { 80, 80, 80 }, 1626 .hsync_len = { 32, 32, 32 }, 1627 .vactive = { 800, 800, 800 }, 1628 .vfront_porch = { 3, 3, 3 }, 1629 .vback_porch = { 14, 14, 14 }, 1630 .vsync_len = { 6, 6, 6 }, 1631 }; 1632 1633 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1634 .timings = &boe_ev121wxm_n10_1850_timing, 1635 .num_timings = 1, 1636 .bpc = 8, 1637 .size = { 1638 .width = 261, 1639 .height = 163, 1640 }, 1641 .delay = { 1642 .prepare = 9, 1643 .enable = 300, 1644 .unprepare = 300, 1645 .disable = 560, 1646 }, 1647 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1648 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1649 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1650 }; 1651 1652 static const struct drm_display_mode boe_hv070wsa_mode = { 1653 .clock = 42105, 1654 .hdisplay = 1024, 1655 .hsync_start = 1024 + 30, 1656 .hsync_end = 1024 + 30 + 30, 1657 .htotal = 1024 + 30 + 30 + 30, 1658 .vdisplay = 600, 1659 .vsync_start = 600 + 10, 1660 .vsync_end = 600 + 10 + 10, 1661 .vtotal = 600 + 10 + 10 + 10, 1662 }; 1663 1664 static const struct panel_desc boe_hv070wsa = { 1665 .modes = &boe_hv070wsa_mode, 1666 .num_modes = 1, 1667 .bpc = 8, 1668 .size = { 1669 .width = 154, 1670 .height = 90, 1671 }, 1672 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1673 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1674 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1675 }; 1676 1677 static const struct display_timing cct_cmt430b19n00_timing = { 1678 .pixelclock = { 8000000, 9000000, 12000000 }, 1679 .hactive = { 480, 480, 480 }, 1680 .hfront_porch = { 2, 8, 75 }, 1681 .hback_porch = { 3, 43, 43 }, 1682 .hsync_len = { 2, 4, 75 }, 1683 .vactive = { 272, 272, 272 }, 1684 .vfront_porch = { 2, 8, 37 }, 1685 .vback_porch = { 2, 12, 12 }, 1686 .vsync_len = { 2, 4, 37 }, 1687 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1688 }; 1689 1690 static const struct panel_desc cct_cmt430b19n00 = { 1691 .timings = &cct_cmt430b19n00_timing, 1692 .num_timings = 1, 1693 .bpc = 8, 1694 .size = { 1695 .width = 95, 1696 .height = 53, 1697 }, 1698 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1699 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1700 .connector_type = DRM_MODE_CONNECTOR_DPI, 1701 }; 1702 1703 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1704 .clock = 9000, 1705 .hdisplay = 480, 1706 .hsync_start = 480 + 5, 1707 .hsync_end = 480 + 5 + 5, 1708 .htotal = 480 + 5 + 5 + 40, 1709 .vdisplay = 272, 1710 .vsync_start = 272 + 8, 1711 .vsync_end = 272 + 8 + 8, 1712 .vtotal = 272 + 8 + 8 + 8, 1713 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1714 }; 1715 1716 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1717 .modes = &cdtech_s043wq26h_ct7_mode, 1718 .num_modes = 1, 1719 .bpc = 8, 1720 .size = { 1721 .width = 95, 1722 .height = 54, 1723 }, 1724 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1725 }; 1726 1727 /* S070PWS19HP-FC21 2017/04/22 */ 1728 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1729 .clock = 51200, 1730 .hdisplay = 1024, 1731 .hsync_start = 1024 + 160, 1732 .hsync_end = 1024 + 160 + 20, 1733 .htotal = 1024 + 160 + 20 + 140, 1734 .vdisplay = 600, 1735 .vsync_start = 600 + 12, 1736 .vsync_end = 600 + 12 + 3, 1737 .vtotal = 600 + 12 + 3 + 20, 1738 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1739 }; 1740 1741 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1742 .modes = &cdtech_s070pws19hp_fc21_mode, 1743 .num_modes = 1, 1744 .bpc = 6, 1745 .size = { 1746 .width = 154, 1747 .height = 86, 1748 }, 1749 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1750 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1751 .connector_type = DRM_MODE_CONNECTOR_DPI, 1752 }; 1753 1754 /* S070SWV29HG-DC44 2017/09/21 */ 1755 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1756 .clock = 33300, 1757 .hdisplay = 800, 1758 .hsync_start = 800 + 210, 1759 .hsync_end = 800 + 210 + 2, 1760 .htotal = 800 + 210 + 2 + 44, 1761 .vdisplay = 480, 1762 .vsync_start = 480 + 22, 1763 .vsync_end = 480 + 22 + 2, 1764 .vtotal = 480 + 22 + 2 + 21, 1765 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1766 }; 1767 1768 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1769 .modes = &cdtech_s070swv29hg_dc44_mode, 1770 .num_modes = 1, 1771 .bpc = 6, 1772 .size = { 1773 .width = 154, 1774 .height = 86, 1775 }, 1776 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1777 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1778 .connector_type = DRM_MODE_CONNECTOR_DPI, 1779 }; 1780 1781 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1782 .clock = 35000, 1783 .hdisplay = 800, 1784 .hsync_start = 800 + 40, 1785 .hsync_end = 800 + 40 + 40, 1786 .htotal = 800 + 40 + 40 + 48, 1787 .vdisplay = 480, 1788 .vsync_start = 480 + 29, 1789 .vsync_end = 480 + 29 + 13, 1790 .vtotal = 480 + 29 + 13 + 3, 1791 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1792 }; 1793 1794 static const struct panel_desc cdtech_s070wv95_ct16 = { 1795 .modes = &cdtech_s070wv95_ct16_mode, 1796 .num_modes = 1, 1797 .bpc = 8, 1798 .size = { 1799 .width = 154, 1800 .height = 85, 1801 }, 1802 }; 1803 1804 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1805 .pixelclock = { 68900000, 71100000, 73400000 }, 1806 .hactive = { 1280, 1280, 1280 }, 1807 .hfront_porch = { 65, 80, 95 }, 1808 .hback_porch = { 64, 79, 94 }, 1809 .hsync_len = { 1, 1, 1 }, 1810 .vactive = { 800, 800, 800 }, 1811 .vfront_porch = { 7, 11, 14 }, 1812 .vback_porch = { 7, 11, 14 }, 1813 .vsync_len = { 1, 1, 1 }, 1814 .flags = DISPLAY_FLAGS_DE_HIGH, 1815 }; 1816 1817 static const struct panel_desc chefree_ch101olhlwh_002 = { 1818 .timings = &chefree_ch101olhlwh_002_timing, 1819 .num_timings = 1, 1820 .bpc = 8, 1821 .size = { 1822 .width = 217, 1823 .height = 135, 1824 }, 1825 .delay = { 1826 .enable = 200, 1827 .disable = 200, 1828 }, 1829 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1830 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1831 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1832 }; 1833 1834 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1835 .clock = 66770, 1836 .hdisplay = 800, 1837 .hsync_start = 800 + 49, 1838 .hsync_end = 800 + 49 + 33, 1839 .htotal = 800 + 49 + 33 + 17, 1840 .vdisplay = 1280, 1841 .vsync_start = 1280 + 1, 1842 .vsync_end = 1280 + 1 + 7, 1843 .vtotal = 1280 + 1 + 7 + 15, 1844 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1845 }; 1846 1847 static const struct panel_desc chunghwa_claa070wp03xg = { 1848 .modes = &chunghwa_claa070wp03xg_mode, 1849 .num_modes = 1, 1850 .bpc = 6, 1851 .size = { 1852 .width = 94, 1853 .height = 150, 1854 }, 1855 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1856 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1857 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1858 }; 1859 1860 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1861 .clock = 72070, 1862 .hdisplay = 1366, 1863 .hsync_start = 1366 + 58, 1864 .hsync_end = 1366 + 58 + 58, 1865 .htotal = 1366 + 58 + 58 + 58, 1866 .vdisplay = 768, 1867 .vsync_start = 768 + 4, 1868 .vsync_end = 768 + 4 + 4, 1869 .vtotal = 768 + 4 + 4 + 4, 1870 }; 1871 1872 static const struct panel_desc chunghwa_claa101wa01a = { 1873 .modes = &chunghwa_claa101wa01a_mode, 1874 .num_modes = 1, 1875 .bpc = 6, 1876 .size = { 1877 .width = 220, 1878 .height = 120, 1879 }, 1880 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1881 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1882 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1883 }; 1884 1885 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1886 .clock = 69300, 1887 .hdisplay = 1366, 1888 .hsync_start = 1366 + 48, 1889 .hsync_end = 1366 + 48 + 32, 1890 .htotal = 1366 + 48 + 32 + 20, 1891 .vdisplay = 768, 1892 .vsync_start = 768 + 16, 1893 .vsync_end = 768 + 16 + 8, 1894 .vtotal = 768 + 16 + 8 + 16, 1895 }; 1896 1897 static const struct panel_desc chunghwa_claa101wb01 = { 1898 .modes = &chunghwa_claa101wb01_mode, 1899 .num_modes = 1, 1900 .bpc = 6, 1901 .size = { 1902 .width = 223, 1903 .height = 125, 1904 }, 1905 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1906 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1907 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1908 }; 1909 1910 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1911 .pixelclock = { 5000000, 9000000, 12000000 }, 1912 .hactive = { 480, 480, 480 }, 1913 .hfront_porch = { 12, 12, 12 }, 1914 .hback_porch = { 12, 12, 12 }, 1915 .hsync_len = { 21, 21, 21 }, 1916 .vactive = { 272, 272, 272 }, 1917 .vfront_porch = { 4, 4, 4 }, 1918 .vback_porch = { 4, 4, 4 }, 1919 .vsync_len = { 8, 8, 8 }, 1920 }; 1921 1922 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1923 .timings = &dataimage_fg040346dsswbg04_timing, 1924 .num_timings = 1, 1925 .bpc = 8, 1926 .size = { 1927 .width = 95, 1928 .height = 54, 1929 }, 1930 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1931 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1932 .connector_type = DRM_MODE_CONNECTOR_DPI, 1933 }; 1934 1935 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1936 .pixelclock = { 68900000, 71110000, 73400000 }, 1937 .hactive = { 1280, 1280, 1280 }, 1938 .vactive = { 800, 800, 800 }, 1939 .hback_porch = { 100, 100, 100 }, 1940 .hfront_porch = { 100, 100, 100 }, 1941 .vback_porch = { 5, 5, 5 }, 1942 .vfront_porch = { 5, 5, 5 }, 1943 .hsync_len = { 24, 24, 24 }, 1944 .vsync_len = { 3, 3, 3 }, 1945 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1946 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1947 }; 1948 1949 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1950 .timings = &dataimage_fg1001l0dsswmg01_timing, 1951 .num_timings = 1, 1952 .bpc = 8, 1953 .size = { 1954 .width = 217, 1955 .height = 136, 1956 }, 1957 }; 1958 1959 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1960 .clock = 33260, 1961 .hdisplay = 800, 1962 .hsync_start = 800 + 40, 1963 .hsync_end = 800 + 40 + 128, 1964 .htotal = 800 + 40 + 128 + 88, 1965 .vdisplay = 480, 1966 .vsync_start = 480 + 10, 1967 .vsync_end = 480 + 10 + 2, 1968 .vtotal = 480 + 10 + 2 + 33, 1969 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1970 }; 1971 1972 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1973 .modes = &dataimage_scf0700c48ggu18_mode, 1974 .num_modes = 1, 1975 .bpc = 8, 1976 .size = { 1977 .width = 152, 1978 .height = 91, 1979 }, 1980 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1981 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1982 .connector_type = DRM_MODE_CONNECTOR_DPI, 1983 }; 1984 1985 static const struct display_timing displaytech_dt050btft_pts_timing = { 1986 /* The TYP pixel clock are recalculated from tV * tH * 60 Hz */ 1987 .pixelclock = { 30000000, 33264000, 50000000 }, 1988 .hactive = { 800, 800, 800 }, 1989 .hfront_porch = { 16, 210, 354 }, 1990 /* Datasheet Figure 3 indicates, that tHPW is part of tHBP */ 1991 .hback_porch = { 41, 26, 6 }, 1992 .hsync_len = { 1, 20, 40 }, 1993 .vactive = { 480, 480, 480 }, 1994 .vfront_porch = { 7, 22, 147 }, 1995 /* Datasheet Figure 2 indicates, that tVPW is part of tVBP */ 1996 .vback_porch = { 22, 13, 3 }, 1997 .vsync_len = { 1, 10, 20 }, 1998 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1999 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2000 DISPLAY_FLAGS_SYNC_POSEDGE, 2001 }; 2002 2003 static const struct panel_desc displaytech_dt050btft_pts = { 2004 .timings = &displaytech_dt050btft_pts_timing, 2005 .num_timings = 1, 2006 .bpc = 8, 2007 .size = { 2008 .width = 108, 2009 .height = 65, 2010 }, 2011 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2012 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2013 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2014 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2015 .connector_type = DRM_MODE_CONNECTOR_DPI, 2016 }; 2017 2018 static const struct display_timing dlc_dlc0700yzg_1_timing = { 2019 .pixelclock = { 45000000, 51200000, 57000000 }, 2020 .hactive = { 1024, 1024, 1024 }, 2021 .hfront_porch = { 100, 106, 113 }, 2022 .hback_porch = { 100, 106, 113 }, 2023 .hsync_len = { 100, 108, 114 }, 2024 .vactive = { 600, 600, 600 }, 2025 .vfront_porch = { 8, 11, 15 }, 2026 .vback_porch = { 8, 11, 15 }, 2027 .vsync_len = { 9, 13, 15 }, 2028 .flags = DISPLAY_FLAGS_DE_HIGH, 2029 }; 2030 2031 static const struct panel_desc dlc_dlc0700yzg_1 = { 2032 .timings = &dlc_dlc0700yzg_1_timing, 2033 .num_timings = 1, 2034 .bpc = 6, 2035 .size = { 2036 .width = 154, 2037 .height = 86, 2038 }, 2039 .delay = { 2040 .prepare = 30, 2041 .enable = 200, 2042 .disable = 200, 2043 }, 2044 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2045 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2046 }; 2047 2048 static const struct display_timing dlc_dlc1010gig_timing = { 2049 .pixelclock = { 68900000, 71100000, 73400000 }, 2050 .hactive = { 1280, 1280, 1280 }, 2051 .hfront_porch = { 43, 53, 63 }, 2052 .hback_porch = { 43, 53, 63 }, 2053 .hsync_len = { 44, 54, 64 }, 2054 .vactive = { 800, 800, 800 }, 2055 .vfront_porch = { 5, 8, 11 }, 2056 .vback_porch = { 5, 8, 11 }, 2057 .vsync_len = { 5, 7, 11 }, 2058 .flags = DISPLAY_FLAGS_DE_HIGH, 2059 }; 2060 2061 static const struct panel_desc dlc_dlc1010gig = { 2062 .timings = &dlc_dlc1010gig_timing, 2063 .num_timings = 1, 2064 .bpc = 8, 2065 .size = { 2066 .width = 216, 2067 .height = 135, 2068 }, 2069 .delay = { 2070 .prepare = 60, 2071 .enable = 150, 2072 .disable = 100, 2073 .unprepare = 60, 2074 }, 2075 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2076 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2077 }; 2078 2079 static const struct drm_display_mode edt_et035012dm6_mode = { 2080 .clock = 6500, 2081 .hdisplay = 320, 2082 .hsync_start = 320 + 20, 2083 .hsync_end = 320 + 20 + 30, 2084 .htotal = 320 + 20 + 68, 2085 .vdisplay = 240, 2086 .vsync_start = 240 + 4, 2087 .vsync_end = 240 + 4 + 4, 2088 .vtotal = 240 + 4 + 4 + 14, 2089 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2090 }; 2091 2092 static const struct panel_desc edt_et035012dm6 = { 2093 .modes = &edt_et035012dm6_mode, 2094 .num_modes = 1, 2095 .bpc = 8, 2096 .size = { 2097 .width = 70, 2098 .height = 52, 2099 }, 2100 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2101 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2102 }; 2103 2104 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 2105 .clock = 6520, 2106 .hdisplay = 320, 2107 .hsync_start = 320 + 20, 2108 .hsync_end = 320 + 20 + 68, 2109 .htotal = 320 + 20 + 68, 2110 .vdisplay = 240, 2111 .vsync_start = 240 + 4, 2112 .vsync_end = 240 + 4 + 18, 2113 .vtotal = 240 + 4 + 18, 2114 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2115 }; 2116 2117 static const struct panel_desc edt_etm0350g0dh6 = { 2118 .modes = &edt_etm0350g0dh6_mode, 2119 .num_modes = 1, 2120 .bpc = 6, 2121 .size = { 2122 .width = 70, 2123 .height = 53, 2124 }, 2125 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2126 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2127 .connector_type = DRM_MODE_CONNECTOR_DPI, 2128 }; 2129 2130 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 2131 .clock = 10870, 2132 .hdisplay = 480, 2133 .hsync_start = 480 + 8, 2134 .hsync_end = 480 + 8 + 4, 2135 .htotal = 480 + 8 + 4 + 41, 2136 2137 /* 2138 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 2139 * fb_align 2140 */ 2141 2142 .vdisplay = 288, 2143 .vsync_start = 288 + 2, 2144 .vsync_end = 288 + 2 + 4, 2145 .vtotal = 288 + 2 + 4 + 10, 2146 }; 2147 2148 static const struct panel_desc edt_etm043080dh6gp = { 2149 .modes = &edt_etm043080dh6gp_mode, 2150 .num_modes = 1, 2151 .bpc = 8, 2152 .size = { 2153 .width = 100, 2154 .height = 65, 2155 }, 2156 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2157 .connector_type = DRM_MODE_CONNECTOR_DPI, 2158 }; 2159 2160 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 2161 .clock = 9000, 2162 .hdisplay = 480, 2163 .hsync_start = 480 + 2, 2164 .hsync_end = 480 + 2 + 41, 2165 .htotal = 480 + 2 + 41 + 2, 2166 .vdisplay = 272, 2167 .vsync_start = 272 + 2, 2168 .vsync_end = 272 + 2 + 10, 2169 .vtotal = 272 + 2 + 10 + 2, 2170 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2171 }; 2172 2173 static const struct panel_desc edt_etm0430g0dh6 = { 2174 .modes = &edt_etm0430g0dh6_mode, 2175 .num_modes = 1, 2176 .bpc = 6, 2177 .size = { 2178 .width = 95, 2179 .height = 54, 2180 }, 2181 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2182 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2183 .connector_type = DRM_MODE_CONNECTOR_DPI, 2184 }; 2185 2186 static const struct drm_display_mode edt_et057090dhu_mode = { 2187 .clock = 25175, 2188 .hdisplay = 640, 2189 .hsync_start = 640 + 16, 2190 .hsync_end = 640 + 16 + 30, 2191 .htotal = 640 + 16 + 30 + 114, 2192 .vdisplay = 480, 2193 .vsync_start = 480 + 10, 2194 .vsync_end = 480 + 10 + 3, 2195 .vtotal = 480 + 10 + 3 + 32, 2196 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2197 }; 2198 2199 static const struct panel_desc edt_et057090dhu = { 2200 .modes = &edt_et057090dhu_mode, 2201 .num_modes = 1, 2202 .bpc = 6, 2203 .size = { 2204 .width = 115, 2205 .height = 86, 2206 }, 2207 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2208 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2209 .connector_type = DRM_MODE_CONNECTOR_DPI, 2210 }; 2211 2212 static const struct display_timing edt_et057023udba_timing = { 2213 .pixelclock = { 23200000, 24190000, 39640000 }, 2214 .hactive = { 640, 640, 640 }, 2215 .hfront_porch = { 20, 40, 200 }, 2216 .hback_porch = { 87, 40, 1 }, 2217 .hsync_len = { 1, 48, 87 }, 2218 .vactive = { 480, 480, 480 }, 2219 .vfront_porch = { 5, 13, 200 }, 2220 .vback_porch = { 31, 31, 29 }, 2221 .vsync_len = { 1, 1, 3 }, 2222 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2223 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2224 DISPLAY_FLAGS_SYNC_POSEDGE, 2225 }; 2226 2227 static const struct panel_desc edt_et057023udba = { 2228 .timings = &edt_et057023udba_timing, 2229 .num_timings = 1, 2230 .bpc = 8, 2231 .size = { 2232 .width = 115, 2233 .height = 86, 2234 }, 2235 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2236 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2237 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2238 .connector_type = DRM_MODE_CONNECTOR_DPI, 2239 }; 2240 2241 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2242 .clock = 33260, 2243 .hdisplay = 800, 2244 .hsync_start = 800 + 40, 2245 .hsync_end = 800 + 40 + 128, 2246 .htotal = 800 + 40 + 128 + 88, 2247 .vdisplay = 480, 2248 .vsync_start = 480 + 10, 2249 .vsync_end = 480 + 10 + 2, 2250 .vtotal = 480 + 10 + 2 + 33, 2251 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2252 }; 2253 2254 static const struct panel_desc edt_etm0700g0dh6 = { 2255 .modes = &edt_etm0700g0dh6_mode, 2256 .num_modes = 1, 2257 .bpc = 6, 2258 .size = { 2259 .width = 152, 2260 .height = 91, 2261 }, 2262 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2263 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2264 .connector_type = DRM_MODE_CONNECTOR_DPI, 2265 }; 2266 2267 static const struct panel_desc edt_etm0700g0bdh6 = { 2268 .modes = &edt_etm0700g0dh6_mode, 2269 .num_modes = 1, 2270 .bpc = 6, 2271 .size = { 2272 .width = 152, 2273 .height = 91, 2274 }, 2275 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2276 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2277 .connector_type = DRM_MODE_CONNECTOR_DPI, 2278 }; 2279 2280 static const struct display_timing edt_etml0700y5dha_timing = { 2281 .pixelclock = { 40800000, 51200000, 67200000 }, 2282 .hactive = { 1024, 1024, 1024 }, 2283 .hfront_porch = { 30, 106, 125 }, 2284 .hback_porch = { 30, 106, 125 }, 2285 .hsync_len = { 30, 108, 126 }, 2286 .vactive = { 600, 600, 600 }, 2287 .vfront_porch = { 3, 12, 67}, 2288 .vback_porch = { 3, 12, 67 }, 2289 .vsync_len = { 4, 11, 66 }, 2290 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2291 DISPLAY_FLAGS_DE_HIGH, 2292 }; 2293 2294 static const struct panel_desc edt_etml0700y5dha = { 2295 .timings = &edt_etml0700y5dha_timing, 2296 .num_timings = 1, 2297 .bpc = 8, 2298 .size = { 2299 .width = 155, 2300 .height = 86, 2301 }, 2302 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2303 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2304 }; 2305 2306 static const struct display_timing edt_etml1010g3dra_timing = { 2307 .pixelclock = { 66300000, 72400000, 78900000 }, 2308 .hactive = { 1280, 1280, 1280 }, 2309 .hfront_porch = { 12, 72, 132 }, 2310 .hback_porch = { 86, 86, 86 }, 2311 .hsync_len = { 2, 2, 2 }, 2312 .vactive = { 800, 800, 800 }, 2313 .vfront_porch = { 1, 15, 49 }, 2314 .vback_porch = { 21, 21, 21 }, 2315 .vsync_len = { 2, 2, 2 }, 2316 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2317 DISPLAY_FLAGS_DE_HIGH, 2318 }; 2319 2320 static const struct panel_desc edt_etml1010g3dra = { 2321 .timings = &edt_etml1010g3dra_timing, 2322 .num_timings = 1, 2323 .bpc = 8, 2324 .size = { 2325 .width = 216, 2326 .height = 135, 2327 }, 2328 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2329 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2330 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2331 }; 2332 2333 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2334 .clock = 25175, 2335 .hdisplay = 640, 2336 .hsync_start = 640, 2337 .hsync_end = 640 + 16, 2338 .htotal = 640 + 16 + 30 + 114, 2339 .vdisplay = 480, 2340 .vsync_start = 480 + 10, 2341 .vsync_end = 480 + 10 + 3, 2342 .vtotal = 480 + 10 + 3 + 35, 2343 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2344 }; 2345 2346 static const struct panel_desc edt_etmv570g2dhu = { 2347 .modes = &edt_etmv570g2dhu_mode, 2348 .num_modes = 1, 2349 .bpc = 6, 2350 .size = { 2351 .width = 115, 2352 .height = 86, 2353 }, 2354 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2355 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2356 .connector_type = DRM_MODE_CONNECTOR_DPI, 2357 }; 2358 2359 static const struct display_timing eink_vb3300_kca_timing = { 2360 .pixelclock = { 40000000, 40000000, 40000000 }, 2361 .hactive = { 334, 334, 334 }, 2362 .hfront_porch = { 1, 1, 1 }, 2363 .hback_porch = { 1, 1, 1 }, 2364 .hsync_len = { 1, 1, 1 }, 2365 .vactive = { 1405, 1405, 1405 }, 2366 .vfront_porch = { 1, 1, 1 }, 2367 .vback_porch = { 1, 1, 1 }, 2368 .vsync_len = { 1, 1, 1 }, 2369 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2370 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2371 }; 2372 2373 static const struct panel_desc eink_vb3300_kca = { 2374 .timings = &eink_vb3300_kca_timing, 2375 .num_timings = 1, 2376 .bpc = 6, 2377 .size = { 2378 .width = 157, 2379 .height = 209, 2380 }, 2381 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2382 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2383 .connector_type = DRM_MODE_CONNECTOR_DPI, 2384 }; 2385 2386 static const struct display_timing evervision_vgg644804_timing = { 2387 .pixelclock = { 25175000, 25175000, 25175000 }, 2388 .hactive = { 640, 640, 640 }, 2389 .hfront_porch = { 16, 16, 16 }, 2390 .hback_porch = { 82, 114, 170 }, 2391 .hsync_len = { 5, 30, 30 }, 2392 .vactive = { 480, 480, 480 }, 2393 .vfront_porch = { 10, 10, 10 }, 2394 .vback_porch = { 30, 32, 34 }, 2395 .vsync_len = { 1, 3, 5 }, 2396 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2397 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2398 DISPLAY_FLAGS_SYNC_POSEDGE, 2399 }; 2400 2401 static const struct panel_desc evervision_vgg644804 = { 2402 .timings = &evervision_vgg644804_timing, 2403 .num_timings = 1, 2404 .bpc = 6, 2405 .size = { 2406 .width = 115, 2407 .height = 86, 2408 }, 2409 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2410 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2411 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2412 }; 2413 2414 static const struct display_timing evervision_vgg804821_timing = { 2415 .pixelclock = { 27600000, 33300000, 50000000 }, 2416 .hactive = { 800, 800, 800 }, 2417 .hfront_porch = { 40, 66, 70 }, 2418 .hback_porch = { 40, 67, 70 }, 2419 .hsync_len = { 40, 67, 70 }, 2420 .vactive = { 480, 480, 480 }, 2421 .vfront_porch = { 6, 10, 10 }, 2422 .vback_porch = { 7, 11, 11 }, 2423 .vsync_len = { 7, 11, 11 }, 2424 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2425 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2426 DISPLAY_FLAGS_SYNC_NEGEDGE, 2427 }; 2428 2429 static const struct panel_desc evervision_vgg804821 = { 2430 .timings = &evervision_vgg804821_timing, 2431 .num_timings = 1, 2432 .bpc = 8, 2433 .size = { 2434 .width = 108, 2435 .height = 64, 2436 }, 2437 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2438 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2439 }; 2440 2441 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2442 .clock = 32260, 2443 .hdisplay = 800, 2444 .hsync_start = 800 + 168, 2445 .hsync_end = 800 + 168 + 64, 2446 .htotal = 800 + 168 + 64 + 88, 2447 .vdisplay = 480, 2448 .vsync_start = 480 + 37, 2449 .vsync_end = 480 + 37 + 2, 2450 .vtotal = 480 + 37 + 2 + 8, 2451 }; 2452 2453 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2454 .modes = &foxlink_fl500wvr00_a0t_mode, 2455 .num_modes = 1, 2456 .bpc = 8, 2457 .size = { 2458 .width = 108, 2459 .height = 65, 2460 }, 2461 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2462 }; 2463 2464 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2465 { /* 60 Hz */ 2466 .clock = 6000, 2467 .hdisplay = 320, 2468 .hsync_start = 320 + 44, 2469 .hsync_end = 320 + 44 + 16, 2470 .htotal = 320 + 44 + 16 + 20, 2471 .vdisplay = 240, 2472 .vsync_start = 240 + 2, 2473 .vsync_end = 240 + 2 + 6, 2474 .vtotal = 240 + 2 + 6 + 2, 2475 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2476 }, 2477 { /* 50 Hz */ 2478 .clock = 5400, 2479 .hdisplay = 320, 2480 .hsync_start = 320 + 56, 2481 .hsync_end = 320 + 56 + 16, 2482 .htotal = 320 + 56 + 16 + 40, 2483 .vdisplay = 240, 2484 .vsync_start = 240 + 2, 2485 .vsync_end = 240 + 2 + 6, 2486 .vtotal = 240 + 2 + 6 + 2, 2487 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2488 }, 2489 }; 2490 2491 static const struct panel_desc frida_frd350h54004 = { 2492 .modes = frida_frd350h54004_modes, 2493 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2494 .bpc = 8, 2495 .size = { 2496 .width = 77, 2497 .height = 64, 2498 }, 2499 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2500 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2501 .connector_type = DRM_MODE_CONNECTOR_DPI, 2502 }; 2503 2504 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2505 .clock = 9000, 2506 .hdisplay = 480, 2507 .hsync_start = 480 + 5, 2508 .hsync_end = 480 + 5 + 1, 2509 .htotal = 480 + 5 + 1 + 40, 2510 .vdisplay = 272, 2511 .vsync_start = 272 + 8, 2512 .vsync_end = 272 + 8 + 1, 2513 .vtotal = 272 + 8 + 1 + 8, 2514 }; 2515 2516 static const struct panel_desc giantplus_gpg482739qs5 = { 2517 .modes = &giantplus_gpg482739qs5_mode, 2518 .num_modes = 1, 2519 .bpc = 8, 2520 .size = { 2521 .width = 95, 2522 .height = 54, 2523 }, 2524 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2525 }; 2526 2527 static const struct display_timing giantplus_gpm940b0_timing = { 2528 .pixelclock = { 13500000, 27000000, 27500000 }, 2529 .hactive = { 320, 320, 320 }, 2530 .hfront_porch = { 14, 686, 718 }, 2531 .hback_porch = { 50, 70, 255 }, 2532 .hsync_len = { 1, 1, 1 }, 2533 .vactive = { 240, 240, 240 }, 2534 .vfront_porch = { 1, 1, 179 }, 2535 .vback_porch = { 1, 21, 31 }, 2536 .vsync_len = { 1, 1, 6 }, 2537 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2538 }; 2539 2540 static const struct panel_desc giantplus_gpm940b0 = { 2541 .timings = &giantplus_gpm940b0_timing, 2542 .num_timings = 1, 2543 .bpc = 8, 2544 .size = { 2545 .width = 60, 2546 .height = 45, 2547 }, 2548 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2549 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2550 }; 2551 2552 static const struct display_timing hannstar_hsd070pww1_timing = { 2553 .pixelclock = { 64300000, 71100000, 82000000 }, 2554 .hactive = { 1280, 1280, 1280 }, 2555 .hfront_porch = { 1, 1, 10 }, 2556 .hback_porch = { 1, 1, 10 }, 2557 /* 2558 * According to the data sheet, the minimum horizontal blanking interval 2559 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2560 * minimum working horizontal blanking interval to be 60 clocks. 2561 */ 2562 .hsync_len = { 58, 158, 661 }, 2563 .vactive = { 800, 800, 800 }, 2564 .vfront_porch = { 1, 1, 10 }, 2565 .vback_porch = { 1, 1, 10 }, 2566 .vsync_len = { 1, 21, 203 }, 2567 .flags = DISPLAY_FLAGS_DE_HIGH, 2568 }; 2569 2570 static const struct panel_desc hannstar_hsd070pww1 = { 2571 .timings = &hannstar_hsd070pww1_timing, 2572 .num_timings = 1, 2573 .bpc = 6, 2574 .size = { 2575 .width = 151, 2576 .height = 94, 2577 }, 2578 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2579 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2580 }; 2581 2582 static const struct display_timing hannstar_hsd100pxn1_timing = { 2583 .pixelclock = { 55000000, 65000000, 75000000 }, 2584 .hactive = { 1024, 1024, 1024 }, 2585 .hfront_porch = { 40, 40, 40 }, 2586 .hback_porch = { 220, 220, 220 }, 2587 .hsync_len = { 20, 60, 100 }, 2588 .vactive = { 768, 768, 768 }, 2589 .vfront_porch = { 7, 7, 7 }, 2590 .vback_porch = { 21, 21, 21 }, 2591 .vsync_len = { 10, 10, 10 }, 2592 .flags = DISPLAY_FLAGS_DE_HIGH, 2593 }; 2594 2595 static const struct panel_desc hannstar_hsd100pxn1 = { 2596 .timings = &hannstar_hsd100pxn1_timing, 2597 .num_timings = 1, 2598 .bpc = 6, 2599 .size = { 2600 .width = 203, 2601 .height = 152, 2602 }, 2603 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2604 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2605 }; 2606 2607 static const struct display_timing hannstar_hsd101pww2_timing = { 2608 .pixelclock = { 64300000, 71100000, 82000000 }, 2609 .hactive = { 1280, 1280, 1280 }, 2610 .hfront_porch = { 1, 1, 10 }, 2611 .hback_porch = { 1, 1, 10 }, 2612 .hsync_len = { 58, 158, 661 }, 2613 .vactive = { 800, 800, 800 }, 2614 .vfront_porch = { 1, 1, 10 }, 2615 .vback_porch = { 1, 1, 10 }, 2616 .vsync_len = { 1, 21, 203 }, 2617 .flags = DISPLAY_FLAGS_DE_HIGH, 2618 }; 2619 2620 static const struct panel_desc hannstar_hsd101pww2 = { 2621 .timings = &hannstar_hsd101pww2_timing, 2622 .num_timings = 1, 2623 .bpc = 8, 2624 .size = { 2625 .width = 217, 2626 .height = 136, 2627 }, 2628 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2629 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2630 }; 2631 2632 static const struct display_timing hannstar_hsd156juw2_timing = { 2633 .pixelclock = { 66000000, 72800000, 80500000 }, 2634 .hactive = { 1920, 1920, 1920 }, 2635 .hfront_porch = { 20, 30, 30 }, 2636 .hback_porch = { 20, 30, 30 }, 2637 .hsync_len = { 50, 60, 90 }, 2638 .vactive = { 1080, 1080, 1080 }, 2639 .vfront_porch = { 1, 2, 4 }, 2640 .vback_porch = { 1, 2, 4 }, 2641 .vsync_len = { 3, 40, 80 }, 2642 .flags = DISPLAY_FLAGS_DE_HIGH, 2643 }; 2644 2645 static const struct panel_desc hannstar_hsd156juw2 = { 2646 .timings = &hannstar_hsd156juw2_timing, 2647 .num_timings = 1, 2648 .bpc = 8, 2649 .size = { 2650 .width = 344, 2651 .height = 194, 2652 }, 2653 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2654 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2655 }; 2656 2657 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2658 .clock = 33333, 2659 .hdisplay = 800, 2660 .hsync_start = 800 + 85, 2661 .hsync_end = 800 + 85 + 86, 2662 .htotal = 800 + 85 + 86 + 85, 2663 .vdisplay = 480, 2664 .vsync_start = 480 + 16, 2665 .vsync_end = 480 + 16 + 13, 2666 .vtotal = 480 + 16 + 13 + 16, 2667 }; 2668 2669 static const struct panel_desc hitachi_tx23d38vm0caa = { 2670 .modes = &hitachi_tx23d38vm0caa_mode, 2671 .num_modes = 1, 2672 .bpc = 6, 2673 .size = { 2674 .width = 195, 2675 .height = 117, 2676 }, 2677 .delay = { 2678 .enable = 160, 2679 .disable = 160, 2680 }, 2681 }; 2682 2683 static const struct drm_display_mode innolux_at043tn24_mode = { 2684 .clock = 9000, 2685 .hdisplay = 480, 2686 .hsync_start = 480 + 2, 2687 .hsync_end = 480 + 2 + 41, 2688 .htotal = 480 + 2 + 41 + 2, 2689 .vdisplay = 272, 2690 .vsync_start = 272 + 2, 2691 .vsync_end = 272 + 2 + 10, 2692 .vtotal = 272 + 2 + 10 + 2, 2693 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2694 }; 2695 2696 static const struct panel_desc innolux_at043tn24 = { 2697 .modes = &innolux_at043tn24_mode, 2698 .num_modes = 1, 2699 .bpc = 8, 2700 .size = { 2701 .width = 95, 2702 .height = 54, 2703 }, 2704 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2705 .connector_type = DRM_MODE_CONNECTOR_DPI, 2706 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2707 }; 2708 2709 static const struct drm_display_mode innolux_at070tn92_mode = { 2710 .clock = 33333, 2711 .hdisplay = 800, 2712 .hsync_start = 800 + 210, 2713 .hsync_end = 800 + 210 + 20, 2714 .htotal = 800 + 210 + 20 + 46, 2715 .vdisplay = 480, 2716 .vsync_start = 480 + 22, 2717 .vsync_end = 480 + 22 + 10, 2718 .vtotal = 480 + 22 + 23 + 10, 2719 }; 2720 2721 static const struct panel_desc innolux_at070tn92 = { 2722 .modes = &innolux_at070tn92_mode, 2723 .num_modes = 1, 2724 .size = { 2725 .width = 154, 2726 .height = 86, 2727 }, 2728 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2729 }; 2730 2731 static const struct display_timing innolux_g070ace_l01_timing = { 2732 .pixelclock = { 25200000, 35000000, 35700000 }, 2733 .hactive = { 800, 800, 800 }, 2734 .hfront_porch = { 30, 32, 87 }, 2735 .hback_porch = { 30, 32, 87 }, 2736 .hsync_len = { 1, 1, 1 }, 2737 .vactive = { 480, 480, 480 }, 2738 .vfront_porch = { 3, 3, 3 }, 2739 .vback_porch = { 13, 13, 13 }, 2740 .vsync_len = { 1, 1, 4 }, 2741 .flags = DISPLAY_FLAGS_DE_HIGH, 2742 }; 2743 2744 static const struct panel_desc innolux_g070ace_l01 = { 2745 .timings = &innolux_g070ace_l01_timing, 2746 .num_timings = 1, 2747 .bpc = 8, 2748 .size = { 2749 .width = 152, 2750 .height = 91, 2751 }, 2752 .delay = { 2753 .prepare = 10, 2754 .enable = 50, 2755 .disable = 50, 2756 .unprepare = 500, 2757 }, 2758 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2759 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2760 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2761 }; 2762 2763 static const struct display_timing innolux_g070y2_l01_timing = { 2764 .pixelclock = { 28000000, 29500000, 32000000 }, 2765 .hactive = { 800, 800, 800 }, 2766 .hfront_porch = { 61, 91, 141 }, 2767 .hback_porch = { 60, 90, 140 }, 2768 .hsync_len = { 12, 12, 12 }, 2769 .vactive = { 480, 480, 480 }, 2770 .vfront_porch = { 4, 9, 30 }, 2771 .vback_porch = { 4, 8, 28 }, 2772 .vsync_len = { 2, 2, 2 }, 2773 .flags = DISPLAY_FLAGS_DE_HIGH, 2774 }; 2775 2776 static const struct panel_desc innolux_g070y2_l01 = { 2777 .timings = &innolux_g070y2_l01_timing, 2778 .num_timings = 1, 2779 .bpc = 8, 2780 .size = { 2781 .width = 152, 2782 .height = 91, 2783 }, 2784 .delay = { 2785 .prepare = 10, 2786 .enable = 100, 2787 .disable = 100, 2788 .unprepare = 800, 2789 }, 2790 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2791 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2792 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2793 }; 2794 2795 static const struct display_timing innolux_g070ace_lh3_timing = { 2796 .pixelclock = { 25200000, 25400000, 35700000 }, 2797 .hactive = { 800, 800, 800 }, 2798 .hfront_porch = { 30, 32, 87 }, 2799 .hback_porch = { 29, 31, 86 }, 2800 .hsync_len = { 1, 1, 1 }, 2801 .vactive = { 480, 480, 480 }, 2802 .vfront_porch = { 4, 5, 65 }, 2803 .vback_porch = { 3, 4, 65 }, 2804 .vsync_len = { 1, 1, 1 }, 2805 .flags = DISPLAY_FLAGS_DE_HIGH, 2806 }; 2807 2808 static const struct panel_desc innolux_g070ace_lh3 = { 2809 .timings = &innolux_g070ace_lh3_timing, 2810 .num_timings = 1, 2811 .bpc = 8, 2812 .size = { 2813 .width = 152, 2814 .height = 91, 2815 }, 2816 .delay = { 2817 .prepare = 10, 2818 .enable = 450, 2819 .disable = 200, 2820 .unprepare = 510, 2821 }, 2822 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2823 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2824 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2825 }; 2826 2827 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2828 .clock = 33333, 2829 .hdisplay = 800, 2830 .hsync_start = 800 + 210, 2831 .hsync_end = 800 + 210 + 20, 2832 .htotal = 800 + 210 + 20 + 46, 2833 .vdisplay = 480, 2834 .vsync_start = 480 + 22, 2835 .vsync_end = 480 + 22 + 10, 2836 .vtotal = 480 + 22 + 23 + 10, 2837 }; 2838 2839 static const struct panel_desc innolux_g070y2_t02 = { 2840 .modes = &innolux_g070y2_t02_mode, 2841 .num_modes = 1, 2842 .bpc = 8, 2843 .size = { 2844 .width = 152, 2845 .height = 92, 2846 }, 2847 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2848 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2849 .connector_type = DRM_MODE_CONNECTOR_DPI, 2850 }; 2851 2852 static const struct display_timing innolux_g101ice_l01_timing = { 2853 .pixelclock = { 60400000, 71100000, 74700000 }, 2854 .hactive = { 1280, 1280, 1280 }, 2855 .hfront_porch = { 30, 60, 70 }, 2856 .hback_porch = { 30, 60, 70 }, 2857 .hsync_len = { 22, 40, 60 }, 2858 .vactive = { 800, 800, 800 }, 2859 .vfront_porch = { 3, 8, 14 }, 2860 .vback_porch = { 3, 8, 14 }, 2861 .vsync_len = { 4, 7, 12 }, 2862 .flags = DISPLAY_FLAGS_DE_HIGH, 2863 }; 2864 2865 static const struct panel_desc innolux_g101ice_l01 = { 2866 .timings = &innolux_g101ice_l01_timing, 2867 .num_timings = 1, 2868 .bpc = 8, 2869 .size = { 2870 .width = 217, 2871 .height = 135, 2872 }, 2873 .delay = { 2874 .enable = 200, 2875 .disable = 200, 2876 }, 2877 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2878 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2879 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2880 }; 2881 2882 static const struct display_timing innolux_g121i1_l01_timing = { 2883 .pixelclock = { 67450000, 71000000, 74550000 }, 2884 .hactive = { 1280, 1280, 1280 }, 2885 .hfront_porch = { 40, 80, 160 }, 2886 .hback_porch = { 39, 79, 159 }, 2887 .hsync_len = { 1, 1, 1 }, 2888 .vactive = { 800, 800, 800 }, 2889 .vfront_porch = { 5, 11, 100 }, 2890 .vback_porch = { 4, 11, 99 }, 2891 .vsync_len = { 1, 1, 1 }, 2892 }; 2893 2894 static const struct panel_desc innolux_g121i1_l01 = { 2895 .timings = &innolux_g121i1_l01_timing, 2896 .num_timings = 1, 2897 .bpc = 6, 2898 .size = { 2899 .width = 261, 2900 .height = 163, 2901 }, 2902 .delay = { 2903 .enable = 200, 2904 .disable = 20, 2905 }, 2906 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2907 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2908 }; 2909 2910 static const struct display_timing innolux_g121x1_l03_timings = { 2911 .pixelclock = { 57500000, 64900000, 74400000 }, 2912 .hactive = { 1024, 1024, 1024 }, 2913 .hfront_porch = { 90, 140, 190 }, 2914 .hback_porch = { 90, 140, 190 }, 2915 .hsync_len = { 36, 40, 60 }, 2916 .vactive = { 768, 768, 768 }, 2917 .vfront_porch = { 2, 15, 30 }, 2918 .vback_porch = { 2, 15, 30 }, 2919 .vsync_len = { 2, 8, 20 }, 2920 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2921 }; 2922 2923 static const struct panel_desc innolux_g121x1_l03 = { 2924 .timings = &innolux_g121x1_l03_timings, 2925 .num_timings = 1, 2926 .bpc = 6, 2927 .size = { 2928 .width = 246, 2929 .height = 185, 2930 }, 2931 .delay = { 2932 .enable = 200, 2933 .unprepare = 200, 2934 .disable = 400, 2935 }, 2936 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2937 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2938 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2939 }; 2940 2941 static const struct panel_desc innolux_g121xce_l01 = { 2942 .timings = &innolux_g121x1_l03_timings, 2943 .num_timings = 1, 2944 .bpc = 8, 2945 .size = { 2946 .width = 246, 2947 .height = 185, 2948 }, 2949 .delay = { 2950 .enable = 200, 2951 .unprepare = 200, 2952 .disable = 400, 2953 }, 2954 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2955 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2956 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2957 }; 2958 2959 static const struct display_timing innolux_g150xge_l05_timing = { 2960 .pixelclock = { 53350000, 65000000, 80000000 }, 2961 .hactive = { 1024, 1024, 1024 }, 2962 .hfront_porch = { 58, 160, 288 }, 2963 .hback_porch = { 58, 160, 288 }, 2964 .hsync_len = { 1, 1, 1 }, 2965 .vactive = { 768, 768, 768 }, 2966 .vfront_porch = { 6, 19, 216 }, 2967 .vback_porch = { 6, 19, 216 }, 2968 .vsync_len = { 1, 1, 1 }, 2969 .flags = DISPLAY_FLAGS_DE_HIGH, 2970 }; 2971 2972 static const struct panel_desc innolux_g150xge_l05 = { 2973 .timings = &innolux_g150xge_l05_timing, 2974 .num_timings = 1, 2975 .bpc = 8, 2976 .size = { 2977 .width = 304, 2978 .height = 228, 2979 }, 2980 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2981 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2982 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2983 }; 2984 2985 static const struct display_timing innolux_g156hce_l01_timings = { 2986 .pixelclock = { 120000000, 141860000, 150000000 }, 2987 .hactive = { 1920, 1920, 1920 }, 2988 .hfront_porch = { 80, 90, 100 }, 2989 .hback_porch = { 80, 90, 100 }, 2990 .hsync_len = { 20, 30, 30 }, 2991 .vactive = { 1080, 1080, 1080 }, 2992 .vfront_porch = { 3, 10, 20 }, 2993 .vback_porch = { 3, 10, 20 }, 2994 .vsync_len = { 4, 10, 10 }, 2995 }; 2996 2997 static const struct panel_desc innolux_g156hce_l01 = { 2998 .timings = &innolux_g156hce_l01_timings, 2999 .num_timings = 1, 3000 .bpc = 8, 3001 .size = { 3002 .width = 344, 3003 .height = 194, 3004 }, 3005 .delay = { 3006 .prepare = 1, /* T1+T2 */ 3007 .enable = 450, /* T5 */ 3008 .disable = 200, /* T6 */ 3009 .unprepare = 10, /* T3+T7 */ 3010 }, 3011 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3012 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3013 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3014 }; 3015 3016 static const struct drm_display_mode innolux_n156bge_l21_mode = { 3017 .clock = 69300, 3018 .hdisplay = 1366, 3019 .hsync_start = 1366 + 16, 3020 .hsync_end = 1366 + 16 + 34, 3021 .htotal = 1366 + 16 + 34 + 50, 3022 .vdisplay = 768, 3023 .vsync_start = 768 + 2, 3024 .vsync_end = 768 + 2 + 6, 3025 .vtotal = 768 + 2 + 6 + 12, 3026 }; 3027 3028 static const struct panel_desc innolux_n156bge_l21 = { 3029 .modes = &innolux_n156bge_l21_mode, 3030 .num_modes = 1, 3031 .bpc = 6, 3032 .size = { 3033 .width = 344, 3034 .height = 193, 3035 }, 3036 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3037 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3038 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3039 }; 3040 3041 static const struct drm_display_mode innolux_zj070na_01p_mode = { 3042 .clock = 51501, 3043 .hdisplay = 1024, 3044 .hsync_start = 1024 + 128, 3045 .hsync_end = 1024 + 128 + 64, 3046 .htotal = 1024 + 128 + 64 + 128, 3047 .vdisplay = 600, 3048 .vsync_start = 600 + 16, 3049 .vsync_end = 600 + 16 + 4, 3050 .vtotal = 600 + 16 + 4 + 16, 3051 }; 3052 3053 static const struct panel_desc innolux_zj070na_01p = { 3054 .modes = &innolux_zj070na_01p_mode, 3055 .num_modes = 1, 3056 .bpc = 6, 3057 .size = { 3058 .width = 154, 3059 .height = 90, 3060 }, 3061 }; 3062 3063 static const struct display_timing jutouch_jt070tm041_timing = { 3064 .pixelclock = { 40800000, 51200000, 67200000 }, 3065 .hactive = { 1024, 1024, 1024 }, 3066 .hfront_porch = { 16, 160, 216 }, 3067 .hback_porch = { 160, 160, 160 }, 3068 .hsync_len = { 1, 1, 140 }, 3069 .vactive = { 600, 600, 600 }, 3070 .vfront_porch = { 1, 12, 127 }, 3071 .vback_porch = { 23, 23, 23 }, 3072 .vsync_len = { 1, 1, 20 }, 3073 }; 3074 3075 static const struct panel_desc jutouch_jt070tm041 = { 3076 .timings = &jutouch_jt070tm041_timing, 3077 .num_timings = 1, 3078 .bpc = 8, 3079 .size = { 3080 .width = 154, 3081 .height = 86, 3082 }, 3083 .delay = { 3084 .enable = 50, 3085 .disable = 50, 3086 }, 3087 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3088 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3089 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3090 }; 3091 3092 static const struct display_timing jutouch_jt101tm023_timing = { 3093 .pixelclock = { 66300000, 72400000, 78900000 }, 3094 .hactive = { 1280, 1280, 1280 }, 3095 .hfront_porch = { 12, 72, 132 }, 3096 .hback_porch = { 88, 88, 88 }, 3097 .hsync_len = { 10, 10, 48 }, 3098 .vactive = { 800, 800, 800 }, 3099 .vfront_porch = { 1, 15, 49 }, 3100 .vback_porch = { 23, 23, 23 }, 3101 .vsync_len = { 5, 6, 13 }, 3102 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3103 DISPLAY_FLAGS_DE_HIGH, 3104 }; 3105 3106 static const struct panel_desc jutouch_jt101tm023 = { 3107 .timings = &jutouch_jt101tm023_timing, 3108 .num_timings = 1, 3109 .bpc = 8, 3110 .size = { 3111 .width = 217, 3112 .height = 136, 3113 }, 3114 .delay = { 3115 .enable = 50, 3116 .disable = 50, 3117 }, 3118 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3119 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3120 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3121 }; 3122 3123 3124 static const struct display_timing koe_tx14d24vm1bpa_timing = { 3125 .pixelclock = { 5580000, 5850000, 6200000 }, 3126 .hactive = { 320, 320, 320 }, 3127 .hfront_porch = { 30, 30, 30 }, 3128 .hback_porch = { 30, 30, 30 }, 3129 .hsync_len = { 1, 5, 17 }, 3130 .vactive = { 240, 240, 240 }, 3131 .vfront_porch = { 6, 6, 6 }, 3132 .vback_porch = { 5, 5, 5 }, 3133 .vsync_len = { 1, 2, 11 }, 3134 .flags = DISPLAY_FLAGS_DE_HIGH, 3135 }; 3136 3137 static const struct panel_desc koe_tx14d24vm1bpa = { 3138 .timings = &koe_tx14d24vm1bpa_timing, 3139 .num_timings = 1, 3140 .bpc = 6, 3141 .size = { 3142 .width = 115, 3143 .height = 86, 3144 }, 3145 }; 3146 3147 static const struct display_timing koe_tx26d202vm0bwa_timing = { 3148 .pixelclock = { 151820000, 156720000, 159780000 }, 3149 .hactive = { 1920, 1920, 1920 }, 3150 .hfront_porch = { 105, 130, 142 }, 3151 .hback_porch = { 45, 70, 82 }, 3152 .hsync_len = { 30, 30, 30 }, 3153 .vactive = { 1200, 1200, 1200}, 3154 .vfront_porch = { 3, 5, 10 }, 3155 .vback_porch = { 2, 5, 10 }, 3156 .vsync_len = { 5, 5, 5 }, 3157 .flags = DISPLAY_FLAGS_DE_HIGH, 3158 }; 3159 3160 static const struct panel_desc koe_tx26d202vm0bwa = { 3161 .timings = &koe_tx26d202vm0bwa_timing, 3162 .num_timings = 1, 3163 .bpc = 8, 3164 .size = { 3165 .width = 217, 3166 .height = 136, 3167 }, 3168 .delay = { 3169 .prepare = 1000, 3170 .enable = 1000, 3171 .unprepare = 1000, 3172 .disable = 1000, 3173 }, 3174 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3175 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3176 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3177 }; 3178 3179 static const struct display_timing koe_tx31d200vm0baa_timing = { 3180 .pixelclock = { 39600000, 43200000, 48000000 }, 3181 .hactive = { 1280, 1280, 1280 }, 3182 .hfront_porch = { 16, 36, 56 }, 3183 .hback_porch = { 16, 36, 56 }, 3184 .hsync_len = { 8, 8, 8 }, 3185 .vactive = { 480, 480, 480 }, 3186 .vfront_porch = { 6, 21, 33 }, 3187 .vback_porch = { 6, 21, 33 }, 3188 .vsync_len = { 8, 8, 8 }, 3189 .flags = DISPLAY_FLAGS_DE_HIGH, 3190 }; 3191 3192 static const struct panel_desc koe_tx31d200vm0baa = { 3193 .timings = &koe_tx31d200vm0baa_timing, 3194 .num_timings = 1, 3195 .bpc = 6, 3196 .size = { 3197 .width = 292, 3198 .height = 109, 3199 }, 3200 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3201 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3202 }; 3203 3204 static const struct display_timing kyo_tcg121xglp_timing = { 3205 .pixelclock = { 52000000, 65000000, 71000000 }, 3206 .hactive = { 1024, 1024, 1024 }, 3207 .hfront_porch = { 2, 2, 2 }, 3208 .hback_porch = { 2, 2, 2 }, 3209 .hsync_len = { 86, 124, 244 }, 3210 .vactive = { 768, 768, 768 }, 3211 .vfront_porch = { 2, 2, 2 }, 3212 .vback_porch = { 2, 2, 2 }, 3213 .vsync_len = { 6, 34, 73 }, 3214 .flags = DISPLAY_FLAGS_DE_HIGH, 3215 }; 3216 3217 static const struct panel_desc kyo_tcg121xglp = { 3218 .timings = &kyo_tcg121xglp_timing, 3219 .num_timings = 1, 3220 .bpc = 8, 3221 .size = { 3222 .width = 246, 3223 .height = 184, 3224 }, 3225 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3226 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3227 }; 3228 3229 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 3230 .clock = 7000, 3231 .hdisplay = 320, 3232 .hsync_start = 320 + 20, 3233 .hsync_end = 320 + 20 + 30, 3234 .htotal = 320 + 20 + 30 + 38, 3235 .vdisplay = 240, 3236 .vsync_start = 240 + 4, 3237 .vsync_end = 240 + 4 + 3, 3238 .vtotal = 240 + 4 + 3 + 15, 3239 }; 3240 3241 static const struct panel_desc lemaker_bl035_rgb_002 = { 3242 .modes = &lemaker_bl035_rgb_002_mode, 3243 .num_modes = 1, 3244 .size = { 3245 .width = 70, 3246 .height = 52, 3247 }, 3248 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3249 .bus_flags = DRM_BUS_FLAG_DE_LOW, 3250 }; 3251 3252 static const struct display_timing lg_lb070wv8_timing = { 3253 .pixelclock = { 31950000, 33260000, 34600000 }, 3254 .hactive = { 800, 800, 800 }, 3255 .hfront_porch = { 88, 88, 88 }, 3256 .hback_porch = { 88, 88, 88 }, 3257 .hsync_len = { 80, 80, 80 }, 3258 .vactive = { 480, 480, 480 }, 3259 .vfront_porch = { 10, 10, 10 }, 3260 .vback_porch = { 10, 10, 10 }, 3261 .vsync_len = { 25, 25, 25 }, 3262 }; 3263 3264 static const struct panel_desc lg_lb070wv8 = { 3265 .timings = &lg_lb070wv8_timing, 3266 .num_timings = 1, 3267 .bpc = 8, 3268 .size = { 3269 .width = 151, 3270 .height = 91, 3271 }, 3272 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3273 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3274 }; 3275 3276 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 3277 .clock = 155127, 3278 .hdisplay = 1920, 3279 .hsync_start = 1920 + 128, 3280 .hsync_end = 1920 + 128 + 20, 3281 .htotal = 1920 + 128 + 20 + 12, 3282 .vdisplay = 1200, 3283 .vsync_start = 1200 + 19, 3284 .vsync_end = 1200 + 19 + 4, 3285 .vtotal = 1200 + 19 + 4 + 20, 3286 }; 3287 3288 static const struct panel_desc lincolntech_lcd185_101ct = { 3289 .modes = &lincolntech_lcd185_101ct_mode, 3290 .bpc = 8, 3291 .num_modes = 1, 3292 .size = { 3293 .width = 217, 3294 .height = 136, 3295 }, 3296 .delay = { 3297 .prepare = 50, 3298 .disable = 50, 3299 }, 3300 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3301 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3302 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3303 }; 3304 3305 static const struct display_timing logictechno_lt161010_2nh_timing = { 3306 .pixelclock = { 26400000, 33300000, 46800000 }, 3307 .hactive = { 800, 800, 800 }, 3308 .hfront_porch = { 16, 210, 354 }, 3309 .hback_porch = { 46, 46, 46 }, 3310 .hsync_len = { 1, 20, 40 }, 3311 .vactive = { 480, 480, 480 }, 3312 .vfront_porch = { 7, 22, 147 }, 3313 .vback_porch = { 23, 23, 23 }, 3314 .vsync_len = { 1, 10, 20 }, 3315 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3316 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3317 DISPLAY_FLAGS_SYNC_POSEDGE, 3318 }; 3319 3320 static const struct panel_desc logictechno_lt161010_2nh = { 3321 .timings = &logictechno_lt161010_2nh_timing, 3322 .num_timings = 1, 3323 .bpc = 6, 3324 .size = { 3325 .width = 154, 3326 .height = 86, 3327 }, 3328 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3329 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3330 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3331 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3332 .connector_type = DRM_MODE_CONNECTOR_DPI, 3333 }; 3334 3335 static const struct display_timing logictechno_lt170410_2whc_timing = { 3336 .pixelclock = { 68900000, 71100000, 73400000 }, 3337 .hactive = { 1280, 1280, 1280 }, 3338 .hfront_porch = { 23, 60, 71 }, 3339 .hback_porch = { 23, 60, 71 }, 3340 .hsync_len = { 15, 40, 47 }, 3341 .vactive = { 800, 800, 800 }, 3342 .vfront_porch = { 5, 7, 10 }, 3343 .vback_porch = { 5, 7, 10 }, 3344 .vsync_len = { 6, 9, 12 }, 3345 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3346 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3347 DISPLAY_FLAGS_SYNC_POSEDGE, 3348 }; 3349 3350 static const struct panel_desc logictechno_lt170410_2whc = { 3351 .timings = &logictechno_lt170410_2whc_timing, 3352 .num_timings = 1, 3353 .bpc = 8, 3354 .size = { 3355 .width = 217, 3356 .height = 136, 3357 }, 3358 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3359 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3360 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3361 }; 3362 3363 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3364 .clock = 33000, 3365 .hdisplay = 800, 3366 .hsync_start = 800 + 112, 3367 .hsync_end = 800 + 112 + 3, 3368 .htotal = 800 + 112 + 3 + 85, 3369 .vdisplay = 480, 3370 .vsync_start = 480 + 38, 3371 .vsync_end = 480 + 38 + 3, 3372 .vtotal = 480 + 38 + 3 + 29, 3373 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3374 }; 3375 3376 static const struct panel_desc logictechno_lttd800480070_l2rt = { 3377 .modes = &logictechno_lttd800480070_l2rt_mode, 3378 .num_modes = 1, 3379 .bpc = 8, 3380 .size = { 3381 .width = 154, 3382 .height = 86, 3383 }, 3384 .delay = { 3385 .prepare = 45, 3386 .enable = 100, 3387 .disable = 100, 3388 .unprepare = 45 3389 }, 3390 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3391 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3392 .connector_type = DRM_MODE_CONNECTOR_DPI, 3393 }; 3394 3395 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3396 .clock = 33000, 3397 .hdisplay = 800, 3398 .hsync_start = 800 + 154, 3399 .hsync_end = 800 + 154 + 3, 3400 .htotal = 800 + 154 + 3 + 43, 3401 .vdisplay = 480, 3402 .vsync_start = 480 + 47, 3403 .vsync_end = 480 + 47 + 3, 3404 .vtotal = 480 + 47 + 3 + 20, 3405 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3406 }; 3407 3408 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3409 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3410 .num_modes = 1, 3411 .bpc = 8, 3412 .size = { 3413 .width = 154, 3414 .height = 86, 3415 }, 3416 .delay = { 3417 .prepare = 45, 3418 .enable = 100, 3419 .disable = 100, 3420 .unprepare = 45 3421 }, 3422 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3423 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3424 .connector_type = DRM_MODE_CONNECTOR_DPI, 3425 }; 3426 3427 static const struct drm_display_mode logicpd_type_28_mode = { 3428 .clock = 9107, 3429 .hdisplay = 480, 3430 .hsync_start = 480 + 3, 3431 .hsync_end = 480 + 3 + 42, 3432 .htotal = 480 + 3 + 42 + 2, 3433 3434 .vdisplay = 272, 3435 .vsync_start = 272 + 2, 3436 .vsync_end = 272 + 2 + 11, 3437 .vtotal = 272 + 2 + 11 + 3, 3438 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3439 }; 3440 3441 static const struct panel_desc logicpd_type_28 = { 3442 .modes = &logicpd_type_28_mode, 3443 .num_modes = 1, 3444 .bpc = 8, 3445 .size = { 3446 .width = 105, 3447 .height = 67, 3448 }, 3449 .delay = { 3450 .prepare = 200, 3451 .enable = 200, 3452 .unprepare = 200, 3453 .disable = 200, 3454 }, 3455 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3456 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3457 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3458 .connector_type = DRM_MODE_CONNECTOR_DPI, 3459 }; 3460 3461 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3462 .clock = 150275, 3463 .hdisplay = 1920, 3464 .hsync_start = 1920 + 32, 3465 .hsync_end = 1920 + 32 + 52, 3466 .htotal = 1920 + 32 + 52 + 24, 3467 .vdisplay = 1200, 3468 .vsync_start = 1200 + 24, 3469 .vsync_end = 1200 + 24 + 8, 3470 .vtotal = 1200 + 24 + 8 + 3, 3471 }; 3472 3473 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3474 .modes = µtips_mf_101hiebcaf0_c_mode, 3475 .bpc = 8, 3476 .num_modes = 1, 3477 .size = { 3478 .width = 217, 3479 .height = 136, 3480 }, 3481 .delay = { 3482 .prepare = 50, 3483 .disable = 50, 3484 }, 3485 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3486 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3487 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3488 }; 3489 3490 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3491 .clock = 93301, 3492 .hdisplay = 1920, 3493 .hsync_start = 1920 + 72, 3494 .hsync_end = 1920 + 72 + 72, 3495 .htotal = 1920 + 72 + 72 + 72, 3496 .vdisplay = 720, 3497 .vsync_start = 720 + 3, 3498 .vsync_end = 720 + 3 + 3, 3499 .vtotal = 720 + 3 + 3 + 2, 3500 }; 3501 3502 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3503 .modes = µtips_mf_103hieb0ga0_mode, 3504 .bpc = 8, 3505 .num_modes = 1, 3506 .size = { 3507 .width = 244, 3508 .height = 92, 3509 }, 3510 .delay = { 3511 .prepare = 50, 3512 .disable = 50, 3513 }, 3514 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3515 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3516 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3517 }; 3518 3519 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3520 .clock = 30400, 3521 .hdisplay = 800, 3522 .hsync_start = 800 + 0, 3523 .hsync_end = 800 + 1, 3524 .htotal = 800 + 0 + 1 + 160, 3525 .vdisplay = 480, 3526 .vsync_start = 480 + 0, 3527 .vsync_end = 480 + 48 + 1, 3528 .vtotal = 480 + 48 + 1 + 0, 3529 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3530 }; 3531 3532 static const struct panel_desc mitsubishi_aa070mc01 = { 3533 .modes = &mitsubishi_aa070mc01_mode, 3534 .num_modes = 1, 3535 .bpc = 8, 3536 .size = { 3537 .width = 152, 3538 .height = 91, 3539 }, 3540 3541 .delay = { 3542 .enable = 200, 3543 .unprepare = 200, 3544 .disable = 400, 3545 }, 3546 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3547 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3548 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3549 }; 3550 3551 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3552 .clock = 56234, 3553 .hdisplay = 1024, 3554 .hsync_start = 1024 + 24, 3555 .hsync_end = 1024 + 24 + 63, 3556 .htotal = 1024 + 24 + 63 + 1, 3557 .vdisplay = 768, 3558 .vsync_start = 768 + 3, 3559 .vsync_end = 768 + 3 + 6, 3560 .vtotal = 768 + 3 + 6 + 1, 3561 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3562 }; 3563 3564 static const struct panel_desc mitsubishi_aa084xe01 = { 3565 .modes = &mitsubishi_aa084xe01_mode, 3566 .num_modes = 1, 3567 .bpc = 8, 3568 .size = { 3569 .width = 1024, 3570 .height = 768, 3571 }, 3572 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3573 .connector_type = DRM_MODE_CONNECTOR_DPI, 3574 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3575 }; 3576 3577 static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3578 .pixelclock = { 26400000, 33000000, 46800000 }, 3579 .hactive = { 800, 800, 800 }, 3580 .hfront_porch = { 16, 204, 354 }, 3581 .hback_porch = { 46, 46, 46 }, 3582 .hsync_len = { 1, 6, 40 }, 3583 .vactive = { 480, 480, 480 }, 3584 .vfront_porch = { 7, 22, 147 }, 3585 .vback_porch = { 23, 23, 23 }, 3586 .vsync_len = { 1, 3, 20 }, 3587 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3588 DISPLAY_FLAGS_DE_HIGH, 3589 }; 3590 3591 static const struct panel_desc multi_inno_mi0700a2t_30 = { 3592 .timings = &multi_inno_mi0700a2t_30_timing, 3593 .num_timings = 1, 3594 .bpc = 6, 3595 .size = { 3596 .width = 153, 3597 .height = 92, 3598 }, 3599 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3600 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3601 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3602 }; 3603 3604 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3605 .pixelclock = { 29000000, 33000000, 38000000 }, 3606 .hactive = { 800, 800, 800 }, 3607 .hfront_porch = { 180, 210, 240 }, 3608 .hback_porch = { 16, 16, 16 }, 3609 .hsync_len = { 30, 30, 30 }, 3610 .vactive = { 480, 480, 480 }, 3611 .vfront_porch = { 12, 22, 32 }, 3612 .vback_porch = { 10, 10, 10 }, 3613 .vsync_len = { 13, 13, 13 }, 3614 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3615 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3616 DISPLAY_FLAGS_SYNC_POSEDGE, 3617 }; 3618 3619 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3620 .timings = &multi_inno_mi0700s4t_6_timing, 3621 .num_timings = 1, 3622 .bpc = 8, 3623 .size = { 3624 .width = 154, 3625 .height = 86, 3626 }, 3627 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3628 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3629 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3630 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3631 .connector_type = DRM_MODE_CONNECTOR_DPI, 3632 }; 3633 3634 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3635 .pixelclock = { 32000000, 40000000, 50000000 }, 3636 .hactive = { 800, 800, 800 }, 3637 .hfront_porch = { 16, 210, 354 }, 3638 .hback_porch = { 6, 26, 45 }, 3639 .hsync_len = { 1, 20, 40 }, 3640 .vactive = { 600, 600, 600 }, 3641 .vfront_porch = { 1, 12, 77 }, 3642 .vback_porch = { 3, 13, 22 }, 3643 .vsync_len = { 1, 10, 20 }, 3644 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3645 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3646 DISPLAY_FLAGS_SYNC_POSEDGE, 3647 }; 3648 3649 static const struct panel_desc multi_inno_mi0800ft_9 = { 3650 .timings = &multi_inno_mi0800ft_9_timing, 3651 .num_timings = 1, 3652 .bpc = 8, 3653 .size = { 3654 .width = 162, 3655 .height = 122, 3656 }, 3657 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3658 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3659 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3660 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3661 .connector_type = DRM_MODE_CONNECTOR_DPI, 3662 }; 3663 3664 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3665 .pixelclock = { 68900000, 70000000, 73400000 }, 3666 .hactive = { 1280, 1280, 1280 }, 3667 .hfront_porch = { 30, 60, 71 }, 3668 .hback_porch = { 30, 60, 71 }, 3669 .hsync_len = { 10, 10, 48 }, 3670 .vactive = { 800, 800, 800 }, 3671 .vfront_porch = { 5, 10, 10 }, 3672 .vback_porch = { 5, 10, 10 }, 3673 .vsync_len = { 5, 6, 13 }, 3674 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3675 DISPLAY_FLAGS_DE_HIGH, 3676 }; 3677 3678 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3679 .timings = &multi_inno_mi1010ait_1cp_timing, 3680 .num_timings = 1, 3681 .bpc = 8, 3682 .size = { 3683 .width = 217, 3684 .height = 136, 3685 }, 3686 .delay = { 3687 .enable = 50, 3688 .disable = 50, 3689 }, 3690 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3691 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3692 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3693 }; 3694 3695 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3696 .pixelclock = { 40800000, 51200000, 67200000 }, 3697 .hactive = { 1024, 1024, 1024 }, 3698 .hfront_porch = { 30, 110, 130 }, 3699 .hback_porch = { 30, 110, 130 }, 3700 .hsync_len = { 30, 100, 116 }, 3701 .vactive = { 600, 600, 600 }, 3702 .vfront_porch = { 4, 13, 80 }, 3703 .vback_porch = { 4, 13, 80 }, 3704 .vsync_len = { 2, 9, 40 }, 3705 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3706 DISPLAY_FLAGS_DE_HIGH, 3707 }; 3708 3709 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3710 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3711 .num_timings = 1, 3712 .bpc = 6, 3713 .size = { 3714 .width = 260, 3715 .height = 162, 3716 }, 3717 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3718 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3719 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3720 }; 3721 3722 static const struct display_timing nec_nl12880bc20_05_timing = { 3723 .pixelclock = { 67000000, 71000000, 75000000 }, 3724 .hactive = { 1280, 1280, 1280 }, 3725 .hfront_porch = { 2, 30, 30 }, 3726 .hback_porch = { 6, 100, 100 }, 3727 .hsync_len = { 2, 30, 30 }, 3728 .vactive = { 800, 800, 800 }, 3729 .vfront_porch = { 5, 5, 5 }, 3730 .vback_porch = { 11, 11, 11 }, 3731 .vsync_len = { 7, 7, 7 }, 3732 }; 3733 3734 static const struct panel_desc nec_nl12880bc20_05 = { 3735 .timings = &nec_nl12880bc20_05_timing, 3736 .num_timings = 1, 3737 .bpc = 8, 3738 .size = { 3739 .width = 261, 3740 .height = 163, 3741 }, 3742 .delay = { 3743 .enable = 50, 3744 .disable = 50, 3745 }, 3746 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3747 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3748 }; 3749 3750 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3751 .clock = 10870, 3752 .hdisplay = 480, 3753 .hsync_start = 480 + 2, 3754 .hsync_end = 480 + 2 + 41, 3755 .htotal = 480 + 2 + 41 + 2, 3756 .vdisplay = 272, 3757 .vsync_start = 272 + 2, 3758 .vsync_end = 272 + 2 + 4, 3759 .vtotal = 272 + 2 + 4 + 2, 3760 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3761 }; 3762 3763 static const struct panel_desc nec_nl4827hc19_05b = { 3764 .modes = &nec_nl4827hc19_05b_mode, 3765 .num_modes = 1, 3766 .bpc = 8, 3767 .size = { 3768 .width = 95, 3769 .height = 54, 3770 }, 3771 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3772 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3773 }; 3774 3775 static const struct drm_display_mode nec_nl6448bc33_70c_mode = { 3776 .clock = 25175, 3777 .hdisplay = 640, 3778 .hsync_start = 640 + 16, 3779 .hsync_end = 640 + 16 + 48, 3780 .htotal = 640 + 16 + 48 + 96, 3781 .vdisplay = 480, 3782 .vsync_start = 480 + 2, 3783 .vsync_end = 480 + 2 + 31, 3784 .vtotal = 480 + 2 + 31 + 31, 3785 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 3786 }; 3787 3788 static const struct panel_desc nec_nl6448bc33_70c = { 3789 .modes = &nec_nl6448bc33_70c_mode, 3790 .num_modes = 1, 3791 .bpc = 6, 3792 .size = { 3793 .width = 211, 3794 .height = 158, 3795 }, 3796 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3797 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3798 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3799 }; 3800 3801 static const struct drm_display_mode netron_dy_e231732_mode = { 3802 .clock = 66000, 3803 .hdisplay = 1024, 3804 .hsync_start = 1024 + 160, 3805 .hsync_end = 1024 + 160 + 70, 3806 .htotal = 1024 + 160 + 70 + 90, 3807 .vdisplay = 600, 3808 .vsync_start = 600 + 127, 3809 .vsync_end = 600 + 127 + 20, 3810 .vtotal = 600 + 127 + 20 + 3, 3811 }; 3812 3813 static const struct panel_desc netron_dy_e231732 = { 3814 .modes = &netron_dy_e231732_mode, 3815 .num_modes = 1, 3816 .size = { 3817 .width = 154, 3818 .height = 87, 3819 }, 3820 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3821 }; 3822 3823 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3824 .clock = 9000, 3825 .hdisplay = 480, 3826 .hsync_start = 480 + 2, 3827 .hsync_end = 480 + 2 + 41, 3828 .htotal = 480 + 2 + 41 + 2, 3829 .vdisplay = 272, 3830 .vsync_start = 272 + 2, 3831 .vsync_end = 272 + 2 + 10, 3832 .vtotal = 272 + 2 + 10 + 2, 3833 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3834 }; 3835 3836 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3837 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3838 .num_modes = 1, 3839 .bpc = 8, 3840 .size = { 3841 .width = 95, 3842 .height = 54, 3843 }, 3844 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3845 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3846 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3847 .connector_type = DRM_MODE_CONNECTOR_DPI, 3848 }; 3849 3850 static const struct drm_display_mode nlt_nl13676bc25_03f_mode = { 3851 .clock = 75400, 3852 .hdisplay = 1366, 3853 .hsync_start = 1366 + 14, 3854 .hsync_end = 1366 + 14 + 56, 3855 .htotal = 1366 + 14 + 56 + 64, 3856 .vdisplay = 768, 3857 .vsync_start = 768 + 1, 3858 .vsync_end = 768 + 1 + 3, 3859 .vtotal = 768 + 1 + 3 + 22, 3860 }; 3861 3862 static const struct panel_desc nlt_nl13676bc25_03f = { 3863 .modes = &nlt_nl13676bc25_03f_mode, 3864 .num_modes = 1, 3865 .bpc = 8, 3866 .size = { 3867 .width = 363, 3868 .height = 215, 3869 }, 3870 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3871 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3872 }; 3873 3874 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3875 .pixelclock = { 130000000, 148350000, 163000000 }, 3876 .hactive = { 1920, 1920, 1920 }, 3877 .hfront_porch = { 80, 100, 100 }, 3878 .hback_porch = { 100, 120, 120 }, 3879 .hsync_len = { 50, 60, 60 }, 3880 .vactive = { 1080, 1080, 1080 }, 3881 .vfront_porch = { 12, 30, 30 }, 3882 .vback_porch = { 4, 10, 10 }, 3883 .vsync_len = { 4, 5, 5 }, 3884 }; 3885 3886 static const struct panel_desc nlt_nl192108ac18_02d = { 3887 .timings = &nlt_nl192108ac18_02d_timing, 3888 .num_timings = 1, 3889 .bpc = 8, 3890 .size = { 3891 .width = 344, 3892 .height = 194, 3893 }, 3894 .delay = { 3895 .unprepare = 500, 3896 }, 3897 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3898 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3899 }; 3900 3901 static const struct drm_display_mode nvd_9128_mode = { 3902 .clock = 29500, 3903 .hdisplay = 800, 3904 .hsync_start = 800 + 130, 3905 .hsync_end = 800 + 130 + 98, 3906 .htotal = 800 + 0 + 130 + 98, 3907 .vdisplay = 480, 3908 .vsync_start = 480 + 10, 3909 .vsync_end = 480 + 10 + 50, 3910 .vtotal = 480 + 0 + 10 + 50, 3911 }; 3912 3913 static const struct panel_desc nvd_9128 = { 3914 .modes = &nvd_9128_mode, 3915 .num_modes = 1, 3916 .bpc = 8, 3917 .size = { 3918 .width = 156, 3919 .height = 88, 3920 }, 3921 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3922 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3923 }; 3924 3925 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3926 .pixelclock = { 30000000, 30000000, 40000000 }, 3927 .hactive = { 800, 800, 800 }, 3928 .hfront_porch = { 40, 40, 40 }, 3929 .hback_porch = { 40, 40, 40 }, 3930 .hsync_len = { 1, 48, 48 }, 3931 .vactive = { 480, 480, 480 }, 3932 .vfront_porch = { 13, 13, 13 }, 3933 .vback_porch = { 29, 29, 29 }, 3934 .vsync_len = { 3, 3, 3 }, 3935 .flags = DISPLAY_FLAGS_DE_HIGH, 3936 }; 3937 3938 static const struct panel_desc okaya_rs800480t_7x0gp = { 3939 .timings = &okaya_rs800480t_7x0gp_timing, 3940 .num_timings = 1, 3941 .bpc = 6, 3942 .size = { 3943 .width = 154, 3944 .height = 87, 3945 }, 3946 .delay = { 3947 .prepare = 41, 3948 .enable = 50, 3949 .unprepare = 41, 3950 .disable = 50, 3951 }, 3952 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3953 }; 3954 3955 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3956 .clock = 9000, 3957 .hdisplay = 480, 3958 .hsync_start = 480 + 5, 3959 .hsync_end = 480 + 5 + 30, 3960 .htotal = 480 + 5 + 30 + 10, 3961 .vdisplay = 272, 3962 .vsync_start = 272 + 8, 3963 .vsync_end = 272 + 8 + 5, 3964 .vtotal = 272 + 8 + 5 + 3, 3965 }; 3966 3967 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3968 .modes = &olimex_lcd_olinuxino_43ts_mode, 3969 .num_modes = 1, 3970 .size = { 3971 .width = 95, 3972 .height = 54, 3973 }, 3974 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3975 }; 3976 3977 static const struct drm_display_mode olimex_lcd_olinuxino_5cts_mode = { 3978 .clock = 33300, 3979 .hdisplay = 800, 3980 .hsync_start = 800 + 210, 3981 .hsync_end = 800 + 210 + 20, 3982 .htotal = 800 + 210 + 20 + 26, 3983 .vdisplay = 480, 3984 .vsync_start = 480 + 22, 3985 .vsync_end = 480 + 22 + 10, 3986 .vtotal = 480 + 22 + 10 + 13, 3987 }; 3988 3989 static const struct panel_desc olimex_lcd_olinuxino_5cts = { 3990 .modes = &olimex_lcd_olinuxino_5cts_mode, 3991 .num_modes = 1, 3992 .size = { 3993 .width = 154, 3994 .height = 86, 3995 }, 3996 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3997 }; 3998 3999 4000 static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 4001 .pixelclock = { 30000000, 30000000, 50000000 }, 4002 .hactive = { 800, 800, 800 }, 4003 .hfront_porch = { 1, 40, 255 }, 4004 .hback_porch = { 1, 40, 87 }, 4005 .hsync_len = { 1, 48, 87 }, 4006 .vactive = { 480, 480, 480 }, 4007 .vfront_porch = { 1, 13, 255 }, 4008 .vback_porch = { 1, 29, 29 }, 4009 .vsync_len = { 3, 3, 31 }, 4010 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4011 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4012 }; 4013 4014 static const struct panel_desc ontat_kd50g21_40nt_a1 = { 4015 .timings = &ontat_kd50g21_40nt_a1_timing, 4016 .num_timings = 1, 4017 .bpc = 8, 4018 .size = { 4019 .width = 108, 4020 .height = 65, 4021 }, 4022 .delay = { 4023 .prepare = 147, /* 5 VSDs */ 4024 .enable = 147, /* 5 VSDs */ 4025 .disable = 88, /* 3 VSDs */ 4026 .unprepare = 117, /* 4 VSDs */ 4027 }, 4028 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4029 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4030 .connector_type = DRM_MODE_CONNECTOR_DPI, 4031 }; 4032 4033 /* 4034 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 4035 * pixel clocks, but this is the timing that was being used in the Adafruit 4036 * installation instructions. 4037 */ 4038 static const struct drm_display_mode ontat_yx700wv03_mode = { 4039 .clock = 29500, 4040 .hdisplay = 800, 4041 .hsync_start = 824, 4042 .hsync_end = 896, 4043 .htotal = 992, 4044 .vdisplay = 480, 4045 .vsync_start = 483, 4046 .vsync_end = 493, 4047 .vtotal = 500, 4048 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4049 }; 4050 4051 /* 4052 * Specification at: 4053 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 4054 */ 4055 static const struct panel_desc ontat_yx700wv03 = { 4056 .modes = &ontat_yx700wv03_mode, 4057 .num_modes = 1, 4058 .bpc = 8, 4059 .size = { 4060 .width = 154, 4061 .height = 83, 4062 }, 4063 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4064 }; 4065 4066 static const struct drm_display_mode ortustech_com37h3m_mode = { 4067 .clock = 22230, 4068 .hdisplay = 480, 4069 .hsync_start = 480 + 40, 4070 .hsync_end = 480 + 40 + 10, 4071 .htotal = 480 + 40 + 10 + 40, 4072 .vdisplay = 640, 4073 .vsync_start = 640 + 4, 4074 .vsync_end = 640 + 4 + 2, 4075 .vtotal = 640 + 4 + 2 + 4, 4076 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4077 }; 4078 4079 static const struct panel_desc ortustech_com37h3m = { 4080 .modes = &ortustech_com37h3m_mode, 4081 .num_modes = 1, 4082 .bpc = 8, 4083 .size = { 4084 .width = 56, /* 56.16mm */ 4085 .height = 75, /* 74.88mm */ 4086 }, 4087 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4088 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4089 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4090 }; 4091 4092 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 4093 .clock = 25000, 4094 .hdisplay = 480, 4095 .hsync_start = 480 + 10, 4096 .hsync_end = 480 + 10 + 10, 4097 .htotal = 480 + 10 + 10 + 15, 4098 .vdisplay = 800, 4099 .vsync_start = 800 + 3, 4100 .vsync_end = 800 + 3 + 3, 4101 .vtotal = 800 + 3 + 3 + 3, 4102 }; 4103 4104 static const struct panel_desc ortustech_com43h4m85ulc = { 4105 .modes = &ortustech_com43h4m85ulc_mode, 4106 .num_modes = 1, 4107 .bpc = 6, 4108 .size = { 4109 .width = 56, 4110 .height = 93, 4111 }, 4112 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4113 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4114 .connector_type = DRM_MODE_CONNECTOR_DPI, 4115 }; 4116 4117 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 4118 .clock = 33000, 4119 .hdisplay = 800, 4120 .hsync_start = 800 + 210, 4121 .hsync_end = 800 + 210 + 30, 4122 .htotal = 800 + 210 + 30 + 16, 4123 .vdisplay = 480, 4124 .vsync_start = 480 + 22, 4125 .vsync_end = 480 + 22 + 13, 4126 .vtotal = 480 + 22 + 13 + 10, 4127 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4128 }; 4129 4130 static const struct panel_desc osddisplays_osd070t1718_19ts = { 4131 .modes = &osddisplays_osd070t1718_19ts_mode, 4132 .num_modes = 1, 4133 .bpc = 8, 4134 .size = { 4135 .width = 152, 4136 .height = 91, 4137 }, 4138 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4139 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 4140 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4141 .connector_type = DRM_MODE_CONNECTOR_DPI, 4142 }; 4143 4144 static const struct drm_display_mode pda_91_00156_a0_mode = { 4145 .clock = 33300, 4146 .hdisplay = 800, 4147 .hsync_start = 800 + 1, 4148 .hsync_end = 800 + 1 + 64, 4149 .htotal = 800 + 1 + 64 + 64, 4150 .vdisplay = 480, 4151 .vsync_start = 480 + 1, 4152 .vsync_end = 480 + 1 + 23, 4153 .vtotal = 480 + 1 + 23 + 22, 4154 }; 4155 4156 static const struct panel_desc pda_91_00156_a0 = { 4157 .modes = &pda_91_00156_a0_mode, 4158 .num_modes = 1, 4159 .size = { 4160 .width = 152, 4161 .height = 91, 4162 }, 4163 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4164 }; 4165 4166 static const struct drm_display_mode powertip_ph128800t004_zza01_mode = { 4167 .clock = 71150, 4168 .hdisplay = 1280, 4169 .hsync_start = 1280 + 48, 4170 .hsync_end = 1280 + 48 + 32, 4171 .htotal = 1280 + 48 + 32 + 80, 4172 .vdisplay = 800, 4173 .vsync_start = 800 + 9, 4174 .vsync_end = 800 + 9 + 8, 4175 .vtotal = 800 + 9 + 8 + 6, 4176 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4177 }; 4178 4179 static const struct panel_desc powertip_ph128800t004_zza01 = { 4180 .modes = &powertip_ph128800t004_zza01_mode, 4181 .num_modes = 1, 4182 .bpc = 8, 4183 .size = { 4184 .width = 216, 4185 .height = 135, 4186 }, 4187 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4188 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4189 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4190 }; 4191 4192 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 4193 .clock = 66500, 4194 .hdisplay = 1280, 4195 .hsync_start = 1280 + 12, 4196 .hsync_end = 1280 + 12 + 20, 4197 .htotal = 1280 + 12 + 20 + 56, 4198 .vdisplay = 800, 4199 .vsync_start = 800 + 1, 4200 .vsync_end = 800 + 1 + 3, 4201 .vtotal = 800 + 1 + 3 + 20, 4202 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4203 }; 4204 4205 static const struct panel_desc powertip_ph128800t006_zhc01 = { 4206 .modes = &powertip_ph128800t006_zhc01_mode, 4207 .num_modes = 1, 4208 .bpc = 8, 4209 .size = { 4210 .width = 216, 4211 .height = 135, 4212 }, 4213 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4214 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4215 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4216 }; 4217 4218 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 4219 .clock = 24750, 4220 .hdisplay = 800, 4221 .hsync_start = 800 + 54, 4222 .hsync_end = 800 + 54 + 2, 4223 .htotal = 800 + 54 + 2 + 44, 4224 .vdisplay = 480, 4225 .vsync_start = 480 + 49, 4226 .vsync_end = 480 + 49 + 2, 4227 .vtotal = 480 + 49 + 2 + 22, 4228 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4229 }; 4230 4231 static const struct panel_desc powertip_ph800480t013_idf02 = { 4232 .modes = &powertip_ph800480t013_idf02_mode, 4233 .num_modes = 1, 4234 .bpc = 8, 4235 .size = { 4236 .width = 152, 4237 .height = 91, 4238 }, 4239 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4240 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4241 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4242 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4243 .connector_type = DRM_MODE_CONNECTOR_DPI, 4244 }; 4245 4246 static const struct drm_display_mode powertip_ph800480t032_zhc19_mode = { 4247 .clock = 27200, 4248 .hdisplay = 800, 4249 .hsync_start = 800 + 52, 4250 .hsync_end = 800 + 52 + 2, 4251 .htotal = 800 + 52 + 2 + 44, 4252 .vdisplay = 480, 4253 .vsync_start = 480 + 7, 4254 .vsync_end = 480 + 7 + 2, 4255 .vtotal = 480 + 7 + 2 + 2, 4256 }; 4257 4258 static const struct panel_desc powertip_ph800480t032_zhc19 = { 4259 .modes = &powertip_ph800480t032_zhc19_mode, 4260 .num_modes = 1, 4261 .bpc = 8, 4262 .size = { 4263 .width = 152, 4264 .height = 91, 4265 }, 4266 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4267 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4268 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4269 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4270 .connector_type = DRM_MODE_CONNECTOR_DPI, 4271 }; 4272 4273 static const struct drm_display_mode primeview_pm070wl4_mode = { 4274 .clock = 32000, 4275 .hdisplay = 800, 4276 .hsync_start = 800 + 42, 4277 .hsync_end = 800 + 42 + 128, 4278 .htotal = 800 + 42 + 128 + 86, 4279 .vdisplay = 480, 4280 .vsync_start = 480 + 10, 4281 .vsync_end = 480 + 10 + 2, 4282 .vtotal = 480 + 10 + 2 + 33, 4283 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4284 }; 4285 4286 static const struct panel_desc primeview_pm070wl4 = { 4287 .modes = &primeview_pm070wl4_mode, 4288 .num_modes = 1, 4289 .bpc = 6, 4290 .size = { 4291 .width = 152, 4292 .height = 91, 4293 }, 4294 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4295 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4296 .connector_type = DRM_MODE_CONNECTOR_DPI, 4297 }; 4298 4299 static const struct drm_display_mode qd43003c0_40_mode = { 4300 .clock = 9000, 4301 .hdisplay = 480, 4302 .hsync_start = 480 + 8, 4303 .hsync_end = 480 + 8 + 4, 4304 .htotal = 480 + 8 + 4 + 39, 4305 .vdisplay = 272, 4306 .vsync_start = 272 + 4, 4307 .vsync_end = 272 + 4 + 10, 4308 .vtotal = 272 + 4 + 10 + 2, 4309 }; 4310 4311 static const struct panel_desc qd43003c0_40 = { 4312 .modes = &qd43003c0_40_mode, 4313 .num_modes = 1, 4314 .bpc = 8, 4315 .size = { 4316 .width = 95, 4317 .height = 53, 4318 }, 4319 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4320 }; 4321 4322 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 4323 { /* 60 Hz */ 4324 .clock = 10800, 4325 .hdisplay = 480, 4326 .hsync_start = 480 + 77, 4327 .hsync_end = 480 + 77 + 41, 4328 .htotal = 480 + 77 + 41 + 2, 4329 .vdisplay = 272, 4330 .vsync_start = 272 + 16, 4331 .vsync_end = 272 + 16 + 10, 4332 .vtotal = 272 + 16 + 10 + 2, 4333 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4334 }, 4335 { /* 50 Hz */ 4336 .clock = 10800, 4337 .hdisplay = 480, 4338 .hsync_start = 480 + 17, 4339 .hsync_end = 480 + 17 + 41, 4340 .htotal = 480 + 17 + 41 + 2, 4341 .vdisplay = 272, 4342 .vsync_start = 272 + 116, 4343 .vsync_end = 272 + 116 + 10, 4344 .vtotal = 272 + 116 + 10 + 2, 4345 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4346 }, 4347 }; 4348 4349 static const struct panel_desc qishenglong_gopher2b_lcd = { 4350 .modes = qishenglong_gopher2b_lcd_modes, 4351 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 4352 .bpc = 8, 4353 .size = { 4354 .width = 95, 4355 .height = 54, 4356 }, 4357 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4358 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4359 .connector_type = DRM_MODE_CONNECTOR_DPI, 4360 }; 4361 4362 static const struct display_timing raystar_rff500f_awh_dnn_timing = { 4363 .pixelclock = { 23000000, 25000000, 27000000 }, 4364 .hactive = { 800, 800, 800 }, 4365 .hback_porch = { 4, 8, 48 }, 4366 .hfront_porch = { 4, 8, 48 }, 4367 .hsync_len = { 2, 4, 8 }, 4368 .vactive = { 480, 480, 480 }, 4369 .vback_porch = { 4, 8, 12 }, 4370 .vfront_porch = { 4, 8, 12 }, 4371 .vsync_len = { 2, 4, 8 }, 4372 }; 4373 4374 static const struct panel_desc raystar_rff500f_awh_dnn = { 4375 .timings = &raystar_rff500f_awh_dnn_timing, 4376 .num_timings = 1, 4377 .bpc = 8, 4378 .size = { 4379 .width = 108, 4380 .height = 65, 4381 }, 4382 .delay = { 4383 .enable = 250, 4384 }, 4385 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4386 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4387 }; 4388 4389 static const struct display_timing rocktech_rk043fn48h_timing = { 4390 .pixelclock = { 6000000, 9000000, 12000000 }, 4391 .hactive = { 480, 480, 480 }, 4392 .hback_porch = { 8, 43, 43 }, 4393 .hfront_porch = { 2, 8, 10 }, 4394 .hsync_len = { 1, 1, 1 }, 4395 .vactive = { 272, 272, 272 }, 4396 .vback_porch = { 2, 12, 26 }, 4397 .vfront_porch = { 1, 4, 4 }, 4398 .vsync_len = { 1, 10, 10 }, 4399 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 4400 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4401 DISPLAY_FLAGS_SYNC_POSEDGE, 4402 }; 4403 4404 static const struct panel_desc rocktech_rk043fn48h = { 4405 .timings = &rocktech_rk043fn48h_timing, 4406 .num_timings = 1, 4407 .bpc = 8, 4408 .size = { 4409 .width = 95, 4410 .height = 54, 4411 }, 4412 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4413 .connector_type = DRM_MODE_CONNECTOR_DPI, 4414 }; 4415 4416 static const struct display_timing rocktech_rk070er9427_timing = { 4417 .pixelclock = { 26400000, 33300000, 46800000 }, 4418 .hactive = { 800, 800, 800 }, 4419 .hfront_porch = { 16, 210, 354 }, 4420 .hback_porch = { 46, 46, 46 }, 4421 .hsync_len = { 1, 1, 1 }, 4422 .vactive = { 480, 480, 480 }, 4423 .vfront_porch = { 7, 22, 147 }, 4424 .vback_porch = { 23, 23, 23 }, 4425 .vsync_len = { 1, 1, 1 }, 4426 .flags = DISPLAY_FLAGS_DE_HIGH, 4427 }; 4428 4429 static const struct panel_desc rocktech_rk070er9427 = { 4430 .timings = &rocktech_rk070er9427_timing, 4431 .num_timings = 1, 4432 .bpc = 6, 4433 .size = { 4434 .width = 154, 4435 .height = 86, 4436 }, 4437 .delay = { 4438 .prepare = 41, 4439 .enable = 50, 4440 .unprepare = 41, 4441 .disable = 50, 4442 }, 4443 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4444 }; 4445 4446 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4447 .clock = 71100, 4448 .hdisplay = 1280, 4449 .hsync_start = 1280 + 48, 4450 .hsync_end = 1280 + 48 + 32, 4451 .htotal = 1280 + 48 + 32 + 80, 4452 .vdisplay = 800, 4453 .vsync_start = 800 + 2, 4454 .vsync_end = 800 + 2 + 5, 4455 .vtotal = 800 + 2 + 5 + 16, 4456 }; 4457 4458 static const struct panel_desc rocktech_rk101ii01d_ct = { 4459 .modes = &rocktech_rk101ii01d_ct_mode, 4460 .bpc = 8, 4461 .num_modes = 1, 4462 .size = { 4463 .width = 217, 4464 .height = 136, 4465 }, 4466 .delay = { 4467 .prepare = 50, 4468 .disable = 50, 4469 }, 4470 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4471 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4472 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4473 }; 4474 4475 static const struct display_timing samsung_ltl101al01_timing = { 4476 .pixelclock = { 66663000, 66663000, 66663000 }, 4477 .hactive = { 1280, 1280, 1280 }, 4478 .hfront_porch = { 18, 18, 18 }, 4479 .hback_porch = { 36, 36, 36 }, 4480 .hsync_len = { 16, 16, 16 }, 4481 .vactive = { 800, 800, 800 }, 4482 .vfront_porch = { 4, 4, 4 }, 4483 .vback_porch = { 16, 16, 16 }, 4484 .vsync_len = { 3, 3, 3 }, 4485 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4486 }; 4487 4488 static const struct panel_desc samsung_ltl101al01 = { 4489 .timings = &samsung_ltl101al01_timing, 4490 .num_timings = 1, 4491 .bpc = 8, 4492 .size = { 4493 .width = 217, 4494 .height = 135, 4495 }, 4496 .delay = { 4497 .prepare = 40, 4498 .enable = 300, 4499 .disable = 200, 4500 .unprepare = 600, 4501 }, 4502 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4503 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4504 }; 4505 4506 static const struct display_timing samsung_ltl106al01_timing = { 4507 .pixelclock = { 71980000, 71980000, 71980000 }, 4508 .hactive = { 1366, 1366, 1366 }, 4509 .hfront_porch = { 56, 56, 56 }, 4510 .hback_porch = { 106, 106, 106 }, 4511 .hsync_len = { 14, 14, 14 }, 4512 .vactive = { 768, 768, 768 }, 4513 .vfront_porch = { 3, 3, 3 }, 4514 .vback_porch = { 6, 6, 6 }, 4515 .vsync_len = { 1, 1, 1 }, 4516 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4517 }; 4518 4519 static const struct panel_desc samsung_ltl106al01 = { 4520 .timings = &samsung_ltl106al01_timing, 4521 .num_timings = 1, 4522 .bpc = 8, 4523 .size = { 4524 .width = 235, 4525 .height = 132, 4526 }, 4527 .delay = { 4528 .prepare = 5, 4529 .enable = 10, 4530 .disable = 10, 4531 .unprepare = 5, 4532 }, 4533 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4534 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4535 }; 4536 4537 static const struct drm_display_mode samsung_ltn101nt05_mode = { 4538 .clock = 54030, 4539 .hdisplay = 1024, 4540 .hsync_start = 1024 + 24, 4541 .hsync_end = 1024 + 24 + 136, 4542 .htotal = 1024 + 24 + 136 + 160, 4543 .vdisplay = 600, 4544 .vsync_start = 600 + 3, 4545 .vsync_end = 600 + 3 + 6, 4546 .vtotal = 600 + 3 + 6 + 61, 4547 }; 4548 4549 static const struct panel_desc samsung_ltn101nt05 = { 4550 .modes = &samsung_ltn101nt05_mode, 4551 .num_modes = 1, 4552 .bpc = 6, 4553 .size = { 4554 .width = 223, 4555 .height = 125, 4556 }, 4557 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4558 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4559 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4560 }; 4561 4562 static const struct display_timing satoz_sat050at40h12r2_timing = { 4563 .pixelclock = {33300000, 33300000, 50000000}, 4564 .hactive = {800, 800, 800}, 4565 .hfront_porch = {16, 210, 354}, 4566 .hback_porch = {46, 46, 46}, 4567 .hsync_len = {1, 1, 40}, 4568 .vactive = {480, 480, 480}, 4569 .vfront_porch = {7, 22, 147}, 4570 .vback_porch = {23, 23, 23}, 4571 .vsync_len = {1, 1, 20}, 4572 }; 4573 4574 static const struct panel_desc satoz_sat050at40h12r2 = { 4575 .timings = &satoz_sat050at40h12r2_timing, 4576 .num_timings = 1, 4577 .bpc = 8, 4578 .size = { 4579 .width = 108, 4580 .height = 65, 4581 }, 4582 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4583 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4584 }; 4585 4586 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4587 .clock = 33260, 4588 .hdisplay = 800, 4589 .hsync_start = 800 + 64, 4590 .hsync_end = 800 + 64 + 128, 4591 .htotal = 800 + 64 + 128 + 64, 4592 .vdisplay = 480, 4593 .vsync_start = 480 + 8, 4594 .vsync_end = 480 + 8 + 2, 4595 .vtotal = 480 + 8 + 2 + 35, 4596 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4597 }; 4598 4599 static const struct panel_desc sharp_lq070y3dg3b = { 4600 .modes = &sharp_lq070y3dg3b_mode, 4601 .num_modes = 1, 4602 .bpc = 8, 4603 .size = { 4604 .width = 152, /* 152.4mm */ 4605 .height = 91, /* 91.4mm */ 4606 }, 4607 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4608 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4609 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4610 }; 4611 4612 static const struct drm_display_mode sharp_lq035q7db03_mode = { 4613 .clock = 5500, 4614 .hdisplay = 240, 4615 .hsync_start = 240 + 16, 4616 .hsync_end = 240 + 16 + 7, 4617 .htotal = 240 + 16 + 7 + 5, 4618 .vdisplay = 320, 4619 .vsync_start = 320 + 9, 4620 .vsync_end = 320 + 9 + 1, 4621 .vtotal = 320 + 9 + 1 + 7, 4622 }; 4623 4624 static const struct panel_desc sharp_lq035q7db03 = { 4625 .modes = &sharp_lq035q7db03_mode, 4626 .num_modes = 1, 4627 .bpc = 6, 4628 .size = { 4629 .width = 54, 4630 .height = 72, 4631 }, 4632 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4633 }; 4634 4635 static const struct display_timing sharp_lq101k1ly04_timing = { 4636 .pixelclock = { 60000000, 65000000, 80000000 }, 4637 .hactive = { 1280, 1280, 1280 }, 4638 .hfront_porch = { 20, 20, 20 }, 4639 .hback_porch = { 20, 20, 20 }, 4640 .hsync_len = { 10, 10, 10 }, 4641 .vactive = { 800, 800, 800 }, 4642 .vfront_porch = { 4, 4, 4 }, 4643 .vback_porch = { 4, 4, 4 }, 4644 .vsync_len = { 4, 4, 4 }, 4645 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4646 }; 4647 4648 static const struct panel_desc sharp_lq101k1ly04 = { 4649 .timings = &sharp_lq101k1ly04_timing, 4650 .num_timings = 1, 4651 .bpc = 8, 4652 .size = { 4653 .width = 217, 4654 .height = 136, 4655 }, 4656 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4657 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4658 }; 4659 4660 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4661 { /* 50 Hz */ 4662 .clock = 3000, 4663 .hdisplay = 240, 4664 .hsync_start = 240 + 58, 4665 .hsync_end = 240 + 58 + 1, 4666 .htotal = 240 + 58 + 1 + 1, 4667 .vdisplay = 160, 4668 .vsync_start = 160 + 24, 4669 .vsync_end = 160 + 24 + 10, 4670 .vtotal = 160 + 24 + 10 + 6, 4671 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4672 }, 4673 { /* 60 Hz */ 4674 .clock = 3000, 4675 .hdisplay = 240, 4676 .hsync_start = 240 + 8, 4677 .hsync_end = 240 + 8 + 1, 4678 .htotal = 240 + 8 + 1 + 1, 4679 .vdisplay = 160, 4680 .vsync_start = 160 + 24, 4681 .vsync_end = 160 + 24 + 10, 4682 .vtotal = 160 + 24 + 10 + 6, 4683 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4684 }, 4685 }; 4686 4687 static const struct panel_desc sharp_ls020b1dd01d = { 4688 .modes = sharp_ls020b1dd01d_modes, 4689 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4690 .bpc = 6, 4691 .size = { 4692 .width = 42, 4693 .height = 28, 4694 }, 4695 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4696 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4697 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4698 | DRM_BUS_FLAG_SHARP_SIGNALS, 4699 }; 4700 4701 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4702 .clock = 33300, 4703 .hdisplay = 800, 4704 .hsync_start = 800 + 1, 4705 .hsync_end = 800 + 1 + 64, 4706 .htotal = 800 + 1 + 64 + 64, 4707 .vdisplay = 480, 4708 .vsync_start = 480 + 1, 4709 .vsync_end = 480 + 1 + 23, 4710 .vtotal = 480 + 1 + 23 + 22, 4711 }; 4712 4713 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4714 .modes = &shelly_sca07010_bfn_lnn_mode, 4715 .num_modes = 1, 4716 .size = { 4717 .width = 152, 4718 .height = 91, 4719 }, 4720 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4721 }; 4722 4723 static const struct drm_display_mode starry_kr070pe2t_mode = { 4724 .clock = 33000, 4725 .hdisplay = 800, 4726 .hsync_start = 800 + 209, 4727 .hsync_end = 800 + 209 + 1, 4728 .htotal = 800 + 209 + 1 + 45, 4729 .vdisplay = 480, 4730 .vsync_start = 480 + 22, 4731 .vsync_end = 480 + 22 + 1, 4732 .vtotal = 480 + 22 + 1 + 22, 4733 }; 4734 4735 static const struct panel_desc starry_kr070pe2t = { 4736 .modes = &starry_kr070pe2t_mode, 4737 .num_modes = 1, 4738 .bpc = 8, 4739 .size = { 4740 .width = 152, 4741 .height = 86, 4742 }, 4743 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4744 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4745 .connector_type = DRM_MODE_CONNECTOR_DPI, 4746 }; 4747 4748 static const struct display_timing startek_kd070hdfld092_timing = { 4749 .pixelclock = { 40800000, 51200000, 67200000 }, 4750 .hactive = { 1024, 1024, 1024 }, 4751 .hfront_porch = { 40, 160, 216 }, 4752 .hback_porch = { 30, 140, 140 }, 4753 .hsync_len = { 20, 20, 20 }, 4754 .vactive = { 600, 600, 600 }, 4755 .vfront_porch = { 2, 12, 177 }, 4756 .vback_porch = { 5, 20, 20 }, 4757 .vsync_len = { 3, 3, 3 }, 4758 .flags = DISPLAY_FLAGS_DE_HIGH, 4759 }; 4760 4761 static const struct panel_desc startek_kd070hdfld092 = { 4762 .timings = &startek_kd070hdfld092_timing, 4763 .num_timings = 1, 4764 .bpc = 8, 4765 .size = { 4766 .width = 154, 4767 .height = 86, 4768 }, 4769 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4770 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4771 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4772 }; 4773 4774 static const struct display_timing startek_kd070wvfpa_mode = { 4775 .pixelclock = { 25200000, 27200000, 30500000 }, 4776 .hactive = { 800, 800, 800 }, 4777 .hfront_porch = { 19, 44, 115 }, 4778 .hback_porch = { 5, 16, 101 }, 4779 .hsync_len = { 1, 2, 100 }, 4780 .vactive = { 480, 480, 480 }, 4781 .vfront_porch = { 5, 43, 67 }, 4782 .vback_porch = { 5, 5, 67 }, 4783 .vsync_len = { 1, 2, 66 }, 4784 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4785 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4786 DISPLAY_FLAGS_SYNC_POSEDGE, 4787 }; 4788 4789 static const struct panel_desc startek_kd070wvfpa = { 4790 .timings = &startek_kd070wvfpa_mode, 4791 .num_timings = 1, 4792 .bpc = 8, 4793 .size = { 4794 .width = 152, 4795 .height = 91, 4796 }, 4797 .delay = { 4798 .prepare = 20, 4799 .enable = 200, 4800 .disable = 200, 4801 }, 4802 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4803 .connector_type = DRM_MODE_CONNECTOR_DPI, 4804 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4805 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4806 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4807 }; 4808 4809 static const struct display_timing tsd_tst043015cmhx_timing = { 4810 .pixelclock = { 5000000, 9000000, 12000000 }, 4811 .hactive = { 480, 480, 480 }, 4812 .hfront_porch = { 4, 5, 65 }, 4813 .hback_porch = { 36, 40, 255 }, 4814 .hsync_len = { 1, 1, 1 }, 4815 .vactive = { 272, 272, 272 }, 4816 .vfront_porch = { 2, 8, 97 }, 4817 .vback_porch = { 3, 8, 31 }, 4818 .vsync_len = { 1, 1, 1 }, 4819 4820 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4821 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4822 }; 4823 4824 static const struct panel_desc tsd_tst043015cmhx = { 4825 .timings = &tsd_tst043015cmhx_timing, 4826 .num_timings = 1, 4827 .bpc = 8, 4828 .size = { 4829 .width = 105, 4830 .height = 67, 4831 }, 4832 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4833 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4834 }; 4835 4836 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4837 .clock = 30000, 4838 .hdisplay = 800, 4839 .hsync_start = 800 + 39, 4840 .hsync_end = 800 + 39 + 47, 4841 .htotal = 800 + 39 + 47 + 39, 4842 .vdisplay = 480, 4843 .vsync_start = 480 + 13, 4844 .vsync_end = 480 + 13 + 2, 4845 .vtotal = 480 + 13 + 2 + 29, 4846 }; 4847 4848 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4849 .modes = &tfc_s9700rtwv43tr_01b_mode, 4850 .num_modes = 1, 4851 .bpc = 8, 4852 .size = { 4853 .width = 155, 4854 .height = 90, 4855 }, 4856 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4857 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4858 }; 4859 4860 static const struct display_timing tianma_tm070jdhg30_timing = { 4861 .pixelclock = { 62600000, 68200000, 78100000 }, 4862 .hactive = { 1280, 1280, 1280 }, 4863 .hfront_porch = { 15, 64, 159 }, 4864 .hback_porch = { 5, 5, 5 }, 4865 .hsync_len = { 1, 1, 256 }, 4866 .vactive = { 800, 800, 800 }, 4867 .vfront_porch = { 3, 40, 99 }, 4868 .vback_porch = { 2, 2, 2 }, 4869 .vsync_len = { 1, 1, 128 }, 4870 .flags = DISPLAY_FLAGS_DE_HIGH, 4871 }; 4872 4873 static const struct panel_desc tianma_tm070jdhg30 = { 4874 .timings = &tianma_tm070jdhg30_timing, 4875 .num_timings = 1, 4876 .bpc = 8, 4877 .size = { 4878 .width = 151, 4879 .height = 95, 4880 }, 4881 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4882 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4883 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4884 }; 4885 4886 static const struct panel_desc tianma_tm070jvhg33 = { 4887 .timings = &tianma_tm070jdhg30_timing, 4888 .num_timings = 1, 4889 .bpc = 8, 4890 .size = { 4891 .width = 150, 4892 .height = 94, 4893 }, 4894 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4895 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4896 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4897 }; 4898 4899 /* 4900 * The TM070JDHG34-00 datasheet computes total blanking as back porch + 4901 * front porch, not including sync pulse width. This is for both H and 4902 * V. To make the total blanking and period correct, subtract the pulse 4903 * width from the front porch. 4904 * 4905 * This works well for the Min and Typ values, but for Max values the sync 4906 * pulse width is higher than back porch + front porch, so work around that 4907 * by reducing the Max sync length value to 1 and then treating the Max 4908 * porches as in the Min and Typ cases. 4909 * 4910 * Exact datasheet values are added as a comment where they differ from the 4911 * ones implemented for the above reason. 4912 * 4913 * The P0700WXF1MBAA datasheet is even less detailed, only listing period 4914 * and total blanking time, however the resulting values are the same as 4915 * the TM070JDHG34-00. 4916 */ 4917 static const struct display_timing tianma_tm070jdhg34_00_timing = { 4918 .pixelclock = { 68400000, 71900000, 78100000 }, 4919 .hactive = { 1280, 1280, 1280 }, 4920 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4921 .hback_porch = { 5, 5, 5 }, 4922 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4923 .vactive = { 800, 800, 800 }, 4924 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4925 .vback_porch = { 2, 2, 2 }, 4926 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4927 .flags = DISPLAY_FLAGS_DE_HIGH, 4928 }; 4929 4930 static const struct panel_desc tianma_tm070jdhg34_00 = { 4931 .timings = &tianma_tm070jdhg34_00_timing, 4932 .num_timings = 1, 4933 .bpc = 8, 4934 .size = { 4935 .width = 150, /* 149.76 */ 4936 .height = 94, /* 93.60 */ 4937 }, 4938 .delay = { 4939 .prepare = 15, /* Tp1 */ 4940 .enable = 150, /* Tp2 */ 4941 .disable = 150, /* Tp4 */ 4942 .unprepare = 120, /* Tp3 */ 4943 }, 4944 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4945 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4946 }; 4947 4948 static const struct panel_desc tianma_p0700wxf1mbaa = { 4949 .timings = &tianma_tm070jdhg34_00_timing, 4950 .num_timings = 1, 4951 .bpc = 8, 4952 .size = { 4953 .width = 150, /* 149.76 */ 4954 .height = 94, /* 93.60 */ 4955 }, 4956 .delay = { 4957 .prepare = 18, /* Tr + Tp1 */ 4958 .enable = 152, /* Tp2 + Tp5 */ 4959 .disable = 152, /* Tp6 + Tp4 */ 4960 .unprepare = 120, /* Tp3 */ 4961 }, 4962 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4963 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4964 }; 4965 4966 static const struct display_timing tianma_tm070rvhg71_timing = { 4967 .pixelclock = { 27700000, 29200000, 39600000 }, 4968 .hactive = { 800, 800, 800 }, 4969 .hfront_porch = { 12, 40, 212 }, 4970 .hback_porch = { 88, 88, 88 }, 4971 .hsync_len = { 1, 1, 40 }, 4972 .vactive = { 480, 480, 480 }, 4973 .vfront_porch = { 1, 13, 88 }, 4974 .vback_porch = { 32, 32, 32 }, 4975 .vsync_len = { 1, 1, 3 }, 4976 .flags = DISPLAY_FLAGS_DE_HIGH, 4977 }; 4978 4979 static const struct panel_desc tianma_tm070rvhg71 = { 4980 .timings = &tianma_tm070rvhg71_timing, 4981 .num_timings = 1, 4982 .bpc = 8, 4983 .size = { 4984 .width = 154, 4985 .height = 86, 4986 }, 4987 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4988 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4989 }; 4990 4991 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4992 { 4993 .clock = 10000, 4994 .hdisplay = 320, 4995 .hsync_start = 320 + 50, 4996 .hsync_end = 320 + 50 + 6, 4997 .htotal = 320 + 50 + 6 + 38, 4998 .vdisplay = 240, 4999 .vsync_start = 240 + 3, 5000 .vsync_end = 240 + 3 + 1, 5001 .vtotal = 240 + 3 + 1 + 17, 5002 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5003 }, 5004 }; 5005 5006 static const struct panel_desc ti_nspire_cx_lcd_panel = { 5007 .modes = ti_nspire_cx_lcd_mode, 5008 .num_modes = 1, 5009 .bpc = 8, 5010 .size = { 5011 .width = 65, 5012 .height = 49, 5013 }, 5014 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5015 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 5016 }; 5017 5018 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 5019 { 5020 .clock = 10000, 5021 .hdisplay = 320, 5022 .hsync_start = 320 + 6, 5023 .hsync_end = 320 + 6 + 6, 5024 .htotal = 320 + 6 + 6 + 6, 5025 .vdisplay = 240, 5026 .vsync_start = 240 + 0, 5027 .vsync_end = 240 + 0 + 1, 5028 .vtotal = 240 + 0 + 1 + 0, 5029 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 5030 }, 5031 }; 5032 5033 static const struct panel_desc ti_nspire_classic_lcd_panel = { 5034 .modes = ti_nspire_classic_lcd_mode, 5035 .num_modes = 1, 5036 /* The grayscale panel has 8 bit for the color .. Y (black) */ 5037 .bpc = 8, 5038 .size = { 5039 .width = 71, 5040 .height = 53, 5041 }, 5042 /* This is the grayscale bus format */ 5043 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 5044 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 5045 }; 5046 5047 static const struct display_timing topland_tian_g07017_01_timing = { 5048 .pixelclock = { 44900000, 51200000, 63000000 }, 5049 .hactive = { 1024, 1024, 1024 }, 5050 .hfront_porch = { 16, 160, 216 }, 5051 .hback_porch = { 160, 160, 160 }, 5052 .hsync_len = { 1, 1, 140 }, 5053 .vactive = { 600, 600, 600 }, 5054 .vfront_porch = { 1, 12, 127 }, 5055 .vback_porch = { 23, 23, 23 }, 5056 .vsync_len = { 1, 1, 20 }, 5057 }; 5058 5059 static const struct panel_desc topland_tian_g07017_01 = { 5060 .timings = &topland_tian_g07017_01_timing, 5061 .num_timings = 1, 5062 .bpc = 8, 5063 .size = { 5064 .width = 154, 5065 .height = 86, 5066 }, 5067 .delay = { 5068 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 5069 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 5070 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 5071 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 5072 }, 5073 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5074 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5075 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5076 }; 5077 5078 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 5079 .clock = 79500, 5080 .hdisplay = 1280, 5081 .hsync_start = 1280 + 192, 5082 .hsync_end = 1280 + 192 + 128, 5083 .htotal = 1280 + 192 + 128 + 64, 5084 .vdisplay = 768, 5085 .vsync_start = 768 + 20, 5086 .vsync_end = 768 + 20 + 7, 5087 .vtotal = 768 + 20 + 7 + 3, 5088 }; 5089 5090 static const struct panel_desc toshiba_lt089ac29000 = { 5091 .modes = &toshiba_lt089ac29000_mode, 5092 .num_modes = 1, 5093 .size = { 5094 .width = 194, 5095 .height = 116, 5096 }, 5097 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 5098 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5099 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5100 }; 5101 5102 static const struct drm_display_mode tpk_f07a_0102_mode = { 5103 .clock = 33260, 5104 .hdisplay = 800, 5105 .hsync_start = 800 + 40, 5106 .hsync_end = 800 + 40 + 128, 5107 .htotal = 800 + 40 + 128 + 88, 5108 .vdisplay = 480, 5109 .vsync_start = 480 + 10, 5110 .vsync_end = 480 + 10 + 2, 5111 .vtotal = 480 + 10 + 2 + 33, 5112 }; 5113 5114 static const struct panel_desc tpk_f07a_0102 = { 5115 .modes = &tpk_f07a_0102_mode, 5116 .num_modes = 1, 5117 .size = { 5118 .width = 152, 5119 .height = 91, 5120 }, 5121 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 5122 }; 5123 5124 static const struct drm_display_mode tpk_f10a_0102_mode = { 5125 .clock = 45000, 5126 .hdisplay = 1024, 5127 .hsync_start = 1024 + 176, 5128 .hsync_end = 1024 + 176 + 5, 5129 .htotal = 1024 + 176 + 5 + 88, 5130 .vdisplay = 600, 5131 .vsync_start = 600 + 20, 5132 .vsync_end = 600 + 20 + 5, 5133 .vtotal = 600 + 20 + 5 + 25, 5134 }; 5135 5136 static const struct panel_desc tpk_f10a_0102 = { 5137 .modes = &tpk_f10a_0102_mode, 5138 .num_modes = 1, 5139 .size = { 5140 .width = 223, 5141 .height = 125, 5142 }, 5143 }; 5144 5145 static const struct drm_display_mode truly_tft320240_229_e_mode = { 5146 .clock = 6410, 5147 .hdisplay = 320, 5148 .hsync_start = 320 + 8, 5149 .hsync_end = 320 + 8 + 39, 5150 .htotal = 320 + 8 + 39 + 4, 5151 .vdisplay = 240, 5152 .vsync_start = 240 + 8, 5153 .vsync_end = 240 + 8 + 8, 5154 .vtotal = 240 + 8 + 8 + 4, 5155 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5156 }; 5157 5158 static const struct panel_desc truly_tft320240_229_e = { 5159 .modes = &truly_tft320240_229_e_mode, 5160 .num_modes = 1, 5161 .bpc = 8, 5162 .size = { 5163 .width = 70, 5164 .height = 53, 5165 }, 5166 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5167 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5168 .connector_type = DRM_MODE_CONNECTOR_DPI, 5169 }; 5170 5171 static const struct display_timing urt_umsh_8596md_timing = { 5172 .pixelclock = { 33260000, 33260000, 33260000 }, 5173 .hactive = { 800, 800, 800 }, 5174 .hfront_porch = { 41, 41, 41 }, 5175 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 5176 .hsync_len = { 71, 128, 128 }, 5177 .vactive = { 480, 480, 480 }, 5178 .vfront_porch = { 10, 10, 10 }, 5179 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 5180 .vsync_len = { 2, 2, 2 }, 5181 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 5182 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 5183 }; 5184 5185 static const struct panel_desc urt_umsh_8596md_lvds = { 5186 .timings = &urt_umsh_8596md_timing, 5187 .num_timings = 1, 5188 .bpc = 6, 5189 .size = { 5190 .width = 152, 5191 .height = 91, 5192 }, 5193 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 5194 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5195 }; 5196 5197 static const struct panel_desc urt_umsh_8596md_parallel = { 5198 .timings = &urt_umsh_8596md_timing, 5199 .num_timings = 1, 5200 .bpc = 6, 5201 .size = { 5202 .width = 152, 5203 .height = 91, 5204 }, 5205 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 5206 }; 5207 5208 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 5209 .clock = 60000, 5210 .hdisplay = 1024, 5211 .hsync_start = 1024 + 160, 5212 .hsync_end = 1024 + 160 + 100, 5213 .htotal = 1024 + 160 + 100 + 60, 5214 .vdisplay = 600, 5215 .vsync_start = 600 + 12, 5216 .vsync_end = 600 + 12 + 10, 5217 .vtotal = 600 + 12 + 10 + 13, 5218 }; 5219 5220 static const struct panel_desc vivax_tpc9150_panel = { 5221 .modes = &vivax_tpc9150_panel_mode, 5222 .num_modes = 1, 5223 .bpc = 6, 5224 .size = { 5225 .width = 200, 5226 .height = 115, 5227 }, 5228 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 5229 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5230 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5231 }; 5232 5233 static const struct drm_display_mode vl050_8048nt_c01_mode = { 5234 .clock = 33333, 5235 .hdisplay = 800, 5236 .hsync_start = 800 + 210, 5237 .hsync_end = 800 + 210 + 20, 5238 .htotal = 800 + 210 + 20 + 46, 5239 .vdisplay = 480, 5240 .vsync_start = 480 + 22, 5241 .vsync_end = 480 + 22 + 10, 5242 .vtotal = 480 + 22 + 10 + 23, 5243 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5244 }; 5245 5246 static const struct panel_desc vl050_8048nt_c01 = { 5247 .modes = &vl050_8048nt_c01_mode, 5248 .num_modes = 1, 5249 .bpc = 8, 5250 .size = { 5251 .width = 120, 5252 .height = 76, 5253 }, 5254 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5255 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 5256 }; 5257 5258 static const struct drm_display_mode waveshare_28_lcd_mode = { 5259 .clock = 50000, 5260 .hdisplay = 480, 5261 .hsync_start = 480 + 150, 5262 .hsync_end = 480 + 150 + 50, 5263 .htotal = 480 + 150 + 50 + 150, 5264 .vdisplay = 640, 5265 .vsync_start = 640 + 150, 5266 .vsync_end = 640 + 150 + 50, 5267 .vtotal = 640 + 150 + 50 + 150, 5268 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5269 }; 5270 5271 static const struct panel_desc waveshare_28_lcd_panel = { 5272 .modes = &waveshare_28_lcd_mode, 5273 .num_modes = 1, 5274 .bpc = 8, 5275 .size = { 5276 .width = 44, 5277 .height = 58, 5278 }, 5279 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5280 .connector_type = DRM_MODE_CONNECTOR_DPI, 5281 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5282 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5283 }; 5284 5285 static const struct drm_display_mode waveshare_34_lcd_c_mode = { 5286 .clock = 50000, 5287 .hdisplay = 800, 5288 .hsync_start = 800 + 32, 5289 .hsync_end = 800 + 32 + 6, 5290 .htotal = 800 + 32 + 6 + 120, 5291 .vdisplay = 800, 5292 .vsync_start = 800 + 8, 5293 .vsync_end = 800 + 8 + 4, 5294 .vtotal = 800 + 8 + 4 + 16, 5295 }; 5296 5297 static const struct panel_desc waveshare_34_lcd_c_panel = { 5298 .modes = &waveshare_34_lcd_c_mode, 5299 .num_modes = 1, 5300 .bpc = 8, 5301 .size = { 5302 .width = 88, 5303 .height = 88, 5304 }, 5305 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5306 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5307 }; 5308 5309 static const struct drm_display_mode waveshare_40_lcd_mode = { 5310 .clock = 50000, 5311 .hdisplay = 480, 5312 .hsync_start = 480 + 150, 5313 .hsync_end = 480 + 150 + 100, 5314 .htotal = 480 + 150 + 100 + 150, 5315 .vdisplay = 800, 5316 .vsync_start = 800 + 20, 5317 .vsync_end = 800 + 20 + 100, 5318 .vtotal = 800 + 20 + 100 + 20, 5319 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5320 }; 5321 5322 static const struct panel_desc waveshare_40_lcd_panel = { 5323 .modes = &waveshare_40_lcd_mode, 5324 .num_modes = 1, 5325 .bpc = 8, 5326 .size = { 5327 .width = 52, 5328 .height = 87, 5329 }, 5330 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5331 .connector_type = DRM_MODE_CONNECTOR_DPI, 5332 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5333 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5334 }; 5335 5336 static const struct drm_display_mode waveshare_40_lcd_c_mode = { 5337 .clock = 50000, 5338 .hdisplay = 720, 5339 .hsync_start = 720 + 32, 5340 .hsync_end = 720 + 32 + 200, 5341 .htotal = 720 + 32 + 200 + 120, 5342 .vdisplay = 720, 5343 .vsync_start = 720 + 8, 5344 .vsync_end = 720 + 8 + 4, 5345 .vtotal = 720 + 8 + 4 + 16, 5346 }; 5347 5348 static const struct panel_desc waveshare_40_lcd_c_panel = { 5349 .modes = &waveshare_40_lcd_c_mode, 5350 .num_modes = 1, 5351 .bpc = 8, 5352 .size = { 5353 .width = 102, 5354 .height = 102, 5355 }, 5356 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5357 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5358 }; 5359 5360 static const struct drm_display_mode waveshare_50_lcd_c_mode = { 5361 .clock = 50000, 5362 .hdisplay = 1024, 5363 .hsync_start = 1024 + 100, 5364 .hsync_end = 1024 + 100 + 100, 5365 .htotal = 1024 + 100 + 100 + 100, 5366 .vdisplay = 600, 5367 .vsync_start = 600 + 10, 5368 .vsync_end = 600 + 10 + 10, 5369 .vtotal = 600 + 10 + 10 + 10, 5370 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5371 }; 5372 5373 static const struct panel_desc waveshare_50_lcd_c_panel = { 5374 .modes = &waveshare_50_lcd_c_mode, 5375 .num_modes = 1, 5376 .bpc = 8, 5377 .size = { 5378 .width = 109, 5379 .height = 66, 5380 }, 5381 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5382 .connector_type = DRM_MODE_CONNECTOR_DPI, 5383 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5384 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5385 }; 5386 5387 static const struct drm_display_mode waveshare_50_lcd_d_mode = { 5388 .clock = 83333, 5389 .hdisplay = 720, 5390 .hsync_start = 720 + 100, 5391 .hsync_end = 720 + 100 + 80, 5392 .htotal = 720 + 100 + 80 + 100, 5393 .vdisplay = 1280, 5394 .vsync_start = 1280 + 20, 5395 .vsync_end = 1280 + 20 + 20, 5396 .vtotal = 1280 + 20 + 20 + 20, 5397 }; 5398 5399 static const struct panel_desc waveshare_50_lcd_d_panel = { 5400 .modes = &waveshare_50_lcd_d_mode, 5401 .num_modes = 1, 5402 .bpc = 8, 5403 .size = { 5404 .width = 62, 5405 .height = 110, 5406 }, 5407 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5408 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5409 }; 5410 5411 static const struct drm_display_mode waveshare_625_lcd_mode = { 5412 .clock = 83333, 5413 .hdisplay = 720, 5414 .hsync_start = 720 + 50, 5415 .hsync_end = 720 + 50 + 50, 5416 .htotal = 720 + 50 + 50 + 50, 5417 .vdisplay = 1560, 5418 .vsync_start = 1560 + 20, 5419 .vsync_end = 1560 + 20 + 20, 5420 .vtotal = 1560 + 20 + 20 + 20, 5421 }; 5422 5423 static const struct panel_desc waveshare_625_lcd_panel = { 5424 .modes = &waveshare_625_lcd_mode, 5425 .num_modes = 1, 5426 .bpc = 8, 5427 .size = { 5428 .width = 66, 5429 .height = 144, 5430 }, 5431 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5432 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5433 }; 5434 5435 static const struct panel_desc waveshare_70_lcd_c_panel = { 5436 .modes = &waveshare_50_lcd_c_mode, 5437 .num_modes = 1, 5438 .bpc = 8, 5439 .size = { 5440 .width = 155, 5441 .height = 87, 5442 }, 5443 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5444 .connector_type = DRM_MODE_CONNECTOR_DPI, 5445 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5446 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5447 }; 5448 5449 static const struct drm_display_mode waveshare_80_lcd_c_mode; 5450 static const struct panel_desc waveshare_70_lcd_e_panel = { 5451 .modes = &waveshare_80_lcd_c_mode, 5452 .num_modes = 1, 5453 .bpc = 8, 5454 .size = { 5455 .width = 152, 5456 .height = 95, 5457 }, 5458 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5459 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5460 }; 5461 5462 static const struct drm_display_mode waveshare_70_lcd_h_mode = { 5463 .clock = 83333, 5464 .hdisplay = 1280, 5465 .hsync_start = 1280 + 64, 5466 .hsync_end = 1280 + 64 + 64, 5467 .htotal = 1280 + 64 + 64 + 64, 5468 .vdisplay = 720, 5469 .vsync_start = 720 + 64, 5470 .vsync_end = 720 + 64 + 64, 5471 .vtotal = 720 + 64 + 64 + 64, 5472 }; 5473 5474 static const struct panel_desc waveshare_70_lcd_h_panel = { 5475 .modes = &waveshare_70_lcd_h_mode, 5476 .num_modes = 1, 5477 .bpc = 8, 5478 .size = { 5479 .width = 155, 5480 .height = 88, 5481 }, 5482 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5483 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5484 }; 5485 5486 static const struct drm_display_mode waveshare_79_lcd_mode = { 5487 .clock = 50000, 5488 .hdisplay = 400, 5489 .hsync_start = 400 + 40, 5490 .hsync_end = 400 + 40 + 30, 5491 .htotal = 400 + 40 + 30 + 40, 5492 .vdisplay = 1280, 5493 .vsync_start = 1280 + 20, 5494 .vsync_end = 1280 + 20 + 10, 5495 .vtotal = 1280 + 20 + 10 + 20, 5496 }; 5497 5498 static const struct panel_desc waveshare_79_lcd_panel = { 5499 .modes = &waveshare_79_lcd_mode, 5500 .num_modes = 1, 5501 .bpc = 8, 5502 .size = { 5503 .width = 60, 5504 .height = 191, 5505 }, 5506 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5507 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5508 }; 5509 5510 static const struct drm_display_mode waveshare_80_lcd_c_mode = { 5511 .clock = 83333, 5512 .hdisplay = 1280, 5513 .hsync_start = 1280 + 156, 5514 .hsync_end = 1280 + 156 + 20, 5515 .htotal = 1280 + 156 + 20 + 40, 5516 .vdisplay = 800, 5517 .vsync_start = 800 + 40, 5518 .vsync_end = 800 + 40 + 48, 5519 .vtotal = 800 + 40 + 48 + 40, 5520 }; 5521 5522 static const struct panel_desc waveshare_80_lcd_c_panel = { 5523 .modes = &waveshare_80_lcd_c_mode, 5524 .num_modes = 1, 5525 .bpc = 8, 5526 .size = { 5527 .width = 173, 5528 .height = 108, 5529 }, 5530 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5531 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5532 }; 5533 5534 static const struct drm_display_mode waveshare_88_lcd_mode = { 5535 .clock = 83333, 5536 .hdisplay = 480, 5537 .hsync_start = 480 + 50, 5538 .hsync_end = 480 + 50 + 50, 5539 .htotal = 480 + 50 + 50 + 50, 5540 .vdisplay = 1920, 5541 .vsync_start = 1920 + 20, 5542 .vsync_end = 1920 + 20 + 20, 5543 .vtotal = 1920 + 20 + 20 + 20, 5544 }; 5545 5546 static const struct panel_desc waveshare_88_lcd_panel = { 5547 .modes = &waveshare_88_lcd_mode, 5548 .num_modes = 1, 5549 .bpc = 8, 5550 .size = { 5551 .width = 56, 5552 .height = 220, 5553 }, 5554 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5555 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5556 }; 5557 5558 static const struct panel_desc waveshare_101_lcd_c_panel = { 5559 .modes = &waveshare_80_lcd_c_mode, 5560 .num_modes = 1, 5561 .bpc = 8, 5562 .size = { 5563 .width = 217, 5564 .height = 136, 5565 }, 5566 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5567 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5568 }; 5569 5570 static const struct drm_display_mode waveshare_119_lcd_mode = { 5571 .clock = 50000, 5572 .hdisplay = 320, 5573 .hsync_start = 320 + 60, 5574 .hsync_end = 320 + 60 + 60, 5575 .htotal = 320 + 60 + 60 + 60, 5576 .vdisplay = 1480, 5577 .vsync_start = 1480 + 60, 5578 .vsync_end = 1480 + 60 + 60, 5579 .vtotal = 1480 + 60 + 60 + 60, 5580 }; 5581 5582 static const struct panel_desc waveshare_119_lcd_panel = { 5583 .modes = &waveshare_119_lcd_mode, 5584 .num_modes = 1, 5585 .bpc = 8, 5586 .size = { 5587 .width = 58, 5588 .height = 268, 5589 }, 5590 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5591 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5592 }; 5593 5594 static const struct drm_display_mode waveshare_133inch_mode = { 5595 .clock = 148500, 5596 .hdisplay = 1920, 5597 .hsync_start = 1920 + 88, 5598 .hsync_end = 1920 + 88 + 44, 5599 .htotal = 1920 + 88 + 44 + 148, 5600 .vdisplay = 1080, 5601 .vsync_start = 1080 + 4, 5602 .vsync_end = 1080 + 4 + 5, 5603 .vtotal = 1080 + 4 + 5 + 36, 5604 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 5605 }; 5606 5607 static const struct panel_desc waveshare_133inch = { 5608 .modes = &waveshare_133inch_mode, 5609 .num_modes = 1, 5610 .bpc = 8, 5611 .size = { 5612 .width = 293, 5613 .height = 163, 5614 }, 5615 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5616 .connector_type = DRM_MODE_CONNECTOR_DPI, 5617 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 5618 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE, 5619 }; 5620 5621 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 5622 .clock = 6410, 5623 .hdisplay = 320, 5624 .hsync_start = 320 + 20, 5625 .hsync_end = 320 + 20 + 30, 5626 .htotal = 320 + 20 + 30 + 38, 5627 .vdisplay = 240, 5628 .vsync_start = 240 + 4, 5629 .vsync_end = 240 + 4 + 3, 5630 .vtotal = 240 + 4 + 3 + 15, 5631 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5632 }; 5633 5634 static const struct panel_desc winstar_wf35ltiacd = { 5635 .modes = &winstar_wf35ltiacd_mode, 5636 .num_modes = 1, 5637 .bpc = 8, 5638 .size = { 5639 .width = 70, 5640 .height = 53, 5641 }, 5642 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5643 }; 5644 5645 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 5646 .clock = 51200, 5647 .hdisplay = 1024, 5648 .hsync_start = 1024 + 100, 5649 .hsync_end = 1024 + 100 + 100, 5650 .htotal = 1024 + 100 + 100 + 120, 5651 .vdisplay = 600, 5652 .vsync_start = 600 + 10, 5653 .vsync_end = 600 + 10 + 10, 5654 .vtotal = 600 + 10 + 10 + 15, 5655 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 5656 }; 5657 5658 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 5659 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 5660 .num_modes = 1, 5661 .bpc = 8, 5662 .size = { 5663 .width = 154, 5664 .height = 90, 5665 }, 5666 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5667 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 5668 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5669 }; 5670 5671 static const struct drm_display_mode mchp_ac69t88a_mode = { 5672 .clock = 25000, 5673 .hdisplay = 800, 5674 .hsync_start = 800 + 88, 5675 .hsync_end = 800 + 88 + 5, 5676 .htotal = 800 + 88 + 5 + 40, 5677 .vdisplay = 480, 5678 .vsync_start = 480 + 23, 5679 .vsync_end = 480 + 23 + 5, 5680 .vtotal = 480 + 23 + 5 + 1, 5681 }; 5682 5683 static const struct panel_desc mchp_ac69t88a = { 5684 .modes = &mchp_ac69t88a_mode, 5685 .num_modes = 1, 5686 .bpc = 8, 5687 .size = { 5688 .width = 108, 5689 .height = 65, 5690 }, 5691 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 5692 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 5693 .connector_type = DRM_MODE_CONNECTOR_LVDS, 5694 }; 5695 5696 static const struct drm_display_mode arm_rtsm_mode[] = { 5697 { 5698 .clock = 65000, 5699 .hdisplay = 1024, 5700 .hsync_start = 1024 + 24, 5701 .hsync_end = 1024 + 24 + 136, 5702 .htotal = 1024 + 24 + 136 + 160, 5703 .vdisplay = 768, 5704 .vsync_start = 768 + 3, 5705 .vsync_end = 768 + 3 + 6, 5706 .vtotal = 768 + 3 + 6 + 29, 5707 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5708 }, 5709 }; 5710 5711 static const struct panel_desc arm_rtsm = { 5712 .modes = arm_rtsm_mode, 5713 .num_modes = 1, 5714 .bpc = 8, 5715 .size = { 5716 .width = 400, 5717 .height = 300, 5718 }, 5719 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 5720 }; 5721 5722 static const struct of_device_id platform_of_match[] = { 5723 { 5724 .compatible = "ampire,am-1280800n3tzqw-t00h", 5725 .data = &ire_am_1280800n3tzqw_t00h, 5726 }, { 5727 .compatible = "ampire,am-1280800w8tzqw-t00h", 5728 .data = &ire_am_1280800w8tzqw_t00h, 5729 }, { 5730 .compatible = "ampire,am-480272h3tmqw-t01h", 5731 .data = &ire_am_480272h3tmqw_t01h, 5732 }, { 5733 .compatible = "ampire,am-800480l1tmqw-t00h", 5734 .data = &ire_am_800480l1tmqw_t00h, 5735 }, { 5736 .compatible = "ampire,am-800480n3tzqw-00h", 5737 .data = &ire_am_800480n3tzqw_00h, 5738 }, { 5739 .compatible = "ampire,am800480r3tmqwa1h", 5740 .data = &ire_am800480r3tmqwa1h, 5741 }, { 5742 .compatible = "ampire,am800600p5tmqw-tb8h", 5743 .data = &ire_am800600p5tmqwtb8h, 5744 }, { 5745 .compatible = "arm,rtsm-display", 5746 .data = &arm_rtsm, 5747 }, { 5748 .compatible = "armadeus,st0700-adapt", 5749 .data = &armadeus_st0700_adapt, 5750 }, { 5751 .compatible = "auo,b101aw03", 5752 .data = &auo_b101aw03, 5753 }, { 5754 .compatible = "auo,b101xtn01", 5755 .data = &auo_b101xtn01, 5756 }, { 5757 .compatible = "auo,b116xw03", 5758 .data = &auo_b116xw03, 5759 }, { 5760 .compatible = "auo,g070vvn01", 5761 .data = &auo_g070vvn01, 5762 }, { 5763 .compatible = "auo,g101evn010", 5764 .data = &auo_g101evn010, 5765 }, { 5766 .compatible = "auo,g104sn02", 5767 .data = &auo_g104sn02, 5768 }, { 5769 .compatible = "auo,g104stn01", 5770 .data = &auo_g104stn01, 5771 }, { 5772 .compatible = "auo,g121ean01", 5773 .data = &auo_g121ean01, 5774 }, { 5775 .compatible = "auo,g133han01", 5776 .data = &auo_g133han01, 5777 }, { 5778 .compatible = "auo,g156han04", 5779 .data = &auo_g156han04, 5780 }, { 5781 .compatible = "auo,g156xtn01", 5782 .data = &auo_g156xtn01, 5783 }, { 5784 .compatible = "auo,g185han01", 5785 .data = &auo_g185han01, 5786 }, { 5787 .compatible = "auo,g190ean01", 5788 .data = &auo_g190ean01, 5789 }, { 5790 .compatible = "auo,p238han01", 5791 .data = &auo_p238han01, 5792 }, { 5793 .compatible = "auo,p320hvn03", 5794 .data = &auo_p320hvn03, 5795 }, { 5796 .compatible = "auo,t215hvn01", 5797 .data = &auo_t215hvn01, 5798 }, { 5799 .compatible = "avic,tm070ddh03", 5800 .data = &avic_tm070ddh03, 5801 }, { 5802 .compatible = "bananapi,s070wv20-ct16", 5803 .data = &bananapi_s070wv20_ct16, 5804 }, { 5805 .compatible = "boe,av101hdt-a10", 5806 .data = &boe_av101hdt_a10, 5807 }, { 5808 .compatible = "boe,av123z7m-n17", 5809 .data = &boe_av123z7m_n17, 5810 }, { 5811 .compatible = "boe,bp082wx1-100", 5812 .data = &boe_bp082wx1_100, 5813 }, { 5814 .compatible = "boe,bp101wx1-100", 5815 .data = &boe_bp101wx1_100, 5816 }, { 5817 .compatible = "boe,dv215fhm-r01", 5818 .data = &boe_dv215fhm_r01, 5819 }, { 5820 .compatible = "boe,ev121wxm-n10-1850", 5821 .data = &boe_ev121wxm_n10_1850, 5822 }, { 5823 .compatible = "boe,hv070wsa-100", 5824 .data = &boe_hv070wsa 5825 }, { 5826 .compatible = "cct,cmt430b19n00", 5827 .data = &cct_cmt430b19n00, 5828 }, { 5829 .compatible = "cdtech,s043wq26h-ct7", 5830 .data = &cdtech_s043wq26h_ct7, 5831 }, { 5832 .compatible = "cdtech,s070pws19hp-fc21", 5833 .data = &cdtech_s070pws19hp_fc21, 5834 }, { 5835 .compatible = "cdtech,s070swv29hg-dc44", 5836 .data = &cdtech_s070swv29hg_dc44, 5837 }, { 5838 .compatible = "cdtech,s070wv95-ct16", 5839 .data = &cdtech_s070wv95_ct16, 5840 }, { 5841 .compatible = "chefree,ch101olhlwh-002", 5842 .data = &chefree_ch101olhlwh_002, 5843 }, { 5844 .compatible = "chunghwa,claa070wp03xg", 5845 .data = &chunghwa_claa070wp03xg, 5846 }, { 5847 .compatible = "chunghwa,claa101wa01a", 5848 .data = &chunghwa_claa101wa01a 5849 }, { 5850 .compatible = "chunghwa,claa101wb01", 5851 .data = &chunghwa_claa101wb01 5852 }, { 5853 .compatible = "dataimage,fg040346dsswbg04", 5854 .data = &dataimage_fg040346dsswbg04, 5855 }, { 5856 .compatible = "dataimage,fg1001l0dsswmg01", 5857 .data = &dataimage_fg1001l0dsswmg01, 5858 }, { 5859 .compatible = "dataimage,scf0700c48ggu18", 5860 .data = &dataimage_scf0700c48ggu18, 5861 }, { 5862 .compatible = "displaytech,dt050btft-pts", 5863 .data = &displaytech_dt050btft_pts, 5864 }, { 5865 .compatible = "dlc,dlc0700yzg-1", 5866 .data = &dlc_dlc0700yzg_1, 5867 }, { 5868 .compatible = "dlc,dlc1010gig", 5869 .data = &dlc_dlc1010gig, 5870 }, { 5871 .compatible = "edt,et035012dm6", 5872 .data = &edt_et035012dm6, 5873 }, { 5874 .compatible = "edt,etm0350g0dh6", 5875 .data = &edt_etm0350g0dh6, 5876 }, { 5877 .compatible = "edt,etm043080dh6gp", 5878 .data = &edt_etm043080dh6gp, 5879 }, { 5880 .compatible = "edt,etm0430g0dh6", 5881 .data = &edt_etm0430g0dh6, 5882 }, { 5883 .compatible = "edt,et057023udba", 5884 .data = &edt_et057023udba, 5885 }, { 5886 .compatible = "edt,et057090dhu", 5887 .data = &edt_et057090dhu, 5888 }, { 5889 .compatible = "edt,et070080dh6", 5890 .data = &edt_etm0700g0dh6, 5891 }, { 5892 .compatible = "edt,etm0700g0dh6", 5893 .data = &edt_etm0700g0dh6, 5894 }, { 5895 .compatible = "edt,etm0700g0bdh6", 5896 .data = &edt_etm0700g0bdh6, 5897 }, { 5898 .compatible = "edt,etm0700g0edh6", 5899 .data = &edt_etm0700g0bdh6, 5900 }, { 5901 .compatible = "edt,etml0700y5dha", 5902 .data = &edt_etml0700y5dha, 5903 }, { 5904 .compatible = "edt,etml1010g3dra", 5905 .data = &edt_etml1010g3dra, 5906 }, { 5907 .compatible = "edt,etmv570g2dhu", 5908 .data = &edt_etmv570g2dhu, 5909 }, { 5910 .compatible = "eink,vb3300-kca", 5911 .data = &eink_vb3300_kca, 5912 }, { 5913 .compatible = "evervision,vgg644804", 5914 .data = &evervision_vgg644804, 5915 }, { 5916 .compatible = "evervision,vgg804821", 5917 .data = &evervision_vgg804821, 5918 }, { 5919 .compatible = "foxlink,fl500wvr00-a0t", 5920 .data = &foxlink_fl500wvr00_a0t, 5921 }, { 5922 .compatible = "frida,frd350h54004", 5923 .data = &frida_frd350h54004, 5924 }, { 5925 .compatible = "giantplus,gpg482739qs5", 5926 .data = &giantplus_gpg482739qs5 5927 }, { 5928 .compatible = "giantplus,gpm940b0", 5929 .data = &giantplus_gpm940b0, 5930 }, { 5931 .compatible = "hannstar,hsd070pww1", 5932 .data = &hannstar_hsd070pww1, 5933 }, { 5934 .compatible = "hannstar,hsd100pxn1", 5935 .data = &hannstar_hsd100pxn1, 5936 }, { 5937 .compatible = "hannstar,hsd101pww2", 5938 .data = &hannstar_hsd101pww2, 5939 }, { 5940 .compatible = "hannstar,hsd156juw2", 5941 .data = &hannstar_hsd156juw2, 5942 }, { 5943 .compatible = "hit,tx23d38vm0caa", 5944 .data = &hitachi_tx23d38vm0caa 5945 }, { 5946 .compatible = "innolux,at043tn24", 5947 .data = &innolux_at043tn24, 5948 }, { 5949 .compatible = "innolux,at070tn92", 5950 .data = &innolux_at070tn92, 5951 }, { 5952 .compatible = "innolux,g070ace-l01", 5953 .data = &innolux_g070ace_l01, 5954 }, { 5955 .compatible = "innolux,g070ace-lh3", 5956 .data = &innolux_g070ace_lh3, 5957 }, { 5958 .compatible = "innolux,g070y2-l01", 5959 .data = &innolux_g070y2_l01, 5960 }, { 5961 .compatible = "innolux,g070y2-t02", 5962 .data = &innolux_g070y2_t02, 5963 }, { 5964 .compatible = "innolux,g101ice-l01", 5965 .data = &innolux_g101ice_l01 5966 }, { 5967 .compatible = "innolux,g121i1-l01", 5968 .data = &innolux_g121i1_l01 5969 }, { 5970 .compatible = "innolux,g121x1-l03", 5971 .data = &innolux_g121x1_l03, 5972 }, { 5973 .compatible = "innolux,g121xce-l01", 5974 .data = &innolux_g121xce_l01, 5975 }, { 5976 .compatible = "innolux,g150xge-l05", 5977 .data = &innolux_g150xge_l05, 5978 }, { 5979 .compatible = "innolux,g156hce-l01", 5980 .data = &innolux_g156hce_l01, 5981 }, { 5982 .compatible = "innolux,n156bge-l21", 5983 .data = &innolux_n156bge_l21, 5984 }, { 5985 .compatible = "innolux,zj070na-01p", 5986 .data = &innolux_zj070na_01p, 5987 }, { 5988 .compatible = "jutouch,jt070tm041", 5989 .data = &jutouch_jt070tm041, 5990 }, { 5991 .compatible = "jutouch,jt101tm023", 5992 .data = &jutouch_jt101tm023, 5993 }, { 5994 .compatible = "koe,tx14d24vm1bpa", 5995 .data = &koe_tx14d24vm1bpa, 5996 }, { 5997 .compatible = "koe,tx26d202vm0bwa", 5998 .data = &koe_tx26d202vm0bwa, 5999 }, { 6000 .compatible = "koe,tx31d200vm0baa", 6001 .data = &koe_tx31d200vm0baa, 6002 }, { 6003 .compatible = "kyo,tcg070wvlq", 6004 .data = &lg_lb070wv8, 6005 }, { 6006 .compatible = "kyo,tcg121xglp", 6007 .data = &kyo_tcg121xglp, 6008 }, { 6009 .compatible = "lemaker,bl035-rgb-002", 6010 .data = &lemaker_bl035_rgb_002, 6011 }, { 6012 .compatible = "lg,lb070wv8", 6013 .data = &lg_lb070wv8, 6014 }, { 6015 .compatible = "lincolntech,lcd185-101ct", 6016 .data = &lincolntech_lcd185_101ct, 6017 }, { 6018 .compatible = "logicpd,type28", 6019 .data = &logicpd_type_28, 6020 }, { 6021 .compatible = "logictechno,lt161010-2nhc", 6022 .data = &logictechno_lt161010_2nh, 6023 }, { 6024 .compatible = "logictechno,lt161010-2nhr", 6025 .data = &logictechno_lt161010_2nh, 6026 }, { 6027 .compatible = "logictechno,lt170410-2whc", 6028 .data = &logictechno_lt170410_2whc, 6029 }, { 6030 .compatible = "logictechno,lttd800480070-l2rt", 6031 .data = &logictechno_lttd800480070_l2rt, 6032 }, { 6033 .compatible = "logictechno,lttd800480070-l6wh-rt", 6034 .data = &logictechno_lttd800480070_l6wh_rt, 6035 }, { 6036 .compatible = "microtips,mf-101hiebcaf0", 6037 .data = µtips_mf_101hiebcaf0_c, 6038 }, { 6039 .compatible = "microtips,mf-103hieb0ga0", 6040 .data = µtips_mf_103hieb0ga0, 6041 }, { 6042 .compatible = "mitsubishi,aa070mc01-ca1", 6043 .data = &mitsubishi_aa070mc01, 6044 }, { 6045 .compatible = "mitsubishi,aa084xe01", 6046 .data = &mitsubishi_aa084xe01, 6047 }, { 6048 .compatible = "multi-inno,mi0700a2t-30", 6049 .data = &multi_inno_mi0700a2t_30, 6050 }, { 6051 .compatible = "multi-inno,mi0700s4t-6", 6052 .data = &multi_inno_mi0700s4t_6, 6053 }, { 6054 .compatible = "multi-inno,mi0800ft-9", 6055 .data = &multi_inno_mi0800ft_9, 6056 }, { 6057 .compatible = "multi-inno,mi1010ait-1cp", 6058 .data = &multi_inno_mi1010ait_1cp, 6059 }, { 6060 .compatible = "multi-inno,mi1010z1t-1cp11", 6061 .data = &multi_inno_mi1010z1t_1cp11, 6062 }, { 6063 .compatible = "nec,nl12880bc20-05", 6064 .data = &nec_nl12880bc20_05, 6065 }, { 6066 .compatible = "nec,nl4827hc19-05b", 6067 .data = &nec_nl4827hc19_05b, 6068 }, { 6069 .compatible = "nec,nl6448bc33-70c", 6070 .data = &nec_nl6448bc33_70c, 6071 }, { 6072 .compatible = "netron-dy,e231732", 6073 .data = &netron_dy_e231732, 6074 }, { 6075 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 6076 .data = &newhaven_nhd_43_480272ef_atxl, 6077 }, { 6078 .compatible = "nlt,nl13676bc25-03f", 6079 .data = &nlt_nl13676bc25_03f, 6080 }, { 6081 .compatible = "nlt,nl192108ac18-02d", 6082 .data = &nlt_nl192108ac18_02d, 6083 }, { 6084 .compatible = "nvd,9128", 6085 .data = &nvd_9128, 6086 }, { 6087 .compatible = "okaya,rs800480t-7x0gp", 6088 .data = &okaya_rs800480t_7x0gp, 6089 }, { 6090 .compatible = "olimex,lcd-olinuxino-43-ts", 6091 .data = &olimex_lcd_olinuxino_43ts, 6092 }, { 6093 .compatible = "olimex,lcd-olinuxino-5-cts", 6094 .data = &olimex_lcd_olinuxino_5cts, 6095 }, { 6096 .compatible = "ontat,kd50g21-40nt-a1", 6097 .data = &ontat_kd50g21_40nt_a1, 6098 }, { 6099 .compatible = "ontat,yx700wv03", 6100 .data = &ontat_yx700wv03, 6101 }, { 6102 .compatible = "ortustech,com37h3m05dtc", 6103 .data = &ortustech_com37h3m, 6104 }, { 6105 .compatible = "ortustech,com37h3m99dtc", 6106 .data = &ortustech_com37h3m, 6107 }, { 6108 .compatible = "ortustech,com43h4m85ulc", 6109 .data = &ortustech_com43h4m85ulc, 6110 }, { 6111 .compatible = "osddisplays,osd070t1718-19ts", 6112 .data = &osddisplays_osd070t1718_19ts, 6113 }, { 6114 .compatible = "pda,91-00156-a0", 6115 .data = &pda_91_00156_a0, 6116 }, { 6117 .compatible = "powertip,ph128800t004-zza01", 6118 .data = &powertip_ph128800t004_zza01, 6119 }, { 6120 .compatible = "powertip,ph128800t006-zhc01", 6121 .data = &powertip_ph128800t006_zhc01, 6122 }, { 6123 .compatible = "powertip,ph800480t013-idf02", 6124 .data = &powertip_ph800480t013_idf02, 6125 }, { 6126 .compatible = "powertip,ph800480t032-zhc19", 6127 .data = &powertip_ph800480t032_zhc19, 6128 }, { 6129 .compatible = "primeview,pm070wl4", 6130 .data = &primeview_pm070wl4, 6131 }, { 6132 .compatible = "qiaodian,qd43003c0-40", 6133 .data = &qd43003c0_40, 6134 }, { 6135 .compatible = "qishenglong,gopher2b-lcd", 6136 .data = &qishenglong_gopher2b_lcd, 6137 }, { 6138 .compatible = "raystar,rff500f-awh-dnn", 6139 .data = &raystar_rff500f_awh_dnn, 6140 }, { 6141 .compatible = "rocktech,rk043fn48h", 6142 .data = &rocktech_rk043fn48h, 6143 }, { 6144 .compatible = "rocktech,rk070er9427", 6145 .data = &rocktech_rk070er9427, 6146 }, { 6147 .compatible = "rocktech,rk101ii01d-ct", 6148 .data = &rocktech_rk101ii01d_ct, 6149 }, { 6150 .compatible = "samsung,ltl101al01", 6151 .data = &samsung_ltl101al01, 6152 }, { 6153 .compatible = "samsung,ltl106al01", 6154 .data = &samsung_ltl106al01, 6155 }, { 6156 .compatible = "samsung,ltn101nt05", 6157 .data = &samsung_ltn101nt05, 6158 }, { 6159 .compatible = "satoz,sat050at40h12r2", 6160 .data = &satoz_sat050at40h12r2, 6161 }, { 6162 .compatible = "sharp,lq035q7db03", 6163 .data = &sharp_lq035q7db03, 6164 }, { 6165 .compatible = "sharp,lq070y3dg3b", 6166 .data = &sharp_lq070y3dg3b, 6167 }, { 6168 .compatible = "sharp,lq101k1ly04", 6169 .data = &sharp_lq101k1ly04, 6170 }, { 6171 .compatible = "sharp,ls020b1dd01d", 6172 .data = &sharp_ls020b1dd01d, 6173 }, { 6174 .compatible = "shelly,sca07010-bfn-lnn", 6175 .data = &shelly_sca07010_bfn_lnn, 6176 }, { 6177 .compatible = "starry,kr070pe2t", 6178 .data = &starry_kr070pe2t, 6179 }, { 6180 .compatible = "startek,kd070hdfld092", 6181 .data = &startek_kd070hdfld092, 6182 }, { 6183 .compatible = "startek,kd070wvfpa", 6184 .data = &startek_kd070wvfpa, 6185 }, { 6186 .compatible = "team-source-display,tst043015cmhx", 6187 .data = &tsd_tst043015cmhx, 6188 }, { 6189 .compatible = "tfc,s9700rtwv43tr-01b", 6190 .data = &tfc_s9700rtwv43tr_01b, 6191 }, { 6192 .compatible = "tianma,p0700wxf1mbaa", 6193 .data = &tianma_p0700wxf1mbaa, 6194 }, { 6195 .compatible = "tianma,tm050rdh03", 6196 .data = &ontat_kd50g21_40nt_a1, 6197 }, { 6198 .compatible = "tianma,tm070jdhg30", 6199 .data = &tianma_tm070jdhg30, 6200 }, { 6201 .compatible = "tianma,tm070jdhg34-00", 6202 .data = &tianma_tm070jdhg34_00, 6203 }, { 6204 .compatible = "tianma,tm070jvhg33", 6205 .data = &tianma_tm070jvhg33, 6206 }, { 6207 .compatible = "tianma,tm070rvhg71", 6208 .data = &tianma_tm070rvhg71, 6209 }, { 6210 .compatible = "ti,nspire-cx-lcd-panel", 6211 .data = &ti_nspire_cx_lcd_panel, 6212 }, { 6213 .compatible = "ti,nspire-classic-lcd-panel", 6214 .data = &ti_nspire_classic_lcd_panel, 6215 }, { 6216 .compatible = "toshiba,lt089ac29000", 6217 .data = &toshiba_lt089ac29000, 6218 }, { 6219 .compatible = "topland,tian-g07017-01", 6220 .data = &topland_tian_g07017_01, 6221 }, { 6222 .compatible = "tpk,f07a-0102", 6223 .data = &tpk_f07a_0102, 6224 }, { 6225 .compatible = "tpk,f10a-0102", 6226 .data = &tpk_f10a_0102, 6227 }, { 6228 .compatible = "truly,tft320240-229-e", 6229 .data = &truly_tft320240_229_e, 6230 }, { 6231 .compatible = "urt,umsh-8596md-t", 6232 .data = &urt_umsh_8596md_parallel, 6233 }, { 6234 .compatible = "urt,umsh-8596md-1t", 6235 .data = &urt_umsh_8596md_parallel, 6236 }, { 6237 .compatible = "urt,umsh-8596md-7t", 6238 .data = &urt_umsh_8596md_parallel, 6239 }, { 6240 .compatible = "urt,umsh-8596md-11t", 6241 .data = &urt_umsh_8596md_lvds, 6242 }, { 6243 .compatible = "urt,umsh-8596md-19t", 6244 .data = &urt_umsh_8596md_lvds, 6245 }, { 6246 .compatible = "urt,umsh-8596md-20t", 6247 .data = &urt_umsh_8596md_parallel, 6248 }, { 6249 .compatible = "vivax,tpc9150-panel", 6250 .data = &vivax_tpc9150_panel, 6251 }, { 6252 .compatible = "vxt,vl050-8048nt-c01", 6253 .data = &vl050_8048nt_c01, 6254 }, { 6255 .compatible = "waveshare,2.8inch-panel", 6256 .data = &waveshare_28_lcd_panel 6257 }, { 6258 .compatible = "waveshare,3.4inch-c-panel", 6259 .data = &waveshare_34_lcd_c_panel 6260 }, { 6261 .compatible = "waveshare,4.0inch-panel", 6262 .data = &waveshare_40_lcd_panel 6263 }, { 6264 .compatible = "waveshare,4.0inch-c-panel", 6265 .data = &waveshare_40_lcd_c_panel 6266 }, { 6267 .compatible = "waveshare,5.0inch-c-panel", 6268 .data = &waveshare_50_lcd_c_panel 6269 }, { 6270 .compatible = "waveshare,5.0inch-d-panel", 6271 .data = &waveshare_50_lcd_d_panel 6272 }, { 6273 .compatible = "waveshare,6.25inch-panel", 6274 .data = &waveshare_625_lcd_panel 6275 }, { 6276 .compatible = "waveshare,7.0inch-c-panel", 6277 .data = &waveshare_70_lcd_c_panel 6278 }, { 6279 .compatible = "waveshare,7.0inch-e-panel", 6280 .data = &waveshare_70_lcd_e_panel 6281 }, { 6282 .compatible = "waveshare,7.0inch-h-panel", 6283 .data = &waveshare_70_lcd_h_panel 6284 }, { 6285 .compatible = "waveshare,7.9inch-panel", 6286 .data = &waveshare_79_lcd_panel 6287 }, { 6288 .compatible = "waveshare,8.0inch-c-panel", 6289 .data = &waveshare_80_lcd_c_panel 6290 }, { 6291 .compatible = "waveshare,8.8inch-panel", 6292 .data = &waveshare_88_lcd_panel 6293 }, { 6294 .compatible = "waveshare,10.1inch-c-panel", 6295 .data = &waveshare_101_lcd_c_panel 6296 }, { 6297 .compatible = "waveshare,11.9inch-panel", 6298 .data = &waveshare_119_lcd_panel 6299 }, { 6300 .compatible = "waveshare,13.3inch-panel", 6301 .data = &waveshare_133inch, 6302 }, { 6303 .compatible = "winstar,wf35ltiacd", 6304 .data = &winstar_wf35ltiacd, 6305 }, { 6306 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 6307 .data = &yes_optoelectronics_ytc700tlag_05_201c, 6308 }, { 6309 .compatible = "microchip,ac69t88a", 6310 .data = &mchp_ac69t88a, 6311 }, { 6312 /* Must be the last entry */ 6313 .compatible = "panel-dpi", 6314 6315 /* 6316 * Explicitly NULL, the panel_desc structure will be 6317 * allocated by panel_dpi_probe(). 6318 */ 6319 .data = NULL, 6320 }, { 6321 /* sentinel */ 6322 } 6323 }; 6324 MODULE_DEVICE_TABLE(of, platform_of_match); 6325 6326 static int panel_simple_platform_probe(struct platform_device *pdev) 6327 { 6328 struct panel_simple *panel; 6329 6330 panel = panel_simple_probe(&pdev->dev); 6331 if (IS_ERR(panel)) 6332 return PTR_ERR(panel); 6333 6334 return 0; 6335 } 6336 6337 static void panel_simple_platform_remove(struct platform_device *pdev) 6338 { 6339 panel_simple_remove(&pdev->dev); 6340 } 6341 6342 static void panel_simple_platform_shutdown(struct platform_device *pdev) 6343 { 6344 panel_simple_shutdown(&pdev->dev); 6345 } 6346 6347 static const struct dev_pm_ops panel_simple_pm_ops = { 6348 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 6349 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 6350 pm_runtime_force_resume) 6351 }; 6352 6353 static struct platform_driver panel_simple_platform_driver = { 6354 .driver = { 6355 .name = "panel-simple", 6356 .of_match_table = platform_of_match, 6357 .pm = &panel_simple_pm_ops, 6358 }, 6359 .probe = panel_simple_platform_probe, 6360 .remove = panel_simple_platform_remove, 6361 .shutdown = panel_simple_platform_shutdown, 6362 }; 6363 6364 static const struct drm_display_mode auo_b080uan01_mode = { 6365 .clock = 154500, 6366 .hdisplay = 1200, 6367 .hsync_start = 1200 + 62, 6368 .hsync_end = 1200 + 62 + 4, 6369 .htotal = 1200 + 62 + 4 + 62, 6370 .vdisplay = 1920, 6371 .vsync_start = 1920 + 9, 6372 .vsync_end = 1920 + 9 + 2, 6373 .vtotal = 1920 + 9 + 2 + 8, 6374 }; 6375 6376 static const struct panel_desc_dsi auo_b080uan01 = { 6377 .desc = { 6378 .modes = &auo_b080uan01_mode, 6379 .num_modes = 1, 6380 .bpc = 8, 6381 .size = { 6382 .width = 108, 6383 .height = 272, 6384 }, 6385 .connector_type = DRM_MODE_CONNECTOR_DSI, 6386 }, 6387 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 6388 .format = MIPI_DSI_FMT_RGB888, 6389 .lanes = 4, 6390 }; 6391 6392 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 6393 .clock = 160000, 6394 .hdisplay = 1200, 6395 .hsync_start = 1200 + 120, 6396 .hsync_end = 1200 + 120 + 20, 6397 .htotal = 1200 + 120 + 20 + 21, 6398 .vdisplay = 1920, 6399 .vsync_start = 1920 + 21, 6400 .vsync_end = 1920 + 21 + 3, 6401 .vtotal = 1920 + 21 + 3 + 18, 6402 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 6403 }; 6404 6405 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 6406 .desc = { 6407 .modes = &boe_tv080wum_nl0_mode, 6408 .num_modes = 1, 6409 .size = { 6410 .width = 107, 6411 .height = 172, 6412 }, 6413 .connector_type = DRM_MODE_CONNECTOR_DSI, 6414 }, 6415 .flags = MIPI_DSI_MODE_VIDEO | 6416 MIPI_DSI_MODE_VIDEO_BURST | 6417 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 6418 .format = MIPI_DSI_FMT_RGB888, 6419 .lanes = 4, 6420 }; 6421 6422 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 6423 .clock = 67000, 6424 .hdisplay = 720, 6425 .hsync_start = 720 + 12, 6426 .hsync_end = 720 + 12 + 4, 6427 .htotal = 720 + 12 + 4 + 112, 6428 .vdisplay = 1280, 6429 .vsync_start = 1280 + 8, 6430 .vsync_end = 1280 + 8 + 4, 6431 .vtotal = 1280 + 8 + 4 + 12, 6432 }; 6433 6434 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 6435 .desc = { 6436 .modes = &lg_lh500wx1_sd03_mode, 6437 .num_modes = 1, 6438 .bpc = 8, 6439 .size = { 6440 .width = 62, 6441 .height = 110, 6442 }, 6443 .connector_type = DRM_MODE_CONNECTOR_DSI, 6444 }, 6445 .flags = MIPI_DSI_MODE_VIDEO, 6446 .format = MIPI_DSI_FMT_RGB888, 6447 .lanes = 4, 6448 }; 6449 6450 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 6451 .clock = 157200, 6452 .hdisplay = 1920, 6453 .hsync_start = 1920 + 154, 6454 .hsync_end = 1920 + 154 + 16, 6455 .htotal = 1920 + 154 + 16 + 32, 6456 .vdisplay = 1200, 6457 .vsync_start = 1200 + 17, 6458 .vsync_end = 1200 + 17 + 2, 6459 .vtotal = 1200 + 17 + 2 + 16, 6460 }; 6461 6462 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 6463 .desc = { 6464 .modes = &panasonic_vvx10f004b00_mode, 6465 .num_modes = 1, 6466 .bpc = 8, 6467 .size = { 6468 .width = 217, 6469 .height = 136, 6470 }, 6471 .connector_type = DRM_MODE_CONNECTOR_DSI, 6472 }, 6473 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 6474 MIPI_DSI_CLOCK_NON_CONTINUOUS, 6475 .format = MIPI_DSI_FMT_RGB888, 6476 .lanes = 4, 6477 }; 6478 6479 static const struct drm_display_mode lg_acx467akm_7_mode = { 6480 .clock = 150000, 6481 .hdisplay = 1080, 6482 .hsync_start = 1080 + 2, 6483 .hsync_end = 1080 + 2 + 2, 6484 .htotal = 1080 + 2 + 2 + 2, 6485 .vdisplay = 1920, 6486 .vsync_start = 1920 + 2, 6487 .vsync_end = 1920 + 2 + 2, 6488 .vtotal = 1920 + 2 + 2 + 2, 6489 }; 6490 6491 static const struct panel_desc_dsi lg_acx467akm_7 = { 6492 .desc = { 6493 .modes = &lg_acx467akm_7_mode, 6494 .num_modes = 1, 6495 .bpc = 8, 6496 .size = { 6497 .width = 62, 6498 .height = 110, 6499 }, 6500 .connector_type = DRM_MODE_CONNECTOR_DSI, 6501 }, 6502 .flags = 0, 6503 .format = MIPI_DSI_FMT_RGB888, 6504 .lanes = 4, 6505 }; 6506 6507 static const struct drm_display_mode osd101t2045_53ts_mode = { 6508 .clock = 154500, 6509 .hdisplay = 1920, 6510 .hsync_start = 1920 + 112, 6511 .hsync_end = 1920 + 112 + 16, 6512 .htotal = 1920 + 112 + 16 + 32, 6513 .vdisplay = 1200, 6514 .vsync_start = 1200 + 16, 6515 .vsync_end = 1200 + 16 + 2, 6516 .vtotal = 1200 + 16 + 2 + 16, 6517 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 6518 }; 6519 6520 static const struct panel_desc_dsi osd101t2045_53ts = { 6521 .desc = { 6522 .modes = &osd101t2045_53ts_mode, 6523 .num_modes = 1, 6524 .bpc = 8, 6525 .size = { 6526 .width = 217, 6527 .height = 136, 6528 }, 6529 .connector_type = DRM_MODE_CONNECTOR_DSI, 6530 }, 6531 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 6532 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 6533 MIPI_DSI_MODE_NO_EOT_PACKET, 6534 .format = MIPI_DSI_FMT_RGB888, 6535 .lanes = 4, 6536 }; 6537 6538 static const struct drm_display_mode tsd_tst070wsbe_196c_mode = { 6539 .clock = 52477, 6540 .hdisplay = 1024, 6541 .hsync_start = 1024 + 160, 6542 .hsync_end = 1024 + 160 + 12, 6543 .htotal = 1024 + 160 + 160 + 12, 6544 .vdisplay = 600, 6545 .vsync_start = 600 + 12, 6546 .vsync_end = 600 + 12 + 10, 6547 .vtotal = 600 + 12 + 10 + 23, 6548 }; 6549 6550 static const struct panel_desc_dsi tsd_tst070wsbe_196c = { 6551 .desc = { 6552 .modes = &tsd_tst070wsbe_196c_mode, 6553 .num_modes = 1, 6554 .bpc = 8, 6555 .size = { 6556 .width = 190, 6557 .height = 121, 6558 }, 6559 .delay = { 6560 .prepare = 20, 6561 }, 6562 .connector_type = DRM_MODE_CONNECTOR_DSI, 6563 }, 6564 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM | 6565 MIPI_DSI_MODE_VIDEO_BURST | 6566 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 6567 .format = MIPI_DSI_FMT_RGB888, 6568 .lanes = 4, 6569 }; 6570 6571 static const struct of_device_id dsi_of_match[] = { 6572 { 6573 .compatible = "auo,b080uan01", 6574 .data = &auo_b080uan01 6575 }, { 6576 .compatible = "boe,tv080wum-nl0", 6577 .data = &boe_tv080wum_nl0 6578 }, { 6579 .compatible = "lg,lh500wx1-sd03", 6580 .data = &lg_lh500wx1_sd03 6581 }, { 6582 .compatible = "panasonic,vvx10f004b00", 6583 .data = &panasonic_vvx10f004b00 6584 }, { 6585 .compatible = "lg,acx467akm-7", 6586 .data = &lg_acx467akm_7 6587 }, { 6588 .compatible = "osddisplays,osd101t2045-53ts", 6589 .data = &osd101t2045_53ts 6590 }, { 6591 .compatible = "team-source-display,tst070wsbe-196c", 6592 .data = &tsd_tst070wsbe_196c 6593 }, { 6594 /* sentinel */ 6595 } 6596 }; 6597 MODULE_DEVICE_TABLE(of, dsi_of_match); 6598 6599 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 6600 { 6601 const struct panel_desc_dsi *desc; 6602 struct panel_simple *panel; 6603 int err; 6604 6605 panel = panel_simple_probe(&dsi->dev); 6606 if (IS_ERR(panel)) 6607 return PTR_ERR(panel); 6608 6609 desc = container_of(panel->desc, struct panel_desc_dsi, desc); 6610 dsi->mode_flags = desc->flags; 6611 dsi->format = desc->format; 6612 dsi->lanes = desc->lanes; 6613 6614 err = mipi_dsi_attach(dsi); 6615 if (err) { 6616 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 6617 6618 drm_panel_remove(&panel->base); 6619 } 6620 6621 return err; 6622 } 6623 6624 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 6625 { 6626 int err; 6627 6628 err = mipi_dsi_detach(dsi); 6629 if (err < 0) 6630 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 6631 6632 panel_simple_remove(&dsi->dev); 6633 } 6634 6635 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 6636 { 6637 panel_simple_shutdown(&dsi->dev); 6638 } 6639 6640 static struct mipi_dsi_driver panel_simple_dsi_driver = { 6641 .driver = { 6642 .name = "panel-simple-dsi", 6643 .of_match_table = dsi_of_match, 6644 .pm = &panel_simple_pm_ops, 6645 }, 6646 .probe = panel_simple_dsi_probe, 6647 .remove = panel_simple_dsi_remove, 6648 .shutdown = panel_simple_dsi_shutdown, 6649 }; 6650 6651 static int __init panel_simple_init(void) 6652 { 6653 int err; 6654 6655 err = platform_driver_register(&panel_simple_platform_driver); 6656 if (err < 0) 6657 return err; 6658 6659 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 6660 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 6661 if (err < 0) 6662 goto err_did_platform_register; 6663 } 6664 6665 return 0; 6666 6667 err_did_platform_register: 6668 platform_driver_unregister(&panel_simple_platform_driver); 6669 6670 return err; 6671 } 6672 module_init(panel_simple_init); 6673 6674 static void __exit panel_simple_exit(void) 6675 { 6676 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 6677 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 6678 6679 platform_driver_unregister(&panel_simple_platform_driver); 6680 } 6681 module_exit(panel_simple_exit); 6682 6683 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 6684 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 6685 MODULE_LICENSE("GPL and additional rights"); 6686